1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Information about a relocation unspec. SYMBOL is the relocation symbol
127 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
128 is the constant addend. */
132 HOST_WIDE_INT offset;
135 /* Temporary register allocation support structure. */
136 typedef struct frv_tmp_reg_struct
138 HARD_REG_SET regs; /* possible registers to allocate */
139 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
143 /* Register state information for VLIW re-packing phase. */
144 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
145 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
146 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
147 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
149 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
151 typedef unsigned char regstate_t;
153 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
161 /* Information required by frv_frame_access. */
164 /* This field is FRV_LOAD if registers are to be loaded from the stack and
165 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
166 the move is being done by the prologue code while FRV_LOAD implies it
167 is being done by the epilogue. */
168 enum frv_stack_op op;
170 /* The base register to use when accessing the stack. This may be the
171 frame pointer, stack pointer, or a temporary. The choice of register
172 depends on which part of the frame is being accessed and how big the
176 /* The offset of BASE from the bottom of the current frame, in bytes. */
178 } frv_frame_accessor_t;
180 /* Define the information needed to generate branch and scc insns. This is
181 stored from the compare operation. */
185 /* Conditional execution support gathered together in one structure. */
188 /* Linked list of insns to add if the conditional execution conversion was
189 successful. Each link points to an EXPR_LIST which points to the pattern
190 of the insn to add, and the insn to be inserted before. */
191 rtx added_insns_list;
193 /* Identify which registers are safe to allocate for if conversions to
194 conditional execution. We keep the last allocated register in the
195 register classes between COND_EXEC statements. This will mean we allocate
196 different registers for each different COND_EXEC group if we can. This
197 might allow the scheduler to intermix two different COND_EXEC sections. */
198 frv_tmp_reg_t tmp_reg;
200 /* For nested IFs, identify which CC registers are used outside of setting
201 via a compare isnsn, and using via a check insn. This will allow us to
202 know if we can rewrite the register to use a different register that will
203 be paired with the CR register controlling the nested IF-THEN blocks. */
204 HARD_REG_SET nested_cc_ok_rewrite;
206 /* Temporary registers allocated to hold constants during conditional
208 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
210 /* Current number of temp registers available. */
211 int cur_scratch_regs;
213 /* Number of nested conditional execution blocks. */
214 int num_nested_cond_exec;
216 /* Map of insns that set up constants in scratch registers. */
217 bitmap scratch_insns_bitmap;
219 /* Conditional execution test register (CC0..CC7). */
222 /* Conditional execution compare register that is paired with cr_reg, so that
223 nested compares can be done. The csubcc and caddcc instructions don't
224 have enough bits to specify both a CC register to be set and a CR register
225 to do the test on, so the same bit number is used for both. Needless to
226 say, this is rather inconvenient for GCC. */
229 /* Extra CR registers used for &&, ||. */
233 /* Previous CR used in nested if, to make sure we are dealing with the same
234 nested if as the previous statement. */
235 rtx last_nested_if_cr;
239 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
241 /* Map register number to smallest register class. */
242 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
244 /* Map class letter into register class. */
245 enum reg_class reg_class_from_letter[256];
247 /* Cached value of frv_stack_info. */
248 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
251 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
253 /* Forward references */
255 static bool frv_handle_option (size_t, const char *, int);
256 static int frv_default_flags_for_cpu (void);
257 static int frv_string_begins_with (tree, const char *);
258 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
259 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
260 static void frv_print_operand_memory_reference_reg
262 static void frv_print_operand_memory_reference (FILE *, rtx, int);
263 static int frv_print_operand_jump_hint (rtx);
264 static const char *comparison_string (enum rtx_code, rtx);
265 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
266 static rtx single_set_pattern (rtx);
267 static int frv_function_contains_far_jump (void);
268 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
272 static rtx frv_frame_offset_rtx (int);
273 static rtx frv_frame_mem (enum machine_mode, rtx, int);
274 static rtx frv_dwarf_store (rtx, int);
275 static void frv_frame_insn (rtx, rtx);
276 static void frv_frame_access (frv_frame_accessor_t*,
278 static void frv_frame_access_multi (frv_frame_accessor_t*,
280 static void frv_frame_access_standard_regs (enum frv_stack_op,
282 static struct machine_function *frv_init_machine_status (void);
283 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
284 static rtx frv_int_to_acc (enum insn_code, int, rtx);
285 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
286 static rtx frv_read_argument (tree *);
287 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
288 static int frv_check_constant_argument (enum insn_code, int, rtx);
289 static rtx frv_legitimize_target (enum insn_code, rtx);
290 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
291 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
292 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
293 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
294 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
295 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
296 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
297 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
298 static rtx frv_expand_int_void2arg (enum insn_code, tree);
299 static rtx frv_expand_prefetches (enum insn_code, tree);
300 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
301 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
302 static rtx frv_expand_mclracc_builtin (tree);
303 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
304 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
305 static rtx frv_expand_noargs_builtin (enum insn_code);
306 static void frv_split_iacc_move (rtx, rtx);
307 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
308 static int frv_clear_registers_used (rtx *, void *);
309 static void frv_ifcvt_add_insn (rtx, rtx, int);
310 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
311 static rtx frv_ifcvt_load_value (rtx, rtx);
312 static int frv_acc_group_1 (rtx *, void *);
313 static unsigned int frv_insn_unit (rtx);
314 static bool frv_issues_to_branch_unit_p (rtx);
315 static int frv_cond_flags (rtx);
316 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
317 static int frv_registers_conflict_p_1 (rtx *, void *);
318 static bool frv_registers_conflict_p (rtx);
319 static void frv_registers_update_1 (rtx, rtx, void *);
320 static void frv_registers_update (rtx);
321 static void frv_start_packet (void);
322 static void frv_start_packet_block (void);
323 static void frv_finish_packet (void (*) (void));
324 static bool frv_pack_insn_p (rtx);
325 static void frv_add_insn_to_packet (rtx);
326 static void frv_insert_nop_in_packet (rtx);
327 static bool frv_for_each_packet (void (*) (void));
328 static bool frv_sort_insn_group_1 (enum frv_insn_group,
329 unsigned int, unsigned int,
330 unsigned int, unsigned int,
332 static int frv_compare_insns (const void *, const void *);
333 static void frv_sort_insn_group (enum frv_insn_group);
334 static void frv_reorder_packet (void);
335 static void frv_fill_unused_units (enum frv_insn_group);
336 static void frv_align_label (void);
337 static void frv_reorg_packet (void);
338 static void frv_register_nop (rtx);
339 static void frv_reorg (void);
340 static void frv_pack_insns (void);
341 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
342 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
343 static bool frv_assemble_integer (rtx, unsigned, int);
344 static void frv_init_builtins (void);
345 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
346 static void frv_init_libfuncs (void);
347 static bool frv_in_small_data_p (tree);
348 static void frv_asm_output_mi_thunk
349 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
350 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
353 static rtx frv_expand_builtin_saveregs (void);
354 static bool frv_rtx_costs (rtx, int, int, int*);
355 static void frv_asm_out_constructor (rtx, int);
356 static void frv_asm_out_destructor (rtx, int);
357 static bool frv_function_symbol_referenced_p (rtx);
358 static bool frv_cannot_force_const_mem (rtx);
359 static const char *unspec_got_name (int);
360 static void frv_output_const_unspec (FILE *,
361 const struct frv_unspec *);
362 static bool frv_function_ok_for_sibcall (tree, tree);
363 static rtx frv_struct_value_rtx (tree, int);
364 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
365 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
368 /* Allow us to easily change the default for -malloc-cc. */
369 #ifndef DEFAULT_NO_ALLOC_CC
370 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
372 #define MASK_DEFAULT_ALLOC_CC 0
375 /* Initialize the GCC target structure. */
376 #undef TARGET_ASM_FUNCTION_PROLOGUE
377 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
378 #undef TARGET_ASM_FUNCTION_EPILOGUE
379 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
380 #undef TARGET_ASM_INTEGER
381 #define TARGET_ASM_INTEGER frv_assemble_integer
382 #undef TARGET_DEFAULT_TARGET_FLAGS
383 #define TARGET_DEFAULT_TARGET_FLAGS \
384 (MASK_DEFAULT_ALLOC_CC \
391 #undef TARGET_HANDLE_OPTION
392 #define TARGET_HANDLE_OPTION frv_handle_option
393 #undef TARGET_INIT_BUILTINS
394 #define TARGET_INIT_BUILTINS frv_init_builtins
395 #undef TARGET_EXPAND_BUILTIN
396 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
397 #undef TARGET_INIT_LIBFUNCS
398 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
399 #undef TARGET_IN_SMALL_DATA_P
400 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
401 #undef TARGET_RTX_COSTS
402 #define TARGET_RTX_COSTS frv_rtx_costs
403 #undef TARGET_ASM_CONSTRUCTOR
404 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
405 #undef TARGET_ASM_DESTRUCTOR
406 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
408 #undef TARGET_ASM_OUTPUT_MI_THUNK
409 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
410 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
411 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
413 #undef TARGET_SCHED_ISSUE_RATE
414 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
416 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
417 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
418 #undef TARGET_CANNOT_FORCE_CONST_MEM
419 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
421 #undef TARGET_HAVE_TLS
422 #define TARGET_HAVE_TLS HAVE_AS_TLS
424 #undef TARGET_STRUCT_VALUE_RTX
425 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
426 #undef TARGET_MUST_PASS_IN_STACK
427 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
428 #undef TARGET_PASS_BY_REFERENCE
429 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
430 #undef TARGET_ARG_PARTIAL_BYTES
431 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
433 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
434 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
435 #undef TARGET_SETUP_INCOMING_VARARGS
436 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
437 #undef TARGET_MACHINE_DEPENDENT_REORG
438 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
440 struct gcc_target targetm = TARGET_INITIALIZER;
442 #define FRV_SYMBOL_REF_TLS_P(RTX) \
443 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
446 /* Any function call that satisfies the machine-independent
447 requirements is eligible on FR-V. */
450 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
451 tree exp ATTRIBUTE_UNUSED)
456 /* Return true if SYMBOL is a small data symbol and relocation RELOC
457 can be used to access it directly in a load or store. */
459 static FRV_INLINE bool
460 frv_small_data_reloc_p (rtx symbol, int reloc)
462 return (GET_CODE (symbol) == SYMBOL_REF
463 && SYMBOL_REF_SMALL_P (symbol)
464 && (!TARGET_FDPIC || flag_pic == 1)
465 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
468 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
471 static FRV_INLINE bool
472 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
474 if (GET_CODE (x) == CONST)
478 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
480 unspec->offset += INTVAL (XEXP (x, 1));
483 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
485 unspec->symbol = XVECEXP (x, 0, 0);
486 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
488 if (unspec->offset == 0)
491 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
492 && unspec->offset > 0
493 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
500 /* Decide whether we can force certain constants to memory. If we
501 decide we can't, the caller should be able to cope with it in
504 We never allow constants to be forced into memory for TARGET_FDPIC.
505 This is necessary for several reasons:
507 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
508 target-independent code will try to force them into the constant
509 pool, thus leading to infinite recursion.
511 2. We can never introduce new constant pool references during reload.
512 Any such reference would require use of the pseudo FDPIC register.
514 3. We can't represent a constant added to a function pointer (which is
515 not the same as a pointer to a function+constant).
517 4. In many cases, it's more efficient to calculate the constant in-line. */
520 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
525 /* Implement TARGET_HANDLE_OPTION. */
528 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
533 if (strcmp (arg, "simple") == 0)
534 frv_cpu_type = FRV_CPU_SIMPLE;
535 else if (strcmp (arg, "tomcat") == 0)
536 frv_cpu_type = FRV_CPU_TOMCAT;
537 else if (strcmp (arg, "fr550") == 0)
538 frv_cpu_type = FRV_CPU_FR550;
539 else if (strcmp (arg, "fr500") == 0)
540 frv_cpu_type = FRV_CPU_FR500;
541 else if (strcmp (arg, "fr450") == 0)
542 frv_cpu_type = FRV_CPU_FR450;
543 else if (strcmp (arg, "fr405") == 0)
544 frv_cpu_type = FRV_CPU_FR405;
545 else if (strcmp (arg, "fr400") == 0)
546 frv_cpu_type = FRV_CPU_FR400;
547 else if (strcmp (arg, "fr300") == 0)
548 frv_cpu_type = FRV_CPU_FR300;
549 else if (strcmp (arg, "frv") == 0)
550 frv_cpu_type = FRV_CPU_GENERIC;
561 frv_default_flags_for_cpu (void)
563 switch (frv_cpu_type)
565 case FRV_CPU_GENERIC:
566 return MASK_DEFAULT_FRV;
569 return MASK_DEFAULT_FR550;
573 return MASK_DEFAULT_FR500;
576 return MASK_DEFAULT_FR450;
580 return MASK_DEFAULT_FR400;
584 return MASK_DEFAULT_SIMPLE;
589 /* Sometimes certain combinations of command options do not make
590 sense on a particular target machine. You can define a macro
591 `OVERRIDE_OPTIONS' to take account of this. This macro, if
592 defined, is executed once just after all the command options have
595 Don't use this macro to turn on various extra optimizations for
596 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
599 frv_override_options (void)
604 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
606 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
607 linker about linking pic and non-pic code. */
610 if (!flag_pic) /* -fPIC */
613 if (! g_switch_set) /* -G0 */
620 /* A C expression whose value is a register class containing hard
621 register REGNO. In general there is more than one such class;
622 choose a class which is "minimal", meaning that no smaller class
623 also contains the register. */
625 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
627 enum reg_class class;
631 int gpr_reg = regno - GPR_FIRST;
633 if (gpr_reg == GR8_REG)
636 else if (gpr_reg == GR9_REG)
639 else if (gpr_reg == GR14_REG)
640 class = FDPIC_FPTR_REGS;
642 else if (gpr_reg == FDPIC_REGNO)
645 else if ((gpr_reg & 3) == 0)
648 else if ((gpr_reg & 1) == 0)
655 else if (FPR_P (regno))
657 int fpr_reg = regno - GPR_FIRST;
658 if ((fpr_reg & 3) == 0)
659 class = QUAD_FPR_REGS;
661 else if ((fpr_reg & 1) == 0)
668 else if (regno == LR_REGNO)
671 else if (regno == LCR_REGNO)
674 else if (ICC_P (regno))
677 else if (FCC_P (regno))
680 else if (ICR_P (regno))
683 else if (FCR_P (regno))
686 else if (ACC_P (regno))
688 int r = regno - ACC_FIRST;
690 class = QUAD_ACC_REGS;
691 else if ((r & 1) == 0)
692 class = EVEN_ACC_REGS;
697 else if (ACCG_P (regno))
703 regno_reg_class[regno] = class;
706 /* Check for small data option */
708 g_switch_value = SDATA_DEFAULT_SIZE;
710 /* A C expression which defines the machine-dependent operand
711 constraint letters for register classes. If CHAR is such a
712 letter, the value should be the register class corresponding to
713 it. Otherwise, the value should be `NO_REGS'. The register
714 letter `r', corresponding to class `GENERAL_REGS', will not be
715 passed to this macro; you do not need to handle it.
717 The following letters are unavailable, due to being used as
722 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
723 'Q', 'R', 'S', 'T', 'U'
725 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
727 for (i = 0; i < 256; i++)
728 reg_class_from_letter[i] = NO_REGS;
730 reg_class_from_letter['a'] = ACC_REGS;
731 reg_class_from_letter['b'] = EVEN_ACC_REGS;
732 reg_class_from_letter['c'] = CC_REGS;
733 reg_class_from_letter['d'] = GPR_REGS;
734 reg_class_from_letter['e'] = EVEN_REGS;
735 reg_class_from_letter['f'] = FPR_REGS;
736 reg_class_from_letter['h'] = FEVEN_REGS;
737 reg_class_from_letter['l'] = LR_REG;
738 reg_class_from_letter['q'] = QUAD_REGS;
739 reg_class_from_letter['t'] = ICC_REGS;
740 reg_class_from_letter['u'] = FCC_REGS;
741 reg_class_from_letter['v'] = ICR_REGS;
742 reg_class_from_letter['w'] = FCR_REGS;
743 reg_class_from_letter['x'] = QUAD_FPR_REGS;
744 reg_class_from_letter['y'] = LCR_REG;
745 reg_class_from_letter['z'] = SPR_REGS;
746 reg_class_from_letter['A'] = QUAD_ACC_REGS;
747 reg_class_from_letter['B'] = ACCG_REGS;
748 reg_class_from_letter['C'] = CR_REGS;
749 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
750 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
752 /* There is no single unaligned SI op for PIC code. Sometimes we
753 need to use ".4byte" and sometimes we need to use ".picptr".
754 See frv_assemble_integer for details. */
755 if (flag_pic || TARGET_FDPIC)
756 targetm.asm_out.unaligned_op.si = 0;
758 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
759 target_flags |= MASK_LINKED_FP;
761 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
762 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
764 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
765 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
767 init_machine_status = frv_init_machine_status;
771 /* Some machines may desire to change what optimizations are performed for
772 various optimization levels. This macro, if defined, is executed once just
773 after the optimization level is determined and before the remainder of the
774 command options have been parsed. Values set in this macro are used as the
775 default values for the other command line options.
777 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
778 `-O' is specified, and 0 if neither is specified.
780 SIZE is nonzero if `-Os' is specified, 0 otherwise.
782 You should not use this macro to change options that are not
783 machine-specific. These should uniformly selected by the same optimization
784 level on all supported machines. Use this macro to enable machbine-specific
787 *Do not examine `write_symbols' in this macro!* The debugging options are
788 *not supposed to alter the generated code. */
790 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
791 scheduling pass at the current time. */
793 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
797 #ifdef DISABLE_SCHED2
798 flag_schedule_insns_after_reload = 0;
807 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
810 frv_string_begins_with (tree name, const char *prefix)
812 int prefix_len = strlen (prefix);
814 /* Remember: NAME's length includes the null terminator. */
815 return (TREE_STRING_LENGTH (name) > prefix_len
816 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
819 /* Zero or more C statements that may conditionally modify two variables
820 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
821 been initialized from the two preceding macros.
823 This is necessary in case the fixed or call-clobbered registers depend on
826 You need not define this macro if it has no work to do.
828 If the usage of an entire class of registers depends on the target flags,
829 you may indicate this to GCC by using this macro to modify `fixed_regs' and
830 `call_used_regs' to 1 for each of the registers in the classes which should
831 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
832 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
834 (However, if this class is not included in `GENERAL_REGS' and all of the
835 insn patterns whose constraints permit this class are controlled by target
836 switches, then GCC will automatically avoid using these registers when the
837 target switches are opposed to them.) */
840 frv_conditional_register_usage (void)
844 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
845 fixed_regs[i] = call_used_regs[i] = 1;
847 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
848 fixed_regs[i] = call_used_regs[i] = 1;
850 /* Reserve the registers used for conditional execution. At present, we need
851 1 ICC and 1 ICR register. */
852 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
853 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
857 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
858 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
859 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
860 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
864 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
865 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
868 /* If -fpic, SDA_BASE_REG is the PIC register. */
869 if (g_switch_value == 0 && !flag_pic)
870 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
873 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
879 * Compute the stack frame layout
882 * +---------------+-----------------------+-----------------------+
883 * |Register |type |caller-save/callee-save|
884 * +---------------+-----------------------+-----------------------+
885 * |GR0 |Zero register | - |
886 * |GR1 |Stack pointer(SP) | - |
887 * |GR2 |Frame pointer(FP) | - |
888 * |GR3 |Hidden parameter | caller save |
889 * |GR4-GR7 | - | caller save |
890 * |GR8-GR13 |Argument register | caller save |
891 * |GR14-GR15 | - | caller save |
892 * |GR16-GR31 | - | callee save |
893 * |GR32-GR47 | - | caller save |
894 * |GR48-GR63 | - | callee save |
895 * |FR0-FR15 | - | caller save |
896 * |FR16-FR31 | - | callee save |
897 * |FR32-FR47 | - | caller save |
898 * |FR48-FR63 | - | callee save |
899 * +---------------+-----------------------+-----------------------+
903 * SP-> |-----------------------------------|
905 * |-----------------------------------|
906 * | Register save area |
907 * |-----------------------------------|
908 * | Local variable save area |
909 * FP-> |-----------------------------------|
911 * |-----------------------------------|
912 * | Hidden parameter save area |
913 * |-----------------------------------|
914 * | Return address(LR) storage area |
915 * |-----------------------------------|
916 * | Padding for alignment |
917 * |-----------------------------------|
918 * | Register argument area |
919 * OLD SP-> |-----------------------------------|
921 * |-----------------------------------|
924 * Argument area/Parameter area:
926 * When a function is called, this area is used for argument transfer. When
927 * the argument is set up by the caller function, this area is referred to as
928 * the argument area. When the argument is referenced by the callee function,
929 * this area is referred to as the parameter area. The area is allocated when
930 * all arguments cannot be placed on the argument register at the time of
933 * Register save area:
935 * This is a register save area that must be guaranteed for the caller
936 * function. This area is not secured when the register save operation is not
939 * Local variable save area:
941 * This is the area for local variables and temporary variables.
945 * This area stores the FP value of the caller function.
947 * Hidden parameter save area:
949 * This area stores the start address of the return value storage
950 * area for a struct/union return function.
951 * When a struct/union is used as the return value, the caller
952 * function stores the return value storage area start address in
953 * register GR3 and passes it to the caller function.
954 * The callee function interprets the address stored in the GR3
955 * as the return value storage area start address.
956 * When register GR3 needs to be saved into memory, the callee
957 * function saves it in the hidden parameter save area. This
958 * area is not secured when the save operation is not needed.
960 * Return address(LR) storage area:
962 * This area saves the LR. The LR stores the address of a return to the caller
963 * function for the purpose of function calling.
965 * Argument register area:
967 * This area saves the argument register. This area is not secured when the
968 * save operation is not needed.
972 * Arguments, the count of which equals the count of argument registers (6
973 * words), are positioned in registers GR8 to GR13 and delivered to the callee
974 * function. When a struct/union return function is called, the return value
975 * area address is stored in register GR3. Arguments not placed in the
976 * argument registers will be stored in the stack argument area for transfer
977 * purposes. When an 8-byte type argument is to be delivered using registers,
978 * it is divided into two and placed in two registers for transfer. When
979 * argument registers must be saved to memory, the callee function secures an
980 * argument register save area in the stack. In this case, a continuous
981 * argument register save area must be established in the parameter area. The
982 * argument register save area must be allocated as needed to cover the size of
983 * the argument register to be saved. If the function has a variable count of
984 * arguments, it saves all argument registers in the argument register save
987 * Argument Extension Format:
989 * When an argument is to be stored in the stack, its type is converted to an
990 * extended type in accordance with the individual argument type. The argument
991 * is freed by the caller function after the return from the callee function is
994 * +-----------------------+---------------+------------------------+
995 * | Argument Type |Extended Type |Stack Storage Size(byte)|
996 * +-----------------------+---------------+------------------------+
998 * |signed char |int | 4 |
999 * |unsigned char |int | 4 |
1000 * |[signed] short int |int | 4 |
1001 * |unsigned short int |int | 4 |
1002 * |[signed] int |No extension | 4 |
1003 * |unsigned int |No extension | 4 |
1004 * |[signed] long int |No extension | 4 |
1005 * |unsigned long int |No extension | 4 |
1006 * |[signed] long long int |No extension | 8 |
1007 * |unsigned long long int |No extension | 8 |
1008 * |float |double | 8 |
1009 * |double |No extension | 8 |
1010 * |long double |No extension | 8 |
1011 * |pointer |No extension | 4 |
1012 * |struct/union |- | 4 (*1) |
1013 * +-----------------------+---------------+------------------------+
1015 * When a struct/union is to be delivered as an argument, the caller copies it
1016 * to the local variable area and delivers the address of that area.
1020 * +-------------------------------+----------------------+
1021 * |Return Value Type |Return Value Interface|
1022 * +-------------------------------+----------------------+
1024 * |[signed|unsigned] char |GR8 |
1025 * |[signed|unsigned] short int |GR8 |
1026 * |[signed|unsigned] int |GR8 |
1027 * |[signed|unsigned] long int |GR8 |
1029 * |[signed|unsigned] long long int|GR8 & GR9 |
1031 * |double |GR8 & GR9 |
1032 * |long double |GR8 & GR9 |
1033 * |struct/union |(*1) |
1034 * +-------------------------------+----------------------+
1036 * When a struct/union is used as the return value, the caller function stores
1037 * the start address of the return value storage area into GR3 and then passes
1038 * it to the callee function. The callee function interprets GR3 as the start
1039 * address of the return value storage area. When this address needs to be
1040 * saved in memory, the callee function secures the hidden parameter save area
1041 * and saves the address in that area.
1045 frv_stack_info (void)
1047 static frv_stack_t info, zero_info;
1048 frv_stack_t *info_ptr = &info;
1049 tree fndecl = current_function_decl;
1057 /* If we've already calculated the values and reload is complete,
1059 if (frv_stack_cache)
1060 return frv_stack_cache;
1062 /* Zero all fields. */
1065 /* Set up the register range information. */
1066 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1067 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1068 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1069 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1071 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1072 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1073 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1074 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1076 info_ptr->regs[STACK_REGS_LR].name = "lr";
1077 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1078 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1079 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1081 info_ptr->regs[STACK_REGS_CC].name = "cc";
1082 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1083 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1084 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1086 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1087 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1088 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1090 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1091 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1092 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1093 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1094 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1096 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1097 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1098 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1099 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1101 info_ptr->regs[STACK_REGS_FP].name = "fp";
1102 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1103 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1104 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1106 /* Determine if this is a stdarg function. If so, allocate space to store
1113 /* Find the last argument, and see if it is __builtin_va_alist. */
1114 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1116 next_arg = TREE_CHAIN (cur_arg);
1117 if (next_arg == (tree)0)
1119 if (DECL_NAME (cur_arg)
1120 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1128 /* Iterate over all of the register ranges. */
1129 for (range = 0; range < STACK_REGS_MAX; range++)
1131 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1132 int first = reg_ptr->first;
1133 int last = reg_ptr->last;
1135 int size_2words = 0;
1138 /* Calculate which registers need to be saved & save area size. */
1142 for (regno = first; regno <= last; regno++)
1144 if ((regs_ever_live[regno] && !call_used_regs[regno])
1145 || (current_function_calls_eh_return
1146 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1147 || (!TARGET_FDPIC && flag_pic
1148 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1150 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1151 size_1word += UNITS_PER_WORD;
1156 /* Calculate whether we need to create a frame after everything else
1157 has been processed. */
1162 if (regs_ever_live[LR_REGNO]
1164 /* This is set for __builtin_return_address, etc. */
1165 || cfun->machine->frame_needed
1166 || (TARGET_LINKED_FP && frame_pointer_needed)
1167 || (!TARGET_FDPIC && flag_pic
1168 && cfun->uses_pic_offset_table))
1170 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1171 size_1word += UNITS_PER_WORD;
1175 case STACK_REGS_STDARG:
1178 /* If this is a stdarg function with a non varardic
1179 argument split between registers and the stack,
1180 adjust the saved registers downward. */
1181 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1184 for (regno = first; regno <= last; regno++)
1186 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1187 size_1word += UNITS_PER_WORD;
1190 info_ptr->stdarg_size = size_1word;
1194 case STACK_REGS_STRUCT:
1195 if (cfun->returns_struct)
1197 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1198 size_1word += UNITS_PER_WORD;
1206 /* If this is a field, it only takes one word. */
1207 if (reg_ptr->field_p)
1208 size_1word = UNITS_PER_WORD;
1210 /* Determine which register pairs can be saved together. */
1211 else if (reg_ptr->dword_p && TARGET_DWORD)
1213 for (regno = first; regno < last; regno += 2)
1215 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1217 size_2words += 2 * UNITS_PER_WORD;
1218 size_1word -= 2 * UNITS_PER_WORD;
1219 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1220 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1225 reg_ptr->size_1word = size_1word;
1226 reg_ptr->size_2words = size_2words;
1228 if (! reg_ptr->special_p)
1230 info_ptr->regs_size_1word += size_1word;
1231 info_ptr->regs_size_2words += size_2words;
1236 /* Set up the sizes of each each field in the frame body, making the sizes
1237 of each be divisible by the size of a dword if dword operations might
1238 be used, or the size of a word otherwise. */
1239 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1241 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1242 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1243 + info_ptr->regs_size_1word,
1245 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1247 info_ptr->pretend_size = cfun->pretend_args_size;
1249 /* Work out the size of the frame, excluding the header. Both the frame
1250 body and register parameter area will be dword-aligned. */
1251 info_ptr->total_size
1252 = (ADDR_ALIGN (info_ptr->parameter_size
1253 + info_ptr->regs_size
1254 + info_ptr->vars_size,
1256 + ADDR_ALIGN (info_ptr->pretend_size
1257 + info_ptr->stdarg_size,
1258 2 * UNITS_PER_WORD));
1260 /* See if we need to create a frame at all, if so add header area. */
1261 if (info_ptr->total_size > 0
1262 || frame_pointer_needed
1263 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1264 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1266 offset = info_ptr->parameter_size;
1267 info_ptr->header_size = 4 * UNITS_PER_WORD;
1268 info_ptr->total_size += 4 * UNITS_PER_WORD;
1270 /* Calculate the offsets to save normal register pairs. */
1271 for (range = 0; range < STACK_REGS_MAX; range++)
1273 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1274 if (! reg_ptr->special_p)
1276 int first = reg_ptr->first;
1277 int last = reg_ptr->last;
1280 for (regno = first; regno <= last; regno++)
1281 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1282 && regno != FRAME_POINTER_REGNUM
1283 && (regno < FIRST_ARG_REGNUM
1284 || regno > LAST_ARG_REGNUM))
1286 info_ptr->reg_offset[regno] = offset;
1287 offset += 2 * UNITS_PER_WORD;
1292 /* Calculate the offsets to save normal single registers. */
1293 for (range = 0; range < STACK_REGS_MAX; range++)
1295 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1296 if (! reg_ptr->special_p)
1298 int first = reg_ptr->first;
1299 int last = reg_ptr->last;
1302 for (regno = first; regno <= last; regno++)
1303 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1304 && regno != FRAME_POINTER_REGNUM
1305 && (regno < FIRST_ARG_REGNUM
1306 || regno > LAST_ARG_REGNUM))
1308 info_ptr->reg_offset[regno] = offset;
1309 offset += UNITS_PER_WORD;
1314 /* Calculate the offset to save the local variables at. */
1315 offset = ADDR_ALIGN (offset, alignment);
1316 if (info_ptr->vars_size)
1318 info_ptr->vars_offset = offset;
1319 offset += info_ptr->vars_size;
1322 /* Align header to a dword-boundary. */
1323 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1325 /* Calculate the offsets in the fixed frame. */
1326 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1327 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1328 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1330 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1331 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1332 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1334 if (cfun->returns_struct)
1336 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1337 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1338 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1341 /* Calculate the offsets to store the arguments passed in registers
1342 for stdarg functions. The register pairs are first and the single
1343 register if any is last. The register save area starts on a
1345 if (info_ptr->stdarg_size)
1347 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1348 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1351 /* Skip the header. */
1352 offset += 4 * UNITS_PER_WORD;
1353 for (regno = first; regno <= last; regno++)
1355 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1357 info_ptr->reg_offset[regno] = offset;
1358 offset += 2 * UNITS_PER_WORD;
1360 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1362 info_ptr->reg_offset[regno] = offset;
1363 offset += UNITS_PER_WORD;
1369 if (reload_completed)
1370 frv_stack_cache = info_ptr;
1376 /* Print the information about the frv stack offsets, etc. when debugging. */
1379 frv_debug_stack (frv_stack_t *info)
1384 info = frv_stack_info ();
1386 fprintf (stderr, "\nStack information for function %s:\n",
1387 ((current_function_decl && DECL_NAME (current_function_decl))
1388 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1391 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1392 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1393 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1394 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1395 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1397 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1398 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1399 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1400 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1402 for (range = 0; range < STACK_REGS_MAX; range++)
1404 frv_stack_regs_t *regs = &(info->regs[range]);
1405 if ((regs->size_1word + regs->size_2words) > 0)
1407 int first = regs->first;
1408 int last = regs->last;
1411 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1412 regs->name, regs->size_1word + regs->size_2words,
1413 regs->size_1word, regs->size_2words);
1415 for (regno = first; regno <= last; regno++)
1417 if (info->save_p[regno] == REG_SAVE_1WORD)
1418 fprintf (stderr, " %s (%d)", reg_names[regno],
1419 info->reg_offset[regno]);
1421 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1422 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1423 reg_names[regno+1], info->reg_offset[regno]);
1426 fputc ('\n', stderr);
1436 /* Used during final to control the packing of insns. The value is
1437 1 if the current instruction should be packed with the next one,
1438 0 if it shouldn't or -1 if packing is disabled altogether. */
1440 static int frv_insn_packing_flag;
1442 /* True if the current function contains a far jump. */
1445 frv_function_contains_far_jump (void)
1447 rtx insn = get_insns ();
1449 && !(GET_CODE (insn) == JUMP_INSN
1450 /* Ignore tablejump patterns. */
1451 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1452 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1453 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1454 insn = NEXT_INSN (insn);
1455 return (insn != NULL);
1458 /* For the FRV, this function makes sure that a function with far jumps
1459 will return correctly. It also does the VLIW packing. */
1462 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1464 /* If no frame was created, check whether the function uses a call
1465 instruction to implement a far jump. If so, save the link in gr3 and
1466 replace all returns to LR with returns to GR3. GR3 is used because it
1467 is call-clobbered, because is not available to the register allocator,
1468 and because all functions that take a hidden argument pointer will have
1470 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1474 /* Just to check that the above comment is true. */
1475 if (regs_ever_live[GPR_FIRST + 3])
1478 /* Generate the instruction that saves the link register. */
1479 fprintf (file, "\tmovsg lr,gr3\n");
1481 /* Replace the LR with GR3 in *return_internal patterns. The insn
1482 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1483 simply emit a different assembly directive because bralr and jmpl
1484 execute in different units. */
1485 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1486 if (GET_CODE (insn) == JUMP_INSN)
1488 rtx pattern = PATTERN (insn);
1489 if (GET_CODE (pattern) == PARALLEL
1490 && XVECLEN (pattern, 0) >= 2
1491 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1492 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1494 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1495 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1496 REGNO (address) = GPR_FIRST + 3;
1503 /* Allow the garbage collector to free the nops created by frv_reorg. */
1504 memset (frv_nops, 0, sizeof (frv_nops));
1508 /* Return the next available temporary register in a given class. */
1511 frv_alloc_temp_reg (
1512 frv_tmp_reg_t *info, /* which registers are available */
1513 enum reg_class class, /* register class desired */
1514 enum machine_mode mode, /* mode to allocate register with */
1515 int mark_as_used, /* register not available after allocation */
1516 int no_abort) /* return NULL instead of aborting */
1518 int regno = info->next_reg[ (int)class ];
1519 int orig_regno = regno;
1520 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1525 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1526 && TEST_HARD_REG_BIT (info->regs, regno))
1529 if (++regno >= FIRST_PSEUDO_REGISTER)
1531 if (regno == orig_regno)
1540 nr = HARD_REGNO_NREGS (regno, mode);
1541 info->next_reg[ (int)class ] = regno + nr;
1544 for (i = 0; i < nr; i++)
1545 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1547 return gen_rtx_REG (mode, regno);
1551 /* Return an rtx with the value OFFSET, which will either be a register or a
1552 signed 12-bit integer. It can be used as the second operand in an "add"
1553 instruction, or as the index in a load or store.
1555 The function returns a constant rtx if OFFSET is small enough, otherwise
1556 it loads the constant into register OFFSET_REGNO and returns that. */
1558 frv_frame_offset_rtx (int offset)
1560 rtx offset_rtx = GEN_INT (offset);
1561 if (IN_RANGE_P (offset, -2048, 2047))
1565 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1566 if (IN_RANGE_P (offset, -32768, 32767))
1567 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1570 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1571 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1577 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1578 prologue and epilogue uses such expressions to access the stack. */
1580 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1582 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1584 frv_frame_offset_rtx (offset)));
1587 /* Generate a frame-related expression:
1589 (set REG (mem (plus (sp) (const_int OFFSET)))).
1591 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1592 instructions. Marking the expressions as frame-related is superfluous if
1593 the note contains just a single set. But if the note contains a PARALLEL
1594 or SEQUENCE that has several sets, each set must be individually marked
1595 as frame-related. */
1597 frv_dwarf_store (rtx reg, int offset)
1599 rtx set = gen_rtx_SET (VOIDmode,
1600 gen_rtx_MEM (GET_MODE (reg),
1601 plus_constant (stack_pointer_rtx,
1604 RTX_FRAME_RELATED_P (set) = 1;
1608 /* Emit a frame-related instruction whose pattern is PATTERN. The
1609 instruction is the last in a sequence that cumulatively performs the
1610 operation described by DWARF_PATTERN. The instruction is marked as
1611 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1614 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1616 rtx insn = emit_insn (pattern);
1617 RTX_FRAME_RELATED_P (insn) = 1;
1618 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1623 /* Emit instructions that transfer REG to or from the memory location (sp +
1624 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1625 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1626 function to store registers and only the epilogue uses it to load them.
1628 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1629 The generated instruction will use BASE as its base register. BASE may
1630 simply be the stack pointer, but if several accesses are being made to a
1631 region far away from the stack pointer, it may be more efficient to set
1632 up a temporary instead.
1634 Store instructions will be frame-related and will be annotated with the
1635 overall effect of the store. Load instructions will be followed by a
1636 (use) to prevent later optimizations from zapping them.
1638 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1639 as a temporary in such cases. */
1641 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1643 enum machine_mode mode = GET_MODE (reg);
1644 rtx mem = frv_frame_mem (mode,
1646 stack_offset - accessor->base_offset);
1648 if (accessor->op == FRV_LOAD)
1650 if (SPR_P (REGNO (reg)))
1652 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1653 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1654 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1657 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1658 emit_insn (gen_rtx_USE (VOIDmode, reg));
1662 if (SPR_P (REGNO (reg)))
1664 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1665 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1666 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1667 frv_dwarf_store (reg, stack_offset));
1669 else if (GET_MODE (reg) == DImode)
1671 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1672 with a separate save for each register. */
1673 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1674 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1675 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1676 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1677 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1678 gen_rtx_PARALLEL (VOIDmode,
1679 gen_rtvec (2, set1, set2)));
1682 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1683 frv_dwarf_store (reg, stack_offset));
1687 /* A function that uses frv_frame_access to transfer a group of registers to
1688 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1689 is the stack information generated by frv_stack_info, and REG_SET is the
1690 number of the register set to transfer. */
1692 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1696 frv_stack_regs_t *regs_info;
1699 regs_info = &info->regs[reg_set];
1700 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1701 if (info->save_p[regno])
1702 frv_frame_access (accessor,
1703 info->save_p[regno] == REG_SAVE_2WORDS
1704 ? gen_rtx_REG (DImode, regno)
1705 : gen_rtx_REG (SImode, regno),
1706 info->reg_offset[regno]);
1709 /* Save or restore callee-saved registers that are kept outside the frame
1710 header. The function saves the registers if OP is FRV_STORE and restores
1711 them if OP is FRV_LOAD. INFO is the stack information generated by
1714 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1716 frv_frame_accessor_t accessor;
1719 accessor.base = stack_pointer_rtx;
1720 accessor.base_offset = 0;
1721 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1722 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1723 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1727 /* Called after register allocation to add any instructions needed for the
1728 prologue. Using a prologue insn is favored compared to putting all of the
1729 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1730 it allows the scheduler to intermix instructions with the saves of
1731 the caller saved registers. In some cases, it might be necessary
1732 to emit a barrier instruction as the last insn to prevent such
1735 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1736 so that the debug info generation code can handle them properly. */
1738 frv_expand_prologue (void)
1740 frv_stack_t *info = frv_stack_info ();
1741 rtx sp = stack_pointer_rtx;
1742 rtx fp = frame_pointer_rtx;
1743 frv_frame_accessor_t accessor;
1745 if (TARGET_DEBUG_STACK)
1746 frv_debug_stack (info);
1748 if (info->total_size == 0)
1751 /* We're interested in three areas of the frame here:
1753 A: the register save area
1755 C: the header after B
1757 If the frame pointer isn't used, we'll have to set up A, B and C
1758 using the stack pointer. If the frame pointer is used, we'll access
1762 B: set up using sp or a temporary (see below)
1765 We set up B using the stack pointer if the frame is small enough.
1766 Otherwise, it's more efficient to copy the old stack pointer into a
1767 temporary and use that.
1769 Note that it's important to make sure the prologue and epilogue use the
1770 same registers to access A and C, since doing otherwise will confuse
1771 the aliasing code. */
1773 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1774 isn't used, the same method will serve for C. */
1775 accessor.op = FRV_STORE;
1776 if (frame_pointer_needed && info->total_size > 2048)
1780 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1781 accessor.base_offset = info->total_size;
1782 insn = emit_insn (gen_movsi (accessor.base, sp));
1786 accessor.base = stack_pointer_rtx;
1787 accessor.base_offset = 0;
1790 /* Allocate the stack space. */
1792 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1793 rtx dwarf_offset = GEN_INT (-info->total_size);
1795 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1798 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1801 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1802 and point the new one to that location. */
1803 if (frame_pointer_needed)
1805 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1807 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1808 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1810 rtx asm_src = plus_constant (accessor.base,
1811 fp_offset - accessor.base_offset);
1812 rtx dwarf_src = plus_constant (sp, fp_offset);
1814 /* Store the old frame pointer at (sp + FP_OFFSET). */
1815 frv_frame_access (&accessor, fp, fp_offset);
1817 /* Set up the new frame pointer. */
1818 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1819 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1821 /* Access region C from the frame pointer. */
1823 accessor.base_offset = fp_offset;
1826 /* Set up region C. */
1827 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1828 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1829 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1831 /* Set up region A. */
1832 frv_frame_access_standard_regs (FRV_STORE, info);
1834 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1835 scheduler from moving loads before the stores saving the registers. */
1836 if (info->stdarg_size > 0)
1837 emit_insn (gen_blockage ());
1839 /* Set up pic register/small data register for this function. */
1840 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1841 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1842 gen_rtx_REG (Pmode, LR_REGNO),
1843 gen_rtx_REG (SImode, OFFSET_REGNO)));
1847 /* Under frv, all of the work is done via frv_expand_epilogue, but
1848 this function provides a convenient place to do cleanup. */
1851 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1852 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1854 frv_stack_cache = (frv_stack_t *)0;
1856 /* Zap last used registers for conditional execution. */
1857 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1859 /* Release the bitmap of created insns. */
1860 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1864 /* Called after register allocation to add any instructions needed for the
1865 epilogue. Using an epilogue insn is favored compared to putting all of the
1866 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1867 it allows the scheduler to intermix instructions with the saves of
1868 the caller saved registers. In some cases, it might be necessary
1869 to emit a barrier instruction as the last insn to prevent such
1873 frv_expand_epilogue (bool emit_return)
1875 frv_stack_t *info = frv_stack_info ();
1876 rtx fp = frame_pointer_rtx;
1877 rtx sp = stack_pointer_rtx;
1881 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1883 /* Restore the stack pointer to its original value if alloca or the like
1885 if (! current_function_sp_is_unchanging)
1886 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1888 /* Restore the callee-saved registers that were used in this function. */
1889 frv_frame_access_standard_regs (FRV_LOAD, info);
1891 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1892 no return instruction should be emitted. */
1893 if (info->save_p[LR_REGNO])
1898 /* Use the same method to access the link register's slot as we did in
1899 the prologue. In other words, use the frame pointer if available,
1900 otherwise use the stack pointer.
1902 LR_OFFSET is the offset of the link register's slot from the start
1903 of the frame and MEM is a memory rtx for it. */
1904 lr_offset = info->reg_offset[LR_REGNO];
1905 if (frame_pointer_needed)
1906 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1908 mem = frv_frame_mem (Pmode, sp, lr_offset);
1910 /* Load the old link register into a GPR. */
1911 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1912 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1915 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1917 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1918 the load is preserved. */
1919 if (frame_pointer_needed)
1921 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1922 emit_insn (gen_rtx_USE (VOIDmode, fp));
1925 /* Deallocate the stack frame. */
1926 if (info->total_size != 0)
1928 rtx offset = frv_frame_offset_rtx (info->total_size);
1929 emit_insn (gen_stack_adjust (sp, sp, offset));
1932 /* If this function uses eh_return, add the final stack adjustment now. */
1933 if (current_function_calls_eh_return)
1934 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1937 emit_jump_insn (gen_epilogue_return (return_addr));
1940 rtx lr = return_addr;
1942 if (REGNO (return_addr) != LR_REGNO)
1944 lr = gen_rtx_REG (Pmode, LR_REGNO);
1945 emit_move_insn (lr, return_addr);
1948 emit_insn (gen_rtx_USE (VOIDmode, lr));
1953 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1956 frv_asm_output_mi_thunk (FILE *file,
1957 tree thunk_fndecl ATTRIBUTE_UNUSED,
1958 HOST_WIDE_INT delta,
1959 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1962 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1963 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1964 const char *name_jmp = reg_names[JUMP_REGNO];
1965 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1967 /* Do the add using an addi if possible. */
1968 if (IN_RANGE_P (delta, -2048, 2047))
1969 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1972 const char *const name_add = reg_names[TEMP_REGNO];
1973 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1974 parallel, delta, name_add);
1975 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1977 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1982 const char *name_pic = reg_names[FDPIC_REGNO];
1983 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1987 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1988 assemble_name (file, name_func);
1989 fprintf (file, "),%s\n", name_jmp);
1991 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1992 assemble_name (file, name_func);
1993 fprintf (file, "),%s\n", name_jmp);
1995 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1999 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2000 assemble_name (file, name_func);
2001 fprintf (file, "\t)), %s\n", name_jmp);
2006 fprintf (file, "\tsethi%s #hi(", parallel);
2007 assemble_name (file, name_func);
2008 fprintf (file, "),%s\n", name_jmp);
2010 fprintf (file, "\tsetlo #lo(");
2011 assemble_name (file, name_func);
2012 fprintf (file, "),%s\n", name_jmp);
2016 /* Use JUMP_REGNO as a temporary PIC register. */
2017 const char *name_lr = reg_names[LR_REGNO];
2018 const char *name_gppic = name_jmp;
2019 const char *name_tmp = reg_names[TEMP_REGNO];
2021 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2022 fprintf (file, "\tcall 1f\n");
2023 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2024 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2025 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2026 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2027 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2029 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2030 assemble_name (file, name_func);
2031 fprintf (file, "),%s\n", name_tmp);
2033 fprintf (file, "\tsetlo #gprello(");
2034 assemble_name (file, name_func);
2035 fprintf (file, "),%s\n", name_tmp);
2037 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2040 /* Jump to the function address. */
2041 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2045 /* A C expression which is nonzero if a function must have and use a frame
2046 pointer. This expression is evaluated in the reload pass. If its value is
2047 nonzero the function will have a frame pointer.
2049 The expression can in principle examine the current function and decide
2050 according to the facts, but on most machines the constant 0 or the constant
2051 1 suffices. Use 0 when the machine allows code to be generated with no
2052 frame pointer, and doing so saves some time or space. Use 1 when there is
2053 no possible advantage to avoiding a frame pointer.
2055 In certain cases, the compiler does not know how to produce valid code
2056 without a frame pointer. The compiler recognizes those cases and
2057 automatically gives the function a frame pointer regardless of what
2058 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2060 In a function that does not require a frame pointer, the frame pointer
2061 register can be allocated for ordinary usage, unless you mark it as a fixed
2062 register. See `FIXED_REGISTERS' for more information. */
2064 /* On frv, create a frame whenever we need to create stack. */
2067 frv_frame_pointer_required (void)
2069 /* If we forgoing the usual linkage requirements, we only need
2070 a frame pointer if the stack pointer might change. */
2071 if (!TARGET_LINKED_FP)
2072 return !current_function_sp_is_unchanging;
2074 if (! current_function_is_leaf)
2077 if (get_frame_size () != 0)
2083 if (!current_function_sp_is_unchanging)
2086 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2092 if (cfun->machine->frame_needed)
2099 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2100 initial difference between the specified pair of registers. This macro must
2101 be defined if `ELIMINABLE_REGS' is defined. */
2103 /* See frv_stack_info for more details on the frv stack frame. */
2106 frv_initial_elimination_offset (int from, int to)
2108 frv_stack_t *info = frv_stack_info ();
2111 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2112 ret = info->total_size - info->pretend_size;
2114 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2115 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2117 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2118 ret = (info->total_size
2119 - info->reg_offset[FRAME_POINTER_REGNUM]
2120 - info->pretend_size);
2125 if (TARGET_DEBUG_STACK)
2126 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2127 reg_names [from], reg_names[to], ret);
2133 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2136 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2137 enum machine_mode mode,
2138 tree type ATTRIBUTE_UNUSED,
2142 if (TARGET_DEBUG_ARG)
2144 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2145 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2149 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2152 frv_expand_builtin_saveregs (void)
2154 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2156 if (TARGET_DEBUG_ARG)
2157 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2160 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2164 /* Expand __builtin_va_start to do the va_start macro. */
2167 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2170 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2172 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2173 GEN_INT (UNITS_PER_WORD * num));
2175 if (TARGET_DEBUG_ARG)
2177 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2178 cfun->args_info, num);
2180 debug_rtx (nextarg);
2183 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2184 make_tree (ptr_type_node, nextarg));
2185 TREE_SIDE_EFFECTS (t) = 1;
2187 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2191 /* Expand a block move operation, and return 1 if successful. Return 0
2192 if we should let the compiler generate normal code.
2194 operands[0] is the destination
2195 operands[1] is the source
2196 operands[2] is the length
2197 operands[3] is the alignment */
2199 /* Maximum number of loads to do before doing the stores */
2200 #ifndef MAX_MOVE_REG
2201 #define MAX_MOVE_REG 4
2204 /* Maximum number of total loads to do. */
2205 #ifndef TOTAL_MOVE_REG
2206 #define TOTAL_MOVE_REG 8
2210 frv_expand_block_move (rtx operands[])
2212 rtx orig_dest = operands[0];
2213 rtx orig_src = operands[1];
2214 rtx bytes_rtx = operands[2];
2215 rtx align_rtx = operands[3];
2216 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2229 rtx stores[MAX_MOVE_REG];
2231 enum machine_mode mode;
2233 /* If this is not a fixed size move, just call memcpy. */
2237 /* If this is not a fixed size alignment, abort. */
2238 if (GET_CODE (align_rtx) != CONST_INT)
2241 align = INTVAL (align_rtx);
2243 /* Anything to move? */
2244 bytes = INTVAL (bytes_rtx);
2248 /* Don't support real large moves. */
2249 if (bytes > TOTAL_MOVE_REG*align)
2252 /* Move the address into scratch registers. */
2253 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2254 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2256 num_reg = offset = 0;
2257 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2259 /* Calculate the correct offset for src/dest. */
2263 dest_addr = dest_reg;
2267 src_addr = plus_constant (src_reg, offset);
2268 dest_addr = plus_constant (dest_reg, offset);
2271 /* Generate the appropriate load and store, saving the stores
2273 if (bytes >= 4 && align >= 4)
2275 else if (bytes >= 2 && align >= 2)
2280 move_bytes = GET_MODE_SIZE (mode);
2281 tmp_reg = gen_reg_rtx (mode);
2282 src_mem = change_address (orig_src, mode, src_addr);
2283 dest_mem = change_address (orig_dest, mode, dest_addr);
2284 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2285 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2287 if (num_reg >= MAX_MOVE_REG)
2289 for (i = 0; i < num_reg; i++)
2290 emit_insn (stores[i]);
2295 for (i = 0; i < num_reg; i++)
2296 emit_insn (stores[i]);
2302 /* Expand a block clear operation, and return 1 if successful. Return 0
2303 if we should let the compiler generate normal code.
2305 operands[0] is the destination
2306 operands[1] is the length
2307 operands[2] is the alignment */
2310 frv_expand_block_clear (rtx operands[])
2312 rtx orig_dest = operands[0];
2313 rtx bytes_rtx = operands[1];
2314 rtx align_rtx = operands[2];
2315 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2324 enum machine_mode mode;
2326 /* If this is not a fixed size move, just call memcpy. */
2330 /* If this is not a fixed size alignment, abort. */
2331 if (GET_CODE (align_rtx) != CONST_INT)
2334 align = INTVAL (align_rtx);
2336 /* Anything to move? */
2337 bytes = INTVAL (bytes_rtx);
2341 /* Don't support real large clears. */
2342 if (bytes > TOTAL_MOVE_REG*align)
2345 /* Move the address into a scratch register. */
2346 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2348 num_reg = offset = 0;
2349 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2351 /* Calculate the correct offset for src/dest. */
2352 dest_addr = ((offset == 0)
2354 : plus_constant (dest_reg, offset));
2356 /* Generate the appropriate store of gr0. */
2357 if (bytes >= 4 && align >= 4)
2359 else if (bytes >= 2 && align >= 2)
2364 clear_bytes = GET_MODE_SIZE (mode);
2365 dest_mem = change_address (orig_dest, mode, dest_addr);
2366 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2373 /* The following variable is used to output modifiers of assembler
2374 code of the current output insn. */
2376 static rtx *frv_insn_operands;
2378 /* The following function is used to add assembler insn code suffix .p
2379 if it is necessary. */
2382 frv_asm_output_opcode (FILE *f, const char *ptr)
2386 if (frv_insn_packing_flag <= 0)
2389 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2392 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2393 || (*ptr >= 'A' && *ptr <= 'Z')))
2395 int letter = *ptr++;
2398 frv_print_operand (f, frv_insn_operands [c], letter);
2399 while ((c = *ptr) >= '0' && c <= '9')
2411 /* Set up the packing bit for the current output insn. Note that this
2412 function is not called for asm insns. */
2415 frv_final_prescan_insn (rtx insn, rtx *opvec,
2416 int noperands ATTRIBUTE_UNUSED)
2420 if (frv_insn_packing_flag >= 0)
2422 frv_insn_operands = opvec;
2423 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2425 else if (recog_memoized (insn) >= 0
2426 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2427 /* Packing optimizations have been disabled, but INSN can only
2428 be issued in M1. Insert an mnop in M0. */
2429 fprintf (asm_out_file, "\tmnop.p\n");
2435 /* A C expression whose value is RTL representing the address in a stack frame
2436 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2437 an RTL expression for the address of the stack frame itself.
2439 If you don't define this macro, the default is to return the value of
2440 FRAMEADDR--that is, the stack frame address is also the address of the stack
2441 word that points to the previous frame. */
2443 /* The default is correct, but we need to make sure the frame gets created. */
2445 frv_dynamic_chain_address (rtx frame)
2447 cfun->machine->frame_needed = 1;
2452 /* A C expression whose value is RTL representing the value of the return
2453 address for the frame COUNT steps up from the current frame, after the
2454 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2455 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2458 The value of the expression must always be the correct address when COUNT is
2459 zero, but may be `NULL_RTX' if there is not way to determine the return
2460 address of other frames. */
2463 frv_return_addr_rtx (int count, rtx frame)
2467 cfun->machine->frame_needed = 1;
2468 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2471 /* Given a memory reference MEMREF, interpret the referenced memory as
2472 an array of MODE values, and return a reference to the element
2473 specified by INDEX. Assume that any pre-modification implicit in
2474 MEMREF has already happened.
2476 MEMREF must be a legitimate operand for modes larger than SImode.
2477 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2478 this function cannot handle. */
2480 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2482 rtx base = XEXP (memref, 0);
2483 if (GET_CODE (base) == PRE_MODIFY)
2484 base = XEXP (base, 0);
2485 return change_address (memref, mode,
2486 plus_constant (base, index * GET_MODE_SIZE (mode)));
2490 /* Print a memory address as an operand to reference that memory location. */
2492 frv_print_operand_address (FILE * stream, rtx x)
2494 if (GET_CODE (x) == MEM)
2497 switch (GET_CODE (x))
2500 fputs (reg_names [ REGNO (x)], stream);
2504 fprintf (stream, "%ld", (long) INTVAL (x));
2508 assemble_name (stream, XSTR (x, 0));
2513 output_addr_const (stream, x);
2520 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2525 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2527 int regno = true_regnum (x);
2529 fputs (reg_names[regno], stream);
2531 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2534 /* Print a memory reference suitable for the ld/st instructions. */
2537 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2539 struct frv_unspec unspec;
2543 switch (GET_CODE (x))
2550 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2552 x1 = XEXP (XEXP (x, 1), 1);
2562 if (GET_CODE (x0) == CONST_INT)
2570 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2579 else if (GET_CODE (x1) != CONST_INT)
2580 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2583 fputs ("@(", stream);
2585 fputs (reg_names[GPR_R0], stream);
2586 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2587 frv_print_operand_memory_reference_reg (stream, x0);
2589 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2591 fputs (",", stream);
2593 fputs (reg_names [GPR_R0], stream);
2597 switch (GET_CODE (x1))
2601 frv_print_operand_memory_reference_reg (stream, x1);
2605 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2609 if (!frv_const_unspec_p (x1, &unspec))
2610 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2611 frv_output_const_unspec (stream, &unspec);
2615 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2619 fputs (")", stream);
2623 /* Return 2 for likely branches and 0 for non-likely branches */
2625 #define FRV_JUMP_LIKELY 2
2626 #define FRV_JUMP_NOT_LIKELY 0
2629 frv_print_operand_jump_hint (rtx insn)
2634 HOST_WIDE_INT prob = -1;
2635 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2637 if (GET_CODE (insn) != JUMP_INSN)
2640 /* Assume any non-conditional jump is likely. */
2641 if (! any_condjump_p (insn))
2642 ret = FRV_JUMP_LIKELY;
2646 labelref = condjump_label (insn);
2649 rtx label = XEXP (labelref, 0);
2650 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2655 note = find_reg_note (insn, REG_BR_PROB, 0);
2657 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2661 prob = INTVAL (XEXP (note, 0));
2662 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2664 : FRV_JUMP_NOT_LIKELY);
2676 case UNKNOWN: direction = "unknown jump direction"; break;
2677 case BACKWARD: direction = "jump backward"; break;
2678 case FORWARD: direction = "jump forward"; break;
2682 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2683 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2684 (long)INSN_UID (insn), direction, (long)prob,
2685 (long)REG_BR_PROB_BASE, ret);
2693 /* Return the comparison operator to use for CODE given that the ICC
2697 comparison_string (enum rtx_code code, rtx op0)
2699 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2702 default: output_operand_lossage ("bad condition code");
2703 case EQ: return "eq";
2704 case NE: return "ne";
2705 case LT: return is_nz_p ? "n" : "lt";
2706 case LE: return "le";
2707 case GT: return "gt";
2708 case GE: return is_nz_p ? "p" : "ge";
2709 case LTU: return is_nz_p ? "no" : "c";
2710 case LEU: return is_nz_p ? "eq" : "ls";
2711 case GTU: return is_nz_p ? "ne" : "hi";
2712 case GEU: return is_nz_p ? "ra" : "nc";
2716 /* Print an operand to an assembler instruction.
2718 `%' followed by a letter and a digit says to output an operand in an
2719 alternate fashion. Four letters have standard, built-in meanings described
2720 below. The machine description macro `PRINT_OPERAND' can define additional
2721 letters with nonstandard meanings.
2723 `%cDIGIT' can be used to substitute an operand that is a constant value
2724 without the syntax that normally indicates an immediate operand.
2726 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2729 `%aDIGIT' can be used to substitute an operand as if it were a memory
2730 reference, with the actual operand treated as the address. This may be
2731 useful when outputting a "load address" instruction, because often the
2732 assembler syntax for such an instruction requires you to write the operand
2733 as if it were a memory reference.
2735 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2737 `%=' outputs a number which is unique to each instruction in the entire
2738 compilation. This is useful for making local labels to be referred to more
2739 than once in a single template that generates multiple assembler
2742 `%' followed by a punctuation character specifies a substitution that does
2743 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2744 assembler code. Other nonstandard cases can be defined in the
2745 `PRINT_OPERAND' macro. You must also define which punctuation characters
2746 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2749 frv_print_operand (FILE * file, rtx x, int code)
2751 struct frv_unspec unspec;
2752 HOST_WIDE_INT value;
2755 if (code != 0 && !isalpha (code))
2758 else if (GET_CODE (x) == CONST_INT)
2761 else if (GET_CODE (x) == CONST_DOUBLE)
2763 if (GET_MODE (x) == SFmode)
2768 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2769 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2773 else if (GET_MODE (x) == VOIDmode)
2774 value = CONST_DOUBLE_LOW (x);
2777 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2788 fputs (reg_names[GPR_R0], file);
2792 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2796 /* Output small data area base register (gr16). */
2797 fputs (reg_names[SDA_BASE_REG], file);
2801 /* Output pic register (gr17). */
2802 fputs (reg_names[PIC_REGNO], file);
2806 /* Output the temporary integer CCR register. */
2807 fputs (reg_names[ICR_TEMP], file);
2811 /* Output the temporary integer CC register. */
2812 fputs (reg_names[ICC_TEMP], file);
2815 /* case 'a': print an address. */
2818 /* Print appropriate test for integer branch false operation. */
2819 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2820 XEXP (x, 0)), file);
2824 /* Print appropriate test for integer branch true operation. */
2825 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2829 /* Print 1 for a NE and 0 for an EQ to give the final argument
2830 for a conditional instruction. */
2831 if (GET_CODE (x) == NE)
2834 else if (GET_CODE (x) == EQ)
2838 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2842 /* Print appropriate test for floating point branch false operation. */
2843 switch (GET_CODE (x))
2846 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2848 case EQ: fputs ("ne", file); break;
2849 case NE: fputs ("eq", file); break;
2850 case LT: fputs ("uge", file); break;
2851 case LE: fputs ("ug", file); break;
2852 case GT: fputs ("ule", file); break;
2853 case GE: fputs ("ul", file); break;
2858 /* Print appropriate test for floating point branch true operation. */
2859 switch (GET_CODE (x))
2862 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2864 case EQ: fputs ("eq", file); break;
2865 case NE: fputs ("ne", file); break;
2866 case LT: fputs ("lt", file); break;
2867 case LE: fputs ("le", file); break;
2868 case GT: fputs ("gt", file); break;
2869 case GE: fputs ("ge", file); break;
2874 /* Print appropriate GOT function. */
2875 if (GET_CODE (x) != CONST_INT)
2876 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2877 fputs (unspec_got_name (INTVAL (x)), file);
2881 /* Print 'i' if the operand is a constant, or is a memory reference that
2883 if (GET_CODE (x) == MEM)
2884 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2885 ? XEXP (XEXP (x, 0), 1)
2887 else if (GET_CODE (x) == PLUS)
2890 switch (GET_CODE (x))
2904 /* For jump instructions, print 'i' if the operand is a constant or
2905 is an expression that adds a constant. */
2906 if (GET_CODE (x) == CONST_INT)
2911 if (GET_CODE (x) == CONST_INT
2912 || (GET_CODE (x) == PLUS
2913 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2914 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2920 /* Print the lower register of a double word register pair */
2921 if (GET_CODE (x) == REG)
2922 fputs (reg_names[ REGNO (x)+1 ], file);
2924 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2927 /* case 'l': print a LABEL_REF. */
2931 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2932 for the second word of double memory operations. */
2933 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2934 switch (GET_CODE (x))
2937 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2940 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2948 frv_print_operand_memory_reference (file, x, offset);
2954 /* Print the opcode of a command. */
2955 switch (GET_CODE (x))
2958 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2960 case PLUS: fputs ("add", file); break;
2961 case MINUS: fputs ("sub", file); break;
2962 case AND: fputs ("and", file); break;
2963 case IOR: fputs ("or", file); break;
2964 case XOR: fputs ("xor", file); break;
2965 case ASHIFT: fputs ("sll", file); break;
2966 case ASHIFTRT: fputs ("sra", file); break;
2967 case LSHIFTRT: fputs ("srl", file); break;
2971 /* case 'n': negate and print a constant int. */
2974 /* Print PIC label using operand as the number. */
2975 if (GET_CODE (x) != CONST_INT)
2976 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2978 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2982 /* Print 'u' if the operand is a update load/store. */
2983 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2988 /* If value is 0, print gr0, otherwise it must be a register. */
2989 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2990 fputs (reg_names[GPR_R0], file);
2992 else if (GET_CODE (x) == REG)
2993 fputs (reg_names [REGNO (x)], file);
2996 fatal_insn ("Bad insn in frv_print_operand, z case", x);
3000 /* Print constant in hex. */
3001 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3003 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3010 if (GET_CODE (x) == REG)
3011 fputs (reg_names [REGNO (x)], file);
3013 else if (GET_CODE (x) == CONST_INT
3014 || GET_CODE (x) == CONST_DOUBLE)
3015 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3017 else if (frv_const_unspec_p (x, &unspec))
3018 frv_output_const_unspec (file, &unspec);
3020 else if (GET_CODE (x) == MEM)
3021 frv_print_operand_address (file, XEXP (x, 0));
3023 else if (CONSTANT_ADDRESS_P (x))
3024 frv_print_operand_address (file, x);
3027 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3032 fatal_insn ("frv_print_operand: unknown code", x);
3040 /* A C statement (sans semicolon) for initializing the variable CUM for the
3041 state at the beginning of the argument list. The variable has type
3042 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3043 of the function which will receive the args, or 0 if the args are to a
3044 compiler support library function. The value of INDIRECT is nonzero when
3045 processing an indirect call, for example a call through a function pointer.
3046 The value of INDIRECT is zero for a call to an explicitly named function, a
3047 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3048 arguments for the function being compiled.
3050 When processing a call to a compiler support library function, LIBNAME
3051 identifies which one. It is a `symbol_ref' rtx which contains the name of
3052 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3053 being processed. Thus, each time this macro is called, either LIBNAME or
3054 FNTYPE is nonzero, but never both of them at once. */
3057 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3063 *cum = FIRST_ARG_REGNUM;
3065 if (TARGET_DEBUG_ARG)
3067 fprintf (stderr, "\ninit_cumulative_args:");
3068 if (!fndecl && fntype)
3069 fputs (" indirect", stderr);
3072 fputs (" incoming", stderr);
3076 tree ret_type = TREE_TYPE (fntype);
3077 fprintf (stderr, " return=%s,",
3078 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3081 if (libname && GET_CODE (libname) == SYMBOL_REF)
3082 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3084 if (cfun->returns_struct)
3085 fprintf (stderr, " return-struct");
3087 putc ('\n', stderr);
3092 /* Return true if we should pass an argument on the stack rather than
3096 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3098 if (mode == BLKmode)
3102 return AGGREGATE_TYPE_P (type);
3105 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3106 argument with the specified mode and type. If it is not defined,
3107 `PARM_BOUNDARY' is used for all arguments. */
3110 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3111 tree type ATTRIBUTE_UNUSED)
3113 return BITS_PER_WORD;
3117 frv_function_arg (CUMULATIVE_ARGS *cum,
3118 enum machine_mode mode,
3119 tree type ATTRIBUTE_UNUSED,
3121 int incoming ATTRIBUTE_UNUSED)
3123 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3128 /* Return a marker for use in the call instruction. */
3129 if (xmode == VOIDmode)
3135 else if (arg_num <= LAST_ARG_REGNUM)
3137 ret = gen_rtx_REG (xmode, arg_num);
3138 debstr = reg_names[arg_num];
3147 if (TARGET_DEBUG_ARG)
3149 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3150 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3156 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3157 advance past an argument in the argument list. The values MODE, TYPE and
3158 NAMED describe that argument. Once this is done, the variable CUM is
3159 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3161 This macro need not do anything if the argument in question was passed on
3162 the stack. The compiler knows how to track the amount of stack space used
3163 for arguments without any special help. */
3166 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3167 enum machine_mode mode,
3168 tree type ATTRIBUTE_UNUSED,
3171 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3172 int bytes = GET_MODE_SIZE (xmode);
3173 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3176 *cum = arg_num + words;
3178 if (TARGET_DEBUG_ARG)
3180 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3181 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3185 /* A C expression for the number of words, at the beginning of an argument,
3186 must be put in registers. The value must be zero for arguments that are
3187 passed entirely in registers or that are entirely pushed on the stack.
3189 On some machines, certain arguments must be passed partially in registers
3190 and partially in memory. On these machines, typically the first N words of
3191 arguments are passed in registers, and the rest on the stack. If a
3192 multi-word argument (a `double' or a structure) crosses that boundary, its
3193 first few words must be passed in registers and the rest must be pushed.
3194 This macro tells the compiler when this occurs, and how many of the words
3195 should go in registers.
3197 `FUNCTION_ARG' for these arguments should return the first register to be
3198 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3199 the called function. */
3202 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3203 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3205 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3206 int bytes = GET_MODE_SIZE (xmode);
3207 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3211 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3212 ? LAST_ARG_REGNUM - arg_num + 1
3214 ret *= UNITS_PER_WORD;
3216 if (TARGET_DEBUG_ARG && ret)
3217 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3223 /* Return true if a register is ok to use as a base or index register. */
3225 static FRV_INLINE int
3226 frv_regno_ok_for_base_p (int regno, int strict_p)
3232 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3234 if (regno == ARG_POINTER_REGNUM)
3237 return (regno >= FIRST_PSEUDO_REGISTER);
3241 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3242 RTX) is a legitimate memory address on the target machine for a memory
3243 operand of mode MODE.
3245 It usually pays to define several simpler macros to serve as subroutines for
3246 this one. Otherwise it may be too complicated to understand.
3248 This macro must exist in two variants: a strict variant and a non-strict
3249 one. The strict variant is used in the reload pass. It must be defined so
3250 that any pseudo-register that has not been allocated a hard register is
3251 considered a memory reference. In contexts where some kind of register is
3252 required, a pseudo-register with no hard register must be rejected.
3254 The non-strict variant is used in other passes. It must be defined to
3255 accept all pseudo-registers in every context where some kind of register is
3258 Compiler source files that want to use the strict variant of this macro
3259 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3260 conditional to define the strict variant in that case and the non-strict
3263 Subroutines to check for acceptable registers for various purposes (one for
3264 base registers, one for index registers, and so on) are typically among the
3265 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3266 subroutine macros need have two variants; the higher levels of macros may be
3267 the same whether strict or not.
3269 Normally, constant addresses which are the sum of a `symbol_ref' and an
3270 integer are stored inside a `const' RTX to mark them as constant.
3271 Therefore, there is no need to recognize such sums specifically as
3272 legitimate addresses. Normally you would simply recognize any `const' as
3275 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3276 are not marked with `const'. It assumes that a naked `plus' indicates
3277 indexing. If so, then you *must* reject such naked constant sums as
3278 illegitimate addresses, so that none of them will be given to
3279 `PRINT_OPERAND_ADDRESS'.
3281 On some machines, whether a symbolic address is legitimate depends on the
3282 section that the address refers to. On these machines, define the macro
3283 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3284 then check for it here. When you see a `const', you will have to look
3285 inside it to find the `symbol_ref' in order to determine the section.
3287 The best way to modify the name string is by adding text to the beginning,
3288 with suitable punctuation to prevent any ambiguity. Allocate the new name
3289 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3290 remove and decode the added text and output the name accordingly, and define
3291 `(* targetm.strip_name_encoding)' to access the original name string.
3293 You can check the information stored here into the `symbol_ref' in the
3294 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3295 `PRINT_OPERAND_ADDRESS'. */
3298 frv_legitimate_address_p (enum machine_mode mode,
3302 int allow_double_reg_p)
3306 HOST_WIDE_INT value;
3309 if (FRV_SYMBOL_REF_TLS_P (x))
3312 switch (GET_CODE (x))
3319 if (GET_CODE (x) != REG)
3325 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3331 if (GET_CODE (x0) != REG
3332 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3333 || GET_CODE (x1) != PLUS
3334 || ! rtx_equal_p (x0, XEXP (x1, 0))
3335 || GET_CODE (XEXP (x1, 1)) != REG
3336 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3343 /* 12 bit immediate */
3348 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3350 /* If we can't use load/store double operations, make sure we can
3351 address the second word. */
3352 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3353 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3362 if (GET_CODE (x0) == SUBREG)
3363 x0 = SUBREG_REG (x0);
3365 if (GET_CODE (x0) != REG)
3368 regno0 = REGNO (x0);
3369 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3372 switch (GET_CODE (x1))
3378 x1 = SUBREG_REG (x1);
3379 if (GET_CODE (x1) != REG)
3385 /* Do not allow reg+reg addressing for modes > 1 word if we
3386 can't depend on having move double instructions. */
3387 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3390 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3394 /* 12 bit immediate */
3399 value = INTVAL (x1);
3400 ret = IN_RANGE_P (value, -2048, 2047);
3402 /* If we can't use load/store double operations, make sure we can
3403 address the second word. */
3404 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3405 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3410 if (!condexec_p && got12_operand (x1, VOIDmode))
3418 if (TARGET_DEBUG_ADDR)
3420 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3421 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3422 (condexec_p) ? ", inside conditional code" : "");
3429 /* Given an ADDR, generate code to inline the PLT. */
3431 gen_inlined_tls_plt (rtx addr)
3433 rtx mem, retval, dest;
3434 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3437 dest = gen_reg_rtx (DImode);
3444 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3445 calll #gettlsoff(ADDR)@(gr8, gr0)
3447 emit_insn (gen_tls_lddi (dest, addr, picreg));
3454 sethi.p #gottlsdeschi(ADDR), gr8
3455 setlo #gottlsdesclo(ADDR), gr8
3456 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3457 calll #gettlsoff(ADDR)@(gr8, gr0)
3459 rtx reguse = gen_reg_rtx (Pmode);
3460 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3461 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3464 retval = gen_reg_rtx (Pmode);
3465 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3469 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3470 the destination address. */
3472 gen_tlsmoff (rtx addr, rtx reg)
3474 rtx dest = gen_reg_rtx (Pmode);
3478 /* sethi.p #tlsmoffhi(x), grA
3479 setlo #tlsmofflo(x), grA
3481 dest = gen_reg_rtx (Pmode);
3482 emit_insn (gen_tlsoff_hilo (dest, addr,
3483 GEN_INT (R_FRV_TLSMOFFHI)));
3484 dest = gen_rtx_PLUS (Pmode, dest, reg);
3488 /* addi grB, #tlsmoff12(x), grC
3490 ld/st @(grB, #tlsmoff12(x)), grC
3492 dest = gen_reg_rtx (Pmode);
3493 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3494 GEN_INT (R_FRV_TLSMOFF12)));
3499 /* Generate code for a TLS address. */
3501 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3503 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3504 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3508 case TLS_MODEL_INITIAL_EXEC:
3512 ldi @(gr15, #gottlsoff12(x)), gr5
3514 dest = gen_reg_rtx (Pmode);
3515 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3516 dest = gen_rtx_PLUS (Pmode, tp, dest);
3520 /* -fPIC or anything else.
3522 sethi.p #gottlsoffhi(x), gr14
3523 setlo #gottlsofflo(x), gr14
3524 ld #tlsoff(x)@(gr15, gr14), gr9
3526 rtx tmp = gen_reg_rtx (Pmode);
3527 dest = gen_reg_rtx (Pmode);
3528 emit_insn (gen_tlsoff_hilo (tmp, addr,
3529 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3531 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3532 dest = gen_rtx_PLUS (Pmode, tp, dest);
3535 case TLS_MODEL_LOCAL_DYNAMIC:
3539 if (TARGET_INLINE_PLT)
3540 retval = gen_inlined_tls_plt (GEN_INT (0));
3543 /* call #gettlsoff(0) */
3544 retval = gen_reg_rtx (Pmode);
3545 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3548 reg = gen_reg_rtx (Pmode);
3549 emit_insn (gen_rtx_SET (VOIDmode, reg,
3550 gen_rtx_PLUS (Pmode,
3553 dest = gen_tlsmoff (addr, reg);
3556 dest = gen_reg_rtx (Pmode);
3557 emit_insn (gen_tlsoff_hilo (dest, addr,
3558 GEN_INT (R_FRV_TLSMOFFHI)));
3559 dest = gen_rtx_PLUS (Pmode, dest, reg);
3563 case TLS_MODEL_LOCAL_EXEC:
3564 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3566 case TLS_MODEL_GLOBAL_DYNAMIC:
3570 if (TARGET_INLINE_PLT)
3571 retval = gen_inlined_tls_plt (addr);
3574 /* call #gettlsoff(x) */
3575 retval = gen_reg_rtx (Pmode);
3576 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3578 dest = gen_rtx_PLUS (Pmode, retval, tp);
3589 frv_legitimize_address (rtx x,
3590 rtx oldx ATTRIBUTE_UNUSED,
3591 enum machine_mode mode ATTRIBUTE_UNUSED)
3593 if (GET_CODE (x) == SYMBOL_REF)
3595 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3597 return frv_legitimize_tls_address (x, model);
3603 /* Test whether a local function descriptor is canonical, i.e.,
3604 whether we can use FUNCDESC_GOTOFF to compute the address of the
3608 frv_local_funcdesc_p (rtx fnx)
3611 enum symbol_visibility vis;
3614 if (! SYMBOL_REF_LOCAL_P (fnx))
3617 fn = SYMBOL_REF_DECL (fnx);
3622 vis = DECL_VISIBILITY (fn);
3624 if (vis == VISIBILITY_PROTECTED)
3625 /* Private function descriptors for protected functions are not
3626 canonical. Temporarily change the visibility to global. */
3627 vis = VISIBILITY_DEFAULT;
3628 else if (flag_shlib)
3629 /* If we're already compiling for a shared library (that, unlike
3630 executables, can't assume that the existence of a definition
3631 implies local binding), we can skip the re-testing. */
3634 ret = default_binds_local_p_1 (fn, flag_pic);
3636 DECL_VISIBILITY (fn) = vis;
3641 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3645 frv_gen_GPsym2reg (rtx dest, rtx src)
3647 tree gp = get_identifier ("_gp");
3648 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3650 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3654 unspec_got_name (int i)
3658 case R_FRV_GOT12: return "got12";
3659 case R_FRV_GOTHI: return "gothi";
3660 case R_FRV_GOTLO: return "gotlo";
3661 case R_FRV_FUNCDESC: return "funcdesc";
3662 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3663 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3664 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3665 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3666 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3667 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3668 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3669 case R_FRV_GOTOFF12: return "gotoff12";
3670 case R_FRV_GOTOFFHI: return "gotoffhi";
3671 case R_FRV_GOTOFFLO: return "gotofflo";
3672 case R_FRV_GPREL12: return "gprel12";
3673 case R_FRV_GPRELHI: return "gprelhi";
3674 case R_FRV_GPRELLO: return "gprello";
3675 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3676 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3677 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3678 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3679 case R_FRV_TLSMOFF12: return "tlsmoff12";
3680 case R_FRV_TLSDESCHI: return "tlsdeschi";
3681 case R_FRV_TLSDESCLO: return "tlsdesclo";
3682 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3683 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3688 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3689 is added inside the relocation operator. */
3692 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3694 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3695 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3696 fputs (")", stream);
3699 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3700 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3701 otherwise return ORIG_X. */
3704 frv_find_base_term (rtx x)
3706 struct frv_unspec unspec;
3708 if (frv_const_unspec_p (x, &unspec)
3709 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3710 return plus_constant (unspec.symbol, unspec.offset);
3715 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3716 the operand is used by a predicated instruction. */
3719 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3721 return ((GET_MODE (op) == mode || mode == VOIDmode)
3722 && GET_CODE (op) == MEM
3723 && frv_legitimate_address_p (mode, XEXP (op, 0),
3724 reload_completed, condexec_p, FALSE));
3728 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3730 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3731 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3737 rvrtx = operands[0];
3741 addr = XEXP (operands[0], 0);
3743 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3744 any calls that would involve a PLT, but can't tell, since we
3745 don't know whether an extern function is going to be provided by
3746 a separate translation unit or imported from a separate module.
3747 When compiling for shared libraries, if the function has default
3748 visibility, we assume it's overridable, so we inline the PLT, but
3749 for executables, we don't really have a way to make a good
3750 decision: a function is as likely to be imported from a shared
3751 library as it is to be defined in the executable itself. We
3752 assume executables will get global functions defined locally,
3753 whereas shared libraries will have them potentially overridden,
3754 so we only inline PLTs when compiling for shared libraries.
3756 In order to mark a function as local to a shared library, any
3757 non-default visibility attribute suffices. Unfortunately,
3758 there's no simple way to tag a function declaration as ``in a
3759 different module'', which we could then use to trigger PLT
3760 inlining on executables. There's -minline-plt, but it affects
3761 all external functions, so one would have to also mark function
3762 declarations available in the same module with non-default
3763 visibility, which is advantageous in itself. */
3764 if (GET_CODE (addr) == SYMBOL_REF
3765 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3769 dest = gen_reg_rtx (SImode);
3771 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3772 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3774 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3775 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3777 cfun->uses_pic_offset_table = TRUE;
3780 else if (GET_CODE (addr) == SYMBOL_REF)
3782 /* These are always either local, or handled through a local
3785 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3786 operands[2], picreg, lr);
3788 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3792 else if (! ldd_address_operand (addr, Pmode))
3793 addr = force_reg (Pmode, addr);
3795 picreg = gen_reg_rtx (DImode);
3796 emit_insn (gen_movdi_ldd (picreg, addr));
3798 if (sibcall && ret_value)
3799 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3801 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3803 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3805 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3809 /* An address operand that may use a pair of registers, an addressing
3810 mode that we reject in general. */
3813 ldd_address_operand (rtx x, enum machine_mode mode)
3815 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3818 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3822 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3824 if (GET_MODE (op) != mode && mode != VOIDmode)
3826 if (GET_CODE (op) != REG)
3828 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3833 /* Return 1 is OP is a memory operand, or will be turned into one by
3837 frv_load_operand (rtx op, enum machine_mode mode)
3839 if (GET_MODE (op) != mode && mode != VOIDmode)
3842 if (reload_in_progress)
3845 if (GET_CODE (tmp) == SUBREG)
3846 tmp = SUBREG_REG (tmp);
3847 if (GET_CODE (tmp) == REG
3848 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3849 op = reg_equiv_memory_loc[REGNO (tmp)];
3852 return op && memory_operand (op, mode);
3856 /* Return 1 if operand is a GPR register or a FPR register. */
3859 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3863 if (GET_MODE (op) != mode && mode != VOIDmode)
3866 if (GET_CODE (op) == SUBREG)
3868 if (GET_CODE (SUBREG_REG (op)) != REG)
3869 return register_operand (op, mode);
3871 op = SUBREG_REG (op);
3874 if (GET_CODE (op) != REG)
3878 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3884 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3887 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3889 if (GET_CODE (op) == CONST_INT)
3890 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3892 if (got12_operand (op, mode))
3895 if (GET_MODE (op) != mode && mode != VOIDmode)
3898 if (GET_CODE (op) == SUBREG)
3900 if (GET_CODE (SUBREG_REG (op)) != REG)
3901 return register_operand (op, mode);
3903 op = SUBREG_REG (op);
3906 if (GET_CODE (op) != REG)
3909 return GPR_OR_PSEUDO_P (REGNO (op));
3912 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3913 signed immediate. */
3916 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3920 if (GET_CODE (op) == CONST_INT)
3921 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3923 if (GET_MODE (op) != mode && mode != VOIDmode)
3926 if (GET_CODE (op) == SUBREG)
3928 if (GET_CODE (SUBREG_REG (op)) != REG)
3929 return register_operand (op, mode);
3931 op = SUBREG_REG (op);
3934 if (GET_CODE (op) != REG)
3938 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3944 /* Return 1 if operand is a register or 6 bit signed immediate. */
3947 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3949 if (GET_CODE (op) == CONST_INT)
3950 return IN_RANGE_P (INTVAL (op), -32, 31);
3952 if (GET_MODE (op) != mode && mode != VOIDmode)
3955 if (GET_CODE (op) == SUBREG)
3957 if (GET_CODE (SUBREG_REG (op)) != REG)
3958 return register_operand (op, mode);
3960 op = SUBREG_REG (op);
3963 if (GET_CODE (op) != REG)
3966 return FPR_OR_PSEUDO_P (REGNO (op));
3969 /* Return 1 if operand is a register or 10 bit signed immediate. */
3972 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3974 if (GET_CODE (op) == CONST_INT)
3975 return IN_RANGE_P (INTVAL (op), -512, 511);
3977 if (GET_MODE (op) != mode && mode != VOIDmode)
3980 if (GET_CODE (op) == SUBREG)
3982 if (GET_CODE (SUBREG_REG (op)) != REG)
3983 return register_operand (op, mode);
3985 op = SUBREG_REG (op);
3988 if (GET_CODE (op) != REG)
3991 return GPR_OR_PSEUDO_P (REGNO (op));
3994 /* Return 1 if operand is a register or an integer immediate. */
3997 gpr_or_int_operand (rtx op, enum machine_mode mode)
3999 if (GET_CODE (op) == CONST_INT)
4002 if (GET_MODE (op) != mode && mode != VOIDmode)
4005 if (GET_CODE (op) == SUBREG)
4007 if (GET_CODE (SUBREG_REG (op)) != REG)
4008 return register_operand (op, mode);
4010 op = SUBREG_REG (op);
4013 if (GET_CODE (op) != REG)
4016 return GPR_OR_PSEUDO_P (REGNO (op));
4019 /* Return 1 if operand is a 12 bit signed immediate. */
4022 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4024 if (GET_CODE (op) != CONST_INT)
4027 return IN_RANGE_P (INTVAL (op), -2048, 2047);
4030 /* Return 1 if operand is a 6 bit signed immediate. */
4033 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4035 if (GET_CODE (op) != CONST_INT)
4038 return IN_RANGE_P (INTVAL (op), -32, 31);
4041 /* Return 1 if operand is a 5 bit signed immediate. */
4044 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4046 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
4049 /* Return 1 if operand is a 5 bit unsigned immediate. */
4052 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4054 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
4057 /* Return 1 if operand is a 4 bit unsigned immediate. */
4060 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4062 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
4065 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
4068 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4070 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
4073 /* Return 1 if operand is an integer constant that takes 2 instructions
4074 to load up and can be split into sethi/setlo instructions.. */
4077 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4079 HOST_WIDE_INT value;
4083 switch (GET_CODE (op))
4092 return (flag_pic == 0);
4095 if (flag_pic || TARGET_FDPIC)
4099 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
4101 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
4107 /* small data references are already 1 word */
4108 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
4111 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
4114 if (GET_MODE (op) == SFmode)
4116 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4117 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4119 return ! IN_RANGE_P (value, -32768, 32767);
4121 else if (GET_MODE (op) == VOIDmode)
4123 value = CONST_DOUBLE_LOW (op);
4124 return ! IN_RANGE_P (value, -32768, 32767);
4132 /* Return 1 if operand is a 16 bit unsigned immediate. */
4135 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4137 if (GET_CODE (op) != CONST_INT)
4140 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
4143 /* Return 1 if operand is an integer constant with the bottom 16 bits
4147 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4149 if (GET_CODE (op) != CONST_INT)
4152 return ((INTVAL (op) & 0xffff) == 0);
4155 /* Return true if operand is a GPR register. */
4158 integer_register_operand (rtx op, enum machine_mode mode)
4160 if (GET_MODE (op) != mode && mode != VOIDmode)
4163 if (GET_CODE (op) == SUBREG)
4165 if (GET_CODE (SUBREG_REG (op)) != REG)
4166 return register_operand (op, mode);
4168 op = SUBREG_REG (op);
4171 if (GET_CODE (op) != REG)
4174 return GPR_OR_PSEUDO_P (REGNO (op));
4177 /* Return true if operand is a GPR register. Do not allow SUBREG's
4178 here, in order to prevent a combine bug. */
4181 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
4183 if (GET_MODE (op) != mode && mode != VOIDmode)
4186 if (GET_CODE (op) != REG)
4189 return GPR_OR_PSEUDO_P (REGNO (op));
4192 /* Return true if operand is a FPR register. */
4195 fpr_operand (rtx op, enum machine_mode mode)
4197 if (GET_MODE (op) != mode && mode != VOIDmode)
4200 if (GET_CODE (op) == SUBREG)
4202 if (GET_CODE (SUBREG_REG (op)) != REG)
4203 return register_operand (op, mode);
4205 op = SUBREG_REG (op);
4208 if (GET_CODE (op) != REG)
4211 return FPR_OR_PSEUDO_P (REGNO (op));
4214 /* Return true if operand is an even GPR or FPR register. */
4217 even_reg_operand (rtx op, enum machine_mode mode)
4221 if (GET_MODE (op) != mode && mode != VOIDmode)
4224 if (GET_CODE (op) == SUBREG)
4226 if (GET_CODE (SUBREG_REG (op)) != REG)
4227 return register_operand (op, mode);
4229 op = SUBREG_REG (op);
4232 if (GET_CODE (op) != REG)
4236 if (regno >= FIRST_PSEUDO_REGISTER)
4240 return (((regno - GPR_FIRST) & 1) == 0);
4243 return (((regno - FPR_FIRST) & 1) == 0);
4248 /* Return true if operand is an odd GPR register. */
4251 odd_reg_operand (rtx op, enum machine_mode mode)
4255 if (GET_MODE (op) != mode && mode != VOIDmode)
4258 if (GET_CODE (op) == SUBREG)
4260 if (GET_CODE (SUBREG_REG (op)) != REG)
4261 return register_operand (op, mode);
4263 op = SUBREG_REG (op);
4266 if (GET_CODE (op) != REG)
4270 /* Assume that reload will give us an even register. */
4271 if (regno >= FIRST_PSEUDO_REGISTER)
4275 return (((regno - GPR_FIRST) & 1) != 0);
4278 return (((regno - FPR_FIRST) & 1) != 0);
4283 /* Return true if operand is an even GPR register. */
4286 even_gpr_operand (rtx op, enum machine_mode mode)
4290 if (GET_MODE (op) != mode && mode != VOIDmode)
4293 if (GET_CODE (op) == SUBREG)
4295 if (GET_CODE (SUBREG_REG (op)) != REG)
4296 return register_operand (op, mode);
4298 op = SUBREG_REG (op);
4301 if (GET_CODE (op) != REG)
4305 if (regno >= FIRST_PSEUDO_REGISTER)
4308 if (! GPR_P (regno))
4311 return (((regno - GPR_FIRST) & 1) == 0);
4314 /* Return true if operand is an odd GPR register. */
4317 odd_gpr_operand (rtx op, enum machine_mode mode)
4321 if (GET_MODE (op) != mode && mode != VOIDmode)
4324 if (GET_CODE (op) == SUBREG)
4326 if (GET_CODE (SUBREG_REG (op)) != REG)
4327 return register_operand (op, mode);
4329 op = SUBREG_REG (op);
4332 if (GET_CODE (op) != REG)
4336 /* Assume that reload will give us an even register. */
4337 if (regno >= FIRST_PSEUDO_REGISTER)
4340 if (! GPR_P (regno))
4343 return (((regno - GPR_FIRST) & 1) != 0);
4346 /* Return true if operand is a quad aligned FPR register. */
4349 quad_fpr_operand (rtx op, enum machine_mode mode)
4353 if (GET_MODE (op) != mode && mode != VOIDmode)
4356 if (GET_CODE (op) == SUBREG)
4358 if (GET_CODE (SUBREG_REG (op)) != REG)
4359 return register_operand (op, mode);
4361 op = SUBREG_REG (op);
4364 if (GET_CODE (op) != REG)
4368 if (regno >= FIRST_PSEUDO_REGISTER)
4371 if (! FPR_P (regno))
4374 return (((regno - FPR_FIRST) & 3) == 0);
4377 /* Return true if operand is an even FPR register. */
4380 even_fpr_operand (rtx op, enum machine_mode mode)
4384 if (GET_MODE (op) != mode && mode != VOIDmode)
4387 if (GET_CODE (op) == SUBREG)
4389 if (GET_CODE (SUBREG_REG (op)) != REG)
4390 return register_operand (op, mode);
4392 op = SUBREG_REG (op);
4395 if (GET_CODE (op) != REG)
4399 if (regno >= FIRST_PSEUDO_REGISTER)
4402 if (! FPR_P (regno))
4405 return (((regno - FPR_FIRST) & 1) == 0);
4408 /* Return true if operand is an odd FPR register. */
4411 odd_fpr_operand (rtx op, enum machine_mode mode)
4415 if (GET_MODE (op) != mode && mode != VOIDmode)
4418 if (GET_CODE (op) == SUBREG)
4420 if (GET_CODE (SUBREG_REG (op)) != REG)
4421 return register_operand (op, mode);
4423 op = SUBREG_REG (op);
4426 if (GET_CODE (op) != REG)
4430 /* Assume that reload will give us an even register. */
4431 if (regno >= FIRST_PSEUDO_REGISTER)
4434 if (! FPR_P (regno))
4437 return (((regno - FPR_FIRST) & 1) != 0);
4440 /* Return true if operand is a 2 word memory address that can be loaded in one
4441 instruction to load or store. We assume the stack and frame pointers are
4442 suitably aligned, and variables in the small data area. FIXME -- at some we
4443 should recognize other globals and statics. We can't assume that any old
4444 pointer is aligned, given that arguments could be passed on an odd word on
4445 the stack and the address taken and passed through to another function. */
4448 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4456 if (GET_CODE (op) != MEM)
4459 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4462 addr = XEXP (op, 0);
4463 if (GET_CODE (addr) == REG)
4466 else if (GET_CODE (addr) == PLUS)
4468 rtx addr0 = XEXP (addr, 0);
4469 rtx addr1 = XEXP (addr, 1);
4471 if (GET_CODE (addr0) != REG)
4474 if (got12_operand (addr1, VOIDmode))
4477 if (GET_CODE (addr1) != CONST_INT)
4480 if ((INTVAL (addr1) & 7) != 0)
4489 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4495 /* Return true if operand is a 2 word memory address that needs to
4496 use two instructions to load or store. */
4499 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4501 if (GET_CODE (op) != MEM)
4504 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4510 return ! dbl_memory_one_insn_operand (op, mode);
4513 /* Return true if operand is something that can be an output for a move
4517 move_destination_operand (rtx op, enum machine_mode mode)
4522 switch (GET_CODE (op))
4528 if (GET_MODE (op) != mode && mode != VOIDmode)
4531 subreg = SUBREG_REG (op);
4532 code = GET_CODE (subreg);
4534 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4535 reload_completed, FALSE, FALSE);
4537 return (code == REG);
4540 if (GET_MODE (op) != mode && mode != VOIDmode)
4546 return frv_legitimate_memory_operand (op, mode, FALSE);
4552 /* Return true if we the operand is a valid destination for a movcc_fp
4553 instruction. This means rejecting fcc_operands, since we need
4554 scratch registers to write to them. */
4557 movcc_fp_destination_operand (rtx op, enum machine_mode mode)
4559 if (fcc_operand (op, mode))
4562 return move_destination_operand (op, mode);
4565 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4566 process these separately from any offsets, such that we add any
4567 offsets to the function descriptor (the actual pointer), not to the
4568 function address. */
4571 frv_function_symbol_referenced_p (rtx x)
4577 if (GET_CODE (x) == SYMBOL_REF)
4578 return SYMBOL_REF_FUNCTION_P (x);
4580 length = GET_RTX_LENGTH (GET_CODE (x));
4581 format = GET_RTX_FORMAT (GET_CODE (x));
4583 for (j = 0; j < length; ++j)
4588 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4594 if (XVEC (x, j) != 0)
4597 for (k = 0; k < XVECLEN (x, j); ++k)
4598 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4604 /* Nothing to do. */
4612 /* Return true if operand is something that can be an input for a move
4616 move_source_operand (rtx op, enum machine_mode mode)
4621 switch (GET_CODE (op))
4628 return immediate_operand (op, mode);
4631 if (GET_MODE (op) != mode && mode != VOIDmode)
4634 subreg = SUBREG_REG (op);
4635 code = GET_CODE (subreg);
4637 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4638 reload_completed, FALSE, FALSE);
4640 return (code == REG);
4643 if (GET_MODE (op) != mode && mode != VOIDmode)
4649 return frv_legitimate_memory_operand (op, mode, FALSE);
4655 /* Return true if operand is something that can be an output for a conditional
4659 condexec_dest_operand (rtx op, enum machine_mode mode)
4664 switch (GET_CODE (op))
4670 if (GET_MODE (op) != mode && mode != VOIDmode)
4673 subreg = SUBREG_REG (op);
4674 code = GET_CODE (subreg);
4676 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4677 reload_completed, TRUE, FALSE);
4679 return (code == REG);
4682 if (GET_MODE (op) != mode && mode != VOIDmode)
4688 return frv_legitimate_memory_operand (op, mode, TRUE);
4694 /* Return true if operand is something that can be an input for a conditional
4698 condexec_source_operand (rtx op, enum machine_mode mode)
4703 switch (GET_CODE (op))
4713 if (GET_MODE (op) != mode && mode != VOIDmode)
4716 subreg = SUBREG_REG (op);
4717 code = GET_CODE (subreg);
4719 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4720 reload_completed, TRUE, FALSE);
4722 return (code == REG);
4725 if (GET_MODE (op) != mode && mode != VOIDmode)
4731 return frv_legitimate_memory_operand (op, mode, TRUE);
4737 /* Return true if operand is a register of any flavor or a 0 of the
4738 appropriate type. */
4741 reg_or_0_operand (rtx op, enum machine_mode mode)
4743 switch (GET_CODE (op))
4750 if (GET_MODE (op) != mode && mode != VOIDmode)
4753 return register_operand (op, mode);
4763 /* Return true if operand is the link register. */
4766 lr_operand (rtx op, enum machine_mode mode)
4768 if (GET_CODE (op) != REG)
4771 if (GET_MODE (op) != mode && mode != VOIDmode)
4774 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4780 /* Return true if operand is the uClinux PIC register. */
4783 fdpic_operand (rtx op, enum machine_mode mode)
4788 if (GET_CODE (op) != REG)
4791 if (GET_MODE (op) != mode && mode != VOIDmode)
4794 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4801 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4803 struct frv_unspec unspec;
4805 if (frv_const_unspec_p (op, &unspec))
4806 switch (unspec.reloc)
4809 case R_FRV_GOTOFF12:
4810 case R_FRV_FUNCDESC_GOT12:
4811 case R_FRV_FUNCDESC_GOTOFF12:
4813 case R_FRV_TLSMOFF12:
4819 /* Return true if OP is a valid const-unspec expression. */
4822 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4824 struct frv_unspec unspec;
4826 return frv_const_unspec_p (op, &unspec);
4829 /* Return true if operand is a gpr register or a valid memory operand. */
4832 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4834 return (integer_register_operand (op, mode)
4835 || frv_legitimate_memory_operand (op, mode, FALSE));
4838 /* Return true if operand is a gpr register, a valid memory operand,
4839 or a memory operand that can be made valid using an additional gpr
4843 gpr_or_memory_operand_with_scratch (rtx op, enum machine_mode mode)
4847 if (gpr_or_memory_operand (op, mode))
4850 if (GET_CODE (op) != MEM)
4853 if (GET_MODE (op) != mode)
4856 addr = XEXP (op, 0);
4858 if (GET_CODE (addr) != PLUS)
4861 if (!integer_register_operand (XEXP (addr, 0), Pmode))
4864 if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
4870 /* Return true if operand is a fpr register or a valid memory operation. */
4873 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4875 return (fpr_operand (op, mode)
4876 || frv_legitimate_memory_operand (op, mode, FALSE));
4879 /* Return true if operand is an icc register. */
4882 icc_operand (rtx op, enum machine_mode mode)
4886 if (GET_MODE (op) != mode && mode != VOIDmode)
4889 if (GET_CODE (op) != REG)
4893 return ICC_OR_PSEUDO_P (regno);
4896 /* Return true if operand is an fcc register. */
4899 fcc_operand (rtx op, enum machine_mode mode)
4903 if (GET_MODE (op) != mode && mode != VOIDmode)
4906 if (GET_CODE (op) != REG)
4910 return FCC_OR_PSEUDO_P (regno);
4913 /* Return true if operand is either an fcc or icc register. */
4916 cc_operand (rtx op, enum machine_mode mode)
4920 if (GET_MODE (op) != mode && mode != VOIDmode)
4923 if (GET_CODE (op) != REG)
4927 if (CC_OR_PSEUDO_P (regno))
4933 /* Return true if operand is an integer CCR register. */
4936 icr_operand (rtx op, enum machine_mode mode)
4940 if (GET_MODE (op) != mode && mode != VOIDmode)
4943 if (GET_CODE (op) != REG)
4947 return ICR_OR_PSEUDO_P (regno);
4950 /* Return true if operand is an fcc register. */
4953 fcr_operand (rtx op, enum machine_mode mode)
4957 if (GET_MODE (op) != mode && mode != VOIDmode)
4960 if (GET_CODE (op) != REG)
4964 return FCR_OR_PSEUDO_P (regno);
4967 /* Return true if operand is either an fcc or icc register. */
4970 cr_operand (rtx op, enum machine_mode mode)
4974 if (GET_MODE (op) != mode && mode != VOIDmode)
4977 if (GET_CODE (op) != REG)
4981 if (CR_OR_PSEUDO_P (regno))
4987 /* Return true if operand is a memory reference suitable for a call. */
4990 call_operand (rtx op, enum machine_mode mode)
4992 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4995 if (GET_CODE (op) == SYMBOL_REF)
4996 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
4998 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4999 never occur anyway), but prevents reload from not handling the case
5000 properly of a call through a pointer on a function that calls
5001 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
5002 return gpr_or_int12_operand (op, mode);
5005 /* Return true if operand is a memory reference suitable for a sibcall. */
5008 sibcall_operand (rtx op, enum machine_mode mode)
5010 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
5013 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
5014 never occur anyway), but prevents reload from not handling the case
5015 properly of a call through a pointer on a function that calls
5016 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
5017 return gpr_or_int12_operand (op, mode);
5020 /* Returns 1 if OP is either a SYMBOL_REF or a constant. */
5022 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5024 enum rtx_code c = GET_CODE (op);
5028 /* Allow (const:SI (plus:SI (symbol_ref) (const_int))). */
5029 return GET_MODE (op) == SImode
5030 && GET_CODE (XEXP (op, 0)) == PLUS
5031 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
5032 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
5035 return c == SYMBOL_REF || c == CONST_INT;
5038 /* Return true if operator is a kind of relational operator. */
5041 relational_operator (rtx op, enum machine_mode mode)
5043 return (integer_relational_operator (op, mode)
5044 || float_relational_operator (op, mode));
5047 /* Return true if OP is a relational operator suitable for CCmode,
5048 CC_UNSmode or CC_NZmode. */
5051 integer_relational_operator (rtx op, enum machine_mode mode)
5053 if (mode != VOIDmode && mode != GET_MODE (op))
5056 /* The allowable relations depend on the mode of the ICC register. */
5057 switch (GET_CODE (op))
5066 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
5067 || GET_MODE (XEXP (op, 0)) == CCmode);
5071 return GET_MODE (XEXP (op, 0)) == CCmode;
5077 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
5078 || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
5082 /* Return true if operator is a floating point relational operator. */
5085 float_relational_operator (rtx op, enum machine_mode mode)
5087 if (mode != VOIDmode && mode != GET_MODE (op))
5090 switch (GET_CODE (op))
5105 return GET_MODE (XEXP (op, 0)) == CC_FPmode;
5109 /* Return true if operator is EQ/NE of a conditional execution register. */
5112 ccr_eqne_operator (rtx op, enum machine_mode mode)
5114 enum machine_mode op_mode = GET_MODE (op);
5119 if (mode != VOIDmode && op_mode != mode)
5122 switch (GET_CODE (op))
5133 if (op1 != const0_rtx)
5137 if (GET_CODE (op0) != REG)
5140 regno = REGNO (op0);
5141 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
5147 /* Return true if operator is a minimum or maximum operator (both signed and
5151 minmax_operator (rtx op, enum machine_mode mode)
5153 if (mode != VOIDmode && mode != GET_MODE (op))
5156 switch (GET_CODE (op))
5168 if (! integer_register_operand (XEXP (op, 0), mode))
5171 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5177 /* Return true if operator is an integer binary operator that can executed
5178 conditionally and takes 1 cycle. */
5181 condexec_si_binary_operator (rtx op, enum machine_mode mode)
5183 enum machine_mode op_mode = GET_MODE (op);
5185 if (mode != VOIDmode && op_mode != mode)
5188 switch (GET_CODE (op))
5205 /* Return true if operator is an integer binary operator that can be
5206 executed conditionally by a media instruction. */
5209 condexec_si_media_operator (rtx op, enum machine_mode mode)
5211 enum machine_mode op_mode = GET_MODE (op);
5213 if (mode != VOIDmode && op_mode != mode)
5216 switch (GET_CODE (op))
5228 /* Return true if operator is an integer division operator that can executed
5232 condexec_si_divide_operator (rtx op, enum machine_mode mode)
5234 enum machine_mode op_mode = GET_MODE (op);
5236 if (mode != VOIDmode && op_mode != mode)
5239 switch (GET_CODE (op))
5250 /* Return true if operator is an integer unary operator that can executed
5254 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5256 enum machine_mode op_mode = GET_MODE (op);
5258 if (mode != VOIDmode && op_mode != mode)
5261 switch (GET_CODE (op))
5272 /* Return true if operator is a conversion-type expression that can be
5273 evaluated conditionally by floating-point instructions. */
5276 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5278 enum machine_mode op_mode = GET_MODE (op);
5280 if (mode != VOIDmode && op_mode != mode)
5283 switch (GET_CODE (op))
5294 /* Return true if operator is an addition or subtraction expression.
5295 Such expressions can be evaluated conditionally by floating-point
5299 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5301 enum machine_mode op_mode = GET_MODE (op);
5303 if (mode != VOIDmode && op_mode != mode)
5306 switch (GET_CODE (op))
5317 /* Return true if the memory operand is one that can be conditionally
5321 condexec_memory_operand (rtx op, enum machine_mode mode)
5323 enum machine_mode op_mode = GET_MODE (op);
5326 if (mode != VOIDmode && op_mode != mode)
5341 if (GET_CODE (op) != MEM)
5344 addr = XEXP (op, 0);
5345 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5348 /* Return true if OP is an integer binary operator that can be combined
5349 with a (set ... (compare:CC_NZ ...)) pattern. */
5352 intop_compare_operator (rtx op, enum machine_mode mode)
5354 if (mode != VOIDmode && GET_MODE (op) != mode)
5357 switch (GET_CODE (op))
5369 return GET_MODE (op) == SImode;
5373 /* Return 1 if operand is a valid ACC register number. */
5376 acc_operand (rtx op, enum machine_mode mode)
5378 return ((mode == VOIDmode || mode == GET_MODE (op))
5379 && REG_P (op) && ACC_P (REGNO (op))
5380 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
5383 /* Return 1 if operand is a valid even ACC register number. */
5386 even_acc_operand (rtx op, enum machine_mode mode)
5388 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
5391 /* Return 1 if operand is zero or four. */
5394 quad_acc_operand (rtx op, enum machine_mode mode)
5396 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
5399 /* Return 1 if operand is a valid ACCG register number. */
5402 accg_operand (rtx op, enum machine_mode mode)
5404 return ((mode == VOIDmode || mode == GET_MODE (op))
5405 && REG_P (op) && ACCG_P (REGNO (op))
5406 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
5410 /* Return true if the bare return instruction can be used outside of the
5411 epilog code. For frv, we only do it if there was no stack allocation. */
5414 direct_return_p (void)
5418 if (!reload_completed)
5421 info = frv_stack_info ();
5422 return (info->total_size == 0);
5427 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
5429 if (GET_CODE (src) == SYMBOL_REF)
5431 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
5433 src = frv_legitimize_tls_address (src, model);
5439 if (frv_emit_movsi (dest, src))
5448 if (!reload_in_progress
5449 && !reload_completed
5450 && !register_operand (dest, mode)
5451 && !reg_or_0_operand (src, mode))
5452 src = copy_to_mode_reg (mode, src);
5459 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
5462 /* Emit code to handle a MOVSI, adding in the small data register or pic
5463 register if needed to load up addresses. Return TRUE if the appropriate
5464 instructions are emitted. */
5467 frv_emit_movsi (rtx dest, rtx src)
5469 int base_regno = -1;
5472 struct frv_unspec old_unspec;
5474 if (!reload_in_progress
5475 && !reload_completed
5476 && !register_operand (dest, SImode)
5477 && (!reg_or_0_operand (src, SImode)
5478 /* Virtual registers will almost always be replaced by an
5479 add instruction, so expose this to CSE by copying to
5480 an intermediate register. */
5481 || (GET_CODE (src) == REG
5482 && IN_RANGE_P (REGNO (src),
5483 FIRST_VIRTUAL_REGISTER,
5484 LAST_VIRTUAL_REGISTER))))
5486 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5490 /* Explicitly add in the PIC or small data register if needed. */
5491 switch (GET_CODE (src))
5500 /* Using GPREL12, we use a single GOT entry for all symbols
5501 in read-only sections, but trade sequences such as:
5503 sethi #gothi(label), gr#
5504 setlo #gotlo(label), gr#
5509 ld @(gr15,#got12(_gp)), gr#
5510 sethi #gprelhi(label), gr##
5511 setlo #gprello(label), gr##
5514 We may often be able to share gr# for multiple
5515 computations of GPREL addresses, and we may often fold
5516 the final add into the pair of registers of a load or
5517 store instruction, so it's often profitable. Even when
5518 optimizing for size, we're trading a GOT entry for an
5519 additional instruction, which trades GOT space
5520 (read-write) for code size (read-only, shareable), as
5521 long as the symbol is not used in more than two different
5524 With -fpie/-fpic, we'd be trading a single load for a
5525 sequence of 4 instructions, because the offset of the
5526 label can't be assumed to be addressable with 12 bits, so
5527 we don't do this. */
5528 if (TARGET_GPREL_RO)
5529 unspec = R_FRV_GPREL12;
5531 unspec = R_FRV_GOT12;
5534 base_regno = PIC_REGNO;
5539 if (frv_const_unspec_p (src, &old_unspec))
5542 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5545 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5546 emit_move_insn (dest, src);
5551 sym = XEXP (sym, 0);
5552 if (GET_CODE (sym) == PLUS
5553 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5554 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5555 sym = XEXP (sym, 0);
5556 if (GET_CODE (sym) == SYMBOL_REF)
5558 else if (GET_CODE (sym) == LABEL_REF)
5561 goto handle_whatever;
5569 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
5573 src = frv_legitimize_tls_address (src, model);
5574 emit_move_insn (dest, src);
5578 if (SYMBOL_REF_FUNCTION_P (sym))
5580 if (frv_local_funcdesc_p (sym))
5581 unspec = R_FRV_FUNCDESC_GOTOFF12;
5583 unspec = R_FRV_FUNCDESC_GOT12;
5587 if (CONSTANT_POOL_ADDRESS_P (sym))
5588 switch (GET_CODE (get_pool_constant (sym)))
5595 unspec = R_FRV_GOTOFF12;
5600 if (TARGET_GPREL_RO)
5601 unspec = R_FRV_GPREL12;
5603 unspec = R_FRV_GOT12;
5606 else if (SYMBOL_REF_LOCAL_P (sym)
5607 && !SYMBOL_REF_EXTERNAL_P (sym)
5608 && SYMBOL_REF_DECL (sym)
5609 && (!DECL_P (SYMBOL_REF_DECL (sym))
5610 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5612 tree decl = SYMBOL_REF_DECL (sym);
5613 tree init = TREE_CODE (decl) == VAR_DECL
5614 ? DECL_INITIAL (decl)
5615 : TREE_CODE (decl) == CONSTRUCTOR
5618 bool named_section, readonly;
5620 if (init && init != error_mark_node)
5621 reloc = compute_reloc_for_constant (init);
5623 named_section = TREE_CODE (decl) == VAR_DECL
5624 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5625 readonly = decl_readonly_section (decl, reloc);
5628 unspec = R_FRV_GOT12;
5630 unspec = R_FRV_GOTOFF12;
5631 else if (readonly && TARGET_GPREL_RO)
5632 unspec = R_FRV_GPREL12;
5634 unspec = R_FRV_GOT12;
5637 unspec = R_FRV_GOT12;
5641 else if (SYMBOL_REF_SMALL_P (sym))
5642 base_regno = SDA_BASE_REG;
5645 base_regno = PIC_REGNO;
5650 if (base_regno >= 0)
5652 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5653 emit_insn (gen_symGOTOFF2reg (dest, src,
5654 gen_rtx_REG (Pmode, base_regno),
5655 GEN_INT (R_FRV_GPREL12)));
5657 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5658 gen_rtx_REG (Pmode, base_regno),
5659 GEN_INT (R_FRV_GPREL12)));
5660 if (base_regno == PIC_REGNO)
5661 cfun->uses_pic_offset_table = TRUE;
5669 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5670 new uses of it once reload has begun. */
5671 if (reload_in_progress || reload_completed)
5676 case R_FRV_GOTOFF12:
5677 if (!frv_small_data_reloc_p (sym, unspec))
5678 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5681 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5684 if (!frv_small_data_reloc_p (sym, unspec))
5685 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5688 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5690 case R_FRV_FUNCDESC_GOTOFF12:
5692 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5695 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5699 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5702 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5706 cfun->uses_pic_offset_table = TRUE;
5715 /* Return a string to output a single word move. */
5718 output_move_single (rtx operands[], rtx insn)
5720 rtx dest = operands[0];
5721 rtx src = operands[1];
5723 if (GET_CODE (dest) == REG)
5725 int dest_regno = REGNO (dest);
5726 enum machine_mode mode = GET_MODE (dest);
5728 if (GPR_P (dest_regno))
5730 if (GET_CODE (src) == REG)
5732 /* gpr <- some sort of register */
5733 int src_regno = REGNO (src);
5735 if (GPR_P (src_regno))
5736 return "mov %1, %0";
5738 else if (FPR_P (src_regno))
5739 return "movfg %1, %0";
5741 else if (SPR_P (src_regno))
5742 return "movsg %1, %0";
5745 else if (GET_CODE (src) == MEM)
5754 return "ldsb%I1%U1 %M1,%0";
5757 return "ldsh%I1%U1 %M1,%0";
5761 return "ld%I1%U1 %M1, %0";
5765 else if (GET_CODE (src) == CONST_INT
5766 || GET_CODE (src) == CONST_DOUBLE)
5768 /* gpr <- integer/floating constant */
5769 HOST_WIDE_INT value;
5771 if (GET_CODE (src) == CONST_INT)
5772 value = INTVAL (src);
5774 else if (mode == SFmode)
5779 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5780 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5785 value = CONST_DOUBLE_LOW (src);
5787 if (IN_RANGE_P (value, -32768, 32767))
5788 return "setlos %1, %0";
5793 else if (GET_CODE (src) == SYMBOL_REF
5794 || GET_CODE (src) == LABEL_REF
5795 || GET_CODE (src) == CONST)
5801 else if (FPR_P (dest_regno))
5803 if (GET_CODE (src) == REG)
5805 /* fpr <- some sort of register */
5806 int src_regno = REGNO (src);
5808 if (GPR_P (src_regno))
5809 return "movgf %1, %0";
5811 else if (FPR_P (src_regno))
5813 if (TARGET_HARD_FLOAT)
5814 return "fmovs %1, %0";
5816 return "mor %1, %1, %0";
5820 else if (GET_CODE (src) == MEM)
5829 return "ldbf%I1%U1 %M1,%0";
5832 return "ldhf%I1%U1 %M1,%0";
5836 return "ldf%I1%U1 %M1, %0";
5840 else if (ZERO_P (src))
5841 return "movgf %., %0";
5844 else if (SPR_P (dest_regno))
5846 if (GET_CODE (src) == REG)
5848 /* spr <- some sort of register */
5849 int src_regno = REGNO (src);
5851 if (GPR_P (src_regno))
5852 return "movgs %1, %0";
5854 else if (ZERO_P (src))
5855 return "movgs %., %0";
5859 else if (GET_CODE (dest) == MEM)
5861 if (GET_CODE (src) == REG)
5863 int src_regno = REGNO (src);
5864 enum machine_mode mode = GET_MODE (dest);
5866 if (GPR_P (src_regno))
5874 return "stb%I0%U0 %1, %M0";
5877 return "sth%I0%U0 %1, %M0";
5881 return "st%I0%U0 %1, %M0";
5885 else if (FPR_P (src_regno))
5893 return "stbf%I0%U0 %1, %M0";
5896 return "sthf%I0%U0 %1, %M0";
5900 return "stf%I0%U0 %1, %M0";
5905 else if (ZERO_P (src))
5907 switch (GET_MODE (dest))
5913 return "stb%I0%U0 %., %M0";
5916 return "sth%I0%U0 %., %M0";
5920 return "st%I0%U0 %., %M0";
5925 fatal_insn ("Bad output_move_single operand", insn);
5930 /* Return a string to output a double word move. */
5933 output_move_double (rtx operands[], rtx insn)
5935 rtx dest = operands[0];
5936 rtx src = operands[1];
5937 enum machine_mode mode = GET_MODE (dest);
5939 if (GET_CODE (dest) == REG)
5941 int dest_regno = REGNO (dest);
5943 if (GPR_P (dest_regno))
5945 if (GET_CODE (src) == REG)
5947 /* gpr <- some sort of register */
5948 int src_regno = REGNO (src);
5950 if (GPR_P (src_regno))
5953 else if (FPR_P (src_regno))
5955 if (((dest_regno - GPR_FIRST) & 1) == 0
5956 && ((src_regno - FPR_FIRST) & 1) == 0)
5957 return "movfgd %1, %0";
5963 else if (GET_CODE (src) == MEM)
5966 if (dbl_memory_one_insn_operand (src, mode))
5967 return "ldd%I1%U1 %M1, %0";
5972 else if (GET_CODE (src) == CONST_INT
5973 || GET_CODE (src) == CONST_DOUBLE)
5977 else if (FPR_P (dest_regno))
5979 if (GET_CODE (src) == REG)
5981 /* fpr <- some sort of register */
5982 int src_regno = REGNO (src);
5984 if (GPR_P (src_regno))
5986 if (((dest_regno - FPR_FIRST) & 1) == 0
5987 && ((src_regno - GPR_FIRST) & 1) == 0)
5988 return "movgfd %1, %0";
5993 else if (FPR_P (src_regno))
5996 && ((dest_regno - FPR_FIRST) & 1) == 0
5997 && ((src_regno - FPR_FIRST) & 1) == 0)
5998 return "fmovd %1, %0";
6004 else if (GET_CODE (src) == MEM)
6007 if (dbl_memory_one_insn_operand (src, mode))
6008 return "lddf%I1%U1 %M1, %0";
6013 else if (ZERO_P (src))
6018 else if (GET_CODE (dest) == MEM)
6020 if (GET_CODE (src) == REG)
6022 int src_regno = REGNO (src);
6024 if (GPR_P (src_regno))
6026 if (((src_regno - GPR_FIRST) & 1) == 0
6027 && dbl_memory_one_insn_operand (dest, mode))
6028 return "std%I0%U0 %1, %M0";
6033 if (FPR_P (src_regno))
6035 if (((src_regno - FPR_FIRST) & 1) == 0
6036 && dbl_memory_one_insn_operand (dest, mode))
6037 return "stdf%I0%U0 %1, %M0";
6043 else if (ZERO_P (src))
6045 if (dbl_memory_one_insn_operand (dest, mode))
6046 return "std%I0%U0 %., %M0";
6052 fatal_insn ("Bad output_move_double operand", insn);
6057 /* Return a string to output a single word conditional move.
6058 Operand0 -- EQ/NE of ccr register and 0
6059 Operand1 -- CCR register
6060 Operand2 -- destination
6061 Operand3 -- source */
6064 output_condmove_single (rtx operands[], rtx insn)
6066 rtx dest = operands[2];
6067 rtx src = operands[3];
6069 if (GET_CODE (dest) == REG)
6071 int dest_regno = REGNO (dest);
6072 enum machine_mode mode = GET_MODE (dest);
6074 if (GPR_P (dest_regno))
6076 if (GET_CODE (src) == REG)
6078 /* gpr <- some sort of register */
6079 int src_regno = REGNO (src);
6081 if (GPR_P (src_regno))
6082 return "cmov %z3, %2, %1, %e0";
6084 else if (FPR_P (src_regno))
6085 return "cmovfg %3, %2, %1, %e0";
6088 else if (GET_CODE (src) == MEM)
6097 return "cldsb%I3%U3 %M3, %2, %1, %e0";
6100 return "cldsh%I3%U3 %M3, %2, %1, %e0";
6104 return "cld%I3%U3 %M3, %2, %1, %e0";
6108 else if (ZERO_P (src))
6109 return "cmov %., %2, %1, %e0";
6112 else if (FPR_P (dest_regno))
6114 if (GET_CODE (src) == REG)
6116 /* fpr <- some sort of register */
6117 int src_regno = REGNO (src);
6119 if (GPR_P (src_regno))
6120 return "cmovgf %3, %2, %1, %e0";
6122 else if (FPR_P (src_regno))
6124 if (TARGET_HARD_FLOAT)
6125 return "cfmovs %3,%2,%1,%e0";
6127 return "cmor %3, %3, %2, %1, %e0";
6131 else if (GET_CODE (src) == MEM)
6134 if (mode == SImode || mode == SFmode)
6135 return "cldf%I3%U3 %M3, %2, %1, %e0";
6138 else if (ZERO_P (src))
6139 return "cmovgf %., %2, %1, %e0";
6143 else if (GET_CODE (dest) == MEM)
6145 if (GET_CODE (src) == REG)
6147 int src_regno = REGNO (src);
6148 enum machine_mode mode = GET_MODE (dest);
6150 if (GPR_P (src_regno))
6158 return "cstb%I2%U2 %3, %M2, %1, %e0";
6161 return "csth%I2%U2 %3, %M2, %1, %e0";
6165 return "cst%I2%U2 %3, %M2, %1, %e0";
6169 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
6170 return "cstf%I2%U2 %3, %M2, %1, %e0";
6173 else if (ZERO_P (src))
6175 enum machine_mode mode = GET_MODE (dest);
6182 return "cstb%I2%U2 %., %M2, %1, %e0";
6185 return "csth%I2%U2 %., %M2, %1, %e0";
6189 return "cst%I2%U2 %., %M2, %1, %e0";
6194 fatal_insn ("Bad output_condmove_single operand", insn);
6199 /* Emit the appropriate code to do a comparison, returning the register the
6200 comparison was done it. */
6203 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
6205 enum machine_mode cc_mode;
6208 /* Floating point doesn't have comparison against a constant. */
6209 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6210 op1 = force_reg (GET_MODE (op0), op1);
6212 /* Possibly disable using anything but a fixed register in order to work
6213 around cse moving comparisons past function calls. */
6214 cc_mode = SELECT_CC_MODE (test, op0, op1);
6215 cc_reg = ((TARGET_ALLOC_CC)
6216 ? gen_reg_rtx (cc_mode)
6217 : gen_rtx_REG (cc_mode,
6218 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6220 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6221 gen_rtx_COMPARE (cc_mode, op0, op1)));
6227 /* Emit code for a conditional branch. The comparison operands were previously
6228 stored in frv_compare_op0 and frv_compare_op1.
6230 XXX: I originally wanted to add a clobber of a CCR register to use in
6231 conditional execution, but that confuses the rest of the compiler. */
6234 frv_emit_cond_branch (enum rtx_code test, rtx label)
6239 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6240 enum machine_mode cc_mode = GET_MODE (cc_reg);
6242 /* Branches generate:
6244 (if_then_else (<test>, <cc_reg>, (const_int 0))
6245 (label_ref <branch_label>)
6247 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6248 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6249 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6250 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6255 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6256 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6259 frv_emit_scc (enum rtx_code test, rtx target)
6265 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6267 /* SCC instructions generate:
6268 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6269 (clobber (<ccr_reg>))]) */
6270 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6271 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6273 cr_reg = ((TARGET_ALLOC_CC)
6274 ? gen_reg_rtx (CC_CCRmode)
6275 : gen_rtx_REG (CC_CCRmode,
6276 ((GET_MODE (cc_reg) == CC_FPmode)
6280 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6281 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6286 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6287 the separate insns. */
6290 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6296 /* Set the appropriate CCR bit. */
6297 emit_insn (gen_rtx_SET (VOIDmode,
6299 gen_rtx_fmt_ee (GET_CODE (test),
6304 /* Move the value into the destination. */
6305 emit_move_insn (dest, GEN_INT (value));
6307 /* Move 0 into the destination if the test failed */
6308 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6309 gen_rtx_EQ (GET_MODE (cr_reg),
6312 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6314 /* Finish up, return sequence. */
6321 /* Emit the code for a conditional move, return TRUE if we could do the
6325 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6332 enum rtx_code test = GET_CODE (test_rtx);
6333 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6334 enum machine_mode cc_mode = GET_MODE (cc_reg);
6336 /* Conditional move instructions generate:
6337 (parallel [(set <target>
6338 (if_then_else (<test> <cc_reg> (const_int 0))
6341 (clobber (<ccr_reg>))]) */
6343 /* Handle various cases of conditional move involving two constants. */
6344 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6346 HOST_WIDE_INT value1 = INTVAL (src1);
6347 HOST_WIDE_INT value2 = INTVAL (src2);
6349 /* Having 0 as one of the constants can be done by loading the other
6350 constant, and optionally moving in gr0. */
6351 if (value1 == 0 || value2 == 0)
6354 /* If the first value is within an addi range and also the difference
6355 between the two fits in an addi's range, load up the difference, then
6356 conditionally move in 0, and then unconditionally add the first
6358 else if (IN_RANGE_P (value1, -2048, 2047)
6359 && IN_RANGE_P (value2 - value1, -2048, 2047))
6362 /* If neither condition holds, just force the constant into a
6366 src1 = force_reg (GET_MODE (dest), src1);
6367 src2 = force_reg (GET_MODE (dest), src2);
6371 /* If one value is a register, insure the other value is either 0 or a
6375 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6376 src1 = force_reg (GET_MODE (dest), src1);
6378 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6379 src2 = force_reg (GET_MODE (dest), src2);
6382 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6383 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6385 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6387 cr_reg = ((TARGET_ALLOC_CC)
6388 ? gen_reg_rtx (CC_CCRmode)
6389 : gen_rtx_REG (CC_CCRmode,
6390 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6392 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6393 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6398 /* Split a conditional move into constituent parts, returning a SEQUENCE
6399 containing all of the insns. */
6402 frv_split_cond_move (rtx operands[])
6404 rtx dest = operands[0];
6405 rtx test = operands[1];
6406 rtx cc_reg = operands[2];
6407 rtx src1 = operands[3];
6408 rtx src2 = operands[4];
6409 rtx cr_reg = operands[5];
6411 enum machine_mode cr_mode = GET_MODE (cr_reg);
6415 /* Set the appropriate CCR bit. */
6416 emit_insn (gen_rtx_SET (VOIDmode,
6418 gen_rtx_fmt_ee (GET_CODE (test),
6423 /* Handle various cases of conditional move involving two constants. */
6424 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6426 HOST_WIDE_INT value1 = INTVAL (src1);
6427 HOST_WIDE_INT value2 = INTVAL (src2);
6429 /* Having 0 as one of the constants can be done by loading the other
6430 constant, and optionally moving in gr0. */
6433 emit_move_insn (dest, src2);
6434 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6435 gen_rtx_NE (cr_mode, cr_reg,
6437 gen_rtx_SET (VOIDmode, dest, src1)));
6440 else if (value2 == 0)
6442 emit_move_insn (dest, src1);
6443 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6444 gen_rtx_EQ (cr_mode, cr_reg,
6446 gen_rtx_SET (VOIDmode, dest, src2)));
6449 /* If the first value is within an addi range and also the difference
6450 between the two fits in an addi's range, load up the difference, then
6451 conditionally move in 0, and then unconditionally add the first
6453 else if (IN_RANGE_P (value1, -2048, 2047)
6454 && IN_RANGE_P (value2 - value1, -2048, 2047))
6456 rtx dest_si = ((GET_MODE (dest) == SImode)
6458 : gen_rtx_SUBREG (SImode, dest, 0));
6460 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6461 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6462 gen_rtx_NE (cr_mode, cr_reg,
6464 gen_rtx_SET (VOIDmode, dest_si,
6466 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6474 /* Emit the conditional move for the test being true if needed. */
6475 if (! rtx_equal_p (dest, src1))
6476 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6477 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6478 gen_rtx_SET (VOIDmode, dest, src1)));
6480 /* Emit the conditional move for the test being false if needed. */
6481 if (! rtx_equal_p (dest, src2))
6482 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6483 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6484 gen_rtx_SET (VOIDmode, dest, src2)));
6487 /* Finish up, return sequence. */
6494 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6495 memory location that is not known to be dword-aligned. */
6497 frv_split_double_load (rtx dest, rtx source)
6499 int regno = REGNO (dest);
6500 rtx dest1 = gen_highpart (SImode, dest);
6501 rtx dest2 = gen_lowpart (SImode, dest);
6502 rtx address = XEXP (source, 0);
6504 /* If the address is pre-modified, load the lower-numbered register
6505 first, then load the other register using an integer offset from
6506 the modified base register. This order should always be safe,
6507 since the pre-modification cannot affect the same registers as the
6510 The situation for other loads is more complicated. Loading one
6511 of the registers could affect the value of ADDRESS, so we must
6512 be careful which order we do them in. */
6513 if (GET_CODE (address) == PRE_MODIFY
6514 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6516 /* It is safe to load the lower-numbered register first. */
6517 emit_move_insn (dest1, change_address (source, SImode, NULL));
6518 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6522 /* ADDRESS is not pre-modified and the address depends on the
6523 lower-numbered register. Load the higher-numbered register
6525 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6526 emit_move_insn (dest1, change_address (source, SImode, NULL));
6530 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6531 and SOURCE is either a double register or the constant zero. */
6533 frv_split_double_store (rtx dest, rtx source)
6535 rtx dest1 = change_address (dest, SImode, NULL);
6536 rtx dest2 = frv_index_memory (dest, SImode, 1);
6537 if (ZERO_P (source))
6539 emit_move_insn (dest1, CONST0_RTX (SImode));
6540 emit_move_insn (dest2, CONST0_RTX (SImode));
6544 emit_move_insn (dest1, gen_highpart (SImode, source));
6545 emit_move_insn (dest2, gen_lowpart (SImode, source));
6550 /* Split a min/max operation returning a SEQUENCE containing all of the
6554 frv_split_minmax (rtx operands[])
6556 rtx dest = operands[0];
6557 rtx minmax = operands[1];
6558 rtx src1 = operands[2];
6559 rtx src2 = operands[3];
6560 rtx cc_reg = operands[4];
6561 rtx cr_reg = operands[5];
6563 enum rtx_code test_code;
6564 enum machine_mode cr_mode = GET_MODE (cr_reg);
6568 /* Figure out which test to use. */
6569 switch (GET_CODE (minmax))
6574 case SMIN: test_code = LT; break;
6575 case SMAX: test_code = GT; break;
6576 case UMIN: test_code = LTU; break;
6577 case UMAX: test_code = GTU; break;
6580 /* Issue the compare instruction. */
6581 emit_insn (gen_rtx_SET (VOIDmode,
6583 gen_rtx_COMPARE (GET_MODE (cc_reg),
6586 /* Set the appropriate CCR bit. */
6587 emit_insn (gen_rtx_SET (VOIDmode,
6589 gen_rtx_fmt_ee (test_code,
6594 /* If are taking the min/max of a nonzero constant, load that first, and
6595 then do a conditional move of the other value. */
6596 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6598 if (rtx_equal_p (dest, src1))
6601 emit_move_insn (dest, src2);
6602 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6603 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6604 gen_rtx_SET (VOIDmode, dest, src1)));
6607 /* Otherwise, do each half of the move. */
6610 /* Emit the conditional move for the test being true if needed. */
6611 if (! rtx_equal_p (dest, src1))
6612 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6613 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6614 gen_rtx_SET (VOIDmode, dest, src1)));
6616 /* Emit the conditional move for the test being false if needed. */
6617 if (! rtx_equal_p (dest, src2))
6618 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6619 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6620 gen_rtx_SET (VOIDmode, dest, src2)));
6623 /* Finish up, return sequence. */
6630 /* Split an integer abs operation returning a SEQUENCE containing all of the
6634 frv_split_abs (rtx operands[])
6636 rtx dest = operands[0];
6637 rtx src = operands[1];
6638 rtx cc_reg = operands[2];
6639 rtx cr_reg = operands[3];
6644 /* Issue the compare < 0 instruction. */
6645 emit_insn (gen_rtx_SET (VOIDmode,
6647 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6649 /* Set the appropriate CCR bit. */
6650 emit_insn (gen_rtx_SET (VOIDmode,
6652 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6654 /* Emit the conditional negate if the value is negative. */
6655 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6656 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6657 gen_negsi2 (dest, src)));
6659 /* Emit the conditional move for the test being false if needed. */
6660 if (! rtx_equal_p (dest, src))
6661 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6662 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6663 gen_rtx_SET (VOIDmode, dest, src)));
6665 /* Finish up, return sequence. */
6672 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6673 register used in an insn. */
6676 frv_clear_registers_used (rtx *ptr, void *data)
6678 if (GET_CODE (*ptr) == REG)
6680 int regno = REGNO (*ptr);
6681 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6683 if (regno < FIRST_PSEUDO_REGISTER)
6685 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6687 while (regno < reg_max)
6689 CLEAR_HARD_REG_BIT (*p_regs, regno);
6699 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6701 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6702 initialize the static storage. */
6704 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6706 frv_ifcvt.added_insns_list = NULL_RTX;
6707 frv_ifcvt.cur_scratch_regs = 0;
6708 frv_ifcvt.num_nested_cond_exec = 0;
6709 frv_ifcvt.cr_reg = NULL_RTX;
6710 frv_ifcvt.nested_cc_reg = NULL_RTX;
6711 frv_ifcvt.extra_int_cr = NULL_RTX;
6712 frv_ifcvt.extra_fp_cr = NULL_RTX;
6713 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6717 /* Internal function to add a potential insn to the list of insns to be inserted
6718 if the conditional execution conversion is successful. */
6721 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6723 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6725 link->jump = before_p; /* Mark to add this before or after insn. */
6726 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6727 frv_ifcvt.added_insns_list);
6729 if (TARGET_DEBUG_COND_EXEC)
6732 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6733 (before_p) ? "before" : "after",
6734 (int)INSN_UID (insn));
6736 debug_rtx (pattern);
6741 /* A C expression to modify the code described by the conditional if
6742 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6743 FALSE_EXPR for converting if-then and if-then-else code to conditional
6744 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6745 tests cannot be converted. */
6748 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6750 basic_block test_bb = ce_info->test_bb; /* test basic block */
6751 basic_block then_bb = ce_info->then_bb; /* THEN */
6752 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6753 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6754 rtx true_expr = *p_true;
6758 enum machine_mode mode = GET_MODE (true_expr);
6762 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6764 rtx sub_cond_exec_reg;
6766 enum rtx_code code_true;
6767 enum rtx_code code_false;
6768 enum reg_class cc_class;
6769 enum reg_class cr_class;
6772 reg_set_iterator rsi;
6774 /* Make sure we are only dealing with hard registers. Also honor the
6775 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6777 if (!reload_completed || !TARGET_COND_EXEC
6778 || (!TARGET_NESTED_CE && ce_info->pass > 1))
6781 /* Figure out which registers we can allocate for our own purposes. Only
6782 consider registers that are not preserved across function calls and are
6783 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6784 if we did not need to use them in reloading other registers. */
6785 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6786 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6787 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6788 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6789 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6791 /* If this is a nested IF, we need to discover whether the CC registers that
6792 are set/used inside of the block are used anywhere else. If not, we can
6793 change them to be the CC register that is paired with the CR register that
6794 controls the outermost IF block. */
6795 if (ce_info->pass > 1)
6797 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6798 for (j = CC_FIRST; j <= CC_LAST; j++)
6799 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6801 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6804 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6807 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6810 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6814 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6815 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6817 frv_ifcvt.added_insns_list = NULL_RTX;
6818 frv_ifcvt.cur_scratch_regs = 0;
6820 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6821 * sizeof (basic_block));
6827 /* Remove anything live at the beginning of the join block from being
6828 available for allocation. */
6829 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
6831 if (regno < FIRST_PSEUDO_REGISTER)
6832 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6836 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6838 if (ce_info->num_multiple_test_blocks)
6840 basic_block multiple_test_bb = ce_info->last_test_bb;
6842 while (multiple_test_bb != test_bb)
6844 bb[num_bb++] = multiple_test_bb;
6845 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
6849 /* Add in the THEN and ELSE blocks to be scanned. */
6850 bb[num_bb++] = then_bb;
6852 bb[num_bb++] = else_bb;
6854 sub_cond_exec_reg = NULL_RTX;
6855 frv_ifcvt.num_nested_cond_exec = 0;
6857 /* Scan all of the blocks for registers that must not be allocated. */
6858 for (j = 0; j < num_bb; j++)
6860 rtx last_insn = BB_END (bb[j]);
6861 rtx insn = BB_HEAD (bb[j]);
6865 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6866 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6868 (int) INSN_UID (BB_HEAD (bb[j])),
6869 (int) INSN_UID (BB_END (bb[j])));
6871 /* Anything live at the beginning of the block is obviously unavailable
6873 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
6875 if (regno < FIRST_PSEUDO_REGISTER)
6876 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6879 /* Loop through the insns in the block. */
6882 /* Mark any new registers that are created as being unavailable for
6883 allocation. Also see if the CC register used in nested IFs can be
6889 int skip_nested_if = FALSE;
6891 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6892 (void *)&tmp_reg->regs);
6894 pattern = PATTERN (insn);
6895 if (GET_CODE (pattern) == COND_EXEC)
6897 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6899 if (reg != sub_cond_exec_reg)
6901 sub_cond_exec_reg = reg;
6902 frv_ifcvt.num_nested_cond_exec++;
6906 set = single_set_pattern (pattern);
6909 rtx dest = SET_DEST (set);
6910 rtx src = SET_SRC (set);
6912 if (GET_CODE (dest) == REG)
6914 int regno = REGNO (dest);
6915 enum rtx_code src_code = GET_CODE (src);
6917 if (CC_P (regno) && src_code == COMPARE)
6918 skip_nested_if = TRUE;
6920 else if (CR_P (regno)
6921 && (src_code == IF_THEN_ELSE
6922 || COMPARISON_P (src)))
6923 skip_nested_if = TRUE;
6927 if (! skip_nested_if)
6928 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6929 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6932 if (insn == last_insn)
6935 insn = NEXT_INSN (insn);
6939 /* If this is a nested if, rewrite the CC registers that are available to
6940 include the ones that can be rewritten, to increase the chance of being
6941 able to allocate a paired CC/CR register combination. */
6942 if (ce_info->pass > 1)
6944 for (j = CC_FIRST; j <= CC_LAST; j++)
6945 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6946 SET_HARD_REG_BIT (tmp_reg->regs, j);
6948 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6954 fprintf (dump_file, "Available GPRs: ");
6956 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6957 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6959 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6960 if (++num_gprs > GPR_TEMP_NUM+2)
6964 fprintf (dump_file, "%s\nAvailable CRs: ",
6965 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6967 for (j = CR_FIRST; j <= CR_LAST; j++)
6968 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6969 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6971 fputs ("\n", dump_file);
6973 if (ce_info->pass > 1)
6975 fprintf (dump_file, "Modifiable CCs: ");
6976 for (j = CC_FIRST; j <= CC_LAST; j++)
6977 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6978 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6980 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6981 frv_ifcvt.num_nested_cond_exec);
6985 /* Allocate the appropriate temporary condition code register. Try to
6986 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6987 that conditional cmp's can be done. */
6988 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
6990 cr_class = ICR_REGS;
6991 cc_class = ICC_REGS;
6992 cc_first = ICC_FIRST;
6995 else if (mode == CC_FPmode)
6997 cr_class = FCR_REGS;
6998 cc_class = FCC_REGS;
6999 cc_first = FCC_FIRST;
7004 cc_first = cc_last = 0;
7005 cr_class = cc_class = NO_REGS;
7008 cc = XEXP (true_expr, 0);
7009 nested_cc = cr = NULL_RTX;
7010 if (cc_class != NO_REGS)
7012 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
7013 so we can execute a csubcc/caddcc/cfcmps instruction. */
7016 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
7018 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
7020 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
7021 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
7023 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
7024 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
7027 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
7028 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
7038 fprintf (dump_file, "Could not allocate a CR temporary register\n");
7045 "Will use %s for conditional execution, %s for nested comparisons\n",
7046 reg_names[ REGNO (cr)],
7047 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
7049 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
7050 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
7051 bit being true. We don't do this for floating point, because of NaNs. */
7052 code = GET_CODE (true_expr);
7053 if (GET_MODE (cc) != CC_FPmode)
7055 code = reverse_condition (code);
7065 check_insn = gen_rtx_SET (VOIDmode, cr,
7066 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
7068 /* Record the check insn to be inserted later. */
7069 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
7071 /* Update the tests. */
7072 frv_ifcvt.cr_reg = cr;
7073 frv_ifcvt.nested_cc_reg = nested_cc;
7074 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
7075 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
7078 /* Fail, don't do this conditional execution. */
7081 *p_false = NULL_RTX;
7083 fprintf (dump_file, "Disabling this conditional execution.\n");
7089 /* A C expression to modify the code described by the conditional if
7090 information CE_INFO, for the basic block BB, possibly updating the tests in
7091 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
7092 if-then-else code to conditional instructions. Set either TRUE_EXPR or
7093 FALSE_EXPR to a null pointer if the tests cannot be converted. */
7095 /* p_true and p_false are given expressions of the form:
7097 (and (eq:CC_CCR (reg:CC_CCR)
7103 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
7108 rtx old_true = XEXP (*p_true, 0);
7109 rtx old_false = XEXP (*p_false, 0);
7110 rtx true_expr = XEXP (*p_true, 1);
7111 rtx false_expr = XEXP (*p_false, 1);
7114 rtx cr = XEXP (old_true, 0);
7116 rtx new_cr = NULL_RTX;
7117 rtx *p_new_cr = (rtx *)0;
7121 enum reg_class cr_class;
7122 enum machine_mode mode = GET_MODE (true_expr);
7123 rtx (*logical_func)(rtx, rtx, rtx);
7125 if (TARGET_DEBUG_COND_EXEC)
7128 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7129 ce_info->and_and_p ? "&&" : "||");
7131 debug_rtx (*p_true);
7133 fputs ("\nfalse insn:\n", stderr);
7134 debug_rtx (*p_false);
7137 if (!TARGET_MULTI_CE)
7140 if (GET_CODE (cr) != REG)
7143 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
7145 cr_class = ICR_REGS;
7146 p_new_cr = &frv_ifcvt.extra_int_cr;
7148 else if (mode == CC_FPmode)
7150 cr_class = FCR_REGS;
7151 p_new_cr = &frv_ifcvt.extra_fp_cr;
7156 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7157 more &&/|| tests. */
7161 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7162 CC_CCRmode, TRUE, TRUE);
7167 if (ce_info->and_and_p)
7169 old_test = old_false;
7170 test_expr = true_expr;
7171 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7172 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7173 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7177 old_test = old_false;
7178 test_expr = false_expr;
7179 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7180 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7181 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7184 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7185 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7187 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
7189 /* Now add the conditional check insn. */
7190 cc = XEXP (test_expr, 0);
7191 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7192 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7194 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7196 /* Add the new check insn to the list of check insns that need to be
7198 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
7200 if (TARGET_DEBUG_COND_EXEC)
7202 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7205 debug_rtx (*p_true);
7207 fputs ("\nfalse insn:\n", stderr);
7208 debug_rtx (*p_false);
7214 *p_true = *p_false = NULL_RTX;
7216 /* If we allocated a CR register, release it. */
7219 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7220 *p_new_cr = NULL_RTX;
7223 if (TARGET_DEBUG_COND_EXEC)
7224 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7230 /* Return a register which will be loaded with a value if an IF block is
7231 converted to conditional execution. This is used to rewrite instructions
7232 that use constants to ones that just use registers. */
7235 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
7237 int num_alloc = frv_ifcvt.cur_scratch_regs;
7241 /* We know gr0 == 0, so replace any errant uses. */
7242 if (value == const0_rtx)
7243 return gen_rtx_REG (SImode, GPR_FIRST);
7245 /* First search all registers currently loaded to see if we have an
7246 applicable constant. */
7247 if (CONSTANT_P (value)
7248 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7250 for (i = 0; i < num_alloc; i++)
7252 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7253 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7257 /* Have we exhausted the number of registers available? */
7258 if (num_alloc >= GPR_TEMP_NUM)
7261 fprintf (dump_file, "Too many temporary registers allocated\n");
7266 /* Allocate the new register. */
7267 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7271 fputs ("Could not find a scratch register\n", dump_file);
7276 frv_ifcvt.cur_scratch_regs++;
7277 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7281 if (GET_CODE (value) == CONST_INT)
7282 fprintf (dump_file, "Register %s will hold %ld\n",
7283 reg_names[ REGNO (reg)], (long)INTVAL (value));
7285 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7286 fprintf (dump_file, "Register %s will hold LR\n",
7287 reg_names[ REGNO (reg)]);
7290 fprintf (dump_file, "Register %s will hold a saved value\n",
7291 reg_names[ REGNO (reg)]);
7298 /* Update a MEM used in conditional code that might contain an offset to put
7299 the offset into a scratch register, so that the conditional load/store
7300 operations can be used. This function returns the original pointer if the
7301 MEM is valid to use in conditional code, NULL if we can't load up the offset
7302 into a temporary register, or the new MEM if we were successful. */
7305 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7307 rtx addr = XEXP (mem, 0);
7309 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7311 if (GET_CODE (addr) == PLUS)
7313 rtx addr_op0 = XEXP (addr, 0);
7314 rtx addr_op1 = XEXP (addr, 1);
7316 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7318 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7322 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7329 else if (CONSTANT_P (addr))
7330 addr = frv_ifcvt_load_value (addr, insn);
7335 if (addr == NULL_RTX)
7338 else if (XEXP (mem, 0) != addr)
7339 return change_address (mem, mode, addr);
7346 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7347 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7350 single_set_pattern (rtx pattern)
7355 if (GET_CODE (pattern) == COND_EXEC)
7356 pattern = COND_EXEC_CODE (pattern);
7358 if (GET_CODE (pattern) == SET)
7361 else if (GET_CODE (pattern) == PARALLEL)
7363 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7365 rtx sub = XVECEXP (pattern, 0, i);
7367 switch (GET_CODE (sub))
7391 /* A C expression to modify the code described by the conditional if
7392 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7393 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7394 insn cannot be converted to be executed conditionally. */
7397 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7401 rtx orig_ce_pattern = pattern;
7407 if (GET_CODE (pattern) != COND_EXEC)
7410 test = COND_EXEC_TEST (pattern);
7411 if (GET_CODE (test) == AND)
7413 rtx cr = frv_ifcvt.cr_reg;
7416 op0 = XEXP (test, 0);
7417 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7420 op1 = XEXP (test, 1);
7421 test_reg = XEXP (op1, 0);
7422 if (GET_CODE (test_reg) != REG)
7425 /* Is this the first nested if block in this sequence? If so, generate
7426 an andcr or andncr. */
7427 if (! frv_ifcvt.last_nested_if_cr)
7431 frv_ifcvt.last_nested_if_cr = test_reg;
7432 if (GET_CODE (op0) == NE)
7433 and_op = gen_andcr (test_reg, cr, test_reg);
7435 and_op = gen_andncr (test_reg, cr, test_reg);
7437 frv_ifcvt_add_insn (and_op, insn, TRUE);
7440 /* If this isn't the first statement in the nested if sequence, see if we
7441 are dealing with the same register. */
7442 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7445 COND_EXEC_TEST (pattern) = test = op1;
7448 /* If this isn't a nested if, reset state variables. */
7451 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7454 set = single_set_pattern (pattern);
7457 rtx dest = SET_DEST (set);
7458 rtx src = SET_SRC (set);
7459 enum machine_mode mode = GET_MODE (dest);
7461 /* Check for normal binary operators. */
7462 if (mode == SImode && ARITHMETIC_P (src))
7464 op0 = XEXP (src, 0);
7465 op1 = XEXP (src, 1);
7467 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7469 op1 = frv_ifcvt_load_value (op1, insn);
7471 COND_EXEC_CODE (pattern)
7472 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7480 /* For multiply by a constant, we need to handle the sign extending
7481 correctly. Add a USE of the value after the multiply to prevent flow
7482 from cratering because only one register out of the two were used. */
7483 else if (mode == DImode && GET_CODE (src) == MULT)
7485 op0 = XEXP (src, 0);
7486 op1 = XEXP (src, 1);
7487 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7489 op1 = frv_ifcvt_load_value (op1, insn);
7492 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7493 COND_EXEC_CODE (pattern)
7494 = gen_rtx_SET (VOIDmode, dest,
7495 gen_rtx_MULT (DImode, op0, op1));
7501 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7504 /* If we are just loading a constant created for a nested conditional
7505 execution statement, just load the constant without any conditional
7506 execution, since we know that the constant will not interfere with any
7508 else if (frv_ifcvt.scratch_insns_bitmap
7509 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7511 && REG_P (SET_DEST (set))
7512 /* We must not unconditionally set a scratch reg chosen
7513 for a nested if-converted block if its incoming
7514 value from the TEST block (or the result of the THEN
7515 branch) could/should propagate to the JOIN block.
7516 It suffices to test whether the register is live at
7517 the JOIN point: if it's live there, we can infer
7518 that we set it in the former JOIN block of the
7519 nested if-converted block (otherwise it wouldn't
7520 have been available as a scratch register), and it
7521 is either propagated through or set in the other
7522 conditional block. It's probably not worth trying
7523 to catch the latter case, and it could actually
7524 limit scheduling of the combined block quite
7527 && ! (REGNO_REG_SET_P
7528 (ce_info->join_bb->global_live_at_start,
7529 REGNO (SET_DEST (set))))
7530 /* Similarly, we must not unconditionally set a reg
7531 used as scratch in the THEN branch if the same reg
7532 is live in the ELSE branch. */
7533 && (! ce_info->else_bb
7534 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7535 || ! (REGNO_REG_SET_P
7536 (ce_info->else_bb->global_live_at_start,
7537 REGNO (SET_DEST (set))))))
7540 else if (mode == QImode || mode == HImode || mode == SImode
7543 int changed_p = FALSE;
7545 /* Check for just loading up a constant */
7546 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7548 src = frv_ifcvt_load_value (src, insn);
7555 /* See if we need to fix up stores */
7556 if (GET_CODE (dest) == MEM)
7558 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7563 else if (new_mem != dest)
7570 /* See if we need to fix up loads */
7571 if (GET_CODE (src) == MEM)
7573 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7578 else if (new_mem != src)
7585 /* If either src or destination changed, redo SET. */
7587 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7590 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7591 rewriting the CC register to be the same as the paired CC/CR register
7593 else if (mode == CC_CCRmode && COMPARISON_P (src))
7595 int regno = REGNO (XEXP (src, 0));
7598 if (ce_info->pass > 1
7599 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7600 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7602 src = gen_rtx_fmt_ee (GET_CODE (src),
7604 frv_ifcvt.nested_cc_reg,
7608 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7609 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7612 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7613 else if (ce_info->pass > 1
7614 && GET_CODE (dest) == REG
7615 && CC_P (REGNO (dest))
7616 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7617 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7619 && GET_CODE (src) == COMPARE)
7621 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7622 COND_EXEC_CODE (pattern)
7623 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7627 if (TARGET_DEBUG_COND_EXEC)
7629 rtx orig_pattern = PATTERN (insn);
7631 PATTERN (insn) = pattern;
7633 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7637 PATTERN (insn) = orig_pattern;
7643 if (TARGET_DEBUG_COND_EXEC)
7645 rtx orig_pattern = PATTERN (insn);
7647 PATTERN (insn) = orig_ce_pattern;
7649 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7653 PATTERN (insn) = orig_pattern;
7660 /* A C expression to perform any final machine dependent modifications in
7661 converting code to conditional execution in the code described by the
7662 conditional if information CE_INFO. */
7665 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7669 rtx p = frv_ifcvt.added_insns_list;
7672 /* Loop inserting the check insns. The last check insn is the first test,
7673 and is the appropriate place to insert constants. */
7679 rtx check_and_insert_insns = XEXP (p, 0);
7682 check_insn = XEXP (check_and_insert_insns, 0);
7683 existing_insn = XEXP (check_and_insert_insns, 1);
7686 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7687 the existing insn, otherwise it is to be inserted AFTER. */
7688 if (check_and_insert_insns->jump)
7690 emit_insn_before (check_insn, existing_insn);
7691 check_and_insert_insns->jump = 0;
7694 emit_insn_after (check_insn, existing_insn);
7696 free_EXPR_LIST_node (check_and_insert_insns);
7697 free_EXPR_LIST_node (old_p);
7699 while (p != NULL_RTX);
7701 /* Load up any constants needed into temp gprs */
7702 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7704 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7705 if (! frv_ifcvt.scratch_insns_bitmap)
7706 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
7707 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7708 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7711 frv_ifcvt.added_insns_list = NULL_RTX;
7712 frv_ifcvt.cur_scratch_regs = 0;
7716 /* A C expression to cancel any machine dependent modifications in converting
7717 code to conditional execution in the code described by the conditional if
7718 information CE_INFO. */
7721 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7724 rtx p = frv_ifcvt.added_insns_list;
7726 /* Loop freeing up the EXPR_LIST's allocated. */
7727 while (p != NULL_RTX)
7729 rtx check_and_jump = XEXP (p, 0);
7733 free_EXPR_LIST_node (check_and_jump);
7734 free_EXPR_LIST_node (old_p);
7737 /* Release any temporary gprs allocated. */
7738 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7739 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7741 frv_ifcvt.added_insns_list = NULL_RTX;
7742 frv_ifcvt.cur_scratch_regs = 0;
7746 /* A C expression for the size in bytes of the trampoline, as an integer.
7750 setlo #0, <static_chain>
7752 sethi #0, <static_chain>
7753 jmpl @(gr0,<jmp_reg>) */
7756 frv_trampoline_size (void)
7759 /* Allocate room for the function descriptor and the lddi
7762 return 5 /* instructions */ * 4 /* instruction size. */;
7766 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7767 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7768 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7769 should be passed to the function when it is called.
7774 setlo #0, <static_chain>
7776 sethi #0, <static_chain>
7777 jmpl @(gr0,<jmp_reg>) */
7780 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7782 rtx sc_reg = force_reg (Pmode, static_chain);
7784 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7787 GEN_INT (frv_trampoline_size ()), SImode,
7793 /* Many machines have some registers that cannot be copied directly to or from
7794 memory or even from other types of registers. An example is the `MQ'
7795 register, which on most machines, can only be copied to or from general
7796 registers, but not memory. Some machines allow copying all registers to and
7797 from memory, but require a scratch register for stores to some memory
7798 locations (e.g., those with symbolic address on the RT, and those with
7799 certain symbolic address on the SPARC when compiling PIC). In some cases,
7800 both an intermediate and a scratch register are required.
7802 You should define these macros to indicate to the reload phase that it may
7803 need to allocate at least one register for a reload in addition to the
7804 register to contain the data. Specifically, if copying X to a register
7805 CLASS in MODE requires an intermediate register, you should define
7806 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7807 whose registers can be used as intermediate registers or scratch registers.
7809 If copying a register CLASS in MODE to X requires an intermediate or scratch
7810 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7811 largest register class required. If the requirements for input and output
7812 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7813 instead of defining both macros identically.
7815 The values returned by these macros are often `GENERAL_REGS'. Return
7816 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7817 to or from a register of CLASS in MODE without requiring a scratch register.
7818 Do not define this macro if it would always return `NO_REGS'.
7820 If a scratch register is required (either with or without an intermediate
7821 register), you should define patterns for `reload_inM' or `reload_outM', as
7822 required.. These patterns, which will normally be implemented with a
7823 `define_expand', should be similar to the `movM' patterns, except that
7824 operand 2 is the scratch register.
7826 Define constraints for the reload register and scratch register that contain
7827 a single register class. If the original reload register (whose class is
7828 CLASS) can meet the constraint given in the pattern, the value returned by
7829 these macros is used for the class of the scratch register. Otherwise, two
7830 additional reload registers are required. Their classes are obtained from
7831 the constraints in the insn pattern.
7833 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7834 either be in a hard register or in memory. Use `true_regnum' to find out;
7835 it will return -1 if the pseudo is in memory and the hard register number if
7836 it is in a register.
7838 These macros should not be used in the case where a particular class of
7839 registers can only be copied to memory and not to another class of
7840 registers. In that case, secondary reload registers are not needed and
7841 would not be helpful. Instead, a stack location must be used to perform the
7842 copy and the `movM' pattern should use memory as an intermediate storage.
7843 This case often occurs between floating-point and general registers. */
7846 frv_secondary_reload_class (enum reg_class class,
7847 enum machine_mode mode ATTRIBUTE_UNUSED,
7849 int in_p ATTRIBUTE_UNUSED)
7859 /* Accumulators/Accumulator guard registers need to go through floating
7865 if (x && GET_CODE (x) == REG)
7867 int regno = REGNO (x);
7869 if (ACC_P (regno) || ACCG_P (regno))
7874 /* Nonzero constants should be loaded into an FPR through a GPR. */
7878 if (x && CONSTANT_P (x) && !ZERO_P (x))
7884 /* All of these types need gpr registers. */
7896 /* The accumulators need fpr registers */
7909 /* A C expression whose value is nonzero if pseudos that have been assigned to
7910 registers of class CLASS would likely be spilled because registers of CLASS
7911 are needed for spill registers.
7913 The default value of this macro returns 1 if CLASS has exactly one register
7914 and zero otherwise. On most machines, this default should be used. Only
7915 define this macro to some other expression if pseudo allocated by
7916 `local-alloc.c' end up in memory because their hard registers were needed
7917 for spill registers. If this macro returns nonzero for those classes, those
7918 pseudos will only be allocated by `global.c', which knows how to reallocate
7919 the pseudo to another register. If there would not be another register
7920 available for reallocation, you should not change the definition of this
7921 macro since the only effect of such a definition would be to slow down
7922 register allocation. */
7925 frv_class_likely_spilled_p (enum reg_class class)
7935 case FDPIC_FPTR_REGS:
7957 /* An expression for the alignment of a structure field FIELD if the
7958 alignment computed in the usual way is COMPUTED. GCC uses this
7959 value instead of the value in `BIGGEST_ALIGNMENT' or
7960 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7962 /* The definition type of the bit field data is either char, short, long or
7963 long long. The maximum bit size is the number of bits of its own type.
7965 The bit field data is assigned to a storage unit that has an adequate size
7966 for bit field data retention and is located at the smallest address.
7968 Consecutive bit field data are packed at consecutive bits having the same
7969 storage unit, with regard to the type, beginning with the MSB and continuing
7972 If a field to be assigned lies over a bit field type boundary, its
7973 assignment is completed by aligning it with a boundary suitable for the
7976 When a bit field having a bit length of 0 is declared, it is forcibly
7977 assigned to the next storage unit.
7990 &x 00000000 00000000 00000000 00000000
7993 &x+4 00000000 00000000 00000000 00000000
7996 &x+8 00000000 00000000 00000000 00000000
7999 &x+12 00000000 00000000 00000000 00000000
8005 frv_adjust_field_align (tree field, int computed)
8007 /* Make sure that the bitfield is not wider than the type. */
8008 if (DECL_BIT_FIELD (field)
8009 && !DECL_ARTIFICIAL (field))
8011 tree parent = DECL_CONTEXT (field);
8012 tree prev = NULL_TREE;
8015 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
8017 if (TREE_CODE (cur) != FIELD_DECL)
8026 /* If this isn't a :0 field and if the previous element is a bitfield
8027 also, see if the type is different, if so, we will need to align the
8028 bit-field to the next boundary. */
8030 && ! DECL_PACKED (field)
8031 && ! integer_zerop (DECL_SIZE (field))
8032 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
8034 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
8035 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
8036 computed = (prev_align > cur_align) ? prev_align : cur_align;
8044 /* A C expression that is nonzero if it is permissible to store a value of mode
8045 MODE in hard register number REGNO (or in several registers starting with
8046 that one). For a machine where all registers are equivalent, a suitable
8049 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
8051 It is not necessary for this macro to check for the numbers of fixed
8052 registers, because the allocation mechanism considers them to be always
8055 On some machines, double-precision values must be kept in even/odd register
8056 pairs. The way to implement that is to define this macro to reject odd
8057 register numbers for such modes.
8059 The minimum requirement for a mode to be OK in a register is that the
8060 `movMODE' instruction pattern support moves between the register and any
8061 other hard register for which the mode is OK; and that moving a value into
8062 the register and back out not alter it.
8064 Since the same instruction used to move `SImode' will work for all narrower
8065 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
8066 to distinguish between these modes, provided you define patterns `movhi',
8067 etc., to take advantage of this. This is useful because of the interaction
8068 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
8069 all integer modes to be tieable.
8071 Many machines have special registers for floating point arithmetic. Often
8072 people assume that floating point machine modes are allowed only in floating
8073 point registers. This is not true. Any registers that can hold integers
8074 can safely *hold* a floating point machine mode, whether or not floating
8075 arithmetic can be done on it in those registers. Integer move instructions
8076 can be used to move the values.
8078 On some machines, though, the converse is true: fixed-point machine modes
8079 may not go in floating registers. This is true if the floating registers
8080 normalize any value stored in them, because storing a non-floating value
8081 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
8082 fixed-point machine modes in floating registers. But if the floating
8083 registers do not automatically normalize, if you can store any bit pattern
8084 in one and retrieve it unchanged without a trap, then any machine mode may
8085 go in a floating register, so you can define this macro to say so.
8087 The primary significance of special floating registers is rather that they
8088 are the registers acceptable in floating point arithmetic instructions.
8089 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
8090 writing the proper constraints for those instructions.
8092 On some machines, the floating registers are especially slow to access, so
8093 that it is better to store a value in a stack frame than in such a register
8094 if floating point arithmetic is not being done. As long as the floating
8095 registers are not in class `GENERAL_REGS', they will not be used unless some
8096 pattern's constraint asks for one. */
8099 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
8109 return ICC_P (regno) || GPR_P (regno);
8112 return CR_P (regno) || GPR_P (regno);
8115 return FCC_P (regno) || GPR_P (regno);
8121 /* Set BASE to the first register in REGNO's class. Set MASK to the
8122 bits that must be clear in (REGNO - BASE) for the register to be
8124 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
8128 /* ACCGs store one byte. Two-byte quantities must start in
8129 even-numbered registers, four-byte ones in registers whose
8130 numbers are divisible by four, and so on. */
8132 mask = GET_MODE_SIZE (mode) - 1;
8136 /* The other registers store one word. */
8137 if (GPR_P (regno) || regno == AP_FIRST)
8140 else if (FPR_P (regno))
8143 else if (ACC_P (regno))
8146 else if (SPR_P (regno))
8147 return mode == SImode;
8149 /* Fill in the table. */
8153 /* Anything smaller than an SI is OK in any word-sized register. */
8154 if (GET_MODE_SIZE (mode) < 4)
8157 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8159 return (((regno - base) & mask) == 0);
8166 /* A C expression for the number of consecutive hard registers, starting at
8167 register number REGNO, required to hold a value of mode MODE.
8169 On a machine where all registers are exactly one word, a suitable definition
8172 #define HARD_REGNO_NREGS(REGNO, MODE) \
8173 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8174 / UNITS_PER_WORD)) */
8176 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8177 that we can build the appropriate instructions to properly reload the
8178 values. Also, make the byte-sized accumulator guards use one guard
8182 frv_hard_regno_nregs (int regno, enum machine_mode mode)
8185 return GET_MODE_SIZE (mode);
8187 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8191 /* A C expression for the maximum number of consecutive registers of
8192 class CLASS needed to hold a value of mode MODE.
8194 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8195 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8196 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8198 This macro helps control the handling of multiple-word values in
8201 This declaration is required. */
8204 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
8206 if (class == ACCG_REGS)
8207 /* An N-byte value requires N accumulator guards. */
8208 return GET_MODE_SIZE (mode);
8210 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8214 /* A C expression that is nonzero if X is a legitimate constant for an
8215 immediate operand on the target machine. You can assume that X satisfies
8216 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8217 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8220 frv_legitimate_constant_p (rtx x)
8222 enum machine_mode mode = GET_MODE (x);
8224 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8225 means that the move expanders will be expected to deal with most
8226 kinds of constant, regardless of what we return here.
8228 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8229 a constant can be entered into reg_equiv_constant[]. If we return true,
8230 reload can create new instances of the constant whenever it likes.
8232 The idea is therefore to accept as many constants as possible (to give
8233 reload more freedom) while rejecting constants that can only be created
8234 at certain times. In particular, anything with a symbolic component will
8235 require use of the pseudo FDPIC register, which is only available before
8238 return LEGITIMATE_PIC_OPERAND_P (x);
8240 /* All of the integer constants are ok. */
8241 if (GET_CODE (x) != CONST_DOUBLE)
8244 /* double integer constants are ok. */
8245 if (mode == VOIDmode || mode == DImode)
8248 /* 0 is always ok. */
8249 if (x == CONST0_RTX (mode))
8252 /* If floating point is just emulated, allow any constant, since it will be
8253 constructed in the GPRs. */
8254 if (!TARGET_HAS_FPRS)
8257 if (mode == DFmode && !TARGET_DOUBLE)
8260 /* Otherwise store the constant away and do a load. */
8264 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
8265 CC_NZ for comparisons against zero in which a single Z or N flag test
8266 is enough, CC_UNS for other unsigned comparisons, and CC for other
8267 signed comparisons. */
8270 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
8272 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
8281 return y == const0_rtx ? CC_NZmode : CCmode;
8287 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
8294 /* A C expression for the cost of moving data from a register in class FROM to
8295 one in class TO. The classes are expressed using the enumeration values
8296 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8297 interpreted relative to that.
8299 It is not required that the cost always equal 2 when FROM is the same as TO;
8300 on some machines it is expensive to move between registers if they are not
8303 If reload sees an insn consisting of a single `set' between two hard
8304 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8305 value of 2, reload does not check to ensure that the constraints of the insn
8306 are met. Setting a cost of other than 2 will allow reload to verify that
8307 the constraints are met. You should do this if the `movM' pattern's
8308 constraints do not allow such copying. */
8310 #define HIGH_COST 40
8311 #define MEDIUM_COST 3
8315 frv_register_move_cost (enum reg_class from, enum reg_class to)
8399 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8400 use ".picptr" to generate safe relocations for PIC code. We also
8401 need a fixup entry for aligned (non-debugging) code. */
8404 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8406 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8408 if (GET_CODE (value) == CONST
8409 || GET_CODE (value) == SYMBOL_REF
8410 || GET_CODE (value) == LABEL_REF)
8412 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8413 && SYMBOL_REF_FUNCTION_P (value))
8415 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8416 output_addr_const (asm_out_file, value);
8417 fputs (")\n", asm_out_file);
8420 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8421 && frv_function_symbol_referenced_p (value))
8423 if (aligned_p && !TARGET_FDPIC)
8425 static int label_num = 0;
8429 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8430 p = (* targetm.strip_name_encoding) (buf);
8432 fprintf (asm_out_file, "%s:\n", p);
8433 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8434 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8435 fprintf (asm_out_file, "\t.previous\n");
8437 assemble_integer_with_op ("\t.picptr\t", value);
8442 /* We've set the unaligned SI op to NULL, so we always have to
8443 handle the unaligned case here. */
8444 assemble_integer_with_op ("\t.4byte\t", value);
8448 return default_assemble_integer (value, size, aligned_p);
8451 /* Function to set up the backend function structure. */
8453 static struct machine_function *
8454 frv_init_machine_status (void)
8456 return ggc_alloc_cleared (sizeof (struct machine_function));
8459 /* Implement TARGET_SCHED_ISSUE_RATE. */
8462 frv_issue_rate (void)
8467 switch (frv_cpu_type)
8471 case FRV_CPU_SIMPLE:
8479 case FRV_CPU_GENERIC:
8481 case FRV_CPU_TOMCAT:
8489 /* A for_each_rtx callback. If X refers to an accumulator, return
8490 ACC_GROUP_ODD if the bit 2 of the register number is set and
8491 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
8495 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
8499 if (ACC_P (REGNO (*x)))
8500 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8501 if (ACCG_P (REGNO (*x)))
8502 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8507 /* Return the value of INSN's acc_group attribute. */
8510 frv_acc_group (rtx insn)
8512 /* This distinction only applies to the FR550 packing constraints. */
8513 if (frv_cpu_type != FRV_CPU_FR550)
8514 return ACC_GROUP_NONE;
8515 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
8518 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
8519 INSN will try to claim first. Since this value depends only on the
8520 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
8523 frv_insn_unit (rtx insn)
8525 enum attr_type type;
8527 type = get_attr_type (insn);
8528 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
8530 /* We haven't seen this type of instruction before. */
8534 /* Issue the instruction on its own to see which unit it prefers. */
8535 state = alloca (state_size ());
8536 state_reset (state);
8537 state_transition (state, insn);
8539 /* Find out which unit was taken. */
8540 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
8541 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
8544 if (unit == ARRAY_SIZE (frv_unit_codes))
8547 frv_type_to_unit[type] = unit;
8549 return frv_type_to_unit[type];
8552 /* Return true if INSN issues to a branch unit. */
8555 frv_issues_to_branch_unit_p (rtx insn)
8557 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
8560 /* The current state of the packing pass, implemented by frv_pack_insns. */
8562 /* The state of the pipeline DFA. */
8565 /* Which hardware registers are set within the current packet,
8566 and the conditions under which they are set. */
8567 regstate_t regstate[FIRST_PSEUDO_REGISTER];
8569 /* The memory locations that have been modified so far in this
8570 packet. MEM is the memref and COND is the regstate_t condition
8571 under which it is set. */
8577 /* The number of valid entries in MEMS. The value is larger than
8578 ARRAY_SIZE (mems) if there were too many mems to record. */
8579 unsigned int num_mems;
8581 /* The maximum number of instructions that can be packed together. */
8582 unsigned int issue_rate;
8584 /* The instructions in the packet, partitioned into groups. */
8585 struct frv_packet_group {
8586 /* How many instructions in the packet belong to this group. */
8587 unsigned int num_insns;
8589 /* A list of the instructions that belong to this group, in the order
8590 they appear in the rtl stream. */
8591 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8593 /* The contents of INSNS after they have been sorted into the correct
8594 assembly-language order. Element X issues to unit X. The list may
8595 contain extra nops. */
8596 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
8598 /* The member of frv_nops[] to use in sorted[]. */
8600 } groups[NUM_GROUPS];
8602 /* The instructions that make up the current packet. */
8603 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8604 unsigned int num_insns;
8607 /* Return the regstate_t flags for the given COND_EXEC condition.
8608 Abort if the condition isn't in the right form. */
8611 frv_cond_flags (rtx cond)
8613 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8614 && GET_CODE (XEXP (cond, 0)) == REG
8615 && CR_P (REGNO (XEXP (cond, 0)))
8616 && XEXP (cond, 1) == const0_rtx)
8617 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8618 | (GET_CODE (cond) == NE
8620 : REGSTATE_IF_FALSE));
8625 /* Return true if something accessed under condition COND2 can
8626 conflict with something written under condition COND1. */
8629 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
8631 /* If either reference was unconditional, we have a conflict. */
8632 if ((cond1 & REGSTATE_IF_EITHER) == 0
8633 || (cond2 & REGSTATE_IF_EITHER) == 0)
8636 /* The references might conflict if they were controlled by
8638 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
8641 /* They definitely conflict if they are controlled by the
8643 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
8650 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
8651 the current packet. DATA points to a regstate_t that describes the
8652 condition under which *X might be set or used. */
8655 frv_registers_conflict_p_1 (rtx *x, void *data)
8657 unsigned int regno, i;
8660 cond = *(regstate_t *) data;
8662 if (GET_CODE (*x) == REG)
8663 FOR_EACH_REGNO (regno, *x)
8664 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
8665 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
8668 if (GET_CODE (*x) == MEM)
8670 /* If we ran out of memory slots, assume a conflict. */
8671 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
8674 /* Check for output or true dependencies with earlier MEMs. */
8675 for (i = 0; i < frv_packet.num_mems; i++)
8676 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
8678 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
8682 if (output_dependence (frv_packet.mems[i].mem, *x))
8687 /* The return values of calls aren't significant: they describe
8688 the effect of the call as a whole, not of the insn itself. */
8689 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
8691 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
8696 /* Check subexpressions. */
8701 /* Return true if something in X might depend on an instruction
8702 in the current packet. */
8705 frv_registers_conflict_p (rtx x)
8710 if (GET_CODE (x) == COND_EXEC)
8712 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
8715 flags |= frv_cond_flags (XEXP (x, 0));
8718 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
8722 /* A note_stores callback. DATA points to the regstate_t condition
8723 under which X is modified. Update FRV_PACKET accordingly. */
8726 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8730 if (GET_CODE (x) == REG)
8731 FOR_EACH_REGNO (regno, x)
8732 frv_packet.regstate[regno] |= *(regstate_t *) data;
8734 if (GET_CODE (x) == MEM)
8736 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
8738 frv_packet.mems[frv_packet.num_mems].mem = x;
8739 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
8741 frv_packet.num_mems++;
8746 /* Update the register state information for an instruction whose
8750 frv_registers_update (rtx x)
8754 flags = REGSTATE_MODIFIED;
8755 if (GET_CODE (x) == COND_EXEC)
8757 flags |= frv_cond_flags (XEXP (x, 0));
8760 note_stores (x, frv_registers_update_1, &flags);
8764 /* Initialize frv_packet for the start of a new packet. */
8767 frv_start_packet (void)
8769 enum frv_insn_group group;
8771 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
8772 frv_packet.num_mems = 0;
8773 frv_packet.num_insns = 0;
8774 for (group = 0; group < NUM_GROUPS; group++)
8775 frv_packet.groups[group].num_insns = 0;
8779 /* Likewise for the start of a new basic block. */
8782 frv_start_packet_block (void)
8784 state_reset (frv_packet.dfa_state);
8785 frv_start_packet ();
8789 /* Finish the current packet, if any, and start a new one. Call
8790 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
8793 frv_finish_packet (void (*handle_packet) (void))
8795 if (frv_packet.num_insns > 0)
8798 state_transition (frv_packet.dfa_state, 0);
8799 frv_start_packet ();
8804 /* Return true if INSN can be added to the current packet. Update
8805 the DFA state on success. */
8808 frv_pack_insn_p (rtx insn)
8810 /* See if the packet is already as long as it can be. */
8811 if (frv_packet.num_insns == frv_packet.issue_rate)
8814 /* If the scheduler thought that an instruction should start a packet,
8815 it's usually a good idea to believe it. It knows much more about
8816 the latencies than we do.
8818 There are some exceptions though:
8820 - Conditional instructions are scheduled on the assumption that
8821 they will be executed. This is usually a good thing, since it
8822 tends to avoid unnecessary stalls in the conditional code.
8823 But we want to pack conditional instructions as tightly as
8824 possible, in order to optimize the case where they aren't
8827 - The scheduler will always put branches on their own, even
8828 if there's no real dependency.
8830 - There's no point putting a call in its own packet unless
8832 if (frv_packet.num_insns > 0
8833 && GET_CODE (insn) == INSN
8834 && GET_MODE (insn) == TImode
8835 && GET_CODE (PATTERN (insn)) != COND_EXEC)
8838 /* Check for register conflicts. Don't do this for setlo since any
8839 conflict will be with the partnering sethi, with which it can
8841 if (get_attr_type (insn) != TYPE_SETLO)
8842 if (frv_registers_conflict_p (PATTERN (insn)))
8845 return state_transition (frv_packet.dfa_state, insn) < 0;
8849 /* Add instruction INSN to the current packet. */
8852 frv_add_insn_to_packet (rtx insn)
8854 struct frv_packet_group *packet_group;
8856 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8857 packet_group->insns[packet_group->num_insns++] = insn;
8858 frv_packet.insns[frv_packet.num_insns++] = insn;
8860 frv_registers_update (PATTERN (insn));
8864 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
8865 packet ends in a branch or call, insert the nop before it, otherwise
8869 frv_insert_nop_in_packet (rtx insn)
8871 struct frv_packet_group *packet_group;
8874 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8875 last = frv_packet.insns[frv_packet.num_insns - 1];
8876 if (GET_CODE (last) != INSN)
8878 insn = emit_insn_before (PATTERN (insn), last);
8879 frv_packet.insns[frv_packet.num_insns - 1] = insn;
8880 frv_packet.insns[frv_packet.num_insns++] = last;
8884 insn = emit_insn_after (PATTERN (insn), last);
8885 frv_packet.insns[frv_packet.num_insns++] = insn;
8887 packet_group->insns[packet_group->num_insns++] = insn;
8891 /* If packing is enabled, divide the instructions into packets and
8892 return true. Call HANDLE_PACKET for each complete packet. */
8895 frv_for_each_packet (void (*handle_packet) (void))
8897 rtx insn, next_insn;
8899 frv_packet.issue_rate = frv_issue_rate ();
8901 /* Early exit if we don't want to pack insns. */
8903 || !flag_schedule_insns_after_reload
8904 || !TARGET_VLIW_BRANCH
8905 || frv_packet.issue_rate == 1)
8908 /* Set up the initial packing state. */
8910 frv_packet.dfa_state = alloca (state_size ());
8912 frv_start_packet_block ();
8913 for (insn = get_insns (); insn != 0; insn = next_insn)
8918 code = GET_CODE (insn);
8919 next_insn = NEXT_INSN (insn);
8921 if (code == CODE_LABEL)
8923 frv_finish_packet (handle_packet);
8924 frv_start_packet_block ();
8928 switch (GET_CODE (PATTERN (insn)))
8937 /* Calls mustn't be packed on a TOMCAT. */
8938 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
8939 frv_finish_packet (handle_packet);
8941 /* Since the last instruction in a packet determines the EH
8942 region, any exception-throwing instruction must come at
8943 the end of reordered packet. Insns that issue to a
8944 branch unit are bound to come last; for others it's
8945 too hard to predict. */
8946 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
8947 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
8948 frv_finish_packet (handle_packet);
8950 /* Finish the current packet if we can't add INSN to it.
8951 Simulate cycles until INSN is ready to issue. */
8952 if (!frv_pack_insn_p (insn))
8954 frv_finish_packet (handle_packet);
8955 while (!frv_pack_insn_p (insn))
8956 state_transition (frv_packet.dfa_state, 0);
8959 /* Add the instruction to the packet. */
8960 frv_add_insn_to_packet (insn);
8962 /* Calls and jumps end a packet, as do insns that throw
8964 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
8965 frv_finish_packet (handle_packet);
8969 frv_finish_packet (handle_packet);
8974 /* Subroutine of frv_sort_insn_group. We are trying to sort
8975 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
8976 language order. We have already picked a new position for
8977 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
8978 These instructions will occupy elements [0, LOWER_SLOT) and
8979 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
8980 the DFA state after issuing these instructions.
8982 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
8983 of the unused instructions. Return true if one such permutation gives
8984 a valid ordering, leaving the successful permutation in sorted[].
8985 Do not modify sorted[] until a valid permutation is found. */
8988 frv_sort_insn_group_1 (enum frv_insn_group group,
8989 unsigned int lower_slot, unsigned int upper_slot,
8990 unsigned int issued, unsigned int num_insns,
8993 struct frv_packet_group *packet_group;
8999 /* Early success if we've filled all the slots. */
9000 if (lower_slot == upper_slot)
9003 packet_group = &frv_packet.groups[group];
9004 dfa_size = state_size ();
9005 test_state = alloca (dfa_size);
9007 /* Try issuing each unused instruction. */
9008 for (i = num_insns - 1; i + 1 != 0; i--)
9009 if (~issued & (1 << i))
9011 insn = packet_group->sorted[i];
9012 memcpy (test_state, state, dfa_size);
9013 if (state_transition (test_state, insn) < 0
9014 && cpu_unit_reservation_p (test_state,
9015 NTH_UNIT (group, upper_slot - 1))
9016 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
9017 issued | (1 << i), num_insns,
9020 packet_group->sorted[upper_slot - 1] = insn;
9028 /* Compare two instructions by their frv_insn_unit. */
9031 frv_compare_insns (const void *first, const void *second)
9033 const rtx *insn1 = first, *insn2 = second;
9034 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
9037 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
9038 and sort it into assembly language order. See frv.md for a description of
9042 frv_sort_insn_group (enum frv_insn_group group)
9044 struct frv_packet_group *packet_group;
9045 unsigned int first, i, nop, max_unit, num_slots;
9046 state_t state, test_state;
9049 packet_group = &frv_packet.groups[group];
9051 /* Assume no nop is needed. */
9052 packet_group->nop = 0;
9054 if (packet_group->num_insns == 0)
9057 /* Copy insns[] to sorted[]. */
9058 memcpy (packet_group->sorted, packet_group->insns,
9059 sizeof (rtx) * packet_group->num_insns);
9061 /* Sort sorted[] by the unit that each insn tries to take first. */
9062 if (packet_group->num_insns > 1)
9063 qsort (packet_group->sorted, packet_group->num_insns,
9064 sizeof (rtx), frv_compare_insns);
9066 /* That's always enough for branch and control insns. */
9067 if (group == GROUP_B || group == GROUP_C)
9070 dfa_size = state_size ();
9071 state = alloca (dfa_size);
9072 test_state = alloca (dfa_size);
9074 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
9075 consecutively and such that the DFA takes unit X when sorted[X]
9076 is added. Set STATE to the new DFA state. */
9077 state_reset (test_state);
9078 for (first = 0; first < packet_group->num_insns; first++)
9080 memcpy (state, test_state, dfa_size);
9081 if (state_transition (test_state, packet_group->sorted[first]) >= 0
9082 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
9086 /* If all the instructions issued in ascending order, we're done. */
9087 if (first == packet_group->num_insns)
9090 /* Add nops to the end of sorted[] and try each permutation until
9091 we find one that works. */
9092 for (nop = 0; nop < frv_num_nops; nop++)
9094 max_unit = frv_insn_unit (frv_nops[nop]);
9095 if (frv_unit_groups[max_unit] == group)
9097 packet_group->nop = frv_nops[nop];
9098 num_slots = UNIT_NUMBER (max_unit) + 1;
9099 for (i = packet_group->num_insns; i < num_slots; i++)
9100 packet_group->sorted[i] = frv_nops[nop];
9101 if (frv_sort_insn_group_1 (group, first, num_slots,
9102 (1 << first) - 1, num_slots, state))
9109 /* Sort the current packet into assembly-language order. Set packing
9110 flags as appropriate. */
9113 frv_reorder_packet (void)
9115 unsigned int cursor[NUM_GROUPS];
9116 rtx insns[ARRAY_SIZE (frv_unit_groups)];
9117 unsigned int unit, to, from;
9118 enum frv_insn_group group;
9119 struct frv_packet_group *packet_group;
9121 /* First sort each group individually. */
9122 for (group = 0; group < NUM_GROUPS; group++)
9125 frv_sort_insn_group (group);
9128 /* Go through the unit template and try add an instruction from
9129 that unit's group. */
9131 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
9133 group = frv_unit_groups[unit];
9134 packet_group = &frv_packet.groups[group];
9135 if (cursor[group] < packet_group->num_insns)
9137 /* frv_reorg should have added nops for us. */
9138 if (packet_group->sorted[cursor[group]] == packet_group->nop)
9140 insns[to++] = packet_group->sorted[cursor[group]++];
9144 if (to != frv_packet.num_insns)
9147 /* Clear the last instruction's packing flag, thus marking the end of
9148 a packet. Reorder the other instructions relative to it. */
9149 CLEAR_PACKING_FLAG (insns[to - 1]);
9150 for (from = 0; from < to - 1; from++)
9152 remove_insn (insns[from]);
9153 add_insn_before (insns[from], insns[to - 1]);
9154 SET_PACKING_FLAG (insns[from]);
9159 /* Divide instructions into packets. Reorder the contents of each
9160 packet so that they are in the correct assembly-language order.
9162 Since this pass can change the raw meaning of the rtl stream, it must
9163 only be called at the last minute, just before the instructions are
9167 frv_pack_insns (void)
9169 if (frv_for_each_packet (frv_reorder_packet))
9170 frv_insn_packing_flag = 0;
9172 frv_insn_packing_flag = -1;
9175 /* See whether we need to add nops to group GROUP in order to
9176 make a valid packet. */
9179 frv_fill_unused_units (enum frv_insn_group group)
9181 unsigned int non_nops, nops, i;
9182 struct frv_packet_group *packet_group;
9184 packet_group = &frv_packet.groups[group];
9186 /* Sort the instructions into assembly-language order.
9187 Use nops to fill slots that are otherwise unused. */
9188 frv_sort_insn_group (group);
9190 /* See how many nops are needed before the final useful instruction. */
9192 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
9193 while (packet_group->sorted[i++] == packet_group->nop)
9196 /* Insert that many nops into the instruction stream. */
9198 frv_insert_nop_in_packet (packet_group->nop);
9201 /* Used by frv_reorg to keep track of the current packet's address. */
9202 static unsigned int frv_packet_address;
9204 /* If the current packet falls through to a label, try to pad the packet
9205 with nops in order to fit the label's alignment requirements. */
9208 frv_align_label (void)
9210 unsigned int alignment, target, nop;
9211 rtx x, last, barrier, label;
9213 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
9214 maximum alignment of that packet, LABEL to the last label between
9215 the packets, and BARRIER to the last barrier. */
9216 last = frv_packet.insns[frv_packet.num_insns - 1];
9217 label = barrier = 0;
9219 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
9223 unsigned int subalign = 1 << label_to_alignment (x);
9224 alignment = MAX (alignment, subalign);
9231 /* If -malign-labels, and the packet falls through to an unaligned
9232 label, try introducing a nop to align that label to 8 bytes. */
9233 if (TARGET_ALIGN_LABELS
9236 && frv_packet.num_insns < frv_packet.issue_rate)
9237 alignment = MAX (alignment, 8);
9239 /* Advance the address to the end of the current packet. */
9240 frv_packet_address += frv_packet.num_insns * 4;
9242 /* Work out the target address, after alignment. */
9243 target = (frv_packet_address + alignment - 1) & -alignment;
9245 /* If the packet falls through to the label, try to find an efficient
9246 padding sequence. */
9249 /* First try adding nops to the current packet. */
9250 for (nop = 0; nop < frv_num_nops; nop++)
9251 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
9253 frv_insert_nop_in_packet (frv_nops[nop]);
9254 frv_packet_address += 4;
9257 /* If we still haven't reached the target, add some new packets that
9258 contain only nops. If there are two types of nop, insert an
9259 alternating sequence of frv_nops[0] and frv_nops[1], which will
9260 lead to packets like:
9267 etc. Just emit frv_nops[0] if that's the only nop we have. */
9268 last = frv_packet.insns[frv_packet.num_insns - 1];
9270 while (frv_packet_address < target)
9272 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
9273 frv_packet_address += 4;
9274 if (frv_num_nops > 1)
9279 frv_packet_address = target;
9282 /* Subroutine of frv_reorg, called after each packet has been constructed
9286 frv_reorg_packet (void)
9288 frv_fill_unused_units (GROUP_I);
9289 frv_fill_unused_units (GROUP_FM);
9293 /* Add an instruction with pattern NOP to frv_nops[]. */
9296 frv_register_nop (rtx nop)
9298 nop = make_insn_raw (nop);
9299 NEXT_INSN (nop) = 0;
9300 PREV_INSN (nop) = 0;
9301 frv_nops[frv_num_nops++] = nop;
9304 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
9305 into packets and check whether we need to insert nops in order to
9306 fulfill the processor's issue requirements. Also, if the user has
9307 requested a certain alignment for a label, try to meet that alignment
9308 by inserting nops in the previous packet. */
9314 frv_register_nop (gen_nop ());
9316 frv_register_nop (gen_mnop ());
9317 if (TARGET_HARD_FLOAT)
9318 frv_register_nop (gen_fnop ());
9320 /* Estimate the length of each branch. Although this may change after
9321 we've inserted nops, it will only do so in big functions. */
9322 shorten_branches (get_insns ());
9324 frv_packet_address = 0;
9325 frv_for_each_packet (frv_reorg_packet);
9328 #define def_builtin(name, type, code) \
9329 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
9331 struct builtin_description
9333 enum insn_code icode;
9335 enum frv_builtins code;
9336 enum rtx_code comparison;
9340 /* Media intrinsics that take a single, constant argument. */
9342 static struct builtin_description bdesc_set[] =
9344 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
9347 /* Media intrinsics that take just one argument. */
9349 static struct builtin_description bdesc_1arg[] =
9351 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
9352 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
9353 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
9354 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
9355 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
9356 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
9359 /* Media intrinsics that take two arguments. */
9361 static struct builtin_description bdesc_2arg[] =
9363 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
9364 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
9365 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
9366 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
9367 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
9368 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
9369 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
9370 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
9371 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
9372 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
9373 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
9374 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
9375 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
9376 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
9377 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
9378 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
9379 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
9380 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
9381 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
9382 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
9383 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
9384 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
9385 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
9386 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
9387 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
9388 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
9389 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
9392 /* Integer intrinsics that take two arguments and have no return value. */
9394 static struct builtin_description bdesc_int_void2arg[] =
9396 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
9397 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
9398 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
9401 static struct builtin_description bdesc_prefetches[] =
9403 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
9404 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
9407 /* Media intrinsics that take two arguments, the first being an ACC number. */
9409 static struct builtin_description bdesc_cut[] =
9411 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
9412 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
9413 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
9416 /* Two-argument media intrinsics with an immediate second argument. */
9418 static struct builtin_description bdesc_2argimm[] =
9420 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
9421 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
9422 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
9423 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
9424 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
9425 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
9426 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
9427 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
9428 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
9429 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
9430 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
9431 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
9432 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
9433 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
9434 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
9435 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
9436 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
9439 /* Media intrinsics that take two arguments and return void, the first argument
9440 being a pointer to 4 words in memory. */
9442 static struct builtin_description bdesc_void2arg[] =
9444 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
9445 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
9448 /* Media intrinsics that take three arguments, the first being a const_int that
9449 denotes an accumulator, and that return void. */
9451 static struct builtin_description bdesc_void3arg[] =
9453 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
9454 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
9455 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
9456 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
9457 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
9458 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
9459 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
9460 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
9461 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
9462 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
9463 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9464 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9465 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9466 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9467 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9468 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9469 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9470 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9471 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9472 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9473 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9474 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9475 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9476 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9477 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9480 /* Media intrinsics that take two accumulator numbers as argument and
9483 static struct builtin_description bdesc_voidacc[] =
9485 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9486 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9487 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9488 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9489 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9490 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9493 /* Initialize media builtins. */
9496 frv_init_builtins (void)
9498 tree endlink = void_list_node;
9499 tree accumulator = integer_type_node;
9500 tree integer = integer_type_node;
9501 tree voidt = void_type_node;
9502 tree uhalf = short_unsigned_type_node;
9503 tree sword1 = long_integer_type_node;
9504 tree uword1 = long_unsigned_type_node;
9505 tree sword2 = long_long_integer_type_node;
9506 tree uword2 = long_long_unsigned_type_node;
9507 tree uword4 = build_pointer_type (uword1);
9508 tree iacc = integer_type_node;
9510 #define UNARY(RET, T1) \
9511 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9513 #define BINARY(RET, T1, T2) \
9514 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9515 tree_cons (NULL_TREE, T2, endlink)))
9517 #define TRINARY(RET, T1, T2, T3) \
9518 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9519 tree_cons (NULL_TREE, T2, \
9520 tree_cons (NULL_TREE, T3, endlink))))
9522 #define QUAD(RET, T1, T2, T3, T4) \
9523 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9524 tree_cons (NULL_TREE, T2, \
9525 tree_cons (NULL_TREE, T3, \
9526 tree_cons (NULL_TREE, T4, endlink)))))
9528 tree void_ftype_void = build_function_type (voidt, endlink);
9530 tree void_ftype_acc = UNARY (voidt, accumulator);
9531 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9532 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9533 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9534 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9535 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9536 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9537 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9538 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9540 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9541 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9542 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9543 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9544 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9545 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9546 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9547 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9548 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9549 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9550 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9552 tree sw1_ftype_int = UNARY (sword1, integer);
9553 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9554 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9556 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9557 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9558 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9559 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9560 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9561 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
9563 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9564 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
9565 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
9566 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
9567 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
9568 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
9569 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
9570 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
9571 tree sw2_ftype_iacc = UNARY (sword2, iacc);
9572 tree sw1_ftype_iacc = UNARY (sword1, iacc);
9573 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
9575 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9576 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9577 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9578 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9579 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9580 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9581 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9582 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9583 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9584 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9585 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9586 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9587 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9588 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9589 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9590 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9591 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9592 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9593 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9594 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9595 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9596 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9597 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9598 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9599 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9600 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9601 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9602 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9603 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9604 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9605 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9606 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9607 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9608 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9609 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9610 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9611 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9612 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9613 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9614 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9615 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9616 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9617 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9618 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9619 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9620 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9621 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9622 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9623 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9624 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
9625 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9626 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9627 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9628 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9629 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9630 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9631 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9632 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9633 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9634 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9635 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9636 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9637 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9638 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9639 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9640 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9641 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9642 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9643 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9644 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9645 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9646 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9647 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9648 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9649 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9650 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9651 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9652 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9653 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9654 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9655 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9656 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9657 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9658 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9659 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
9660 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
9661 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
9662 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
9663 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
9664 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
9665 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
9666 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
9667 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
9668 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
9669 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
9670 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
9671 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
9672 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
9673 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
9674 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
9675 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
9676 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
9677 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
9678 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
9686 /* Set the names for various arithmetic operations according to the
9689 frv_init_libfuncs (void)
9691 set_optab_libfunc (smod_optab, SImode, "__modi");
9692 set_optab_libfunc (umod_optab, SImode, "__umodi");
9694 set_optab_libfunc (add_optab, DImode, "__addll");
9695 set_optab_libfunc (sub_optab, DImode, "__subll");
9696 set_optab_libfunc (smul_optab, DImode, "__mulll");
9697 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9698 set_optab_libfunc (smod_optab, DImode, "__modll");
9699 set_optab_libfunc (umod_optab, DImode, "__umodll");
9700 set_optab_libfunc (and_optab, DImode, "__andll");
9701 set_optab_libfunc (ior_optab, DImode, "__orll");
9702 set_optab_libfunc (xor_optab, DImode, "__xorll");
9703 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9705 set_optab_libfunc (add_optab, SFmode, "__addf");
9706 set_optab_libfunc (sub_optab, SFmode, "__subf");
9707 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9708 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9710 set_optab_libfunc (add_optab, DFmode, "__addd");
9711 set_optab_libfunc (sub_optab, DFmode, "__subd");
9712 set_optab_libfunc (smul_optab, DFmode, "__muld");
9713 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9715 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9716 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9718 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9719 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9720 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9721 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9723 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9724 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9725 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9726 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9728 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9729 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9730 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9731 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9734 /* Convert an integer constant to an accumulator register. ICODE is the
9735 code of the target instruction, OPNUM is the number of the
9736 accumulator operand and OPVAL is the constant integer. Try both
9737 ACC and ACCG registers; only report an error if neither fit the
9741 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9746 /* ACCs and ACCGs are implicity global registers if media intrinsics
9747 are being used. We set up this lazily to avoid creating lots of
9748 unnecessary call_insn rtl in non-media code. */
9749 for (i = 0; i <= ACC_MASK; i++)
9750 if ((i & ACC_MASK) == i)
9751 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
9753 if (GET_CODE (opval) != CONST_INT)
9755 error ("accumulator is not a constant integer");
9758 if ((INTVAL (opval) & ~ACC_MASK) != 0)
9760 error ("accumulator number is out of bounds");
9764 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9765 ACC_FIRST + INTVAL (opval));
9766 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9767 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9769 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9771 error ("inappropriate accumulator for %qs", insn_data[icode].name);
9777 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9780 static enum machine_mode
9781 frv_matching_accg_mode (enum machine_mode mode)
9799 /* Return the accumulator guard that should be paired with accumulator
9800 register ACC. The mode of the returned register is in the same
9801 class as ACC, but is four times smaller. */
9804 frv_matching_accg_for_acc (rtx acc)
9806 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9807 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9810 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9811 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9815 frv_read_argument (tree *arglistptr)
9817 tree next = TREE_VALUE (*arglistptr);
9818 *arglistptr = TREE_CHAIN (*arglistptr);
9819 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9822 /* Like frv_read_argument, but interpret the argument as the number
9823 of an IACC register and return a (reg:MODE ...) rtx for it. */
9826 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
9831 op = frv_read_argument (arglistptr);
9832 if (GET_CODE (op) != CONST_INT
9834 || INTVAL (op) > IACC_LAST - IACC_FIRST
9835 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
9837 error ("invalid IACC argument");
9841 /* IACCs are implicity global registers. We set up this lazily to
9842 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
9844 regno = INTVAL (op) + IACC_FIRST;
9845 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
9846 global_regs[regno + i] = 1;
9848 return gen_rtx_REG (mode, regno);
9851 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9852 The instruction should require a constant operand of some sort. The
9853 function prints an error if OPVAL is not valid. */
9856 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9858 if (GET_CODE (opval) != CONST_INT)
9860 error ("%qs expects a constant argument", insn_data[icode].name);
9863 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9865 error ("constant argument out of range for %qs", insn_data[icode].name);
9871 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9872 if it's not null, has the right mode, and satisfies operand 0's
9876 frv_legitimize_target (enum insn_code icode, rtx target)
9878 enum machine_mode mode = insn_data[icode].operand[0].mode;
9881 || GET_MODE (target) != mode
9882 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9883 return gen_reg_rtx (mode);
9888 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9889 check whether ARG satisfies the operand's constraints. If it doesn't,
9890 copy ARG to a temporary register and return that. Otherwise return ARG
9894 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9896 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9898 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9901 return copy_to_mode_reg (mode, arg);
9904 /* Expand builtins that take a single, constant argument. At the moment,
9905 only MHDSETS falls into this category. */
9908 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9911 rtx op0 = frv_read_argument (&arglist);
9913 if (! frv_check_constant_argument (icode, 1, op0))
9916 target = frv_legitimize_target (icode, target);
9917 pat = GEN_FCN (icode) (target, op0);
9925 /* Expand builtins that take one operand. */
9928 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9931 rtx op0 = frv_read_argument (&arglist);
9933 target = frv_legitimize_target (icode, target);
9934 op0 = frv_legitimize_argument (icode, 1, op0);
9935 pat = GEN_FCN (icode) (target, op0);
9943 /* Expand builtins that take two operands. */
9946 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9949 rtx op0 = frv_read_argument (&arglist);
9950 rtx op1 = frv_read_argument (&arglist);
9952 target = frv_legitimize_target (icode, target);
9953 op0 = frv_legitimize_argument (icode, 1, op0);
9954 op1 = frv_legitimize_argument (icode, 2, op1);
9955 pat = GEN_FCN (icode) (target, op0, op1);
9963 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9967 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9970 rtx op0 = frv_read_argument (&arglist);
9971 rtx op1 = frv_read_argument (&arglist);
9974 target = frv_legitimize_target (icode, target);
9975 op0 = frv_int_to_acc (icode, 1, op0);
9979 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9981 if (! frv_check_constant_argument (icode, 2, op1))
9985 op1 = frv_legitimize_argument (icode, 2, op1);
9987 op2 = frv_matching_accg_for_acc (op0);
9988 pat = GEN_FCN (icode) (target, op0, op1, op2);
9996 /* Expand builtins that take two operands and the second is immediate. */
9999 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
10002 rtx op0 = frv_read_argument (&arglist);
10003 rtx op1 = frv_read_argument (&arglist);
10005 if (! frv_check_constant_argument (icode, 2, op1))
10008 target = frv_legitimize_target (icode, target);
10009 op0 = frv_legitimize_argument (icode, 1, op0);
10010 pat = GEN_FCN (icode) (target, op0, op1);
10018 /* Expand builtins that take two operands, the first operand being a pointer to
10019 ints and return void. */
10022 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
10025 rtx op0 = frv_read_argument (&arglist);
10026 rtx op1 = frv_read_argument (&arglist);
10027 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10030 if (GET_CODE (op0) != MEM)
10034 if (! offsettable_address_p (0, mode0, op0))
10036 reg = gen_reg_rtx (Pmode);
10037 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
10040 op0 = gen_rtx_MEM (SImode, reg);
10043 addr = XEXP (op0, 0);
10044 if (! offsettable_address_p (0, mode0, addr))
10045 addr = copy_to_mode_reg (Pmode, op0);
10047 op0 = change_address (op0, V4SImode, addr);
10048 op1 = frv_legitimize_argument (icode, 1, op1);
10049 pat = GEN_FCN (icode) (op0, op1);
10057 /* Expand builtins that take two long operands and return void. */
10060 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
10063 rtx op0 = frv_read_argument (&arglist);
10064 rtx op1 = frv_read_argument (&arglist);
10066 op0 = frv_legitimize_argument (icode, 1, op0);
10067 op1 = frv_legitimize_argument (icode, 1, op1);
10068 pat = GEN_FCN (icode) (op0, op1);
10076 /* Expand prefetch builtins. These take a single address as argument. */
10079 frv_expand_prefetches (enum insn_code icode, tree arglist)
10082 rtx op0 = frv_read_argument (&arglist);
10084 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
10092 /* Expand builtins that take three operands and return void. The first
10093 argument must be a constant that describes a pair or quad accumulators. A
10094 fourth argument is created that is the accumulator guard register that
10095 corresponds to the accumulator. */
10098 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
10101 rtx op0 = frv_read_argument (&arglist);
10102 rtx op1 = frv_read_argument (&arglist);
10103 rtx op2 = frv_read_argument (&arglist);
10106 op0 = frv_int_to_acc (icode, 0, op0);
10110 op1 = frv_legitimize_argument (icode, 1, op1);
10111 op2 = frv_legitimize_argument (icode, 2, op2);
10112 op3 = frv_matching_accg_for_acc (op0);
10113 pat = GEN_FCN (icode) (op0, op1, op2, op3);
10121 /* Expand builtins that perform accumulator-to-accumulator operations.
10122 These builtins take two accumulator numbers as argument and return
10126 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
10129 rtx op0 = frv_read_argument (&arglist);
10130 rtx op1 = frv_read_argument (&arglist);
10134 op0 = frv_int_to_acc (icode, 0, op0);
10138 op1 = frv_int_to_acc (icode, 1, op1);
10142 op2 = frv_matching_accg_for_acc (op0);
10143 op3 = frv_matching_accg_for_acc (op1);
10144 pat = GEN_FCN (icode) (op0, op1, op2, op3);
10152 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
10153 each argument forms one word of the two double-word input registers.
10154 ARGLIST is a TREE_LIST of the arguments and TARGET, if nonnull,
10155 suggests a good place to put the return value. */
10158 frv_expand_mdpackh_builtin (tree arglist, rtx target)
10160 enum insn_code icode = CODE_FOR_mdpackh;
10162 rtx arg1 = frv_read_argument (&arglist);
10163 rtx arg2 = frv_read_argument (&arglist);
10164 rtx arg3 = frv_read_argument (&arglist);
10165 rtx arg4 = frv_read_argument (&arglist);
10167 target = frv_legitimize_target (icode, target);
10168 op0 = gen_reg_rtx (DImode);
10169 op1 = gen_reg_rtx (DImode);
10171 /* The high half of each word is not explicitly initialised, so indicate
10172 that the input operands are not live before this point. */
10173 emit_insn (gen_rtx_CLOBBER (DImode, op0));
10174 emit_insn (gen_rtx_CLOBBER (DImode, op1));
10176 /* Move each argument into the low half of its associated input word. */
10177 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
10178 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
10179 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
10180 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
10182 pat = GEN_FCN (icode) (target, op0, op1);
10190 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
10191 number as argument. */
10194 frv_expand_mclracc_builtin (tree arglist)
10196 enum insn_code icode = CODE_FOR_mclracc;
10198 rtx op0 = frv_read_argument (&arglist);
10200 op0 = frv_int_to_acc (icode, 0, op0);
10204 pat = GEN_FCN (icode) (op0);
10211 /* Expand builtins that take no arguments. */
10214 frv_expand_noargs_builtin (enum insn_code icode)
10216 rtx pat = GEN_FCN (icode) (const0_rtx);
10223 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
10224 number or accumulator guard number as argument and return an SI integer. */
10227 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
10230 rtx target = gen_reg_rtx (SImode);
10231 rtx op0 = frv_read_argument (&arglist);
10233 op0 = frv_int_to_acc (icode, 1, op0);
10237 pat = GEN_FCN (icode) (target, op0);
10245 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
10246 accumulator guard as their first argument and an SImode value as their
10250 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
10253 rtx op0 = frv_read_argument (&arglist);
10254 rtx op1 = frv_read_argument (&arglist);
10256 op0 = frv_int_to_acc (icode, 0, op0);
10260 op1 = frv_legitimize_argument (icode, 1, op1);
10261 pat = GEN_FCN (icode) (op0, op1);
10268 /* Emit a move from SRC to DEST in SImode chunks. This can be used
10269 to move DImode values into and out of IACC0. */
10272 frv_split_iacc_move (rtx dest, rtx src)
10274 enum machine_mode inner;
10277 inner = GET_MODE (dest);
10278 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
10279 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
10280 simplify_gen_subreg (SImode, src, inner, i));
10283 /* Expand builtins. */
10286 frv_expand_builtin (tree exp,
10288 rtx subtarget ATTRIBUTE_UNUSED,
10289 enum machine_mode mode ATTRIBUTE_UNUSED,
10290 int ignore ATTRIBUTE_UNUSED)
10292 tree arglist = TREE_OPERAND (exp, 1);
10293 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10294 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
10296 struct builtin_description *d;
10298 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
10300 error ("media functions are not available unless -mmedia is used");
10306 case FRV_BUILTIN_MCOP1:
10307 case FRV_BUILTIN_MCOP2:
10308 case FRV_BUILTIN_MDUNPACKH:
10309 case FRV_BUILTIN_MBTOHE:
10310 if (! TARGET_MEDIA_REV1)
10312 error ("this media function is only available on the fr500");
10317 case FRV_BUILTIN_MQXMACHS:
10318 case FRV_BUILTIN_MQXMACXHS:
10319 case FRV_BUILTIN_MQMACXHS:
10320 case FRV_BUILTIN_MADDACCS:
10321 case FRV_BUILTIN_MSUBACCS:
10322 case FRV_BUILTIN_MASACCS:
10323 case FRV_BUILTIN_MDADDACCS:
10324 case FRV_BUILTIN_MDSUBACCS:
10325 case FRV_BUILTIN_MDASACCS:
10326 case FRV_BUILTIN_MABSHS:
10327 case FRV_BUILTIN_MDROTLI:
10328 case FRV_BUILTIN_MCPLHI:
10329 case FRV_BUILTIN_MCPLI:
10330 case FRV_BUILTIN_MDCUTSSI:
10331 case FRV_BUILTIN_MQSATHS:
10332 case FRV_BUILTIN_MHSETLOS:
10333 case FRV_BUILTIN_MHSETLOH:
10334 case FRV_BUILTIN_MHSETHIS:
10335 case FRV_BUILTIN_MHSETHIH:
10336 case FRV_BUILTIN_MHDSETS:
10337 case FRV_BUILTIN_MHDSETH:
10338 if (! TARGET_MEDIA_REV2)
10340 error ("this media function is only available on the fr400"
10346 case FRV_BUILTIN_SMASS:
10347 case FRV_BUILTIN_SMSSS:
10348 case FRV_BUILTIN_SMU:
10349 case FRV_BUILTIN_ADDSS:
10350 case FRV_BUILTIN_SUBSS:
10351 case FRV_BUILTIN_SLASS:
10352 case FRV_BUILTIN_SCUTSS:
10353 case FRV_BUILTIN_IACCreadll:
10354 case FRV_BUILTIN_IACCreadl:
10355 case FRV_BUILTIN_IACCsetll:
10356 case FRV_BUILTIN_IACCsetl:
10357 if (!TARGET_FR405_BUILTINS)
10359 error ("this builtin function is only available"
10360 " on the fr405 and fr450");
10365 case FRV_BUILTIN_PREFETCH:
10366 if (!TARGET_FR500_FR550_BUILTINS)
10368 error ("this builtin function is only available on the fr500"
10374 case FRV_BUILTIN_MQLCLRHS:
10375 case FRV_BUILTIN_MQLMTHS:
10376 case FRV_BUILTIN_MQSLLHI:
10377 case FRV_BUILTIN_MQSRAHI:
10378 if (!TARGET_MEDIA_FR450)
10380 error ("this builtin function is only available on the fr450");
10389 /* Expand unique builtins. */
10393 case FRV_BUILTIN_MTRAP:
10394 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
10396 case FRV_BUILTIN_MCLRACC:
10397 return frv_expand_mclracc_builtin (arglist);
10399 case FRV_BUILTIN_MCLRACCA:
10401 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
10403 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
10405 case FRV_BUILTIN_MRDACC:
10406 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
10408 case FRV_BUILTIN_MRDACCG:
10409 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
10411 case FRV_BUILTIN_MWTACC:
10412 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
10414 case FRV_BUILTIN_MWTACCG:
10415 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
10417 case FRV_BUILTIN_MDPACKH:
10418 return frv_expand_mdpackh_builtin (arglist, target);
10420 case FRV_BUILTIN_IACCreadll:
10422 rtx src = frv_read_iacc_argument (DImode, &arglist);
10423 if (target == 0 || !REG_P (target))
10424 target = gen_reg_rtx (DImode);
10425 frv_split_iacc_move (target, src);
10429 case FRV_BUILTIN_IACCreadl:
10430 return frv_read_iacc_argument (SImode, &arglist);
10432 case FRV_BUILTIN_IACCsetll:
10434 rtx dest = frv_read_iacc_argument (DImode, &arglist);
10435 rtx src = frv_read_argument (&arglist);
10436 frv_split_iacc_move (dest, force_reg (DImode, src));
10440 case FRV_BUILTIN_IACCsetl:
10442 rtx dest = frv_read_iacc_argument (SImode, &arglist);
10443 rtx src = frv_read_argument (&arglist);
10444 emit_move_insn (dest, force_reg (SImode, src));
10452 /* Expand groups of builtins. */
10454 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
10455 if (d->code == fcode)
10456 return frv_expand_set_builtin (d->icode, arglist, target);
10458 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10459 if (d->code == fcode)
10460 return frv_expand_unop_builtin (d->icode, arglist, target);
10462 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10463 if (d->code == fcode)
10464 return frv_expand_binop_builtin (d->icode, arglist, target);
10466 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
10467 if (d->code == fcode)
10468 return frv_expand_cut_builtin (d->icode, arglist, target);
10470 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
10471 if (d->code == fcode)
10472 return frv_expand_binopimm_builtin (d->icode, arglist, target);
10474 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
10475 if (d->code == fcode)
10476 return frv_expand_voidbinop_builtin (d->icode, arglist);
10478 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
10479 if (d->code == fcode)
10480 return frv_expand_voidtriop_builtin (d->icode, arglist);
10482 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
10483 if (d->code == fcode)
10484 return frv_expand_voidaccop_builtin (d->icode, arglist);
10486 for (i = 0, d = bdesc_int_void2arg;
10487 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
10488 if (d->code == fcode)
10489 return frv_expand_int_void2arg (d->icode, arglist);
10491 for (i = 0, d = bdesc_prefetches;
10492 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
10493 if (d->code == fcode)
10494 return frv_expand_prefetches (d->icode, arglist);
10500 frv_in_small_data_p (tree decl)
10502 HOST_WIDE_INT size;
10505 /* Don't apply the -G flag to internal compiler structures. We
10506 should leave such structures in the main data section, partly
10507 for efficiency and partly because the size of some of them
10508 (such as C++ typeinfos) is not known until later. */
10509 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
10512 /* If we already know which section the decl should be in, see if
10513 it's a small data section. */
10514 section_name = DECL_SECTION_NAME (decl);
10517 if (TREE_CODE (section_name) != STRING_CST)
10519 if (frv_string_begins_with (section_name, ".sdata"))
10521 if (frv_string_begins_with (section_name, ".sbss"))
10526 size = int_size_in_bytes (TREE_TYPE (decl));
10527 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
10534 frv_rtx_costs (rtx x,
10535 int code ATTRIBUTE_UNUSED,
10536 int outer_code ATTRIBUTE_UNUSED,
10539 if (outer_code == MEM)
10541 /* Don't differentiate between memory addresses. All the ones
10542 we accept have equal cost. */
10543 *total = COSTS_N_INSNS (0);
10550 /* Make 12 bit integers really cheap. */
10551 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
10556 /* Fall through. */
10562 *total = COSTS_N_INSNS (2);
10576 if (GET_MODE (x) == SImode)
10577 *total = COSTS_N_INSNS (1);
10578 else if (GET_MODE (x) == DImode)
10579 *total = COSTS_N_INSNS (2);
10581 *total = COSTS_N_INSNS (3);
10585 if (GET_MODE (x) == SImode)
10586 *total = COSTS_N_INSNS (2);
10588 *total = COSTS_N_INSNS (6); /* guess */
10595 *total = COSTS_N_INSNS (18);
10599 *total = COSTS_N_INSNS (3);
10608 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10611 assemble_align (POINTER_SIZE);
10614 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10618 assemble_integer_with_op ("\t.picptr\t", symbol);
10622 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10625 assemble_align (POINTER_SIZE);
10628 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10632 assemble_integer_with_op ("\t.picptr\t", symbol);
10635 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10638 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
10639 int incoming ATTRIBUTE_UNUSED)
10641 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
10644 #define TLS_BIAS (2048 - 16)
10646 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
10647 We need to emit DTP-relative relocations. */
10650 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
10654 fputs ("\t.picptr\ttlsmoff(", file);
10655 /* We want the unbiased TLS offset, so add the bias to the
10656 expression, such that the implicit biasing cancels out. */
10657 output_addr_const (file, plus_constant (x, TLS_BIAS));
10661 #include "gt-frv.h"