1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
52 #define FRV_INLINE inline
55 /* Temporary register allocation support structure. */
56 typedef struct frv_tmp_reg_struct
58 HARD_REG_SET regs; /* possible registers to allocate */
59 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
63 /* Register state information for VLIW re-packing phase. These values must fit
64 within an unsigned char. */
65 #define REGSTATE_DEAD 0x00 /* register is currently dead */
66 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
67 #define REGSTATE_LIVE 0x08 /* register is live */
68 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
69 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
70 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
71 #define REGSTATE_UNUSED 0x80 /* bit for hire */
72 #define REGSTATE_MASK 0xff /* mask for the bits to set */
74 /* conditional expression used */
75 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
77 /* the following is not sure in the reg_state bytes, so can have a larger value
79 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
81 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
89 /* Information required by frv_frame_access. */
92 /* This field is FRV_LOAD if registers are to be loaded from the stack and
93 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
94 the move is being done by the prologue code while FRV_LOAD implies it
95 is being done by the epilogue. */
98 /* The base register to use when accessing the stack. This may be the
99 frame pointer, stack pointer, or a temporary. The choice of register
100 depends on which part of the frame is being accessed and how big the
104 /* The offset of BASE from the bottom of the current frame, in bytes. */
106 } frv_frame_accessor_t;
108 /* Define the information needed to generate branch and scc insns. This is
109 stored from the compare operation. */
113 /* Conditional execution support gathered together in one structure */
116 /* Linked list of insns to add if the conditional execution conversion was
117 successful. Each link points to an EXPR_LIST which points to the pattern
118 of the insn to add, and the insn to be inserted before. */
119 rtx added_insns_list;
121 /* Identify which registers are safe to allocate for if conversions to
122 conditional execution. We keep the last allocated register in the
123 register classes between COND_EXEC statements. This will mean we allocate
124 different registers for each different COND_EXEC group if we can. This
125 might allow the scheduler to intermix two different COND_EXEC sections. */
126 frv_tmp_reg_t tmp_reg;
128 /* For nested IFs, identify which CC registers are used outside of setting
129 via a compare isnsn, and using via a check insn. This will allow us to
130 know if we can rewrite the register to use a different register that will
131 be paired with the CR register controlling the nested IF-THEN blocks. */
132 HARD_REG_SET nested_cc_ok_rewrite;
134 /* Temporary registers allocated to hold constants during conditional
136 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
138 /* Current number of temp registers available. */
139 int cur_scratch_regs;
141 /* Number of nested conditional execution blocks */
142 int num_nested_cond_exec;
144 /* Map of insns that set up constants in scratch registers. */
145 bitmap scratch_insns_bitmap;
147 /* Conditional execution test register (CC0..CC7) */
150 /* Conditional execution compare register that is paired with cr_reg, so that
151 nested compares can be done. The csubcc and caddcc instructions don't
152 have enough bits to specify both a CC register to be set and a CR register
153 to do the test on, so the same bit number is used for both. Needless to
154 say, this is rather inconvient for GCC. */
157 /* Extra CR registers used for &&, ||. */
161 /* Previous CR used in nested if, to make sure we are dealing with the same
162 nested if as the previous statement. */
163 rtx last_nested_if_cr;
167 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
169 /* Map register number to smallest register class. */
170 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
172 /* Map class letter into register class */
173 enum reg_class reg_class_from_letter[256];
175 /* Cached value of frv_stack_info */
176 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
178 /* -mbranch-cost= support */
179 const char *frv_branch_cost_string;
180 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
183 const char *frv_cpu_string; /* -mcpu= option */
184 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
186 /* -mcond-exec-insns= support */
187 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
188 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
190 /* -mcond-exec-temps= support */
191 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
192 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
194 /* -msched-lookahead=n */
195 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
196 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
198 /* Forward references */
199 static int frv_default_flags_for_cpu PARAMS ((void));
200 static int frv_string_begins_with PARAMS ((tree, const char *));
201 static FRV_INLINE int symbol_ref_small_data_p PARAMS ((rtx));
202 static FRV_INLINE int const_small_data_p PARAMS ((rtx));
203 static FRV_INLINE int plus_small_data_p PARAMS ((rtx, rtx));
204 static void frv_print_operand_memory_reference_reg
205 PARAMS ((FILE *, rtx));
206 static void frv_print_operand_memory_reference PARAMS ((FILE *, rtx, int));
207 static int frv_print_operand_jump_hint PARAMS ((rtx));
208 static FRV_INLINE int frv_regno_ok_for_base_p PARAMS ((int, int));
209 static rtx single_set_pattern PARAMS ((rtx));
210 static int frv_function_contains_far_jump PARAMS ((void));
211 static rtx frv_alloc_temp_reg PARAMS ((frv_tmp_reg_t *,
215 static rtx frv_frame_offset_rtx PARAMS ((int));
216 static rtx frv_frame_mem PARAMS ((enum machine_mode,
218 static rtx frv_dwarf_store PARAMS ((rtx, int));
219 static void frv_frame_insn PARAMS ((rtx, rtx));
220 static void frv_frame_access PARAMS ((frv_frame_accessor_t*,
222 static void frv_frame_access_multi PARAMS ((frv_frame_accessor_t*,
223 frv_stack_t *, int));
224 static void frv_frame_access_standard_regs PARAMS ((enum frv_stack_op,
226 static struct machine_function *frv_init_machine_status PARAMS ((void));
227 static int frv_legitimate_memory_operand PARAMS ((rtx,
230 static rtx frv_int_to_acc PARAMS ((enum insn_code,
232 static enum machine_mode frv_matching_accg_mode PARAMS ((enum machine_mode));
233 static rtx frv_read_argument PARAMS ((tree *));
234 static int frv_check_constant_argument PARAMS ((enum insn_code,
236 static rtx frv_legitimize_target PARAMS ((enum insn_code, rtx));
237 static rtx frv_legitimize_argument PARAMS ((enum insn_code,
239 static rtx frv_expand_set_builtin PARAMS ((enum insn_code,
241 static rtx frv_expand_unop_builtin PARAMS ((enum insn_code,
243 static rtx frv_expand_binop_builtin PARAMS ((enum insn_code,
245 static rtx frv_expand_cut_builtin PARAMS ((enum insn_code,
247 static rtx frv_expand_binopimm_builtin PARAMS ((enum insn_code,
249 static rtx frv_expand_voidbinop_builtin PARAMS ((enum insn_code,
251 static rtx frv_expand_voidtriop_builtin PARAMS ((enum insn_code,
253 static rtx frv_expand_voidaccop_builtin PARAMS ((enum insn_code,
255 static rtx frv_expand_mclracc_builtin PARAMS ((tree));
256 static rtx frv_expand_mrdacc_builtin PARAMS ((enum insn_code,
258 static rtx frv_expand_mwtacc_builtin PARAMS ((enum insn_code,
260 static rtx frv_expand_noargs_builtin PARAMS ((enum insn_code));
261 static rtx frv_emit_comparison PARAMS ((enum rtx_code, rtx,
263 static int frv_clear_registers_used PARAMS ((rtx *, void *));
264 static void frv_ifcvt_add_insn PARAMS ((rtx, rtx, int));
265 static rtx frv_ifcvt_rewrite_mem PARAMS ((rtx,
268 static rtx frv_ifcvt_load_value PARAMS ((rtx, rtx));
269 static void frv_registers_update PARAMS ((rtx, unsigned char [],
270 int [], int *, int));
271 static int frv_registers_used_p PARAMS ((rtx, unsigned char [],
273 static int frv_registers_set_p PARAMS ((rtx, unsigned char [],
275 static void frv_pack_insns PARAMS ((void));
276 static void frv_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
277 static void frv_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
278 static bool frv_assemble_integer PARAMS ((rtx, unsigned, int));
279 static const char * frv_strip_name_encoding PARAMS ((const char *));
280 static void frv_encode_section_info PARAMS ((tree, int));
281 static void frv_init_builtins PARAMS ((void));
282 static rtx frv_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
283 static bool frv_in_small_data_p PARAMS ((tree));
284 static void frv_asm_output_mi_thunk
285 PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree));
287 /* Initialize the GCC target structure. */
288 #undef TARGET_ASM_FUNCTION_PROLOGUE
289 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
290 #undef TARGET_ASM_FUNCTION_EPILOGUE
291 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
292 #undef TARGET_ASM_INTEGER
293 #define TARGET_ASM_INTEGER frv_assemble_integer
294 #undef TARGET_STRIP_NAME_ENCODING
295 #define TARGET_STRIP_NAME_ENCODING frv_strip_name_encoding
296 #undef TARGET_ENCODE_SECTION_INFO
297 #define TARGET_ENCODE_SECTION_INFO frv_encode_section_info
298 #undef TARGET_INIT_BUILTINS
299 #define TARGET_INIT_BUILTINS frv_init_builtins
300 #undef TARGET_EXPAND_BUILTIN
301 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
302 #undef TARGET_IN_SMALL_DATA_P
303 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
305 #undef TARGET_ASM_OUTPUT_MI_THUNK
306 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
307 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
308 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
310 struct gcc_target targetm = TARGET_INITIALIZER;
312 /* Given a SYMBOL_REF, return true if it points to small data. */
314 static FRV_INLINE int
315 symbol_ref_small_data_p (x)
318 return SDATA_NAME_P (XSTR (x, 0));
321 /* Given a CONST, return true if the symbol_ref points to small data. */
323 static FRV_INLINE int
324 const_small_data_p (x)
329 if (GET_CODE (XEXP (x, 0)) != PLUS)
332 x0 = XEXP (XEXP (x, 0), 0);
333 if (GET_CODE (x0) != SYMBOL_REF || !SDATA_NAME_P (XSTR (x0, 0)))
336 x1 = XEXP (XEXP (x, 0), 1);
337 if (GET_CODE (x1) != CONST_INT
338 || !IN_RANGE_P (INTVAL (x1), -2048, 2047))
344 /* Given a PLUS, return true if this is a small data reference. */
346 static FRV_INLINE int
347 plus_small_data_p (op0, op1)
351 if (GET_MODE (op0) == SImode
352 && GET_CODE (op0) == REG
353 && REGNO (op0) == SDA_BASE_REG)
355 if (GET_CODE (op1) == SYMBOL_REF)
356 return symbol_ref_small_data_p (op1);
358 if (GET_CODE (op1) == CONST)
359 return const_small_data_p (op1);
367 frv_default_flags_for_cpu ()
369 switch (frv_cpu_type)
371 case FRV_CPU_GENERIC:
372 return MASK_DEFAULT_FRV;
376 return MASK_DEFAULT_FR500;
379 return MASK_DEFAULT_FR400;
383 return MASK_DEFAULT_SIMPLE;
388 /* Sometimes certain combinations of command options do not make
389 sense on a particular target machine. You can define a macro
390 `OVERRIDE_OPTIONS' to take account of this. This macro, if
391 defined, is executed once just after all the command options have
394 Don't use this macro to turn on various extra optimizations for
395 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
398 frv_override_options ()
402 /* Set the cpu type */
405 if (strcmp (frv_cpu_string, "simple") == 0)
406 frv_cpu_type = FRV_CPU_SIMPLE;
408 else if (strcmp (frv_cpu_string, "tomcat") == 0)
409 frv_cpu_type = FRV_CPU_TOMCAT;
411 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
412 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
416 const char *p = frv_cpu_string + sizeof ("fr") - 1;
417 if (strcmp (p, "500") == 0)
418 frv_cpu_type = FRV_CPU_FR500;
420 else if (strcmp (p, "400") == 0)
421 frv_cpu_type = FRV_CPU_FR400;
423 else if (strcmp (p, "300") == 0)
424 frv_cpu_type = FRV_CPU_FR300;
426 else if (strcmp (p, "v") == 0)
427 frv_cpu_type = FRV_CPU_GENERIC;
430 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
434 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
436 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
437 linker about linking pic and non-pic code. */
440 if (!flag_pic) /* -fPIC */
443 if (! g_switch_set) /* -G0 */
450 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
452 if (write_symbols == DWARF_DEBUG && flag_pic)
453 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
455 /* Change the branch cost value */
456 if (frv_branch_cost_string)
457 frv_branch_cost_int = atoi (frv_branch_cost_string);
459 /* Change the # of insns to be converted to conditional execution */
460 if (frv_condexec_insns_str)
461 frv_condexec_insns = atoi (frv_condexec_insns_str);
463 /* Change # of temporary registers used to hold integer constants */
464 if (frv_condexec_temps_str)
465 frv_condexec_temps = atoi (frv_condexec_temps_str);
467 /* Change scheduling look ahead. */
468 if (frv_sched_lookahead_str)
469 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
471 /* A C expression whose value is a register class containing hard
472 register REGNO. In general there is more than one such class;
473 choose a class which is "minimal", meaning that no smaller class
474 also contains the register. */
476 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
478 enum reg_class class;
482 int gpr_reg = regno - GPR_FIRST;
483 if ((gpr_reg & 3) == 0)
486 else if ((gpr_reg & 1) == 0)
493 else if (FPR_P (regno))
495 int fpr_reg = regno - GPR_FIRST;
496 if ((fpr_reg & 3) == 0)
497 class = QUAD_FPR_REGS;
499 else if ((fpr_reg & 1) == 0)
506 else if (regno == LR_REGNO)
509 else if (regno == LCR_REGNO)
512 else if (ICC_P (regno))
515 else if (FCC_P (regno))
518 else if (ICR_P (regno))
521 else if (FCR_P (regno))
524 else if (ACC_P (regno))
526 int r = regno - ACC_FIRST;
528 class = QUAD_ACC_REGS;
529 else if ((r & 1) == 0)
530 class = EVEN_ACC_REGS;
535 else if (ACCG_P (regno))
541 regno_reg_class[regno] = class;
544 /* Check for small data option */
546 g_switch_value = SDATA_DEFAULT_SIZE;
548 /* A C expression which defines the machine-dependent operand
549 constraint letters for register classes. If CHAR is such a
550 letter, the value should be the register class corresponding to
551 it. Otherwise, the value should be `NO_REGS'. The register
552 letter `r', corresponding to class `GENERAL_REGS', will not be
553 passed to this macro; you do not need to handle it.
555 The following letters are unavailable, due to being used as
560 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
561 'Q', 'R', 'S', 'T', 'U'
563 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
565 for (i = 0; i < 256; i++)
566 reg_class_from_letter[i] = NO_REGS;
568 reg_class_from_letter['a'] = ACC_REGS;
569 reg_class_from_letter['b'] = EVEN_ACC_REGS;
570 reg_class_from_letter['c'] = CC_REGS;
571 reg_class_from_letter['d'] = GPR_REGS;
572 reg_class_from_letter['e'] = EVEN_REGS;
573 reg_class_from_letter['f'] = FPR_REGS;
574 reg_class_from_letter['h'] = FEVEN_REGS;
575 reg_class_from_letter['l'] = LR_REG;
576 reg_class_from_letter['q'] = QUAD_REGS;
577 reg_class_from_letter['t'] = ICC_REGS;
578 reg_class_from_letter['u'] = FCC_REGS;
579 reg_class_from_letter['v'] = ICR_REGS;
580 reg_class_from_letter['w'] = FCR_REGS;
581 reg_class_from_letter['x'] = QUAD_FPR_REGS;
582 reg_class_from_letter['y'] = LCR_REG;
583 reg_class_from_letter['z'] = SPR_REGS;
584 reg_class_from_letter['A'] = QUAD_ACC_REGS;
585 reg_class_from_letter['B'] = ACCG_REGS;
586 reg_class_from_letter['C'] = CR_REGS;
588 /* There is no single unaligned SI op for PIC code. Sometimes we
589 need to use ".4byte" and sometimes we need to use ".picptr".
590 See frv_assemble_integer for details. */
592 targetm.asm_out.unaligned_op.si = 0;
594 init_machine_status = frv_init_machine_status;
598 /* Some machines may desire to change what optimizations are performed for
599 various optimization levels. This macro, if defined, is executed once just
600 after the optimization level is determined and before the remainder of the
601 command options have been parsed. Values set in this macro are used as the
602 default values for the other command line options.
604 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
605 `-O' is specified, and 0 if neither is specified.
607 SIZE is nonzero if `-Os' is specified, 0 otherwise.
609 You should not use this macro to change options that are not
610 machine-specific. These should uniformly selected by the same optimization
611 level on all supported machines. Use this macro to enable machbine-specific
614 *Do not examine `write_symbols' in this macro!* The debugging options are
615 *not supposed to alter the generated code. */
617 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
618 scheduling pass at the current time. */
620 frv_optimization_options (level, size)
622 int size ATTRIBUTE_UNUSED;
626 #ifdef DISABLE_SCHED2
627 flag_schedule_insns_after_reload = 0;
636 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
639 frv_string_begins_with (name, prefix)
643 int prefix_len = strlen (prefix);
645 /* Remember: NAME's length includes the null terminator. */
646 return (TREE_STRING_LENGTH (name) > prefix_len
647 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
650 /* Encode section information of DECL, which is either a VAR_DECL,
651 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
653 For the FRV we want to record:
655 - whether the object lives in .sdata/.sbss.
656 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
661 frv_encode_section_info (decl, first)
667 if (TREE_CODE (decl) == VAR_DECL)
669 int size = int_size_in_bytes (TREE_TYPE (decl));
670 tree section_name = DECL_SECTION_NAME (decl);
673 /* Don't apply the -G flag to internal compiler structures. We
674 should leave such structures in the main data section, partly
675 for efficiency and partly because the size of some of them
676 (such as C++ typeinfos) is not known until later. */
677 if (!DECL_ARTIFICIAL (decl) && size > 0 && size <= g_switch_value)
680 /* If we already know which section the decl should be in, see if
681 it's a small data section. */
684 if (TREE_CODE (section_name) == STRING_CST)
686 if (frv_string_begins_with (section_name, ".sdata"))
688 if (frv_string_begins_with (section_name, ".sbss"))
697 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
698 char * str = xmalloc (2 + strlen (XSTR (sym_ref, 0)));
700 str[0] = SDATA_FLAG_CHAR;
701 strcpy (&str[1], XSTR (sym_ref, 0));
702 XSTR (sym_ref, 0) = str;
708 /* Zero or more C statements that may conditionally modify two variables
709 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
710 been initialized from the two preceding macros.
712 This is necessary in case the fixed or call-clobbered registers depend on
715 You need not define this macro if it has no work to do.
717 If the usage of an entire class of registers depends on the target flags,
718 you may indicate this to GCC by using this macro to modify `fixed_regs' and
719 `call_used_regs' to 1 for each of the registers in the classes which should
720 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
721 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
723 (However, if this class is not included in `GENERAL_REGS' and all of the
724 insn patterns whose constraints permit this class are controlled by target
725 switches, then GCC will automatically avoid using these registers when the
726 target switches are opposed to them.) */
729 frv_conditional_register_usage ()
733 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
734 fixed_regs[i] = call_used_regs[i] = 1;
736 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
737 fixed_regs[i] = call_used_regs[i] = 1;
739 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
740 fixed_regs[i] = call_used_regs[i] = 1;
742 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
743 fixed_regs[i] = call_used_regs[i] = 1;
745 /* Reserve the registers used for conditional execution. At present, we need
746 1 ICC and 1 ICR register. */
747 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
748 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
752 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
753 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
754 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
755 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
759 /* If -fpic, SDA_BASE_REG is the PIC register. */
760 if (g_switch_value == 0 && !flag_pic)
761 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
764 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
770 * Compute the stack frame layout
773 * +---------------+-----------------------+-----------------------+
774 * |Register |type |caller-save/callee-save|
775 * +---------------+-----------------------+-----------------------+
776 * |GR0 |Zero register | - |
777 * |GR1 |Stack pointer(SP) | - |
778 * |GR2 |Frame pointer(FP) | - |
779 * |GR3 |Hidden parameter | caller save |
780 * |GR4-GR7 | - | caller save |
781 * |GR8-GR13 |Argument register | caller save |
782 * |GR14-GR15 | - | caller save |
783 * |GR16-GR31 | - | callee save |
784 * |GR32-GR47 | - | caller save |
785 * |GR48-GR63 | - | callee save |
786 * |FR0-FR15 | - | caller save |
787 * |FR16-FR31 | - | callee save |
788 * |FR32-FR47 | - | caller save |
789 * |FR48-FR63 | - | callee save |
790 * +---------------+-----------------------+-----------------------+
794 * SP-> |-----------------------------------|
796 * |-----------------------------------|
797 * | Register save area |
798 * |-----------------------------------|
799 * | Local variable save area |
800 * FP-> |-----------------------------------|
802 * |-----------------------------------|
803 * | Hidden parameter save area |
804 * |-----------------------------------|
805 * | Return address(LR) storage area |
806 * |-----------------------------------|
807 * | Padding for alignment |
808 * |-----------------------------------|
809 * | Register argument area |
810 * OLD SP-> |-----------------------------------|
812 * |-----------------------------------|
815 * Argument area/Parameter area:
817 * When a function is called, this area is used for argument transfer. When
818 * the argument is set up by the caller function, this area is referred to as
819 * the argument area. When the argument is referenced by the callee function,
820 * this area is referred to as the parameter area. The area is allocated when
821 * all arguments cannot be placed on the argument register at the time of
824 * Register save area:
826 * This is a register save area that must be guaranteed for the caller
827 * function. This area is not secured when the register save operation is not
830 * Local variable save area:
832 * This is the area for local variables and temporary variables.
836 * This area stores the FP value of the caller function.
838 * Hidden parameter save area:
840 * This area stores the start address of the return value storage
841 * area for a struct/union return function.
842 * When a struct/union is used as the return value, the caller
843 * function stores the return value storage area start address in
844 * register GR3 and passes it to the caller function.
845 * The callee function interprets the address stored in the GR3
846 * as the return value storage area start address.
847 * When register GR3 needs to be saved into memory, the callee
848 * function saves it in the hidden parameter save area. This
849 * area is not secured when the save operation is not needed.
851 * Return address(LR) storage area:
853 * This area saves the LR. The LR stores the address of a return to the caller
854 * function for the purpose of function calling.
856 * Argument register area:
858 * This area saves the argument register. This area is not secured when the
859 * save operation is not needed.
863 * Arguments, the count of which equals the count of argument registers (6
864 * words), are positioned in registers GR8 to GR13 and delivered to the callee
865 * function. When a struct/union return function is called, the return value
866 * area address is stored in register GR3. Arguments not placed in the
867 * argument registers will be stored in the stack argument area for transfer
868 * purposes. When an 8-byte type argument is to be delivered using registers,
869 * it is divided into two and placed in two registers for transfer. When
870 * argument registers must be saved to memory, the callee function secures an
871 * argument register save area in the stack. In this case, a continuous
872 * argument register save area must be established in the parameter area. The
873 * argument register save area must be allocated as needed to cover the size of
874 * the argument register to be saved. If the function has a variable count of
875 * arguments, it saves all argument registers in the argument register save
878 * Argument Extension Format:
880 * When an argument is to be stored in the stack, its type is converted to an
881 * extended type in accordance with the individual argument type. The argument
882 * is freed by the caller function after the return from the callee function is
885 * +-----------------------+---------------+------------------------+
886 * | Argument Type |Extended Type |Stack Storage Size(byte)|
887 * +-----------------------+---------------+------------------------+
889 * |signed char |int | 4 |
890 * |unsigned char |int | 4 |
891 * |[signed] short int |int | 4 |
892 * |unsigned short int |int | 4 |
893 * |[signed] int |No extension | 4 |
894 * |unsigned int |No extension | 4 |
895 * |[signed] long int |No extension | 4 |
896 * |unsigned long int |No extension | 4 |
897 * |[signed] long long int |No extension | 8 |
898 * |unsigned long long int |No extension | 8 |
899 * |float |double | 8 |
900 * |double |No extension | 8 |
901 * |long double |No extension | 8 |
902 * |pointer |No extension | 4 |
903 * |struct/union |- | 4 (*1) |
904 * +-----------------------+---------------+------------------------+
906 * When a struct/union is to be delivered as an argument, the caller copies it
907 * to the local variable area and delivers the address of that area.
911 * +-------------------------------+----------------------+
912 * |Return Value Type |Return Value Interface|
913 * +-------------------------------+----------------------+
915 * |[signed|unsigned] char |GR8 |
916 * |[signed|unsigned] short int |GR8 |
917 * |[signed|unsigned] int |GR8 |
918 * |[signed|unsigned] long int |GR8 |
920 * |[signed|unsigned] long long int|GR8 & GR9 |
922 * |double |GR8 & GR9 |
923 * |long double |GR8 & GR9 |
924 * |struct/union |(*1) |
925 * +-------------------------------+----------------------+
927 * When a struct/union is used as the return value, the caller function stores
928 * the start address of the return value storage area into GR3 and then passes
929 * it to the callee function. The callee function interprets GR3 as the start
930 * address of the return value storage area. When this address needs to be
931 * saved in memory, the callee function secures the hidden parameter save area
932 * and saves the address in that area.
938 static frv_stack_t info, zero_info;
939 frv_stack_t *info_ptr = &info;
940 tree fndecl = current_function_decl;
948 /* If we've already calculated the values and reload is complete, just return now */
950 return frv_stack_cache;
952 /* Zero all fields */
955 /* Set up the register range information */
956 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
957 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
958 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
959 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
961 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
962 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
963 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
964 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
966 info_ptr->regs[STACK_REGS_LR].name = "lr";
967 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
968 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
969 info_ptr->regs[STACK_REGS_LR].special_p = 1;
971 info_ptr->regs[STACK_REGS_CC].name = "cc";
972 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
973 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
974 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
976 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
977 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
978 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
980 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
981 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
982 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
983 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
984 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
986 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
987 info_ptr->regs[STACK_REGS_STRUCT].first = STRUCT_VALUE_REGNUM;
988 info_ptr->regs[STACK_REGS_STRUCT].last = STRUCT_VALUE_REGNUM;
989 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
991 info_ptr->regs[STACK_REGS_FP].name = "fp";
992 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
993 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
994 info_ptr->regs[STACK_REGS_FP].special_p = 1;
996 /* Determine if this is a stdarg function. If so, allocate space to store
1003 /* Find the last argument, and see if it is __builtin_va_alist. */
1004 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1006 next_arg = TREE_CHAIN (cur_arg);
1007 if (next_arg == (tree)0)
1009 if (DECL_NAME (cur_arg)
1010 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1018 /* Iterate over all of the register ranges */
1019 for (range = 0; range < STACK_REGS_MAX; range++)
1021 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1022 int first = reg_ptr->first;
1023 int last = reg_ptr->last;
1025 int size_2words = 0;
1028 /* Calculate which registers need to be saved & save area size */
1032 for (regno = first; regno <= last; regno++)
1034 if ((regs_ever_live[regno] && !call_used_regs[regno])
1035 || (current_function_calls_eh_return
1036 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1037 || (flag_pic && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1039 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1040 size_1word += UNITS_PER_WORD;
1045 /* Calculate whether we need to create a frame after everything else
1046 has been processed. */
1051 if (regs_ever_live[LR_REGNO]
1053 || frame_pointer_needed
1054 || (flag_pic && cfun->uses_pic_offset_table))
1056 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1057 size_1word += UNITS_PER_WORD;
1061 case STACK_REGS_STDARG:
1064 /* If this is a stdarg function with an non varardic argument split
1065 between registers and the stack, adjust the saved registers
1067 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1070 for (regno = first; regno <= last; regno++)
1072 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1073 size_1word += UNITS_PER_WORD;
1076 info_ptr->stdarg_size = size_1word;
1080 case STACK_REGS_STRUCT:
1081 if (cfun->returns_struct)
1083 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1084 size_1word += UNITS_PER_WORD;
1092 /* If this is a field, it only takes one word */
1093 if (reg_ptr->field_p)
1094 size_1word = UNITS_PER_WORD;
1096 /* Determine which register pairs can be saved together */
1097 else if (reg_ptr->dword_p && TARGET_DWORD)
1099 for (regno = first; regno < last; regno += 2)
1101 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1103 size_2words += 2 * UNITS_PER_WORD;
1104 size_1word -= 2 * UNITS_PER_WORD;
1105 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1106 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1111 reg_ptr->size_1word = size_1word;
1112 reg_ptr->size_2words = size_2words;
1114 if (! reg_ptr->special_p)
1116 info_ptr->regs_size_1word += size_1word;
1117 info_ptr->regs_size_2words += size_2words;
1122 /* Set up the sizes of each each field in the frame body, making the sizes
1123 of each be divisible by the size of a dword if dword operations might
1124 be used, or the size of a word otherwise. */
1125 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1127 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1128 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1129 + info_ptr->regs_size_1word,
1131 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1133 info_ptr->pretend_size = cfun->pretend_args_size;
1135 /* Work out the size of the frame, excluding the header. Both the frame
1136 body and register parameter area will be dword-aligned. */
1137 info_ptr->total_size
1138 = (ADDR_ALIGN (info_ptr->parameter_size
1139 + info_ptr->regs_size
1140 + info_ptr->vars_size,
1142 + ADDR_ALIGN (info_ptr->pretend_size
1143 + info_ptr->stdarg_size,
1144 2 * UNITS_PER_WORD));
1146 /* See if we need to create a frame at all, if so add header area. */
1147 if (info_ptr->total_size > 0
1148 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1149 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1151 offset = info_ptr->parameter_size;
1152 info_ptr->header_size = 4 * UNITS_PER_WORD;
1153 info_ptr->total_size += 4 * UNITS_PER_WORD;
1155 /* Calculate the offsets to save normal register pairs */
1156 for (range = 0; range < STACK_REGS_MAX; range++)
1158 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1159 if (! reg_ptr->special_p)
1161 int first = reg_ptr->first;
1162 int last = reg_ptr->last;
1165 for (regno = first; regno <= last; regno++)
1166 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1167 && regno != FRAME_POINTER_REGNUM
1168 && (regno < FIRST_ARG_REGNUM
1169 || regno > LAST_ARG_REGNUM))
1171 info_ptr->reg_offset[regno] = offset;
1172 offset += 2 * UNITS_PER_WORD;
1177 /* Calculate the offsets to save normal single registers */
1178 for (range = 0; range < STACK_REGS_MAX; range++)
1180 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1181 if (! reg_ptr->special_p)
1183 int first = reg_ptr->first;
1184 int last = reg_ptr->last;
1187 for (regno = first; regno <= last; regno++)
1188 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1189 && regno != FRAME_POINTER_REGNUM
1190 && (regno < FIRST_ARG_REGNUM
1191 || regno > LAST_ARG_REGNUM))
1193 info_ptr->reg_offset[regno] = offset;
1194 offset += UNITS_PER_WORD;
1199 /* Calculate the offset to save the local variables at. */
1200 offset = ADDR_ALIGN (offset, alignment);
1201 if (info_ptr->vars_size)
1203 info_ptr->vars_offset = offset;
1204 offset += info_ptr->vars_size;
1207 /* Align header to a dword-boundary. */
1208 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1210 /* Calculate the offsets in the fixed frame. */
1211 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1212 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1213 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1215 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1216 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1217 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1219 if (cfun->returns_struct)
1221 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1222 info_ptr->reg_offset[STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1223 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1226 /* Calculate the offsets to store the arguments passed in registers
1227 for stdarg functions. The register pairs are first and the single
1228 register if any is last. The register save area starts on a
1230 if (info_ptr->stdarg_size)
1232 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1233 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1236 /* Skip the header. */
1237 offset += 4 * UNITS_PER_WORD;
1238 for (regno = first; regno <= last; regno++)
1240 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1242 info_ptr->reg_offset[regno] = offset;
1243 offset += 2 * UNITS_PER_WORD;
1245 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1247 info_ptr->reg_offset[regno] = offset;
1248 offset += UNITS_PER_WORD;
1254 if (reload_completed)
1255 frv_stack_cache = info_ptr;
1261 /* Print the information about the frv stack offsets, etc. when debugging. */
1264 frv_debug_stack (info)
1270 info = frv_stack_info ();
1272 fprintf (stderr, "\nStack information for function %s:\n",
1273 ((current_function_decl && DECL_NAME (current_function_decl))
1274 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1277 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1278 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1279 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1280 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1281 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1283 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1284 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1285 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1286 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1288 for (range = 0; range < STACK_REGS_MAX; range++)
1290 frv_stack_regs_t *regs = &(info->regs[range]);
1291 if ((regs->size_1word + regs->size_2words) > 0)
1293 int first = regs->first;
1294 int last = regs->last;
1297 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1298 regs->name, regs->size_1word + regs->size_2words,
1299 regs->size_1word, regs->size_2words);
1301 for (regno = first; regno <= last; regno++)
1303 if (info->save_p[regno] == REG_SAVE_1WORD)
1304 fprintf (stderr, " %s (%d)", reg_names[regno],
1305 info->reg_offset[regno]);
1307 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1308 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1309 reg_names[regno+1], info->reg_offset[regno]);
1312 fputc ('\n', stderr);
1322 /* The following variable value is TRUE if the next output insn should
1323 finish cpu cycle. In order words the insn will have packing bit
1324 (which means absence of asm code suffix `.p' on assembler. */
1326 static int frv_insn_packing_flag;
1328 /* True if the current function contains a far jump. */
1331 frv_function_contains_far_jump ()
1333 rtx insn = get_insns ();
1335 && !(GET_CODE (insn) == JUMP_INSN
1336 /* Ignore tablejump patterns. */
1337 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1338 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1339 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1340 insn = NEXT_INSN (insn);
1341 return (insn != NULL);
1344 /* For the FRV, this function makes sure that a function with far jumps
1345 will return correctly. It also does the VLIW packing. */
1348 frv_function_prologue (file, size)
1350 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1352 /* If no frame was created, check whether the function uses a call
1353 instruction to implement a far jump. If so, save the link in gr3 and
1354 replace all returns to LR with returns to GR3. GR3 is used because it
1355 is call-clobbered, because is not available to the register allocator,
1356 and because all functions that take a hidden argument pointer will have
1358 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1362 /* Just to check that the above comment is true. */
1363 if (regs_ever_live[GPR_FIRST + 3])
1366 /* Generate the instruction that saves the link register. */
1367 fprintf (file, "\tmovsg lr,gr3\n");
1369 /* Replace the LR with GR3 in *return_internal patterns. The insn
1370 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1371 simply emit a different assembly directive because bralr and jmpl
1372 execute in different units. */
1373 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1374 if (GET_CODE (insn) == JUMP_INSN)
1376 rtx pattern = PATTERN (insn);
1377 if (GET_CODE (pattern) == PARALLEL
1378 && XVECLEN (pattern, 0) >= 2
1379 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1380 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1382 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1383 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1384 REGNO (address) = GPR_FIRST + 3;
1390 frv_insn_packing_flag = TRUE;
1394 /* Return the next available temporary register in a given class. */
1397 frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort)
1398 frv_tmp_reg_t *info; /* which registers are available */
1399 enum reg_class class; /* register class desired */
1400 enum machine_mode mode; /* mode to allocate register with */
1401 int mark_as_used; /* register not available after allocation */
1402 int no_abort; /* return NULL instead of aborting */
1404 int regno = info->next_reg[ (int)class ];
1405 int orig_regno = regno;
1406 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1411 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1412 && TEST_HARD_REG_BIT (info->regs, regno))
1415 if (++regno >= FIRST_PSEUDO_REGISTER)
1417 if (regno == orig_regno)
1426 nr = HARD_REGNO_NREGS (regno, mode);
1427 info->next_reg[ (int)class ] = regno + nr;
1430 for (i = 0; i < nr; i++)
1431 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1433 return gen_rtx_REG (mode, regno);
1437 /* Return an rtx with the value OFFSET, which will either be a register or a
1438 signed 12-bit integer. It can be used as the second operand in an "add"
1439 instruction, or as the index in a load or store.
1441 The function returns a constant rtx if OFFSET is small enough, otherwise
1442 it loads the constant into register OFFSET_REGNO and returns that. */
1444 frv_frame_offset_rtx (offset)
1447 rtx offset_rtx = GEN_INT (offset);
1448 if (IN_RANGE_P (offset, -2048, 2047))
1452 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1453 if (IN_RANGE_P (offset, -32768, 32767))
1454 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1457 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1458 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1464 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1465 prologue and epilogue uses such expressions to access the stack. */
1467 frv_frame_mem (mode, base, offset)
1468 enum machine_mode mode;
1472 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1474 frv_frame_offset_rtx (offset)));
1477 /* Generate a frame-related expression:
1479 (set REG (mem (plus (sp) (const_int OFFSET)))).
1481 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1482 instructions. Marking the expressions as frame-related is superfluous if
1483 the note contains just a single set. But if the note contains a PARALLEL
1484 or SEQUENCE that has several sets, each set must be individually marked
1485 as frame-related. */
1487 frv_dwarf_store (reg, offset)
1491 rtx set = gen_rtx_SET (VOIDmode,
1492 gen_rtx_MEM (GET_MODE (reg),
1493 plus_constant (stack_pointer_rtx,
1496 RTX_FRAME_RELATED_P (set) = 1;
1500 /* Emit a frame-related instruction whose pattern is PATTERN. The
1501 instruction is the last in a sequence that cumulatively performs the
1502 operation described by DWARF_PATTERN. The instruction is marked as
1503 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1506 frv_frame_insn (pattern, dwarf_pattern)
1510 rtx insn = emit_insn (pattern);
1511 RTX_FRAME_RELATED_P (insn) = 1;
1512 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1517 /* Emit instructions that transfer REG to or from the memory location (sp +
1518 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1519 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1520 function to store registers and only the epilogue uses it to load them.
1522 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1523 The generated instruction will use BASE as its base register. BASE may
1524 simply be the stack pointer, but if several accesses are being made to a
1525 region far away from the stack pointer, it may be more efficient to set
1526 up a temporary instead.
1528 Store instructions will be frame-related and will be annotated with the
1529 overall effect of the store. Load instructions will be followed by a
1530 (use) to prevent later optimizations from zapping them.
1532 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1533 as a temporary in such cases. */
1535 frv_frame_access (accessor, reg, stack_offset)
1536 frv_frame_accessor_t *accessor;
1540 enum machine_mode mode = GET_MODE (reg);
1541 rtx mem = frv_frame_mem (mode,
1543 stack_offset - accessor->base_offset);
1545 if (accessor->op == FRV_LOAD)
1547 if (SPR_P (REGNO (reg)))
1549 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1550 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1551 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1554 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1555 emit_insn (gen_rtx_USE (VOIDmode, reg));
1559 if (SPR_P (REGNO (reg)))
1561 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1562 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1563 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1564 frv_dwarf_store (reg, stack_offset));
1566 else if (GET_MODE (reg) == DImode)
1568 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1569 with a separate save for each register. */
1570 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1571 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1572 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1573 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1574 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1575 gen_rtx_PARALLEL (VOIDmode,
1576 gen_rtvec (2, set1, set2)));
1579 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1580 frv_dwarf_store (reg, stack_offset));
1584 /* A function that uses frv_frame_access to transfer a group of registers to
1585 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1586 is the stack information generated by frv_stack_info, and REG_SET is the
1587 number of the register set to transfer. */
1589 frv_frame_access_multi (accessor, info, reg_set)
1590 frv_frame_accessor_t *accessor;
1594 frv_stack_regs_t *regs_info;
1597 regs_info = &info->regs[reg_set];
1598 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1599 if (info->save_p[regno])
1600 frv_frame_access (accessor,
1601 info->save_p[regno] == REG_SAVE_2WORDS
1602 ? gen_rtx_REG (DImode, regno)
1603 : gen_rtx_REG (SImode, regno),
1604 info->reg_offset[regno]);
1607 /* Save or restore callee-saved registers that are kept outside the frame
1608 header. The function saves the registers if OP is FRV_STORE and restores
1609 them if OP is FRV_LOAD. INFO is the stack information generated by
1612 frv_frame_access_standard_regs (op, info)
1613 enum frv_stack_op op;
1616 frv_frame_accessor_t accessor;
1619 accessor.base = stack_pointer_rtx;
1620 accessor.base_offset = 0;
1621 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1622 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1623 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1627 /* Called after register allocation to add any instructions needed for the
1628 prologue. Using a prologue insn is favored compared to putting all of the
1629 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1630 to intermix instructions with the saves of the caller saved registers. In
1631 some cases, it might be necessary to emit a barrier instruction as the last
1632 insn to prevent such scheduling.
1634 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1635 so that the debug info generation code can handle them properly. */
1637 frv_expand_prologue ()
1639 frv_stack_t *info = frv_stack_info ();
1640 rtx sp = stack_pointer_rtx;
1641 rtx fp = frame_pointer_rtx;
1642 frv_frame_accessor_t accessor;
1644 if (TARGET_DEBUG_STACK)
1645 frv_debug_stack (info);
1647 if (info->total_size == 0)
1650 /* We're interested in three areas of the frame here:
1652 A: the register save area
1654 C: the header after B
1656 If the frame pointer isn't used, we'll have to set up A, B and C
1657 using the stack pointer. If the frame pointer is used, we'll access
1661 B: set up using sp or a temporary (see below)
1664 We set up B using the stack pointer if the frame is small enough.
1665 Otherwise, it's more efficient to copy the old stack pointer into a
1666 temporary and use that.
1668 Note that it's important to make sure the prologue and epilogue use the
1669 same registers to access A and C, since doing otherwise will confuse
1670 the aliasing code. */
1672 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1673 isn't used, the same method will serve for C. */
1674 accessor.op = FRV_STORE;
1675 if (frame_pointer_needed && info->total_size > 2048)
1679 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1680 accessor.base_offset = info->total_size;
1681 insn = emit_insn (gen_movsi (accessor.base, sp));
1685 accessor.base = stack_pointer_rtx;
1686 accessor.base_offset = 0;
1689 /* Allocate the stack space. */
1691 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1692 rtx dwarf_offset = GEN_INT (-info->total_size);
1694 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1697 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1700 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1701 and point the new one to that location. */
1702 if (frame_pointer_needed)
1704 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1706 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1707 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1709 rtx asm_src = plus_constant (accessor.base,
1710 fp_offset - accessor.base_offset);
1711 rtx dwarf_src = plus_constant (sp, fp_offset);
1713 /* Store the old frame pointer at (sp + FP_OFFSET). */
1714 frv_frame_access (&accessor, fp, fp_offset);
1716 /* Set up the new frame pointer. */
1717 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1718 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1720 /* Access region C from the frame pointer. */
1722 accessor.base_offset = fp_offset;
1725 /* Set up region C. */
1726 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1727 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1728 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1730 /* Set up region A. */
1731 frv_frame_access_standard_regs (FRV_STORE, info);
1733 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1734 scheduler from moving loads before the stores saving the registers. */
1735 if (info->stdarg_size > 0)
1736 emit_insn (gen_blockage ());
1738 /* Set up pic register/small data register for this function. */
1739 if (flag_pic && cfun->uses_pic_offset_table)
1740 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1741 gen_rtx_REG (Pmode, LR_REGNO),
1742 gen_rtx_REG (SImode, OFFSET_REGNO)));
1746 /* Under frv, all of the work is done via frv_expand_epilogue, but
1747 this function provides a convient place to do cleanup. */
1750 frv_function_epilogue (file, size)
1751 FILE *file ATTRIBUTE_UNUSED;
1752 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1754 frv_stack_cache = (frv_stack_t *)0;
1756 /* zap last used registers for conditional execution. */
1757 memset ((PTR) &frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1759 /* release the bitmap of created insns. */
1760 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1764 /* Called after register allocation to add any instructions needed for the
1765 epilogue. Using an epilogue insn is favored compared to putting all of the
1766 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1767 to intermix instructions with the saves of the caller saved registers. In
1768 some cases, it might be necessary to emit a barrier instruction as the last
1769 insn to prevent such scheduling.
1771 If SIBCALL_P is true, the final branch back to the calling function is
1772 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1773 we must not clobber any arguments used for parameter passing or any stack
1774 slots for arguments passed to the current function. */
1777 frv_expand_epilogue (sibcall_p)
1780 frv_stack_t *info = frv_stack_info ();
1781 rtx fp = frame_pointer_rtx;
1782 rtx sp = stack_pointer_rtx;
1786 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1788 /* Restore the stack pointer to its original value if alloca or the like
1790 if (! current_function_sp_is_unchanging)
1791 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1793 /* Restore the callee-saved registers that were used in this function. */
1794 frv_frame_access_standard_regs (FRV_LOAD, info);
1796 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1797 no return instruction should be emitted. */
1800 else if (info->save_p[LR_REGNO])
1805 /* Use the same method to access the link register's slot as we did in
1806 the prologue. In other words, use the frame pointer if available,
1807 otherwise use the stack pointer.
1809 LR_OFFSET is the offset of the link register's slot from the start
1810 of the frame and MEM is a memory rtx for it. */
1811 lr_offset = info->reg_offset[LR_REGNO];
1812 if (frame_pointer_needed)
1813 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1815 mem = frv_frame_mem (Pmode, sp, lr_offset);
1817 /* Load the old link register into a GPR. */
1818 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1819 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1822 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1824 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1825 the load is preserved. */
1826 if (frame_pointer_needed)
1828 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1829 emit_insn (gen_rtx_USE (VOIDmode, fp));
1832 /* Deallocate the stack frame. */
1833 if (info->total_size != 0)
1835 rtx offset = frv_frame_offset_rtx (info->total_size);
1836 emit_insn (gen_stack_adjust (sp, sp, offset));
1839 /* If this function uses eh_return, add the final stack adjustment now. */
1840 if (current_function_calls_eh_return)
1841 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1844 emit_jump_insn (gen_epilogue_return (return_addr));
1848 /* A C compound statement that outputs the assembler code for a thunk function,
1849 used to implement C++ virtual function calls with multiple inheritance. The
1850 thunk acts as a wrapper around a virtual function, adjusting the implicit
1851 object parameter before handing control off to the real function.
1853 First, emit code to add the integer DELTA to the location that contains the
1854 incoming first argument. Assume that this argument contains a pointer, and
1855 is the one used to pass the `this' pointer in C++. This is the incoming
1856 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1857 addition must preserve the values of all other incoming arguments.
1859 After the addition, emit code to jump to FUNCTION, which is a
1860 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1861 the return address. Hence returning from FUNCTION will return to whoever
1862 called the current `thunk'.
1864 The effect must be as if FUNCTION had been called directly with the adjusted
1865 first argument. This macro is responsible for emitting all of the code for
1866 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1869 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1870 extracted from it.) It might possibly be useful on some targets, but
1873 If you do not define this macro, the target-independent code in the C++
1874 frontend will generate a less efficient heavyweight thunk that calls
1875 FUNCTION instead of jumping to it. The generic approach does not support
1879 frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
1881 tree thunk_fndecl ATTRIBUTE_UNUSED;
1882 HOST_WIDE_INT delta;
1883 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
1886 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1887 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1888 const char *name_jmp = reg_names[JUMP_REGNO];
1889 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1891 /* Do the add using an addi if possible */
1892 if (IN_RANGE_P (delta, -2048, 2047))
1893 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1896 const char *name_add = reg_names[TEMP_REGNO];
1897 fprintf (file, "\tsethi%s #hi(", parallel);
1898 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1899 fprintf (file, "),%s\n", name_add);
1900 fprintf (file, "\tsetlo #lo(");
1901 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1902 fprintf (file, "),%s\n", name_add);
1903 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1908 fprintf (file, "\tsethi%s #hi(", parallel);
1909 assemble_name (file, name_func);
1910 fprintf (file, "),%s\n", name_jmp);
1912 fprintf (file, "\tsetlo #lo(");
1913 assemble_name (file, name_func);
1914 fprintf (file, "),%s\n", name_jmp);
1918 /* Use JUMP_REGNO as a temporary PIC register. */
1919 const char *name_lr = reg_names[LR_REGNO];
1920 const char *name_gppic = name_jmp;
1921 const char *name_tmp = reg_names[TEMP_REGNO];
1923 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1924 fprintf (file, "\tcall 1f\n");
1925 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1926 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1927 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1928 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1929 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1931 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1932 assemble_name (file, name_func);
1933 fprintf (file, "),%s\n", name_tmp);
1935 fprintf (file, "\tsetlo #gprello(");
1936 assemble_name (file, name_func);
1937 fprintf (file, "),%s\n", name_tmp);
1939 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1942 /* Jump to the function address */
1943 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1947 /* A C expression which is nonzero if a function must have and use a frame
1948 pointer. This expression is evaluated in the reload pass. If its value is
1949 nonzero the function will have a frame pointer.
1951 The expression can in principle examine the current function and decide
1952 according to the facts, but on most machines the constant 0 or the constant
1953 1 suffices. Use 0 when the machine allows code to be generated with no
1954 frame pointer, and doing so saves some time or space. Use 1 when there is
1955 no possible advantage to avoiding a frame pointer.
1957 In certain cases, the compiler does not know how to produce valid code
1958 without a frame pointer. The compiler recognizes those cases and
1959 automatically gives the function a frame pointer regardless of what
1960 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1962 In a function that does not require a frame pointer, the frame pointer
1963 register can be allocated for ordinary usage, unless you mark it as a fixed
1964 register. See `FIXED_REGISTERS' for more information. */
1966 /* On frv, create a frame whenever we need to create stack */
1969 frv_frame_pointer_required ()
1971 if (! current_function_is_leaf)
1974 if (get_frame_size () != 0)
1980 if (!current_function_sp_is_unchanging)
1983 if (flag_pic && cfun->uses_pic_offset_table)
1989 if (cfun->machine->frame_needed)
1996 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1997 initial difference between the specified pair of registers. This macro must
1998 be defined if `ELIMINABLE_REGS' is defined. */
2000 /* See frv_stack_info for more details on the frv stack frame. */
2003 frv_initial_elimination_offset (from, to)
2007 frv_stack_t *info = frv_stack_info ();
2010 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2011 ret = info->total_size - info->pretend_size;
2013 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2014 ret = - info->reg_offset[FRAME_POINTER_REGNUM];
2016 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2017 ret = (info->total_size
2018 - info->reg_offset[FRAME_POINTER_REGNUM]
2019 - info->pretend_size);
2024 if (TARGET_DEBUG_STACK)
2025 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2026 reg_names [from], reg_names[to], ret);
2032 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2033 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2034 arguments into the stack so that all the arguments appear to have been
2035 passed consecutively on the stack. Once this is done, you can use the
2036 standard implementation of varargs that works for machines that pass all
2037 their arguments on the stack.
2039 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2040 the values that obtain after processing of the named arguments. The
2041 arguments MODE and TYPE describe the last named argument--its machine mode
2042 and its data type as a tree node.
2044 The macro implementation should do two things: first, push onto the stack
2045 all the argument registers *not* used for the named arguments, and second,
2046 store the size of the data thus pushed into the `int'-valued variable whose
2047 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2048 store here will serve as additional offset for setting up the stack frame.
2050 Because you must generate code to push the anonymous arguments at compile
2051 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2052 useful on machines that have just a single category of argument register and
2053 use it uniformly for all data types.
2055 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2056 function are being analyzed for the second time. This happens for an inline
2057 function, which is not actually compiled until the end of the source file.
2058 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2062 frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2063 CUMULATIVE_ARGS *cum;
2064 enum machine_mode mode;
2065 tree type ATTRIBUTE_UNUSED;
2069 if (TARGET_DEBUG_ARG)
2071 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2072 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2076 /* If defined, is a C expression that produces the machine-specific code for a
2077 call to `__builtin_saveregs'. This code will be moved to the very beginning
2078 of the function, before any parameter access are made. The return value of
2079 this function should be an RTX that contains the value to use as the return
2080 of `__builtin_saveregs'.
2082 If this macro is not defined, the compiler will output an ordinary call to
2083 the library function `__builtin_saveregs'. */
2086 frv_expand_builtin_saveregs ()
2088 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2090 if (TARGET_DEBUG_ARG)
2091 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2094 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2098 /* Expand __builtin_va_start to do the va_start macro. */
2101 frv_expand_builtin_va_start (valist, nextarg)
2106 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2108 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2109 GEN_INT (UNITS_PER_WORD * num));
2111 if (TARGET_DEBUG_ARG)
2113 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2114 cfun->args_info, num);
2116 debug_rtx (nextarg);
2119 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2120 make_tree (ptr_type_node, nextarg));
2121 TREE_SIDE_EFFECTS (t) = 1;
2123 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2127 /* Expand __builtin_va_arg to do the va_arg macro. */
2130 frv_expand_builtin_va_arg(valist, type)
2138 if (TARGET_DEBUG_ARG)
2140 fprintf (stderr, "va_arg:\n");
2144 if (! AGGREGATE_TYPE_P (type))
2145 return std_expand_builtin_va_arg (valist, type);
2147 addr = std_expand_builtin_va_arg (valist, ptr_type_node);
2148 mem = gen_rtx_MEM (Pmode, addr);
2149 reg = gen_reg_rtx (Pmode);
2151 set_mem_alias_set (mem, get_varargs_alias_set ());
2152 emit_move_insn (reg, mem);
2158 /* Expand a block move operation, and return 1 if successful. Return 0
2159 if we should let the compiler generate normal code.
2161 operands[0] is the destination
2162 operands[1] is the source
2163 operands[2] is the length
2164 operands[3] is the alignment */
2166 /* Maximum number of loads to do before doing the stores */
2167 #ifndef MAX_MOVE_REG
2168 #define MAX_MOVE_REG 4
2171 /* Maximum number of total loads to do. */
2172 #ifndef TOTAL_MOVE_REG
2173 #define TOTAL_MOVE_REG 8
2177 frv_expand_block_move (operands)
2180 rtx orig_dest = operands[0];
2181 rtx orig_src = operands[1];
2182 rtx bytes_rtx = operands[2];
2183 rtx align_rtx = operands[3];
2184 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2197 rtx stores[MAX_MOVE_REG];
2199 enum machine_mode mode;
2201 /* If this is not a fixed size move, just call memcpy */
2205 /* If this is not a fixed size alignment, abort */
2206 if (GET_CODE (align_rtx) != CONST_INT)
2209 align = INTVAL (align_rtx);
2211 /* Anything to move? */
2212 bytes = INTVAL (bytes_rtx);
2216 /* Don't support real large moves. */
2217 if (bytes > TOTAL_MOVE_REG*align)
2220 /* Move the address into scratch registers. */
2221 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2222 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2224 num_reg = offset = 0;
2225 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2227 /* Calculate the correct offset for src/dest */
2231 dest_addr = dest_reg;
2235 src_addr = plus_constant (src_reg, offset);
2236 dest_addr = plus_constant (dest_reg, offset);
2239 /* Generate the appropriate load and store, saving the stores
2241 if (bytes >= 4 && align >= 4)
2243 else if (bytes >= 2 && align >= 2)
2248 move_bytes = GET_MODE_SIZE (mode);
2249 tmp_reg = gen_reg_rtx (mode);
2250 src_mem = change_address (orig_src, mode, src_addr);
2251 dest_mem = change_address (orig_dest, mode, dest_addr);
2252 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2253 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2255 if (num_reg >= MAX_MOVE_REG)
2257 for (i = 0; i < num_reg; i++)
2258 emit_insn (stores[i]);
2263 for (i = 0; i < num_reg; i++)
2264 emit_insn (stores[i]);
2270 /* Expand a block clear operation, and return 1 if successful. Return 0
2271 if we should let the compiler generate normal code.
2273 operands[0] is the destination
2274 operands[1] is the length
2275 operands[2] is the alignment */
2278 frv_expand_block_clear (operands)
2281 rtx orig_dest = operands[0];
2282 rtx bytes_rtx = operands[1];
2283 rtx align_rtx = operands[2];
2284 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2293 enum machine_mode mode;
2295 /* If this is not a fixed size move, just call memcpy */
2299 /* If this is not a fixed size alignment, abort */
2300 if (GET_CODE (align_rtx) != CONST_INT)
2303 align = INTVAL (align_rtx);
2305 /* Anything to move? */
2306 bytes = INTVAL (bytes_rtx);
2310 /* Don't support real large clears. */
2311 if (bytes > TOTAL_MOVE_REG*align)
2314 /* Move the address into a scratch register. */
2315 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2317 num_reg = offset = 0;
2318 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2320 /* Calculate the correct offset for src/dest */
2321 dest_addr = ((offset == 0)
2323 : plus_constant (dest_reg, offset));
2325 /* Generate the appropriate store of gr0 */
2326 if (bytes >= 4 && align >= 4)
2328 else if (bytes >= 2 && align >= 2)
2333 clear_bytes = GET_MODE_SIZE (mode);
2334 dest_mem = change_address (orig_dest, mode, dest_addr);
2335 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2342 /* The following variable is used to output modifiers of assembler
2343 code of the current output insn.. */
2345 static rtx *frv_insn_operands;
2347 /* The following function is used to add assembler insn code suffix .p
2348 if it is necessary. */
2351 frv_asm_output_opcode (f, ptr)
2357 if (! PACKING_FLAG_USED_P())
2360 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2363 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2364 || (*ptr >= 'A' && *ptr <= 'Z')))
2366 int letter = *ptr++;
2369 frv_print_operand (f, frv_insn_operands [c], letter);
2370 while ((c = *ptr) >= '0' && c <= '9')
2377 if (!frv_insn_packing_flag)
2383 /* The following function sets up the packing bit for the current
2384 output insn. Remember that the function is not called for asm
2388 frv_final_prescan_insn (insn, opvec, noperands)
2391 int noperands ATTRIBUTE_UNUSED;
2393 if (! PACKING_FLAG_USED_P())
2396 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
2399 frv_insn_operands = opvec;
2401 /* Look for the next printable instruction. frv_pack_insns () has set
2402 things up so that any printable instruction will have TImode if it
2403 starts a new packet and VOIDmode if it should be packed with the
2404 previous instruction.
2406 Printable instructions will be asm_operands or match one of the .md
2407 patterns. Since asm instructions cannot be packed -- and will
2408 therefore have TImode -- this loop terminates on any recognisable
2409 instruction, and on any unrecognisable instruction with TImode. */
2410 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2414 else if (!INSN_P (insn))
2416 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2420 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2421 be packed with this one. Set it to TRUE otherwise. If the next
2422 instruction is an asm insntruction, this statement will set the
2423 flag to TRUE, and that value will still hold when the asm operands
2424 themselves are printed. */
2425 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2426 && GET_MODE (insn) != TImode);
2431 /* A C expression whose value is RTL representing the address in a stack frame
2432 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2433 an RTL expression for the address of the stack frame itself.
2435 If you don't define this macro, the default is to return the value of
2436 FRAMEADDR--that is, the stack frame address is also the address of the stack
2437 word that points to the previous frame. */
2439 /* The default is correct, but we need to make sure the frame gets created. */
2441 frv_dynamic_chain_address (frame)
2444 cfun->machine->frame_needed = 1;
2449 /* A C expression whose value is RTL representing the value of the return
2450 address for the frame COUNT steps up from the current frame, after the
2451 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2452 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2455 The value of the expression must always be the correct address when COUNT is
2456 zero, but may be `NULL_RTX' if there is not way to determine the return
2457 address of other frames. */
2460 frv_return_addr_rtx (count, frame)
2461 int count ATTRIBUTE_UNUSED;
2464 cfun->machine->frame_needed = 1;
2465 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2468 /* Given a memory reference MEMREF, interpret the referenced memory as
2469 an array of MODE values, and return a reference to the element
2470 specified by INDEX. Assume that any pre-modification implicit in
2471 MEMREF has already happened.
2473 MEMREF must be a legitimate operand for modes larger than SImode.
2474 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2475 this function cannot handle. */
2477 frv_index_memory (memref, mode, index)
2479 enum machine_mode mode;
2482 rtx base = XEXP (memref, 0);
2483 if (GET_CODE (base) == PRE_MODIFY)
2484 base = XEXP (base, 0);
2485 return change_address (memref, mode,
2486 plus_constant (base, index * GET_MODE_SIZE (mode)));
2490 /* Print a memory address as an operand to reference that memory location. */
2492 frv_print_operand_address (stream, x)
2496 if (GET_CODE (x) == MEM)
2499 switch (GET_CODE (x))
2502 fputs (reg_names [ REGNO (x)], stream);
2506 fprintf (stream, "%ld", (long) INTVAL (x));
2510 assemble_name (stream, XSTR (x, 0));
2515 output_addr_const (stream, x);
2522 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2527 frv_print_operand_memory_reference_reg (stream, x)
2531 int regno = true_regnum (x);
2533 fputs (reg_names[regno], stream);
2535 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2538 /* Print a memory reference suitable for the ld/st instructions. */
2541 frv_print_operand_memory_reference (stream, x, addr_offset)
2549 switch (GET_CODE (x))
2556 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2558 x1 = XEXP (XEXP (x, 1), 1);
2568 if (GET_CODE (x0) == CONST_INT)
2576 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2585 else if (GET_CODE (x1) != CONST_INT)
2586 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2589 fputs ("@(", stream);
2591 fputs (reg_names[GPR_R0], stream);
2592 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2593 frv_print_operand_memory_reference_reg (stream, x0);
2595 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2597 fputs (",", stream);
2599 fputs (reg_names [GPR_R0], stream);
2603 switch (GET_CODE (x1))
2607 frv_print_operand_memory_reference_reg (stream, x1);
2611 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2615 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2616 && symbol_ref_small_data_p (x1))
2618 fputs ("#gprel12(", stream);
2619 assemble_name (stream, XSTR (x1, 0));
2620 fputs (")", stream);
2623 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2627 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2628 && const_small_data_p (x1))
2630 fputs ("#gprel12(", stream);
2631 assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0));
2632 fprintf (stream, "+%d)", INTVAL (XEXP (XEXP (x1, 0), 1)));
2635 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2639 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2643 fputs (")", stream);
2647 /* Return 2 for likely branches and 0 for non-likely branches */
2649 #define FRV_JUMP_LIKELY 2
2650 #define FRV_JUMP_NOT_LIKELY 0
2653 frv_print_operand_jump_hint (insn)
2659 HOST_WIDE_INT prob = -1;
2660 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2662 if (GET_CODE (insn) != JUMP_INSN)
2665 /* Assume any non-conditional jump is likely. */
2666 if (! any_condjump_p (insn))
2667 ret = FRV_JUMP_LIKELY;
2671 labelref = condjump_label (insn);
2674 rtx label = XEXP (labelref, 0);
2675 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2680 note = find_reg_note (insn, REG_BR_PROB, 0);
2682 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2686 prob = INTVAL (XEXP (note, 0));
2687 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2689 : FRV_JUMP_NOT_LIKELY);
2701 case UNKNOWN: direction = "unknown jump direction"; break;
2702 case BACKWARD: direction = "jump backward"; break;
2703 case FORWARD: direction = "jump forward"; break;
2707 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2708 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2709 (long)INSN_UID (insn), direction, (long)prob,
2710 (long)REG_BR_PROB_BASE, ret);
2718 /* Print an operand to an assembler instruction.
2720 `%' followed by a letter and a digit says to output an operand in an
2721 alternate fashion. Four letters have standard, built-in meanings described
2722 below. The machine description macro `PRINT_OPERAND' can define additional
2723 letters with nonstandard meanings.
2725 `%cDIGIT' can be used to substitute an operand that is a constant value
2726 without the syntax that normally indicates an immediate operand.
2728 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2731 `%aDIGIT' can be used to substitute an operand as if it were a memory
2732 reference, with the actual operand treated as the address. This may be
2733 useful when outputting a "load address" instruction, because often the
2734 assembler syntax for such an instruction requires you to write the operand
2735 as if it were a memory reference.
2737 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2739 `%=' outputs a number which is unique to each instruction in the entire
2740 compilation. This is useful for making local labels to be referred to more
2741 than once in a single template that generates multiple assembler
2744 `%' followed by a punctuation character specifies a substitution that does
2745 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2746 assembler code. Other nonstandard cases can be defined in the
2747 `PRINT_OPERAND' macro. You must also define which punctuation characters
2748 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2751 frv_print_operand (file, x, code)
2756 HOST_WIDE_INT value;
2759 if (code != 0 && !isalpha (code))
2762 else if (GET_CODE (x) == CONST_INT)
2765 else if (GET_CODE (x) == CONST_DOUBLE)
2767 if (GET_MODE (x) == SFmode)
2772 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2773 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2777 else if (GET_MODE (x) == VOIDmode)
2778 value = CONST_DOUBLE_LOW (x);
2781 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2792 fputs (reg_names[GPR_R0], file);
2796 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2799 case SDATA_FLAG_CHAR:
2800 /* Output small data area base register (gr16). */
2801 fputs (reg_names[SDA_BASE_REG], file);
2805 /* Output pic register (gr17). */
2806 fputs (reg_names[PIC_REGNO], file);
2810 /* Output the temporary integer CCR register */
2811 fputs (reg_names[ICR_TEMP], file);
2815 /* Output the temporary integer CC register */
2816 fputs (reg_names[ICC_TEMP], file);
2819 /* case 'a': print an address */
2822 /* Print appropriate test for integer branch false operation */
2823 switch (GET_CODE (x))
2826 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2828 case EQ: fputs ("ne", file); break;
2829 case NE: fputs ("eq", file); break;
2830 case LT: fputs ("ge", file); break;
2831 case LE: fputs ("gt", file); break;
2832 case GT: fputs ("le", file); break;
2833 case GE: fputs ("lt", file); break;
2834 case LTU: fputs ("nc", file); break;
2835 case LEU: fputs ("hi", file); break;
2836 case GTU: fputs ("ls", file); break;
2837 case GEU: fputs ("c", file); break;
2841 /* case 'c': print a constant without the constant prefix. If
2842 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2845 /* Print appropriate test for integer branch true operation */
2846 switch (GET_CODE (x))
2849 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2851 case EQ: fputs ("eq", file); break;
2852 case NE: fputs ("ne", file); break;
2853 case LT: fputs ("lt", file); break;
2854 case LE: fputs ("le", file); break;
2855 case GT: fputs ("gt", file); break;
2856 case GE: fputs ("ge", file); break;
2857 case LTU: fputs ("c", file); break;
2858 case LEU: fputs ("ls", file); break;
2859 case GTU: fputs ("hi", file); break;
2860 case GEU: fputs ("nc", file); break;
2865 /* Print 1 for a NE and 0 for an EQ to give the final argument
2866 for a conditional instruction. */
2867 if (GET_CODE (x) == NE)
2870 else if (GET_CODE (x) == EQ)
2874 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2878 /* Print appropriate test for floating point branch false operation */
2879 switch (GET_CODE (x))
2882 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2884 case EQ: fputs ("ne", file); break;
2885 case NE: fputs ("eq", file); break;
2886 case LT: fputs ("uge", file); break;
2887 case LE: fputs ("ug", file); break;
2888 case GT: fputs ("ule", file); break;
2889 case GE: fputs ("ul", file); break;
2894 /* Print appropriate test for floating point branch true operation */
2895 switch (GET_CODE (x))
2898 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2900 case EQ: fputs ("eq", file); break;
2901 case NE: fputs ("ne", file); break;
2902 case LT: fputs ("lt", file); break;
2903 case LE: fputs ("le", file); break;
2904 case GT: fputs ("gt", file); break;
2905 case GE: fputs ("ge", file); break;
2910 /* Print 'i' if the operand is a constant, or is a memory reference that
2912 if (GET_CODE (x) == MEM)
2913 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2914 ? XEXP (XEXP (x, 0), 1)
2917 switch (GET_CODE (x))
2931 /* For jump instructions, print 'i' if the operand is a constant or
2932 is an expression that adds a constant */
2933 if (GET_CODE (x) == CONST_INT)
2938 if (GET_CODE (x) == CONST_INT
2939 || (GET_CODE (x) == PLUS
2940 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2941 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2947 /* Print the lower register of a double word register pair */
2948 if (GET_CODE (x) == REG)
2949 fputs (reg_names[ REGNO (x)+1 ], file);
2951 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2954 /* case 'l': print a LABEL_REF */
2958 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2959 for the second word of double memory operations. */
2960 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2961 switch (GET_CODE (x))
2964 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2967 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2975 frv_print_operand_memory_reference (file, x, offset);
2981 /* Print the opcode of a command. */
2982 switch (GET_CODE (x))
2985 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2987 case PLUS: fputs ("add", file); break;
2988 case MINUS: fputs ("sub", file); break;
2989 case AND: fputs ("and", file); break;
2990 case IOR: fputs ("or", file); break;
2991 case XOR: fputs ("xor", file); break;
2992 case ASHIFT: fputs ("sll", file); break;
2993 case ASHIFTRT: fputs ("sra", file); break;
2994 case LSHIFTRT: fputs ("srl", file); break;
2998 /* case 'n': negate and print a constant int */
3001 /* Print PIC label using operand as the number. */
3002 if (GET_CODE (x) != CONST_INT)
3003 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
3005 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3009 /* Print 'u' if the operand is a update load/store */
3010 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3015 /* If value is 0, print gr0, otherwise it must be a register */
3016 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3017 fputs (reg_names[GPR_R0], file);
3019 else if (GET_CODE (x) == REG)
3020 fputs (reg_names [REGNO (x)], file);
3023 fatal_insn ("Bad insn in frv_print_operand, z case", x);
3027 /* Print constant in hex */
3028 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3030 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3037 if (GET_CODE (x) == REG)
3038 fputs (reg_names [REGNO (x)], file);
3040 else if (GET_CODE (x) == CONST_INT
3041 || GET_CODE (x) == CONST_DOUBLE)
3042 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3044 else if (GET_CODE (x) == MEM)
3045 frv_print_operand_address (file, XEXP (x, 0));
3047 else if (CONSTANT_ADDRESS_P (x))
3048 frv_print_operand_address (file, x);
3051 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3056 fatal_insn ("frv_print_operand: unknown code", x);
3064 /* A C statement (sans semicolon) for initializing the variable CUM for the
3065 state at the beginning of the argument list. The variable has type
3066 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3067 of the function which will receive the args, or 0 if the args are to a
3068 compiler support library function. The value of INDIRECT is nonzero when
3069 processing an indirect call, for example a call through a function pointer.
3070 The value of INDIRECT is zero for a call to an explicitly named function, a
3071 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3072 arguments for the function being compiled.
3074 When processing a call to a compiler support library function, LIBNAME
3075 identifies which one. It is a `symbol_ref' rtx which contains the name of
3076 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3077 being processed. Thus, each time this macro is called, either LIBNAME or
3078 FNTYPE is nonzero, but never both of them at once. */
3081 frv_init_cumulative_args (cum, fntype, libname, indirect, incoming)
3082 CUMULATIVE_ARGS *cum;
3088 *cum = FIRST_ARG_REGNUM;
3090 if (TARGET_DEBUG_ARG)
3092 fprintf (stderr, "\ninit_cumulative_args:");
3094 fputs (" indirect", stderr);
3097 fputs (" incoming", stderr);
3101 tree ret_type = TREE_TYPE (fntype);
3102 fprintf (stderr, " return=%s,",
3103 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3106 if (libname && GET_CODE (libname) == SYMBOL_REF)
3107 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3109 if (cfun->returns_struct)
3110 fprintf (stderr, " return-struct");
3112 putc ('\n', stderr);
3117 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3118 argument with the specified mode and type. If it is not defined,
3119 `PARM_BOUNDARY' is used for all arguments. */
3122 frv_function_arg_boundary (mode, type)
3123 enum machine_mode mode ATTRIBUTE_UNUSED;
3124 tree type ATTRIBUTE_UNUSED;
3126 return BITS_PER_WORD;
3130 /* A C expression that controls whether a function argument is passed in a
3131 register, and which register.
3133 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3134 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3135 arguments so far passed in registers; MODE, the machine mode of the argument;
3136 TYPE, the data type of the argument as a tree node or 0 if that is not known
3137 (which happens for C support library functions); and NAMED, which is 1 for an
3138 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3139 called function's prototype.
3141 The value of the expression should either be a `reg' RTX for the hard
3142 register in which to pass the argument, or zero to pass the argument on the
3145 For machines like the VAX and 68000, where normally all arguments are
3146 pushed, zero suffices as a definition.
3148 The usual way to make the ANSI library `stdarg.h' work on a machine where
3149 some arguments are usually passed in registers, is to cause nameless
3150 arguments to be passed on the stack instead. This is done by making
3151 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3153 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3154 this macro to determine if this argument is of a type that must be passed in
3155 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3156 returns nonzero for such an argument, the compiler will abort. If
3157 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3158 stack and then loaded into a register. */
3161 frv_function_arg (cum, mode, type, named, incoming)
3162 CUMULATIVE_ARGS *cum;
3163 enum machine_mode mode;
3164 tree type ATTRIBUTE_UNUSED;
3166 int incoming ATTRIBUTE_UNUSED;
3168 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3173 /* Return a marker for use in the call instruction. */
3174 if (xmode == VOIDmode)
3180 else if (arg_num <= LAST_ARG_REGNUM)
3182 ret = gen_rtx (REG, xmode, arg_num);
3183 debstr = reg_names[arg_num];
3192 if (TARGET_DEBUG_ARG)
3194 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3195 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3201 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3202 advance past an argument in the argument list. The values MODE, TYPE and
3203 NAMED describe that argument. Once this is done, the variable CUM is
3204 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3206 This macro need not do anything if the argument in question was passed on
3207 the stack. The compiler knows how to track the amount of stack space used
3208 for arguments without any special help. */
3211 frv_function_arg_advance (cum, mode, type, named)
3212 CUMULATIVE_ARGS *cum;
3213 enum machine_mode mode;
3214 tree type ATTRIBUTE_UNUSED;
3217 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3218 int bytes = GET_MODE_SIZE (xmode);
3219 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3222 *cum = arg_num + words;
3224 if (TARGET_DEBUG_ARG)
3226 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3227 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3231 /* A C expression for the number of words, at the beginning of an argument,
3232 must be put in registers. The value must be zero for arguments that are
3233 passed entirely in registers or that are entirely pushed on the stack.
3235 On some machines, certain arguments must be passed partially in registers
3236 and partially in memory. On these machines, typically the first N words of
3237 arguments are passed in registers, and the rest on the stack. If a
3238 multi-word argument (a `double' or a structure) crosses that boundary, its
3239 first few words must be passed in registers and the rest must be pushed.
3240 This macro tells the compiler when this occurs, and how many of the words
3241 should go in registers.
3243 `FUNCTION_ARG' for these arguments should return the first register to be
3244 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3245 the called function. */
3248 frv_function_arg_partial_nregs (cum, mode, type, named)
3249 CUMULATIVE_ARGS *cum;
3250 enum machine_mode mode;
3251 tree type ATTRIBUTE_UNUSED;
3252 int named ATTRIBUTE_UNUSED;
3254 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3255 int bytes = GET_MODE_SIZE (xmode);
3256 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3260 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3261 ? LAST_ARG_REGNUM - arg_num + 1
3264 if (TARGET_DEBUG_ARG && ret)
3265 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3273 /* A C expression that indicates when an argument must be passed by reference.
3274 If nonzero for an argument, a copy of that argument is made in memory and a
3275 pointer to the argument is passed instead of the argument itself. The
3276 pointer is passed in whatever way is appropriate for passing a pointer to
3279 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3280 definition of this macro might be
3281 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3282 MUST_PASS_IN_STACK (MODE, TYPE) */
3285 frv_function_arg_pass_by_reference (cum, mode, type, named)
3286 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3287 enum machine_mode mode;
3289 int named ATTRIBUTE_UNUSED;
3291 return MUST_PASS_IN_STACK (mode, type);
3294 /* If defined, a C expression that indicates when it is the called function's
3295 responsibility to make a copy of arguments passed by invisible reference.
3296 Normally, the caller makes a copy and passes the address of the copy to the
3297 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3298 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3299 the "live" value. The called function must not modify this value. If it
3300 can be determined that the value won't be modified, it need not make a copy;
3301 otherwise a copy must be made. */
3304 frv_function_arg_callee_copies (cum, mode, type, named)
3305 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3306 enum machine_mode mode ATTRIBUTE_UNUSED;
3307 tree type ATTRIBUTE_UNUSED;
3308 int named ATTRIBUTE_UNUSED;
3313 /* If defined, a C expression that indicates when it is more desirable to keep
3314 an argument passed by invisible reference as a reference, rather than
3315 copying it to a pseudo register. */
3318 frv_function_arg_keep_as_reference (cum, mode, type, named)
3319 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3320 enum machine_mode mode ATTRIBUTE_UNUSED;
3321 tree type ATTRIBUTE_UNUSED;
3322 int named ATTRIBUTE_UNUSED;
3328 /* Return true if a register is ok to use as a base or index register. */
3330 static FRV_INLINE int
3331 frv_regno_ok_for_base_p (regno, strict_p)
3339 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3341 if (regno == ARG_POINTER_REGNUM)
3344 return (regno >= FIRST_PSEUDO_REGISTER);
3348 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3349 RTX) is a legitimate memory address on the target machine for a memory
3350 operand of mode MODE.
3352 It usually pays to define several simpler macros to serve as subroutines for
3353 this one. Otherwise it may be too complicated to understand.
3355 This macro must exist in two variants: a strict variant and a non-strict
3356 one. The strict variant is used in the reload pass. It must be defined so
3357 that any pseudo-register that has not been allocated a hard register is
3358 considered a memory reference. In contexts where some kind of register is
3359 required, a pseudo-register with no hard register must be rejected.
3361 The non-strict variant is used in other passes. It must be defined to
3362 accept all pseudo-registers in every context where some kind of register is
3365 Compiler source files that want to use the strict variant of this macro
3366 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3367 conditional to define the strict variant in that case and the non-strict
3370 Subroutines to check for acceptable registers for various purposes (one for
3371 base registers, one for index registers, and so on) are typically among the
3372 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3373 subroutine macros need have two variants; the higher levels of macros may be
3374 the same whether strict or not.
3376 Normally, constant addresses which are the sum of a `symbol_ref' and an
3377 integer are stored inside a `const' RTX to mark them as constant.
3378 Therefore, there is no need to recognize such sums specifically as
3379 legitimate addresses. Normally you would simply recognize any `const' as
3382 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3383 are not marked with `const'. It assumes that a naked `plus' indicates
3384 indexing. If so, then you *must* reject such naked constant sums as
3385 illegitimate addresses, so that none of them will be given to
3386 `PRINT_OPERAND_ADDRESS'.
3388 On some machines, whether a symbolic address is legitimate depends on the
3389 section that the address refers to. On these machines, define the macro
3390 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3391 then check for it here. When you see a `const', you will have to look
3392 inside it to find the `symbol_ref' in order to determine the section.
3394 The best way to modify the name string is by adding text to the beginning,
3395 with suitable punctuation to prevent any ambiguity. Allocate the new name
3396 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3397 remove and decode the added text and output the name accordingly, and define
3398 `(* targetm.strip_name_encoding)' to access the original name string.
3400 You can check the information stored here into the `symbol_ref' in the
3401 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3402 `PRINT_OPERAND_ADDRESS'. */
3405 frv_legitimate_address_p (mode, x, strict_p, condexec_p)
3406 enum machine_mode mode;
3413 HOST_WIDE_INT value;
3416 switch (GET_CODE (x))
3423 if (GET_CODE (x) != REG)
3429 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3435 if (GET_CODE (x0) != REG
3436 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3437 || GET_CODE (x1) != PLUS
3438 || ! rtx_equal_p (x0, XEXP (x1, 0))
3439 || GET_CODE (XEXP (x1, 1)) != REG
3440 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3447 /* 12 bit immediate */
3452 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3454 /* If we can't use load/store double operations, make sure we can
3455 address the second word. */
3456 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3457 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3466 if (GET_CODE (x0) == SUBREG)
3467 x0 = SUBREG_REG (x0);
3469 if (GET_CODE (x0) != REG)
3472 regno0 = REGNO (x0);
3473 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3476 switch (GET_CODE (x1))
3482 x1 = SUBREG_REG (x1);
3483 if (GET_CODE (x1) != REG)
3489 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3490 on having move double instructions */
3491 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3494 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3498 /* 12 bit immediate */
3503 value = INTVAL (x1);
3504 ret = IN_RANGE_P (value, -2048, 2047);
3506 /* If we can't use load/store double operations, make sure we can
3507 address the second word. */
3508 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3509 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3515 && regno0 == SDA_BASE_REG
3516 && symbol_ref_small_data_p (x1))
3521 if (!condexec_p && regno0 == SDA_BASE_REG && const_small_data_p (x1))
3529 if (TARGET_DEBUG_ADDR)
3531 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3532 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3533 (condexec_p) ? ", inside conditional code" : "");
3541 /* A C compound statement that attempts to replace X with a valid memory
3542 address for an operand of mode MODE. WIN will be a C statement label
3543 elsewhere in the code; the macro definition may use
3545 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3547 to avoid further processing if the address has become legitimate.
3549 X will always be the result of a call to `break_out_memory_refs', and OLDX
3550 will be the operand that was given to that function to produce X.
3552 The code generated by this macro should not alter the substructure of X. If
3553 it transforms X into a more legitimate form, it should assign X (which will
3554 always be a C variable) a new value.
3556 It is not necessary for this macro to come up with a legitimate address.
3557 The compiler has standard ways of doing so in all cases. In fact, it is
3558 safe for this macro to do nothing. But often a machine-dependent strategy
3559 can generate better code. */
3562 frv_legitimize_address (x, oldx, mode)
3564 rtx oldx ATTRIBUTE_UNUSED;
3565 enum machine_mode mode ATTRIBUTE_UNUSED;
3569 /* Don't try to legitimize addresses if we are not optimizing, since the
3570 address we generate is not a general operand, and will horribly mess
3571 things up when force_reg is called to try and put it in a register because
3572 we aren't optimizing. */
3574 && ((GET_CODE (x) == SYMBOL_REF && symbol_ref_small_data_p (x))
3575 || (GET_CODE (x) == CONST && const_small_data_p (x))))
3577 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x);
3579 cfun->uses_pic_offset_table = TRUE;
3582 if (TARGET_DEBUG_ADDR && ret != NULL_RTX)
3584 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3585 GET_MODE_NAME (mode));
3592 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3593 the operand is used by a predicated instruction. */
3596 frv_legitimate_memory_operand (op, mode, condexec_p)
3598 enum machine_mode mode;
3601 return ((GET_MODE (op) == mode || mode == VOIDmode)
3602 && GET_CODE (op) == MEM
3603 && frv_legitimate_address_p (mode, XEXP (op, 0),
3604 reload_completed, condexec_p));
3608 /* Return 1 is OP is a memory operand, or will be turned into one by
3611 int frv_load_operand (op, mode)
3613 enum machine_mode mode;
3615 if (GET_MODE (op) != mode && mode != VOIDmode)
3618 if (reload_in_progress)
3621 if (GET_CODE (tmp) == SUBREG)
3622 tmp = SUBREG_REG (tmp);
3623 if (GET_CODE (tmp) == REG
3624 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3625 op = reg_equiv_memory_loc[REGNO (tmp)];
3628 return op && memory_operand (op, mode);
3632 /* Return 1 if operand is a GPR register or a FPR register. */
3634 int gpr_or_fpr_operand (op, mode)
3636 enum machine_mode mode;
3640 if (GET_MODE (op) != mode && mode != VOIDmode)
3643 if (GET_CODE (op) == SUBREG)
3645 if (GET_CODE (SUBREG_REG (op)) != REG)
3646 return register_operand (op, mode);
3648 op = SUBREG_REG (op);
3651 if (GET_CODE (op) != REG)
3655 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3661 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3663 int gpr_or_int12_operand (op, mode)
3665 enum machine_mode mode;
3667 if (GET_CODE (op) == CONST_INT)
3668 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3670 if (GET_MODE (op) != mode && mode != VOIDmode)
3673 if (GET_CODE (op) == SUBREG)
3675 if (GET_CODE (SUBREG_REG (op)) != REG)
3676 return register_operand (op, mode);
3678 op = SUBREG_REG (op);
3681 if (GET_CODE (op) != REG)
3684 return GPR_OR_PSEUDO_P (REGNO (op));
3687 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3688 signed immediate. */
3690 int gpr_fpr_or_int12_operand (op, mode)
3692 enum machine_mode mode;
3696 if (GET_CODE (op) == CONST_INT)
3697 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3699 if (GET_MODE (op) != mode && mode != VOIDmode)
3702 if (GET_CODE (op) == SUBREG)
3704 if (GET_CODE (SUBREG_REG (op)) != REG)
3705 return register_operand (op, mode);
3707 op = SUBREG_REG (op);
3710 if (GET_CODE (op) != REG)
3714 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3720 /* Return 1 if operand is a register or 6 bit signed immediate. */
3722 int fpr_or_int6_operand (op, mode)
3724 enum machine_mode mode;
3726 if (GET_CODE (op) == CONST_INT)
3727 return IN_RANGE_P (INTVAL (op), -32, 31);
3729 if (GET_MODE (op) != mode && mode != VOIDmode)
3732 if (GET_CODE (op) == SUBREG)
3734 if (GET_CODE (SUBREG_REG (op)) != REG)
3735 return register_operand (op, mode);
3737 op = SUBREG_REG (op);
3740 if (GET_CODE (op) != REG)
3743 return FPR_OR_PSEUDO_P (REGNO (op));
3746 /* Return 1 if operand is a register or 10 bit signed immediate. */
3748 int gpr_or_int10_operand (op, mode)
3750 enum machine_mode mode;
3752 if (GET_CODE (op) == CONST_INT)
3753 return IN_RANGE_P (INTVAL (op), -512, 511);
3755 if (GET_MODE (op) != mode && mode != VOIDmode)
3758 if (GET_CODE (op) == SUBREG)
3760 if (GET_CODE (SUBREG_REG (op)) != REG)
3761 return register_operand (op, mode);
3763 op = SUBREG_REG (op);
3766 if (GET_CODE (op) != REG)
3769 return GPR_OR_PSEUDO_P (REGNO (op));
3772 /* Return 1 if operand is a register or an integer immediate. */
3774 int gpr_or_int_operand (op, mode)
3776 enum machine_mode mode;
3778 if (GET_CODE (op) == CONST_INT)
3781 if (GET_MODE (op) != mode && mode != VOIDmode)
3784 if (GET_CODE (op) == SUBREG)
3786 if (GET_CODE (SUBREG_REG (op)) != REG)
3787 return register_operand (op, mode);
3789 op = SUBREG_REG (op);
3792 if (GET_CODE (op) != REG)
3795 return GPR_OR_PSEUDO_P (REGNO (op));
3798 /* Return 1 if operand is a 12 bit signed immediate. */
3800 int int12_operand (op, mode)
3802 enum machine_mode mode ATTRIBUTE_UNUSED;
3804 if (GET_CODE (op) != CONST_INT)
3807 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3810 /* Return 1 if operand is a 6 bit signed immediate. */
3812 int int6_operand (op, mode)
3814 enum machine_mode mode ATTRIBUTE_UNUSED;
3816 if (GET_CODE (op) != CONST_INT)
3819 return IN_RANGE_P (INTVAL (op), -32, 31);
3822 /* Return 1 if operand is a 5 bit signed immediate. */
3824 int int5_operand (op, mode)
3826 enum machine_mode mode ATTRIBUTE_UNUSED;
3828 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3831 /* Return 1 if operand is a 5 bit unsigned immediate. */
3833 int uint5_operand (op, mode)
3835 enum machine_mode mode ATTRIBUTE_UNUSED;
3837 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3840 /* Return 1 if operand is a 4 bit unsigned immediate. */
3842 int uint4_operand (op, mode)
3844 enum machine_mode mode ATTRIBUTE_UNUSED;
3846 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3849 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3851 int uint1_operand (op, mode)
3853 enum machine_mode mode ATTRIBUTE_UNUSED;
3855 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3858 /* Return 1 if operand is an integer constant that takes 2 instructions
3859 to load up and can be split into sethi/setlo instructions.. */
3861 int int_2word_operand (op, mode)
3863 enum machine_mode mode ATTRIBUTE_UNUSED;
3865 HOST_WIDE_INT value;
3869 switch (GET_CODE (op))
3875 return (flag_pic == 0);
3878 /* small data references are already 1 word */
3879 return (flag_pic == 0) && (! const_small_data_p (op));
3882 /* small data references are already 1 word */
3883 return (flag_pic == 0) && (! symbol_ref_small_data_p (op));
3886 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3889 if (GET_MODE (op) == SFmode)
3891 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3892 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3894 return ! IN_RANGE_P (value, -32768, 32767);
3896 else if (GET_MODE (op) == VOIDmode)
3898 value = CONST_DOUBLE_LOW (op);
3899 return ! IN_RANGE_P (value, -32768, 32767);
3907 /* Return 1 if operand is the pic address register. */
3909 pic_register_operand (op, mode)
3911 enum machine_mode mode ATTRIBUTE_UNUSED;
3916 if (GET_CODE (op) != REG)
3919 if (REGNO (op) != PIC_REGNO)
3925 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3926 that takes 3 seperate instructions to form. */
3928 int pic_symbolic_operand (op, mode)
3930 enum machine_mode mode ATTRIBUTE_UNUSED;
3935 switch (GET_CODE (op))
3944 /* small data references are already 1 word */
3945 return ! symbol_ref_small_data_p (op);
3948 /* small data references are already 1 word */
3949 return ! const_small_data_p (op);
3955 /* Return 1 if operand is the small data register. */
3957 small_data_register_operand (op, mode)
3959 enum machine_mode mode ATTRIBUTE_UNUSED;
3961 if (GET_CODE (op) != REG)
3964 if (REGNO (op) != SDA_BASE_REG)
3970 /* Return 1 if operand is a symbolic reference to a small data area static or
3973 int small_data_symbolic_operand (op, mode)
3975 enum machine_mode mode ATTRIBUTE_UNUSED;
3977 switch (GET_CODE (op))
3983 return const_small_data_p (op);
3986 return symbol_ref_small_data_p (op);
3992 /* Return 1 if operand is a 16 bit unsigned immediate */
3994 int uint16_operand (op, mode)
3996 enum machine_mode mode ATTRIBUTE_UNUSED;
3998 if (GET_CODE (op) != CONST_INT)
4001 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
4004 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
4006 int upper_int16_operand (op, mode)
4008 enum machine_mode mode ATTRIBUTE_UNUSED;
4010 if (GET_CODE (op) != CONST_INT)
4013 return ((INTVAL (op) & 0xffff) == 0);
4016 /* Return true if operand is a GPR register. */
4019 integer_register_operand (op, mode)
4021 enum machine_mode mode;
4023 if (GET_MODE (op) != mode && mode != VOIDmode)
4026 if (GET_CODE (op) == SUBREG)
4028 if (GET_CODE (SUBREG_REG (op)) != REG)
4029 return register_operand (op, mode);
4031 op = SUBREG_REG (op);
4034 if (GET_CODE (op) != REG)
4037 return GPR_OR_PSEUDO_P (REGNO (op));
4040 /* Return true if operand is a GPR register. Do not allow SUBREG's
4041 here, in order to prevent a combine bug. */
4044 gpr_no_subreg_operand (op, mode)
4046 enum machine_mode mode;
4048 if (GET_MODE (op) != mode && mode != VOIDmode)
4051 if (GET_CODE (op) != REG)
4054 return GPR_OR_PSEUDO_P (REGNO (op));
4057 /* Return true if operand is a FPR register. */
4060 fpr_operand (op, mode)
4062 enum machine_mode mode;
4064 if (GET_MODE (op) != mode && mode != VOIDmode)
4067 if (GET_CODE (op) == SUBREG)
4069 if (GET_CODE (SUBREG_REG (op)) != REG)
4070 return register_operand (op, mode);
4072 op = SUBREG_REG (op);
4075 if (GET_CODE (op) != REG)
4078 return FPR_OR_PSEUDO_P (REGNO (op));
4081 /* Return true if operand is an even GPR or FPR register. */
4084 even_reg_operand (op, mode)
4086 enum machine_mode mode;
4090 if (GET_MODE (op) != mode && mode != VOIDmode)
4093 if (GET_CODE (op) == SUBREG)
4095 if (GET_CODE (SUBREG_REG (op)) != REG)
4096 return register_operand (op, mode);
4098 op = SUBREG_REG (op);
4101 if (GET_CODE (op) != REG)
4105 if (regno >= FIRST_PSEUDO_REGISTER)
4109 return (((regno - GPR_FIRST) & 1) == 0);
4112 return (((regno - FPR_FIRST) & 1) == 0);
4117 /* Return true if operand is an odd GPR register. */
4120 odd_reg_operand (op, mode)
4122 enum machine_mode mode;
4126 if (GET_MODE (op) != mode && mode != VOIDmode)
4129 if (GET_CODE (op) == SUBREG)
4131 if (GET_CODE (SUBREG_REG (op)) != REG)
4132 return register_operand (op, mode);
4134 op = SUBREG_REG (op);
4137 if (GET_CODE (op) != REG)
4141 /* assume that reload will give us an even register */
4142 if (regno >= FIRST_PSEUDO_REGISTER)
4146 return (((regno - GPR_FIRST) & 1) != 0);
4149 return (((regno - FPR_FIRST) & 1) != 0);
4154 /* Return true if operand is an even GPR register. */
4157 even_gpr_operand (op, mode)
4159 enum machine_mode mode;
4163 if (GET_MODE (op) != mode && mode != VOIDmode)
4166 if (GET_CODE (op) == SUBREG)
4168 if (GET_CODE (SUBREG_REG (op)) != REG)
4169 return register_operand (op, mode);
4171 op = SUBREG_REG (op);
4174 if (GET_CODE (op) != REG)
4178 if (regno >= FIRST_PSEUDO_REGISTER)
4181 if (! GPR_P (regno))
4184 return (((regno - GPR_FIRST) & 1) == 0);
4187 /* Return true if operand is an odd GPR register. */
4190 odd_gpr_operand (op, mode)
4192 enum machine_mode mode;
4196 if (GET_MODE (op) != mode && mode != VOIDmode)
4199 if (GET_CODE (op) == SUBREG)
4201 if (GET_CODE (SUBREG_REG (op)) != REG)
4202 return register_operand (op, mode);
4204 op = SUBREG_REG (op);
4207 if (GET_CODE (op) != REG)
4211 /* assume that reload will give us an even register */
4212 if (regno >= FIRST_PSEUDO_REGISTER)
4215 if (! GPR_P (regno))
4218 return (((regno - GPR_FIRST) & 1) != 0);
4221 /* Return true if operand is a quad aligned FPR register. */
4224 quad_fpr_operand (op, mode)
4226 enum machine_mode mode;
4230 if (GET_MODE (op) != mode && mode != VOIDmode)
4233 if (GET_CODE (op) == SUBREG)
4235 if (GET_CODE (SUBREG_REG (op)) != REG)
4236 return register_operand (op, mode);
4238 op = SUBREG_REG (op);
4241 if (GET_CODE (op) != REG)
4245 if (regno >= FIRST_PSEUDO_REGISTER)
4248 if (! FPR_P (regno))
4251 return (((regno - FPR_FIRST) & 3) == 0);
4254 /* Return true if operand is an even FPR register. */
4257 even_fpr_operand (op, mode)
4259 enum machine_mode mode;
4263 if (GET_MODE (op) != mode && mode != VOIDmode)
4266 if (GET_CODE (op) == SUBREG)
4268 if (GET_CODE (SUBREG_REG (op)) != REG)
4269 return register_operand (op, mode);
4271 op = SUBREG_REG (op);
4274 if (GET_CODE (op) != REG)
4278 if (regno >= FIRST_PSEUDO_REGISTER)
4281 if (! FPR_P (regno))
4284 return (((regno - FPR_FIRST) & 1) == 0);
4287 /* Return true if operand is an odd FPR register. */
4290 odd_fpr_operand (op, mode)
4292 enum machine_mode mode;
4296 if (GET_MODE (op) != mode && mode != VOIDmode)
4299 if (GET_CODE (op) == SUBREG)
4301 if (GET_CODE (SUBREG_REG (op)) != REG)
4302 return register_operand (op, mode);
4304 op = SUBREG_REG (op);
4307 if (GET_CODE (op) != REG)
4311 /* assume that reload will give us an even register */
4312 if (regno >= FIRST_PSEUDO_REGISTER)
4315 if (! FPR_P (regno))
4318 return (((regno - FPR_FIRST) & 1) != 0);
4321 /* Return true if operand is a 2 word memory address that can be loaded in one
4322 instruction to load or store. We assume the stack and frame pointers are
4323 suitably aligned, and variables in the small data area. FIXME -- at some we
4324 should recognize other globals and statics. We can't assume that any old
4325 pointer is aligned, given that arguments could be passed on an odd word on
4326 the stack and the address taken and passed through to another function. */
4329 dbl_memory_one_insn_operand (op, mode)
4331 enum machine_mode mode;
4339 if (GET_CODE (op) != MEM)
4342 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4345 addr = XEXP (op, 0);
4346 if (GET_CODE (addr) == REG)
4349 else if (GET_CODE (addr) == PLUS)
4351 rtx addr0 = XEXP (addr, 0);
4352 rtx addr1 = XEXP (addr, 1);
4354 if (GET_CODE (addr0) != REG)
4357 if (plus_small_data_p (addr0, addr1))
4360 if (GET_CODE (addr1) != CONST_INT)
4363 if ((INTVAL (addr1) & 7) != 0)
4372 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4378 /* Return true if operand is a 2 word memory address that needs to
4379 use two instructions to load or store. */
4382 dbl_memory_two_insn_operand (op, mode)
4384 enum machine_mode mode;
4386 if (GET_CODE (op) != MEM)
4389 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4395 return ! dbl_memory_one_insn_operand (op, mode);
4398 /* Return true if operand is something that can be an output for a move
4402 move_destination_operand (op, mode)
4404 enum machine_mode mode;
4409 switch (GET_CODE (op))
4415 if (GET_MODE (op) != mode && mode != VOIDmode)
4418 subreg = SUBREG_REG (op);
4419 code = GET_CODE (subreg);
4421 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4422 reload_completed, FALSE);
4424 return (code == REG);
4427 if (GET_MODE (op) != mode && mode != VOIDmode)
4433 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4436 return frv_legitimate_memory_operand (op, mode, FALSE);
4442 /* Return true if operand is something that can be an input for a move
4446 move_source_operand (op, mode)
4448 enum machine_mode mode;
4453 switch (GET_CODE (op))
4463 return immediate_operand (op, mode);
4466 if (GET_MODE (op) != mode && mode != VOIDmode)
4469 subreg = SUBREG_REG (op);
4470 code = GET_CODE (subreg);
4472 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4473 reload_completed, FALSE);
4475 return (code == REG);
4478 if (GET_MODE (op) != mode && mode != VOIDmode)
4484 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4487 return frv_legitimate_memory_operand (op, mode, FALSE);
4493 /* Return true if operand is something that can be an output for a conditional
4497 condexec_dest_operand (op, mode)
4499 enum machine_mode mode;
4504 switch (GET_CODE (op))
4510 if (GET_MODE (op) != mode && mode != VOIDmode)
4513 subreg = SUBREG_REG (op);
4514 code = GET_CODE (subreg);
4516 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4517 reload_completed, TRUE);
4519 return (code == REG);
4522 if (GET_MODE (op) != mode && mode != VOIDmode)
4528 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4531 return frv_legitimate_memory_operand (op, mode, TRUE);
4537 /* Return true if operand is something that can be an input for a conditional
4541 condexec_source_operand (op, mode)
4543 enum machine_mode mode;
4548 switch (GET_CODE (op))
4558 if (GET_MODE (op) != mode && mode != VOIDmode)
4561 subreg = SUBREG_REG (op);
4562 code = GET_CODE (subreg);
4564 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4565 reload_completed, TRUE);
4567 return (code == REG);
4570 if (GET_MODE (op) != mode && mode != VOIDmode)
4576 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4579 return frv_legitimate_memory_operand (op, mode, TRUE);
4585 /* Return true if operand is a register of any flavor or a 0 of the
4586 appropriate type. */
4589 reg_or_0_operand (op, mode)
4591 enum machine_mode mode;
4593 switch (GET_CODE (op))
4600 if (GET_MODE (op) != mode && mode != VOIDmode)
4603 return register_operand (op, mode);
4613 /* Return true if operand is the link register */
4616 lr_operand (op, mode)
4618 enum machine_mode mode;
4620 if (GET_CODE (op) != REG)
4623 if (GET_MODE (op) != mode && mode != VOIDmode)
4626 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4632 /* Return true if operand is a gpr register or a valid memory operation. */
4635 gpr_or_memory_operand (op, mode)
4637 enum machine_mode mode;
4639 return (integer_register_operand (op, mode)
4640 || frv_legitimate_memory_operand (op, mode, FALSE));
4643 /* Return true if operand is a fpr register or a valid memory operation. */
4646 fpr_or_memory_operand (op, mode)
4648 enum machine_mode mode;
4650 return (fpr_operand (op, mode)
4651 || frv_legitimate_memory_operand (op, mode, FALSE));
4654 /* Return true if operand is an icc register */
4657 icc_operand (op, mode)
4659 enum machine_mode mode;
4663 if (GET_MODE (op) != mode && mode != VOIDmode)
4666 if (GET_CODE (op) != REG)
4670 return ICC_OR_PSEUDO_P (regno);
4673 /* Return true if operand is an fcc register */
4676 fcc_operand (op, mode)
4678 enum machine_mode mode;
4682 if (GET_MODE (op) != mode && mode != VOIDmode)
4685 if (GET_CODE (op) != REG)
4689 return FCC_OR_PSEUDO_P (regno);
4692 /* Return true if operand is either an fcc or icc register */
4695 cc_operand (op, mode)
4697 enum machine_mode mode;
4701 if (GET_MODE (op) != mode && mode != VOIDmode)
4704 if (GET_CODE (op) != REG)
4708 if (CC_OR_PSEUDO_P (regno))
4714 /* Return true if operand is an integer CCR register */
4717 icr_operand (op, mode)
4719 enum machine_mode mode;
4723 if (GET_MODE (op) != mode && mode != VOIDmode)
4726 if (GET_CODE (op) != REG)
4730 return ICR_OR_PSEUDO_P (regno);
4733 /* Return true if operand is an fcc register */
4736 fcr_operand (op, mode)
4738 enum machine_mode mode;
4742 if (GET_MODE (op) != mode && mode != VOIDmode)
4745 if (GET_CODE (op) != REG)
4749 return FCR_OR_PSEUDO_P (regno);
4752 /* Return true if operand is either an fcc or icc register */
4755 cr_operand (op, mode)
4757 enum machine_mode mode;
4761 if (GET_MODE (op) != mode && mode != VOIDmode)
4764 if (GET_CODE (op) != REG)
4768 if (CR_OR_PSEUDO_P (regno))
4774 /* Return true if operand is a memory reference suitable for a call. */
4777 call_operand (op, mode)
4779 enum machine_mode mode;
4781 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4784 if (GET_CODE (op) == SYMBOL_REF)
4787 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4788 never occur anyway), but prevents reload from not handling the case
4789 properly of a call through a pointer on a function that calls
4790 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4791 return gpr_or_int12_operand (op, mode);
4794 /* Return true if operator is an kind of relational operator */
4797 relational_operator (op, mode)
4799 enum machine_mode mode;
4805 if (mode != VOIDmode && mode != GET_MODE (op))
4808 switch (GET_CODE (op))
4827 if (op1 != const0_rtx)
4831 if (GET_CODE (op0) != REG)
4834 regno = REGNO (op0);
4835 switch (GET_MODE (op0))
4842 return ICC_OR_PSEUDO_P (regno);
4845 return FCC_OR_PSEUDO_P (regno);
4848 return CR_OR_PSEUDO_P (regno);
4854 /* Return true if operator is a signed integer relational operator */
4857 signed_relational_operator (op, mode)
4859 enum machine_mode mode;
4865 if (mode != VOIDmode && mode != GET_MODE (op))
4868 switch (GET_CODE (op))
4883 if (op1 != const0_rtx)
4887 if (GET_CODE (op0) != REG)
4890 regno = REGNO (op0);
4891 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4894 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4900 /* Return true if operator is a signed integer relational operator */
4903 unsigned_relational_operator (op, mode)
4905 enum machine_mode mode;
4911 if (mode != VOIDmode && mode != GET_MODE (op))
4914 switch (GET_CODE (op))
4927 if (op1 != const0_rtx)
4931 if (GET_CODE (op0) != REG)
4934 regno = REGNO (op0);
4935 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4938 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4944 /* Return true if operator is a floating point relational operator */
4947 float_relational_operator (op, mode)
4949 enum machine_mode mode;
4955 if (mode != VOIDmode && mode != GET_MODE (op))
4958 switch (GET_CODE (op))
4977 if (op1 != const0_rtx)
4981 if (GET_CODE (op0) != REG)
4984 regno = REGNO (op0);
4985 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4988 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4994 /* Return true if operator is EQ/NE of a conditional execution register. */
4997 ccr_eqne_operator (op, mode)
4999 enum machine_mode mode;
5001 enum machine_mode op_mode = GET_MODE (op);
5006 if (mode != VOIDmode && op_mode != mode)
5009 switch (GET_CODE (op))
5020 if (op1 != const0_rtx)
5024 if (GET_CODE (op0) != REG)
5027 regno = REGNO (op0);
5028 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
5034 /* Return true if operator is a minimum or maximum operator (both signed and
5038 minmax_operator (op, mode)
5040 enum machine_mode mode;
5042 if (mode != VOIDmode && mode != GET_MODE (op))
5045 switch (GET_CODE (op))
5057 if (! integer_register_operand (XEXP (op, 0), mode))
5060 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5066 /* Return true if operator is an integer binary operator that can executed
5067 conditionally and takes 1 cycle. */
5070 condexec_si_binary_operator (op, mode)
5072 enum machine_mode mode;
5074 enum machine_mode op_mode = GET_MODE (op);
5076 if (mode != VOIDmode && op_mode != mode)
5079 switch (GET_CODE (op))
5096 /* Return true if operator is an integer binary operator that can be
5097 executed conditionally by a media instruction. */
5100 condexec_si_media_operator (op, mode)
5102 enum machine_mode mode;
5104 enum machine_mode op_mode = GET_MODE (op);
5106 if (mode != VOIDmode && op_mode != mode)
5109 switch (GET_CODE (op))
5121 /* Return true if operator is an integer division operator that can executed
5125 condexec_si_divide_operator (op, mode)
5127 enum machine_mode mode;
5129 enum machine_mode op_mode = GET_MODE (op);
5131 if (mode != VOIDmode && op_mode != mode)
5134 switch (GET_CODE (op))
5145 /* Return true if operator is an integer unary operator that can executed
5149 condexec_si_unary_operator (op, mode)
5151 enum machine_mode mode;
5153 enum machine_mode op_mode = GET_MODE (op);
5155 if (mode != VOIDmode && op_mode != mode)
5158 switch (GET_CODE (op))
5169 /* Return true if operator is a conversion-type expression that can be
5170 evaluated conditionally by floating-point instructions. */
5173 condexec_sf_conv_operator (op, mode)
5175 enum machine_mode mode;
5177 enum machine_mode op_mode = GET_MODE (op);
5179 if (mode != VOIDmode && op_mode != mode)
5182 switch (GET_CODE (op))
5193 /* Return true if operator is an addition or subtraction expression.
5194 Such expressions can be evaluated conditionally by floating-point
5198 condexec_sf_add_operator (op, mode)
5200 enum machine_mode mode;
5202 enum machine_mode op_mode = GET_MODE (op);
5204 if (mode != VOIDmode && op_mode != mode)
5207 switch (GET_CODE (op))
5218 /* Return true if the memory operand is one that can be conditionally
5222 condexec_memory_operand (op, mode)
5224 enum machine_mode mode;
5226 enum machine_mode op_mode = GET_MODE (op);
5229 if (mode != VOIDmode && op_mode != mode)
5244 if (GET_CODE (op) != MEM)
5247 addr = XEXP (op, 0);
5248 if (GET_CODE (addr) == ADDRESSOF)
5251 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE);
5254 /* Return true if operator is an integer binary operator that can be combined
5255 with a setcc operation. Do not allow the arithmetic operations that could
5256 potentially overflow since the FR-V sets the condition code based on the
5257 "true" value of the result, not the result after truncating to a 32-bit
5261 intop_compare_operator (op, mode)
5263 enum machine_mode mode;
5265 enum machine_mode op_mode = GET_MODE (op);
5267 if (mode != VOIDmode && op_mode != mode)
5270 switch (GET_CODE (op))
5283 if (! integer_register_operand (XEXP (op, 0), SImode))
5286 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5292 /* Return true if operator is an integer binary operator that can be combined
5293 with a setcc operation inside of a conditional execution. */
5296 condexec_intop_cmp_operator (op, mode)
5298 enum machine_mode mode;
5300 enum machine_mode op_mode = GET_MODE (op);
5302 if (mode != VOIDmode && op_mode != mode)
5305 switch (GET_CODE (op))
5318 if (! integer_register_operand (XEXP (op, 0), SImode))
5321 if (! integer_register_operand (XEXP (op, 1), SImode))
5327 /* Return 1 if operand is a valid ACC register number */
5330 acc_operand (op, mode)
5332 enum machine_mode mode;
5336 if (GET_MODE (op) != mode && mode != VOIDmode)
5339 if (GET_CODE (op) == SUBREG)
5341 if (GET_CODE (SUBREG_REG (op)) != REG)
5342 return register_operand (op, mode);
5344 op = SUBREG_REG (op);
5347 if (GET_CODE (op) != REG)
5351 return ACC_OR_PSEUDO_P (regno);
5354 /* Return 1 if operand is a valid even ACC register number */
5357 even_acc_operand (op, mode)
5359 enum machine_mode mode;
5363 if (GET_MODE (op) != mode && mode != VOIDmode)
5366 if (GET_CODE (op) == SUBREG)
5368 if (GET_CODE (SUBREG_REG (op)) != REG)
5369 return register_operand (op, mode);
5371 op = SUBREG_REG (op);
5374 if (GET_CODE (op) != REG)
5378 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5381 /* Return 1 if operand is zero or four */
5384 quad_acc_operand (op, mode)
5386 enum machine_mode mode;
5390 if (GET_MODE (op) != mode && mode != VOIDmode)
5393 if (GET_CODE (op) == SUBREG)
5395 if (GET_CODE (SUBREG_REG (op)) != REG)
5396 return register_operand (op, mode);
5398 op = SUBREG_REG (op);
5401 if (GET_CODE (op) != REG)
5405 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5408 /* Return 1 if operand is a valid ACCG register number */
5411 accg_operand (op, mode)
5413 enum machine_mode mode;
5415 if (GET_MODE (op) != mode && mode != VOIDmode)
5418 if (GET_CODE (op) == SUBREG)
5420 if (GET_CODE (SUBREG_REG (op)) != REG)
5421 return register_operand (op, mode);
5423 op = SUBREG_REG (op);
5426 if (GET_CODE (op) != REG)
5429 return ACCG_OR_PSEUDO_P (REGNO (op));
5433 /* Return true if the bare return instruction can be used outside of the
5434 epilog code. For frv, we only do it if there was no stack allocation. */
5441 if (!reload_completed)
5444 info = frv_stack_info ();
5445 return (info->total_size == 0);
5449 /* Emit code to handle a MOVSI, adding in the small data register or pic
5450 register if needed to load up addresses. Return TRUE if the appropriate
5451 instructions are emitted. */
5454 frv_emit_movsi (dest, src)
5458 int base_regno = -1;
5460 if (!reload_in_progress
5461 && !reload_completed
5462 && !register_operand (dest, SImode)
5463 && (!reg_or_0_operand (src, SImode)
5464 /* Virtual registers will almost always be replaced by an
5465 add instruction, so expose this to CSE by copying to
5466 an intermediate register */
5467 || (GET_CODE (src) == REG
5468 && IN_RANGE_P (REGNO (src),
5469 FIRST_VIRTUAL_REGISTER,
5470 LAST_VIRTUAL_REGISTER))))
5472 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5476 /* Explicitly add in the PIC or small data register if needed. */
5477 switch (GET_CODE (src))
5484 base_regno = PIC_REGNO;
5489 if (const_small_data_p (src))
5490 base_regno = SDA_BASE_REG;
5493 base_regno = PIC_REGNO;
5498 if (symbol_ref_small_data_p (src))
5499 base_regno = SDA_BASE_REG;
5502 base_regno = PIC_REGNO;
5507 if (base_regno >= 0)
5509 emit_insn (gen_rtx_SET (VOIDmode, dest,
5510 gen_rtx_PLUS (Pmode,
5511 gen_rtx_REG (Pmode, base_regno),
5514 if (base_regno == PIC_REGNO)
5515 cfun->uses_pic_offset_table = TRUE;
5524 /* Return a string to output a single word move. */
5527 output_move_single (operands, insn)
5531 rtx dest = operands[0];
5532 rtx src = operands[1];
5534 if (GET_CODE (dest) == REG)
5536 int dest_regno = REGNO (dest);
5537 enum machine_mode mode = GET_MODE (dest);
5539 if (GPR_P (dest_regno))
5541 if (GET_CODE (src) == REG)
5543 /* gpr <- some sort of register */
5544 int src_regno = REGNO (src);
5546 if (GPR_P (src_regno))
5547 return "mov %1, %0";
5549 else if (FPR_P (src_regno))
5550 return "movfg %1, %0";
5552 else if (SPR_P (src_regno))
5553 return "movsg %1, %0";
5556 else if (GET_CODE (src) == MEM)
5565 return "ldsb%I1%U1 %M1,%0";
5568 return "ldsh%I1%U1 %M1,%0";
5572 return "ld%I1%U1 %M1, %0";
5576 else if (GET_CODE (src) == CONST_INT
5577 || GET_CODE (src) == CONST_DOUBLE)
5579 /* gpr <- integer/floating constant */
5580 HOST_WIDE_INT value;
5582 if (GET_CODE (src) == CONST_INT)
5583 value = INTVAL (src);
5585 else if (mode == SFmode)
5590 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5591 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5596 value = CONST_DOUBLE_LOW (src);
5598 if (IN_RANGE_P (value, -32768, 32767))
5599 return "setlos %1, %0";
5604 else if (GET_CODE (src) == SYMBOL_REF
5605 || GET_CODE (src) == LABEL_REF
5606 || GET_CODE (src) == CONST)
5608 /* Silently fix up instances where the small data pointer is not
5609 used in the address. */
5610 if (small_data_symbolic_operand (src, GET_MODE (src)))
5611 return "addi %@, #gprel12(%1), %0";
5617 else if (FPR_P (dest_regno))
5619 if (GET_CODE (src) == REG)
5621 /* fpr <- some sort of register */
5622 int src_regno = REGNO (src);
5624 if (GPR_P (src_regno))
5625 return "movgf %1, %0";
5627 else if (FPR_P (src_regno))
5629 if (TARGET_HARD_FLOAT)
5630 return "fmovs %1, %0";
5632 return "mor %1, %1, %0";
5636 else if (GET_CODE (src) == MEM)
5645 return "ldbf%I1%U1 %M1,%0";
5648 return "ldhf%I1%U1 %M1,%0";
5652 return "ldf%I1%U1 %M1, %0";
5656 else if (ZERO_P (src))
5657 return "movgf %., %0";
5660 else if (SPR_P (dest_regno))
5662 if (GET_CODE (src) == REG)
5664 /* spr <- some sort of register */
5665 int src_regno = REGNO (src);
5667 if (GPR_P (src_regno))
5668 return "movgs %1, %0";
5673 else if (GET_CODE (dest) == MEM)
5675 if (GET_CODE (src) == REG)
5677 int src_regno = REGNO (src);
5678 enum machine_mode mode = GET_MODE (dest);
5680 if (GPR_P (src_regno))
5688 return "stb%I0%U0 %1, %M0";
5691 return "sth%I0%U0 %1, %M0";
5695 return "st%I0%U0 %1, %M0";
5699 else if (FPR_P (src_regno))
5707 return "stbf%I0%U0 %1, %M0";
5710 return "sthf%I0%U0 %1, %M0";
5714 return "stf%I0%U0 %1, %M0";
5719 else if (ZERO_P (src))
5721 switch (GET_MODE (dest))
5727 return "stb%I0%U0 %., %M0";
5730 return "sth%I0%U0 %., %M0";
5734 return "st%I0%U0 %., %M0";
5739 fatal_insn ("Bad output_move_single operand", insn);
5744 /* Return a string to output a double word move. */
5747 output_move_double (operands, insn)
5751 rtx dest = operands[0];
5752 rtx src = operands[1];
5753 enum machine_mode mode = GET_MODE (dest);
5755 if (GET_CODE (dest) == REG)
5757 int dest_regno = REGNO (dest);
5759 if (GPR_P (dest_regno))
5761 if (GET_CODE (src) == REG)
5763 /* gpr <- some sort of register */
5764 int src_regno = REGNO (src);
5766 if (GPR_P (src_regno))
5769 else if (FPR_P (src_regno))
5771 if (((dest_regno - GPR_FIRST) & 1) == 0
5772 && ((src_regno - FPR_FIRST) & 1) == 0)
5773 return "movfgd %1, %0";
5779 else if (GET_CODE (src) == MEM)
5782 if (dbl_memory_one_insn_operand (src, mode))
5783 return "ldd%I1%U1 %M1, %0";
5788 else if (GET_CODE (src) == CONST_INT
5789 || GET_CODE (src) == CONST_DOUBLE)
5793 else if (FPR_P (dest_regno))
5795 if (GET_CODE (src) == REG)
5797 /* fpr <- some sort of register */
5798 int src_regno = REGNO (src);
5800 if (GPR_P (src_regno))
5802 if (((dest_regno - FPR_FIRST) & 1) == 0
5803 && ((src_regno - GPR_FIRST) & 1) == 0)
5804 return "movgfd %1, %0";
5809 else if (FPR_P (src_regno))
5812 && ((dest_regno - FPR_FIRST) & 1) == 0
5813 && ((src_regno - FPR_FIRST) & 1) == 0)
5814 return "fmovd %1, %0";
5820 else if (GET_CODE (src) == MEM)
5823 if (dbl_memory_one_insn_operand (src, mode))
5824 return "lddf%I1%U1 %M1, %0";
5829 else if (ZERO_P (src))
5834 else if (GET_CODE (dest) == MEM)
5836 if (GET_CODE (src) == REG)
5838 int src_regno = REGNO (src);
5840 if (GPR_P (src_regno))
5842 if (((src_regno - GPR_FIRST) & 1) == 0
5843 && dbl_memory_one_insn_operand (dest, mode))
5844 return "std%I0%U0 %1, %M0";
5849 if (FPR_P (src_regno))
5851 if (((src_regno - FPR_FIRST) & 1) == 0
5852 && dbl_memory_one_insn_operand (dest, mode))
5853 return "stdf%I0%U0 %1, %M0";
5859 else if (ZERO_P (src))
5861 if (dbl_memory_one_insn_operand (dest, mode))
5862 return "std%I0%U0 %., %M0";
5868 fatal_insn ("Bad output_move_double operand", insn);
5873 /* Return a string to output a single word conditional move.
5874 Operand0 -- EQ/NE of ccr register and 0
5875 Operand1 -- CCR register
5876 Operand2 -- destination
5877 Operand3 -- source */
5880 output_condmove_single (operands, insn)
5884 rtx dest = operands[2];
5885 rtx src = operands[3];
5887 if (GET_CODE (dest) == REG)
5889 int dest_regno = REGNO (dest);
5890 enum machine_mode mode = GET_MODE (dest);
5892 if (GPR_P (dest_regno))
5894 if (GET_CODE (src) == REG)
5896 /* gpr <- some sort of register */
5897 int src_regno = REGNO (src);
5899 if (GPR_P (src_regno))
5900 return "cmov %z3, %2, %1, %e0";
5902 else if (FPR_P (src_regno))
5903 return "cmovfg %3, %2, %1, %e0";
5906 else if (GET_CODE (src) == MEM)
5915 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5918 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5922 return "cld%I3%U3 %M3, %2, %1, %e0";
5926 else if (ZERO_P (src))
5927 return "cmov %., %2, %1, %e0";
5930 else if (FPR_P (dest_regno))
5932 if (GET_CODE (src) == REG)
5934 /* fpr <- some sort of register */
5935 int src_regno = REGNO (src);
5937 if (GPR_P (src_regno))
5938 return "cmovgf %3, %2, %1, %e0";
5940 else if (FPR_P (src_regno))
5942 if (TARGET_HARD_FLOAT)
5943 return "cfmovs %3,%2,%1,%e0";
5945 return "cmor %3, %3, %2, %1, %e0";
5949 else if (GET_CODE (src) == MEM)
5952 if (mode == SImode || mode == SFmode)
5953 return "cldf%I3%U3 %M3, %2, %1, %e0";
5956 else if (ZERO_P (src))
5957 return "cmovgf %., %2, %1, %e0";
5961 else if (GET_CODE (dest) == MEM)
5963 if (GET_CODE (src) == REG)
5965 int src_regno = REGNO (src);
5966 enum machine_mode mode = GET_MODE (dest);
5968 if (GPR_P (src_regno))
5976 return "cstb%I2%U2 %3, %M2, %1, %e0";
5979 return "csth%I2%U2 %3, %M2, %1, %e0";
5983 return "cst%I2%U2 %3, %M2, %1, %e0";
5987 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5988 return "cstf%I2%U2 %3, %M2, %1, %e0";
5991 else if (ZERO_P (src))
5993 enum machine_mode mode = GET_MODE (dest);
6000 return "cstb%I2%U2 %., %M2, %1, %e0";
6003 return "csth%I2%U2 %., %M2, %1, %e0";
6007 return "cst%I2%U2 %., %M2, %1, %e0";
6012 fatal_insn ("Bad output_condmove_single operand", insn);
6017 /* Emit the appropriate code to do a comparison, returning the register the
6018 comparison was done it. */
6021 frv_emit_comparison (test, op0, op1)
6026 enum machine_mode cc_mode;
6029 /* Floating point doesn't have comparison against a constant */
6030 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6031 op1 = force_reg (GET_MODE (op0), op1);
6033 /* Possibly disable using anything but a fixed register in order to work
6034 around cse moving comparisons past function calls. */
6035 cc_mode = SELECT_CC_MODE (test, op0, op1);
6036 cc_reg = ((TARGET_ALLOC_CC)
6037 ? gen_reg_rtx (cc_mode)
6038 : gen_rtx_REG (cc_mode,
6039 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6041 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6042 gen_rtx_COMPARE (cc_mode, op0, op1)));
6048 /* Emit code for a conditional branch. The comparison operands were previously
6049 stored in frv_compare_op0 and frv_compare_op1.
6051 XXX: I originally wanted to add a clobber of a CCR register to use in
6052 conditional execution, but that confuses the rest of the compiler. */
6055 frv_emit_cond_branch (test, label)
6062 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6063 enum machine_mode cc_mode = GET_MODE (cc_reg);
6065 /* Branches generate:
6067 (if_then_else (<test>, <cc_reg>, (const_int 0))
6068 (label_ref <branch_label>)
6070 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6071 test_rtx = gen_rtx (test, cc_mode, cc_reg, const0_rtx);
6072 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6073 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6078 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6079 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6082 frv_emit_scc (test, target)
6090 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6092 /* SCC instructions generate:
6093 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6094 (clobber (<ccr_reg>))]) */
6095 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6096 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6098 cr_reg = ((TARGET_ALLOC_CC)
6099 ? gen_reg_rtx (CC_CCRmode)
6100 : gen_rtx_REG (CC_CCRmode,
6101 ((GET_MODE (cc_reg) == CC_FPmode)
6105 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6106 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6111 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6112 the seperate insns. */
6115 frv_split_scc (dest, test, cc_reg, cr_reg, value)
6120 HOST_WIDE_INT value;
6126 /* Set the appropriate CCR bit. */
6127 emit_insn (gen_rtx_SET (VOIDmode,
6129 gen_rtx_fmt_ee (GET_CODE (test),
6134 /* Move the value into the destination. */
6135 emit_move_insn (dest, GEN_INT (value));
6137 /* Move 0 into the destination if the test failed */
6138 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6139 gen_rtx_EQ (GET_MODE (cr_reg),
6142 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6144 /* Finish up, return sequence. */
6151 /* Emit the code for a conditional move, return TRUE if we could do the
6155 frv_emit_cond_move (dest, test_rtx, src1, src2)
6166 enum rtx_code test = GET_CODE (test_rtx);
6167 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6168 enum machine_mode cc_mode = GET_MODE (cc_reg);
6170 /* Conditional move instructions generate:
6171 (parallel [(set <target>
6172 (if_then_else (<test> <cc_reg> (const_int 0))
6175 (clobber (<ccr_reg>))]) */
6177 /* Handle various cases of conditional move involving two constants. */
6178 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6180 HOST_WIDE_INT value1 = INTVAL (src1);
6181 HOST_WIDE_INT value2 = INTVAL (src2);
6183 /* having 0 as one of the constants can be done by loading the other
6184 constant, and optionally moving in gr0. */
6185 if (value1 == 0 || value2 == 0)
6188 /* If the first value is within an addi range and also the difference
6189 between the two fits in an addi's range, load up the difference, then
6190 conditionally move in 0, and then unconditionally add the first
6192 else if (IN_RANGE_P (value1, -2048, 2047)
6193 && IN_RANGE_P (value2 - value1, -2048, 2047))
6196 /* If neither condition holds, just force the constant into a
6200 src1 = force_reg (GET_MODE (dest), src1);
6201 src2 = force_reg (GET_MODE (dest), src2);
6205 /* If one value is a register, insure the other value is either 0 or a
6209 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6210 src1 = force_reg (GET_MODE (dest), src1);
6212 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6213 src2 = force_reg (GET_MODE (dest), src2);
6216 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6217 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6219 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6221 cr_reg = ((TARGET_ALLOC_CC)
6222 ? gen_reg_rtx (CC_CCRmode)
6223 : gen_rtx_REG (CC_CCRmode,
6224 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6226 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6227 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6232 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6233 containing all of the insns. */
6236 frv_split_cond_move (operands)
6239 rtx dest = operands[0];
6240 rtx test = operands[1];
6241 rtx cc_reg = operands[2];
6242 rtx src1 = operands[3];
6243 rtx src2 = operands[4];
6244 rtx cr_reg = operands[5];
6246 enum machine_mode cr_mode = GET_MODE (cr_reg);
6250 /* Set the appropriate CCR bit. */
6251 emit_insn (gen_rtx_SET (VOIDmode,
6253 gen_rtx_fmt_ee (GET_CODE (test),
6258 /* Handle various cases of conditional move involving two constants. */
6259 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6261 HOST_WIDE_INT value1 = INTVAL (src1);
6262 HOST_WIDE_INT value2 = INTVAL (src2);
6264 /* having 0 as one of the constants can be done by loading the other
6265 constant, and optionally moving in gr0. */
6268 emit_move_insn (dest, src2);
6269 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6270 gen_rtx_NE (cr_mode, cr_reg,
6272 gen_rtx_SET (VOIDmode, dest, src1)));
6275 else if (value2 == 0)
6277 emit_move_insn (dest, src1);
6278 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6279 gen_rtx_EQ (cr_mode, cr_reg,
6281 gen_rtx_SET (VOIDmode, dest, src2)));
6284 /* If the first value is within an addi range and also the difference
6285 between the two fits in an addi's range, load up the difference, then
6286 conditionally move in 0, and then unconditionally add the first
6288 else if (IN_RANGE_P (value1, -2048, 2047)
6289 && IN_RANGE_P (value2 - value1, -2048, 2047))
6291 rtx dest_si = ((GET_MODE (dest) == SImode)
6293 : gen_rtx_SUBREG (SImode, dest, 0));
6295 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6296 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6297 gen_rtx_NE (cr_mode, cr_reg,
6299 gen_rtx_SET (VOIDmode, dest_si,
6301 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6309 /* Emit the conditional move for the test being true if needed. */
6310 if (! rtx_equal_p (dest, src1))
6311 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6312 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6313 gen_rtx_SET (VOIDmode, dest, src1)));
6315 /* Emit the conditional move for the test being false if needed. */
6316 if (! rtx_equal_p (dest, src2))
6317 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6318 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6319 gen_rtx_SET (VOIDmode, dest, src2)));
6322 /* Finish up, return sequence. */
6329 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6330 memory location that is not known to be dword-aligned. */
6332 frv_split_double_load (dest, source)
6336 int regno = REGNO (dest);
6337 rtx dest1 = gen_highpart (SImode, dest);
6338 rtx dest2 = gen_lowpart (SImode, dest);
6339 rtx address = XEXP (source, 0);
6341 /* If the address is pre-modified, load the lower-numbered register
6342 first, then load the other register using an integer offset from
6343 the modified base register. This order should always be safe,
6344 since the pre-modification cannot affect the same registers as the
6347 The situation for other loads is more complicated. Loading one
6348 of the registers could affect the value of ADDRESS, so we must
6349 be careful which order we do them in. */
6350 if (GET_CODE (address) == PRE_MODIFY
6351 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6353 /* It is safe to load the lower-numbered register first. */
6354 emit_move_insn (dest1, change_address (source, SImode, NULL));
6355 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6359 /* ADDRESS is not pre-modified and the address depends on the
6360 lower-numbered register. Load the higher-numbered register
6362 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6363 emit_move_insn (dest1, change_address (source, SImode, NULL));
6367 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6368 and SOURCE is either a double register or the constant zero. */
6370 frv_split_double_store (dest, source)
6374 rtx dest1 = change_address (dest, SImode, NULL);
6375 rtx dest2 = frv_index_memory (dest, SImode, 1);
6376 if (ZERO_P (source))
6378 emit_move_insn (dest1, CONST0_RTX (SImode));
6379 emit_move_insn (dest2, CONST0_RTX (SImode));
6383 emit_move_insn (dest1, gen_highpart (SImode, source));
6384 emit_move_insn (dest2, gen_lowpart (SImode, source));
6389 /* Split a min/max operation returning a SEQUENCE containing all of the
6393 frv_split_minmax (operands)
6396 rtx dest = operands[0];
6397 rtx minmax = operands[1];
6398 rtx src1 = operands[2];
6399 rtx src2 = operands[3];
6400 rtx cc_reg = operands[4];
6401 rtx cr_reg = operands[5];
6403 enum rtx_code test_code;
6404 enum machine_mode cr_mode = GET_MODE (cr_reg);
6408 /* Figure out which test to use */
6409 switch (GET_CODE (minmax))
6414 case SMIN: test_code = LT; break;
6415 case SMAX: test_code = GT; break;
6416 case UMIN: test_code = LTU; break;
6417 case UMAX: test_code = GTU; break;
6420 /* Issue the compare instruction. */
6421 emit_insn (gen_rtx_SET (VOIDmode,
6423 gen_rtx_COMPARE (GET_MODE (cc_reg),
6426 /* Set the appropriate CCR bit. */
6427 emit_insn (gen_rtx_SET (VOIDmode,
6429 gen_rtx_fmt_ee (test_code,
6434 /* If are taking the min/max of a nonzero constant, load that first, and
6435 then do a conditional move of the other value. */
6436 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6438 if (rtx_equal_p (dest, src1))
6441 emit_move_insn (dest, src2);
6442 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6443 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6444 gen_rtx_SET (VOIDmode, dest, src1)));
6447 /* Otherwise, do each half of the move. */
6450 /* Emit the conditional move for the test being true if needed. */
6451 if (! rtx_equal_p (dest, src1))
6452 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6453 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6454 gen_rtx_SET (VOIDmode, dest, src1)));
6456 /* Emit the conditional move for the test being false if needed. */
6457 if (! rtx_equal_p (dest, src2))
6458 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6459 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6460 gen_rtx_SET (VOIDmode, dest, src2)));
6463 /* Finish up, return sequence. */
6470 /* Split an integer abs operation returning a SEQUENCE containing all of the
6474 frv_split_abs (operands)
6477 rtx dest = operands[0];
6478 rtx src = operands[1];
6479 rtx cc_reg = operands[2];
6480 rtx cr_reg = operands[3];
6485 /* Issue the compare < 0 instruction. */
6486 emit_insn (gen_rtx_SET (VOIDmode,
6488 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6490 /* Set the appropriate CCR bit. */
6491 emit_insn (gen_rtx_SET (VOIDmode,
6493 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6495 /* Emit the conditional negate if the value is negative */
6496 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6497 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6498 gen_negsi2 (dest, src)));
6500 /* Emit the conditional move for the test being false if needed. */
6501 if (! rtx_equal_p (dest, src))
6502 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6503 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6504 gen_rtx_SET (VOIDmode, dest, src)));
6506 /* Finish up, return sequence. */
6513 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6514 register used in an insn. */
6517 frv_clear_registers_used (ptr, data)
6521 if (GET_CODE (*ptr) == REG)
6523 int regno = REGNO (*ptr);
6524 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6526 if (regno < FIRST_PSEUDO_REGISTER)
6528 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6530 while (regno < reg_max)
6532 CLEAR_HARD_REG_BIT (*p_regs, regno);
6542 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6544 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6545 initialize the static storage. */
6547 frv_ifcvt_init_extra_fields (ce_info)
6548 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
6550 frv_ifcvt.added_insns_list = NULL_RTX;
6551 frv_ifcvt.cur_scratch_regs = 0;
6552 frv_ifcvt.num_nested_cond_exec = 0;
6553 frv_ifcvt.cr_reg = NULL_RTX;
6554 frv_ifcvt.nested_cc_reg = NULL_RTX;
6555 frv_ifcvt.extra_int_cr = NULL_RTX;
6556 frv_ifcvt.extra_fp_cr = NULL_RTX;
6557 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6561 /* Internal function to add a potenial insn to the list of insns to be inserted
6562 if the conditional execution conversion is successful. */
6565 frv_ifcvt_add_insn (pattern, insn, before_p)
6570 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6572 link->jump = before_p; /* mark to add this before or after insn */
6573 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6574 frv_ifcvt.added_insns_list);
6576 if (TARGET_DEBUG_COND_EXEC)
6579 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6580 (before_p) ? "before" : "after",
6581 (int)INSN_UID (insn));
6583 debug_rtx (pattern);
6588 /* A C expression to modify the code described by the conditional if
6589 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6590 FALSE_EXPR for converting if-then and if-then-else code to conditional
6591 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6592 tests cannot be converted. */
6595 frv_ifcvt_modify_tests (ce_info, p_true, p_false)
6596 ce_if_block_t *ce_info;
6600 basic_block test_bb = ce_info->test_bb; /* test basic block */
6601 basic_block then_bb = ce_info->then_bb; /* THEN */
6602 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6603 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6604 rtx true_expr = *p_true;
6608 enum machine_mode mode = GET_MODE (true_expr);
6612 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6614 rtx sub_cond_exec_reg;
6616 enum rtx_code code_true;
6617 enum rtx_code code_false;
6618 enum reg_class cc_class;
6619 enum reg_class cr_class;
6623 /* Make sure we are only dealing with hard registers. Also honor the
6624 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6626 if (!reload_completed || TARGET_NO_COND_EXEC
6627 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6630 /* Figure out which registers we can allocate for our own purposes. Only
6631 consider registers that are not preserved across function calls and are
6632 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6633 if we did not need to use them in reloading other registers. */
6634 memset ((PTR) &tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6635 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6636 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6637 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6638 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6640 /* If this is a nested IF, we need to discover whether the CC registers that
6641 are set/used inside of the block are used anywhere else. If not, we can
6642 change them to be the CC register that is paired with the CR register that
6643 controls the outermost IF block. */
6644 if (ce_info->pass > 1)
6646 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6647 for (j = CC_FIRST; j <= CC_LAST; j++)
6648 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6650 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6653 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6656 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6659 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6663 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6664 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6666 frv_ifcvt.added_insns_list = NULL_RTX;
6667 frv_ifcvt.cur_scratch_regs = 0;
6669 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6670 * sizeof (basic_block));
6676 /* Remove anything live at the beginning of the join block from being
6677 available for allocation. */
6678 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6680 if (regno < FIRST_PSEUDO_REGISTER)
6681 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6685 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6687 if (ce_info->num_multiple_test_blocks)
6689 basic_block multiple_test_bb = ce_info->last_test_bb;
6691 while (multiple_test_bb != test_bb)
6693 bb[num_bb++] = multiple_test_bb;
6694 multiple_test_bb = multiple_test_bb->pred->src;
6698 /* Add in the THEN and ELSE blocks to be scanned. */
6699 bb[num_bb++] = then_bb;
6701 bb[num_bb++] = else_bb;
6703 sub_cond_exec_reg = NULL_RTX;
6704 frv_ifcvt.num_nested_cond_exec = 0;
6706 /* Scan all of the blocks for registers that must not be allocated. */
6707 for (j = 0; j < num_bb; j++)
6709 rtx last_insn = bb[j]->end;
6710 rtx insn = bb[j]->head;
6714 fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n",
6715 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6717 (int) INSN_UID (bb[j]->head),
6718 (int) INSN_UID (bb[j]->end));
6720 /* Anything live at the beginning of the block is obviously unavailable
6722 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6724 if (regno < FIRST_PSEUDO_REGISTER)
6725 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6728 /* loop through the insns in the block. */
6731 /* Mark any new registers that are created as being unavailable for
6732 allocation. Also see if the CC register used in nested IFs can be
6738 int skip_nested_if = FALSE;
6740 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6741 (void *)&tmp_reg->regs);
6743 pattern = PATTERN (insn);
6744 if (GET_CODE (pattern) == COND_EXEC)
6746 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6748 if (reg != sub_cond_exec_reg)
6750 sub_cond_exec_reg = reg;
6751 frv_ifcvt.num_nested_cond_exec++;
6755 set = single_set_pattern (pattern);
6758 rtx dest = SET_DEST (set);
6759 rtx src = SET_SRC (set);
6761 if (GET_CODE (dest) == REG)
6763 int regno = REGNO (dest);
6764 enum rtx_code src_code = GET_CODE (src);
6766 if (CC_P (regno) && src_code == COMPARE)
6767 skip_nested_if = TRUE;
6769 else if (CR_P (regno)
6770 && (src_code == IF_THEN_ELSE
6771 || GET_RTX_CLASS (src_code) == '<'))
6772 skip_nested_if = TRUE;
6776 if (! skip_nested_if)
6777 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6778 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6781 if (insn == last_insn)
6784 insn = NEXT_INSN (insn);
6788 /* If this is a nested if, rewrite the CC registers that are available to
6789 include the ones that can be rewritten, to increase the chance of being
6790 able to allocate a paired CC/CR register combination. */
6791 if (ce_info->pass > 1)
6793 for (j = CC_FIRST; j <= CC_LAST; j++)
6794 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6795 SET_HARD_REG_BIT (tmp_reg->regs, j);
6797 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6803 fprintf (rtl_dump_file, "Available GPRs: ");
6805 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6806 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6808 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6809 if (++num_gprs > GPR_TEMP_NUM+2)
6813 fprintf (rtl_dump_file, "%s\nAvailable CRs: ",
6814 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6816 for (j = CR_FIRST; j <= CR_LAST; j++)
6817 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6818 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6820 fputs ("\n", rtl_dump_file);
6822 if (ce_info->pass > 1)
6824 fprintf (rtl_dump_file, "Modifiable CCs: ");
6825 for (j = CC_FIRST; j <= CC_LAST; j++)
6826 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6827 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6829 fprintf (rtl_dump_file, "\n%d nested COND_EXEC statements\n",
6830 frv_ifcvt.num_nested_cond_exec);
6834 /* Allocate the appropriate temporary condition code register. Try to
6835 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6836 that conditional cmp's can be done. */
6837 if (mode == CCmode || mode == CC_UNSmode)
6839 cr_class = ICR_REGS;
6840 cc_class = ICC_REGS;
6841 cc_first = ICC_FIRST;
6844 else if (mode == CC_FPmode)
6846 cr_class = FCR_REGS;
6847 cc_class = FCC_REGS;
6848 cc_first = FCC_FIRST;
6853 cc_first = cc_last = 0;
6854 cr_class = cc_class = NO_REGS;
6857 cc = XEXP (true_expr, 0);
6858 nested_cc = cr = NULL_RTX;
6859 if (cc_class != NO_REGS)
6861 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6862 so we can execute a csubcc/caddcc/cfcmps instruction. */
6865 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6867 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6869 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6870 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6872 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6873 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6876 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6877 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6887 fprintf (rtl_dump_file, "Could not allocate a CR temporary register\n");
6893 fprintf (rtl_dump_file,
6894 "Will use %s for conditional execution, %s for nested comparisons\n",
6895 reg_names[ REGNO (cr)],
6896 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6898 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6899 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6900 bit being true. We don't do this for floating point, because of NaNs. */
6901 code = GET_CODE (true_expr);
6902 if (GET_MODE (cc) != CC_FPmode)
6904 code = reverse_condition (code);
6914 check_insn = gen_rtx_SET (VOIDmode, cr,
6915 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6917 /* Record the check insn to be inserted later. */
6918 frv_ifcvt_add_insn (check_insn, test_bb->end, TRUE);
6920 /* Update the tests. */
6921 frv_ifcvt.cr_reg = cr;
6922 frv_ifcvt.nested_cc_reg = nested_cc;
6923 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6924 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6927 /* Fail, don't do this conditional execution. */
6930 *p_false = NULL_RTX;
6932 fprintf (rtl_dump_file, "Disabling this conditional execution.\n");
6938 /* A C expression to modify the code described by the conditional if
6939 information CE_INFO, for the basic block BB, possibly updating the tests in
6940 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6941 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6942 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6944 /* p_true and p_false are given expressions of the form:
6946 (and (eq:CC_CCR (reg:CC_CCR)
6952 frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false)
6953 ce_if_block_t *ce_info;
6958 rtx old_true = XEXP (*p_true, 0);
6959 rtx old_false = XEXP (*p_false, 0);
6960 rtx true_expr = XEXP (*p_true, 1);
6961 rtx false_expr = XEXP (*p_false, 1);
6964 rtx cr = XEXP (old_true, 0);
6966 rtx new_cr = NULL_RTX;
6967 rtx *p_new_cr = (rtx *)0;
6971 enum reg_class cr_class;
6972 enum machine_mode mode = GET_MODE (true_expr);
6973 rtx (*logical_func)(rtx, rtx, rtx);
6975 if (TARGET_DEBUG_COND_EXEC)
6978 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6979 ce_info->and_and_p ? "&&" : "||");
6981 debug_rtx (*p_true);
6983 fputs ("\nfalse insn:\n", stderr);
6984 debug_rtx (*p_false);
6987 if (TARGET_NO_MULTI_CE)
6990 if (GET_CODE (cr) != REG)
6993 if (mode == CCmode || mode == CC_UNSmode)
6995 cr_class = ICR_REGS;
6996 p_new_cr = &frv_ifcvt.extra_int_cr;
6998 else if (mode == CC_FPmode)
7000 cr_class = FCR_REGS;
7001 p_new_cr = &frv_ifcvt.extra_fp_cr;
7006 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7007 more &&/|| tests. */
7011 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7012 CC_CCRmode, TRUE, TRUE);
7017 if (ce_info->and_and_p)
7019 old_test = old_false;
7020 test_expr = true_expr;
7021 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7022 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7023 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7027 old_test = old_false;
7028 test_expr = false_expr;
7029 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7030 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7031 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7034 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7035 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7037 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), bb->end, TRUE);
7039 /* Now add the conditional check insn. */
7040 cc = XEXP (test_expr, 0);
7041 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7042 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7044 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7046 /* add the new check insn to the list of check insns that need to be
7048 frv_ifcvt_add_insn (check_insn, bb->end, TRUE);
7050 if (TARGET_DEBUG_COND_EXEC)
7052 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7055 debug_rtx (*p_true);
7057 fputs ("\nfalse insn:\n", stderr);
7058 debug_rtx (*p_false);
7064 *p_true = *p_false = NULL_RTX;
7066 /* If we allocated a CR register, release it. */
7069 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7070 *p_new_cr = NULL_RTX;
7073 if (TARGET_DEBUG_COND_EXEC)
7074 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7080 /* Return a register which will be loaded with a value if an IF block is
7081 converted to conditional execution. This is used to rewrite instructions
7082 that use constants to ones that just use registers. */
7085 frv_ifcvt_load_value (value, insn)
7087 rtx insn ATTRIBUTE_UNUSED;
7089 int num_alloc = frv_ifcvt.cur_scratch_regs;
7093 /* We know gr0 == 0, so replace any errant uses. */
7094 if (value == const0_rtx)
7095 return gen_rtx_REG (SImode, GPR_FIRST);
7097 /* First search all registers currently loaded to see if we have an
7098 applicable constant. */
7099 if (CONSTANT_P (value)
7100 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7102 for (i = 0; i < num_alloc; i++)
7104 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7105 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7109 /* Have we exhausted the number of registers available? */
7110 if (num_alloc >= GPR_TEMP_NUM)
7113 fprintf (rtl_dump_file, "Too many temporary registers allocated\n");
7118 /* Allocate the new register. */
7119 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7123 fputs ("Could not find a scratch register\n", rtl_dump_file);
7128 frv_ifcvt.cur_scratch_regs++;
7129 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7133 if (GET_CODE (value) == CONST_INT)
7134 fprintf (rtl_dump_file, "Register %s will hold %ld\n",
7135 reg_names[ REGNO (reg)], (long)INTVAL (value));
7137 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7138 fprintf (rtl_dump_file, "Register %s will hold LR\n",
7139 reg_names[ REGNO (reg)]);
7142 fprintf (rtl_dump_file, "Register %s will hold a saved value\n",
7143 reg_names[ REGNO (reg)]);
7150 /* Update a MEM used in conditional code that might contain an offset to put
7151 the offset into a scratch register, so that the conditional load/store
7152 operations can be used. This function returns the original pointer if the
7153 MEM is valid to use in conditional code, NULL if we can't load up the offset
7154 into a temporary register, or the new MEM if we were successful. */
7157 frv_ifcvt_rewrite_mem (mem, mode, insn)
7159 enum machine_mode mode;
7162 rtx addr = XEXP (mem, 0);
7164 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE))
7166 if (GET_CODE (addr) == PLUS)
7168 rtx addr_op0 = XEXP (addr, 0);
7169 rtx addr_op1 = XEXP (addr, 1);
7171 if (plus_small_data_p (addr_op0, addr_op1))
7172 addr = frv_ifcvt_load_value (addr, insn);
7174 else if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7176 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7180 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7187 else if (CONSTANT_P (addr))
7188 addr = frv_ifcvt_load_value (addr, insn);
7193 if (addr == NULL_RTX)
7196 else if (XEXP (mem, 0) != addr)
7197 return change_address (mem, mode, addr);
7204 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7205 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7208 single_set_pattern (pattern)
7214 if (GET_CODE (pattern) == COND_EXEC)
7215 pattern = COND_EXEC_CODE (pattern);
7217 if (GET_CODE (pattern) == SET)
7220 else if (GET_CODE (pattern) == PARALLEL)
7222 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7224 rtx sub = XVECEXP (pattern, 0, i);
7226 switch (GET_CODE (sub))
7250 /* A C expression to modify the code described by the conditional if
7251 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7252 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7253 insn cannot be converted to be executed conditionally. */
7256 frv_ifcvt_modify_insn (ce_info, pattern, insn)
7257 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7261 rtx orig_ce_pattern = pattern;
7267 if (GET_CODE (pattern) != COND_EXEC)
7270 test = COND_EXEC_TEST (pattern);
7271 if (GET_CODE (test) == AND)
7273 rtx cr = frv_ifcvt.cr_reg;
7276 op0 = XEXP (test, 0);
7277 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7280 op1 = XEXP (test, 1);
7281 test_reg = XEXP (op1, 0);
7282 if (GET_CODE (test_reg) != REG)
7285 /* Is this the first nested if block in this sequence? If so, generate
7286 an andcr or andncr. */
7287 if (! frv_ifcvt.last_nested_if_cr)
7291 frv_ifcvt.last_nested_if_cr = test_reg;
7292 if (GET_CODE (op0) == NE)
7293 and_op = gen_andcr (test_reg, cr, test_reg);
7295 and_op = gen_andncr (test_reg, cr, test_reg);
7297 frv_ifcvt_add_insn (and_op, insn, TRUE);
7300 /* If this isn't the first statement in the nested if sequence, see if we
7301 are dealing with the same register. */
7302 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7305 COND_EXEC_TEST (pattern) = test = op1;
7308 /* If this isn't a nested if, reset state variables. */
7311 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7314 set = single_set_pattern (pattern);
7317 rtx dest = SET_DEST (set);
7318 rtx src = SET_SRC (set);
7319 enum machine_mode mode = GET_MODE (dest);
7321 /* Check for normal binary operators */
7323 && (GET_RTX_CLASS (GET_CODE (src)) == '2'
7324 || GET_RTX_CLASS (GET_CODE (src)) == 'c'))
7326 op0 = XEXP (src, 0);
7327 op1 = XEXP (src, 1);
7329 /* Special case load of small data address which looks like:
7331 if (GET_CODE (src) == PLUS && plus_small_data_p (op0, op1))
7333 src = frv_ifcvt_load_value (src, insn);
7335 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7340 else if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7342 op1 = frv_ifcvt_load_value (op1, insn);
7344 COND_EXEC_CODE (pattern)
7345 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7353 /* For multiply by a constant, we need to handle the sign extending
7354 correctly. Add a USE of the value after the multiply to prevent flow
7355 from cratering because only one register out of the two were used. */
7356 else if (mode == DImode && GET_CODE (src) == MULT)
7358 op0 = XEXP (src, 0);
7359 op1 = XEXP (src, 1);
7360 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7362 op1 = frv_ifcvt_load_value (op1, insn);
7365 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7366 COND_EXEC_CODE (pattern)
7367 = gen_rtx_SET (VOIDmode, dest,
7368 gen_rtx_MULT (DImode, op0, op1));
7374 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7377 /* If we are just loading a constant created for a nested conditional
7378 execution statement, just load the constant without any conditional
7379 execution, since we know that the constant will not interfere with any
7381 else if (frv_ifcvt.scratch_insns_bitmap
7382 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7386 else if (mode == QImode || mode == HImode || mode == SImode
7389 int changed_p = FALSE;
7391 /* Check for just loading up a constant */
7392 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7394 src = frv_ifcvt_load_value (src, insn);
7401 /* See if we need to fix up stores */
7402 if (GET_CODE (dest) == MEM)
7404 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7409 else if (new_mem != dest)
7416 /* See if we need to fix up loads */
7417 if (GET_CODE (src) == MEM)
7419 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7424 else if (new_mem != src)
7431 /* If either src or destination changed, redo SET. */
7433 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7436 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7437 rewriting the CC register to be the same as the paired CC/CR register
7439 else if (mode == CC_CCRmode && GET_RTX_CLASS (GET_CODE (src)) == '<')
7441 int regno = REGNO (XEXP (src, 0));
7444 if (ce_info->pass > 1
7445 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7446 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7448 src = gen_rtx_fmt_ee (GET_CODE (src),
7450 frv_ifcvt.nested_cc_reg,
7454 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7455 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7458 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7459 else if (ce_info->pass > 1
7460 && GET_CODE (dest) == REG
7461 && CC_P (REGNO (dest))
7462 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7463 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7465 && GET_CODE (src) == COMPARE)
7467 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7468 COND_EXEC_CODE (pattern)
7469 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7473 if (TARGET_DEBUG_COND_EXEC)
7475 rtx orig_pattern = PATTERN (insn);
7477 PATTERN (insn) = pattern;
7479 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7483 PATTERN (insn) = orig_pattern;
7489 if (TARGET_DEBUG_COND_EXEC)
7491 rtx orig_pattern = PATTERN (insn);
7493 PATTERN (insn) = orig_ce_pattern;
7495 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7499 PATTERN (insn) = orig_pattern;
7506 /* A C expression to perform any final machine dependent modifications in
7507 converting code to conditional execution in the code described by the
7508 conditional if information CE_INFO. */
7511 frv_ifcvt_modify_final (ce_info)
7512 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7516 rtx p = frv_ifcvt.added_insns_list;
7519 /* Loop inserting the check insns. The last check insn is the first test,
7520 and is the appropriate place to insert constants. */
7526 rtx check_and_insert_insns = XEXP (p, 0);
7529 check_insn = XEXP (check_and_insert_insns, 0);
7530 existing_insn = XEXP (check_and_insert_insns, 1);
7533 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7534 the existing insn, otherwise it is to be inserted AFTER. */
7535 if (check_and_insert_insns->jump)
7537 emit_insn_before (check_insn, existing_insn);
7538 check_and_insert_insns->jump = 0;
7541 emit_insn_after (check_insn, existing_insn);
7543 free_EXPR_LIST_node (check_and_insert_insns);
7544 free_EXPR_LIST_node (old_p);
7546 while (p != NULL_RTX);
7548 /* Load up any constants needed into temp gprs */
7549 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7551 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7552 if (! frv_ifcvt.scratch_insns_bitmap)
7553 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7554 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7555 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7558 frv_ifcvt.added_insns_list = NULL_RTX;
7559 frv_ifcvt.cur_scratch_regs = 0;
7563 /* A C expression to cancel any machine dependent modifications in converting
7564 code to conditional execution in the code described by the conditional if
7565 information CE_INFO. */
7568 frv_ifcvt_modify_cancel (ce_info)
7569 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7572 rtx p = frv_ifcvt.added_insns_list;
7574 /* Loop freeing up the EXPR_LIST's allocated. */
7575 while (p != NULL_RTX)
7577 rtx check_and_jump = XEXP (p, 0);
7581 free_EXPR_LIST_node (check_and_jump);
7582 free_EXPR_LIST_node (old_p);
7585 /* Release any temporary gprs allocated. */
7586 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7587 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7589 frv_ifcvt.added_insns_list = NULL_RTX;
7590 frv_ifcvt.cur_scratch_regs = 0;
7594 /* A C expression for the size in bytes of the trampoline, as an integer.
7598 setlo #0, <static_chain>
7600 sethi #0, <static_chain>
7601 jmpl @(gr0,<jmp_reg>) */
7604 frv_trampoline_size ()
7606 return 5 /* instructions */ * 4 /* instruction size */;
7610 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7611 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7612 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7613 should be passed to the function when it is called.
7618 setlo #0, <static_chain>
7620 sethi #0, <static_chain>
7621 jmpl @(gr0,<jmp_reg>) */
7624 frv_initialize_trampoline (addr, fnaddr, static_chain)
7629 rtx sc_reg = force_reg (Pmode, static_chain);
7631 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7634 GEN_INT (frv_trampoline_size ()), SImode,
7640 /* Many machines have some registers that cannot be copied directly to or from
7641 memory or even from other types of registers. An example is the `MQ'
7642 register, which on most machines, can only be copied to or from general
7643 registers, but not memory. Some machines allow copying all registers to and
7644 from memory, but require a scratch register for stores to some memory
7645 locations (e.g., those with symbolic address on the RT, and those with
7646 certain symbolic address on the SPARC when compiling PIC). In some cases,
7647 both an intermediate and a scratch register are required.
7649 You should define these macros to indicate to the reload phase that it may
7650 need to allocate at least one register for a reload in addition to the
7651 register to contain the data. Specifically, if copying X to a register
7652 CLASS in MODE requires an intermediate register, you should define
7653 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7654 whose registers can be used as intermediate registers or scratch registers.
7656 If copying a register CLASS in MODE to X requires an intermediate or scratch
7657 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7658 largest register class required. If the requirements for input and output
7659 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7660 instead of defining both macros identically.
7662 The values returned by these macros are often `GENERAL_REGS'. Return
7663 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7664 to or from a register of CLASS in MODE without requiring a scratch register.
7665 Do not define this macro if it would always return `NO_REGS'.
7667 If a scratch register is required (either with or without an intermediate
7668 register), you should define patterns for `reload_inM' or `reload_outM', as
7669 required.. These patterns, which will normally be implemented with a
7670 `define_expand', should be similar to the `movM' patterns, except that
7671 operand 2 is the scratch register.
7673 Define constraints for the reload register and scratch register that contain
7674 a single register class. If the original reload register (whose class is
7675 CLASS) can meet the constraint given in the pattern, the value returned by
7676 these macros is used for the class of the scratch register. Otherwise, two
7677 additional reload registers are required. Their classes are obtained from
7678 the constraints in the insn pattern.
7680 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7681 either be in a hard register or in memory. Use `true_regnum' to find out;
7682 it will return -1 if the pseudo is in memory and the hard register number if
7683 it is in a register.
7685 These macros should not be used in the case where a particular class of
7686 registers can only be copied to memory and not to another class of
7687 registers. In that case, secondary reload registers are not needed and
7688 would not be helpful. Instead, a stack location must be used to perform the
7689 copy and the `movM' pattern should use memory as an intermediate storage.
7690 This case often occurs between floating-point and general registers. */
7693 frv_secondary_reload_class (class, mode, x, in_p)
7694 enum reg_class class;
7695 enum machine_mode mode ATTRIBUTE_UNUSED;
7697 int in_p ATTRIBUTE_UNUSED;
7707 /* Accumulators/Accumulator guard registers need to go through floating
7713 if (x && GET_CODE (x) == REG)
7715 int regno = REGNO (x);
7717 if (ACC_P (regno) || ACCG_P (regno))
7722 /* Nonzero constants should be loaded into an FPR through a GPR. */
7726 if (x && CONSTANT_P (x) && !ZERO_P (x))
7732 /* All of these types need gpr registers. */
7744 /* The accumulators need fpr registers */
7757 /* A C expression whose value is nonzero if pseudos that have been assigned to
7758 registers of class CLASS would likely be spilled because registers of CLASS
7759 are needed for spill registers.
7761 The default value of this macro returns 1 if CLASS has exactly one register
7762 and zero otherwise. On most machines, this default should be used. Only
7763 define this macro to some other expression if pseudo allocated by
7764 `local-alloc.c' end up in memory because their hard registers were needed
7765 for spill registers. If this macro returns nonzero for those classes, those
7766 pseudos will only be allocated by `global.c', which knows how to reallocate
7767 the pseudo to another register. If there would not be another register
7768 available for reallocation, you should not change the definition of this
7769 macro since the only effect of such a definition would be to slow down
7770 register allocation. */
7773 frv_class_likely_spilled_p (class)
7774 enum reg_class class;
7801 /* An expression for the alignment of a structure field FIELD if the
7802 alignment computed in the usual way is COMPUTED. GNU CC uses this
7803 value instead of the value in `BIGGEST_ALIGNMENT' or
7804 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7806 /* The definition type of the bit field data is either char, short, long or
7807 long long. The maximum bit size is the number of bits of its own type.
7809 The bit field data is assigned to a storage unit that has an adequate size
7810 for bit field data retention and is located at the smallest address.
7812 Consecutive bit field data are packed at consecutive bits having the same
7813 storage unit, with regard to the type, beginning with the MSB and continuing
7816 If a field to be assigned lies over a bit field type boundary, its
7817 assignment is completed by aligning it with a boundary suitable for the
7820 When a bit field having a bit length of 0 is declared, it is forcibly
7821 assigned to the next storage unit.
7834 &x 00000000 00000000 00000000 00000000
7837 &x+4 00000000 00000000 00000000 00000000
7840 &x+8 00000000 00000000 00000000 00000000
7843 &x+12 00000000 00000000 00000000 00000000
7849 frv_adjust_field_align (field, computed)
7853 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7855 if (DECL_BIT_FIELD (field) && DECL_CONTEXT (field))
7857 tree parent = DECL_CONTEXT (field);
7858 tree prev = NULL_TREE;
7861 /* Loop finding the previous field to the current one */
7862 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7864 if (TREE_CODE (cur) != FIELD_DECL)
7873 /* If this isn't a :0 field and if the previous element is a bitfield
7874 also, see if the type is different, if so, we will need to align the
7875 bit-field to the next boundary */
7877 && ! DECL_PACKED (field)
7878 && ! integer_zerop (DECL_SIZE (field))
7879 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7881 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7882 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7883 computed = (prev_align > cur_align) ? prev_align : cur_align;
7891 /* A C expression that is nonzero if it is permissible to store a value of mode
7892 MODE in hard register number REGNO (or in several registers starting with
7893 that one). For a machine where all registers are equivalent, a suitable
7896 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7898 It is not necessary for this macro to check for the numbers of fixed
7899 registers, because the allocation mechanism considers them to be always
7902 On some machines, double-precision values must be kept in even/odd register
7903 pairs. The way to implement that is to define this macro to reject odd
7904 register numbers for such modes.
7906 The minimum requirement for a mode to be OK in a register is that the
7907 `movMODE' instruction pattern support moves between the register and any
7908 other hard register for which the mode is OK; and that moving a value into
7909 the register and back out not alter it.
7911 Since the same instruction used to move `SImode' will work for all narrower
7912 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7913 to distinguish between these modes, provided you define patterns `movhi',
7914 etc., to take advantage of this. This is useful because of the interaction
7915 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7916 all integer modes to be tieable.
7918 Many machines have special registers for floating point arithmetic. Often
7919 people assume that floating point machine modes are allowed only in floating
7920 point registers. This is not true. Any registers that can hold integers
7921 can safely *hold* a floating point machine mode, whether or not floating
7922 arithmetic can be done on it in those registers. Integer move instructions
7923 can be used to move the values.
7925 On some machines, though, the converse is true: fixed-point machine modes
7926 may not go in floating registers. This is true if the floating registers
7927 normalize any value stored in them, because storing a non-floating value
7928 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7929 fixed-point machine modes in floating registers. But if the floating
7930 registers do not automatically normalize, if you can store any bit pattern
7931 in one and retrieve it unchanged without a trap, then any machine mode may
7932 go in a floating register, so you can define this macro to say so.
7934 The primary significance of special floating registers is rather that they
7935 are the registers acceptable in floating point arithmetic instructions.
7936 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7937 writing the proper constraints for those instructions.
7939 On some machines, the floating registers are especially slow to access, so
7940 that it is better to store a value in a stack frame than in such a register
7941 if floating point arithmetic is not being done. As long as the floating
7942 registers are not in class `GENERAL_REGS', they will not be used unless some
7943 pattern's constraint asks for one. */
7946 frv_hard_regno_mode_ok (regno, mode)
7948 enum machine_mode mode;
7957 return ICC_P (regno) || GPR_P (regno);
7960 return CR_P (regno) || GPR_P (regno);
7963 return FCC_P (regno) || GPR_P (regno);
7969 /* Set BASE to the first register in REGNO's class. Set MASK to the
7970 bits that must be clear in (REGNO - BASE) for the register to be
7972 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7976 /* ACCGs store one byte. Two-byte quantities must start in
7977 even-numbered registers, four-byte ones in registers whose
7978 numbers are divisible by four, and so on. */
7980 mask = GET_MODE_SIZE (mode) - 1;
7984 /* The other registers store one word. */
7988 else if (FPR_P (regno))
7991 else if (ACC_P (regno))
7997 /* Anything smaller than an SI is OK in any word-sized register. */
7998 if (GET_MODE_SIZE (mode) < 4)
8001 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8003 return (((regno - base) & mask) == 0);
8010 /* A C expression for the number of consecutive hard registers, starting at
8011 register number REGNO, required to hold a value of mode MODE.
8013 On a machine where all registers are exactly one word, a suitable definition
8016 #define HARD_REGNO_NREGS(REGNO, MODE) \
8017 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8018 / UNITS_PER_WORD)) */
8020 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8021 that we can build the appropriate instructions to properly reload the
8022 values. Also, make the byte-sized accumulator guards use one guard
8026 frv_hard_regno_nregs (regno, mode)
8028 enum machine_mode mode;
8031 return GET_MODE_SIZE (mode);
8033 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8037 /* A C expression for the maximum number of consecutive registers of
8038 class CLASS needed to hold a value of mode MODE.
8040 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8041 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8042 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8044 This macro helps control the handling of multiple-word values in
8047 This declaration is required. */
8050 frv_class_max_nregs (class, mode)
8051 enum reg_class class;
8052 enum machine_mode mode;
8054 if (class == ACCG_REGS)
8055 /* An N-byte value requires N accumulator guards. */
8056 return GET_MODE_SIZE (mode);
8058 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8062 /* A C expression that is nonzero if X is a legitimate constant for an
8063 immediate operand on the target machine. You can assume that X satisfies
8064 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8065 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8068 frv_legitimate_constant_p (x)
8071 enum machine_mode mode = GET_MODE (x);
8073 /* All of the integer constants are ok */
8074 if (GET_CODE (x) != CONST_DOUBLE)
8077 /* double integer constants are ok */
8078 if (mode == VOIDmode || mode == DImode)
8081 /* 0 is always ok */
8082 if (x == CONST0_RTX (mode))
8085 /* If floating point is just emulated, allow any constant, since it will be
8086 constructed in the GPRs */
8087 if (!TARGET_HAS_FPRS)
8090 if (mode == DFmode && !TARGET_DOUBLE)
8093 /* Otherwise store the constant away and do a load. */
8097 /* A C expression for the cost of moving data from a register in class FROM to
8098 one in class TO. The classes are expressed using the enumeration values
8099 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8100 interpreted relative to that.
8102 It is not required that the cost always equal 2 when FROM is the same as TO;
8103 on some machines it is expensive to move between registers if they are not
8106 If reload sees an insn consisting of a single `set' between two hard
8107 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8108 value of 2, reload does not check to ensure that the constraints of the insn
8109 are met. Setting a cost of other than 2 will allow reload to verify that
8110 the constraints are met. You should do this if the `movM' pattern's
8111 constraints do not allow such copying. */
8113 #define HIGH_COST 40
8114 #define MEDIUM_COST 3
8118 frv_register_move_cost (from, to)
8119 enum reg_class from;
8204 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8205 use ".picptr" to generate safe relocations for PIC code. We also
8206 need a fixup entry for aligned (non-debugging) code. */
8209 frv_assemble_integer (value, size, aligned_p)
8214 if (flag_pic && size == UNITS_PER_WORD)
8216 if (GET_CODE (value) == CONST
8217 || GET_CODE (value) == SYMBOL_REF
8218 || GET_CODE (value) == LABEL_REF)
8222 static int label_num = 0;
8226 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8227 p = (* targetm.strip_name_encoding) (buf);
8229 fprintf (asm_out_file, "%s:\n", p);
8230 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8231 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8232 fprintf (asm_out_file, "\t.previous\n");
8234 assemble_integer_with_op ("\t.picptr\t", value);
8239 /* We've set the unaligned SI op to NULL, so we always have to
8240 handle the unaligned case here. */
8241 assemble_integer_with_op ("\t.4byte\t", value);
8245 return default_assemble_integer (value, size, aligned_p);
8248 /* Function to set up the backend function structure. */
8250 static struct machine_function *
8251 frv_init_machine_status ()
8253 return ggc_alloc_cleared (sizeof (struct machine_function));
8257 /* Update the register state information, to know about which registers are set
8261 frv_registers_update (x, reg_state, modified, p_num_mod, flag)
8263 unsigned char reg_state[];
8275 switch (GET_CODE (x))
8280 /* Clobber just modifies a register, it doesn't make it live. */
8282 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8283 flag | REGSTATE_MODIFIED);
8286 /* Pre modify updates the first argument, just references the second. */
8289 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8290 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8291 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8294 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8295 statement, but just to be sure, make sure it is the type of cond_exec
8299 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8300 && GET_CODE (XEXP (cond, 0)) == REG
8301 && CR_P (REGNO (XEXP (cond, 0)))
8302 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8303 && INTVAL (XEXP (cond, 1)) == 0
8304 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8306 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8307 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8308 | ((GET_CODE (cond) == NE)
8310 : REGSTATE_IF_FALSE));
8312 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8317 fatal_insn ("frv_registers_update", x);
8319 /* MEM resets the modification bits. */
8321 flag &= ~REGSTATE_MODIFIED;
8324 /* See if we need to set the modified flag. */
8326 reg = SUBREG_REG (x);
8327 if (GET_CODE (reg) == REG)
8329 regno = subreg_regno (x);
8330 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8337 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8341 if (flag & REGSTATE_MODIFIED)
8343 flag &= REGSTATE_MASK;
8344 while (regno < reg_max)
8346 int rs = reg_state[regno];
8350 if ((rs & REGSTATE_MODIFIED) == 0)
8352 modified[ *p_num_mod ] = regno;
8356 /* If the previous register state had the register as
8357 modified, possibly in some conditional execution context,
8358 and the current insn modifies in some other context, or
8359 outside of conditional execution, just mark the variable
8362 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8364 reg_state[regno] = (rs | flag);
8373 length = GET_RTX_LENGTH (GET_CODE (x));
8374 format = GET_RTX_FORMAT (GET_CODE (x));
8376 for (j = 0; j < length; ++j)
8381 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8387 if (XVEC (x, j) != 0)
8390 for (k = 0; k < XVECLEN (x, j); ++k)
8391 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8397 /* Nothing to do. */
8406 /* Return if any registers in a hard register set were used an insn. */
8409 frv_registers_used_p (x, reg_state, flag)
8411 unsigned char reg_state[];
8423 switch (GET_CODE (x))
8428 /* Skip clobber, that doesn't use the previous value */
8432 /* For SET, if a conditional jump has occurred in the same insn, only
8433 allow a set of a CR register if that register is not currently live.
8434 This is because on the FR-V, B0/B1 instructions are always last.
8435 Otherwise, don't look at the result, except within a MEM, but do look
8438 dest = SET_DEST (x);
8439 if (flag & REGSTATE_CONDJUMP
8440 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8441 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8444 if (GET_CODE (dest) == MEM)
8446 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8451 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8453 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8454 statement, but just to be sure, make sure it is the type of cond_exec
8458 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8459 && GET_CODE (XEXP (cond, 0)) == REG
8460 && CR_P (REGNO (XEXP (cond, 0)))
8461 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8462 && INTVAL (XEXP (cond, 1)) == 0
8463 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8465 result = frv_registers_used_p (cond, reg_state, flag);
8469 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8470 | ((GET_CODE (cond) == NE)
8472 : REGSTATE_IF_FALSE));
8474 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8477 fatal_insn ("frv_registers_used_p", x);
8479 /* See if a register or subreg was modified in the same VLIW insn. */
8481 reg = SUBREG_REG (x);
8482 if (GET_CODE (reg) == REG)
8484 regno = subreg_regno (x);
8485 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8492 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8496 while (regno < reg_max)
8498 int rs = reg_state[regno];
8500 if (rs & REGSTATE_MODIFIED)
8502 int rs_if = rs & REGSTATE_IF_EITHER;
8503 int flag_if = flag & REGSTATE_IF_EITHER;
8505 /* Simple modification, no conditional execution */
8506 if ((rs & REGSTATE_IF_EITHER) == 0)
8509 /* See if the variable is only modified in a conditional
8510 execution expression opposite to the conditional execution
8511 expression that governs this expression (ie, true vs. false
8512 for the same CC register). If this isn't two halves of the
8513 same conditional expression, consider the register
8515 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8516 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8517 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8529 length = GET_RTX_LENGTH (GET_CODE (x));
8530 format = GET_RTX_FORMAT (GET_CODE (x));
8532 for (j = 0; j < length; ++j)
8537 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8544 if (XVEC (x, j) != 0)
8547 for (k = 0; k < XVECLEN (x, j); ++k)
8549 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8558 /* Nothing to do. */
8566 /* Return if any registers in a hard register set were set in an insn. */
8569 frv_registers_set_p (x, reg_state, modify_p)
8571 unsigned char reg_state[];
8581 switch (GET_CODE (x))
8587 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8591 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8592 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8596 /* just to be sure, make sure it is the type of cond_exec we
8598 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8599 && GET_CODE (XEXP (cond, 0)) == REG
8600 && CR_P (REGNO (XEXP (cond, 0)))
8601 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8602 && INTVAL (XEXP (cond, 1)) == 0
8604 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8606 fatal_insn ("frv_registers_set_p", x);
8608 /* MEM resets the modification bits. */
8613 /* See if we need to set the modified modify_p. */
8615 reg = SUBREG_REG (x);
8616 if (GET_CODE (reg) == REG)
8618 regno = subreg_regno (x);
8619 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8626 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8631 while (regno < reg_max)
8633 int rs = reg_state[regno];
8635 if (rs & REGSTATE_MODIFIED)
8643 length = GET_RTX_LENGTH (GET_CODE (x));
8644 format = GET_RTX_FORMAT (GET_CODE (x));
8646 for (j = 0; j < length; ++j)
8651 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8657 if (XVEC (x, j) != 0)
8660 for (k = 0; k < XVECLEN (x, j); ++k)
8661 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8668 /* Nothing to do. */
8677 /* In rare cases, correct code generation requires extra machine dependent
8678 processing between the second jump optimization pass and delayed branch
8679 scheduling. On those machines, define this macro as a C statement to act on
8680 the code starting at INSN. */
8682 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8683 conditional branches/calls/jumps, etc. with previous insns where it can. It
8684 does not reorder the instructions. We assume the scheduler left the flow
8685 information in a reasonable state. */
8690 state_t frv_state; /* frv state machine */
8691 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8692 int next_start_vliw_p; /* next insn starts a VLIW insn */
8693 int cur_condjump_p; /* flag if current insn is a cond jump*/
8694 int next_condjump_p; /* flag if next insn is a cond jump */
8698 int num_mod = 0; /* # of modified registers */
8699 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8700 /* register state information */
8701 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8703 /* If we weren't going to pack the insns, don't bother with this pass. */
8704 if (!optimize || !flag_schedule_insns_after_reload || TARGET_NO_VLIW_BRANCH)
8707 switch (frv_cpu_type)
8710 case FRV_CPU_FR300: /* FR300/simple are single issue */
8711 case FRV_CPU_SIMPLE:
8714 case FRV_CPU_GENERIC: /* FR-V and FR500 are multi-issue */
8717 case FRV_CPU_TOMCAT:
8721 /* Set up the instruction and register states. */
8723 frv_state = (state_t) xmalloc (state_size ());
8724 memset ((PTR) reg_state, REGSTATE_DEAD, sizeof (reg_state));
8726 /* Go through the insns, and repack the insns. */
8727 state_reset (frv_state);
8728 cur_start_vliw_p = FALSE;
8729 next_start_vliw_p = TRUE;
8731 next_condjump_p = 0;
8733 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8735 enum rtx_code code = GET_CODE (insn);
8736 enum rtx_code pattern_code;
8738 /* For basic block begin notes redo the live information, and skip other
8742 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8746 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8747 reg_state[j] &= ~ REGSTATE_LIVE;
8749 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8750 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8752 reg_state[j] |= REGSTATE_LIVE;
8759 /* things like labels reset everything. */
8760 if (GET_RTX_CLASS (code) != 'i')
8762 next_start_vliw_p = TRUE;
8766 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8767 set on the USE insn that preceeds the return, and potentially on
8768 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8769 holding the case table labels. */
8770 pattern_code = GET_CODE (PATTERN (insn));
8771 if (pattern_code == USE || pattern_code == CLOBBER
8772 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8774 CLEAR_VLIW_START (insn);
8778 cur_start_vliw_p = next_start_vliw_p;
8779 next_start_vliw_p = FALSE;
8781 cur_condjump_p |= next_condjump_p;
8782 next_condjump_p = 0;
8784 /* Unconditional branches and calls end the current VLIW insn. */
8785 if (code == CALL_INSN)
8787 next_start_vliw_p = TRUE;
8789 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8790 if (frv_cpu_type == FRV_CPU_TOMCAT)
8791 cur_start_vliw_p = TRUE;
8793 else if (code == JUMP_INSN)
8795 if (any_condjump_p (insn))
8796 next_condjump_p = REGSTATE_CONDJUMP;
8798 next_start_vliw_p = TRUE;
8801 /* Only allow setting a CCR register after a conditional branch. */
8802 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8803 && get_attr_type (insn) != TYPE_CCR)
8804 cur_start_vliw_p = TRUE;
8806 /* Determine if we need to start a new VLIW instruction. */
8807 if (cur_start_vliw_p
8808 /* Do not check for register conflicts in a setlo instruction
8809 because any output or true dependencies will be with the
8810 partnering sethi instruction, with which it can be packed.
8812 Although output dependencies are rare they are still
8813 possible. So check output dependencies in VLIW insn. */
8814 || (get_attr_type (insn) != TYPE_SETLO
8815 && (frv_registers_used_p (PATTERN (insn),
8818 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8819 || state_transition (frv_state, insn) >= 0)
8821 SET_VLIW_START (insn);
8822 state_reset (frv_state);
8823 state_transition (frv_state, insn);
8826 /* Update the modified registers. */
8827 for (j = 0; j < num_mod; j++)
8828 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8829 | REGSTATE_IF_EITHER
8830 | REGSTATE_MODIFIED);
8835 CLEAR_VLIW_START (insn);
8837 /* Record which registers are modified. */
8838 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8840 /* Process the death notices */
8841 for (link = REG_NOTES (insn);
8843 link = XEXP (link, 1))
8845 rtx reg = XEXP (link, 0);
8847 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8849 int regno = REGNO (reg);
8850 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8851 for (; regno < n; regno++)
8852 reg_state[regno] &= ~REGSTATE_LIVE;
8857 free ((PTR) frv_state);
8863 #define def_builtin(name, type, code) \
8864 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8866 struct builtin_description
8868 enum insn_code icode;
8870 enum frv_builtins code;
8871 enum rtx_code comparison;
8875 /* Media intrinsics that take a single, constant argument. */
8877 static struct builtin_description bdesc_set[] =
8879 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8882 /* Media intrinsics that take just one argument. */
8884 static struct builtin_description bdesc_1arg[] =
8886 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8887 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8888 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8889 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8890 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8893 /* Media intrinsics that take two arguments. */
8895 static struct builtin_description bdesc_2arg[] =
8897 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8898 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8899 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8900 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8901 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8902 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8903 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8904 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8905 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8906 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8907 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8908 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8909 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8910 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8911 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8912 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8913 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8914 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8915 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8916 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8919 /* Media intrinsics that take two arguments, the first being an ACC number. */
8921 static struct builtin_description bdesc_cut[] =
8923 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8924 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8925 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8928 /* Two-argument media intrinsics with an immediate second argument. */
8930 static struct builtin_description bdesc_2argimm[] =
8932 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8933 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8934 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8935 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8936 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8937 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8938 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8939 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8940 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8941 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8942 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8943 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8944 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8945 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8946 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8949 /* Media intrinsics that take two arguments and return void, the first argument
8950 being a pointer to 4 words in memory. */
8952 static struct builtin_description bdesc_void2arg[] =
8954 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8955 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8958 /* Media intrinsics that take three arguments, the first being a const_int that
8959 denotes an accumulator, and that return void. */
8961 static struct builtin_description bdesc_void3arg[] =
8963 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8964 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8965 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8966 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8967 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8968 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8969 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8970 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8971 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8972 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8973 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8974 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8975 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8976 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8977 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8978 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8979 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8980 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8981 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8982 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8983 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8984 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8985 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8986 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8987 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8990 /* Media intrinsics that take two accumulator numbers as argument and
8993 static struct builtin_description bdesc_voidacc[] =
8995 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8996 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8997 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8998 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8999 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9000 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9003 /* Initialize media builtins. */
9006 frv_init_builtins ()
9008 tree endlink = void_list_node;
9009 tree accumulator = integer_type_node;
9010 tree integer = integer_type_node;
9011 tree voidt = void_type_node;
9012 tree uhalf = short_unsigned_type_node;
9013 tree sword1 = long_integer_type_node;
9014 tree uword1 = long_unsigned_type_node;
9015 tree sword2 = long_long_integer_type_node;
9016 tree uword2 = long_long_unsigned_type_node;
9017 tree uword4 = build_pointer_type (uword1);
9019 #define UNARY(RET, T1) \
9020 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9022 #define BINARY(RET, T1, T2) \
9023 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9024 tree_cons (NULL_TREE, T2, endlink)))
9026 #define TRINARY(RET, T1, T2, T3) \
9027 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9028 tree_cons (NULL_TREE, T2, \
9029 tree_cons (NULL_TREE, T3, endlink))))
9031 tree void_ftype_void = build_function_type (voidt, endlink);
9033 tree void_ftype_acc = UNARY (voidt, accumulator);
9034 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9035 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9036 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9037 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9038 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9039 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9040 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9041 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9043 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9044 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9045 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9046 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9047 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9048 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9049 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9050 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9051 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9052 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9053 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9055 tree sw1_ftype_int = UNARY (sword1, integer);
9056 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9057 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9059 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9060 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9061 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9062 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9063 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9065 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9067 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9068 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9069 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9070 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9071 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9072 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9073 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9074 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9075 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9076 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9077 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9078 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9079 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9080 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9081 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9082 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9083 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9084 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9085 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9086 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9087 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9088 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9089 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9090 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9091 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9092 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9093 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9094 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9095 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9096 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9097 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9098 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9099 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9100 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9101 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9102 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9103 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9104 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9105 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9106 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9107 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9108 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9109 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9110 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9111 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9112 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9113 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9114 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9115 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9116 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9117 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9118 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9119 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9120 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9121 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9122 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9123 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9124 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9125 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9126 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9127 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9128 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9129 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9130 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9131 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9132 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9133 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9134 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9135 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9136 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9137 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9138 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9139 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9140 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9141 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9142 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9143 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9144 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9145 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9146 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9147 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9148 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9149 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9150 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9157 /* Convert an integer constant to an accumulator register. ICODE is the
9158 code of the target instruction, OPNUM is the number of the
9159 accumulator operand and OPVAL is the constant integer. Try both
9160 ACC and ACCG registers; only report an error if neither fit the
9164 frv_int_to_acc (icode, opnum, opval)
9165 enum insn_code icode;
9171 if (GET_CODE (opval) != CONST_INT)
9173 error ("accumulator is not a constant integer");
9176 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9178 error ("accumulator number is out of bounds");
9182 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9183 ACC_FIRST + INTVAL (opval));
9184 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9185 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9187 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9189 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9195 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9198 static enum machine_mode
9199 frv_matching_accg_mode (mode)
9200 enum machine_mode mode;
9218 /* Return the accumulator guard that should be paired with accumulator
9219 register ACC. The mode of the returned register is in the same
9220 class as ACC, but is four times smaller. */
9223 frv_matching_accg_for_acc (acc)
9226 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9227 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9230 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9231 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9235 frv_read_argument (arglistptr)
9238 tree next = TREE_VALUE (*arglistptr);
9239 *arglistptr = TREE_CHAIN (*arglistptr);
9240 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9243 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9244 The instruction should require a constant operand of some sort. The
9245 function prints an error if OPVAL is not valid. */
9248 frv_check_constant_argument (icode, opnum, opval)
9249 enum insn_code icode;
9253 if (GET_CODE (opval) != CONST_INT)
9255 error ("`%s' expects a constant argument", insn_data[icode].name);
9258 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9260 error ("constant argument out of range for `%s'", insn_data[icode].name);
9266 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9267 if it's not null, has the right mode, and satisfies operand 0's
9271 frv_legitimize_target (icode, target)
9272 enum insn_code icode;
9275 enum machine_mode mode = insn_data[icode].operand[0].mode;
9278 || GET_MODE (target) != mode
9279 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9280 return gen_reg_rtx (mode);
9285 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9286 check whether ARG satisfies the operand's contraints. If it doesn't,
9287 copy ARG to a temporary register and return that. Otherwise return ARG
9291 frv_legitimize_argument (icode, opnum, arg)
9292 enum insn_code icode;
9296 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9298 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9301 return copy_to_mode_reg (mode, arg);
9304 /* Expand builtins that take a single, constant argument. At the moment,
9305 only MHDSETS falls into this category. */
9308 frv_expand_set_builtin (icode, arglist, target)
9309 enum insn_code icode;
9314 rtx op0 = frv_read_argument (&arglist);
9316 if (! frv_check_constant_argument (icode, 1, op0))
9319 target = frv_legitimize_target (icode, target);
9320 pat = GEN_FCN (icode) (target, op0);
9328 /* Expand builtins that take one operand. */
9331 frv_expand_unop_builtin (icode, arglist, target)
9332 enum insn_code icode;
9337 rtx op0 = frv_read_argument (&arglist);
9339 target = frv_legitimize_target (icode, target);
9340 op0 = frv_legitimize_argument (icode, 1, op0);
9341 pat = GEN_FCN (icode) (target, op0);
9349 /* Expand builtins that take two operands. */
9352 frv_expand_binop_builtin (icode, arglist, target)
9353 enum insn_code icode;
9358 rtx op0 = frv_read_argument (&arglist);
9359 rtx op1 = frv_read_argument (&arglist);
9361 target = frv_legitimize_target (icode, target);
9362 op0 = frv_legitimize_argument (icode, 1, op0);
9363 op1 = frv_legitimize_argument (icode, 2, op1);
9364 pat = GEN_FCN (icode) (target, op0, op1);
9372 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9376 frv_expand_cut_builtin (icode, arglist, target)
9377 enum insn_code icode;
9382 rtx op0 = frv_read_argument (&arglist);
9383 rtx op1 = frv_read_argument (&arglist);
9386 target = frv_legitimize_target (icode, target);
9387 op0 = frv_int_to_acc (icode, 1, op0);
9391 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9393 if (! frv_check_constant_argument (icode, 2, op1))
9397 op1 = frv_legitimize_argument (icode, 2, op1);
9399 op2 = frv_matching_accg_for_acc (op0);
9400 pat = GEN_FCN (icode) (target, op0, op1, op2);
9408 /* Expand builtins that take two operands and the second is immediate. */
9411 frv_expand_binopimm_builtin (icode, arglist, target)
9412 enum insn_code icode;
9417 rtx op0 = frv_read_argument (&arglist);
9418 rtx op1 = frv_read_argument (&arglist);
9420 if (! frv_check_constant_argument (icode, 2, op1))
9423 target = frv_legitimize_target (icode, target);
9424 op0 = frv_legitimize_argument (icode, 1, op0);
9425 pat = GEN_FCN (icode) (target, op0, op1);
9433 /* Expand builtins that take two operands, the first operand being a pointer to
9434 ints and return void. */
9437 frv_expand_voidbinop_builtin (icode, arglist)
9438 enum insn_code icode;
9442 rtx op0 = frv_read_argument (&arglist);
9443 rtx op1 = frv_read_argument (&arglist);
9444 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9447 if (GET_CODE (op0) != MEM)
9451 if (! offsettable_address_p (0, mode0, op0))
9453 reg = gen_reg_rtx (Pmode);
9454 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9457 op0 = gen_rtx_MEM (SImode, reg);
9460 addr = XEXP (op0, 0);
9461 if (! offsettable_address_p (0, mode0, addr))
9462 addr = copy_to_mode_reg (Pmode, op0);
9464 op0 = change_address (op0, V4SImode, addr);
9465 op1 = frv_legitimize_argument (icode, 1, op1);
9466 pat = GEN_FCN (icode) (op0, op1);
9474 /* Expand builtins that take three operands and return void. The first
9475 argument must be a constant that describes a pair or quad accumulators. A
9476 fourth argument is created that is the accumulator guard register that
9477 corresponds to the accumulator. */
9480 frv_expand_voidtriop_builtin (icode, arglist)
9481 enum insn_code icode;
9485 rtx op0 = frv_read_argument (&arglist);
9486 rtx op1 = frv_read_argument (&arglist);
9487 rtx op2 = frv_read_argument (&arglist);
9490 op0 = frv_int_to_acc (icode, 0, op0);
9494 op1 = frv_legitimize_argument (icode, 1, op1);
9495 op2 = frv_legitimize_argument (icode, 2, op2);
9496 op3 = frv_matching_accg_for_acc (op0);
9497 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9505 /* Expand builtins that perform accumulator-to-accumulator operations.
9506 These builtins take two accumulator numbers as argument and return
9510 frv_expand_voidaccop_builtin (icode, arglist)
9511 enum insn_code icode;
9515 rtx op0 = frv_read_argument (&arglist);
9516 rtx op1 = frv_read_argument (&arglist);
9520 op0 = frv_int_to_acc (icode, 0, op0);
9524 op1 = frv_int_to_acc (icode, 1, op1);
9528 op2 = frv_matching_accg_for_acc (op0);
9529 op3 = frv_matching_accg_for_acc (op1);
9530 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9538 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9539 number as argument. */
9542 frv_expand_mclracc_builtin (arglist)
9545 enum insn_code icode = CODE_FOR_mclracc;
9547 rtx op0 = frv_read_argument (&arglist);
9549 op0 = frv_int_to_acc (icode, 0, op0);
9553 pat = GEN_FCN (icode) (op0);
9560 /* Expand builtins that take no arguments. */
9563 frv_expand_noargs_builtin (icode)
9564 enum insn_code icode;
9566 rtx pat = GEN_FCN (icode) (GEN_INT (0));
9573 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9574 number or accumulator guard number as argument and return an SI integer. */
9577 frv_expand_mrdacc_builtin (icode, arglist)
9578 enum insn_code icode;
9582 rtx target = gen_reg_rtx (SImode);
9583 rtx op0 = frv_read_argument (&arglist);
9585 op0 = frv_int_to_acc (icode, 1, op0);
9589 pat = GEN_FCN (icode) (target, op0);
9597 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9598 accumulator guard as their first argument and an SImode value as their
9602 frv_expand_mwtacc_builtin (icode, arglist)
9603 enum insn_code icode;
9607 rtx op0 = frv_read_argument (&arglist);
9608 rtx op1 = frv_read_argument (&arglist);
9610 op0 = frv_int_to_acc (icode, 0, op0);
9614 op1 = frv_legitimize_argument (icode, 1, op1);
9615 pat = GEN_FCN (icode) (op0, op1);
9622 /* Expand builtins. */
9625 frv_expand_builtin (exp, target, subtarget, mode, ignore)
9628 rtx subtarget ATTRIBUTE_UNUSED;
9629 enum machine_mode mode ATTRIBUTE_UNUSED;
9630 int ignore ATTRIBUTE_UNUSED;
9632 tree arglist = TREE_OPERAND (exp, 1);
9633 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9634 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9636 struct builtin_description *d;
9640 error ("media functions are not available unless -mmedia is used");
9646 case FRV_BUILTIN_MCOP1:
9647 case FRV_BUILTIN_MCOP2:
9648 case FRV_BUILTIN_MDUNPACKH:
9649 case FRV_BUILTIN_MBTOHE:
9650 if (! TARGET_MEDIA_REV1)
9652 error ("this media function is only available on the fr500");
9657 case FRV_BUILTIN_MQXMACHS:
9658 case FRV_BUILTIN_MQXMACXHS:
9659 case FRV_BUILTIN_MQMACXHS:
9660 case FRV_BUILTIN_MADDACCS:
9661 case FRV_BUILTIN_MSUBACCS:
9662 case FRV_BUILTIN_MASACCS:
9663 case FRV_BUILTIN_MDADDACCS:
9664 case FRV_BUILTIN_MDSUBACCS:
9665 case FRV_BUILTIN_MDASACCS:
9666 case FRV_BUILTIN_MABSHS:
9667 case FRV_BUILTIN_MDROTLI:
9668 case FRV_BUILTIN_MCPLHI:
9669 case FRV_BUILTIN_MCPLI:
9670 case FRV_BUILTIN_MDCUTSSI:
9671 case FRV_BUILTIN_MQSATHS:
9672 case FRV_BUILTIN_MHSETLOS:
9673 case FRV_BUILTIN_MHSETLOH:
9674 case FRV_BUILTIN_MHSETHIS:
9675 case FRV_BUILTIN_MHSETHIH:
9676 case FRV_BUILTIN_MHDSETS:
9677 case FRV_BUILTIN_MHDSETH:
9678 if (! TARGET_MEDIA_REV2)
9680 error ("this media function is only available on the fr400");
9689 /* Expand unique builtins. */
9693 case FRV_BUILTIN_MTRAP:
9694 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9696 case FRV_BUILTIN_MCLRACC:
9697 return frv_expand_mclracc_builtin (arglist);
9699 case FRV_BUILTIN_MCLRACCA:
9701 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9703 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9705 case FRV_BUILTIN_MRDACC:
9706 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9708 case FRV_BUILTIN_MRDACCG:
9709 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9711 case FRV_BUILTIN_MWTACC:
9712 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9714 case FRV_BUILTIN_MWTACCG:
9715 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9721 /* Expand groups of builtins. */
9723 for (i = 0, d = bdesc_set; i < sizeof (bdesc_set) / sizeof *d; i++, d++)
9724 if (d->code == fcode)
9725 return frv_expand_set_builtin (d->icode, arglist, target);
9727 for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++)
9728 if (d->code == fcode)
9729 return frv_expand_unop_builtin (d->icode, arglist, target);
9731 for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
9732 if (d->code == fcode)
9733 return frv_expand_binop_builtin (d->icode, arglist, target);
9735 for (i = 0, d = bdesc_cut; i < sizeof (bdesc_cut) / sizeof *d; i++, d++)
9736 if (d->code == fcode)
9737 return frv_expand_cut_builtin (d->icode, arglist, target);
9739 for (i = 0, d = bdesc_2argimm;
9740 i < sizeof (bdesc_2argimm) / sizeof *d;
9743 if (d->code == fcode)
9744 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9747 for (i = 0, d = bdesc_void2arg;
9748 i < sizeof (bdesc_void2arg) / sizeof *d;
9751 if (d->code == fcode)
9752 return frv_expand_voidbinop_builtin (d->icode, arglist);
9755 for (i = 0, d = bdesc_void3arg;
9756 i < sizeof (bdesc_void3arg) / sizeof *d;
9759 if (d->code == fcode)
9760 return frv_expand_voidtriop_builtin (d->icode, arglist);
9763 for (i = 0, d = bdesc_voidacc;
9764 i < sizeof (bdesc_voidacc) / sizeof *d;
9767 if (d->code == fcode)
9768 return frv_expand_voidaccop_builtin (d->icode, arglist);
9774 frv_strip_name_encoding (str)
9777 while (*str == '*' || *str == SDATA_FLAG_CHAR)
9783 frv_in_small_data_p (decl)
9786 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
9788 return symbol_ref_small_data_p (XEXP (DECL_RTL (decl), 0))
9789 && size > 0 && size <= g_switch_value;