1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* Information about a relocation unspec. SYMBOL is the relocation symbol
60 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
61 is the constant addend. */
68 /* Temporary register allocation support structure. */
69 typedef struct frv_tmp_reg_struct
71 HARD_REG_SET regs; /* possible registers to allocate */
72 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
76 /* Register state information for VLIW re-packing phase. These values must fit
77 within an unsigned char. */
78 #define REGSTATE_DEAD 0x00 /* register is currently dead */
79 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
80 #define REGSTATE_LIVE 0x08 /* register is live */
81 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
82 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
83 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
84 #define REGSTATE_UNUSED 0x80 /* bit for hire */
85 #define REGSTATE_MASK 0xff /* mask for the bits to set */
87 /* conditional expression used */
88 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
90 /* The following is not sure in the reg_state bytes, so can have a larger value
92 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
94 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
102 /* Information required by frv_frame_access. */
105 /* This field is FRV_LOAD if registers are to be loaded from the stack and
106 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
107 the move is being done by the prologue code while FRV_LOAD implies it
108 is being done by the epilogue. */
109 enum frv_stack_op op;
111 /* The base register to use when accessing the stack. This may be the
112 frame pointer, stack pointer, or a temporary. The choice of register
113 depends on which part of the frame is being accessed and how big the
117 /* The offset of BASE from the bottom of the current frame, in bytes. */
119 } frv_frame_accessor_t;
121 /* Define the information needed to generate branch and scc insns. This is
122 stored from the compare operation. */
126 /* Conditional execution support gathered together in one structure. */
129 /* Linked list of insns to add if the conditional execution conversion was
130 successful. Each link points to an EXPR_LIST which points to the pattern
131 of the insn to add, and the insn to be inserted before. */
132 rtx added_insns_list;
134 /* Identify which registers are safe to allocate for if conversions to
135 conditional execution. We keep the last allocated register in the
136 register classes between COND_EXEC statements. This will mean we allocate
137 different registers for each different COND_EXEC group if we can. This
138 might allow the scheduler to intermix two different COND_EXEC sections. */
139 frv_tmp_reg_t tmp_reg;
141 /* For nested IFs, identify which CC registers are used outside of setting
142 via a compare isnsn, and using via a check insn. This will allow us to
143 know if we can rewrite the register to use a different register that will
144 be paired with the CR register controlling the nested IF-THEN blocks. */
145 HARD_REG_SET nested_cc_ok_rewrite;
147 /* Temporary registers allocated to hold constants during conditional
149 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
151 /* Current number of temp registers available. */
152 int cur_scratch_regs;
154 /* Number of nested conditional execution blocks. */
155 int num_nested_cond_exec;
157 /* Map of insns that set up constants in scratch registers. */
158 bitmap scratch_insns_bitmap;
160 /* Conditional execution test register (CC0..CC7). */
163 /* Conditional execution compare register that is paired with cr_reg, so that
164 nested compares can be done. The csubcc and caddcc instructions don't
165 have enough bits to specify both a CC register to be set and a CR register
166 to do the test on, so the same bit number is used for both. Needless to
167 say, this is rather inconvenient for GCC. */
170 /* Extra CR registers used for &&, ||. */
174 /* Previous CR used in nested if, to make sure we are dealing with the same
175 nested if as the previous statement. */
176 rtx last_nested_if_cr;
180 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
182 /* Map register number to smallest register class. */
183 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
185 /* Map class letter into register class. */
186 enum reg_class reg_class_from_letter[256];
188 /* Cached value of frv_stack_info. */
189 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
191 /* -mbranch-cost= support */
192 const char *frv_branch_cost_string;
193 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
196 const char *frv_cpu_string; /* -mcpu= option */
197 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
199 /* -mcond-exec-insns= support */
200 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
201 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
203 /* -mcond-exec-temps= support */
204 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
205 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
207 /* -msched-lookahead=n */
208 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
209 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
211 /* Forward references */
212 static int frv_default_flags_for_cpu (void);
213 static int frv_string_begins_with (tree, const char *);
214 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
215 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
216 static void frv_print_operand_memory_reference_reg
218 static void frv_print_operand_memory_reference (FILE *, rtx, int);
219 static int frv_print_operand_jump_hint (rtx);
220 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
221 static rtx single_set_pattern (rtx);
222 static int frv_function_contains_far_jump (void);
223 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
227 static rtx frv_frame_offset_rtx (int);
228 static rtx frv_frame_mem (enum machine_mode, rtx, int);
229 static rtx frv_dwarf_store (rtx, int);
230 static void frv_frame_insn (rtx, rtx);
231 static void frv_frame_access (frv_frame_accessor_t*,
233 static void frv_frame_access_multi (frv_frame_accessor_t*,
235 static void frv_frame_access_standard_regs (enum frv_stack_op,
237 static struct machine_function *frv_init_machine_status (void);
238 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
239 static rtx frv_int_to_acc (enum insn_code, int, rtx);
240 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
241 static rtx frv_read_argument (tree *);
242 static int frv_check_constant_argument (enum insn_code, int, rtx);
243 static rtx frv_legitimize_target (enum insn_code, rtx);
244 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
245 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
246 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
247 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
248 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
249 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
250 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
251 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
252 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
253 static rtx frv_expand_mclracc_builtin (tree);
254 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
255 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
256 static rtx frv_expand_noargs_builtin (enum insn_code);
257 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
258 static int frv_clear_registers_used (rtx *, void *);
259 static void frv_ifcvt_add_insn (rtx, rtx, int);
260 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
261 static rtx frv_ifcvt_load_value (rtx, rtx);
262 static void frv_registers_update (rtx, unsigned char [],
264 static int frv_registers_used_p (rtx, unsigned char [], int);
265 static int frv_registers_set_p (rtx, unsigned char [], int);
266 static int frv_issue_rate (void);
267 static void frv_pack_insns (void);
268 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
269 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
270 static bool frv_assemble_integer (rtx, unsigned, int);
271 static void frv_init_builtins (void);
272 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
273 static void frv_init_libfuncs (void);
274 static bool frv_in_small_data_p (tree);
275 static void frv_asm_output_mi_thunk
276 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
277 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
280 static rtx frv_expand_builtin_saveregs (void);
281 static bool frv_rtx_costs (rtx, int, int, int*);
282 static void frv_asm_out_constructor (rtx, int);
283 static void frv_asm_out_destructor (rtx, int);
284 static bool frv_function_symbol_referenced_p (rtx);
285 static bool frv_cannot_force_const_mem (rtx);
286 static const char *unspec_got_name (int);
287 static void frv_output_const_unspec (FILE *,
288 const struct frv_unspec *);
289 static bool frv_function_ok_for_sibcall (tree, tree);
290 static rtx frv_struct_value_rtx (tree, int);
291 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
293 /* Initialize the GCC target structure. */
294 #undef TARGET_ASM_FUNCTION_PROLOGUE
295 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
296 #undef TARGET_ASM_FUNCTION_EPILOGUE
297 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
298 #undef TARGET_ASM_INTEGER
299 #define TARGET_ASM_INTEGER frv_assemble_integer
300 #undef TARGET_INIT_BUILTINS
301 #define TARGET_INIT_BUILTINS frv_init_builtins
302 #undef TARGET_EXPAND_BUILTIN
303 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
304 #undef TARGET_INIT_LIBFUNCS
305 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
306 #undef TARGET_IN_SMALL_DATA_P
307 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
308 #undef TARGET_RTX_COSTS
309 #define TARGET_RTX_COSTS frv_rtx_costs
310 #undef TARGET_ASM_CONSTRUCTOR
311 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
312 #undef TARGET_ASM_DESTRUCTOR
313 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
315 #undef TARGET_ASM_OUTPUT_MI_THUNK
316 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
317 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
318 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
320 #undef TARGET_SCHED_ISSUE_RATE
321 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
323 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
324 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
325 #undef TARGET_CANNOT_FORCE_CONST_MEM
326 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
328 #undef TARGET_STRUCT_VALUE_RTX
329 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
330 #undef TARGET_MUST_PASS_IN_STACK
331 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
332 #undef TARGET_PASS_BY_REFERENCE
333 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
335 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
336 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
337 #undef TARGET_SETUP_INCOMING_VARARGS
338 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
340 struct gcc_target targetm = TARGET_INITIALIZER;
342 /* Any function call that satisfies the machine-independent
343 requirements is eligible on FR-V. */
346 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
347 tree exp ATTRIBUTE_UNUSED)
352 /* Return true if SYMBOL is a small data symbol and relocation RELOC
353 can be used to access it directly in a load or store. */
355 static FRV_INLINE bool
356 frv_small_data_reloc_p (rtx symbol, int reloc)
358 return (GET_CODE (symbol) == SYMBOL_REF
359 && SYMBOL_REF_SMALL_P (symbol)
360 && (!TARGET_FDPIC || flag_pic == 1)
361 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
364 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
367 static FRV_INLINE bool
368 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
370 if (GET_CODE (x) == CONST)
374 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
376 unspec->offset += INTVAL (XEXP (x, 1));
379 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
381 unspec->symbol = XVECEXP (x, 0, 0);
382 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
384 if (unspec->offset == 0)
387 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
388 && unspec->offset > 0
389 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
396 /* Decide whether we can force certain constants to memory. If we
397 decide we can't, the caller should be able to cope with it in
400 We never allow constants to be forced into memory for TARGET_FDPIC.
401 This is necessary for several reasons:
403 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
404 target-independent code will try to force them into the constant
405 pool, thus leading to infinite recursion.
407 2. We can never introduce new constant pool references during reload.
408 Any such reference would require use of the pseudo FDPIC register.
410 3. We can't represent a constant added to a function pointer (which is
411 not the same as a pointer to a function+constant).
413 4. In many cases, it's more efficient to calculate the constant in-line. */
416 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
422 frv_default_flags_for_cpu (void)
424 switch (frv_cpu_type)
426 case FRV_CPU_GENERIC:
427 return MASK_DEFAULT_FRV;
431 return MASK_DEFAULT_FR500;
434 return MASK_DEFAULT_FR400;
438 return MASK_DEFAULT_SIMPLE;
443 /* Sometimes certain combinations of command options do not make
444 sense on a particular target machine. You can define a macro
445 `OVERRIDE_OPTIONS' to take account of this. This macro, if
446 defined, is executed once just after all the command options have
449 Don't use this macro to turn on various extra optimizations for
450 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
453 frv_override_options (void)
457 /* Set the cpu type. */
460 if (strcmp (frv_cpu_string, "simple") == 0)
461 frv_cpu_type = FRV_CPU_SIMPLE;
463 else if (strcmp (frv_cpu_string, "tomcat") == 0)
464 frv_cpu_type = FRV_CPU_TOMCAT;
466 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
467 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
471 const char *p = frv_cpu_string + sizeof ("fr") - 1;
472 if (strcmp (p, "500") == 0)
473 frv_cpu_type = FRV_CPU_FR500;
475 else if (strcmp (p, "400") == 0)
476 frv_cpu_type = FRV_CPU_FR400;
478 else if (strcmp (p, "300") == 0)
479 frv_cpu_type = FRV_CPU_FR300;
481 else if (strcmp (p, "v") == 0)
482 frv_cpu_type = FRV_CPU_GENERIC;
485 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
489 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
491 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
492 linker about linking pic and non-pic code. */
495 if (!flag_pic) /* -fPIC */
498 if (! g_switch_set) /* -G0 */
505 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
507 if (write_symbols == DWARF_DEBUG && flag_pic)
508 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
510 /* Change the branch cost value. */
511 if (frv_branch_cost_string)
512 frv_branch_cost_int = atoi (frv_branch_cost_string);
514 /* Change the # of insns to be converted to conditional execution. */
515 if (frv_condexec_insns_str)
516 frv_condexec_insns = atoi (frv_condexec_insns_str);
518 /* Change # of temporary registers used to hold integer constants. */
519 if (frv_condexec_temps_str)
520 frv_condexec_temps = atoi (frv_condexec_temps_str);
522 /* Change scheduling look ahead. */
523 if (frv_sched_lookahead_str)
524 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
526 /* A C expression whose value is a register class containing hard
527 register REGNO. In general there is more than one such class;
528 choose a class which is "minimal", meaning that no smaller class
529 also contains the register. */
531 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
533 enum reg_class class;
537 int gpr_reg = regno - GPR_FIRST;
538 if ((gpr_reg & 3) == 0)
541 else if ((gpr_reg & 1) == 0)
548 else if (FPR_P (regno))
550 int fpr_reg = regno - GPR_FIRST;
551 if ((fpr_reg & 3) == 0)
552 class = QUAD_FPR_REGS;
554 else if ((fpr_reg & 1) == 0)
561 else if (regno == LR_REGNO)
564 else if (regno == LCR_REGNO)
567 else if (ICC_P (regno))
570 else if (FCC_P (regno))
573 else if (ICR_P (regno))
576 else if (FCR_P (regno))
579 else if (ACC_P (regno))
581 int r = regno - ACC_FIRST;
583 class = QUAD_ACC_REGS;
584 else if ((r & 1) == 0)
585 class = EVEN_ACC_REGS;
590 else if (ACCG_P (regno))
596 regno_reg_class[regno] = class;
599 /* Check for small data option */
601 g_switch_value = SDATA_DEFAULT_SIZE;
603 /* A C expression which defines the machine-dependent operand
604 constraint letters for register classes. If CHAR is such a
605 letter, the value should be the register class corresponding to
606 it. Otherwise, the value should be `NO_REGS'. The register
607 letter `r', corresponding to class `GENERAL_REGS', will not be
608 passed to this macro; you do not need to handle it.
610 The following letters are unavailable, due to being used as
615 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
616 'Q', 'R', 'S', 'T', 'U'
618 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
620 for (i = 0; i < 256; i++)
621 reg_class_from_letter[i] = NO_REGS;
623 reg_class_from_letter['a'] = ACC_REGS;
624 reg_class_from_letter['b'] = EVEN_ACC_REGS;
625 reg_class_from_letter['c'] = CC_REGS;
626 reg_class_from_letter['d'] = GPR_REGS;
627 reg_class_from_letter['e'] = EVEN_REGS;
628 reg_class_from_letter['f'] = FPR_REGS;
629 reg_class_from_letter['h'] = FEVEN_REGS;
630 reg_class_from_letter['l'] = LR_REG;
631 reg_class_from_letter['q'] = QUAD_REGS;
632 reg_class_from_letter['t'] = ICC_REGS;
633 reg_class_from_letter['u'] = FCC_REGS;
634 reg_class_from_letter['v'] = ICR_REGS;
635 reg_class_from_letter['w'] = FCR_REGS;
636 reg_class_from_letter['x'] = QUAD_FPR_REGS;
637 reg_class_from_letter['y'] = LCR_REG;
638 reg_class_from_letter['z'] = SPR_REGS;
639 reg_class_from_letter['A'] = QUAD_ACC_REGS;
640 reg_class_from_letter['B'] = ACCG_REGS;
641 reg_class_from_letter['C'] = CR_REGS;
642 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
643 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
645 /* There is no single unaligned SI op for PIC code. Sometimes we
646 need to use ".4byte" and sometimes we need to use ".picptr".
647 See frv_assemble_integer for details. */
648 if (flag_pic || TARGET_FDPIC)
649 targetm.asm_out.unaligned_op.si = 0;
651 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
652 target_flags |= MASK_LINKED_FP;
654 init_machine_status = frv_init_machine_status;
658 /* Some machines may desire to change what optimizations are performed for
659 various optimization levels. This macro, if defined, is executed once just
660 after the optimization level is determined and before the remainder of the
661 command options have been parsed. Values set in this macro are used as the
662 default values for the other command line options.
664 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
665 `-O' is specified, and 0 if neither is specified.
667 SIZE is nonzero if `-Os' is specified, 0 otherwise.
669 You should not use this macro to change options that are not
670 machine-specific. These should uniformly selected by the same optimization
671 level on all supported machines. Use this macro to enable machbine-specific
674 *Do not examine `write_symbols' in this macro!* The debugging options are
675 *not supposed to alter the generated code. */
677 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
678 scheduling pass at the current time. */
680 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
684 #ifdef DISABLE_SCHED2
685 flag_schedule_insns_after_reload = 0;
694 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
697 frv_string_begins_with (tree name, const char *prefix)
699 int prefix_len = strlen (prefix);
701 /* Remember: NAME's length includes the null terminator. */
702 return (TREE_STRING_LENGTH (name) > prefix_len
703 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
706 /* Zero or more C statements that may conditionally modify two variables
707 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
708 been initialized from the two preceding macros.
710 This is necessary in case the fixed or call-clobbered registers depend on
713 You need not define this macro if it has no work to do.
715 If the usage of an entire class of registers depends on the target flags,
716 you may indicate this to GCC by using this macro to modify `fixed_regs' and
717 `call_used_regs' to 1 for each of the registers in the classes which should
718 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
719 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
721 (However, if this class is not included in `GENERAL_REGS' and all of the
722 insn patterns whose constraints permit this class are controlled by target
723 switches, then GCC will automatically avoid using these registers when the
724 target switches are opposed to them.) */
727 frv_conditional_register_usage (void)
731 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
732 fixed_regs[i] = call_used_regs[i] = 1;
734 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
735 fixed_regs[i] = call_used_regs[i] = 1;
737 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
738 fixed_regs[i] = call_used_regs[i] = 1;
740 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
741 fixed_regs[i] = call_used_regs[i] = 1;
743 /* Reserve the registers used for conditional execution. At present, we need
744 1 ICC and 1 ICR register. */
745 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
746 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
750 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
751 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
752 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
753 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
757 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
758 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
761 /* If -fpic, SDA_BASE_REG is the PIC register. */
762 if (g_switch_value == 0 && !flag_pic)
763 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
766 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
772 * Compute the stack frame layout
775 * +---------------+-----------------------+-----------------------+
776 * |Register |type |caller-save/callee-save|
777 * +---------------+-----------------------+-----------------------+
778 * |GR0 |Zero register | - |
779 * |GR1 |Stack pointer(SP) | - |
780 * |GR2 |Frame pointer(FP) | - |
781 * |GR3 |Hidden parameter | caller save |
782 * |GR4-GR7 | - | caller save |
783 * |GR8-GR13 |Argument register | caller save |
784 * |GR14-GR15 | - | caller save |
785 * |GR16-GR31 | - | callee save |
786 * |GR32-GR47 | - | caller save |
787 * |GR48-GR63 | - | callee save |
788 * |FR0-FR15 | - | caller save |
789 * |FR16-FR31 | - | callee save |
790 * |FR32-FR47 | - | caller save |
791 * |FR48-FR63 | - | callee save |
792 * +---------------+-----------------------+-----------------------+
796 * SP-> |-----------------------------------|
798 * |-----------------------------------|
799 * | Register save area |
800 * |-----------------------------------|
801 * | Local variable save area |
802 * FP-> |-----------------------------------|
804 * |-----------------------------------|
805 * | Hidden parameter save area |
806 * |-----------------------------------|
807 * | Return address(LR) storage area |
808 * |-----------------------------------|
809 * | Padding for alignment |
810 * |-----------------------------------|
811 * | Register argument area |
812 * OLD SP-> |-----------------------------------|
814 * |-----------------------------------|
817 * Argument area/Parameter area:
819 * When a function is called, this area is used for argument transfer. When
820 * the argument is set up by the caller function, this area is referred to as
821 * the argument area. When the argument is referenced by the callee function,
822 * this area is referred to as the parameter area. The area is allocated when
823 * all arguments cannot be placed on the argument register at the time of
826 * Register save area:
828 * This is a register save area that must be guaranteed for the caller
829 * function. This area is not secured when the register save operation is not
832 * Local variable save area:
834 * This is the area for local variables and temporary variables.
838 * This area stores the FP value of the caller function.
840 * Hidden parameter save area:
842 * This area stores the start address of the return value storage
843 * area for a struct/union return function.
844 * When a struct/union is used as the return value, the caller
845 * function stores the return value storage area start address in
846 * register GR3 and passes it to the caller function.
847 * The callee function interprets the address stored in the GR3
848 * as the return value storage area start address.
849 * When register GR3 needs to be saved into memory, the callee
850 * function saves it in the hidden parameter save area. This
851 * area is not secured when the save operation is not needed.
853 * Return address(LR) storage area:
855 * This area saves the LR. The LR stores the address of a return to the caller
856 * function for the purpose of function calling.
858 * Argument register area:
860 * This area saves the argument register. This area is not secured when the
861 * save operation is not needed.
865 * Arguments, the count of which equals the count of argument registers (6
866 * words), are positioned in registers GR8 to GR13 and delivered to the callee
867 * function. When a struct/union return function is called, the return value
868 * area address is stored in register GR3. Arguments not placed in the
869 * argument registers will be stored in the stack argument area for transfer
870 * purposes. When an 8-byte type argument is to be delivered using registers,
871 * it is divided into two and placed in two registers for transfer. When
872 * argument registers must be saved to memory, the callee function secures an
873 * argument register save area in the stack. In this case, a continuous
874 * argument register save area must be established in the parameter area. The
875 * argument register save area must be allocated as needed to cover the size of
876 * the argument register to be saved. If the function has a variable count of
877 * arguments, it saves all argument registers in the argument register save
880 * Argument Extension Format:
882 * When an argument is to be stored in the stack, its type is converted to an
883 * extended type in accordance with the individual argument type. The argument
884 * is freed by the caller function after the return from the callee function is
887 * +-----------------------+---------------+------------------------+
888 * | Argument Type |Extended Type |Stack Storage Size(byte)|
889 * +-----------------------+---------------+------------------------+
891 * |signed char |int | 4 |
892 * |unsigned char |int | 4 |
893 * |[signed] short int |int | 4 |
894 * |unsigned short int |int | 4 |
895 * |[signed] int |No extension | 4 |
896 * |unsigned int |No extension | 4 |
897 * |[signed] long int |No extension | 4 |
898 * |unsigned long int |No extension | 4 |
899 * |[signed] long long int |No extension | 8 |
900 * |unsigned long long int |No extension | 8 |
901 * |float |double | 8 |
902 * |double |No extension | 8 |
903 * |long double |No extension | 8 |
904 * |pointer |No extension | 4 |
905 * |struct/union |- | 4 (*1) |
906 * +-----------------------+---------------+------------------------+
908 * When a struct/union is to be delivered as an argument, the caller copies it
909 * to the local variable area and delivers the address of that area.
913 * +-------------------------------+----------------------+
914 * |Return Value Type |Return Value Interface|
915 * +-------------------------------+----------------------+
917 * |[signed|unsigned] char |GR8 |
918 * |[signed|unsigned] short int |GR8 |
919 * |[signed|unsigned] int |GR8 |
920 * |[signed|unsigned] long int |GR8 |
922 * |[signed|unsigned] long long int|GR8 & GR9 |
924 * |double |GR8 & GR9 |
925 * |long double |GR8 & GR9 |
926 * |struct/union |(*1) |
927 * +-------------------------------+----------------------+
929 * When a struct/union is used as the return value, the caller function stores
930 * the start address of the return value storage area into GR3 and then passes
931 * it to the callee function. The callee function interprets GR3 as the start
932 * address of the return value storage area. When this address needs to be
933 * saved in memory, the callee function secures the hidden parameter save area
934 * and saves the address in that area.
938 frv_stack_info (void)
940 static frv_stack_t info, zero_info;
941 frv_stack_t *info_ptr = &info;
942 tree fndecl = current_function_decl;
950 /* If we've already calculated the values and reload is complete,
953 return frv_stack_cache;
955 /* Zero all fields. */
958 /* Set up the register range information. */
959 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
960 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
961 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
962 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
964 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
965 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
966 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
967 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
969 info_ptr->regs[STACK_REGS_LR].name = "lr";
970 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
971 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
972 info_ptr->regs[STACK_REGS_LR].special_p = 1;
974 info_ptr->regs[STACK_REGS_CC].name = "cc";
975 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
976 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
977 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
979 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
980 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
981 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
983 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
984 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
985 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
986 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
987 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
989 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
990 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
991 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
992 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
994 info_ptr->regs[STACK_REGS_FP].name = "fp";
995 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
996 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
997 info_ptr->regs[STACK_REGS_FP].special_p = 1;
999 /* Determine if this is a stdarg function. If so, allocate space to store
1006 /* Find the last argument, and see if it is __builtin_va_alist. */
1007 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1009 next_arg = TREE_CHAIN (cur_arg);
1010 if (next_arg == (tree)0)
1012 if (DECL_NAME (cur_arg)
1013 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1021 /* Iterate over all of the register ranges. */
1022 for (range = 0; range < STACK_REGS_MAX; range++)
1024 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1025 int first = reg_ptr->first;
1026 int last = reg_ptr->last;
1028 int size_2words = 0;
1031 /* Calculate which registers need to be saved & save area size. */
1035 for (regno = first; regno <= last; regno++)
1037 if ((regs_ever_live[regno] && !call_used_regs[regno])
1038 || (current_function_calls_eh_return
1039 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1040 || (!TARGET_FDPIC && flag_pic
1041 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1043 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1044 size_1word += UNITS_PER_WORD;
1049 /* Calculate whether we need to create a frame after everything else
1050 has been processed. */
1055 if (regs_ever_live[LR_REGNO]
1057 /* This is set for __builtin_return_address, etc. */
1058 || cfun->machine->frame_needed
1059 || (TARGET_LINKED_FP && frame_pointer_needed)
1060 || (!TARGET_FDPIC && flag_pic
1061 && cfun->uses_pic_offset_table))
1063 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1064 size_1word += UNITS_PER_WORD;
1068 case STACK_REGS_STDARG:
1071 /* If this is a stdarg function with a non varardic
1072 argument split between registers and the stack,
1073 adjust the saved registers downward. */
1074 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1077 for (regno = first; regno <= last; regno++)
1079 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1080 size_1word += UNITS_PER_WORD;
1083 info_ptr->stdarg_size = size_1word;
1087 case STACK_REGS_STRUCT:
1088 if (cfun->returns_struct)
1090 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1091 size_1word += UNITS_PER_WORD;
1099 /* If this is a field, it only takes one word. */
1100 if (reg_ptr->field_p)
1101 size_1word = UNITS_PER_WORD;
1103 /* Determine which register pairs can be saved together. */
1104 else if (reg_ptr->dword_p && TARGET_DWORD)
1106 for (regno = first; regno < last; regno += 2)
1108 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1110 size_2words += 2 * UNITS_PER_WORD;
1111 size_1word -= 2 * UNITS_PER_WORD;
1112 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1113 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1118 reg_ptr->size_1word = size_1word;
1119 reg_ptr->size_2words = size_2words;
1121 if (! reg_ptr->special_p)
1123 info_ptr->regs_size_1word += size_1word;
1124 info_ptr->regs_size_2words += size_2words;
1129 /* Set up the sizes of each each field in the frame body, making the sizes
1130 of each be divisible by the size of a dword if dword operations might
1131 be used, or the size of a word otherwise. */
1132 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1134 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1135 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1136 + info_ptr->regs_size_1word,
1138 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1140 info_ptr->pretend_size = cfun->pretend_args_size;
1142 /* Work out the size of the frame, excluding the header. Both the frame
1143 body and register parameter area will be dword-aligned. */
1144 info_ptr->total_size
1145 = (ADDR_ALIGN (info_ptr->parameter_size
1146 + info_ptr->regs_size
1147 + info_ptr->vars_size,
1149 + ADDR_ALIGN (info_ptr->pretend_size
1150 + info_ptr->stdarg_size,
1151 2 * UNITS_PER_WORD));
1153 /* See if we need to create a frame at all, if so add header area. */
1154 if (info_ptr->total_size > 0
1155 || frame_pointer_needed
1156 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1157 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1159 offset = info_ptr->parameter_size;
1160 info_ptr->header_size = 4 * UNITS_PER_WORD;
1161 info_ptr->total_size += 4 * UNITS_PER_WORD;
1163 /* Calculate the offsets to save normal register pairs. */
1164 for (range = 0; range < STACK_REGS_MAX; range++)
1166 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1167 if (! reg_ptr->special_p)
1169 int first = reg_ptr->first;
1170 int last = reg_ptr->last;
1173 for (regno = first; regno <= last; regno++)
1174 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1175 && regno != FRAME_POINTER_REGNUM
1176 && (regno < FIRST_ARG_REGNUM
1177 || regno > LAST_ARG_REGNUM))
1179 info_ptr->reg_offset[regno] = offset;
1180 offset += 2 * UNITS_PER_WORD;
1185 /* Calculate the offsets to save normal single registers. */
1186 for (range = 0; range < STACK_REGS_MAX; range++)
1188 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1189 if (! reg_ptr->special_p)
1191 int first = reg_ptr->first;
1192 int last = reg_ptr->last;
1195 for (regno = first; regno <= last; regno++)
1196 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1197 && regno != FRAME_POINTER_REGNUM
1198 && (regno < FIRST_ARG_REGNUM
1199 || regno > LAST_ARG_REGNUM))
1201 info_ptr->reg_offset[regno] = offset;
1202 offset += UNITS_PER_WORD;
1207 /* Calculate the offset to save the local variables at. */
1208 offset = ADDR_ALIGN (offset, alignment);
1209 if (info_ptr->vars_size)
1211 info_ptr->vars_offset = offset;
1212 offset += info_ptr->vars_size;
1215 /* Align header to a dword-boundary. */
1216 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1218 /* Calculate the offsets in the fixed frame. */
1219 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1220 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1221 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1223 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1224 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1225 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1227 if (cfun->returns_struct)
1229 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1230 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1231 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1234 /* Calculate the offsets to store the arguments passed in registers
1235 for stdarg functions. The register pairs are first and the single
1236 register if any is last. The register save area starts on a
1238 if (info_ptr->stdarg_size)
1240 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1241 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1244 /* Skip the header. */
1245 offset += 4 * UNITS_PER_WORD;
1246 for (regno = first; regno <= last; regno++)
1248 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1250 info_ptr->reg_offset[regno] = offset;
1251 offset += 2 * UNITS_PER_WORD;
1253 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1255 info_ptr->reg_offset[regno] = offset;
1256 offset += UNITS_PER_WORD;
1262 if (reload_completed)
1263 frv_stack_cache = info_ptr;
1269 /* Print the information about the frv stack offsets, etc. when debugging. */
1272 frv_debug_stack (frv_stack_t *info)
1277 info = frv_stack_info ();
1279 fprintf (stderr, "\nStack information for function %s:\n",
1280 ((current_function_decl && DECL_NAME (current_function_decl))
1281 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1284 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1285 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1286 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1287 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1288 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1290 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1291 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1292 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1293 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1295 for (range = 0; range < STACK_REGS_MAX; range++)
1297 frv_stack_regs_t *regs = &(info->regs[range]);
1298 if ((regs->size_1word + regs->size_2words) > 0)
1300 int first = regs->first;
1301 int last = regs->last;
1304 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1305 regs->name, regs->size_1word + regs->size_2words,
1306 regs->size_1word, regs->size_2words);
1308 for (regno = first; regno <= last; regno++)
1310 if (info->save_p[regno] == REG_SAVE_1WORD)
1311 fprintf (stderr, " %s (%d)", reg_names[regno],
1312 info->reg_offset[regno]);
1314 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1315 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1316 reg_names[regno+1], info->reg_offset[regno]);
1319 fputc ('\n', stderr);
1329 /* The following variable value is TRUE if the next output insn should
1330 finish cpu cycle. In order words the insn will have packing bit
1331 (which means absence of asm code suffix `.p' on assembler. */
1333 static int frv_insn_packing_flag;
1335 /* True if the current function contains a far jump. */
1338 frv_function_contains_far_jump (void)
1340 rtx insn = get_insns ();
1342 && !(GET_CODE (insn) == JUMP_INSN
1343 /* Ignore tablejump patterns. */
1344 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1345 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1346 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1347 insn = NEXT_INSN (insn);
1348 return (insn != NULL);
1351 /* For the FRV, this function makes sure that a function with far jumps
1352 will return correctly. It also does the VLIW packing. */
1355 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1357 /* If no frame was created, check whether the function uses a call
1358 instruction to implement a far jump. If so, save the link in gr3 and
1359 replace all returns to LR with returns to GR3. GR3 is used because it
1360 is call-clobbered, because is not available to the register allocator,
1361 and because all functions that take a hidden argument pointer will have
1363 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1367 /* Just to check that the above comment is true. */
1368 if (regs_ever_live[GPR_FIRST + 3])
1371 /* Generate the instruction that saves the link register. */
1372 fprintf (file, "\tmovsg lr,gr3\n");
1374 /* Replace the LR with GR3 in *return_internal patterns. The insn
1375 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1376 simply emit a different assembly directive because bralr and jmpl
1377 execute in different units. */
1378 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1379 if (GET_CODE (insn) == JUMP_INSN)
1381 rtx pattern = PATTERN (insn);
1382 if (GET_CODE (pattern) == PARALLEL
1383 && XVECLEN (pattern, 0) >= 2
1384 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1385 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1387 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1388 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1389 REGNO (address) = GPR_FIRST + 3;
1395 frv_insn_packing_flag = TRUE;
1399 /* Return the next available temporary register in a given class. */
1402 frv_alloc_temp_reg (
1403 frv_tmp_reg_t *info, /* which registers are available */
1404 enum reg_class class, /* register class desired */
1405 enum machine_mode mode, /* mode to allocate register with */
1406 int mark_as_used, /* register not available after allocation */
1407 int no_abort) /* return NULL instead of aborting */
1409 int regno = info->next_reg[ (int)class ];
1410 int orig_regno = regno;
1411 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1416 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1417 && TEST_HARD_REG_BIT (info->regs, regno))
1420 if (++regno >= FIRST_PSEUDO_REGISTER)
1422 if (regno == orig_regno)
1431 nr = HARD_REGNO_NREGS (regno, mode);
1432 info->next_reg[ (int)class ] = regno + nr;
1435 for (i = 0; i < nr; i++)
1436 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1438 return gen_rtx_REG (mode, regno);
1442 /* Return an rtx with the value OFFSET, which will either be a register or a
1443 signed 12-bit integer. It can be used as the second operand in an "add"
1444 instruction, or as the index in a load or store.
1446 The function returns a constant rtx if OFFSET is small enough, otherwise
1447 it loads the constant into register OFFSET_REGNO and returns that. */
1449 frv_frame_offset_rtx (int offset)
1451 rtx offset_rtx = GEN_INT (offset);
1452 if (IN_RANGE_P (offset, -2048, 2047))
1456 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1457 if (IN_RANGE_P (offset, -32768, 32767))
1458 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1461 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1462 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1468 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1469 prologue and epilogue uses such expressions to access the stack. */
1471 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1473 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1475 frv_frame_offset_rtx (offset)));
1478 /* Generate a frame-related expression:
1480 (set REG (mem (plus (sp) (const_int OFFSET)))).
1482 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1483 instructions. Marking the expressions as frame-related is superfluous if
1484 the note contains just a single set. But if the note contains a PARALLEL
1485 or SEQUENCE that has several sets, each set must be individually marked
1486 as frame-related. */
1488 frv_dwarf_store (rtx reg, int offset)
1490 rtx set = gen_rtx_SET (VOIDmode,
1491 gen_rtx_MEM (GET_MODE (reg),
1492 plus_constant (stack_pointer_rtx,
1495 RTX_FRAME_RELATED_P (set) = 1;
1499 /* Emit a frame-related instruction whose pattern is PATTERN. The
1500 instruction is the last in a sequence that cumulatively performs the
1501 operation described by DWARF_PATTERN. The instruction is marked as
1502 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1505 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1507 rtx insn = emit_insn (pattern);
1508 RTX_FRAME_RELATED_P (insn) = 1;
1509 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1514 /* Emit instructions that transfer REG to or from the memory location (sp +
1515 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1516 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1517 function to store registers and only the epilogue uses it to load them.
1519 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1520 The generated instruction will use BASE as its base register. BASE may
1521 simply be the stack pointer, but if several accesses are being made to a
1522 region far away from the stack pointer, it may be more efficient to set
1523 up a temporary instead.
1525 Store instructions will be frame-related and will be annotated with the
1526 overall effect of the store. Load instructions will be followed by a
1527 (use) to prevent later optimizations from zapping them.
1529 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1530 as a temporary in such cases. */
1532 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1534 enum machine_mode mode = GET_MODE (reg);
1535 rtx mem = frv_frame_mem (mode,
1537 stack_offset - accessor->base_offset);
1539 if (accessor->op == FRV_LOAD)
1541 if (SPR_P (REGNO (reg)))
1543 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1544 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1545 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1548 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1549 emit_insn (gen_rtx_USE (VOIDmode, reg));
1553 if (SPR_P (REGNO (reg)))
1555 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1556 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1557 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1558 frv_dwarf_store (reg, stack_offset));
1560 else if (GET_MODE (reg) == DImode)
1562 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1563 with a separate save for each register. */
1564 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1565 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1566 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1567 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1568 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1569 gen_rtx_PARALLEL (VOIDmode,
1570 gen_rtvec (2, set1, set2)));
1573 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1574 frv_dwarf_store (reg, stack_offset));
1578 /* A function that uses frv_frame_access to transfer a group of registers to
1579 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1580 is the stack information generated by frv_stack_info, and REG_SET is the
1581 number of the register set to transfer. */
1583 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1587 frv_stack_regs_t *regs_info;
1590 regs_info = &info->regs[reg_set];
1591 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1592 if (info->save_p[regno])
1593 frv_frame_access (accessor,
1594 info->save_p[regno] == REG_SAVE_2WORDS
1595 ? gen_rtx_REG (DImode, regno)
1596 : gen_rtx_REG (SImode, regno),
1597 info->reg_offset[regno]);
1600 /* Save or restore callee-saved registers that are kept outside the frame
1601 header. The function saves the registers if OP is FRV_STORE and restores
1602 them if OP is FRV_LOAD. INFO is the stack information generated by
1605 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1607 frv_frame_accessor_t accessor;
1610 accessor.base = stack_pointer_rtx;
1611 accessor.base_offset = 0;
1612 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1613 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1614 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1618 /* Called after register allocation to add any instructions needed for the
1619 prologue. Using a prologue insn is favored compared to putting all of the
1620 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1621 it allows the scheduler to intermix instructions with the saves of
1622 the caller saved registers. In some cases, it might be necessary
1623 to emit a barrier instruction as the last insn to prevent such
1626 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1627 so that the debug info generation code can handle them properly. */
1629 frv_expand_prologue (void)
1631 frv_stack_t *info = frv_stack_info ();
1632 rtx sp = stack_pointer_rtx;
1633 rtx fp = frame_pointer_rtx;
1634 frv_frame_accessor_t accessor;
1636 if (TARGET_DEBUG_STACK)
1637 frv_debug_stack (info);
1639 if (info->total_size == 0)
1642 /* We're interested in three areas of the frame here:
1644 A: the register save area
1646 C: the header after B
1648 If the frame pointer isn't used, we'll have to set up A, B and C
1649 using the stack pointer. If the frame pointer is used, we'll access
1653 B: set up using sp or a temporary (see below)
1656 We set up B using the stack pointer if the frame is small enough.
1657 Otherwise, it's more efficient to copy the old stack pointer into a
1658 temporary and use that.
1660 Note that it's important to make sure the prologue and epilogue use the
1661 same registers to access A and C, since doing otherwise will confuse
1662 the aliasing code. */
1664 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1665 isn't used, the same method will serve for C. */
1666 accessor.op = FRV_STORE;
1667 if (frame_pointer_needed && info->total_size > 2048)
1671 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1672 accessor.base_offset = info->total_size;
1673 insn = emit_insn (gen_movsi (accessor.base, sp));
1677 accessor.base = stack_pointer_rtx;
1678 accessor.base_offset = 0;
1681 /* Allocate the stack space. */
1683 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1684 rtx dwarf_offset = GEN_INT (-info->total_size);
1686 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1689 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1692 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1693 and point the new one to that location. */
1694 if (frame_pointer_needed)
1696 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1698 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1699 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1701 rtx asm_src = plus_constant (accessor.base,
1702 fp_offset - accessor.base_offset);
1703 rtx dwarf_src = plus_constant (sp, fp_offset);
1705 /* Store the old frame pointer at (sp + FP_OFFSET). */
1706 frv_frame_access (&accessor, fp, fp_offset);
1708 /* Set up the new frame pointer. */
1709 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1710 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1712 /* Access region C from the frame pointer. */
1714 accessor.base_offset = fp_offset;
1717 /* Set up region C. */
1718 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1719 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1720 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1722 /* Set up region A. */
1723 frv_frame_access_standard_regs (FRV_STORE, info);
1725 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1726 scheduler from moving loads before the stores saving the registers. */
1727 if (info->stdarg_size > 0)
1728 emit_insn (gen_blockage ());
1730 /* Set up pic register/small data register for this function. */
1731 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1732 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1733 gen_rtx_REG (Pmode, LR_REGNO),
1734 gen_rtx_REG (SImode, OFFSET_REGNO)));
1738 /* Under frv, all of the work is done via frv_expand_epilogue, but
1739 this function provides a convenient place to do cleanup. */
1742 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1743 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1745 frv_stack_cache = (frv_stack_t *)0;
1747 /* Zap last used registers for conditional execution. */
1748 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1750 /* Release the bitmap of created insns. */
1751 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1755 /* Called after register allocation to add any instructions needed for the
1756 epilogue. Using an epilogue insn is favored compared to putting all of the
1757 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1758 it allows the scheduler to intermix instructions with the saves of
1759 the caller saved registers. In some cases, it might be necessary
1760 to emit a barrier instruction as the last insn to prevent such
1763 If SIBCALL_P is true, the final branch back to the calling function is
1764 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1765 we must not clobber any arguments used for parameter passing or any stack
1766 slots for arguments passed to the current function. */
1769 frv_expand_epilogue (bool emit_return)
1771 frv_stack_t *info = frv_stack_info ();
1772 rtx fp = frame_pointer_rtx;
1773 rtx sp = stack_pointer_rtx;
1777 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1779 /* Restore the stack pointer to its original value if alloca or the like
1781 if (! current_function_sp_is_unchanging)
1782 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1784 /* Restore the callee-saved registers that were used in this function. */
1785 frv_frame_access_standard_regs (FRV_LOAD, info);
1787 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1788 no return instruction should be emitted. */
1789 if (info->save_p[LR_REGNO])
1794 /* Use the same method to access the link register's slot as we did in
1795 the prologue. In other words, use the frame pointer if available,
1796 otherwise use the stack pointer.
1798 LR_OFFSET is the offset of the link register's slot from the start
1799 of the frame and MEM is a memory rtx for it. */
1800 lr_offset = info->reg_offset[LR_REGNO];
1801 if (frame_pointer_needed)
1802 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1804 mem = frv_frame_mem (Pmode, sp, lr_offset);
1806 /* Load the old link register into a GPR. */
1807 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1808 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1811 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1813 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1814 the load is preserved. */
1815 if (frame_pointer_needed)
1817 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1818 emit_insn (gen_rtx_USE (VOIDmode, fp));
1821 /* Deallocate the stack frame. */
1822 if (info->total_size != 0)
1824 rtx offset = frv_frame_offset_rtx (info->total_size);
1825 emit_insn (gen_stack_adjust (sp, sp, offset));
1828 /* If this function uses eh_return, add the final stack adjustment now. */
1829 if (current_function_calls_eh_return)
1830 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1833 emit_jump_insn (gen_epilogue_return (return_addr));
1836 rtx lr = return_addr;
1838 if (REGNO (return_addr) != LR_REGNO)
1840 lr = gen_rtx_REG (Pmode, LR_REGNO);
1841 emit_move_insn (lr, return_addr);
1844 emit_insn (gen_rtx_USE (VOIDmode, lr));
1849 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1852 frv_asm_output_mi_thunk (FILE *file,
1853 tree thunk_fndecl ATTRIBUTE_UNUSED,
1854 HOST_WIDE_INT delta,
1855 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1858 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1859 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1860 const char *name_jmp = reg_names[JUMP_REGNO];
1861 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1863 /* Do the add using an addi if possible. */
1864 if (IN_RANGE_P (delta, -2048, 2047))
1865 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1868 const char *const name_add = reg_names[TEMP_REGNO];
1869 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1870 parallel, delta, name_add);
1871 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1873 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1878 const char *name_pic = reg_names[FDPIC_REGNO];
1879 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1883 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1884 assemble_name (file, name_func);
1885 fprintf (file, "),%s\n", name_jmp);
1887 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1888 assemble_name (file, name_func);
1889 fprintf (file, "),%s\n", name_jmp);
1891 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1895 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1896 assemble_name (file, name_func);
1897 fprintf (file, "\t)), %s\n", name_jmp);
1902 fprintf (file, "\tsethi%s #hi(", parallel);
1903 assemble_name (file, name_func);
1904 fprintf (file, "),%s\n", name_jmp);
1906 fprintf (file, "\tsetlo #lo(");
1907 assemble_name (file, name_func);
1908 fprintf (file, "),%s\n", name_jmp);
1912 /* Use JUMP_REGNO as a temporary PIC register. */
1913 const char *name_lr = reg_names[LR_REGNO];
1914 const char *name_gppic = name_jmp;
1915 const char *name_tmp = reg_names[TEMP_REGNO];
1917 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1918 fprintf (file, "\tcall 1f\n");
1919 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1920 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1921 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1922 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1923 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1925 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1926 assemble_name (file, name_func);
1927 fprintf (file, "),%s\n", name_tmp);
1929 fprintf (file, "\tsetlo #gprello(");
1930 assemble_name (file, name_func);
1931 fprintf (file, "),%s\n", name_tmp);
1933 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1936 /* Jump to the function address. */
1937 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1941 /* A C expression which is nonzero if a function must have and use a frame
1942 pointer. This expression is evaluated in the reload pass. If its value is
1943 nonzero the function will have a frame pointer.
1945 The expression can in principle examine the current function and decide
1946 according to the facts, but on most machines the constant 0 or the constant
1947 1 suffices. Use 0 when the machine allows code to be generated with no
1948 frame pointer, and doing so saves some time or space. Use 1 when there is
1949 no possible advantage to avoiding a frame pointer.
1951 In certain cases, the compiler does not know how to produce valid code
1952 without a frame pointer. The compiler recognizes those cases and
1953 automatically gives the function a frame pointer regardless of what
1954 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1956 In a function that does not require a frame pointer, the frame pointer
1957 register can be allocated for ordinary usage, unless you mark it as a fixed
1958 register. See `FIXED_REGISTERS' for more information. */
1960 /* On frv, create a frame whenever we need to create stack. */
1963 frv_frame_pointer_required (void)
1965 /* If we forgoing the usual linkage requirements, we only need
1966 a frame pointer if the stack pointer might change. */
1967 if (!TARGET_LINKED_FP)
1968 return !current_function_sp_is_unchanging;
1970 if (! current_function_is_leaf)
1973 if (get_frame_size () != 0)
1979 if (!current_function_sp_is_unchanging)
1982 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1988 if (cfun->machine->frame_needed)
1995 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1996 initial difference between the specified pair of registers. This macro must
1997 be defined if `ELIMINABLE_REGS' is defined. */
1999 /* See frv_stack_info for more details on the frv stack frame. */
2002 frv_initial_elimination_offset (int from, int to)
2004 frv_stack_t *info = frv_stack_info ();
2007 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2008 ret = info->total_size - info->pretend_size;
2010 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2011 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2013 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2014 ret = (info->total_size
2015 - info->reg_offset[FRAME_POINTER_REGNUM]
2016 - info->pretend_size);
2021 if (TARGET_DEBUG_STACK)
2022 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2023 reg_names [from], reg_names[to], ret);
2029 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2032 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2033 enum machine_mode mode,
2034 tree type ATTRIBUTE_UNUSED,
2038 if (TARGET_DEBUG_ARG)
2040 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2041 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2045 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2048 frv_expand_builtin_saveregs (void)
2050 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2052 if (TARGET_DEBUG_ARG)
2053 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2056 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2060 /* Expand __builtin_va_start to do the va_start macro. */
2063 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2066 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2068 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2069 GEN_INT (UNITS_PER_WORD * num));
2071 if (TARGET_DEBUG_ARG)
2073 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2074 cfun->args_info, num);
2076 debug_rtx (nextarg);
2079 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2080 make_tree (ptr_type_node, nextarg));
2081 TREE_SIDE_EFFECTS (t) = 1;
2083 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2087 /* Expand a block move operation, and return 1 if successful. Return 0
2088 if we should let the compiler generate normal code.
2090 operands[0] is the destination
2091 operands[1] is the source
2092 operands[2] is the length
2093 operands[3] is the alignment */
2095 /* Maximum number of loads to do before doing the stores */
2096 #ifndef MAX_MOVE_REG
2097 #define MAX_MOVE_REG 4
2100 /* Maximum number of total loads to do. */
2101 #ifndef TOTAL_MOVE_REG
2102 #define TOTAL_MOVE_REG 8
2106 frv_expand_block_move (rtx operands[])
2108 rtx orig_dest = operands[0];
2109 rtx orig_src = operands[1];
2110 rtx bytes_rtx = operands[2];
2111 rtx align_rtx = operands[3];
2112 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2125 rtx stores[MAX_MOVE_REG];
2127 enum machine_mode mode;
2129 /* If this is not a fixed size move, just call memcpy. */
2133 /* If this is not a fixed size alignment, abort. */
2134 if (GET_CODE (align_rtx) != CONST_INT)
2137 align = INTVAL (align_rtx);
2139 /* Anything to move? */
2140 bytes = INTVAL (bytes_rtx);
2144 /* Don't support real large moves. */
2145 if (bytes > TOTAL_MOVE_REG*align)
2148 /* Move the address into scratch registers. */
2149 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2150 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2152 num_reg = offset = 0;
2153 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2155 /* Calculate the correct offset for src/dest. */
2159 dest_addr = dest_reg;
2163 src_addr = plus_constant (src_reg, offset);
2164 dest_addr = plus_constant (dest_reg, offset);
2167 /* Generate the appropriate load and store, saving the stores
2169 if (bytes >= 4 && align >= 4)
2171 else if (bytes >= 2 && align >= 2)
2176 move_bytes = GET_MODE_SIZE (mode);
2177 tmp_reg = gen_reg_rtx (mode);
2178 src_mem = change_address (orig_src, mode, src_addr);
2179 dest_mem = change_address (orig_dest, mode, dest_addr);
2180 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2181 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2183 if (num_reg >= MAX_MOVE_REG)
2185 for (i = 0; i < num_reg; i++)
2186 emit_insn (stores[i]);
2191 for (i = 0; i < num_reg; i++)
2192 emit_insn (stores[i]);
2198 /* Expand a block clear operation, and return 1 if successful. Return 0
2199 if we should let the compiler generate normal code.
2201 operands[0] is the destination
2202 operands[1] is the length
2203 operands[2] is the alignment */
2206 frv_expand_block_clear (rtx operands[])
2208 rtx orig_dest = operands[0];
2209 rtx bytes_rtx = operands[1];
2210 rtx align_rtx = operands[2];
2211 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2220 enum machine_mode mode;
2222 /* If this is not a fixed size move, just call memcpy. */
2226 /* If this is not a fixed size alignment, abort. */
2227 if (GET_CODE (align_rtx) != CONST_INT)
2230 align = INTVAL (align_rtx);
2232 /* Anything to move? */
2233 bytes = INTVAL (bytes_rtx);
2237 /* Don't support real large clears. */
2238 if (bytes > TOTAL_MOVE_REG*align)
2241 /* Move the address into a scratch register. */
2242 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2244 num_reg = offset = 0;
2245 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2247 /* Calculate the correct offset for src/dest. */
2248 dest_addr = ((offset == 0)
2250 : plus_constant (dest_reg, offset));
2252 /* Generate the appropriate store of gr0. */
2253 if (bytes >= 4 && align >= 4)
2255 else if (bytes >= 2 && align >= 2)
2260 clear_bytes = GET_MODE_SIZE (mode);
2261 dest_mem = change_address (orig_dest, mode, dest_addr);
2262 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2269 /* The following variable is used to output modifiers of assembler
2270 code of the current output insn. */
2272 static rtx *frv_insn_operands;
2274 /* The following function is used to add assembler insn code suffix .p
2275 if it is necessary. */
2278 frv_asm_output_opcode (FILE *f, const char *ptr)
2282 if (! PACKING_FLAG_USED_P())
2285 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2288 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2289 || (*ptr >= 'A' && *ptr <= 'Z')))
2291 int letter = *ptr++;
2294 frv_print_operand (f, frv_insn_operands [c], letter);
2295 while ((c = *ptr) >= '0' && c <= '9')
2302 if (!frv_insn_packing_flag)
2308 /* The following function sets up the packing bit for the current
2309 output insn. Remember that the function is not called for asm
2313 frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED)
2315 if (! PACKING_FLAG_USED_P())
2321 frv_insn_operands = opvec;
2323 /* Look for the next printable instruction. frv_pack_insns () has set
2324 things up so that any printable instruction will have TImode if it
2325 starts a new packet and VOIDmode if it should be packed with the
2326 previous instruction.
2328 Printable instructions will be asm_operands or match one of the .md
2329 patterns. Since asm instructions cannot be packed -- and will
2330 therefore have TImode -- this loop terminates on any recognizable
2331 instruction, and on any unrecognizable instruction with TImode. */
2332 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2336 else if (!INSN_P (insn))
2338 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2342 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2343 be packed with this one. Set it to TRUE otherwise. If the next
2344 instruction is an asm instruction, this statement will set the
2345 flag to TRUE, and that value will still hold when the asm operands
2346 themselves are printed. */
2347 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2348 && GET_MODE (insn) != TImode);
2353 /* A C expression whose value is RTL representing the address in a stack frame
2354 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2355 an RTL expression for the address of the stack frame itself.
2357 If you don't define this macro, the default is to return the value of
2358 FRAMEADDR--that is, the stack frame address is also the address of the stack
2359 word that points to the previous frame. */
2361 /* The default is correct, but we need to make sure the frame gets created. */
2363 frv_dynamic_chain_address (rtx frame)
2365 cfun->machine->frame_needed = 1;
2370 /* A C expression whose value is RTL representing the value of the return
2371 address for the frame COUNT steps up from the current frame, after the
2372 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2373 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2376 The value of the expression must always be the correct address when COUNT is
2377 zero, but may be `NULL_RTX' if there is not way to determine the return
2378 address of other frames. */
2381 frv_return_addr_rtx (int count, rtx frame)
2385 cfun->machine->frame_needed = 1;
2386 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2389 /* Given a memory reference MEMREF, interpret the referenced memory as
2390 an array of MODE values, and return a reference to the element
2391 specified by INDEX. Assume that any pre-modification implicit in
2392 MEMREF has already happened.
2394 MEMREF must be a legitimate operand for modes larger than SImode.
2395 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2396 this function cannot handle. */
2398 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2400 rtx base = XEXP (memref, 0);
2401 if (GET_CODE (base) == PRE_MODIFY)
2402 base = XEXP (base, 0);
2403 return change_address (memref, mode,
2404 plus_constant (base, index * GET_MODE_SIZE (mode)));
2408 /* Print a memory address as an operand to reference that memory location. */
2410 frv_print_operand_address (FILE * stream, rtx x)
2412 if (GET_CODE (x) == MEM)
2415 switch (GET_CODE (x))
2418 fputs (reg_names [ REGNO (x)], stream);
2422 fprintf (stream, "%ld", (long) INTVAL (x));
2426 assemble_name (stream, XSTR (x, 0));
2431 output_addr_const (stream, x);
2438 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2443 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2445 int regno = true_regnum (x);
2447 fputs (reg_names[regno], stream);
2449 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2452 /* Print a memory reference suitable for the ld/st instructions. */
2455 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2457 struct frv_unspec unspec;
2461 switch (GET_CODE (x))
2468 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2470 x1 = XEXP (XEXP (x, 1), 1);
2480 if (GET_CODE (x0) == CONST_INT)
2488 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2497 else if (GET_CODE (x1) != CONST_INT)
2498 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2501 fputs ("@(", stream);
2503 fputs (reg_names[GPR_R0], stream);
2504 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2505 frv_print_operand_memory_reference_reg (stream, x0);
2507 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2509 fputs (",", stream);
2511 fputs (reg_names [GPR_R0], stream);
2515 switch (GET_CODE (x1))
2519 frv_print_operand_memory_reference_reg (stream, x1);
2523 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2527 if (!frv_const_unspec_p (x1, &unspec))
2528 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2529 frv_output_const_unspec (stream, &unspec);
2533 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2537 fputs (")", stream);
2541 /* Return 2 for likely branches and 0 for non-likely branches */
2543 #define FRV_JUMP_LIKELY 2
2544 #define FRV_JUMP_NOT_LIKELY 0
2547 frv_print_operand_jump_hint (rtx insn)
2552 HOST_WIDE_INT prob = -1;
2553 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2555 if (GET_CODE (insn) != JUMP_INSN)
2558 /* Assume any non-conditional jump is likely. */
2559 if (! any_condjump_p (insn))
2560 ret = FRV_JUMP_LIKELY;
2564 labelref = condjump_label (insn);
2567 rtx label = XEXP (labelref, 0);
2568 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2573 note = find_reg_note (insn, REG_BR_PROB, 0);
2575 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2579 prob = INTVAL (XEXP (note, 0));
2580 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2582 : FRV_JUMP_NOT_LIKELY);
2594 case UNKNOWN: direction = "unknown jump direction"; break;
2595 case BACKWARD: direction = "jump backward"; break;
2596 case FORWARD: direction = "jump forward"; break;
2600 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2601 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2602 (long)INSN_UID (insn), direction, (long)prob,
2603 (long)REG_BR_PROB_BASE, ret);
2611 /* Print an operand to an assembler instruction.
2613 `%' followed by a letter and a digit says to output an operand in an
2614 alternate fashion. Four letters have standard, built-in meanings described
2615 below. The machine description macro `PRINT_OPERAND' can define additional
2616 letters with nonstandard meanings.
2618 `%cDIGIT' can be used to substitute an operand that is a constant value
2619 without the syntax that normally indicates an immediate operand.
2621 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2624 `%aDIGIT' can be used to substitute an operand as if it were a memory
2625 reference, with the actual operand treated as the address. This may be
2626 useful when outputting a "load address" instruction, because often the
2627 assembler syntax for such an instruction requires you to write the operand
2628 as if it were a memory reference.
2630 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2632 `%=' outputs a number which is unique to each instruction in the entire
2633 compilation. This is useful for making local labels to be referred to more
2634 than once in a single template that generates multiple assembler
2637 `%' followed by a punctuation character specifies a substitution that does
2638 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2639 assembler code. Other nonstandard cases can be defined in the
2640 `PRINT_OPERAND' macro. You must also define which punctuation characters
2641 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2644 frv_print_operand (FILE * file, rtx x, int code)
2646 struct frv_unspec unspec;
2647 HOST_WIDE_INT value;
2650 if (code != 0 && !isalpha (code))
2653 else if (GET_CODE (x) == CONST_INT)
2656 else if (GET_CODE (x) == CONST_DOUBLE)
2658 if (GET_MODE (x) == SFmode)
2663 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2664 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2668 else if (GET_MODE (x) == VOIDmode)
2669 value = CONST_DOUBLE_LOW (x);
2672 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2683 fputs (reg_names[GPR_R0], file);
2687 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2691 /* Output small data area base register (gr16). */
2692 fputs (reg_names[SDA_BASE_REG], file);
2696 /* Output pic register (gr17). */
2697 fputs (reg_names[PIC_REGNO], file);
2701 /* Output the temporary integer CCR register. */
2702 fputs (reg_names[ICR_TEMP], file);
2706 /* Output the temporary integer CC register. */
2707 fputs (reg_names[ICC_TEMP], file);
2710 /* case 'a': print an address. */
2713 /* Print appropriate test for integer branch false operation. */
2714 switch (GET_CODE (x))
2717 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2719 case EQ: fputs ("ne", file); break;
2720 case NE: fputs ("eq", file); break;
2721 case LT: fputs ("ge", file); break;
2722 case LE: fputs ("gt", file); break;
2723 case GT: fputs ("le", file); break;
2724 case GE: fputs ("lt", file); break;
2725 case LTU: fputs ("nc", file); break;
2726 case LEU: fputs ("hi", file); break;
2727 case GTU: fputs ("ls", file); break;
2728 case GEU: fputs ("c", file); break;
2732 /* case 'c': print a constant without the constant prefix. If
2733 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2736 /* Print appropriate test for integer branch true operation. */
2737 switch (GET_CODE (x))
2740 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2742 case EQ: fputs ("eq", file); break;
2743 case NE: fputs ("ne", file); break;
2744 case LT: fputs ("lt", file); break;
2745 case LE: fputs ("le", file); break;
2746 case GT: fputs ("gt", file); break;
2747 case GE: fputs ("ge", file); break;
2748 case LTU: fputs ("c", file); break;
2749 case LEU: fputs ("ls", file); break;
2750 case GTU: fputs ("hi", file); break;
2751 case GEU: fputs ("nc", file); break;
2756 /* Print 1 for a NE and 0 for an EQ to give the final argument
2757 for a conditional instruction. */
2758 if (GET_CODE (x) == NE)
2761 else if (GET_CODE (x) == EQ)
2765 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2769 /* Print appropriate test for floating point branch false operation. */
2770 switch (GET_CODE (x))
2773 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2775 case EQ: fputs ("ne", file); break;
2776 case NE: fputs ("eq", file); break;
2777 case LT: fputs ("uge", file); break;
2778 case LE: fputs ("ug", file); break;
2779 case GT: fputs ("ule", file); break;
2780 case GE: fputs ("ul", file); break;
2785 /* Print appropriate test for floating point branch true operation. */
2786 switch (GET_CODE (x))
2789 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2791 case EQ: fputs ("eq", file); break;
2792 case NE: fputs ("ne", file); break;
2793 case LT: fputs ("lt", file); break;
2794 case LE: fputs ("le", file); break;
2795 case GT: fputs ("gt", file); break;
2796 case GE: fputs ("ge", file); break;
2801 /* Print appropriate GOT function. */
2802 if (GET_CODE (x) != CONST_INT)
2803 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2804 fputs (unspec_got_name (INTVAL (x)), file);
2808 /* Print 'i' if the operand is a constant, or is a memory reference that
2810 if (GET_CODE (x) == MEM)
2811 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2812 ? XEXP (XEXP (x, 0), 1)
2814 else if (GET_CODE (x) == PLUS)
2817 switch (GET_CODE (x))
2831 /* For jump instructions, print 'i' if the operand is a constant or
2832 is an expression that adds a constant. */
2833 if (GET_CODE (x) == CONST_INT)
2838 if (GET_CODE (x) == CONST_INT
2839 || (GET_CODE (x) == PLUS
2840 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2841 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2847 /* Print the lower register of a double word register pair */
2848 if (GET_CODE (x) == REG)
2849 fputs (reg_names[ REGNO (x)+1 ], file);
2851 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2854 /* case 'l': print a LABEL_REF. */
2858 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2859 for the second word of double memory operations. */
2860 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2861 switch (GET_CODE (x))
2864 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2867 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2875 frv_print_operand_memory_reference (file, x, offset);
2881 /* Print the opcode of a command. */
2882 switch (GET_CODE (x))
2885 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2887 case PLUS: fputs ("add", file); break;
2888 case MINUS: fputs ("sub", file); break;
2889 case AND: fputs ("and", file); break;
2890 case IOR: fputs ("or", file); break;
2891 case XOR: fputs ("xor", file); break;
2892 case ASHIFT: fputs ("sll", file); break;
2893 case ASHIFTRT: fputs ("sra", file); break;
2894 case LSHIFTRT: fputs ("srl", file); break;
2898 /* case 'n': negate and print a constant int. */
2901 /* Print PIC label using operand as the number. */
2902 if (GET_CODE (x) != CONST_INT)
2903 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2905 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2909 /* Print 'u' if the operand is a update load/store. */
2910 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2915 /* If value is 0, print gr0, otherwise it must be a register. */
2916 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2917 fputs (reg_names[GPR_R0], file);
2919 else if (GET_CODE (x) == REG)
2920 fputs (reg_names [REGNO (x)], file);
2923 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2927 /* Print constant in hex. */
2928 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2930 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2937 if (GET_CODE (x) == REG)
2938 fputs (reg_names [REGNO (x)], file);
2940 else if (GET_CODE (x) == CONST_INT
2941 || GET_CODE (x) == CONST_DOUBLE)
2942 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2944 else if (frv_const_unspec_p (x, &unspec))
2945 frv_output_const_unspec (file, &unspec);
2947 else if (GET_CODE (x) == MEM)
2948 frv_print_operand_address (file, XEXP (x, 0));
2950 else if (CONSTANT_ADDRESS_P (x))
2951 frv_print_operand_address (file, x);
2954 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
2959 fatal_insn ("frv_print_operand: unknown code", x);
2967 /* A C statement (sans semicolon) for initializing the variable CUM for the
2968 state at the beginning of the argument list. The variable has type
2969 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2970 of the function which will receive the args, or 0 if the args are to a
2971 compiler support library function. The value of INDIRECT is nonzero when
2972 processing an indirect call, for example a call through a function pointer.
2973 The value of INDIRECT is zero for a call to an explicitly named function, a
2974 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
2975 arguments for the function being compiled.
2977 When processing a call to a compiler support library function, LIBNAME
2978 identifies which one. It is a `symbol_ref' rtx which contains the name of
2979 the function, as a string. LIBNAME is 0 when an ordinary C function call is
2980 being processed. Thus, each time this macro is called, either LIBNAME or
2981 FNTYPE is nonzero, but never both of them at once. */
2984 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
2990 *cum = FIRST_ARG_REGNUM;
2992 if (TARGET_DEBUG_ARG)
2994 fprintf (stderr, "\ninit_cumulative_args:");
2995 if (!fndecl && fntype)
2996 fputs (" indirect", stderr);
2999 fputs (" incoming", stderr);
3003 tree ret_type = TREE_TYPE (fntype);
3004 fprintf (stderr, " return=%s,",
3005 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3008 if (libname && GET_CODE (libname) == SYMBOL_REF)
3009 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3011 if (cfun->returns_struct)
3012 fprintf (stderr, " return-struct");
3014 putc ('\n', stderr);
3019 /* Return true if we should pass an argument on the stack rather than
3023 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3025 if (mode == BLKmode)
3029 return AGGREGATE_TYPE_P (type);
3032 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3033 argument with the specified mode and type. If it is not defined,
3034 `PARM_BOUNDARY' is used for all arguments. */
3037 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3038 tree type ATTRIBUTE_UNUSED)
3040 return BITS_PER_WORD;
3044 frv_function_arg (CUMULATIVE_ARGS *cum,
3045 enum machine_mode mode,
3046 tree type ATTRIBUTE_UNUSED,
3048 int incoming ATTRIBUTE_UNUSED)
3050 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3055 /* Return a marker for use in the call instruction. */
3056 if (xmode == VOIDmode)
3062 else if (arg_num <= LAST_ARG_REGNUM)
3064 ret = gen_rtx_REG (xmode, arg_num);
3065 debstr = reg_names[arg_num];
3074 if (TARGET_DEBUG_ARG)
3076 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3077 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3083 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3084 advance past an argument in the argument list. The values MODE, TYPE and
3085 NAMED describe that argument. Once this is done, the variable CUM is
3086 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3088 This macro need not do anything if the argument in question was passed on
3089 the stack. The compiler knows how to track the amount of stack space used
3090 for arguments without any special help. */
3093 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3094 enum machine_mode mode,
3095 tree type ATTRIBUTE_UNUSED,
3098 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3099 int bytes = GET_MODE_SIZE (xmode);
3100 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3103 *cum = arg_num + words;
3105 if (TARGET_DEBUG_ARG)
3107 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3108 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3112 /* A C expression for the number of words, at the beginning of an argument,
3113 must be put in registers. The value must be zero for arguments that are
3114 passed entirely in registers or that are entirely pushed on the stack.
3116 On some machines, certain arguments must be passed partially in registers
3117 and partially in memory. On these machines, typically the first N words of
3118 arguments are passed in registers, and the rest on the stack. If a
3119 multi-word argument (a `double' or a structure) crosses that boundary, its
3120 first few words must be passed in registers and the rest must be pushed.
3121 This macro tells the compiler when this occurs, and how many of the words
3122 should go in registers.
3124 `FUNCTION_ARG' for these arguments should return the first register to be
3125 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3126 the called function. */
3129 frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum,
3130 enum machine_mode mode,
3131 tree type ATTRIBUTE_UNUSED,
3132 int named ATTRIBUTE_UNUSED)
3134 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3135 int bytes = GET_MODE_SIZE (xmode);
3136 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3140 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3141 ? LAST_ARG_REGNUM - arg_num + 1
3144 if (TARGET_DEBUG_ARG && ret)
3145 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3152 /* If defined, a C expression that indicates when it is the called function's
3153 responsibility to make a copy of arguments passed by invisible reference.
3154 Normally, the caller makes a copy and passes the address of the copy to the
3155 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3156 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3157 the "live" value. The called function must not modify this value. If it
3158 can be determined that the value won't be modified, it need not make a copy;
3159 otherwise a copy must be made. */
3162 frv_function_arg_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3163 enum machine_mode mode ATTRIBUTE_UNUSED,
3164 tree type ATTRIBUTE_UNUSED,
3165 int named ATTRIBUTE_UNUSED)
3171 /* Return true if a register is ok to use as a base or index register. */
3173 static FRV_INLINE int
3174 frv_regno_ok_for_base_p (int regno, int strict_p)
3180 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3182 if (regno == ARG_POINTER_REGNUM)
3185 return (regno >= FIRST_PSEUDO_REGISTER);
3189 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3190 RTX) is a legitimate memory address on the target machine for a memory
3191 operand of mode MODE.
3193 It usually pays to define several simpler macros to serve as subroutines for
3194 this one. Otherwise it may be too complicated to understand.
3196 This macro must exist in two variants: a strict variant and a non-strict
3197 one. The strict variant is used in the reload pass. It must be defined so
3198 that any pseudo-register that has not been allocated a hard register is
3199 considered a memory reference. In contexts where some kind of register is
3200 required, a pseudo-register with no hard register must be rejected.
3202 The non-strict variant is used in other passes. It must be defined to
3203 accept all pseudo-registers in every context where some kind of register is
3206 Compiler source files that want to use the strict variant of this macro
3207 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3208 conditional to define the strict variant in that case and the non-strict
3211 Subroutines to check for acceptable registers for various purposes (one for
3212 base registers, one for index registers, and so on) are typically among the
3213 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3214 subroutine macros need have two variants; the higher levels of macros may be
3215 the same whether strict or not.
3217 Normally, constant addresses which are the sum of a `symbol_ref' and an
3218 integer are stored inside a `const' RTX to mark them as constant.
3219 Therefore, there is no need to recognize such sums specifically as
3220 legitimate addresses. Normally you would simply recognize any `const' as
3223 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3224 are not marked with `const'. It assumes that a naked `plus' indicates
3225 indexing. If so, then you *must* reject such naked constant sums as
3226 illegitimate addresses, so that none of them will be given to
3227 `PRINT_OPERAND_ADDRESS'.
3229 On some machines, whether a symbolic address is legitimate depends on the
3230 section that the address refers to. On these machines, define the macro
3231 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3232 then check for it here. When you see a `const', you will have to look
3233 inside it to find the `symbol_ref' in order to determine the section.
3235 The best way to modify the name string is by adding text to the beginning,
3236 with suitable punctuation to prevent any ambiguity. Allocate the new name
3237 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3238 remove and decode the added text and output the name accordingly, and define
3239 `(* targetm.strip_name_encoding)' to access the original name string.
3241 You can check the information stored here into the `symbol_ref' in the
3242 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3243 `PRINT_OPERAND_ADDRESS'. */
3246 frv_legitimate_address_p (enum machine_mode mode,
3250 int allow_double_reg_p)
3254 HOST_WIDE_INT value;
3257 switch (GET_CODE (x))
3264 if (GET_CODE (x) != REG)
3270 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3276 if (GET_CODE (x0) != REG
3277 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3278 || GET_CODE (x1) != PLUS
3279 || ! rtx_equal_p (x0, XEXP (x1, 0))
3280 || GET_CODE (XEXP (x1, 1)) != REG
3281 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3288 /* 12 bit immediate */
3293 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3295 /* If we can't use load/store double operations, make sure we can
3296 address the second word. */
3297 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3298 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3307 if (GET_CODE (x0) == SUBREG)
3308 x0 = SUBREG_REG (x0);
3310 if (GET_CODE (x0) != REG)
3313 regno0 = REGNO (x0);
3314 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3317 switch (GET_CODE (x1))
3323 x1 = SUBREG_REG (x1);
3324 if (GET_CODE (x1) != REG)
3330 /* Do not allow reg+reg addressing for modes > 1 word if we
3331 can't depend on having move double instructions. */
3332 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3335 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3339 /* 12 bit immediate */
3344 value = INTVAL (x1);
3345 ret = IN_RANGE_P (value, -2048, 2047);
3347 /* If we can't use load/store double operations, make sure we can
3348 address the second word. */
3349 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3350 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3355 if (!condexec_p && got12_operand (x1, VOIDmode))
3363 if (TARGET_DEBUG_ADDR)
3365 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3366 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3367 (condexec_p) ? ", inside conditional code" : "");
3375 /* Test whether a local function descriptor is canonical, i.e.,
3376 whether we can use FUNCDESC_GOTOFF to compute the address of the
3380 frv_local_funcdesc_p (rtx fnx)
3383 enum symbol_visibility vis;
3386 if (! SYMBOL_REF_LOCAL_P (fnx))
3389 fn = SYMBOL_REF_DECL (fnx);
3394 vis = DECL_VISIBILITY (fn);
3396 if (vis == VISIBILITY_PROTECTED)
3397 /* Private function descriptors for protected functions are not
3398 canonical. Temporarily change the visibility to global. */
3399 vis = VISIBILITY_DEFAULT;
3400 else if (flag_shlib)
3401 /* If we're already compiling for a shared library (that, unlike
3402 executables, can't assume that the existence of a definition
3403 implies local binding), we can skip the re-testing. */
3406 ret = default_binds_local_p_1 (fn, flag_pic);
3408 DECL_VISIBILITY (fn) = vis;
3413 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3417 frv_gen_GPsym2reg (rtx dest, rtx src)
3419 tree gp = get_identifier ("_gp");
3420 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3422 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3426 unspec_got_name (int i)
3430 case R_FRV_GOT12: return "got12";
3431 case R_FRV_GOTHI: return "gothi";
3432 case R_FRV_GOTLO: return "gotlo";
3433 case R_FRV_FUNCDESC: return "funcdesc";
3434 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3435 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3436 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3437 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3438 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3439 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3440 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3441 case R_FRV_GOTOFF12: return "gotoff12";
3442 case R_FRV_GOTOFFHI: return "gotoffhi";
3443 case R_FRV_GOTOFFLO: return "gotofflo";
3444 case R_FRV_GPREL12: return "gprel12";
3445 case R_FRV_GPRELHI: return "gprelhi";
3446 case R_FRV_GPRELLO: return "gprello";
3451 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3452 is added inside the relocation operator. */
3455 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3457 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3458 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3459 fputs (")", stream);
3462 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3463 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3464 otherwise return ORIG_X. */
3467 frv_find_base_term (rtx x)
3469 struct frv_unspec unspec;
3471 if (frv_const_unspec_p (x, &unspec)
3472 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3473 return plus_constant (unspec.symbol, unspec.offset);
3478 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3479 the operand is used by a predicated instruction. */
3482 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3484 return ((GET_MODE (op) == mode || mode == VOIDmode)
3485 && GET_CODE (op) == MEM
3486 && frv_legitimate_address_p (mode, XEXP (op, 0),
3487 reload_completed, condexec_p, FALSE));
3491 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3493 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3494 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3500 rvrtx = operands[0];
3504 addr = XEXP (operands[0], 0);
3506 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3507 any calls that would involve a PLT, but can't tell, since we
3508 don't know whether an extern function is going to be provided by
3509 a separate translation unit or imported from a separate module.
3510 When compiling for shared libraries, if the function has default
3511 visibility, we assume it's overridable, so we inline the PLT, but
3512 for executables, we don't really have a way to make a good
3513 decision: a function is as likely to be imported from a shared
3514 library as it is to be defined in the executable itself. We
3515 assume executables will get global functions defined locally,
3516 whereas shared libraries will have them potentially overridden,
3517 so we only inline PLTs when compiling for shared libraries.
3519 In order to mark a function as local to a shared library, any
3520 non-default visibility attribute suffices. Unfortunately,
3521 there's no simple way to tag a function declaration as ``in a
3522 different module'', which we could then use to trigger PLT
3523 inlining on executables. There's -minline-plt, but it affects
3524 all external functions, so one would have to also mark function
3525 declarations available in the same module with non-default
3526 visibility, which is advantageous in itself. */
3527 if (GET_CODE (addr) == SYMBOL_REF
3528 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3532 dest = gen_reg_rtx (SImode);
3534 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3535 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3537 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3538 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3540 cfun->uses_pic_offset_table = TRUE;
3543 else if (GET_CODE (addr) == SYMBOL_REF)
3545 /* These are always either local, or handled through a local
3548 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3549 operands[2], picreg, lr);
3551 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3555 else if (! ldd_address_operand (addr, Pmode))
3556 addr = force_reg (Pmode, addr);
3558 picreg = gen_reg_rtx (DImode);
3559 emit_insn (gen_movdi_ldd (picreg, addr));
3561 if (sibcall && ret_value)
3562 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3564 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3566 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3568 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3572 /* An address operand that may use a pair of registers, an addressing
3573 mode that we reject in general. */
3576 ldd_address_operand (rtx x, enum machine_mode mode)
3578 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3581 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3585 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3587 if (GET_MODE (op) != mode && mode != VOIDmode)
3589 if (GET_CODE (op) != REG)
3591 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3596 /* Return 1 is OP is a memory operand, or will be turned into one by
3600 frv_load_operand (rtx op, enum machine_mode mode)
3602 if (GET_MODE (op) != mode && mode != VOIDmode)
3605 if (reload_in_progress)
3608 if (GET_CODE (tmp) == SUBREG)
3609 tmp = SUBREG_REG (tmp);
3610 if (GET_CODE (tmp) == REG
3611 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3612 op = reg_equiv_memory_loc[REGNO (tmp)];
3615 return op && memory_operand (op, mode);
3619 /* Return 1 if operand is a GPR register or a FPR register. */
3622 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3626 if (GET_MODE (op) != mode && mode != VOIDmode)
3629 if (GET_CODE (op) == SUBREG)
3631 if (GET_CODE (SUBREG_REG (op)) != REG)
3632 return register_operand (op, mode);
3634 op = SUBREG_REG (op);
3637 if (GET_CODE (op) != REG)
3641 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3647 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3650 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3652 if (GET_CODE (op) == CONST_INT)
3653 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3655 if (got12_operand (op, mode))
3658 if (GET_MODE (op) != mode && mode != VOIDmode)
3661 if (GET_CODE (op) == SUBREG)
3663 if (GET_CODE (SUBREG_REG (op)) != REG)
3664 return register_operand (op, mode);
3666 op = SUBREG_REG (op);
3669 if (GET_CODE (op) != REG)
3672 return GPR_OR_PSEUDO_P (REGNO (op));
3675 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3676 signed immediate. */
3679 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3683 if (GET_CODE (op) == CONST_INT)
3684 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3686 if (GET_MODE (op) != mode && mode != VOIDmode)
3689 if (GET_CODE (op) == SUBREG)
3691 if (GET_CODE (SUBREG_REG (op)) != REG)
3692 return register_operand (op, mode);
3694 op = SUBREG_REG (op);
3697 if (GET_CODE (op) != REG)
3701 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3707 /* Return 1 if operand is a register or 6 bit signed immediate. */
3710 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3712 if (GET_CODE (op) == CONST_INT)
3713 return IN_RANGE_P (INTVAL (op), -32, 31);
3715 if (GET_MODE (op) != mode && mode != VOIDmode)
3718 if (GET_CODE (op) == SUBREG)
3720 if (GET_CODE (SUBREG_REG (op)) != REG)
3721 return register_operand (op, mode);
3723 op = SUBREG_REG (op);
3726 if (GET_CODE (op) != REG)
3729 return FPR_OR_PSEUDO_P (REGNO (op));
3732 /* Return 1 if operand is a register or 10 bit signed immediate. */
3735 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3737 if (GET_CODE (op) == CONST_INT)
3738 return IN_RANGE_P (INTVAL (op), -512, 511);
3740 if (GET_MODE (op) != mode && mode != VOIDmode)
3743 if (GET_CODE (op) == SUBREG)
3745 if (GET_CODE (SUBREG_REG (op)) != REG)
3746 return register_operand (op, mode);
3748 op = SUBREG_REG (op);
3751 if (GET_CODE (op) != REG)
3754 return GPR_OR_PSEUDO_P (REGNO (op));
3757 /* Return 1 if operand is a register or an integer immediate. */
3760 gpr_or_int_operand (rtx op, enum machine_mode mode)
3762 if (GET_CODE (op) == CONST_INT)
3765 if (GET_MODE (op) != mode && mode != VOIDmode)
3768 if (GET_CODE (op) == SUBREG)
3770 if (GET_CODE (SUBREG_REG (op)) != REG)
3771 return register_operand (op, mode);
3773 op = SUBREG_REG (op);
3776 if (GET_CODE (op) != REG)
3779 return GPR_OR_PSEUDO_P (REGNO (op));
3782 /* Return 1 if operand is a 12 bit signed immediate. */
3785 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3787 if (GET_CODE (op) != CONST_INT)
3790 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3793 /* Return 1 if operand is a 6 bit signed immediate. */
3796 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3798 if (GET_CODE (op) != CONST_INT)
3801 return IN_RANGE_P (INTVAL (op), -32, 31);
3804 /* Return 1 if operand is a 5 bit signed immediate. */
3807 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3809 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3812 /* Return 1 if operand is a 5 bit unsigned immediate. */
3815 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3817 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3820 /* Return 1 if operand is a 4 bit unsigned immediate. */
3823 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3825 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3828 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3831 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3833 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3836 /* Return 1 if operand is an integer constant that takes 2 instructions
3837 to load up and can be split into sethi/setlo instructions.. */
3840 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3842 HOST_WIDE_INT value;
3846 switch (GET_CODE (op))
3855 return (flag_pic == 0);
3858 if (flag_pic || TARGET_FDPIC)
3862 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3864 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
3870 /* small data references are already 1 word */
3871 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3874 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3877 if (GET_MODE (op) == SFmode)
3879 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3880 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3882 return ! IN_RANGE_P (value, -32768, 32767);
3884 else if (GET_MODE (op) == VOIDmode)
3886 value = CONST_DOUBLE_LOW (op);
3887 return ! IN_RANGE_P (value, -32768, 32767);
3895 /* Return 1 if operand is a 16 bit unsigned immediate. */
3898 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3900 if (GET_CODE (op) != CONST_INT)
3903 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3906 /* Return 1 if operand is an integer constant with the bottom 16 bits
3910 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3912 if (GET_CODE (op) != CONST_INT)
3915 return ((INTVAL (op) & 0xffff) == 0);
3918 /* Return true if operand is a GPR register. */
3921 integer_register_operand (rtx op, enum machine_mode mode)
3923 if (GET_MODE (op) != mode && mode != VOIDmode)
3926 if (GET_CODE (op) == SUBREG)
3928 if (GET_CODE (SUBREG_REG (op)) != REG)
3929 return register_operand (op, mode);
3931 op = SUBREG_REG (op);
3934 if (GET_CODE (op) != REG)
3937 return GPR_OR_PSEUDO_P (REGNO (op));
3940 /* Return true if operand is a GPR register. Do not allow SUBREG's
3941 here, in order to prevent a combine bug. */
3944 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
3946 if (GET_MODE (op) != mode && mode != VOIDmode)
3949 if (GET_CODE (op) != REG)
3952 return GPR_OR_PSEUDO_P (REGNO (op));
3955 /* Return true if operand is a FPR register. */
3958 fpr_operand (rtx op, enum machine_mode mode)
3960 if (GET_MODE (op) != mode && mode != VOIDmode)
3963 if (GET_CODE (op) == SUBREG)
3965 if (GET_CODE (SUBREG_REG (op)) != REG)
3966 return register_operand (op, mode);
3968 op = SUBREG_REG (op);
3971 if (GET_CODE (op) != REG)
3974 return FPR_OR_PSEUDO_P (REGNO (op));
3977 /* Return true if operand is an even GPR or FPR register. */
3980 even_reg_operand (rtx op, enum machine_mode mode)
3984 if (GET_MODE (op) != mode && mode != VOIDmode)
3987 if (GET_CODE (op) == SUBREG)
3989 if (GET_CODE (SUBREG_REG (op)) != REG)
3990 return register_operand (op, mode);
3992 op = SUBREG_REG (op);
3995 if (GET_CODE (op) != REG)
3999 if (regno >= FIRST_PSEUDO_REGISTER)
4003 return (((regno - GPR_FIRST) & 1) == 0);
4006 return (((regno - FPR_FIRST) & 1) == 0);
4011 /* Return true if operand is an odd GPR register. */
4014 odd_reg_operand (rtx op, enum machine_mode mode)
4018 if (GET_MODE (op) != mode && mode != VOIDmode)
4021 if (GET_CODE (op) == SUBREG)
4023 if (GET_CODE (SUBREG_REG (op)) != REG)
4024 return register_operand (op, mode);
4026 op = SUBREG_REG (op);
4029 if (GET_CODE (op) != REG)
4033 /* Assume that reload will give us an even register. */
4034 if (regno >= FIRST_PSEUDO_REGISTER)
4038 return (((regno - GPR_FIRST) & 1) != 0);
4041 return (((regno - FPR_FIRST) & 1) != 0);
4046 /* Return true if operand is an even GPR register. */
4049 even_gpr_operand (rtx op, enum machine_mode mode)
4053 if (GET_MODE (op) != mode && mode != VOIDmode)
4056 if (GET_CODE (op) == SUBREG)
4058 if (GET_CODE (SUBREG_REG (op)) != REG)
4059 return register_operand (op, mode);
4061 op = SUBREG_REG (op);
4064 if (GET_CODE (op) != REG)
4068 if (regno >= FIRST_PSEUDO_REGISTER)
4071 if (! GPR_P (regno))
4074 return (((regno - GPR_FIRST) & 1) == 0);
4077 /* Return true if operand is an odd GPR register. */
4080 odd_gpr_operand (rtx op, enum machine_mode mode)
4084 if (GET_MODE (op) != mode && mode != VOIDmode)
4087 if (GET_CODE (op) == SUBREG)
4089 if (GET_CODE (SUBREG_REG (op)) != REG)
4090 return register_operand (op, mode);
4092 op = SUBREG_REG (op);
4095 if (GET_CODE (op) != REG)
4099 /* Assume that reload will give us an even register. */
4100 if (regno >= FIRST_PSEUDO_REGISTER)
4103 if (! GPR_P (regno))
4106 return (((regno - GPR_FIRST) & 1) != 0);
4109 /* Return true if operand is a quad aligned FPR register. */
4112 quad_fpr_operand (rtx op, enum machine_mode mode)
4116 if (GET_MODE (op) != mode && mode != VOIDmode)
4119 if (GET_CODE (op) == SUBREG)
4121 if (GET_CODE (SUBREG_REG (op)) != REG)
4122 return register_operand (op, mode);
4124 op = SUBREG_REG (op);
4127 if (GET_CODE (op) != REG)
4131 if (regno >= FIRST_PSEUDO_REGISTER)
4134 if (! FPR_P (regno))
4137 return (((regno - FPR_FIRST) & 3) == 0);
4140 /* Return true if operand is an even FPR register. */
4143 even_fpr_operand (rtx op, enum machine_mode mode)
4147 if (GET_MODE (op) != mode && mode != VOIDmode)
4150 if (GET_CODE (op) == SUBREG)
4152 if (GET_CODE (SUBREG_REG (op)) != REG)
4153 return register_operand (op, mode);
4155 op = SUBREG_REG (op);
4158 if (GET_CODE (op) != REG)
4162 if (regno >= FIRST_PSEUDO_REGISTER)
4165 if (! FPR_P (regno))
4168 return (((regno - FPR_FIRST) & 1) == 0);
4171 /* Return true if operand is an odd FPR register. */
4174 odd_fpr_operand (rtx op, enum machine_mode mode)
4178 if (GET_MODE (op) != mode && mode != VOIDmode)
4181 if (GET_CODE (op) == SUBREG)
4183 if (GET_CODE (SUBREG_REG (op)) != REG)
4184 return register_operand (op, mode);
4186 op = SUBREG_REG (op);
4189 if (GET_CODE (op) != REG)
4193 /* Assume that reload will give us an even register. */
4194 if (regno >= FIRST_PSEUDO_REGISTER)
4197 if (! FPR_P (regno))
4200 return (((regno - FPR_FIRST) & 1) != 0);
4203 /* Return true if operand is a 2 word memory address that can be loaded in one
4204 instruction to load or store. We assume the stack and frame pointers are
4205 suitably aligned, and variables in the small data area. FIXME -- at some we
4206 should recognize other globals and statics. We can't assume that any old
4207 pointer is aligned, given that arguments could be passed on an odd word on
4208 the stack and the address taken and passed through to another function. */
4211 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4219 if (GET_CODE (op) != MEM)
4222 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4225 addr = XEXP (op, 0);
4226 if (GET_CODE (addr) == REG)
4229 else if (GET_CODE (addr) == PLUS)
4231 rtx addr0 = XEXP (addr, 0);
4232 rtx addr1 = XEXP (addr, 1);
4234 if (GET_CODE (addr0) != REG)
4237 if (got12_operand (addr1, VOIDmode))
4240 if (GET_CODE (addr1) != CONST_INT)
4243 if ((INTVAL (addr1) & 7) != 0)
4252 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4258 /* Return true if operand is a 2 word memory address that needs to
4259 use two instructions to load or store. */
4262 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4264 if (GET_CODE (op) != MEM)
4267 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4273 return ! dbl_memory_one_insn_operand (op, mode);
4276 /* Return true if operand is something that can be an output for a move
4280 move_destination_operand (rtx op, enum machine_mode mode)
4285 switch (GET_CODE (op))
4291 if (GET_MODE (op) != mode && mode != VOIDmode)
4294 subreg = SUBREG_REG (op);
4295 code = GET_CODE (subreg);
4297 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4298 reload_completed, FALSE, FALSE);
4300 return (code == REG);
4303 if (GET_MODE (op) != mode && mode != VOIDmode)
4309 return frv_legitimate_memory_operand (op, mode, FALSE);
4315 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4316 process these separately from any offsets, such that we add any
4317 offsets to the function descriptor (the actual pointer), not to the
4318 function address. */
4321 frv_function_symbol_referenced_p (rtx x)
4327 if (GET_CODE (x) == SYMBOL_REF)
4328 return SYMBOL_REF_FUNCTION_P (x);
4330 length = GET_RTX_LENGTH (GET_CODE (x));
4331 format = GET_RTX_FORMAT (GET_CODE (x));
4333 for (j = 0; j < length; ++j)
4338 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4344 if (XVEC (x, j) != 0)
4347 for (k = 0; k < XVECLEN (x, j); ++k)
4348 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4354 /* Nothing to do. */
4362 /* Return true if operand is something that can be an input for a move
4366 move_source_operand (rtx op, enum machine_mode mode)
4371 switch (GET_CODE (op))
4378 return immediate_operand (op, mode);
4381 if (GET_MODE (op) != mode && mode != VOIDmode)
4384 subreg = SUBREG_REG (op);
4385 code = GET_CODE (subreg);
4387 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4388 reload_completed, FALSE, FALSE);
4390 return (code == REG);
4393 if (GET_MODE (op) != mode && mode != VOIDmode)
4399 return frv_legitimate_memory_operand (op, mode, FALSE);
4405 /* Return true if operand is something that can be an output for a conditional
4409 condexec_dest_operand (rtx op, enum machine_mode mode)
4414 switch (GET_CODE (op))
4420 if (GET_MODE (op) != mode && mode != VOIDmode)
4423 subreg = SUBREG_REG (op);
4424 code = GET_CODE (subreg);
4426 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4427 reload_completed, TRUE, FALSE);
4429 return (code == REG);
4432 if (GET_MODE (op) != mode && mode != VOIDmode)
4438 return frv_legitimate_memory_operand (op, mode, TRUE);
4444 /* Return true if operand is something that can be an input for a conditional
4448 condexec_source_operand (rtx op, enum machine_mode mode)
4453 switch (GET_CODE (op))
4463 if (GET_MODE (op) != mode && mode != VOIDmode)
4466 subreg = SUBREG_REG (op);
4467 code = GET_CODE (subreg);
4469 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4470 reload_completed, TRUE, FALSE);
4472 return (code == REG);
4475 if (GET_MODE (op) != mode && mode != VOIDmode)
4481 return frv_legitimate_memory_operand (op, mode, TRUE);
4487 /* Return true if operand is a register of any flavor or a 0 of the
4488 appropriate type. */
4491 reg_or_0_operand (rtx op, enum machine_mode mode)
4493 switch (GET_CODE (op))
4500 if (GET_MODE (op) != mode && mode != VOIDmode)
4503 return register_operand (op, mode);
4513 /* Return true if operand is the link register. */
4516 lr_operand (rtx op, enum machine_mode mode)
4518 if (GET_CODE (op) != REG)
4521 if (GET_MODE (op) != mode && mode != VOIDmode)
4524 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4530 /* Return true if operand is the uClinux PIC register. */
4533 fdpic_operand (rtx op, enum machine_mode mode)
4538 if (GET_CODE (op) != REG)
4541 if (GET_MODE (op) != mode && mode != VOIDmode)
4544 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4551 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4553 struct frv_unspec unspec;
4555 if (frv_const_unspec_p (op, &unspec))
4556 switch (unspec.reloc)
4559 case R_FRV_GOTOFF12:
4560 case R_FRV_FUNCDESC_GOT12:
4561 case R_FRV_FUNCDESC_GOTOFF12:
4568 /* Return true if OP is a valid const-unspec expression. */
4571 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4573 struct frv_unspec unspec;
4575 return frv_const_unspec_p (op, &unspec);
4577 /* Return true if operand is a gpr register or a valid memory operation. */
4580 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4582 return (integer_register_operand (op, mode)
4583 || frv_legitimate_memory_operand (op, mode, FALSE));
4586 /* Return true if operand is a fpr register or a valid memory operation. */
4589 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4591 return (fpr_operand (op, mode)
4592 || frv_legitimate_memory_operand (op, mode, FALSE));
4595 /* Return true if operand is an icc register. */
4598 icc_operand (rtx op, enum machine_mode mode)
4602 if (GET_MODE (op) != mode && mode != VOIDmode)
4605 if (GET_CODE (op) != REG)
4609 return ICC_OR_PSEUDO_P (regno);
4612 /* Return true if operand is an fcc register. */
4615 fcc_operand (rtx op, enum machine_mode mode)
4619 if (GET_MODE (op) != mode && mode != VOIDmode)
4622 if (GET_CODE (op) != REG)
4626 return FCC_OR_PSEUDO_P (regno);
4629 /* Return true if operand is either an fcc or icc register. */
4632 cc_operand (rtx op, enum machine_mode mode)
4636 if (GET_MODE (op) != mode && mode != VOIDmode)
4639 if (GET_CODE (op) != REG)
4643 if (CC_OR_PSEUDO_P (regno))
4649 /* Return true if operand is an integer CCR register. */
4652 icr_operand (rtx op, enum machine_mode mode)
4656 if (GET_MODE (op) != mode && mode != VOIDmode)
4659 if (GET_CODE (op) != REG)
4663 return ICR_OR_PSEUDO_P (regno);
4666 /* Return true if operand is an fcc register. */
4669 fcr_operand (rtx op, enum machine_mode mode)
4673 if (GET_MODE (op) != mode && mode != VOIDmode)
4676 if (GET_CODE (op) != REG)
4680 return FCR_OR_PSEUDO_P (regno);
4683 /* Return true if operand is either an fcc or icc register. */
4686 cr_operand (rtx op, enum machine_mode mode)
4690 if (GET_MODE (op) != mode && mode != VOIDmode)
4693 if (GET_CODE (op) != REG)
4697 if (CR_OR_PSEUDO_P (regno))
4703 /* Return true if operand is a memory reference suitable for a call. */
4706 call_operand (rtx op, enum machine_mode mode)
4708 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4711 if (GET_CODE (op) == SYMBOL_REF)
4714 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4715 never occur anyway), but prevents reload from not handling the case
4716 properly of a call through a pointer on a function that calls
4717 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4718 return gpr_or_int12_operand (op, mode);
4721 /* Return true if operand is a memory reference suitable for a sibcall. */
4724 sibcall_operand (rtx op, enum machine_mode mode)
4726 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4729 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4730 never occur anyway), but prevents reload from not handling the case
4731 properly of a call through a pointer on a function that calls
4732 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4733 return gpr_or_int12_operand (op, mode);
4736 /* Return true if operator is a kind of relational operator. */
4739 relational_operator (rtx op, enum machine_mode mode)
4745 if (mode != VOIDmode && mode != GET_MODE (op))
4748 switch (GET_CODE (op))
4767 if (op1 != const0_rtx)
4771 if (GET_CODE (op0) != REG)
4774 regno = REGNO (op0);
4775 switch (GET_MODE (op0))
4782 return ICC_OR_PSEUDO_P (regno);
4785 return FCC_OR_PSEUDO_P (regno);
4788 return CR_OR_PSEUDO_P (regno);
4794 /* Return true if operator is a signed integer relational operator. */
4797 signed_relational_operator (rtx op, enum machine_mode mode)
4803 if (mode != VOIDmode && mode != GET_MODE (op))
4806 switch (GET_CODE (op))
4821 if (op1 != const0_rtx)
4825 if (GET_CODE (op0) != REG)
4828 regno = REGNO (op0);
4829 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4832 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4838 /* Return true if operator is a signed integer relational operator. */
4841 unsigned_relational_operator (rtx op, enum machine_mode mode)
4847 if (mode != VOIDmode && mode != GET_MODE (op))
4850 switch (GET_CODE (op))
4863 if (op1 != const0_rtx)
4867 if (GET_CODE (op0) != REG)
4870 regno = REGNO (op0);
4871 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4874 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4880 /* Return true if operator is a floating point relational operator. */
4883 float_relational_operator (rtx op, enum machine_mode mode)
4889 if (mode != VOIDmode && mode != GET_MODE (op))
4892 switch (GET_CODE (op))
4911 if (op1 != const0_rtx)
4915 if (GET_CODE (op0) != REG)
4918 regno = REGNO (op0);
4919 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4922 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4928 /* Return true if operator is EQ/NE of a conditional execution register. */
4931 ccr_eqne_operator (rtx op, enum machine_mode mode)
4933 enum machine_mode op_mode = GET_MODE (op);
4938 if (mode != VOIDmode && op_mode != mode)
4941 switch (GET_CODE (op))
4952 if (op1 != const0_rtx)
4956 if (GET_CODE (op0) != REG)
4959 regno = REGNO (op0);
4960 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4966 /* Return true if operator is a minimum or maximum operator (both signed and
4970 minmax_operator (rtx op, enum machine_mode mode)
4972 if (mode != VOIDmode && mode != GET_MODE (op))
4975 switch (GET_CODE (op))
4987 if (! integer_register_operand (XEXP (op, 0), mode))
4990 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
4996 /* Return true if operator is an integer binary operator that can executed
4997 conditionally and takes 1 cycle. */
5000 condexec_si_binary_operator (rtx op, enum machine_mode mode)
5002 enum machine_mode op_mode = GET_MODE (op);
5004 if (mode != VOIDmode && op_mode != mode)
5007 switch (GET_CODE (op))
5024 /* Return true if operator is an integer binary operator that can be
5025 executed conditionally by a media instruction. */
5028 condexec_si_media_operator (rtx op, enum machine_mode mode)
5030 enum machine_mode op_mode = GET_MODE (op);
5032 if (mode != VOIDmode && op_mode != mode)
5035 switch (GET_CODE (op))
5047 /* Return true if operator is an integer division operator that can executed
5051 condexec_si_divide_operator (rtx op, enum machine_mode mode)
5053 enum machine_mode op_mode = GET_MODE (op);
5055 if (mode != VOIDmode && op_mode != mode)
5058 switch (GET_CODE (op))
5069 /* Return true if operator is an integer unary operator that can executed
5073 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5075 enum machine_mode op_mode = GET_MODE (op);
5077 if (mode != VOIDmode && op_mode != mode)
5080 switch (GET_CODE (op))
5091 /* Return true if operator is a conversion-type expression that can be
5092 evaluated conditionally by floating-point instructions. */
5095 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5097 enum machine_mode op_mode = GET_MODE (op);
5099 if (mode != VOIDmode && op_mode != mode)
5102 switch (GET_CODE (op))
5113 /* Return true if operator is an addition or subtraction expression.
5114 Such expressions can be evaluated conditionally by floating-point
5118 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5120 enum machine_mode op_mode = GET_MODE (op);
5122 if (mode != VOIDmode && op_mode != mode)
5125 switch (GET_CODE (op))
5136 /* Return true if the memory operand is one that can be conditionally
5140 condexec_memory_operand (rtx op, enum machine_mode mode)
5142 enum machine_mode op_mode = GET_MODE (op);
5145 if (mode != VOIDmode && op_mode != mode)
5160 if (GET_CODE (op) != MEM)
5163 addr = XEXP (op, 0);
5164 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5167 /* Return true if operator is an integer binary operator that can be combined
5168 with a setcc operation. Do not allow the arithmetic operations that could
5169 potentially overflow since the FR-V sets the condition code based on the
5170 "true" value of the result, not the result after truncating to a 32-bit
5174 intop_compare_operator (rtx op, enum machine_mode mode)
5176 enum machine_mode op_mode = GET_MODE (op);
5178 if (mode != VOIDmode && op_mode != mode)
5181 switch (GET_CODE (op))
5194 if (! integer_register_operand (XEXP (op, 0), SImode))
5197 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5203 /* Return true if operator is an integer binary operator that can be combined
5204 with a setcc operation inside of a conditional execution. */
5207 condexec_intop_cmp_operator (rtx op, enum machine_mode mode)
5209 enum machine_mode op_mode = GET_MODE (op);
5211 if (mode != VOIDmode && op_mode != mode)
5214 switch (GET_CODE (op))
5227 if (! integer_register_operand (XEXP (op, 0), SImode))
5230 if (! integer_register_operand (XEXP (op, 1), SImode))
5236 /* Return 1 if operand is a valid ACC register number. */
5239 acc_operand (rtx op, enum machine_mode mode)
5243 if (GET_MODE (op) != mode && mode != VOIDmode)
5246 if (GET_CODE (op) == SUBREG)
5248 if (GET_CODE (SUBREG_REG (op)) != REG)
5249 return register_operand (op, mode);
5251 op = SUBREG_REG (op);
5254 if (GET_CODE (op) != REG)
5258 return ACC_OR_PSEUDO_P (regno);
5261 /* Return 1 if operand is a valid even ACC register number. */
5264 even_acc_operand (rtx op, enum machine_mode mode)
5268 if (GET_MODE (op) != mode && mode != VOIDmode)
5271 if (GET_CODE (op) == SUBREG)
5273 if (GET_CODE (SUBREG_REG (op)) != REG)
5274 return register_operand (op, mode);
5276 op = SUBREG_REG (op);
5279 if (GET_CODE (op) != REG)
5283 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5286 /* Return 1 if operand is zero or four. */
5289 quad_acc_operand (rtx op, enum machine_mode mode)
5293 if (GET_MODE (op) != mode && mode != VOIDmode)
5296 if (GET_CODE (op) == SUBREG)
5298 if (GET_CODE (SUBREG_REG (op)) != REG)
5299 return register_operand (op, mode);
5301 op = SUBREG_REG (op);
5304 if (GET_CODE (op) != REG)
5308 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5311 /* Return 1 if operand is a valid ACCG register number. */
5314 accg_operand (rtx op, enum machine_mode mode)
5316 if (GET_MODE (op) != mode && mode != VOIDmode)
5319 if (GET_CODE (op) == SUBREG)
5321 if (GET_CODE (SUBREG_REG (op)) != REG)
5322 return register_operand (op, mode);
5324 op = SUBREG_REG (op);
5327 if (GET_CODE (op) != REG)
5330 return ACCG_OR_PSEUDO_P (REGNO (op));
5334 /* Return true if the bare return instruction can be used outside of the
5335 epilog code. For frv, we only do it if there was no stack allocation. */
5338 direct_return_p (void)
5342 if (!reload_completed)
5345 info = frv_stack_info ();
5346 return (info->total_size == 0);
5350 /* Emit code to handle a MOVSI, adding in the small data register or pic
5351 register if needed to load up addresses. Return TRUE if the appropriate
5352 instructions are emitted. */
5355 frv_emit_movsi (rtx dest, rtx src)
5357 int base_regno = -1;
5360 struct frv_unspec old_unspec;
5362 if (!reload_in_progress
5363 && !reload_completed
5364 && !register_operand (dest, SImode)
5365 && (!reg_or_0_operand (src, SImode)
5366 /* Virtual registers will almost always be replaced by an
5367 add instruction, so expose this to CSE by copying to
5368 an intermediate register. */
5369 || (GET_CODE (src) == REG
5370 && IN_RANGE_P (REGNO (src),
5371 FIRST_VIRTUAL_REGISTER,
5372 LAST_VIRTUAL_REGISTER))))
5374 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5378 /* Explicitly add in the PIC or small data register if needed. */
5379 switch (GET_CODE (src))
5388 /* Using GPREL12, we use a single GOT entry for all symbols
5389 in read-only sections, but trade sequences such as:
5391 sethi #gothi(label), gr#
5392 setlo #gotlo(label), gr#
5397 ld @(gr15,#got12(_gp)), gr#
5398 sethi #gprelhi(label), gr##
5399 setlo #gprello(label), gr##
5402 We may often be able to share gr# for multiple
5403 computations of GPREL addresses, and we may often fold
5404 the final add into the pair of registers of a load or
5405 store instruction, so it's often profitable. Even when
5406 optimizing for size, we're trading a GOT entry for an
5407 additional instruction, which trades GOT space
5408 (read-write) for code size (read-only, shareable), as
5409 long as the symbol is not used in more than two different
5412 With -fpie/-fpic, we'd be trading a single load for a
5413 sequence of 4 instructions, because the offset of the
5414 label can't be assumed to be addressable with 12 bits, so
5415 we don't do this. */
5416 if (TARGET_GPREL_RO)
5417 unspec = R_FRV_GPREL12;
5419 unspec = R_FRV_GOT12;
5422 base_regno = PIC_REGNO;
5427 if (frv_const_unspec_p (src, &old_unspec))
5430 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5433 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5434 emit_move_insn (dest, src);
5439 sym = XEXP (sym, 0);
5440 if (GET_CODE (sym) == PLUS
5441 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5442 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5443 sym = XEXP (sym, 0);
5444 if (GET_CODE (sym) == SYMBOL_REF)
5446 else if (GET_CODE (sym) == LABEL_REF)
5449 goto handle_whatever;
5457 if (SYMBOL_REF_FUNCTION_P (sym))
5459 if (frv_local_funcdesc_p (sym))
5460 unspec = R_FRV_FUNCDESC_GOTOFF12;
5462 unspec = R_FRV_FUNCDESC_GOT12;
5466 if (CONSTANT_POOL_ADDRESS_P (sym))
5467 switch (GET_CODE (get_pool_constant (sym)))
5474 unspec = R_FRV_GOTOFF12;
5479 if (TARGET_GPREL_RO)
5480 unspec = R_FRV_GPREL12;
5482 unspec = R_FRV_GOT12;
5485 else if (SYMBOL_REF_LOCAL_P (sym)
5486 && !SYMBOL_REF_EXTERNAL_P (sym)
5487 && SYMBOL_REF_DECL (sym)
5488 && (!DECL_P (SYMBOL_REF_DECL (sym))
5489 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5491 tree decl = SYMBOL_REF_DECL (sym);
5492 tree init = TREE_CODE (decl) == VAR_DECL
5493 ? DECL_INITIAL (decl)
5494 : TREE_CODE (decl) == CONSTRUCTOR
5497 bool named_section, readonly;
5499 if (init && init != error_mark_node)
5500 reloc = compute_reloc_for_constant (init);
5502 named_section = TREE_CODE (decl) == VAR_DECL
5503 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5504 readonly = decl_readonly_section (decl, reloc);
5507 unspec = R_FRV_GOT12;
5509 unspec = R_FRV_GOTOFF12;
5510 else if (readonly && TARGET_GPREL_RO)
5511 unspec = R_FRV_GPREL12;
5513 unspec = R_FRV_GOT12;
5516 unspec = R_FRV_GOT12;
5520 else if (SYMBOL_REF_SMALL_P (sym))
5521 base_regno = SDA_BASE_REG;
5524 base_regno = PIC_REGNO;
5529 if (base_regno >= 0)
5531 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5532 emit_insn (gen_symGOTOFF2reg (dest, src,
5533 gen_rtx_REG (Pmode, base_regno),
5534 GEN_INT (R_FRV_GPREL12)));
5536 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5537 gen_rtx_REG (Pmode, base_regno),
5538 GEN_INT (R_FRV_GPREL12)));
5539 if (base_regno == PIC_REGNO)
5540 cfun->uses_pic_offset_table = TRUE;
5548 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5549 new uses of it once reload has begun. */
5550 if (reload_in_progress || reload_completed)
5555 case R_FRV_GOTOFF12:
5556 if (!frv_small_data_reloc_p (sym, unspec))
5557 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5560 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5563 if (!frv_small_data_reloc_p (sym, unspec))
5564 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5567 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5569 case R_FRV_FUNCDESC_GOTOFF12:
5571 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5574 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5578 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5581 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5585 cfun->uses_pic_offset_table = TRUE;
5594 /* Return a string to output a single word move. */
5597 output_move_single (rtx operands[], rtx insn)
5599 rtx dest = operands[0];
5600 rtx src = operands[1];
5602 if (GET_CODE (dest) == REG)
5604 int dest_regno = REGNO (dest);
5605 enum machine_mode mode = GET_MODE (dest);
5607 if (GPR_P (dest_regno))
5609 if (GET_CODE (src) == REG)
5611 /* gpr <- some sort of register */
5612 int src_regno = REGNO (src);
5614 if (GPR_P (src_regno))
5615 return "mov %1, %0";
5617 else if (FPR_P (src_regno))
5618 return "movfg %1, %0";
5620 else if (SPR_P (src_regno))
5621 return "movsg %1, %0";
5624 else if (GET_CODE (src) == MEM)
5633 return "ldsb%I1%U1 %M1,%0";
5636 return "ldsh%I1%U1 %M1,%0";
5640 return "ld%I1%U1 %M1, %0";
5644 else if (GET_CODE (src) == CONST_INT
5645 || GET_CODE (src) == CONST_DOUBLE)
5647 /* gpr <- integer/floating constant */
5648 HOST_WIDE_INT value;
5650 if (GET_CODE (src) == CONST_INT)
5651 value = INTVAL (src);
5653 else if (mode == SFmode)
5658 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5659 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5664 value = CONST_DOUBLE_LOW (src);
5666 if (IN_RANGE_P (value, -32768, 32767))
5667 return "setlos %1, %0";
5672 else if (GET_CODE (src) == SYMBOL_REF
5673 || GET_CODE (src) == LABEL_REF
5674 || GET_CODE (src) == CONST)
5680 else if (FPR_P (dest_regno))
5682 if (GET_CODE (src) == REG)
5684 /* fpr <- some sort of register */
5685 int src_regno = REGNO (src);
5687 if (GPR_P (src_regno))
5688 return "movgf %1, %0";
5690 else if (FPR_P (src_regno))
5692 if (TARGET_HARD_FLOAT)
5693 return "fmovs %1, %0";
5695 return "mor %1, %1, %0";
5699 else if (GET_CODE (src) == MEM)
5708 return "ldbf%I1%U1 %M1,%0";
5711 return "ldhf%I1%U1 %M1,%0";
5715 return "ldf%I1%U1 %M1, %0";
5719 else if (ZERO_P (src))
5720 return "movgf %., %0";
5723 else if (SPR_P (dest_regno))
5725 if (GET_CODE (src) == REG)
5727 /* spr <- some sort of register */
5728 int src_regno = REGNO (src);
5730 if (GPR_P (src_regno))
5731 return "movgs %1, %0";
5736 else if (GET_CODE (dest) == MEM)
5738 if (GET_CODE (src) == REG)
5740 int src_regno = REGNO (src);
5741 enum machine_mode mode = GET_MODE (dest);
5743 if (GPR_P (src_regno))
5751 return "stb%I0%U0 %1, %M0";
5754 return "sth%I0%U0 %1, %M0";
5758 return "st%I0%U0 %1, %M0";
5762 else if (FPR_P (src_regno))
5770 return "stbf%I0%U0 %1, %M0";
5773 return "sthf%I0%U0 %1, %M0";
5777 return "stf%I0%U0 %1, %M0";
5782 else if (ZERO_P (src))
5784 switch (GET_MODE (dest))
5790 return "stb%I0%U0 %., %M0";
5793 return "sth%I0%U0 %., %M0";
5797 return "st%I0%U0 %., %M0";
5802 fatal_insn ("Bad output_move_single operand", insn);
5807 /* Return a string to output a double word move. */
5810 output_move_double (rtx operands[], rtx insn)
5812 rtx dest = operands[0];
5813 rtx src = operands[1];
5814 enum machine_mode mode = GET_MODE (dest);
5816 if (GET_CODE (dest) == REG)
5818 int dest_regno = REGNO (dest);
5820 if (GPR_P (dest_regno))
5822 if (GET_CODE (src) == REG)
5824 /* gpr <- some sort of register */
5825 int src_regno = REGNO (src);
5827 if (GPR_P (src_regno))
5830 else if (FPR_P (src_regno))
5832 if (((dest_regno - GPR_FIRST) & 1) == 0
5833 && ((src_regno - FPR_FIRST) & 1) == 0)
5834 return "movfgd %1, %0";
5840 else if (GET_CODE (src) == MEM)
5843 if (dbl_memory_one_insn_operand (src, mode))
5844 return "ldd%I1%U1 %M1, %0";
5849 else if (GET_CODE (src) == CONST_INT
5850 || GET_CODE (src) == CONST_DOUBLE)
5854 else if (FPR_P (dest_regno))
5856 if (GET_CODE (src) == REG)
5858 /* fpr <- some sort of register */
5859 int src_regno = REGNO (src);
5861 if (GPR_P (src_regno))
5863 if (((dest_regno - FPR_FIRST) & 1) == 0
5864 && ((src_regno - GPR_FIRST) & 1) == 0)
5865 return "movgfd %1, %0";
5870 else if (FPR_P (src_regno))
5873 && ((dest_regno - FPR_FIRST) & 1) == 0
5874 && ((src_regno - FPR_FIRST) & 1) == 0)
5875 return "fmovd %1, %0";
5881 else if (GET_CODE (src) == MEM)
5884 if (dbl_memory_one_insn_operand (src, mode))
5885 return "lddf%I1%U1 %M1, %0";
5890 else if (ZERO_P (src))
5895 else if (GET_CODE (dest) == MEM)
5897 if (GET_CODE (src) == REG)
5899 int src_regno = REGNO (src);
5901 if (GPR_P (src_regno))
5903 if (((src_regno - GPR_FIRST) & 1) == 0
5904 && dbl_memory_one_insn_operand (dest, mode))
5905 return "std%I0%U0 %1, %M0";
5910 if (FPR_P (src_regno))
5912 if (((src_regno - FPR_FIRST) & 1) == 0
5913 && dbl_memory_one_insn_operand (dest, mode))
5914 return "stdf%I0%U0 %1, %M0";
5920 else if (ZERO_P (src))
5922 if (dbl_memory_one_insn_operand (dest, mode))
5923 return "std%I0%U0 %., %M0";
5929 fatal_insn ("Bad output_move_double operand", insn);
5934 /* Return a string to output a single word conditional move.
5935 Operand0 -- EQ/NE of ccr register and 0
5936 Operand1 -- CCR register
5937 Operand2 -- destination
5938 Operand3 -- source */
5941 output_condmove_single (rtx operands[], rtx insn)
5943 rtx dest = operands[2];
5944 rtx src = operands[3];
5946 if (GET_CODE (dest) == REG)
5948 int dest_regno = REGNO (dest);
5949 enum machine_mode mode = GET_MODE (dest);
5951 if (GPR_P (dest_regno))
5953 if (GET_CODE (src) == REG)
5955 /* gpr <- some sort of register */
5956 int src_regno = REGNO (src);
5958 if (GPR_P (src_regno))
5959 return "cmov %z3, %2, %1, %e0";
5961 else if (FPR_P (src_regno))
5962 return "cmovfg %3, %2, %1, %e0";
5965 else if (GET_CODE (src) == MEM)
5974 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5977 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5981 return "cld%I3%U3 %M3, %2, %1, %e0";
5985 else if (ZERO_P (src))
5986 return "cmov %., %2, %1, %e0";
5989 else if (FPR_P (dest_regno))
5991 if (GET_CODE (src) == REG)
5993 /* fpr <- some sort of register */
5994 int src_regno = REGNO (src);
5996 if (GPR_P (src_regno))
5997 return "cmovgf %3, %2, %1, %e0";
5999 else if (FPR_P (src_regno))
6001 if (TARGET_HARD_FLOAT)
6002 return "cfmovs %3,%2,%1,%e0";
6004 return "cmor %3, %3, %2, %1, %e0";
6008 else if (GET_CODE (src) == MEM)
6011 if (mode == SImode || mode == SFmode)
6012 return "cldf%I3%U3 %M3, %2, %1, %e0";
6015 else if (ZERO_P (src))
6016 return "cmovgf %., %2, %1, %e0";
6020 else if (GET_CODE (dest) == MEM)
6022 if (GET_CODE (src) == REG)
6024 int src_regno = REGNO (src);
6025 enum machine_mode mode = GET_MODE (dest);
6027 if (GPR_P (src_regno))
6035 return "cstb%I2%U2 %3, %M2, %1, %e0";
6038 return "csth%I2%U2 %3, %M2, %1, %e0";
6042 return "cst%I2%U2 %3, %M2, %1, %e0";
6046 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
6047 return "cstf%I2%U2 %3, %M2, %1, %e0";
6050 else if (ZERO_P (src))
6052 enum machine_mode mode = GET_MODE (dest);
6059 return "cstb%I2%U2 %., %M2, %1, %e0";
6062 return "csth%I2%U2 %., %M2, %1, %e0";
6066 return "cst%I2%U2 %., %M2, %1, %e0";
6071 fatal_insn ("Bad output_condmove_single operand", insn);
6076 /* Emit the appropriate code to do a comparison, returning the register the
6077 comparison was done it. */
6080 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
6082 enum machine_mode cc_mode;
6085 /* Floating point doesn't have comparison against a constant. */
6086 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6087 op1 = force_reg (GET_MODE (op0), op1);
6089 /* Possibly disable using anything but a fixed register in order to work
6090 around cse moving comparisons past function calls. */
6091 cc_mode = SELECT_CC_MODE (test, op0, op1);
6092 cc_reg = ((TARGET_ALLOC_CC)
6093 ? gen_reg_rtx (cc_mode)
6094 : gen_rtx_REG (cc_mode,
6095 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6097 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6098 gen_rtx_COMPARE (cc_mode, op0, op1)));
6104 /* Emit code for a conditional branch. The comparison operands were previously
6105 stored in frv_compare_op0 and frv_compare_op1.
6107 XXX: I originally wanted to add a clobber of a CCR register to use in
6108 conditional execution, but that confuses the rest of the compiler. */
6111 frv_emit_cond_branch (enum rtx_code test, rtx label)
6116 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6117 enum machine_mode cc_mode = GET_MODE (cc_reg);
6119 /* Branches generate:
6121 (if_then_else (<test>, <cc_reg>, (const_int 0))
6122 (label_ref <branch_label>)
6124 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6125 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6126 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6127 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6132 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6133 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6136 frv_emit_scc (enum rtx_code test, rtx target)
6142 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6144 /* SCC instructions generate:
6145 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6146 (clobber (<ccr_reg>))]) */
6147 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6148 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6150 cr_reg = ((TARGET_ALLOC_CC)
6151 ? gen_reg_rtx (CC_CCRmode)
6152 : gen_rtx_REG (CC_CCRmode,
6153 ((GET_MODE (cc_reg) == CC_FPmode)
6157 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6158 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6163 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6164 the separate insns. */
6167 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6173 /* Set the appropriate CCR bit. */
6174 emit_insn (gen_rtx_SET (VOIDmode,
6176 gen_rtx_fmt_ee (GET_CODE (test),
6181 /* Move the value into the destination. */
6182 emit_move_insn (dest, GEN_INT (value));
6184 /* Move 0 into the destination if the test failed */
6185 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6186 gen_rtx_EQ (GET_MODE (cr_reg),
6189 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6191 /* Finish up, return sequence. */
6198 /* Emit the code for a conditional move, return TRUE if we could do the
6202 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6209 enum rtx_code test = GET_CODE (test_rtx);
6210 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6211 enum machine_mode cc_mode = GET_MODE (cc_reg);
6213 /* Conditional move instructions generate:
6214 (parallel [(set <target>
6215 (if_then_else (<test> <cc_reg> (const_int 0))
6218 (clobber (<ccr_reg>))]) */
6220 /* Handle various cases of conditional move involving two constants. */
6221 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6223 HOST_WIDE_INT value1 = INTVAL (src1);
6224 HOST_WIDE_INT value2 = INTVAL (src2);
6226 /* Having 0 as one of the constants can be done by loading the other
6227 constant, and optionally moving in gr0. */
6228 if (value1 == 0 || value2 == 0)
6231 /* If the first value is within an addi range and also the difference
6232 between the two fits in an addi's range, load up the difference, then
6233 conditionally move in 0, and then unconditionally add the first
6235 else if (IN_RANGE_P (value1, -2048, 2047)
6236 && IN_RANGE_P (value2 - value1, -2048, 2047))
6239 /* If neither condition holds, just force the constant into a
6243 src1 = force_reg (GET_MODE (dest), src1);
6244 src2 = force_reg (GET_MODE (dest), src2);
6248 /* If one value is a register, insure the other value is either 0 or a
6252 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6253 src1 = force_reg (GET_MODE (dest), src1);
6255 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6256 src2 = force_reg (GET_MODE (dest), src2);
6259 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6260 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6262 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6264 cr_reg = ((TARGET_ALLOC_CC)
6265 ? gen_reg_rtx (CC_CCRmode)
6266 : gen_rtx_REG (CC_CCRmode,
6267 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6269 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6270 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6275 /* Split a conditional move into constituent parts, returning a SEQUENCE
6276 containing all of the insns. */
6279 frv_split_cond_move (rtx operands[])
6281 rtx dest = operands[0];
6282 rtx test = operands[1];
6283 rtx cc_reg = operands[2];
6284 rtx src1 = operands[3];
6285 rtx src2 = operands[4];
6286 rtx cr_reg = operands[5];
6288 enum machine_mode cr_mode = GET_MODE (cr_reg);
6292 /* Set the appropriate CCR bit. */
6293 emit_insn (gen_rtx_SET (VOIDmode,
6295 gen_rtx_fmt_ee (GET_CODE (test),
6300 /* Handle various cases of conditional move involving two constants. */
6301 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6303 HOST_WIDE_INT value1 = INTVAL (src1);
6304 HOST_WIDE_INT value2 = INTVAL (src2);
6306 /* Having 0 as one of the constants can be done by loading the other
6307 constant, and optionally moving in gr0. */
6310 emit_move_insn (dest, src2);
6311 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6312 gen_rtx_NE (cr_mode, cr_reg,
6314 gen_rtx_SET (VOIDmode, dest, src1)));
6317 else if (value2 == 0)
6319 emit_move_insn (dest, src1);
6320 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6321 gen_rtx_EQ (cr_mode, cr_reg,
6323 gen_rtx_SET (VOIDmode, dest, src2)));
6326 /* If the first value is within an addi range and also the difference
6327 between the two fits in an addi's range, load up the difference, then
6328 conditionally move in 0, and then unconditionally add the first
6330 else if (IN_RANGE_P (value1, -2048, 2047)
6331 && IN_RANGE_P (value2 - value1, -2048, 2047))
6333 rtx dest_si = ((GET_MODE (dest) == SImode)
6335 : gen_rtx_SUBREG (SImode, dest, 0));
6337 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6338 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6339 gen_rtx_NE (cr_mode, cr_reg,
6341 gen_rtx_SET (VOIDmode, dest_si,
6343 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6351 /* Emit the conditional move for the test being true if needed. */
6352 if (! rtx_equal_p (dest, src1))
6353 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6354 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6355 gen_rtx_SET (VOIDmode, dest, src1)));
6357 /* Emit the conditional move for the test being false if needed. */
6358 if (! rtx_equal_p (dest, src2))
6359 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6360 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6361 gen_rtx_SET (VOIDmode, dest, src2)));
6364 /* Finish up, return sequence. */
6371 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6372 memory location that is not known to be dword-aligned. */
6374 frv_split_double_load (rtx dest, rtx source)
6376 int regno = REGNO (dest);
6377 rtx dest1 = gen_highpart (SImode, dest);
6378 rtx dest2 = gen_lowpart (SImode, dest);
6379 rtx address = XEXP (source, 0);
6381 /* If the address is pre-modified, load the lower-numbered register
6382 first, then load the other register using an integer offset from
6383 the modified base register. This order should always be safe,
6384 since the pre-modification cannot affect the same registers as the
6387 The situation for other loads is more complicated. Loading one
6388 of the registers could affect the value of ADDRESS, so we must
6389 be careful which order we do them in. */
6390 if (GET_CODE (address) == PRE_MODIFY
6391 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6393 /* It is safe to load the lower-numbered register first. */
6394 emit_move_insn (dest1, change_address (source, SImode, NULL));
6395 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6399 /* ADDRESS is not pre-modified and the address depends on the
6400 lower-numbered register. Load the higher-numbered register
6402 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6403 emit_move_insn (dest1, change_address (source, SImode, NULL));
6407 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6408 and SOURCE is either a double register or the constant zero. */
6410 frv_split_double_store (rtx dest, rtx source)
6412 rtx dest1 = change_address (dest, SImode, NULL);
6413 rtx dest2 = frv_index_memory (dest, SImode, 1);
6414 if (ZERO_P (source))
6416 emit_move_insn (dest1, CONST0_RTX (SImode));
6417 emit_move_insn (dest2, CONST0_RTX (SImode));
6421 emit_move_insn (dest1, gen_highpart (SImode, source));
6422 emit_move_insn (dest2, gen_lowpart (SImode, source));
6427 /* Split a min/max operation returning a SEQUENCE containing all of the
6431 frv_split_minmax (rtx operands[])
6433 rtx dest = operands[0];
6434 rtx minmax = operands[1];
6435 rtx src1 = operands[2];
6436 rtx src2 = operands[3];
6437 rtx cc_reg = operands[4];
6438 rtx cr_reg = operands[5];
6440 enum rtx_code test_code;
6441 enum machine_mode cr_mode = GET_MODE (cr_reg);
6445 /* Figure out which test to use. */
6446 switch (GET_CODE (minmax))
6451 case SMIN: test_code = LT; break;
6452 case SMAX: test_code = GT; break;
6453 case UMIN: test_code = LTU; break;
6454 case UMAX: test_code = GTU; break;
6457 /* Issue the compare instruction. */
6458 emit_insn (gen_rtx_SET (VOIDmode,
6460 gen_rtx_COMPARE (GET_MODE (cc_reg),
6463 /* Set the appropriate CCR bit. */
6464 emit_insn (gen_rtx_SET (VOIDmode,
6466 gen_rtx_fmt_ee (test_code,
6471 /* If are taking the min/max of a nonzero constant, load that first, and
6472 then do a conditional move of the other value. */
6473 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6475 if (rtx_equal_p (dest, src1))
6478 emit_move_insn (dest, src2);
6479 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6480 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6481 gen_rtx_SET (VOIDmode, dest, src1)));
6484 /* Otherwise, do each half of the move. */
6487 /* Emit the conditional move for the test being true if needed. */
6488 if (! rtx_equal_p (dest, src1))
6489 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6490 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6491 gen_rtx_SET (VOIDmode, dest, src1)));
6493 /* Emit the conditional move for the test being false if needed. */
6494 if (! rtx_equal_p (dest, src2))
6495 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6496 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6497 gen_rtx_SET (VOIDmode, dest, src2)));
6500 /* Finish up, return sequence. */
6507 /* Split an integer abs operation returning a SEQUENCE containing all of the
6511 frv_split_abs (rtx operands[])
6513 rtx dest = operands[0];
6514 rtx src = operands[1];
6515 rtx cc_reg = operands[2];
6516 rtx cr_reg = operands[3];
6521 /* Issue the compare < 0 instruction. */
6522 emit_insn (gen_rtx_SET (VOIDmode,
6524 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6526 /* Set the appropriate CCR bit. */
6527 emit_insn (gen_rtx_SET (VOIDmode,
6529 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6531 /* Emit the conditional negate if the value is negative. */
6532 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6533 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6534 gen_negsi2 (dest, src)));
6536 /* Emit the conditional move for the test being false if needed. */
6537 if (! rtx_equal_p (dest, src))
6538 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6539 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6540 gen_rtx_SET (VOIDmode, dest, src)));
6542 /* Finish up, return sequence. */
6549 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6550 register used in an insn. */
6553 frv_clear_registers_used (rtx *ptr, void *data)
6555 if (GET_CODE (*ptr) == REG)
6557 int regno = REGNO (*ptr);
6558 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6560 if (regno < FIRST_PSEUDO_REGISTER)
6562 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6564 while (regno < reg_max)
6566 CLEAR_HARD_REG_BIT (*p_regs, regno);
6576 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6578 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6579 initialize the static storage. */
6581 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6583 frv_ifcvt.added_insns_list = NULL_RTX;
6584 frv_ifcvt.cur_scratch_regs = 0;
6585 frv_ifcvt.num_nested_cond_exec = 0;
6586 frv_ifcvt.cr_reg = NULL_RTX;
6587 frv_ifcvt.nested_cc_reg = NULL_RTX;
6588 frv_ifcvt.extra_int_cr = NULL_RTX;
6589 frv_ifcvt.extra_fp_cr = NULL_RTX;
6590 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6594 /* Internal function to add a potential insn to the list of insns to be inserted
6595 if the conditional execution conversion is successful. */
6598 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6600 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6602 link->jump = before_p; /* Mark to add this before or after insn. */
6603 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6604 frv_ifcvt.added_insns_list);
6606 if (TARGET_DEBUG_COND_EXEC)
6609 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6610 (before_p) ? "before" : "after",
6611 (int)INSN_UID (insn));
6613 debug_rtx (pattern);
6618 /* A C expression to modify the code described by the conditional if
6619 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6620 FALSE_EXPR for converting if-then and if-then-else code to conditional
6621 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6622 tests cannot be converted. */
6625 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6627 basic_block test_bb = ce_info->test_bb; /* test basic block */
6628 basic_block then_bb = ce_info->then_bb; /* THEN */
6629 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6630 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6631 rtx true_expr = *p_true;
6635 enum machine_mode mode = GET_MODE (true_expr);
6639 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6641 rtx sub_cond_exec_reg;
6643 enum rtx_code code_true;
6644 enum rtx_code code_false;
6645 enum reg_class cc_class;
6646 enum reg_class cr_class;
6650 /* Make sure we are only dealing with hard registers. Also honor the
6651 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6653 if (!reload_completed || TARGET_NO_COND_EXEC
6654 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6657 /* Figure out which registers we can allocate for our own purposes. Only
6658 consider registers that are not preserved across function calls and are
6659 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6660 if we did not need to use them in reloading other registers. */
6661 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6662 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6663 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6664 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6665 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6667 /* If this is a nested IF, we need to discover whether the CC registers that
6668 are set/used inside of the block are used anywhere else. If not, we can
6669 change them to be the CC register that is paired with the CR register that
6670 controls the outermost IF block. */
6671 if (ce_info->pass > 1)
6673 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6674 for (j = CC_FIRST; j <= CC_LAST; j++)
6675 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6677 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6680 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6683 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6686 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6690 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6691 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6693 frv_ifcvt.added_insns_list = NULL_RTX;
6694 frv_ifcvt.cur_scratch_regs = 0;
6696 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6697 * sizeof (basic_block));
6703 /* Remove anything live at the beginning of the join block from being
6704 available for allocation. */
6705 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6707 if (regno < FIRST_PSEUDO_REGISTER)
6708 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6712 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6714 if (ce_info->num_multiple_test_blocks)
6716 basic_block multiple_test_bb = ce_info->last_test_bb;
6718 while (multiple_test_bb != test_bb)
6720 bb[num_bb++] = multiple_test_bb;
6721 multiple_test_bb = multiple_test_bb->pred->src;
6725 /* Add in the THEN and ELSE blocks to be scanned. */
6726 bb[num_bb++] = then_bb;
6728 bb[num_bb++] = else_bb;
6730 sub_cond_exec_reg = NULL_RTX;
6731 frv_ifcvt.num_nested_cond_exec = 0;
6733 /* Scan all of the blocks for registers that must not be allocated. */
6734 for (j = 0; j < num_bb; j++)
6736 rtx last_insn = BB_END (bb[j]);
6737 rtx insn = BB_HEAD (bb[j]);
6741 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6742 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6744 (int) INSN_UID (BB_HEAD (bb[j])),
6745 (int) INSN_UID (BB_END (bb[j])));
6747 /* Anything live at the beginning of the block is obviously unavailable
6749 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6751 if (regno < FIRST_PSEUDO_REGISTER)
6752 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6755 /* Loop through the insns in the block. */
6758 /* Mark any new registers that are created as being unavailable for
6759 allocation. Also see if the CC register used in nested IFs can be
6765 int skip_nested_if = FALSE;
6767 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6768 (void *)&tmp_reg->regs);
6770 pattern = PATTERN (insn);
6771 if (GET_CODE (pattern) == COND_EXEC)
6773 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6775 if (reg != sub_cond_exec_reg)
6777 sub_cond_exec_reg = reg;
6778 frv_ifcvt.num_nested_cond_exec++;
6782 set = single_set_pattern (pattern);
6785 rtx dest = SET_DEST (set);
6786 rtx src = SET_SRC (set);
6788 if (GET_CODE (dest) == REG)
6790 int regno = REGNO (dest);
6791 enum rtx_code src_code = GET_CODE (src);
6793 if (CC_P (regno) && src_code == COMPARE)
6794 skip_nested_if = TRUE;
6796 else if (CR_P (regno)
6797 && (src_code == IF_THEN_ELSE
6798 || COMPARISON_P (src)))
6799 skip_nested_if = TRUE;
6803 if (! skip_nested_if)
6804 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6805 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6808 if (insn == last_insn)
6811 insn = NEXT_INSN (insn);
6815 /* If this is a nested if, rewrite the CC registers that are available to
6816 include the ones that can be rewritten, to increase the chance of being
6817 able to allocate a paired CC/CR register combination. */
6818 if (ce_info->pass > 1)
6820 for (j = CC_FIRST; j <= CC_LAST; j++)
6821 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6822 SET_HARD_REG_BIT (tmp_reg->regs, j);
6824 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6830 fprintf (dump_file, "Available GPRs: ");
6832 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6833 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6835 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6836 if (++num_gprs > GPR_TEMP_NUM+2)
6840 fprintf (dump_file, "%s\nAvailable CRs: ",
6841 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6843 for (j = CR_FIRST; j <= CR_LAST; j++)
6844 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6845 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6847 fputs ("\n", dump_file);
6849 if (ce_info->pass > 1)
6851 fprintf (dump_file, "Modifiable CCs: ");
6852 for (j = CC_FIRST; j <= CC_LAST; j++)
6853 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6854 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6856 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6857 frv_ifcvt.num_nested_cond_exec);
6861 /* Allocate the appropriate temporary condition code register. Try to
6862 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6863 that conditional cmp's can be done. */
6864 if (mode == CCmode || mode == CC_UNSmode)
6866 cr_class = ICR_REGS;
6867 cc_class = ICC_REGS;
6868 cc_first = ICC_FIRST;
6871 else if (mode == CC_FPmode)
6873 cr_class = FCR_REGS;
6874 cc_class = FCC_REGS;
6875 cc_first = FCC_FIRST;
6880 cc_first = cc_last = 0;
6881 cr_class = cc_class = NO_REGS;
6884 cc = XEXP (true_expr, 0);
6885 nested_cc = cr = NULL_RTX;
6886 if (cc_class != NO_REGS)
6888 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6889 so we can execute a csubcc/caddcc/cfcmps instruction. */
6892 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6894 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6896 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6897 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6899 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6900 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6903 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6904 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6914 fprintf (dump_file, "Could not allocate a CR temporary register\n");
6921 "Will use %s for conditional execution, %s for nested comparisons\n",
6922 reg_names[ REGNO (cr)],
6923 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6925 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6926 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6927 bit being true. We don't do this for floating point, because of NaNs. */
6928 code = GET_CODE (true_expr);
6929 if (GET_MODE (cc) != CC_FPmode)
6931 code = reverse_condition (code);
6941 check_insn = gen_rtx_SET (VOIDmode, cr,
6942 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6944 /* Record the check insn to be inserted later. */
6945 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6947 /* Update the tests. */
6948 frv_ifcvt.cr_reg = cr;
6949 frv_ifcvt.nested_cc_reg = nested_cc;
6950 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6951 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6954 /* Fail, don't do this conditional execution. */
6957 *p_false = NULL_RTX;
6959 fprintf (dump_file, "Disabling this conditional execution.\n");
6965 /* A C expression to modify the code described by the conditional if
6966 information CE_INFO, for the basic block BB, possibly updating the tests in
6967 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6968 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6969 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6971 /* p_true and p_false are given expressions of the form:
6973 (and (eq:CC_CCR (reg:CC_CCR)
6979 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
6984 rtx old_true = XEXP (*p_true, 0);
6985 rtx old_false = XEXP (*p_false, 0);
6986 rtx true_expr = XEXP (*p_true, 1);
6987 rtx false_expr = XEXP (*p_false, 1);
6990 rtx cr = XEXP (old_true, 0);
6992 rtx new_cr = NULL_RTX;
6993 rtx *p_new_cr = (rtx *)0;
6997 enum reg_class cr_class;
6998 enum machine_mode mode = GET_MODE (true_expr);
6999 rtx (*logical_func)(rtx, rtx, rtx);
7001 if (TARGET_DEBUG_COND_EXEC)
7004 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7005 ce_info->and_and_p ? "&&" : "||");
7007 debug_rtx (*p_true);
7009 fputs ("\nfalse insn:\n", stderr);
7010 debug_rtx (*p_false);
7013 if (TARGET_NO_MULTI_CE)
7016 if (GET_CODE (cr) != REG)
7019 if (mode == CCmode || mode == CC_UNSmode)
7021 cr_class = ICR_REGS;
7022 p_new_cr = &frv_ifcvt.extra_int_cr;
7024 else if (mode == CC_FPmode)
7026 cr_class = FCR_REGS;
7027 p_new_cr = &frv_ifcvt.extra_fp_cr;
7032 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7033 more &&/|| tests. */
7037 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7038 CC_CCRmode, TRUE, TRUE);
7043 if (ce_info->and_and_p)
7045 old_test = old_false;
7046 test_expr = true_expr;
7047 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7048 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7049 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7053 old_test = old_false;
7054 test_expr = false_expr;
7055 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7056 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7057 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7060 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7061 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7063 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
7065 /* Now add the conditional check insn. */
7066 cc = XEXP (test_expr, 0);
7067 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7068 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7070 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7072 /* Add the new check insn to the list of check insns that need to be
7074 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
7076 if (TARGET_DEBUG_COND_EXEC)
7078 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7081 debug_rtx (*p_true);
7083 fputs ("\nfalse insn:\n", stderr);
7084 debug_rtx (*p_false);
7090 *p_true = *p_false = NULL_RTX;
7092 /* If we allocated a CR register, release it. */
7095 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7096 *p_new_cr = NULL_RTX;
7099 if (TARGET_DEBUG_COND_EXEC)
7100 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7106 /* Return a register which will be loaded with a value if an IF block is
7107 converted to conditional execution. This is used to rewrite instructions
7108 that use constants to ones that just use registers. */
7111 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
7113 int num_alloc = frv_ifcvt.cur_scratch_regs;
7117 /* We know gr0 == 0, so replace any errant uses. */
7118 if (value == const0_rtx)
7119 return gen_rtx_REG (SImode, GPR_FIRST);
7121 /* First search all registers currently loaded to see if we have an
7122 applicable constant. */
7123 if (CONSTANT_P (value)
7124 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7126 for (i = 0; i < num_alloc; i++)
7128 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7129 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7133 /* Have we exhausted the number of registers available? */
7134 if (num_alloc >= GPR_TEMP_NUM)
7137 fprintf (dump_file, "Too many temporary registers allocated\n");
7142 /* Allocate the new register. */
7143 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7147 fputs ("Could not find a scratch register\n", dump_file);
7152 frv_ifcvt.cur_scratch_regs++;
7153 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7157 if (GET_CODE (value) == CONST_INT)
7158 fprintf (dump_file, "Register %s will hold %ld\n",
7159 reg_names[ REGNO (reg)], (long)INTVAL (value));
7161 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7162 fprintf (dump_file, "Register %s will hold LR\n",
7163 reg_names[ REGNO (reg)]);
7166 fprintf (dump_file, "Register %s will hold a saved value\n",
7167 reg_names[ REGNO (reg)]);
7174 /* Update a MEM used in conditional code that might contain an offset to put
7175 the offset into a scratch register, so that the conditional load/store
7176 operations can be used. This function returns the original pointer if the
7177 MEM is valid to use in conditional code, NULL if we can't load up the offset
7178 into a temporary register, or the new MEM if we were successful. */
7181 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7183 rtx addr = XEXP (mem, 0);
7185 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7187 if (GET_CODE (addr) == PLUS)
7189 rtx addr_op0 = XEXP (addr, 0);
7190 rtx addr_op1 = XEXP (addr, 1);
7192 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7194 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7198 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7205 else if (CONSTANT_P (addr))
7206 addr = frv_ifcvt_load_value (addr, insn);
7211 if (addr == NULL_RTX)
7214 else if (XEXP (mem, 0) != addr)
7215 return change_address (mem, mode, addr);
7222 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7223 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7226 single_set_pattern (rtx pattern)
7231 if (GET_CODE (pattern) == COND_EXEC)
7232 pattern = COND_EXEC_CODE (pattern);
7234 if (GET_CODE (pattern) == SET)
7237 else if (GET_CODE (pattern) == PARALLEL)
7239 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7241 rtx sub = XVECEXP (pattern, 0, i);
7243 switch (GET_CODE (sub))
7267 /* A C expression to modify the code described by the conditional if
7268 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7269 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7270 insn cannot be converted to be executed conditionally. */
7273 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7277 rtx orig_ce_pattern = pattern;
7283 if (GET_CODE (pattern) != COND_EXEC)
7286 test = COND_EXEC_TEST (pattern);
7287 if (GET_CODE (test) == AND)
7289 rtx cr = frv_ifcvt.cr_reg;
7292 op0 = XEXP (test, 0);
7293 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7296 op1 = XEXP (test, 1);
7297 test_reg = XEXP (op1, 0);
7298 if (GET_CODE (test_reg) != REG)
7301 /* Is this the first nested if block in this sequence? If so, generate
7302 an andcr or andncr. */
7303 if (! frv_ifcvt.last_nested_if_cr)
7307 frv_ifcvt.last_nested_if_cr = test_reg;
7308 if (GET_CODE (op0) == NE)
7309 and_op = gen_andcr (test_reg, cr, test_reg);
7311 and_op = gen_andncr (test_reg, cr, test_reg);
7313 frv_ifcvt_add_insn (and_op, insn, TRUE);
7316 /* If this isn't the first statement in the nested if sequence, see if we
7317 are dealing with the same register. */
7318 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7321 COND_EXEC_TEST (pattern) = test = op1;
7324 /* If this isn't a nested if, reset state variables. */
7327 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7330 set = single_set_pattern (pattern);
7333 rtx dest = SET_DEST (set);
7334 rtx src = SET_SRC (set);
7335 enum machine_mode mode = GET_MODE (dest);
7337 /* Check for normal binary operators. */
7338 if (mode == SImode && ARITHMETIC_P (src))
7340 op0 = XEXP (src, 0);
7341 op1 = XEXP (src, 1);
7343 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7345 op1 = frv_ifcvt_load_value (op1, insn);
7347 COND_EXEC_CODE (pattern)
7348 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7356 /* For multiply by a constant, we need to handle the sign extending
7357 correctly. Add a USE of the value after the multiply to prevent flow
7358 from cratering because only one register out of the two were used. */
7359 else if (mode == DImode && GET_CODE (src) == MULT)
7361 op0 = XEXP (src, 0);
7362 op1 = XEXP (src, 1);
7363 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7365 op1 = frv_ifcvt_load_value (op1, insn);
7368 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7369 COND_EXEC_CODE (pattern)
7370 = gen_rtx_SET (VOIDmode, dest,
7371 gen_rtx_MULT (DImode, op0, op1));
7377 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7380 /* If we are just loading a constant created for a nested conditional
7381 execution statement, just load the constant without any conditional
7382 execution, since we know that the constant will not interfere with any
7384 else if (frv_ifcvt.scratch_insns_bitmap
7385 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7387 /* We must not unconditionally set a reg set used as
7388 scratch in the THEN branch if the same reg is live
7389 in the ELSE branch. */
7390 && REG_P (SET_DEST (set))
7391 && (! ce_info->else_bb
7392 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7393 || ! (REGNO_REG_SET_P
7394 (ce_info->else_bb->global_live_at_start,
7395 REGNO (SET_DEST (set))))))
7398 else if (mode == QImode || mode == HImode || mode == SImode
7401 int changed_p = FALSE;
7403 /* Check for just loading up a constant */
7404 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7406 src = frv_ifcvt_load_value (src, insn);
7413 /* See if we need to fix up stores */
7414 if (GET_CODE (dest) == MEM)
7416 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7421 else if (new_mem != dest)
7428 /* See if we need to fix up loads */
7429 if (GET_CODE (src) == MEM)
7431 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7436 else if (new_mem != src)
7443 /* If either src or destination changed, redo SET. */
7445 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7448 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7449 rewriting the CC register to be the same as the paired CC/CR register
7451 else if (mode == CC_CCRmode && COMPARISON_P (src))
7453 int regno = REGNO (XEXP (src, 0));
7456 if (ce_info->pass > 1
7457 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7458 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7460 src = gen_rtx_fmt_ee (GET_CODE (src),
7462 frv_ifcvt.nested_cc_reg,
7466 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7467 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7470 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7471 else if (ce_info->pass > 1
7472 && GET_CODE (dest) == REG
7473 && CC_P (REGNO (dest))
7474 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7475 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7477 && GET_CODE (src) == COMPARE)
7479 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7480 COND_EXEC_CODE (pattern)
7481 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7485 if (TARGET_DEBUG_COND_EXEC)
7487 rtx orig_pattern = PATTERN (insn);
7489 PATTERN (insn) = pattern;
7491 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7495 PATTERN (insn) = orig_pattern;
7501 if (TARGET_DEBUG_COND_EXEC)
7503 rtx orig_pattern = PATTERN (insn);
7505 PATTERN (insn) = orig_ce_pattern;
7507 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7511 PATTERN (insn) = orig_pattern;
7518 /* A C expression to perform any final machine dependent modifications in
7519 converting code to conditional execution in the code described by the
7520 conditional if information CE_INFO. */
7523 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7527 rtx p = frv_ifcvt.added_insns_list;
7530 /* Loop inserting the check insns. The last check insn is the first test,
7531 and is the appropriate place to insert constants. */
7537 rtx check_and_insert_insns = XEXP (p, 0);
7540 check_insn = XEXP (check_and_insert_insns, 0);
7541 existing_insn = XEXP (check_and_insert_insns, 1);
7544 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7545 the existing insn, otherwise it is to be inserted AFTER. */
7546 if (check_and_insert_insns->jump)
7548 emit_insn_before (check_insn, existing_insn);
7549 check_and_insert_insns->jump = 0;
7552 emit_insn_after (check_insn, existing_insn);
7554 free_EXPR_LIST_node (check_and_insert_insns);
7555 free_EXPR_LIST_node (old_p);
7557 while (p != NULL_RTX);
7559 /* Load up any constants needed into temp gprs */
7560 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7562 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7563 if (! frv_ifcvt.scratch_insns_bitmap)
7564 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7565 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7566 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7569 frv_ifcvt.added_insns_list = NULL_RTX;
7570 frv_ifcvt.cur_scratch_regs = 0;
7574 /* A C expression to cancel any machine dependent modifications in converting
7575 code to conditional execution in the code described by the conditional if
7576 information CE_INFO. */
7579 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7582 rtx p = frv_ifcvt.added_insns_list;
7584 /* Loop freeing up the EXPR_LIST's allocated. */
7585 while (p != NULL_RTX)
7587 rtx check_and_jump = XEXP (p, 0);
7591 free_EXPR_LIST_node (check_and_jump);
7592 free_EXPR_LIST_node (old_p);
7595 /* Release any temporary gprs allocated. */
7596 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7597 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7599 frv_ifcvt.added_insns_list = NULL_RTX;
7600 frv_ifcvt.cur_scratch_regs = 0;
7604 /* A C expression for the size in bytes of the trampoline, as an integer.
7608 setlo #0, <static_chain>
7610 sethi #0, <static_chain>
7611 jmpl @(gr0,<jmp_reg>) */
7614 frv_trampoline_size (void)
7617 /* Allocate room for the function descriptor and the lddi
7620 return 5 /* instructions */ * 4 /* instruction size. */;
7624 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7625 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7626 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7627 should be passed to the function when it is called.
7632 setlo #0, <static_chain>
7634 sethi #0, <static_chain>
7635 jmpl @(gr0,<jmp_reg>) */
7638 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7640 rtx sc_reg = force_reg (Pmode, static_chain);
7642 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7645 GEN_INT (frv_trampoline_size ()), SImode,
7651 /* Many machines have some registers that cannot be copied directly to or from
7652 memory or even from other types of registers. An example is the `MQ'
7653 register, which on most machines, can only be copied to or from general
7654 registers, but not memory. Some machines allow copying all registers to and
7655 from memory, but require a scratch register for stores to some memory
7656 locations (e.g., those with symbolic address on the RT, and those with
7657 certain symbolic address on the SPARC when compiling PIC). In some cases,
7658 both an intermediate and a scratch register are required.
7660 You should define these macros to indicate to the reload phase that it may
7661 need to allocate at least one register for a reload in addition to the
7662 register to contain the data. Specifically, if copying X to a register
7663 CLASS in MODE requires an intermediate register, you should define
7664 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7665 whose registers can be used as intermediate registers or scratch registers.
7667 If copying a register CLASS in MODE to X requires an intermediate or scratch
7668 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7669 largest register class required. If the requirements for input and output
7670 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7671 instead of defining both macros identically.
7673 The values returned by these macros are often `GENERAL_REGS'. Return
7674 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7675 to or from a register of CLASS in MODE without requiring a scratch register.
7676 Do not define this macro if it would always return `NO_REGS'.
7678 If a scratch register is required (either with or without an intermediate
7679 register), you should define patterns for `reload_inM' or `reload_outM', as
7680 required.. These patterns, which will normally be implemented with a
7681 `define_expand', should be similar to the `movM' patterns, except that
7682 operand 2 is the scratch register.
7684 Define constraints for the reload register and scratch register that contain
7685 a single register class. If the original reload register (whose class is
7686 CLASS) can meet the constraint given in the pattern, the value returned by
7687 these macros is used for the class of the scratch register. Otherwise, two
7688 additional reload registers are required. Their classes are obtained from
7689 the constraints in the insn pattern.
7691 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7692 either be in a hard register or in memory. Use `true_regnum' to find out;
7693 it will return -1 if the pseudo is in memory and the hard register number if
7694 it is in a register.
7696 These macros should not be used in the case where a particular class of
7697 registers can only be copied to memory and not to another class of
7698 registers. In that case, secondary reload registers are not needed and
7699 would not be helpful. Instead, a stack location must be used to perform the
7700 copy and the `movM' pattern should use memory as an intermediate storage.
7701 This case often occurs between floating-point and general registers. */
7704 frv_secondary_reload_class (enum reg_class class,
7705 enum machine_mode mode ATTRIBUTE_UNUSED,
7707 int in_p ATTRIBUTE_UNUSED)
7717 /* Accumulators/Accumulator guard registers need to go through floating
7723 if (x && GET_CODE (x) == REG)
7725 int regno = REGNO (x);
7727 if (ACC_P (regno) || ACCG_P (regno))
7732 /* Nonzero constants should be loaded into an FPR through a GPR. */
7736 if (x && CONSTANT_P (x) && !ZERO_P (x))
7742 /* All of these types need gpr registers. */
7754 /* The accumulators need fpr registers */
7767 /* A C expression whose value is nonzero if pseudos that have been assigned to
7768 registers of class CLASS would likely be spilled because registers of CLASS
7769 are needed for spill registers.
7771 The default value of this macro returns 1 if CLASS has exactly one register
7772 and zero otherwise. On most machines, this default should be used. Only
7773 define this macro to some other expression if pseudo allocated by
7774 `local-alloc.c' end up in memory because their hard registers were needed
7775 for spill registers. If this macro returns nonzero for those classes, those
7776 pseudos will only be allocated by `global.c', which knows how to reallocate
7777 the pseudo to another register. If there would not be another register
7778 available for reallocation, you should not change the definition of this
7779 macro since the only effect of such a definition would be to slow down
7780 register allocation. */
7783 frv_class_likely_spilled_p (enum reg_class class)
7810 /* An expression for the alignment of a structure field FIELD if the
7811 alignment computed in the usual way is COMPUTED. GCC uses this
7812 value instead of the value in `BIGGEST_ALIGNMENT' or
7813 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7815 /* The definition type of the bit field data is either char, short, long or
7816 long long. The maximum bit size is the number of bits of its own type.
7818 The bit field data is assigned to a storage unit that has an adequate size
7819 for bit field data retention and is located at the smallest address.
7821 Consecutive bit field data are packed at consecutive bits having the same
7822 storage unit, with regard to the type, beginning with the MSB and continuing
7825 If a field to be assigned lies over a bit field type boundary, its
7826 assignment is completed by aligning it with a boundary suitable for the
7829 When a bit field having a bit length of 0 is declared, it is forcibly
7830 assigned to the next storage unit.
7843 &x 00000000 00000000 00000000 00000000
7846 &x+4 00000000 00000000 00000000 00000000
7849 &x+8 00000000 00000000 00000000 00000000
7852 &x+12 00000000 00000000 00000000 00000000
7858 frv_adjust_field_align (tree field, int computed)
7860 /* Make sure that the bitfield is not wider than the type. */
7861 if (DECL_BIT_FIELD (field)
7862 && !DECL_ARTIFICIAL (field))
7864 tree parent = DECL_CONTEXT (field);
7865 tree prev = NULL_TREE;
7868 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7870 if (TREE_CODE (cur) != FIELD_DECL)
7879 /* If this isn't a :0 field and if the previous element is a bitfield
7880 also, see if the type is different, if so, we will need to align the
7881 bit-field to the next boundary. */
7883 && ! DECL_PACKED (field)
7884 && ! integer_zerop (DECL_SIZE (field))
7885 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7887 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7888 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7889 computed = (prev_align > cur_align) ? prev_align : cur_align;
7897 /* A C expression that is nonzero if it is permissible to store a value of mode
7898 MODE in hard register number REGNO (or in several registers starting with
7899 that one). For a machine where all registers are equivalent, a suitable
7902 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7904 It is not necessary for this macro to check for the numbers of fixed
7905 registers, because the allocation mechanism considers them to be always
7908 On some machines, double-precision values must be kept in even/odd register
7909 pairs. The way to implement that is to define this macro to reject odd
7910 register numbers for such modes.
7912 The minimum requirement for a mode to be OK in a register is that the
7913 `movMODE' instruction pattern support moves between the register and any
7914 other hard register for which the mode is OK; and that moving a value into
7915 the register and back out not alter it.
7917 Since the same instruction used to move `SImode' will work for all narrower
7918 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7919 to distinguish between these modes, provided you define patterns `movhi',
7920 etc., to take advantage of this. This is useful because of the interaction
7921 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7922 all integer modes to be tieable.
7924 Many machines have special registers for floating point arithmetic. Often
7925 people assume that floating point machine modes are allowed only in floating
7926 point registers. This is not true. Any registers that can hold integers
7927 can safely *hold* a floating point machine mode, whether or not floating
7928 arithmetic can be done on it in those registers. Integer move instructions
7929 can be used to move the values.
7931 On some machines, though, the converse is true: fixed-point machine modes
7932 may not go in floating registers. This is true if the floating registers
7933 normalize any value stored in them, because storing a non-floating value
7934 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7935 fixed-point machine modes in floating registers. But if the floating
7936 registers do not automatically normalize, if you can store any bit pattern
7937 in one and retrieve it unchanged without a trap, then any machine mode may
7938 go in a floating register, so you can define this macro to say so.
7940 The primary significance of special floating registers is rather that they
7941 are the registers acceptable in floating point arithmetic instructions.
7942 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7943 writing the proper constraints for those instructions.
7945 On some machines, the floating registers are especially slow to access, so
7946 that it is better to store a value in a stack frame than in such a register
7947 if floating point arithmetic is not being done. As long as the floating
7948 registers are not in class `GENERAL_REGS', they will not be used unless some
7949 pattern's constraint asks for one. */
7952 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7961 return ICC_P (regno) || GPR_P (regno);
7964 return CR_P (regno) || GPR_P (regno);
7967 return FCC_P (regno) || GPR_P (regno);
7973 /* Set BASE to the first register in REGNO's class. Set MASK to the
7974 bits that must be clear in (REGNO - BASE) for the register to be
7976 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7980 /* ACCGs store one byte. Two-byte quantities must start in
7981 even-numbered registers, four-byte ones in registers whose
7982 numbers are divisible by four, and so on. */
7984 mask = GET_MODE_SIZE (mode) - 1;
7988 /* The other registers store one word. */
7989 if (GPR_P (regno) || regno == AP_FIRST)
7992 else if (FPR_P (regno))
7995 else if (ACC_P (regno))
7998 else if (SPR_P (regno))
7999 return mode == SImode;
8001 /* Fill in the table. */
8005 /* Anything smaller than an SI is OK in any word-sized register. */
8006 if (GET_MODE_SIZE (mode) < 4)
8009 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8011 return (((regno - base) & mask) == 0);
8018 /* A C expression for the number of consecutive hard registers, starting at
8019 register number REGNO, required to hold a value of mode MODE.
8021 On a machine where all registers are exactly one word, a suitable definition
8024 #define HARD_REGNO_NREGS(REGNO, MODE) \
8025 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8026 / UNITS_PER_WORD)) */
8028 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8029 that we can build the appropriate instructions to properly reload the
8030 values. Also, make the byte-sized accumulator guards use one guard
8034 frv_hard_regno_nregs (int regno, enum machine_mode mode)
8037 return GET_MODE_SIZE (mode);
8039 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8043 /* A C expression for the maximum number of consecutive registers of
8044 class CLASS needed to hold a value of mode MODE.
8046 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8047 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8048 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8050 This macro helps control the handling of multiple-word values in
8053 This declaration is required. */
8056 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
8058 if (class == ACCG_REGS)
8059 /* An N-byte value requires N accumulator guards. */
8060 return GET_MODE_SIZE (mode);
8062 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8066 /* A C expression that is nonzero if X is a legitimate constant for an
8067 immediate operand on the target machine. You can assume that X satisfies
8068 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8069 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8072 frv_legitimate_constant_p (rtx x)
8074 enum machine_mode mode = GET_MODE (x);
8076 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8077 means that the move expanders will be expected to deal with most
8078 kinds of constant, regardless of what we return here.
8080 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8081 a constant can be entered into reg_equiv_constant[]. If we return true,
8082 reload can create new instances of the constant whenever it likes.
8084 The idea is therefore to accept as many constants as possible (to give
8085 reload more freedom) while rejecting constants that can only be created
8086 at certain times. In particular, anything with a symbolic component will
8087 require use of the pseudo FDPIC register, which is only available before
8090 return LEGITIMATE_PIC_OPERAND_P (x);
8092 /* All of the integer constants are ok. */
8093 if (GET_CODE (x) != CONST_DOUBLE)
8096 /* double integer constants are ok. */
8097 if (mode == VOIDmode || mode == DImode)
8100 /* 0 is always ok. */
8101 if (x == CONST0_RTX (mode))
8104 /* If floating point is just emulated, allow any constant, since it will be
8105 constructed in the GPRs. */
8106 if (!TARGET_HAS_FPRS)
8109 if (mode == DFmode && !TARGET_DOUBLE)
8112 /* Otherwise store the constant away and do a load. */
8116 /* A C expression for the cost of moving data from a register in class FROM to
8117 one in class TO. The classes are expressed using the enumeration values
8118 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8119 interpreted relative to that.
8121 It is not required that the cost always equal 2 when FROM is the same as TO;
8122 on some machines it is expensive to move between registers if they are not
8125 If reload sees an insn consisting of a single `set' between two hard
8126 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8127 value of 2, reload does not check to ensure that the constraints of the insn
8128 are met. Setting a cost of other than 2 will allow reload to verify that
8129 the constraints are met. You should do this if the `movM' pattern's
8130 constraints do not allow such copying. */
8132 #define HIGH_COST 40
8133 #define MEDIUM_COST 3
8137 frv_register_move_cost (enum reg_class from, enum reg_class to)
8221 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8222 use ".picptr" to generate safe relocations for PIC code. We also
8223 need a fixup entry for aligned (non-debugging) code. */
8226 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8228 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8230 if (GET_CODE (value) == CONST
8231 || GET_CODE (value) == SYMBOL_REF
8232 || GET_CODE (value) == LABEL_REF)
8234 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8235 && SYMBOL_REF_FUNCTION_P (value))
8237 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8238 output_addr_const (asm_out_file, value);
8239 fputs (")\n", asm_out_file);
8242 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8243 && frv_function_symbol_referenced_p (value))
8245 if (aligned_p && !TARGET_FDPIC)
8247 static int label_num = 0;
8251 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8252 p = (* targetm.strip_name_encoding) (buf);
8254 fprintf (asm_out_file, "%s:\n", p);
8255 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8256 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8257 fprintf (asm_out_file, "\t.previous\n");
8259 assemble_integer_with_op ("\t.picptr\t", value);
8264 /* We've set the unaligned SI op to NULL, so we always have to
8265 handle the unaligned case here. */
8266 assemble_integer_with_op ("\t.4byte\t", value);
8270 return default_assemble_integer (value, size, aligned_p);
8273 /* Function to set up the backend function structure. */
8275 static struct machine_function *
8276 frv_init_machine_status (void)
8278 return ggc_alloc_cleared (sizeof (struct machine_function));
8281 /* Implement TARGET_SCHED_ISSUE_RATE. */
8284 frv_issue_rate (void)
8289 switch (frv_cpu_type)
8293 case FRV_CPU_SIMPLE:
8299 case FRV_CPU_GENERIC:
8301 case FRV_CPU_TOMCAT:
8306 /* Update the register state information, to know about which registers are set
8310 frv_registers_update (rtx x,
8311 unsigned char reg_state[],
8323 switch (GET_CODE (x))
8328 /* Clobber just modifies a register, it doesn't make it live. */
8330 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8331 flag | REGSTATE_MODIFIED);
8334 /* Pre modify updates the first argument, just references the second. */
8337 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8338 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8339 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8342 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8343 statement, but just to be sure, make sure it is the type of cond_exec
8347 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8348 && GET_CODE (XEXP (cond, 0)) == REG
8349 && CR_P (REGNO (XEXP (cond, 0)))
8350 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8351 && INTVAL (XEXP (cond, 1)) == 0
8352 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8354 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8355 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8356 | ((GET_CODE (cond) == NE)
8358 : REGSTATE_IF_FALSE));
8360 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8365 fatal_insn ("frv_registers_update", x);
8367 /* MEM resets the modification bits. */
8369 flag &= ~REGSTATE_MODIFIED;
8372 /* See if we need to set the modified flag. */
8374 reg = SUBREG_REG (x);
8375 if (GET_CODE (reg) == REG)
8377 regno = subreg_regno (x);
8378 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8385 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8389 if (flag & REGSTATE_MODIFIED)
8391 flag &= REGSTATE_MASK;
8392 while (regno < reg_max)
8394 int rs = reg_state[regno];
8398 if ((rs & REGSTATE_MODIFIED) == 0)
8400 modified[ *p_num_mod ] = regno;
8404 /* If the previous register state had the register as
8405 modified, possibly in some conditional execution context,
8406 and the current insn modifies in some other context, or
8407 outside of conditional execution, just mark the variable
8410 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8412 reg_state[regno] = (rs | flag);
8421 length = GET_RTX_LENGTH (GET_CODE (x));
8422 format = GET_RTX_FORMAT (GET_CODE (x));
8424 for (j = 0; j < length; ++j)
8429 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8435 if (XVEC (x, j) != 0)
8438 for (k = 0; k < XVECLEN (x, j); ++k)
8439 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8445 /* Nothing to do. */
8454 /* Return if any registers in a hard register set were used an insn. */
8457 frv_registers_used_p (rtx x, unsigned char reg_state[], int flag)
8468 switch (GET_CODE (x))
8473 /* Skip clobber, that doesn't use the previous value. */
8477 /* For SET, if a conditional jump has occurred in the same insn, only
8478 allow a set of a CR register if that register is not currently live.
8479 This is because on the FR-V, B0/B1 instructions are always last.
8480 Otherwise, don't look at the result, except within a MEM, but do look
8483 dest = SET_DEST (x);
8484 if (flag & REGSTATE_CONDJUMP
8485 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8486 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8489 if (GET_CODE (dest) == MEM)
8491 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8496 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8498 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8499 statement, but just to be sure, make sure it is the type of cond_exec
8503 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8504 && GET_CODE (XEXP (cond, 0)) == REG
8505 && CR_P (REGNO (XEXP (cond, 0)))
8506 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8507 && INTVAL (XEXP (cond, 1)) == 0
8508 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8510 result = frv_registers_used_p (cond, reg_state, flag);
8514 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8515 | ((GET_CODE (cond) == NE)
8517 : REGSTATE_IF_FALSE));
8519 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8522 fatal_insn ("frv_registers_used_p", x);
8524 /* See if a register or subreg was modified in the same VLIW insn. */
8526 reg = SUBREG_REG (x);
8527 if (GET_CODE (reg) == REG)
8529 regno = subreg_regno (x);
8530 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8537 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8541 while (regno < reg_max)
8543 int rs = reg_state[regno];
8545 if (rs & REGSTATE_MODIFIED)
8547 int rs_if = rs & REGSTATE_IF_EITHER;
8548 int flag_if = flag & REGSTATE_IF_EITHER;
8550 /* Simple modification, no conditional execution */
8551 if ((rs & REGSTATE_IF_EITHER) == 0)
8554 /* See if the variable is only modified in a conditional
8555 execution expression opposite to the conditional execution
8556 expression that governs this expression (ie, true vs. false
8557 for the same CC register). If this isn't two halves of the
8558 same conditional expression, consider the register
8560 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8561 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8562 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8574 length = GET_RTX_LENGTH (GET_CODE (x));
8575 format = GET_RTX_FORMAT (GET_CODE (x));
8577 for (j = 0; j < length; ++j)
8582 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8589 if (XVEC (x, j) != 0)
8592 for (k = 0; k < XVECLEN (x, j); ++k)
8594 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8603 /* Nothing to do. */
8611 /* Return if any registers in a hard register set were set in an insn. */
8614 frv_registers_set_p (rtx x, unsigned char reg_state[], int modify_p)
8623 switch (GET_CODE (x))
8629 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8633 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8634 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8638 /* Just to be sure, make sure it is the type of cond_exec we
8640 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8641 && GET_CODE (XEXP (cond, 0)) == REG
8642 && CR_P (REGNO (XEXP (cond, 0)))
8643 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8644 && INTVAL (XEXP (cond, 1)) == 0
8646 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8648 fatal_insn ("frv_registers_set_p", x);
8650 /* MEM resets the modification bits. */
8655 /* See if we need to set the modified modify_p. */
8657 reg = SUBREG_REG (x);
8658 if (GET_CODE (reg) == REG)
8660 regno = subreg_regno (x);
8661 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8668 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8673 while (regno < reg_max)
8675 int rs = reg_state[regno];
8677 if (rs & REGSTATE_MODIFIED)
8685 length = GET_RTX_LENGTH (GET_CODE (x));
8686 format = GET_RTX_FORMAT (GET_CODE (x));
8688 for (j = 0; j < length; ++j)
8693 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8699 if (XVEC (x, j) != 0)
8702 for (k = 0; k < XVECLEN (x, j); ++k)
8703 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8710 /* Nothing to do. */
8719 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8720 conditional branches/calls/jumps, etc. with previous insns where it can. It
8721 does not reorder the instructions. We assume the scheduler left the flow
8722 information in a reasonable state. */
8725 frv_pack_insns (void)
8727 state_t frv_state; /* frv state machine */
8728 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8729 int next_start_vliw_p; /* next insn starts a VLIW insn */
8730 int cur_condjump_p; /* flag if current insn is a cond jump*/
8731 int next_condjump_p; /* flag if next insn is a cond jump */
8735 int num_mod = 0; /* # of modified registers */
8736 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8737 /* register state information */
8738 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8740 /* If we weren't going to pack the insns, don't bother with this pass. */
8742 || !flag_schedule_insns_after_reload
8743 || TARGET_NO_VLIW_BRANCH
8744 || frv_issue_rate () == 1)
8747 /* Set up the instruction and register states. */
8749 frv_state = (state_t) xmalloc (state_size ());
8750 memset (reg_state, REGSTATE_DEAD, sizeof (reg_state));
8752 /* Go through the insns, and repack the insns. */
8753 state_reset (frv_state);
8754 cur_start_vliw_p = FALSE;
8755 next_start_vliw_p = TRUE;
8757 next_condjump_p = 0;
8759 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8761 enum rtx_code code = GET_CODE (insn);
8762 enum rtx_code pattern_code;
8764 /* For basic block begin notes redo the live information, and skip other
8768 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8772 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8773 reg_state[j] &= ~ REGSTATE_LIVE;
8775 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8776 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8778 reg_state[j] |= REGSTATE_LIVE;
8785 /* Things like labels reset everything. */
8788 next_start_vliw_p = TRUE;
8792 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8793 set on the USE insn that precedes the return, and potentially on
8794 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8795 holding the case table labels. */
8796 pattern_code = GET_CODE (PATTERN (insn));
8797 if (pattern_code == USE || pattern_code == CLOBBER
8798 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8800 CLEAR_VLIW_START (insn);
8804 cur_start_vliw_p = next_start_vliw_p;
8805 next_start_vliw_p = FALSE;
8807 cur_condjump_p |= next_condjump_p;
8808 next_condjump_p = 0;
8810 /* Unconditional branches and calls end the current VLIW insn. */
8811 if (code == CALL_INSN)
8813 next_start_vliw_p = TRUE;
8815 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8816 if (frv_cpu_type == FRV_CPU_TOMCAT)
8817 cur_start_vliw_p = TRUE;
8819 else if (code == JUMP_INSN)
8821 if (any_condjump_p (insn))
8822 next_condjump_p = REGSTATE_CONDJUMP;
8824 next_start_vliw_p = TRUE;
8827 /* Only allow setting a CCR register after a conditional branch. */
8828 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8829 && get_attr_type (insn) != TYPE_CCR)
8830 cur_start_vliw_p = TRUE;
8832 /* Determine if we need to start a new VLIW instruction. */
8833 if (cur_start_vliw_p
8834 /* Do not check for register conflicts in a setlo instruction
8835 because any output or true dependencies will be with the
8836 partnering sethi instruction, with which it can be packed.
8838 Although output dependencies are rare they are still
8839 possible. So check output dependencies in VLIW insn. */
8840 || (get_attr_type (insn) != TYPE_SETLO
8841 && (frv_registers_used_p (PATTERN (insn),
8844 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8845 || state_transition (frv_state, insn) >= 0)
8847 SET_VLIW_START (insn);
8848 state_reset (frv_state);
8849 state_transition (frv_state, insn);
8852 /* Update the modified registers. */
8853 for (j = 0; j < num_mod; j++)
8854 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8855 | REGSTATE_IF_EITHER
8856 | REGSTATE_MODIFIED);
8861 CLEAR_VLIW_START (insn);
8863 /* Record which registers are modified. */
8864 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8866 /* Process the death notices. */
8867 for (link = REG_NOTES (insn);
8869 link = XEXP (link, 1))
8871 rtx reg = XEXP (link, 0);
8873 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8875 int regno = REGNO (reg);
8876 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8877 for (; regno < n; regno++)
8878 reg_state[regno] &= ~REGSTATE_LIVE;
8889 #define def_builtin(name, type, code) \
8890 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8892 struct builtin_description
8894 enum insn_code icode;
8896 enum frv_builtins code;
8897 enum rtx_code comparison;
8901 /* Media intrinsics that take a single, constant argument. */
8903 static struct builtin_description bdesc_set[] =
8905 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8908 /* Media intrinsics that take just one argument. */
8910 static struct builtin_description bdesc_1arg[] =
8912 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8913 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8914 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8915 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8916 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8919 /* Media intrinsics that take two arguments. */
8921 static struct builtin_description bdesc_2arg[] =
8923 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8924 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8925 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8926 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8927 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8928 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8929 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8930 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8931 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8932 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8933 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8934 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8935 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8936 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8937 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8938 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8939 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8940 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8941 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8942 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8945 /* Media intrinsics that take two arguments, the first being an ACC number. */
8947 static struct builtin_description bdesc_cut[] =
8949 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8950 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8951 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8954 /* Two-argument media intrinsics with an immediate second argument. */
8956 static struct builtin_description bdesc_2argimm[] =
8958 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8959 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8960 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8961 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8962 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8963 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8964 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8965 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8966 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8967 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8968 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8969 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8970 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8971 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8972 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8975 /* Media intrinsics that take two arguments and return void, the first argument
8976 being a pointer to 4 words in memory. */
8978 static struct builtin_description bdesc_void2arg[] =
8980 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8981 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8984 /* Media intrinsics that take three arguments, the first being a const_int that
8985 denotes an accumulator, and that return void. */
8987 static struct builtin_description bdesc_void3arg[] =
8989 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8990 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8991 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8992 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8993 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8994 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8995 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8996 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8997 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8998 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8999 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9000 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9001 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9002 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9003 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9004 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9005 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9006 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9007 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9008 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9009 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9010 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9011 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9012 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9013 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9016 /* Media intrinsics that take two accumulator numbers as argument and
9019 static struct builtin_description bdesc_voidacc[] =
9021 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9022 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9023 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9024 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9025 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9026 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9029 /* Initialize media builtins. */
9032 frv_init_builtins (void)
9034 tree endlink = void_list_node;
9035 tree accumulator = integer_type_node;
9036 tree integer = integer_type_node;
9037 tree voidt = void_type_node;
9038 tree uhalf = short_unsigned_type_node;
9039 tree sword1 = long_integer_type_node;
9040 tree uword1 = long_unsigned_type_node;
9041 tree sword2 = long_long_integer_type_node;
9042 tree uword2 = long_long_unsigned_type_node;
9043 tree uword4 = build_pointer_type (uword1);
9045 #define UNARY(RET, T1) \
9046 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9048 #define BINARY(RET, T1, T2) \
9049 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9050 tree_cons (NULL_TREE, T2, endlink)))
9052 #define TRINARY(RET, T1, T2, T3) \
9053 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9054 tree_cons (NULL_TREE, T2, \
9055 tree_cons (NULL_TREE, T3, endlink))))
9057 tree void_ftype_void = build_function_type (voidt, endlink);
9059 tree void_ftype_acc = UNARY (voidt, accumulator);
9060 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9061 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9062 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9063 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9064 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9065 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9066 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9067 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9069 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9070 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9071 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9072 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9073 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9074 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9075 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9076 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9077 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9078 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9079 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9081 tree sw1_ftype_int = UNARY (sword1, integer);
9082 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9083 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9085 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9086 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9087 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9088 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9089 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9091 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9093 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9094 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9095 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9096 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9097 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9098 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9099 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9100 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9101 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9102 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9103 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9104 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9105 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9106 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9107 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9108 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9109 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9110 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9111 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9112 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9113 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9114 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9115 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9116 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9117 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9118 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9119 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9120 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9121 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9122 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9123 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9124 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9125 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9126 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9127 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9128 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9129 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9130 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9131 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9132 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9133 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9134 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9135 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9136 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9137 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9138 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9139 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9140 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9141 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9142 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9143 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9144 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9145 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9146 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9147 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9148 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9149 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9150 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9151 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9152 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9153 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9154 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9155 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9156 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9157 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9158 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9159 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9160 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9161 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9162 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9163 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9164 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9165 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9166 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9167 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9168 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9169 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9170 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9171 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9172 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9173 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9174 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9175 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9176 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9183 /* Set the names for various arithmetic operations according to the
9186 frv_init_libfuncs (void)
9188 set_optab_libfunc (smod_optab, SImode, "__modi");
9189 set_optab_libfunc (umod_optab, SImode, "__umodi");
9191 set_optab_libfunc (add_optab, DImode, "__addll");
9192 set_optab_libfunc (sub_optab, DImode, "__subll");
9193 set_optab_libfunc (smul_optab, DImode, "__mulll");
9194 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9195 set_optab_libfunc (smod_optab, DImode, "__modll");
9196 set_optab_libfunc (umod_optab, DImode, "__umodll");
9197 set_optab_libfunc (and_optab, DImode, "__andll");
9198 set_optab_libfunc (ior_optab, DImode, "__orll");
9199 set_optab_libfunc (xor_optab, DImode, "__xorll");
9200 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9202 set_optab_libfunc (add_optab, SFmode, "__addf");
9203 set_optab_libfunc (sub_optab, SFmode, "__subf");
9204 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9205 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9207 set_optab_libfunc (add_optab, DFmode, "__addd");
9208 set_optab_libfunc (sub_optab, DFmode, "__subd");
9209 set_optab_libfunc (smul_optab, DFmode, "__muld");
9210 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9212 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9213 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9215 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9216 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9217 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9218 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9220 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9221 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9222 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9223 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9225 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9226 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9227 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9228 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9231 /* Convert an integer constant to an accumulator register. ICODE is the
9232 code of the target instruction, OPNUM is the number of the
9233 accumulator operand and OPVAL is the constant integer. Try both
9234 ACC and ACCG registers; only report an error if neither fit the
9238 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9242 if (GET_CODE (opval) != CONST_INT)
9244 error ("accumulator is not a constant integer");
9247 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9249 error ("accumulator number is out of bounds");
9253 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9254 ACC_FIRST + INTVAL (opval));
9255 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9256 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9258 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9260 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9266 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9269 static enum machine_mode
9270 frv_matching_accg_mode (enum machine_mode mode)
9288 /* Return the accumulator guard that should be paired with accumulator
9289 register ACC. The mode of the returned register is in the same
9290 class as ACC, but is four times smaller. */
9293 frv_matching_accg_for_acc (rtx acc)
9295 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9296 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9299 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9300 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9304 frv_read_argument (tree *arglistptr)
9306 tree next = TREE_VALUE (*arglistptr);
9307 *arglistptr = TREE_CHAIN (*arglistptr);
9308 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9311 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9312 The instruction should require a constant operand of some sort. The
9313 function prints an error if OPVAL is not valid. */
9316 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9318 if (GET_CODE (opval) != CONST_INT)
9320 error ("`%s' expects a constant argument", insn_data[icode].name);
9323 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9325 error ("constant argument out of range for `%s'", insn_data[icode].name);
9331 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9332 if it's not null, has the right mode, and satisfies operand 0's
9336 frv_legitimize_target (enum insn_code icode, rtx target)
9338 enum machine_mode mode = insn_data[icode].operand[0].mode;
9341 || GET_MODE (target) != mode
9342 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9343 return gen_reg_rtx (mode);
9348 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9349 check whether ARG satisfies the operand's constraints. If it doesn't,
9350 copy ARG to a temporary register and return that. Otherwise return ARG
9354 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9356 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9358 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9361 return copy_to_mode_reg (mode, arg);
9364 /* Expand builtins that take a single, constant argument. At the moment,
9365 only MHDSETS falls into this category. */
9368 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9371 rtx op0 = frv_read_argument (&arglist);
9373 if (! frv_check_constant_argument (icode, 1, op0))
9376 target = frv_legitimize_target (icode, target);
9377 pat = GEN_FCN (icode) (target, op0);
9385 /* Expand builtins that take one operand. */
9388 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9391 rtx op0 = frv_read_argument (&arglist);
9393 target = frv_legitimize_target (icode, target);
9394 op0 = frv_legitimize_argument (icode, 1, op0);
9395 pat = GEN_FCN (icode) (target, op0);
9403 /* Expand builtins that take two operands. */
9406 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9409 rtx op0 = frv_read_argument (&arglist);
9410 rtx op1 = frv_read_argument (&arglist);
9412 target = frv_legitimize_target (icode, target);
9413 op0 = frv_legitimize_argument (icode, 1, op0);
9414 op1 = frv_legitimize_argument (icode, 2, op1);
9415 pat = GEN_FCN (icode) (target, op0, op1);
9423 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9427 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9430 rtx op0 = frv_read_argument (&arglist);
9431 rtx op1 = frv_read_argument (&arglist);
9434 target = frv_legitimize_target (icode, target);
9435 op0 = frv_int_to_acc (icode, 1, op0);
9439 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9441 if (! frv_check_constant_argument (icode, 2, op1))
9445 op1 = frv_legitimize_argument (icode, 2, op1);
9447 op2 = frv_matching_accg_for_acc (op0);
9448 pat = GEN_FCN (icode) (target, op0, op1, op2);
9456 /* Expand builtins that take two operands and the second is immediate. */
9459 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9462 rtx op0 = frv_read_argument (&arglist);
9463 rtx op1 = frv_read_argument (&arglist);
9465 if (! frv_check_constant_argument (icode, 2, op1))
9468 target = frv_legitimize_target (icode, target);
9469 op0 = frv_legitimize_argument (icode, 1, op0);
9470 pat = GEN_FCN (icode) (target, op0, op1);
9478 /* Expand builtins that take two operands, the first operand being a pointer to
9479 ints and return void. */
9482 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9485 rtx op0 = frv_read_argument (&arglist);
9486 rtx op1 = frv_read_argument (&arglist);
9487 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9490 if (GET_CODE (op0) != MEM)
9494 if (! offsettable_address_p (0, mode0, op0))
9496 reg = gen_reg_rtx (Pmode);
9497 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9500 op0 = gen_rtx_MEM (SImode, reg);
9503 addr = XEXP (op0, 0);
9504 if (! offsettable_address_p (0, mode0, addr))
9505 addr = copy_to_mode_reg (Pmode, op0);
9507 op0 = change_address (op0, V4SImode, addr);
9508 op1 = frv_legitimize_argument (icode, 1, op1);
9509 pat = GEN_FCN (icode) (op0, op1);
9517 /* Expand builtins that take three operands and return void. The first
9518 argument must be a constant that describes a pair or quad accumulators. A
9519 fourth argument is created that is the accumulator guard register that
9520 corresponds to the accumulator. */
9523 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9526 rtx op0 = frv_read_argument (&arglist);
9527 rtx op1 = frv_read_argument (&arglist);
9528 rtx op2 = frv_read_argument (&arglist);
9531 op0 = frv_int_to_acc (icode, 0, op0);
9535 op1 = frv_legitimize_argument (icode, 1, op1);
9536 op2 = frv_legitimize_argument (icode, 2, op2);
9537 op3 = frv_matching_accg_for_acc (op0);
9538 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9546 /* Expand builtins that perform accumulator-to-accumulator operations.
9547 These builtins take two accumulator numbers as argument and return
9551 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9554 rtx op0 = frv_read_argument (&arglist);
9555 rtx op1 = frv_read_argument (&arglist);
9559 op0 = frv_int_to_acc (icode, 0, op0);
9563 op1 = frv_int_to_acc (icode, 1, op1);
9567 op2 = frv_matching_accg_for_acc (op0);
9568 op3 = frv_matching_accg_for_acc (op1);
9569 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9577 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9578 number as argument. */
9581 frv_expand_mclracc_builtin (tree arglist)
9583 enum insn_code icode = CODE_FOR_mclracc;
9585 rtx op0 = frv_read_argument (&arglist);
9587 op0 = frv_int_to_acc (icode, 0, op0);
9591 pat = GEN_FCN (icode) (op0);
9598 /* Expand builtins that take no arguments. */
9601 frv_expand_noargs_builtin (enum insn_code icode)
9603 rtx pat = GEN_FCN (icode) (const0_rtx);
9610 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9611 number or accumulator guard number as argument and return an SI integer. */
9614 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
9617 rtx target = gen_reg_rtx (SImode);
9618 rtx op0 = frv_read_argument (&arglist);
9620 op0 = frv_int_to_acc (icode, 1, op0);
9624 pat = GEN_FCN (icode) (target, op0);
9632 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9633 accumulator guard as their first argument and an SImode value as their
9637 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
9640 rtx op0 = frv_read_argument (&arglist);
9641 rtx op1 = frv_read_argument (&arglist);
9643 op0 = frv_int_to_acc (icode, 0, op0);
9647 op1 = frv_legitimize_argument (icode, 1, op1);
9648 pat = GEN_FCN (icode) (op0, op1);
9655 /* Expand builtins. */
9658 frv_expand_builtin (tree exp,
9660 rtx subtarget ATTRIBUTE_UNUSED,
9661 enum machine_mode mode ATTRIBUTE_UNUSED,
9662 int ignore ATTRIBUTE_UNUSED)
9664 tree arglist = TREE_OPERAND (exp, 1);
9665 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9666 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9668 struct builtin_description *d;
9672 error ("media functions are not available unless -mmedia is used");
9678 case FRV_BUILTIN_MCOP1:
9679 case FRV_BUILTIN_MCOP2:
9680 case FRV_BUILTIN_MDUNPACKH:
9681 case FRV_BUILTIN_MBTOHE:
9682 if (! TARGET_MEDIA_REV1)
9684 error ("this media function is only available on the fr500");
9689 case FRV_BUILTIN_MQXMACHS:
9690 case FRV_BUILTIN_MQXMACXHS:
9691 case FRV_BUILTIN_MQMACXHS:
9692 case FRV_BUILTIN_MADDACCS:
9693 case FRV_BUILTIN_MSUBACCS:
9694 case FRV_BUILTIN_MASACCS:
9695 case FRV_BUILTIN_MDADDACCS:
9696 case FRV_BUILTIN_MDSUBACCS:
9697 case FRV_BUILTIN_MDASACCS:
9698 case FRV_BUILTIN_MABSHS:
9699 case FRV_BUILTIN_MDROTLI:
9700 case FRV_BUILTIN_MCPLHI:
9701 case FRV_BUILTIN_MCPLI:
9702 case FRV_BUILTIN_MDCUTSSI:
9703 case FRV_BUILTIN_MQSATHS:
9704 case FRV_BUILTIN_MHSETLOS:
9705 case FRV_BUILTIN_MHSETLOH:
9706 case FRV_BUILTIN_MHSETHIS:
9707 case FRV_BUILTIN_MHSETHIH:
9708 case FRV_BUILTIN_MHDSETS:
9709 case FRV_BUILTIN_MHDSETH:
9710 if (! TARGET_MEDIA_REV2)
9712 error ("this media function is only available on the fr400");
9721 /* Expand unique builtins. */
9725 case FRV_BUILTIN_MTRAP:
9726 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9728 case FRV_BUILTIN_MCLRACC:
9729 return frv_expand_mclracc_builtin (arglist);
9731 case FRV_BUILTIN_MCLRACCA:
9733 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9735 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9737 case FRV_BUILTIN_MRDACC:
9738 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9740 case FRV_BUILTIN_MRDACCG:
9741 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9743 case FRV_BUILTIN_MWTACC:
9744 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9746 case FRV_BUILTIN_MWTACCG:
9747 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9753 /* Expand groups of builtins. */
9755 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9756 if (d->code == fcode)
9757 return frv_expand_set_builtin (d->icode, arglist, target);
9759 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9760 if (d->code == fcode)
9761 return frv_expand_unop_builtin (d->icode, arglist, target);
9763 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9764 if (d->code == fcode)
9765 return frv_expand_binop_builtin (d->icode, arglist, target);
9767 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9768 if (d->code == fcode)
9769 return frv_expand_cut_builtin (d->icode, arglist, target);
9771 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9772 if (d->code == fcode)
9773 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9775 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9776 if (d->code == fcode)
9777 return frv_expand_voidbinop_builtin (d->icode, arglist);
9779 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9780 if (d->code == fcode)
9781 return frv_expand_voidtriop_builtin (d->icode, arglist);
9783 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9784 if (d->code == fcode)
9785 return frv_expand_voidaccop_builtin (d->icode, arglist);
9791 frv_in_small_data_p (tree decl)
9796 /* Don't apply the -G flag to internal compiler structures. We
9797 should leave such structures in the main data section, partly
9798 for efficiency and partly because the size of some of them
9799 (such as C++ typeinfos) is not known until later. */
9800 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9803 /* If we already know which section the decl should be in, see if
9804 it's a small data section. */
9805 section_name = DECL_SECTION_NAME (decl);
9808 if (TREE_CODE (section_name) != STRING_CST)
9810 if (frv_string_begins_with (section_name, ".sdata"))
9812 if (frv_string_begins_with (section_name, ".sbss"))
9817 size = int_size_in_bytes (TREE_TYPE (decl));
9818 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9825 frv_rtx_costs (rtx x,
9826 int code ATTRIBUTE_UNUSED,
9827 int outer_code ATTRIBUTE_UNUSED,
9830 if (outer_code == MEM)
9832 /* Don't differentiate between memory addresses. All the ones
9833 we accept have equal cost. */
9834 *total = COSTS_N_INSNS (0);
9841 /* Make 12 bit integers really cheap. */
9842 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9853 *total = COSTS_N_INSNS (2);
9867 if (GET_MODE (x) == SImode)
9868 *total = COSTS_N_INSNS (1);
9869 else if (GET_MODE (x) == DImode)
9870 *total = COSTS_N_INSNS (2);
9872 *total = COSTS_N_INSNS (3);
9876 if (GET_MODE (x) == SImode)
9877 *total = COSTS_N_INSNS (2);
9879 *total = COSTS_N_INSNS (6); /* guess */
9886 *total = COSTS_N_INSNS (18);
9890 *total = COSTS_N_INSNS (3);
9899 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9902 assemble_align (POINTER_SIZE);
9905 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9909 assemble_integer_with_op ("\t.picptr\t", symbol);
9913 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9916 assemble_align (POINTER_SIZE);
9919 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9923 assemble_integer_with_op ("\t.picptr\t", symbol);
9926 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9929 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9930 int incoming ATTRIBUTE_UNUSED)
9932 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);