1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
52 #define FRV_INLINE inline
55 /* Temporary register allocation support structure. */
56 typedef struct frv_tmp_reg_struct
58 HARD_REG_SET regs; /* possible registers to allocate */
59 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
63 /* Register state information for VLIW re-packing phase. These values must fit
64 within an unsigned char. */
65 #define REGSTATE_DEAD 0x00 /* register is currently dead */
66 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
67 #define REGSTATE_LIVE 0x08 /* register is live */
68 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
69 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
70 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
71 #define REGSTATE_UNUSED 0x80 /* bit for hire */
72 #define REGSTATE_MASK 0xff /* mask for the bits to set */
74 /* conditional expression used */
75 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
77 /* the following is not sure in the reg_state bytes, so can have a larger value
79 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
81 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
89 /* Information required by frv_frame_access. */
92 /* This field is FRV_LOAD if registers are to be loaded from the stack and
93 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
94 the move is being done by the prologue code while FRV_LOAD implies it
95 is being done by the epilogue. */
98 /* The base register to use when accessing the stack. This may be the
99 frame pointer, stack pointer, or a temporary. The choice of register
100 depends on which part of the frame is being accessed and how big the
104 /* The offset of BASE from the bottom of the current frame, in bytes. */
106 } frv_frame_accessor_t;
108 /* Define the information needed to generate branch and scc insns. This is
109 stored from the compare operation. */
113 /* Conditional execution support gathered together in one structure */
116 /* Linked list of insns to add if the conditional execution conversion was
117 successful. Each link points to an EXPR_LIST which points to the pattern
118 of the insn to add, and the insn to be inserted before. */
119 rtx added_insns_list;
121 /* Identify which registers are safe to allocate for if conversions to
122 conditional execution. We keep the last allocated register in the
123 register classes between COND_EXEC statements. This will mean we allocate
124 different registers for each different COND_EXEC group if we can. This
125 might allow the scheduler to intermix two different COND_EXEC sections. */
126 frv_tmp_reg_t tmp_reg;
128 /* For nested IFs, identify which CC registers are used outside of setting
129 via a compare isnsn, and using via a check insn. This will allow us to
130 know if we can rewrite the register to use a different register that will
131 be paired with the CR register controlling the nested IF-THEN blocks. */
132 HARD_REG_SET nested_cc_ok_rewrite;
134 /* Temporary registers allocated to hold constants during conditional
136 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
138 /* Current number of temp registers available. */
139 int cur_scratch_regs;
141 /* Number of nested conditional execution blocks */
142 int num_nested_cond_exec;
144 /* Map of insns that set up constants in scratch registers. */
145 bitmap scratch_insns_bitmap;
147 /* Conditional execution test register (CC0..CC7) */
150 /* Conditional execution compare register that is paired with cr_reg, so that
151 nested compares can be done. The csubcc and caddcc instructions don't
152 have enough bits to specify both a CC register to be set and a CR register
153 to do the test on, so the same bit number is used for both. Needless to
154 say, this is rather inconvient for GCC. */
157 /* Extra CR registers used for &&, ||. */
161 /* Previous CR used in nested if, to make sure we are dealing with the same
162 nested if as the previous statement. */
163 rtx last_nested_if_cr;
167 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
169 /* Map register number to smallest register class. */
170 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
172 /* Map class letter into register class */
173 enum reg_class reg_class_from_letter[256];
175 /* Cached value of frv_stack_info */
176 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
178 /* -mbranch-cost= support */
179 const char *frv_branch_cost_string;
180 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
183 const char *frv_cpu_string; /* -mcpu= option */
184 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
186 /* -mcond-exec-insns= support */
187 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
188 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
190 /* -mcond-exec-temps= support */
191 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
192 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
194 /* -msched-lookahead=n */
195 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
196 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
198 /* Forward references */
199 static int frv_default_flags_for_cpu PARAMS ((void));
200 static int frv_string_begins_with PARAMS ((tree, const char *));
201 static FRV_INLINE int const_small_data_p PARAMS ((rtx));
202 static FRV_INLINE int plus_small_data_p PARAMS ((rtx, rtx));
203 static void frv_print_operand_memory_reference_reg
204 PARAMS ((FILE *, rtx));
205 static void frv_print_operand_memory_reference PARAMS ((FILE *, rtx, int));
206 static int frv_print_operand_jump_hint PARAMS ((rtx));
207 static FRV_INLINE int frv_regno_ok_for_base_p PARAMS ((int, int));
208 static rtx single_set_pattern PARAMS ((rtx));
209 static int frv_function_contains_far_jump PARAMS ((void));
210 static rtx frv_alloc_temp_reg PARAMS ((frv_tmp_reg_t *,
214 static rtx frv_frame_offset_rtx PARAMS ((int));
215 static rtx frv_frame_mem PARAMS ((enum machine_mode,
217 static rtx frv_dwarf_store PARAMS ((rtx, int));
218 static void frv_frame_insn PARAMS ((rtx, rtx));
219 static void frv_frame_access PARAMS ((frv_frame_accessor_t*,
221 static void frv_frame_access_multi PARAMS ((frv_frame_accessor_t*,
222 frv_stack_t *, int));
223 static void frv_frame_access_standard_regs PARAMS ((enum frv_stack_op,
225 static struct machine_function *frv_init_machine_status PARAMS ((void));
226 static int frv_legitimate_memory_operand PARAMS ((rtx,
229 static rtx frv_int_to_acc PARAMS ((enum insn_code,
231 static enum machine_mode frv_matching_accg_mode PARAMS ((enum machine_mode));
232 static rtx frv_read_argument PARAMS ((tree *));
233 static int frv_check_constant_argument PARAMS ((enum insn_code,
235 static rtx frv_legitimize_target PARAMS ((enum insn_code, rtx));
236 static rtx frv_legitimize_argument PARAMS ((enum insn_code,
238 static rtx frv_expand_set_builtin PARAMS ((enum insn_code,
240 static rtx frv_expand_unop_builtin PARAMS ((enum insn_code,
242 static rtx frv_expand_binop_builtin PARAMS ((enum insn_code,
244 static rtx frv_expand_cut_builtin PARAMS ((enum insn_code,
246 static rtx frv_expand_binopimm_builtin PARAMS ((enum insn_code,
248 static rtx frv_expand_voidbinop_builtin PARAMS ((enum insn_code,
250 static rtx frv_expand_voidtriop_builtin PARAMS ((enum insn_code,
252 static rtx frv_expand_voidaccop_builtin PARAMS ((enum insn_code,
254 static rtx frv_expand_mclracc_builtin PARAMS ((tree));
255 static rtx frv_expand_mrdacc_builtin PARAMS ((enum insn_code,
257 static rtx frv_expand_mwtacc_builtin PARAMS ((enum insn_code,
259 static rtx frv_expand_noargs_builtin PARAMS ((enum insn_code));
260 static rtx frv_emit_comparison PARAMS ((enum rtx_code, rtx,
262 static int frv_clear_registers_used PARAMS ((rtx *, void *));
263 static void frv_ifcvt_add_insn PARAMS ((rtx, rtx, int));
264 static rtx frv_ifcvt_rewrite_mem PARAMS ((rtx,
267 static rtx frv_ifcvt_load_value PARAMS ((rtx, rtx));
268 static void frv_registers_update PARAMS ((rtx, unsigned char [],
269 int [], int *, int));
270 static int frv_registers_used_p PARAMS ((rtx, unsigned char [],
272 static int frv_registers_set_p PARAMS ((rtx, unsigned char [],
274 static void frv_pack_insns PARAMS ((void));
275 static void frv_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
276 static void frv_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
277 static bool frv_assemble_integer PARAMS ((rtx, unsigned, int));
278 static void frv_init_builtins PARAMS ((void));
279 static rtx frv_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
280 static bool frv_in_small_data_p PARAMS ((tree));
281 static void frv_asm_output_mi_thunk
282 PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree));
283 static bool frv_rtx_costs PARAMS ((rtx, int, int, int*));
284 static void frv_asm_out_constructor PARAMS ((rtx, int));
285 static void frv_asm_out_destructor PARAMS ((rtx, int));
287 /* Initialize the GCC target structure. */
288 #undef TARGET_ASM_FUNCTION_PROLOGUE
289 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
290 #undef TARGET_ASM_FUNCTION_EPILOGUE
291 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
292 #undef TARGET_ASM_INTEGER
293 #define TARGET_ASM_INTEGER frv_assemble_integer
294 #undef TARGET_INIT_BUILTINS
295 #define TARGET_INIT_BUILTINS frv_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
298 #undef TARGET_IN_SMALL_DATA_P
299 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
300 #undef TARGET_RTX_COSTS
301 #define TARGET_RTX_COSTS frv_rtx_costs
302 #undef TARGET_ASM_CONSTRUCTOR
303 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
304 #undef TARGET_ASM_DESTRUCTOR
305 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
307 #undef TARGET_ASM_OUTPUT_MI_THUNK
308 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
309 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
310 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
312 struct gcc_target targetm = TARGET_INITIALIZER;
314 /* Given a CONST, return true if the symbol_ref points to small data. */
316 static FRV_INLINE int
317 const_small_data_p (x)
322 if (GET_CODE (XEXP (x, 0)) != PLUS)
325 x0 = XEXP (XEXP (x, 0), 0);
326 if (GET_CODE (x0) != SYMBOL_REF || !SYMBOL_REF_SMALL_P (x0))
329 x1 = XEXP (XEXP (x, 0), 1);
330 if (GET_CODE (x1) != CONST_INT
331 || !IN_RANGE_P (INTVAL (x1), -2048, 2047))
337 /* Given a PLUS, return true if this is a small data reference. */
339 static FRV_INLINE int
340 plus_small_data_p (op0, op1)
344 if (GET_MODE (op0) == SImode
345 && GET_CODE (op0) == REG
346 && REGNO (op0) == SDA_BASE_REG)
348 if (GET_CODE (op1) == SYMBOL_REF)
349 return SYMBOL_REF_SMALL_P (op1);
351 if (GET_CODE (op1) == CONST)
352 return const_small_data_p (op1);
360 frv_default_flags_for_cpu ()
362 switch (frv_cpu_type)
364 case FRV_CPU_GENERIC:
365 return MASK_DEFAULT_FRV;
369 return MASK_DEFAULT_FR500;
372 return MASK_DEFAULT_FR400;
376 return MASK_DEFAULT_SIMPLE;
381 /* Sometimes certain combinations of command options do not make
382 sense on a particular target machine. You can define a macro
383 `OVERRIDE_OPTIONS' to take account of this. This macro, if
384 defined, is executed once just after all the command options have
387 Don't use this macro to turn on various extra optimizations for
388 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
391 frv_override_options ()
395 /* Set the cpu type */
398 if (strcmp (frv_cpu_string, "simple") == 0)
399 frv_cpu_type = FRV_CPU_SIMPLE;
401 else if (strcmp (frv_cpu_string, "tomcat") == 0)
402 frv_cpu_type = FRV_CPU_TOMCAT;
404 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
405 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
409 const char *p = frv_cpu_string + sizeof ("fr") - 1;
410 if (strcmp (p, "500") == 0)
411 frv_cpu_type = FRV_CPU_FR500;
413 else if (strcmp (p, "400") == 0)
414 frv_cpu_type = FRV_CPU_FR400;
416 else if (strcmp (p, "300") == 0)
417 frv_cpu_type = FRV_CPU_FR300;
419 else if (strcmp (p, "v") == 0)
420 frv_cpu_type = FRV_CPU_GENERIC;
423 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
427 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
429 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
430 linker about linking pic and non-pic code. */
433 if (!flag_pic) /* -fPIC */
436 if (! g_switch_set) /* -G0 */
443 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
445 if (write_symbols == DWARF_DEBUG && flag_pic)
446 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
448 /* Change the branch cost value */
449 if (frv_branch_cost_string)
450 frv_branch_cost_int = atoi (frv_branch_cost_string);
452 /* Change the # of insns to be converted to conditional execution */
453 if (frv_condexec_insns_str)
454 frv_condexec_insns = atoi (frv_condexec_insns_str);
456 /* Change # of temporary registers used to hold integer constants */
457 if (frv_condexec_temps_str)
458 frv_condexec_temps = atoi (frv_condexec_temps_str);
460 /* Change scheduling look ahead. */
461 if (frv_sched_lookahead_str)
462 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
464 /* A C expression whose value is a register class containing hard
465 register REGNO. In general there is more than one such class;
466 choose a class which is "minimal", meaning that no smaller class
467 also contains the register. */
469 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
471 enum reg_class class;
475 int gpr_reg = regno - GPR_FIRST;
476 if ((gpr_reg & 3) == 0)
479 else if ((gpr_reg & 1) == 0)
486 else if (FPR_P (regno))
488 int fpr_reg = regno - GPR_FIRST;
489 if ((fpr_reg & 3) == 0)
490 class = QUAD_FPR_REGS;
492 else if ((fpr_reg & 1) == 0)
499 else if (regno == LR_REGNO)
502 else if (regno == LCR_REGNO)
505 else if (ICC_P (regno))
508 else if (FCC_P (regno))
511 else if (ICR_P (regno))
514 else if (FCR_P (regno))
517 else if (ACC_P (regno))
519 int r = regno - ACC_FIRST;
521 class = QUAD_ACC_REGS;
522 else if ((r & 1) == 0)
523 class = EVEN_ACC_REGS;
528 else if (ACCG_P (regno))
534 regno_reg_class[regno] = class;
537 /* Check for small data option */
539 g_switch_value = SDATA_DEFAULT_SIZE;
541 /* A C expression which defines the machine-dependent operand
542 constraint letters for register classes. If CHAR is such a
543 letter, the value should be the register class corresponding to
544 it. Otherwise, the value should be `NO_REGS'. The register
545 letter `r', corresponding to class `GENERAL_REGS', will not be
546 passed to this macro; you do not need to handle it.
548 The following letters are unavailable, due to being used as
553 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
554 'Q', 'R', 'S', 'T', 'U'
556 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
558 for (i = 0; i < 256; i++)
559 reg_class_from_letter[i] = NO_REGS;
561 reg_class_from_letter['a'] = ACC_REGS;
562 reg_class_from_letter['b'] = EVEN_ACC_REGS;
563 reg_class_from_letter['c'] = CC_REGS;
564 reg_class_from_letter['d'] = GPR_REGS;
565 reg_class_from_letter['e'] = EVEN_REGS;
566 reg_class_from_letter['f'] = FPR_REGS;
567 reg_class_from_letter['h'] = FEVEN_REGS;
568 reg_class_from_letter['l'] = LR_REG;
569 reg_class_from_letter['q'] = QUAD_REGS;
570 reg_class_from_letter['t'] = ICC_REGS;
571 reg_class_from_letter['u'] = FCC_REGS;
572 reg_class_from_letter['v'] = ICR_REGS;
573 reg_class_from_letter['w'] = FCR_REGS;
574 reg_class_from_letter['x'] = QUAD_FPR_REGS;
575 reg_class_from_letter['y'] = LCR_REG;
576 reg_class_from_letter['z'] = SPR_REGS;
577 reg_class_from_letter['A'] = QUAD_ACC_REGS;
578 reg_class_from_letter['B'] = ACCG_REGS;
579 reg_class_from_letter['C'] = CR_REGS;
581 /* There is no single unaligned SI op for PIC code. Sometimes we
582 need to use ".4byte" and sometimes we need to use ".picptr".
583 See frv_assemble_integer for details. */
585 targetm.asm_out.unaligned_op.si = 0;
587 init_machine_status = frv_init_machine_status;
591 /* Some machines may desire to change what optimizations are performed for
592 various optimization levels. This macro, if defined, is executed once just
593 after the optimization level is determined and before the remainder of the
594 command options have been parsed. Values set in this macro are used as the
595 default values for the other command line options.
597 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
598 `-O' is specified, and 0 if neither is specified.
600 SIZE is nonzero if `-Os' is specified, 0 otherwise.
602 You should not use this macro to change options that are not
603 machine-specific. These should uniformly selected by the same optimization
604 level on all supported machines. Use this macro to enable machbine-specific
607 *Do not examine `write_symbols' in this macro!* The debugging options are
608 *not supposed to alter the generated code. */
610 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
611 scheduling pass at the current time. */
613 frv_optimization_options (level, size)
615 int size ATTRIBUTE_UNUSED;
619 #ifdef DISABLE_SCHED2
620 flag_schedule_insns_after_reload = 0;
629 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
632 frv_string_begins_with (name, prefix)
636 int prefix_len = strlen (prefix);
638 /* Remember: NAME's length includes the null terminator. */
639 return (TREE_STRING_LENGTH (name) > prefix_len
640 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
643 /* Zero or more C statements that may conditionally modify two variables
644 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
645 been initialized from the two preceding macros.
647 This is necessary in case the fixed or call-clobbered registers depend on
650 You need not define this macro if it has no work to do.
652 If the usage of an entire class of registers depends on the target flags,
653 you may indicate this to GCC by using this macro to modify `fixed_regs' and
654 `call_used_regs' to 1 for each of the registers in the classes which should
655 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
656 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
658 (However, if this class is not included in `GENERAL_REGS' and all of the
659 insn patterns whose constraints permit this class are controlled by target
660 switches, then GCC will automatically avoid using these registers when the
661 target switches are opposed to them.) */
664 frv_conditional_register_usage ()
668 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
669 fixed_regs[i] = call_used_regs[i] = 1;
671 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
672 fixed_regs[i] = call_used_regs[i] = 1;
674 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
675 fixed_regs[i] = call_used_regs[i] = 1;
677 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
678 fixed_regs[i] = call_used_regs[i] = 1;
680 /* Reserve the registers used for conditional execution. At present, we need
681 1 ICC and 1 ICR register. */
682 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
683 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
687 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
688 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
689 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
690 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
694 /* If -fpic, SDA_BASE_REG is the PIC register. */
695 if (g_switch_value == 0 && !flag_pic)
696 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
699 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
705 * Compute the stack frame layout
708 * +---------------+-----------------------+-----------------------+
709 * |Register |type |caller-save/callee-save|
710 * +---------------+-----------------------+-----------------------+
711 * |GR0 |Zero register | - |
712 * |GR1 |Stack pointer(SP) | - |
713 * |GR2 |Frame pointer(FP) | - |
714 * |GR3 |Hidden parameter | caller save |
715 * |GR4-GR7 | - | caller save |
716 * |GR8-GR13 |Argument register | caller save |
717 * |GR14-GR15 | - | caller save |
718 * |GR16-GR31 | - | callee save |
719 * |GR32-GR47 | - | caller save |
720 * |GR48-GR63 | - | callee save |
721 * |FR0-FR15 | - | caller save |
722 * |FR16-FR31 | - | callee save |
723 * |FR32-FR47 | - | caller save |
724 * |FR48-FR63 | - | callee save |
725 * +---------------+-----------------------+-----------------------+
729 * SP-> |-----------------------------------|
731 * |-----------------------------------|
732 * | Register save area |
733 * |-----------------------------------|
734 * | Local variable save area |
735 * FP-> |-----------------------------------|
737 * |-----------------------------------|
738 * | Hidden parameter save area |
739 * |-----------------------------------|
740 * | Return address(LR) storage area |
741 * |-----------------------------------|
742 * | Padding for alignment |
743 * |-----------------------------------|
744 * | Register argument area |
745 * OLD SP-> |-----------------------------------|
747 * |-----------------------------------|
750 * Argument area/Parameter area:
752 * When a function is called, this area is used for argument transfer. When
753 * the argument is set up by the caller function, this area is referred to as
754 * the argument area. When the argument is referenced by the callee function,
755 * this area is referred to as the parameter area. The area is allocated when
756 * all arguments cannot be placed on the argument register at the time of
759 * Register save area:
761 * This is a register save area that must be guaranteed for the caller
762 * function. This area is not secured when the register save operation is not
765 * Local variable save area:
767 * This is the area for local variables and temporary variables.
771 * This area stores the FP value of the caller function.
773 * Hidden parameter save area:
775 * This area stores the start address of the return value storage
776 * area for a struct/union return function.
777 * When a struct/union is used as the return value, the caller
778 * function stores the return value storage area start address in
779 * register GR3 and passes it to the caller function.
780 * The callee function interprets the address stored in the GR3
781 * as the return value storage area start address.
782 * When register GR3 needs to be saved into memory, the callee
783 * function saves it in the hidden parameter save area. This
784 * area is not secured when the save operation is not needed.
786 * Return address(LR) storage area:
788 * This area saves the LR. The LR stores the address of a return to the caller
789 * function for the purpose of function calling.
791 * Argument register area:
793 * This area saves the argument register. This area is not secured when the
794 * save operation is not needed.
798 * Arguments, the count of which equals the count of argument registers (6
799 * words), are positioned in registers GR8 to GR13 and delivered to the callee
800 * function. When a struct/union return function is called, the return value
801 * area address is stored in register GR3. Arguments not placed in the
802 * argument registers will be stored in the stack argument area for transfer
803 * purposes. When an 8-byte type argument is to be delivered using registers,
804 * it is divided into two and placed in two registers for transfer. When
805 * argument registers must be saved to memory, the callee function secures an
806 * argument register save area in the stack. In this case, a continuous
807 * argument register save area must be established in the parameter area. The
808 * argument register save area must be allocated as needed to cover the size of
809 * the argument register to be saved. If the function has a variable count of
810 * arguments, it saves all argument registers in the argument register save
813 * Argument Extension Format:
815 * When an argument is to be stored in the stack, its type is converted to an
816 * extended type in accordance with the individual argument type. The argument
817 * is freed by the caller function after the return from the callee function is
820 * +-----------------------+---------------+------------------------+
821 * | Argument Type |Extended Type |Stack Storage Size(byte)|
822 * +-----------------------+---------------+------------------------+
824 * |signed char |int | 4 |
825 * |unsigned char |int | 4 |
826 * |[signed] short int |int | 4 |
827 * |unsigned short int |int | 4 |
828 * |[signed] int |No extension | 4 |
829 * |unsigned int |No extension | 4 |
830 * |[signed] long int |No extension | 4 |
831 * |unsigned long int |No extension | 4 |
832 * |[signed] long long int |No extension | 8 |
833 * |unsigned long long int |No extension | 8 |
834 * |float |double | 8 |
835 * |double |No extension | 8 |
836 * |long double |No extension | 8 |
837 * |pointer |No extension | 4 |
838 * |struct/union |- | 4 (*1) |
839 * +-----------------------+---------------+------------------------+
841 * When a struct/union is to be delivered as an argument, the caller copies it
842 * to the local variable area and delivers the address of that area.
846 * +-------------------------------+----------------------+
847 * |Return Value Type |Return Value Interface|
848 * +-------------------------------+----------------------+
850 * |[signed|unsigned] char |GR8 |
851 * |[signed|unsigned] short int |GR8 |
852 * |[signed|unsigned] int |GR8 |
853 * |[signed|unsigned] long int |GR8 |
855 * |[signed|unsigned] long long int|GR8 & GR9 |
857 * |double |GR8 & GR9 |
858 * |long double |GR8 & GR9 |
859 * |struct/union |(*1) |
860 * +-------------------------------+----------------------+
862 * When a struct/union is used as the return value, the caller function stores
863 * the start address of the return value storage area into GR3 and then passes
864 * it to the callee function. The callee function interprets GR3 as the start
865 * address of the return value storage area. When this address needs to be
866 * saved in memory, the callee function secures the hidden parameter save area
867 * and saves the address in that area.
873 static frv_stack_t info, zero_info;
874 frv_stack_t *info_ptr = &info;
875 tree fndecl = current_function_decl;
883 /* If we've already calculated the values and reload is complete, just return now */
885 return frv_stack_cache;
887 /* Zero all fields */
890 /* Set up the register range information */
891 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
892 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
893 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
894 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
896 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
897 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
898 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
899 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
901 info_ptr->regs[STACK_REGS_LR].name = "lr";
902 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
903 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
904 info_ptr->regs[STACK_REGS_LR].special_p = 1;
906 info_ptr->regs[STACK_REGS_CC].name = "cc";
907 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
908 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
909 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
911 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
912 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
913 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
915 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
916 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
917 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
918 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
919 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
921 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
922 info_ptr->regs[STACK_REGS_STRUCT].first = STRUCT_VALUE_REGNUM;
923 info_ptr->regs[STACK_REGS_STRUCT].last = STRUCT_VALUE_REGNUM;
924 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
926 info_ptr->regs[STACK_REGS_FP].name = "fp";
927 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
928 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
929 info_ptr->regs[STACK_REGS_FP].special_p = 1;
931 /* Determine if this is a stdarg function. If so, allocate space to store
938 /* Find the last argument, and see if it is __builtin_va_alist. */
939 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
941 next_arg = TREE_CHAIN (cur_arg);
942 if (next_arg == (tree)0)
944 if (DECL_NAME (cur_arg)
945 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
953 /* Iterate over all of the register ranges */
954 for (range = 0; range < STACK_REGS_MAX; range++)
956 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
957 int first = reg_ptr->first;
958 int last = reg_ptr->last;
963 /* Calculate which registers need to be saved & save area size */
967 for (regno = first; regno <= last; regno++)
969 if ((regs_ever_live[regno] && !call_used_regs[regno])
970 || (current_function_calls_eh_return
971 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
972 || (flag_pic && cfun->uses_pic_offset_table && regno == PIC_REGNO))
974 info_ptr->save_p[regno] = REG_SAVE_1WORD;
975 size_1word += UNITS_PER_WORD;
980 /* Calculate whether we need to create a frame after everything else
981 has been processed. */
986 if (regs_ever_live[LR_REGNO]
988 || frame_pointer_needed
989 || (flag_pic && cfun->uses_pic_offset_table))
991 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
992 size_1word += UNITS_PER_WORD;
996 case STACK_REGS_STDARG:
999 /* If this is a stdarg function with a non varardic argument split
1000 between registers and the stack, adjust the saved registers
1002 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1005 for (regno = first; regno <= last; regno++)
1007 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1008 size_1word += UNITS_PER_WORD;
1011 info_ptr->stdarg_size = size_1word;
1015 case STACK_REGS_STRUCT:
1016 if (cfun->returns_struct)
1018 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1019 size_1word += UNITS_PER_WORD;
1027 /* If this is a field, it only takes one word */
1028 if (reg_ptr->field_p)
1029 size_1word = UNITS_PER_WORD;
1031 /* Determine which register pairs can be saved together */
1032 else if (reg_ptr->dword_p && TARGET_DWORD)
1034 for (regno = first; regno < last; regno += 2)
1036 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1038 size_2words += 2 * UNITS_PER_WORD;
1039 size_1word -= 2 * UNITS_PER_WORD;
1040 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1041 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1046 reg_ptr->size_1word = size_1word;
1047 reg_ptr->size_2words = size_2words;
1049 if (! reg_ptr->special_p)
1051 info_ptr->regs_size_1word += size_1word;
1052 info_ptr->regs_size_2words += size_2words;
1057 /* Set up the sizes of each each field in the frame body, making the sizes
1058 of each be divisible by the size of a dword if dword operations might
1059 be used, or the size of a word otherwise. */
1060 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1062 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1063 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1064 + info_ptr->regs_size_1word,
1066 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1068 info_ptr->pretend_size = cfun->pretend_args_size;
1070 /* Work out the size of the frame, excluding the header. Both the frame
1071 body and register parameter area will be dword-aligned. */
1072 info_ptr->total_size
1073 = (ADDR_ALIGN (info_ptr->parameter_size
1074 + info_ptr->regs_size
1075 + info_ptr->vars_size,
1077 + ADDR_ALIGN (info_ptr->pretend_size
1078 + info_ptr->stdarg_size,
1079 2 * UNITS_PER_WORD));
1081 /* See if we need to create a frame at all, if so add header area. */
1082 if (info_ptr->total_size > 0
1083 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1084 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1086 offset = info_ptr->parameter_size;
1087 info_ptr->header_size = 4 * UNITS_PER_WORD;
1088 info_ptr->total_size += 4 * UNITS_PER_WORD;
1090 /* Calculate the offsets to save normal register pairs */
1091 for (range = 0; range < STACK_REGS_MAX; range++)
1093 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1094 if (! reg_ptr->special_p)
1096 int first = reg_ptr->first;
1097 int last = reg_ptr->last;
1100 for (regno = first; regno <= last; regno++)
1101 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1102 && regno != FRAME_POINTER_REGNUM
1103 && (regno < FIRST_ARG_REGNUM
1104 || regno > LAST_ARG_REGNUM))
1106 info_ptr->reg_offset[regno] = offset;
1107 offset += 2 * UNITS_PER_WORD;
1112 /* Calculate the offsets to save normal single registers */
1113 for (range = 0; range < STACK_REGS_MAX; range++)
1115 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1116 if (! reg_ptr->special_p)
1118 int first = reg_ptr->first;
1119 int last = reg_ptr->last;
1122 for (regno = first; regno <= last; regno++)
1123 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1124 && regno != FRAME_POINTER_REGNUM
1125 && (regno < FIRST_ARG_REGNUM
1126 || regno > LAST_ARG_REGNUM))
1128 info_ptr->reg_offset[regno] = offset;
1129 offset += UNITS_PER_WORD;
1134 /* Calculate the offset to save the local variables at. */
1135 offset = ADDR_ALIGN (offset, alignment);
1136 if (info_ptr->vars_size)
1138 info_ptr->vars_offset = offset;
1139 offset += info_ptr->vars_size;
1142 /* Align header to a dword-boundary. */
1143 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1145 /* Calculate the offsets in the fixed frame. */
1146 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1147 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1148 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1150 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1151 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1152 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1154 if (cfun->returns_struct)
1156 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1157 info_ptr->reg_offset[STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1158 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1161 /* Calculate the offsets to store the arguments passed in registers
1162 for stdarg functions. The register pairs are first and the single
1163 register if any is last. The register save area starts on a
1165 if (info_ptr->stdarg_size)
1167 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1168 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1171 /* Skip the header. */
1172 offset += 4 * UNITS_PER_WORD;
1173 for (regno = first; regno <= last; regno++)
1175 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1177 info_ptr->reg_offset[regno] = offset;
1178 offset += 2 * UNITS_PER_WORD;
1180 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1182 info_ptr->reg_offset[regno] = offset;
1183 offset += UNITS_PER_WORD;
1189 if (reload_completed)
1190 frv_stack_cache = info_ptr;
1196 /* Print the information about the frv stack offsets, etc. when debugging. */
1199 frv_debug_stack (info)
1205 info = frv_stack_info ();
1207 fprintf (stderr, "\nStack information for function %s:\n",
1208 ((current_function_decl && DECL_NAME (current_function_decl))
1209 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1212 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1213 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1214 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1215 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1216 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1218 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1219 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1220 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1221 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1223 for (range = 0; range < STACK_REGS_MAX; range++)
1225 frv_stack_regs_t *regs = &(info->regs[range]);
1226 if ((regs->size_1word + regs->size_2words) > 0)
1228 int first = regs->first;
1229 int last = regs->last;
1232 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1233 regs->name, regs->size_1word + regs->size_2words,
1234 regs->size_1word, regs->size_2words);
1236 for (regno = first; regno <= last; regno++)
1238 if (info->save_p[regno] == REG_SAVE_1WORD)
1239 fprintf (stderr, " %s (%d)", reg_names[regno],
1240 info->reg_offset[regno]);
1242 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1243 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1244 reg_names[regno+1], info->reg_offset[regno]);
1247 fputc ('\n', stderr);
1257 /* The following variable value is TRUE if the next output insn should
1258 finish cpu cycle. In order words the insn will have packing bit
1259 (which means absence of asm code suffix `.p' on assembler. */
1261 static int frv_insn_packing_flag;
1263 /* True if the current function contains a far jump. */
1266 frv_function_contains_far_jump ()
1268 rtx insn = get_insns ();
1270 && !(GET_CODE (insn) == JUMP_INSN
1271 /* Ignore tablejump patterns. */
1272 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1273 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1274 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1275 insn = NEXT_INSN (insn);
1276 return (insn != NULL);
1279 /* For the FRV, this function makes sure that a function with far jumps
1280 will return correctly. It also does the VLIW packing. */
1283 frv_function_prologue (file, size)
1285 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1287 /* If no frame was created, check whether the function uses a call
1288 instruction to implement a far jump. If so, save the link in gr3 and
1289 replace all returns to LR with returns to GR3. GR3 is used because it
1290 is call-clobbered, because is not available to the register allocator,
1291 and because all functions that take a hidden argument pointer will have
1293 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1297 /* Just to check that the above comment is true. */
1298 if (regs_ever_live[GPR_FIRST + 3])
1301 /* Generate the instruction that saves the link register. */
1302 fprintf (file, "\tmovsg lr,gr3\n");
1304 /* Replace the LR with GR3 in *return_internal patterns. The insn
1305 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1306 simply emit a different assembly directive because bralr and jmpl
1307 execute in different units. */
1308 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1309 if (GET_CODE (insn) == JUMP_INSN)
1311 rtx pattern = PATTERN (insn);
1312 if (GET_CODE (pattern) == PARALLEL
1313 && XVECLEN (pattern, 0) >= 2
1314 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1315 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1317 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1318 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1319 REGNO (address) = GPR_FIRST + 3;
1325 frv_insn_packing_flag = TRUE;
1329 /* Return the next available temporary register in a given class. */
1332 frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort)
1333 frv_tmp_reg_t *info; /* which registers are available */
1334 enum reg_class class; /* register class desired */
1335 enum machine_mode mode; /* mode to allocate register with */
1336 int mark_as_used; /* register not available after allocation */
1337 int no_abort; /* return NULL instead of aborting */
1339 int regno = info->next_reg[ (int)class ];
1340 int orig_regno = regno;
1341 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1346 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1347 && TEST_HARD_REG_BIT (info->regs, regno))
1350 if (++regno >= FIRST_PSEUDO_REGISTER)
1352 if (regno == orig_regno)
1361 nr = HARD_REGNO_NREGS (regno, mode);
1362 info->next_reg[ (int)class ] = regno + nr;
1365 for (i = 0; i < nr; i++)
1366 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1368 return gen_rtx_REG (mode, regno);
1372 /* Return an rtx with the value OFFSET, which will either be a register or a
1373 signed 12-bit integer. It can be used as the second operand in an "add"
1374 instruction, or as the index in a load or store.
1376 The function returns a constant rtx if OFFSET is small enough, otherwise
1377 it loads the constant into register OFFSET_REGNO and returns that. */
1379 frv_frame_offset_rtx (offset)
1382 rtx offset_rtx = GEN_INT (offset);
1383 if (IN_RANGE_P (offset, -2048, 2047))
1387 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1388 if (IN_RANGE_P (offset, -32768, 32767))
1389 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1392 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1393 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1399 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1400 prologue and epilogue uses such expressions to access the stack. */
1402 frv_frame_mem (mode, base, offset)
1403 enum machine_mode mode;
1407 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1409 frv_frame_offset_rtx (offset)));
1412 /* Generate a frame-related expression:
1414 (set REG (mem (plus (sp) (const_int OFFSET)))).
1416 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1417 instructions. Marking the expressions as frame-related is superfluous if
1418 the note contains just a single set. But if the note contains a PARALLEL
1419 or SEQUENCE that has several sets, each set must be individually marked
1420 as frame-related. */
1422 frv_dwarf_store (reg, offset)
1426 rtx set = gen_rtx_SET (VOIDmode,
1427 gen_rtx_MEM (GET_MODE (reg),
1428 plus_constant (stack_pointer_rtx,
1431 RTX_FRAME_RELATED_P (set) = 1;
1435 /* Emit a frame-related instruction whose pattern is PATTERN. The
1436 instruction is the last in a sequence that cumulatively performs the
1437 operation described by DWARF_PATTERN. The instruction is marked as
1438 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1441 frv_frame_insn (pattern, dwarf_pattern)
1445 rtx insn = emit_insn (pattern);
1446 RTX_FRAME_RELATED_P (insn) = 1;
1447 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1452 /* Emit instructions that transfer REG to or from the memory location (sp +
1453 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1454 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1455 function to store registers and only the epilogue uses it to load them.
1457 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1458 The generated instruction will use BASE as its base register. BASE may
1459 simply be the stack pointer, but if several accesses are being made to a
1460 region far away from the stack pointer, it may be more efficient to set
1461 up a temporary instead.
1463 Store instructions will be frame-related and will be annotated with the
1464 overall effect of the store. Load instructions will be followed by a
1465 (use) to prevent later optimizations from zapping them.
1467 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1468 as a temporary in such cases. */
1470 frv_frame_access (accessor, reg, stack_offset)
1471 frv_frame_accessor_t *accessor;
1475 enum machine_mode mode = GET_MODE (reg);
1476 rtx mem = frv_frame_mem (mode,
1478 stack_offset - accessor->base_offset);
1480 if (accessor->op == FRV_LOAD)
1482 if (SPR_P (REGNO (reg)))
1484 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1485 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1486 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1489 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1490 emit_insn (gen_rtx_USE (VOIDmode, reg));
1494 if (SPR_P (REGNO (reg)))
1496 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1497 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1498 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1499 frv_dwarf_store (reg, stack_offset));
1501 else if (GET_MODE (reg) == DImode)
1503 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1504 with a separate save for each register. */
1505 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1506 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1507 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1508 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1509 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1510 gen_rtx_PARALLEL (VOIDmode,
1511 gen_rtvec (2, set1, set2)));
1514 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1515 frv_dwarf_store (reg, stack_offset));
1519 /* A function that uses frv_frame_access to transfer a group of registers to
1520 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1521 is the stack information generated by frv_stack_info, and REG_SET is the
1522 number of the register set to transfer. */
1524 frv_frame_access_multi (accessor, info, reg_set)
1525 frv_frame_accessor_t *accessor;
1529 frv_stack_regs_t *regs_info;
1532 regs_info = &info->regs[reg_set];
1533 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1534 if (info->save_p[regno])
1535 frv_frame_access (accessor,
1536 info->save_p[regno] == REG_SAVE_2WORDS
1537 ? gen_rtx_REG (DImode, regno)
1538 : gen_rtx_REG (SImode, regno),
1539 info->reg_offset[regno]);
1542 /* Save or restore callee-saved registers that are kept outside the frame
1543 header. The function saves the registers if OP is FRV_STORE and restores
1544 them if OP is FRV_LOAD. INFO is the stack information generated by
1547 frv_frame_access_standard_regs (op, info)
1548 enum frv_stack_op op;
1551 frv_frame_accessor_t accessor;
1554 accessor.base = stack_pointer_rtx;
1555 accessor.base_offset = 0;
1556 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1557 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1558 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1562 /* Called after register allocation to add any instructions needed for the
1563 prologue. Using a prologue insn is favored compared to putting all of the
1564 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1565 to intermix instructions with the saves of the caller saved registers. In
1566 some cases, it might be necessary to emit a barrier instruction as the last
1567 insn to prevent such scheduling.
1569 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1570 so that the debug info generation code can handle them properly. */
1572 frv_expand_prologue ()
1574 frv_stack_t *info = frv_stack_info ();
1575 rtx sp = stack_pointer_rtx;
1576 rtx fp = frame_pointer_rtx;
1577 frv_frame_accessor_t accessor;
1579 if (TARGET_DEBUG_STACK)
1580 frv_debug_stack (info);
1582 if (info->total_size == 0)
1585 /* We're interested in three areas of the frame here:
1587 A: the register save area
1589 C: the header after B
1591 If the frame pointer isn't used, we'll have to set up A, B and C
1592 using the stack pointer. If the frame pointer is used, we'll access
1596 B: set up using sp or a temporary (see below)
1599 We set up B using the stack pointer if the frame is small enough.
1600 Otherwise, it's more efficient to copy the old stack pointer into a
1601 temporary and use that.
1603 Note that it's important to make sure the prologue and epilogue use the
1604 same registers to access A and C, since doing otherwise will confuse
1605 the aliasing code. */
1607 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1608 isn't used, the same method will serve for C. */
1609 accessor.op = FRV_STORE;
1610 if (frame_pointer_needed && info->total_size > 2048)
1614 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1615 accessor.base_offset = info->total_size;
1616 insn = emit_insn (gen_movsi (accessor.base, sp));
1620 accessor.base = stack_pointer_rtx;
1621 accessor.base_offset = 0;
1624 /* Allocate the stack space. */
1626 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1627 rtx dwarf_offset = GEN_INT (-info->total_size);
1629 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1632 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1635 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1636 and point the new one to that location. */
1637 if (frame_pointer_needed)
1639 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1641 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1642 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1644 rtx asm_src = plus_constant (accessor.base,
1645 fp_offset - accessor.base_offset);
1646 rtx dwarf_src = plus_constant (sp, fp_offset);
1648 /* Store the old frame pointer at (sp + FP_OFFSET). */
1649 frv_frame_access (&accessor, fp, fp_offset);
1651 /* Set up the new frame pointer. */
1652 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1653 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1655 /* Access region C from the frame pointer. */
1657 accessor.base_offset = fp_offset;
1660 /* Set up region C. */
1661 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1662 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1663 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1665 /* Set up region A. */
1666 frv_frame_access_standard_regs (FRV_STORE, info);
1668 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1669 scheduler from moving loads before the stores saving the registers. */
1670 if (info->stdarg_size > 0)
1671 emit_insn (gen_blockage ());
1673 /* Set up pic register/small data register for this function. */
1674 if (flag_pic && cfun->uses_pic_offset_table)
1675 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1676 gen_rtx_REG (Pmode, LR_REGNO),
1677 gen_rtx_REG (SImode, OFFSET_REGNO)));
1681 /* Under frv, all of the work is done via frv_expand_epilogue, but
1682 this function provides a convient place to do cleanup. */
1685 frv_function_epilogue (file, size)
1686 FILE *file ATTRIBUTE_UNUSED;
1687 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1689 frv_stack_cache = (frv_stack_t *)0;
1691 /* zap last used registers for conditional execution. */
1692 memset ((PTR) &frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1694 /* release the bitmap of created insns. */
1695 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1699 /* Called after register allocation to add any instructions needed for the
1700 epilogue. Using an epilogue insn is favored compared to putting all of the
1701 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1702 to intermix instructions with the saves of the caller saved registers. In
1703 some cases, it might be necessary to emit a barrier instruction as the last
1704 insn to prevent such scheduling.
1706 If SIBCALL_P is true, the final branch back to the calling function is
1707 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1708 we must not clobber any arguments used for parameter passing or any stack
1709 slots for arguments passed to the current function. */
1712 frv_expand_epilogue (sibcall_p)
1715 frv_stack_t *info = frv_stack_info ();
1716 rtx fp = frame_pointer_rtx;
1717 rtx sp = stack_pointer_rtx;
1721 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1723 /* Restore the stack pointer to its original value if alloca or the like
1725 if (! current_function_sp_is_unchanging)
1726 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1728 /* Restore the callee-saved registers that were used in this function. */
1729 frv_frame_access_standard_regs (FRV_LOAD, info);
1731 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1732 no return instruction should be emitted. */
1735 else if (info->save_p[LR_REGNO])
1740 /* Use the same method to access the link register's slot as we did in
1741 the prologue. In other words, use the frame pointer if available,
1742 otherwise use the stack pointer.
1744 LR_OFFSET is the offset of the link register's slot from the start
1745 of the frame and MEM is a memory rtx for it. */
1746 lr_offset = info->reg_offset[LR_REGNO];
1747 if (frame_pointer_needed)
1748 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1750 mem = frv_frame_mem (Pmode, sp, lr_offset);
1752 /* Load the old link register into a GPR. */
1753 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1754 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1757 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1759 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1760 the load is preserved. */
1761 if (frame_pointer_needed)
1763 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1764 emit_insn (gen_rtx_USE (VOIDmode, fp));
1767 /* Deallocate the stack frame. */
1768 if (info->total_size != 0)
1770 rtx offset = frv_frame_offset_rtx (info->total_size);
1771 emit_insn (gen_stack_adjust (sp, sp, offset));
1774 /* If this function uses eh_return, add the final stack adjustment now. */
1775 if (current_function_calls_eh_return)
1776 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1779 emit_jump_insn (gen_epilogue_return (return_addr));
1783 /* A C compound statement that outputs the assembler code for a thunk function,
1784 used to implement C++ virtual function calls with multiple inheritance. The
1785 thunk acts as a wrapper around a virtual function, adjusting the implicit
1786 object parameter before handing control off to the real function.
1788 First, emit code to add the integer DELTA to the location that contains the
1789 incoming first argument. Assume that this argument contains a pointer, and
1790 is the one used to pass the `this' pointer in C++. This is the incoming
1791 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1792 addition must preserve the values of all other incoming arguments.
1794 After the addition, emit code to jump to FUNCTION, which is a
1795 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1796 the return address. Hence returning from FUNCTION will return to whoever
1797 called the current `thunk'.
1799 The effect must be as if FUNCTION had been called directly with the adjusted
1800 first argument. This macro is responsible for emitting all of the code for
1801 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1804 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1805 extracted from it.) It might possibly be useful on some targets, but
1808 If you do not define this macro, the target-independent code in the C++
1809 frontend will generate a less efficient heavyweight thunk that calls
1810 FUNCTION instead of jumping to it. The generic approach does not support
1814 frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
1816 tree thunk_fndecl ATTRIBUTE_UNUSED;
1817 HOST_WIDE_INT delta;
1818 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
1821 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1822 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1823 const char *name_jmp = reg_names[JUMP_REGNO];
1824 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1826 /* Do the add using an addi if possible */
1827 if (IN_RANGE_P (delta, -2048, 2047))
1828 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1831 const char *name_add = reg_names[TEMP_REGNO];
1832 fprintf (file, "\tsethi%s #hi(", parallel);
1833 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1834 fprintf (file, "),%s\n", name_add);
1835 fprintf (file, "\tsetlo #lo(");
1836 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
1837 fprintf (file, "),%s\n", name_add);
1838 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1843 fprintf (file, "\tsethi%s #hi(", parallel);
1844 assemble_name (file, name_func);
1845 fprintf (file, "),%s\n", name_jmp);
1847 fprintf (file, "\tsetlo #lo(");
1848 assemble_name (file, name_func);
1849 fprintf (file, "),%s\n", name_jmp);
1853 /* Use JUMP_REGNO as a temporary PIC register. */
1854 const char *name_lr = reg_names[LR_REGNO];
1855 const char *name_gppic = name_jmp;
1856 const char *name_tmp = reg_names[TEMP_REGNO];
1858 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1859 fprintf (file, "\tcall 1f\n");
1860 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1861 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1862 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1863 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1864 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1866 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1867 assemble_name (file, name_func);
1868 fprintf (file, "),%s\n", name_tmp);
1870 fprintf (file, "\tsetlo #gprello(");
1871 assemble_name (file, name_func);
1872 fprintf (file, "),%s\n", name_tmp);
1874 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1877 /* Jump to the function address */
1878 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1882 /* A C expression which is nonzero if a function must have and use a frame
1883 pointer. This expression is evaluated in the reload pass. If its value is
1884 nonzero the function will have a frame pointer.
1886 The expression can in principle examine the current function and decide
1887 according to the facts, but on most machines the constant 0 or the constant
1888 1 suffices. Use 0 when the machine allows code to be generated with no
1889 frame pointer, and doing so saves some time or space. Use 1 when there is
1890 no possible advantage to avoiding a frame pointer.
1892 In certain cases, the compiler does not know how to produce valid code
1893 without a frame pointer. The compiler recognizes those cases and
1894 automatically gives the function a frame pointer regardless of what
1895 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1897 In a function that does not require a frame pointer, the frame pointer
1898 register can be allocated for ordinary usage, unless you mark it as a fixed
1899 register. See `FIXED_REGISTERS' for more information. */
1901 /* On frv, create a frame whenever we need to create stack */
1904 frv_frame_pointer_required ()
1906 if (! current_function_is_leaf)
1909 if (get_frame_size () != 0)
1915 if (!current_function_sp_is_unchanging)
1918 if (flag_pic && cfun->uses_pic_offset_table)
1924 if (cfun->machine->frame_needed)
1931 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1932 initial difference between the specified pair of registers. This macro must
1933 be defined if `ELIMINABLE_REGS' is defined. */
1935 /* See frv_stack_info for more details on the frv stack frame. */
1938 frv_initial_elimination_offset (from, to)
1942 frv_stack_t *info = frv_stack_info ();
1945 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1946 ret = info->total_size - info->pretend_size;
1948 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
1949 ret = - info->reg_offset[FRAME_POINTER_REGNUM];
1951 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1952 ret = (info->total_size
1953 - info->reg_offset[FRAME_POINTER_REGNUM]
1954 - info->pretend_size);
1959 if (TARGET_DEBUG_STACK)
1960 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
1961 reg_names [from], reg_names[to], ret);
1967 /* This macro offers an alternative to using `__builtin_saveregs' and defining
1968 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1969 arguments into the stack so that all the arguments appear to have been
1970 passed consecutively on the stack. Once this is done, you can use the
1971 standard implementation of varargs that works for machines that pass all
1972 their arguments on the stack.
1974 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
1975 the values that obtain after processing of the named arguments. The
1976 arguments MODE and TYPE describe the last named argument--its machine mode
1977 and its data type as a tree node.
1979 The macro implementation should do two things: first, push onto the stack
1980 all the argument registers *not* used for the named arguments, and second,
1981 store the size of the data thus pushed into the `int'-valued variable whose
1982 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
1983 store here will serve as additional offset for setting up the stack frame.
1985 Because you must generate code to push the anonymous arguments at compile
1986 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
1987 useful on machines that have just a single category of argument register and
1988 use it uniformly for all data types.
1990 If the argument SECOND_TIME is nonzero, it means that the arguments of the
1991 function are being analyzed for the second time. This happens for an inline
1992 function, which is not actually compiled until the end of the source file.
1993 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
1997 frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
1998 CUMULATIVE_ARGS *cum;
1999 enum machine_mode mode;
2000 tree type ATTRIBUTE_UNUSED;
2004 if (TARGET_DEBUG_ARG)
2006 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2007 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2011 /* If defined, is a C expression that produces the machine-specific code for a
2012 call to `__builtin_saveregs'. This code will be moved to the very beginning
2013 of the function, before any parameter access are made. The return value of
2014 this function should be an RTX that contains the value to use as the return
2015 of `__builtin_saveregs'.
2017 If this macro is not defined, the compiler will output an ordinary call to
2018 the library function `__builtin_saveregs'. */
2021 frv_expand_builtin_saveregs ()
2023 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2025 if (TARGET_DEBUG_ARG)
2026 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2029 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2033 /* Expand __builtin_va_start to do the va_start macro. */
2036 frv_expand_builtin_va_start (valist, nextarg)
2041 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2043 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2044 GEN_INT (UNITS_PER_WORD * num));
2046 if (TARGET_DEBUG_ARG)
2048 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2049 cfun->args_info, num);
2051 debug_rtx (nextarg);
2054 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2055 make_tree (ptr_type_node, nextarg));
2056 TREE_SIDE_EFFECTS (t) = 1;
2058 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2062 /* Expand __builtin_va_arg to do the va_arg macro. */
2065 frv_expand_builtin_va_arg(valist, type)
2073 if (TARGET_DEBUG_ARG)
2075 fprintf (stderr, "va_arg:\n");
2079 if (! AGGREGATE_TYPE_P (type))
2080 return std_expand_builtin_va_arg (valist, type);
2082 addr = std_expand_builtin_va_arg (valist, ptr_type_node);
2083 mem = gen_rtx_MEM (Pmode, addr);
2084 reg = gen_reg_rtx (Pmode);
2086 set_mem_alias_set (mem, get_varargs_alias_set ());
2087 emit_move_insn (reg, mem);
2093 /* Expand a block move operation, and return 1 if successful. Return 0
2094 if we should let the compiler generate normal code.
2096 operands[0] is the destination
2097 operands[1] is the source
2098 operands[2] is the length
2099 operands[3] is the alignment */
2101 /* Maximum number of loads to do before doing the stores */
2102 #ifndef MAX_MOVE_REG
2103 #define MAX_MOVE_REG 4
2106 /* Maximum number of total loads to do. */
2107 #ifndef TOTAL_MOVE_REG
2108 #define TOTAL_MOVE_REG 8
2112 frv_expand_block_move (operands)
2115 rtx orig_dest = operands[0];
2116 rtx orig_src = operands[1];
2117 rtx bytes_rtx = operands[2];
2118 rtx align_rtx = operands[3];
2119 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2132 rtx stores[MAX_MOVE_REG];
2134 enum machine_mode mode;
2136 /* If this is not a fixed size move, just call memcpy */
2140 /* If this is not a fixed size alignment, abort */
2141 if (GET_CODE (align_rtx) != CONST_INT)
2144 align = INTVAL (align_rtx);
2146 /* Anything to move? */
2147 bytes = INTVAL (bytes_rtx);
2151 /* Don't support real large moves. */
2152 if (bytes > TOTAL_MOVE_REG*align)
2155 /* Move the address into scratch registers. */
2156 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2157 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2159 num_reg = offset = 0;
2160 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2162 /* Calculate the correct offset for src/dest */
2166 dest_addr = dest_reg;
2170 src_addr = plus_constant (src_reg, offset);
2171 dest_addr = plus_constant (dest_reg, offset);
2174 /* Generate the appropriate load and store, saving the stores
2176 if (bytes >= 4 && align >= 4)
2178 else if (bytes >= 2 && align >= 2)
2183 move_bytes = GET_MODE_SIZE (mode);
2184 tmp_reg = gen_reg_rtx (mode);
2185 src_mem = change_address (orig_src, mode, src_addr);
2186 dest_mem = change_address (orig_dest, mode, dest_addr);
2187 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2188 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2190 if (num_reg >= MAX_MOVE_REG)
2192 for (i = 0; i < num_reg; i++)
2193 emit_insn (stores[i]);
2198 for (i = 0; i < num_reg; i++)
2199 emit_insn (stores[i]);
2205 /* Expand a block clear operation, and return 1 if successful. Return 0
2206 if we should let the compiler generate normal code.
2208 operands[0] is the destination
2209 operands[1] is the length
2210 operands[2] is the alignment */
2213 frv_expand_block_clear (operands)
2216 rtx orig_dest = operands[0];
2217 rtx bytes_rtx = operands[1];
2218 rtx align_rtx = operands[2];
2219 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2228 enum machine_mode mode;
2230 /* If this is not a fixed size move, just call memcpy */
2234 /* If this is not a fixed size alignment, abort */
2235 if (GET_CODE (align_rtx) != CONST_INT)
2238 align = INTVAL (align_rtx);
2240 /* Anything to move? */
2241 bytes = INTVAL (bytes_rtx);
2245 /* Don't support real large clears. */
2246 if (bytes > TOTAL_MOVE_REG*align)
2249 /* Move the address into a scratch register. */
2250 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2252 num_reg = offset = 0;
2253 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2255 /* Calculate the correct offset for src/dest */
2256 dest_addr = ((offset == 0)
2258 : plus_constant (dest_reg, offset));
2260 /* Generate the appropriate store of gr0 */
2261 if (bytes >= 4 && align >= 4)
2263 else if (bytes >= 2 && align >= 2)
2268 clear_bytes = GET_MODE_SIZE (mode);
2269 dest_mem = change_address (orig_dest, mode, dest_addr);
2270 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2277 /* The following variable is used to output modifiers of assembler
2278 code of the current output insn.. */
2280 static rtx *frv_insn_operands;
2282 /* The following function is used to add assembler insn code suffix .p
2283 if it is necessary. */
2286 frv_asm_output_opcode (f, ptr)
2292 if (! PACKING_FLAG_USED_P())
2295 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2298 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2299 || (*ptr >= 'A' && *ptr <= 'Z')))
2301 int letter = *ptr++;
2304 frv_print_operand (f, frv_insn_operands [c], letter);
2305 while ((c = *ptr) >= '0' && c <= '9')
2312 if (!frv_insn_packing_flag)
2318 /* The following function sets up the packing bit for the current
2319 output insn. Remember that the function is not called for asm
2323 frv_final_prescan_insn (insn, opvec, noperands)
2326 int noperands ATTRIBUTE_UNUSED;
2328 if (! PACKING_FLAG_USED_P())
2331 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
2334 frv_insn_operands = opvec;
2336 /* Look for the next printable instruction. frv_pack_insns () has set
2337 things up so that any printable instruction will have TImode if it
2338 starts a new packet and VOIDmode if it should be packed with the
2339 previous instruction.
2341 Printable instructions will be asm_operands or match one of the .md
2342 patterns. Since asm instructions cannot be packed -- and will
2343 therefore have TImode -- this loop terminates on any recognisable
2344 instruction, and on any unrecognisable instruction with TImode. */
2345 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2349 else if (!INSN_P (insn))
2351 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2355 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2356 be packed with this one. Set it to TRUE otherwise. If the next
2357 instruction is an asm insntruction, this statement will set the
2358 flag to TRUE, and that value will still hold when the asm operands
2359 themselves are printed. */
2360 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2361 && GET_MODE (insn) != TImode);
2366 /* A C expression whose value is RTL representing the address in a stack frame
2367 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2368 an RTL expression for the address of the stack frame itself.
2370 If you don't define this macro, the default is to return the value of
2371 FRAMEADDR--that is, the stack frame address is also the address of the stack
2372 word that points to the previous frame. */
2374 /* The default is correct, but we need to make sure the frame gets created. */
2376 frv_dynamic_chain_address (frame)
2379 cfun->machine->frame_needed = 1;
2384 /* A C expression whose value is RTL representing the value of the return
2385 address for the frame COUNT steps up from the current frame, after the
2386 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2387 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2390 The value of the expression must always be the correct address when COUNT is
2391 zero, but may be `NULL_RTX' if there is not way to determine the return
2392 address of other frames. */
2395 frv_return_addr_rtx (count, frame)
2396 int count ATTRIBUTE_UNUSED;
2399 cfun->machine->frame_needed = 1;
2400 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2403 /* Given a memory reference MEMREF, interpret the referenced memory as
2404 an array of MODE values, and return a reference to the element
2405 specified by INDEX. Assume that any pre-modification implicit in
2406 MEMREF has already happened.
2408 MEMREF must be a legitimate operand for modes larger than SImode.
2409 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2410 this function cannot handle. */
2412 frv_index_memory (memref, mode, index)
2414 enum machine_mode mode;
2417 rtx base = XEXP (memref, 0);
2418 if (GET_CODE (base) == PRE_MODIFY)
2419 base = XEXP (base, 0);
2420 return change_address (memref, mode,
2421 plus_constant (base, index * GET_MODE_SIZE (mode)));
2425 /* Print a memory address as an operand to reference that memory location. */
2427 frv_print_operand_address (stream, x)
2431 if (GET_CODE (x) == MEM)
2434 switch (GET_CODE (x))
2437 fputs (reg_names [ REGNO (x)], stream);
2441 fprintf (stream, "%ld", (long) INTVAL (x));
2445 assemble_name (stream, XSTR (x, 0));
2450 output_addr_const (stream, x);
2457 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2462 frv_print_operand_memory_reference_reg (stream, x)
2466 int regno = true_regnum (x);
2468 fputs (reg_names[regno], stream);
2470 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2473 /* Print a memory reference suitable for the ld/st instructions. */
2476 frv_print_operand_memory_reference (stream, x, addr_offset)
2484 switch (GET_CODE (x))
2491 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2493 x1 = XEXP (XEXP (x, 1), 1);
2503 if (GET_CODE (x0) == CONST_INT)
2511 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2520 else if (GET_CODE (x1) != CONST_INT)
2521 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2524 fputs ("@(", stream);
2526 fputs (reg_names[GPR_R0], stream);
2527 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2528 frv_print_operand_memory_reference_reg (stream, x0);
2530 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2532 fputs (",", stream);
2534 fputs (reg_names [GPR_R0], stream);
2538 switch (GET_CODE (x1))
2542 frv_print_operand_memory_reference_reg (stream, x1);
2546 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2550 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2551 && SYMBOL_REF_SMALL_P (x1))
2553 fputs ("#gprel12(", stream);
2554 assemble_name (stream, XSTR (x1, 0));
2555 fputs (")", stream);
2558 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2562 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2563 && const_small_data_p (x1))
2565 fputs ("#gprel12(", stream);
2566 assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0));
2567 fprintf (stream, "+"HOST_WIDE_INT_PRINT_DEC")",
2568 INTVAL (XEXP (XEXP (x1, 0), 1)));
2571 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2575 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2579 fputs (")", stream);
2583 /* Return 2 for likely branches and 0 for non-likely branches */
2585 #define FRV_JUMP_LIKELY 2
2586 #define FRV_JUMP_NOT_LIKELY 0
2589 frv_print_operand_jump_hint (insn)
2595 HOST_WIDE_INT prob = -1;
2596 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2598 if (GET_CODE (insn) != JUMP_INSN)
2601 /* Assume any non-conditional jump is likely. */
2602 if (! any_condjump_p (insn))
2603 ret = FRV_JUMP_LIKELY;
2607 labelref = condjump_label (insn);
2610 rtx label = XEXP (labelref, 0);
2611 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2616 note = find_reg_note (insn, REG_BR_PROB, 0);
2618 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2622 prob = INTVAL (XEXP (note, 0));
2623 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2625 : FRV_JUMP_NOT_LIKELY);
2637 case UNKNOWN: direction = "unknown jump direction"; break;
2638 case BACKWARD: direction = "jump backward"; break;
2639 case FORWARD: direction = "jump forward"; break;
2643 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2644 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2645 (long)INSN_UID (insn), direction, (long)prob,
2646 (long)REG_BR_PROB_BASE, ret);
2654 /* Print an operand to an assembler instruction.
2656 `%' followed by a letter and a digit says to output an operand in an
2657 alternate fashion. Four letters have standard, built-in meanings described
2658 below. The machine description macro `PRINT_OPERAND' can define additional
2659 letters with nonstandard meanings.
2661 `%cDIGIT' can be used to substitute an operand that is a constant value
2662 without the syntax that normally indicates an immediate operand.
2664 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2667 `%aDIGIT' can be used to substitute an operand as if it were a memory
2668 reference, with the actual operand treated as the address. This may be
2669 useful when outputting a "load address" instruction, because often the
2670 assembler syntax for such an instruction requires you to write the operand
2671 as if it were a memory reference.
2673 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2675 `%=' outputs a number which is unique to each instruction in the entire
2676 compilation. This is useful for making local labels to be referred to more
2677 than once in a single template that generates multiple assembler
2680 `%' followed by a punctuation character specifies a substitution that does
2681 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2682 assembler code. Other nonstandard cases can be defined in the
2683 `PRINT_OPERAND' macro. You must also define which punctuation characters
2684 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2687 frv_print_operand (file, x, code)
2692 HOST_WIDE_INT value;
2695 if (code != 0 && !isalpha (code))
2698 else if (GET_CODE (x) == CONST_INT)
2701 else if (GET_CODE (x) == CONST_DOUBLE)
2703 if (GET_MODE (x) == SFmode)
2708 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2709 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2713 else if (GET_MODE (x) == VOIDmode)
2714 value = CONST_DOUBLE_LOW (x);
2717 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2728 fputs (reg_names[GPR_R0], file);
2732 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2736 /* Output small data area base register (gr16). */
2737 fputs (reg_names[SDA_BASE_REG], file);
2741 /* Output pic register (gr17). */
2742 fputs (reg_names[PIC_REGNO], file);
2746 /* Output the temporary integer CCR register */
2747 fputs (reg_names[ICR_TEMP], file);
2751 /* Output the temporary integer CC register */
2752 fputs (reg_names[ICC_TEMP], file);
2755 /* case 'a': print an address */
2758 /* Print appropriate test for integer branch false operation */
2759 switch (GET_CODE (x))
2762 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2764 case EQ: fputs ("ne", file); break;
2765 case NE: fputs ("eq", file); break;
2766 case LT: fputs ("ge", file); break;
2767 case LE: fputs ("gt", file); break;
2768 case GT: fputs ("le", file); break;
2769 case GE: fputs ("lt", file); break;
2770 case LTU: fputs ("nc", file); break;
2771 case LEU: fputs ("hi", file); break;
2772 case GTU: fputs ("ls", file); break;
2773 case GEU: fputs ("c", file); break;
2777 /* case 'c': print a constant without the constant prefix. If
2778 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2781 /* Print appropriate test for integer branch true operation */
2782 switch (GET_CODE (x))
2785 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2787 case EQ: fputs ("eq", file); break;
2788 case NE: fputs ("ne", file); break;
2789 case LT: fputs ("lt", file); break;
2790 case LE: fputs ("le", file); break;
2791 case GT: fputs ("gt", file); break;
2792 case GE: fputs ("ge", file); break;
2793 case LTU: fputs ("c", file); break;
2794 case LEU: fputs ("ls", file); break;
2795 case GTU: fputs ("hi", file); break;
2796 case GEU: fputs ("nc", file); break;
2801 /* Print 1 for a NE and 0 for an EQ to give the final argument
2802 for a conditional instruction. */
2803 if (GET_CODE (x) == NE)
2806 else if (GET_CODE (x) == EQ)
2810 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2814 /* Print appropriate test for floating point branch false operation */
2815 switch (GET_CODE (x))
2818 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2820 case EQ: fputs ("ne", file); break;
2821 case NE: fputs ("eq", file); break;
2822 case LT: fputs ("uge", file); break;
2823 case LE: fputs ("ug", file); break;
2824 case GT: fputs ("ule", file); break;
2825 case GE: fputs ("ul", file); break;
2830 /* Print appropriate test for floating point branch true operation */
2831 switch (GET_CODE (x))
2834 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2836 case EQ: fputs ("eq", file); break;
2837 case NE: fputs ("ne", file); break;
2838 case LT: fputs ("lt", file); break;
2839 case LE: fputs ("le", file); break;
2840 case GT: fputs ("gt", file); break;
2841 case GE: fputs ("ge", file); break;
2846 /* Print 'i' if the operand is a constant, or is a memory reference that
2848 if (GET_CODE (x) == MEM)
2849 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2850 ? XEXP (XEXP (x, 0), 1)
2853 switch (GET_CODE (x))
2867 /* For jump instructions, print 'i' if the operand is a constant or
2868 is an expression that adds a constant */
2869 if (GET_CODE (x) == CONST_INT)
2874 if (GET_CODE (x) == CONST_INT
2875 || (GET_CODE (x) == PLUS
2876 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2877 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2883 /* Print the lower register of a double word register pair */
2884 if (GET_CODE (x) == REG)
2885 fputs (reg_names[ REGNO (x)+1 ], file);
2887 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2890 /* case 'l': print a LABEL_REF */
2894 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2895 for the second word of double memory operations. */
2896 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2897 switch (GET_CODE (x))
2900 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2903 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2911 frv_print_operand_memory_reference (file, x, offset);
2917 /* Print the opcode of a command. */
2918 switch (GET_CODE (x))
2921 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2923 case PLUS: fputs ("add", file); break;
2924 case MINUS: fputs ("sub", file); break;
2925 case AND: fputs ("and", file); break;
2926 case IOR: fputs ("or", file); break;
2927 case XOR: fputs ("xor", file); break;
2928 case ASHIFT: fputs ("sll", file); break;
2929 case ASHIFTRT: fputs ("sra", file); break;
2930 case LSHIFTRT: fputs ("srl", file); break;
2934 /* case 'n': negate and print a constant int */
2937 /* Print PIC label using operand as the number. */
2938 if (GET_CODE (x) != CONST_INT)
2939 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2941 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2945 /* Print 'u' if the operand is a update load/store */
2946 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2951 /* If value is 0, print gr0, otherwise it must be a register */
2952 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2953 fputs (reg_names[GPR_R0], file);
2955 else if (GET_CODE (x) == REG)
2956 fputs (reg_names [REGNO (x)], file);
2959 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2963 /* Print constant in hex */
2964 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2966 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2973 if (GET_CODE (x) == REG)
2974 fputs (reg_names [REGNO (x)], file);
2976 else if (GET_CODE (x) == CONST_INT
2977 || GET_CODE (x) == CONST_DOUBLE)
2978 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2980 else if (GET_CODE (x) == MEM)
2981 frv_print_operand_address (file, XEXP (x, 0));
2983 else if (CONSTANT_ADDRESS_P (x))
2984 frv_print_operand_address (file, x);
2987 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
2992 fatal_insn ("frv_print_operand: unknown code", x);
3000 /* A C statement (sans semicolon) for initializing the variable CUM for the
3001 state at the beginning of the argument list. The variable has type
3002 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3003 of the function which will receive the args, or 0 if the args are to a
3004 compiler support library function. The value of INDIRECT is nonzero when
3005 processing an indirect call, for example a call through a function pointer.
3006 The value of INDIRECT is zero for a call to an explicitly named function, a
3007 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3008 arguments for the function being compiled.
3010 When processing a call to a compiler support library function, LIBNAME
3011 identifies which one. It is a `symbol_ref' rtx which contains the name of
3012 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3013 being processed. Thus, each time this macro is called, either LIBNAME or
3014 FNTYPE is nonzero, but never both of them at once. */
3017 frv_init_cumulative_args (cum, fntype, libname, fndecl, incoming)
3018 CUMULATIVE_ARGS *cum;
3024 *cum = FIRST_ARG_REGNUM;
3026 if (TARGET_DEBUG_ARG)
3028 fprintf (stderr, "\ninit_cumulative_args:");
3029 if (!fndecl && fntype)
3030 fputs (" indirect", stderr);
3033 fputs (" incoming", stderr);
3037 tree ret_type = TREE_TYPE (fntype);
3038 fprintf (stderr, " return=%s,",
3039 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3042 if (libname && GET_CODE (libname) == SYMBOL_REF)
3043 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3045 if (cfun->returns_struct)
3046 fprintf (stderr, " return-struct");
3048 putc ('\n', stderr);
3053 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3054 argument with the specified mode and type. If it is not defined,
3055 `PARM_BOUNDARY' is used for all arguments. */
3058 frv_function_arg_boundary (mode, type)
3059 enum machine_mode mode ATTRIBUTE_UNUSED;
3060 tree type ATTRIBUTE_UNUSED;
3062 return BITS_PER_WORD;
3066 /* A C expression that controls whether a function argument is passed in a
3067 register, and which register.
3069 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3070 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3071 arguments so far passed in registers; MODE, the machine mode of the argument;
3072 TYPE, the data type of the argument as a tree node or 0 if that is not known
3073 (which happens for C support library functions); and NAMED, which is 1 for an
3074 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3075 called function's prototype.
3077 The value of the expression should either be a `reg' RTX for the hard
3078 register in which to pass the argument, or zero to pass the argument on the
3081 For machines like the VAX and 68000, where normally all arguments are
3082 pushed, zero suffices as a definition.
3084 The usual way to make the ANSI library `stdarg.h' work on a machine where
3085 some arguments are usually passed in registers, is to cause nameless
3086 arguments to be passed on the stack instead. This is done by making
3087 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3089 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3090 this macro to determine if this argument is of a type that must be passed in
3091 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3092 returns nonzero for such an argument, the compiler will abort. If
3093 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3094 stack and then loaded into a register. */
3097 frv_function_arg (cum, mode, type, named, incoming)
3098 CUMULATIVE_ARGS *cum;
3099 enum machine_mode mode;
3100 tree type ATTRIBUTE_UNUSED;
3102 int incoming ATTRIBUTE_UNUSED;
3104 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3109 /* Return a marker for use in the call instruction. */
3110 if (xmode == VOIDmode)
3116 else if (arg_num <= LAST_ARG_REGNUM)
3118 ret = gen_rtx (REG, xmode, arg_num);
3119 debstr = reg_names[arg_num];
3128 if (TARGET_DEBUG_ARG)
3130 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3131 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3137 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3138 advance past an argument in the argument list. The values MODE, TYPE and
3139 NAMED describe that argument. Once this is done, the variable CUM is
3140 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3142 This macro need not do anything if the argument in question was passed on
3143 the stack. The compiler knows how to track the amount of stack space used
3144 for arguments without any special help. */
3147 frv_function_arg_advance (cum, mode, type, named)
3148 CUMULATIVE_ARGS *cum;
3149 enum machine_mode mode;
3150 tree type ATTRIBUTE_UNUSED;
3153 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3154 int bytes = GET_MODE_SIZE (xmode);
3155 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3158 *cum = arg_num + words;
3160 if (TARGET_DEBUG_ARG)
3162 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3163 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3167 /* A C expression for the number of words, at the beginning of an argument,
3168 must be put in registers. The value must be zero for arguments that are
3169 passed entirely in registers or that are entirely pushed on the stack.
3171 On some machines, certain arguments must be passed partially in registers
3172 and partially in memory. On these machines, typically the first N words of
3173 arguments are passed in registers, and the rest on the stack. If a
3174 multi-word argument (a `double' or a structure) crosses that boundary, its
3175 first few words must be passed in registers and the rest must be pushed.
3176 This macro tells the compiler when this occurs, and how many of the words
3177 should go in registers.
3179 `FUNCTION_ARG' for these arguments should return the first register to be
3180 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3181 the called function. */
3184 frv_function_arg_partial_nregs (cum, mode, type, named)
3185 CUMULATIVE_ARGS *cum;
3186 enum machine_mode mode;
3187 tree type ATTRIBUTE_UNUSED;
3188 int named ATTRIBUTE_UNUSED;
3190 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3191 int bytes = GET_MODE_SIZE (xmode);
3192 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3196 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3197 ? LAST_ARG_REGNUM - arg_num + 1
3200 if (TARGET_DEBUG_ARG && ret)
3201 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3209 /* A C expression that indicates when an argument must be passed by reference.
3210 If nonzero for an argument, a copy of that argument is made in memory and a
3211 pointer to the argument is passed instead of the argument itself. The
3212 pointer is passed in whatever way is appropriate for passing a pointer to
3215 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3216 definition of this macro might be
3217 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3218 MUST_PASS_IN_STACK (MODE, TYPE) */
3221 frv_function_arg_pass_by_reference (cum, mode, type, named)
3222 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3223 enum machine_mode mode;
3225 int named ATTRIBUTE_UNUSED;
3227 return MUST_PASS_IN_STACK (mode, type);
3230 /* If defined, a C expression that indicates when it is the called function's
3231 responsibility to make a copy of arguments passed by invisible reference.
3232 Normally, the caller makes a copy and passes the address of the copy to the
3233 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3234 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3235 the "live" value. The called function must not modify this value. If it
3236 can be determined that the value won't be modified, it need not make a copy;
3237 otherwise a copy must be made. */
3240 frv_function_arg_callee_copies (cum, mode, type, named)
3241 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3242 enum machine_mode mode ATTRIBUTE_UNUSED;
3243 tree type ATTRIBUTE_UNUSED;
3244 int named ATTRIBUTE_UNUSED;
3249 /* If defined, a C expression that indicates when it is more desirable to keep
3250 an argument passed by invisible reference as a reference, rather than
3251 copying it to a pseudo register. */
3254 frv_function_arg_keep_as_reference (cum, mode, type, named)
3255 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3256 enum machine_mode mode ATTRIBUTE_UNUSED;
3257 tree type ATTRIBUTE_UNUSED;
3258 int named ATTRIBUTE_UNUSED;
3264 /* Return true if a register is ok to use as a base or index register. */
3266 static FRV_INLINE int
3267 frv_regno_ok_for_base_p (regno, strict_p)
3275 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3277 if (regno == ARG_POINTER_REGNUM)
3280 return (regno >= FIRST_PSEUDO_REGISTER);
3284 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3285 RTX) is a legitimate memory address on the target machine for a memory
3286 operand of mode MODE.
3288 It usually pays to define several simpler macros to serve as subroutines for
3289 this one. Otherwise it may be too complicated to understand.
3291 This macro must exist in two variants: a strict variant and a non-strict
3292 one. The strict variant is used in the reload pass. It must be defined so
3293 that any pseudo-register that has not been allocated a hard register is
3294 considered a memory reference. In contexts where some kind of register is
3295 required, a pseudo-register with no hard register must be rejected.
3297 The non-strict variant is used in other passes. It must be defined to
3298 accept all pseudo-registers in every context where some kind of register is
3301 Compiler source files that want to use the strict variant of this macro
3302 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3303 conditional to define the strict variant in that case and the non-strict
3306 Subroutines to check for acceptable registers for various purposes (one for
3307 base registers, one for index registers, and so on) are typically among the
3308 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3309 subroutine macros need have two variants; the higher levels of macros may be
3310 the same whether strict or not.
3312 Normally, constant addresses which are the sum of a `symbol_ref' and an
3313 integer are stored inside a `const' RTX to mark them as constant.
3314 Therefore, there is no need to recognize such sums specifically as
3315 legitimate addresses. Normally you would simply recognize any `const' as
3318 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3319 are not marked with `const'. It assumes that a naked `plus' indicates
3320 indexing. If so, then you *must* reject such naked constant sums as
3321 illegitimate addresses, so that none of them will be given to
3322 `PRINT_OPERAND_ADDRESS'.
3324 On some machines, whether a symbolic address is legitimate depends on the
3325 section that the address refers to. On these machines, define the macro
3326 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3327 then check for it here. When you see a `const', you will have to look
3328 inside it to find the `symbol_ref' in order to determine the section.
3330 The best way to modify the name string is by adding text to the beginning,
3331 with suitable punctuation to prevent any ambiguity. Allocate the new name
3332 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3333 remove and decode the added text and output the name accordingly, and define
3334 `(* targetm.strip_name_encoding)' to access the original name string.
3336 You can check the information stored here into the `symbol_ref' in the
3337 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3338 `PRINT_OPERAND_ADDRESS'. */
3341 frv_legitimate_address_p (mode, x, strict_p, condexec_p)
3342 enum machine_mode mode;
3349 HOST_WIDE_INT value;
3352 switch (GET_CODE (x))
3359 if (GET_CODE (x) != REG)
3365 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3371 if (GET_CODE (x0) != REG
3372 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3373 || GET_CODE (x1) != PLUS
3374 || ! rtx_equal_p (x0, XEXP (x1, 0))
3375 || GET_CODE (XEXP (x1, 1)) != REG
3376 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3383 /* 12 bit immediate */
3388 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3390 /* If we can't use load/store double operations, make sure we can
3391 address the second word. */
3392 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3393 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3402 if (GET_CODE (x0) == SUBREG)
3403 x0 = SUBREG_REG (x0);
3405 if (GET_CODE (x0) != REG)
3408 regno0 = REGNO (x0);
3409 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3412 switch (GET_CODE (x1))
3418 x1 = SUBREG_REG (x1);
3419 if (GET_CODE (x1) != REG)
3425 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3426 on having move double instructions */
3427 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3430 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3434 /* 12 bit immediate */
3439 value = INTVAL (x1);
3440 ret = IN_RANGE_P (value, -2048, 2047);
3442 /* If we can't use load/store double operations, make sure we can
3443 address the second word. */
3444 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3445 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3451 && regno0 == SDA_BASE_REG
3452 && SYMBOL_REF_SMALL_P (x1))
3457 if (!condexec_p && regno0 == SDA_BASE_REG && const_small_data_p (x1))
3465 if (TARGET_DEBUG_ADDR)
3467 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3468 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3469 (condexec_p) ? ", inside conditional code" : "");
3477 /* A C compound statement that attempts to replace X with a valid memory
3478 address for an operand of mode MODE. WIN will be a C statement label
3479 elsewhere in the code; the macro definition may use
3481 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3483 to avoid further processing if the address has become legitimate.
3485 X will always be the result of a call to `break_out_memory_refs', and OLDX
3486 will be the operand that was given to that function to produce X.
3488 The code generated by this macro should not alter the substructure of X. If
3489 it transforms X into a more legitimate form, it should assign X (which will
3490 always be a C variable) a new value.
3492 It is not necessary for this macro to come up with a legitimate address.
3493 The compiler has standard ways of doing so in all cases. In fact, it is
3494 safe for this macro to do nothing. But often a machine-dependent strategy
3495 can generate better code. */
3498 frv_legitimize_address (x, oldx, mode)
3500 rtx oldx ATTRIBUTE_UNUSED;
3501 enum machine_mode mode ATTRIBUTE_UNUSED;
3505 /* Don't try to legitimize addresses if we are not optimizing, since the
3506 address we generate is not a general operand, and will horribly mess
3507 things up when force_reg is called to try and put it in a register because
3508 we aren't optimizing. */
3510 && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x))
3511 || (GET_CODE (x) == CONST && const_small_data_p (x))))
3513 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x);
3515 cfun->uses_pic_offset_table = TRUE;
3518 if (TARGET_DEBUG_ADDR && ret != NULL_RTX)
3520 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3521 GET_MODE_NAME (mode));
3528 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3529 the operand is used by a predicated instruction. */
3532 frv_legitimate_memory_operand (op, mode, condexec_p)
3534 enum machine_mode mode;
3537 return ((GET_MODE (op) == mode || mode == VOIDmode)
3538 && GET_CODE (op) == MEM
3539 && frv_legitimate_address_p (mode, XEXP (op, 0),
3540 reload_completed, condexec_p));
3544 /* Return 1 is OP is a memory operand, or will be turned into one by
3547 int frv_load_operand (op, mode)
3549 enum machine_mode mode;
3551 if (GET_MODE (op) != mode && mode != VOIDmode)
3554 if (reload_in_progress)
3557 if (GET_CODE (tmp) == SUBREG)
3558 tmp = SUBREG_REG (tmp);
3559 if (GET_CODE (tmp) == REG
3560 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3561 op = reg_equiv_memory_loc[REGNO (tmp)];
3564 return op && memory_operand (op, mode);
3568 /* Return 1 if operand is a GPR register or a FPR register. */
3570 int gpr_or_fpr_operand (op, mode)
3572 enum machine_mode mode;
3576 if (GET_MODE (op) != mode && mode != VOIDmode)
3579 if (GET_CODE (op) == SUBREG)
3581 if (GET_CODE (SUBREG_REG (op)) != REG)
3582 return register_operand (op, mode);
3584 op = SUBREG_REG (op);
3587 if (GET_CODE (op) != REG)
3591 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3597 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3599 int gpr_or_int12_operand (op, mode)
3601 enum machine_mode mode;
3603 if (GET_CODE (op) == CONST_INT)
3604 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3606 if (GET_MODE (op) != mode && mode != VOIDmode)
3609 if (GET_CODE (op) == SUBREG)
3611 if (GET_CODE (SUBREG_REG (op)) != REG)
3612 return register_operand (op, mode);
3614 op = SUBREG_REG (op);
3617 if (GET_CODE (op) != REG)
3620 return GPR_OR_PSEUDO_P (REGNO (op));
3623 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3624 signed immediate. */
3626 int gpr_fpr_or_int12_operand (op, mode)
3628 enum machine_mode mode;
3632 if (GET_CODE (op) == CONST_INT)
3633 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3635 if (GET_MODE (op) != mode && mode != VOIDmode)
3638 if (GET_CODE (op) == SUBREG)
3640 if (GET_CODE (SUBREG_REG (op)) != REG)
3641 return register_operand (op, mode);
3643 op = SUBREG_REG (op);
3646 if (GET_CODE (op) != REG)
3650 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3656 /* Return 1 if operand is a register or 6 bit signed immediate. */
3658 int fpr_or_int6_operand (op, mode)
3660 enum machine_mode mode;
3662 if (GET_CODE (op) == CONST_INT)
3663 return IN_RANGE_P (INTVAL (op), -32, 31);
3665 if (GET_MODE (op) != mode && mode != VOIDmode)
3668 if (GET_CODE (op) == SUBREG)
3670 if (GET_CODE (SUBREG_REG (op)) != REG)
3671 return register_operand (op, mode);
3673 op = SUBREG_REG (op);
3676 if (GET_CODE (op) != REG)
3679 return FPR_OR_PSEUDO_P (REGNO (op));
3682 /* Return 1 if operand is a register or 10 bit signed immediate. */
3684 int gpr_or_int10_operand (op, mode)
3686 enum machine_mode mode;
3688 if (GET_CODE (op) == CONST_INT)
3689 return IN_RANGE_P (INTVAL (op), -512, 511);
3691 if (GET_MODE (op) != mode && mode != VOIDmode)
3694 if (GET_CODE (op) == SUBREG)
3696 if (GET_CODE (SUBREG_REG (op)) != REG)
3697 return register_operand (op, mode);
3699 op = SUBREG_REG (op);
3702 if (GET_CODE (op) != REG)
3705 return GPR_OR_PSEUDO_P (REGNO (op));
3708 /* Return 1 if operand is a register or an integer immediate. */
3710 int gpr_or_int_operand (op, mode)
3712 enum machine_mode mode;
3714 if (GET_CODE (op) == CONST_INT)
3717 if (GET_MODE (op) != mode && mode != VOIDmode)
3720 if (GET_CODE (op) == SUBREG)
3722 if (GET_CODE (SUBREG_REG (op)) != REG)
3723 return register_operand (op, mode);
3725 op = SUBREG_REG (op);
3728 if (GET_CODE (op) != REG)
3731 return GPR_OR_PSEUDO_P (REGNO (op));
3734 /* Return 1 if operand is a 12 bit signed immediate. */
3736 int int12_operand (op, mode)
3738 enum machine_mode mode ATTRIBUTE_UNUSED;
3740 if (GET_CODE (op) != CONST_INT)
3743 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3746 /* Return 1 if operand is a 6 bit signed immediate. */
3748 int int6_operand (op, mode)
3750 enum machine_mode mode ATTRIBUTE_UNUSED;
3752 if (GET_CODE (op) != CONST_INT)
3755 return IN_RANGE_P (INTVAL (op), -32, 31);
3758 /* Return 1 if operand is a 5 bit signed immediate. */
3760 int int5_operand (op, mode)
3762 enum machine_mode mode ATTRIBUTE_UNUSED;
3764 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3767 /* Return 1 if operand is a 5 bit unsigned immediate. */
3769 int uint5_operand (op, mode)
3771 enum machine_mode mode ATTRIBUTE_UNUSED;
3773 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3776 /* Return 1 if operand is a 4 bit unsigned immediate. */
3778 int uint4_operand (op, mode)
3780 enum machine_mode mode ATTRIBUTE_UNUSED;
3782 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3785 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3787 int uint1_operand (op, mode)
3789 enum machine_mode mode ATTRIBUTE_UNUSED;
3791 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3794 /* Return 1 if operand is an integer constant that takes 2 instructions
3795 to load up and can be split into sethi/setlo instructions.. */
3797 int int_2word_operand (op, mode)
3799 enum machine_mode mode ATTRIBUTE_UNUSED;
3801 HOST_WIDE_INT value;
3805 switch (GET_CODE (op))
3811 return (flag_pic == 0);
3814 /* small data references are already 1 word */
3815 return (flag_pic == 0) && (! const_small_data_p (op));
3818 /* small data references are already 1 word */
3819 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3822 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3825 if (GET_MODE (op) == SFmode)
3827 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3828 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3830 return ! IN_RANGE_P (value, -32768, 32767);
3832 else if (GET_MODE (op) == VOIDmode)
3834 value = CONST_DOUBLE_LOW (op);
3835 return ! IN_RANGE_P (value, -32768, 32767);
3843 /* Return 1 if operand is the pic address register. */
3845 pic_register_operand (op, mode)
3847 enum machine_mode mode ATTRIBUTE_UNUSED;
3852 if (GET_CODE (op) != REG)
3855 if (REGNO (op) != PIC_REGNO)
3861 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3862 that takes 3 seperate instructions to form. */
3864 int pic_symbolic_operand (op, mode)
3866 enum machine_mode mode ATTRIBUTE_UNUSED;
3871 switch (GET_CODE (op))
3880 /* small data references are already 1 word */
3881 return ! SYMBOL_REF_SMALL_P (op);
3884 /* small data references are already 1 word */
3885 return ! const_small_data_p (op);
3891 /* Return 1 if operand is the small data register. */
3893 small_data_register_operand (op, mode)
3895 enum machine_mode mode ATTRIBUTE_UNUSED;
3897 if (GET_CODE (op) != REG)
3900 if (REGNO (op) != SDA_BASE_REG)
3906 /* Return 1 if operand is a symbolic reference to a small data area static or
3909 int small_data_symbolic_operand (op, mode)
3911 enum machine_mode mode ATTRIBUTE_UNUSED;
3913 switch (GET_CODE (op))
3919 return const_small_data_p (op);
3922 return SYMBOL_REF_SMALL_P (op);
3928 /* Return 1 if operand is a 16 bit unsigned immediate */
3930 int uint16_operand (op, mode)
3932 enum machine_mode mode ATTRIBUTE_UNUSED;
3934 if (GET_CODE (op) != CONST_INT)
3937 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3940 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
3942 int upper_int16_operand (op, mode)
3944 enum machine_mode mode ATTRIBUTE_UNUSED;
3946 if (GET_CODE (op) != CONST_INT)
3949 return ((INTVAL (op) & 0xffff) == 0);
3952 /* Return true if operand is a GPR register. */
3955 integer_register_operand (op, mode)
3957 enum machine_mode mode;
3959 if (GET_MODE (op) != mode && mode != VOIDmode)
3962 if (GET_CODE (op) == SUBREG)
3964 if (GET_CODE (SUBREG_REG (op)) != REG)
3965 return register_operand (op, mode);
3967 op = SUBREG_REG (op);
3970 if (GET_CODE (op) != REG)
3973 return GPR_OR_PSEUDO_P (REGNO (op));
3976 /* Return true if operand is a GPR register. Do not allow SUBREG's
3977 here, in order to prevent a combine bug. */
3980 gpr_no_subreg_operand (op, mode)
3982 enum machine_mode mode;
3984 if (GET_MODE (op) != mode && mode != VOIDmode)
3987 if (GET_CODE (op) != REG)
3990 return GPR_OR_PSEUDO_P (REGNO (op));
3993 /* Return true if operand is a FPR register. */
3996 fpr_operand (op, mode)
3998 enum machine_mode mode;
4000 if (GET_MODE (op) != mode && mode != VOIDmode)
4003 if (GET_CODE (op) == SUBREG)
4005 if (GET_CODE (SUBREG_REG (op)) != REG)
4006 return register_operand (op, mode);
4008 op = SUBREG_REG (op);
4011 if (GET_CODE (op) != REG)
4014 return FPR_OR_PSEUDO_P (REGNO (op));
4017 /* Return true if operand is an even GPR or FPR register. */
4020 even_reg_operand (op, mode)
4022 enum machine_mode mode;
4026 if (GET_MODE (op) != mode && mode != VOIDmode)
4029 if (GET_CODE (op) == SUBREG)
4031 if (GET_CODE (SUBREG_REG (op)) != REG)
4032 return register_operand (op, mode);
4034 op = SUBREG_REG (op);
4037 if (GET_CODE (op) != REG)
4041 if (regno >= FIRST_PSEUDO_REGISTER)
4045 return (((regno - GPR_FIRST) & 1) == 0);
4048 return (((regno - FPR_FIRST) & 1) == 0);
4053 /* Return true if operand is an odd GPR register. */
4056 odd_reg_operand (op, mode)
4058 enum machine_mode mode;
4062 if (GET_MODE (op) != mode && mode != VOIDmode)
4065 if (GET_CODE (op) == SUBREG)
4067 if (GET_CODE (SUBREG_REG (op)) != REG)
4068 return register_operand (op, mode);
4070 op = SUBREG_REG (op);
4073 if (GET_CODE (op) != REG)
4077 /* assume that reload will give us an even register */
4078 if (regno >= FIRST_PSEUDO_REGISTER)
4082 return (((regno - GPR_FIRST) & 1) != 0);
4085 return (((regno - FPR_FIRST) & 1) != 0);
4090 /* Return true if operand is an even GPR register. */
4093 even_gpr_operand (op, mode)
4095 enum machine_mode mode;
4099 if (GET_MODE (op) != mode && mode != VOIDmode)
4102 if (GET_CODE (op) == SUBREG)
4104 if (GET_CODE (SUBREG_REG (op)) != REG)
4105 return register_operand (op, mode);
4107 op = SUBREG_REG (op);
4110 if (GET_CODE (op) != REG)
4114 if (regno >= FIRST_PSEUDO_REGISTER)
4117 if (! GPR_P (regno))
4120 return (((regno - GPR_FIRST) & 1) == 0);
4123 /* Return true if operand is an odd GPR register. */
4126 odd_gpr_operand (op, mode)
4128 enum machine_mode mode;
4132 if (GET_MODE (op) != mode && mode != VOIDmode)
4135 if (GET_CODE (op) == SUBREG)
4137 if (GET_CODE (SUBREG_REG (op)) != REG)
4138 return register_operand (op, mode);
4140 op = SUBREG_REG (op);
4143 if (GET_CODE (op) != REG)
4147 /* assume that reload will give us an even register */
4148 if (regno >= FIRST_PSEUDO_REGISTER)
4151 if (! GPR_P (regno))
4154 return (((regno - GPR_FIRST) & 1) != 0);
4157 /* Return true if operand is a quad aligned FPR register. */
4160 quad_fpr_operand (op, mode)
4162 enum machine_mode mode;
4166 if (GET_MODE (op) != mode && mode != VOIDmode)
4169 if (GET_CODE (op) == SUBREG)
4171 if (GET_CODE (SUBREG_REG (op)) != REG)
4172 return register_operand (op, mode);
4174 op = SUBREG_REG (op);
4177 if (GET_CODE (op) != REG)
4181 if (regno >= FIRST_PSEUDO_REGISTER)
4184 if (! FPR_P (regno))
4187 return (((regno - FPR_FIRST) & 3) == 0);
4190 /* Return true if operand is an even FPR register. */
4193 even_fpr_operand (op, mode)
4195 enum machine_mode mode;
4199 if (GET_MODE (op) != mode && mode != VOIDmode)
4202 if (GET_CODE (op) == SUBREG)
4204 if (GET_CODE (SUBREG_REG (op)) != REG)
4205 return register_operand (op, mode);
4207 op = SUBREG_REG (op);
4210 if (GET_CODE (op) != REG)
4214 if (regno >= FIRST_PSEUDO_REGISTER)
4217 if (! FPR_P (regno))
4220 return (((regno - FPR_FIRST) & 1) == 0);
4223 /* Return true if operand is an odd FPR register. */
4226 odd_fpr_operand (op, mode)
4228 enum machine_mode mode;
4232 if (GET_MODE (op) != mode && mode != VOIDmode)
4235 if (GET_CODE (op) == SUBREG)
4237 if (GET_CODE (SUBREG_REG (op)) != REG)
4238 return register_operand (op, mode);
4240 op = SUBREG_REG (op);
4243 if (GET_CODE (op) != REG)
4247 /* assume that reload will give us an even register */
4248 if (regno >= FIRST_PSEUDO_REGISTER)
4251 if (! FPR_P (regno))
4254 return (((regno - FPR_FIRST) & 1) != 0);
4257 /* Return true if operand is a 2 word memory address that can be loaded in one
4258 instruction to load or store. We assume the stack and frame pointers are
4259 suitably aligned, and variables in the small data area. FIXME -- at some we
4260 should recognize other globals and statics. We can't assume that any old
4261 pointer is aligned, given that arguments could be passed on an odd word on
4262 the stack and the address taken and passed through to another function. */
4265 dbl_memory_one_insn_operand (op, mode)
4267 enum machine_mode mode;
4275 if (GET_CODE (op) != MEM)
4278 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4281 addr = XEXP (op, 0);
4282 if (GET_CODE (addr) == REG)
4285 else if (GET_CODE (addr) == PLUS)
4287 rtx addr0 = XEXP (addr, 0);
4288 rtx addr1 = XEXP (addr, 1);
4290 if (GET_CODE (addr0) != REG)
4293 if (plus_small_data_p (addr0, addr1))
4296 if (GET_CODE (addr1) != CONST_INT)
4299 if ((INTVAL (addr1) & 7) != 0)
4308 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4314 /* Return true if operand is a 2 word memory address that needs to
4315 use two instructions to load or store. */
4318 dbl_memory_two_insn_operand (op, mode)
4320 enum machine_mode mode;
4322 if (GET_CODE (op) != MEM)
4325 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4331 return ! dbl_memory_one_insn_operand (op, mode);
4334 /* Return true if operand is something that can be an output for a move
4338 move_destination_operand (op, mode)
4340 enum machine_mode mode;
4345 switch (GET_CODE (op))
4351 if (GET_MODE (op) != mode && mode != VOIDmode)
4354 subreg = SUBREG_REG (op);
4355 code = GET_CODE (subreg);
4357 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4358 reload_completed, FALSE);
4360 return (code == REG);
4363 if (GET_MODE (op) != mode && mode != VOIDmode)
4369 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4372 return frv_legitimate_memory_operand (op, mode, FALSE);
4378 /* Return true if operand is something that can be an input for a move
4382 move_source_operand (op, mode)
4384 enum machine_mode mode;
4389 switch (GET_CODE (op))
4399 return immediate_operand (op, mode);
4402 if (GET_MODE (op) != mode && mode != VOIDmode)
4405 subreg = SUBREG_REG (op);
4406 code = GET_CODE (subreg);
4408 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4409 reload_completed, FALSE);
4411 return (code == REG);
4414 if (GET_MODE (op) != mode && mode != VOIDmode)
4420 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4423 return frv_legitimate_memory_operand (op, mode, FALSE);
4429 /* Return true if operand is something that can be an output for a conditional
4433 condexec_dest_operand (op, mode)
4435 enum machine_mode mode;
4440 switch (GET_CODE (op))
4446 if (GET_MODE (op) != mode && mode != VOIDmode)
4449 subreg = SUBREG_REG (op);
4450 code = GET_CODE (subreg);
4452 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4453 reload_completed, TRUE);
4455 return (code == REG);
4458 if (GET_MODE (op) != mode && mode != VOIDmode)
4464 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4467 return frv_legitimate_memory_operand (op, mode, TRUE);
4473 /* Return true if operand is something that can be an input for a conditional
4477 condexec_source_operand (op, mode)
4479 enum machine_mode mode;
4484 switch (GET_CODE (op))
4494 if (GET_MODE (op) != mode && mode != VOIDmode)
4497 subreg = SUBREG_REG (op);
4498 code = GET_CODE (subreg);
4500 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4501 reload_completed, TRUE);
4503 return (code == REG);
4506 if (GET_MODE (op) != mode && mode != VOIDmode)
4512 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4515 return frv_legitimate_memory_operand (op, mode, TRUE);
4521 /* Return true if operand is a register of any flavor or a 0 of the
4522 appropriate type. */
4525 reg_or_0_operand (op, mode)
4527 enum machine_mode mode;
4529 switch (GET_CODE (op))
4536 if (GET_MODE (op) != mode && mode != VOIDmode)
4539 return register_operand (op, mode);
4549 /* Return true if operand is the link register */
4552 lr_operand (op, mode)
4554 enum machine_mode mode;
4556 if (GET_CODE (op) != REG)
4559 if (GET_MODE (op) != mode && mode != VOIDmode)
4562 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4568 /* Return true if operand is a gpr register or a valid memory operation. */
4571 gpr_or_memory_operand (op, mode)
4573 enum machine_mode mode;
4575 return (integer_register_operand (op, mode)
4576 || frv_legitimate_memory_operand (op, mode, FALSE));
4579 /* Return true if operand is a fpr register or a valid memory operation. */
4582 fpr_or_memory_operand (op, mode)
4584 enum machine_mode mode;
4586 return (fpr_operand (op, mode)
4587 || frv_legitimate_memory_operand (op, mode, FALSE));
4590 /* Return true if operand is an icc register */
4593 icc_operand (op, mode)
4595 enum machine_mode mode;
4599 if (GET_MODE (op) != mode && mode != VOIDmode)
4602 if (GET_CODE (op) != REG)
4606 return ICC_OR_PSEUDO_P (regno);
4609 /* Return true if operand is an fcc register */
4612 fcc_operand (op, mode)
4614 enum machine_mode mode;
4618 if (GET_MODE (op) != mode && mode != VOIDmode)
4621 if (GET_CODE (op) != REG)
4625 return FCC_OR_PSEUDO_P (regno);
4628 /* Return true if operand is either an fcc or icc register */
4631 cc_operand (op, mode)
4633 enum machine_mode mode;
4637 if (GET_MODE (op) != mode && mode != VOIDmode)
4640 if (GET_CODE (op) != REG)
4644 if (CC_OR_PSEUDO_P (regno))
4650 /* Return true if operand is an integer CCR register */
4653 icr_operand (op, mode)
4655 enum machine_mode mode;
4659 if (GET_MODE (op) != mode && mode != VOIDmode)
4662 if (GET_CODE (op) != REG)
4666 return ICR_OR_PSEUDO_P (regno);
4669 /* Return true if operand is an fcc register */
4672 fcr_operand (op, mode)
4674 enum machine_mode mode;
4678 if (GET_MODE (op) != mode && mode != VOIDmode)
4681 if (GET_CODE (op) != REG)
4685 return FCR_OR_PSEUDO_P (regno);
4688 /* Return true if operand is either an fcc or icc register */
4691 cr_operand (op, mode)
4693 enum machine_mode mode;
4697 if (GET_MODE (op) != mode && mode != VOIDmode)
4700 if (GET_CODE (op) != REG)
4704 if (CR_OR_PSEUDO_P (regno))
4710 /* Return true if operand is a memory reference suitable for a call. */
4713 call_operand (op, mode)
4715 enum machine_mode mode;
4717 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4720 if (GET_CODE (op) == SYMBOL_REF)
4723 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4724 never occur anyway), but prevents reload from not handling the case
4725 properly of a call through a pointer on a function that calls
4726 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4727 return gpr_or_int12_operand (op, mode);
4730 /* Return true if operator is a kind of relational operator. */
4733 relational_operator (op, mode)
4735 enum machine_mode mode;
4741 if (mode != VOIDmode && mode != GET_MODE (op))
4744 switch (GET_CODE (op))
4763 if (op1 != const0_rtx)
4767 if (GET_CODE (op0) != REG)
4770 regno = REGNO (op0);
4771 switch (GET_MODE (op0))
4778 return ICC_OR_PSEUDO_P (regno);
4781 return FCC_OR_PSEUDO_P (regno);
4784 return CR_OR_PSEUDO_P (regno);
4790 /* Return true if operator is a signed integer relational operator */
4793 signed_relational_operator (op, mode)
4795 enum machine_mode mode;
4801 if (mode != VOIDmode && mode != GET_MODE (op))
4804 switch (GET_CODE (op))
4819 if (op1 != const0_rtx)
4823 if (GET_CODE (op0) != REG)
4826 regno = REGNO (op0);
4827 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4830 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4836 /* Return true if operator is a signed integer relational operator */
4839 unsigned_relational_operator (op, mode)
4841 enum machine_mode mode;
4847 if (mode != VOIDmode && mode != GET_MODE (op))
4850 switch (GET_CODE (op))
4863 if (op1 != const0_rtx)
4867 if (GET_CODE (op0) != REG)
4870 regno = REGNO (op0);
4871 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4874 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4880 /* Return true if operator is a floating point relational operator */
4883 float_relational_operator (op, mode)
4885 enum machine_mode mode;
4891 if (mode != VOIDmode && mode != GET_MODE (op))
4894 switch (GET_CODE (op))
4913 if (op1 != const0_rtx)
4917 if (GET_CODE (op0) != REG)
4920 regno = REGNO (op0);
4921 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4924 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4930 /* Return true if operator is EQ/NE of a conditional execution register. */
4933 ccr_eqne_operator (op, mode)
4935 enum machine_mode mode;
4937 enum machine_mode op_mode = GET_MODE (op);
4942 if (mode != VOIDmode && op_mode != mode)
4945 switch (GET_CODE (op))
4956 if (op1 != const0_rtx)
4960 if (GET_CODE (op0) != REG)
4963 regno = REGNO (op0);
4964 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4970 /* Return true if operator is a minimum or maximum operator (both signed and
4974 minmax_operator (op, mode)
4976 enum machine_mode mode;
4978 if (mode != VOIDmode && mode != GET_MODE (op))
4981 switch (GET_CODE (op))
4993 if (! integer_register_operand (XEXP (op, 0), mode))
4996 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5002 /* Return true if operator is an integer binary operator that can executed
5003 conditionally and takes 1 cycle. */
5006 condexec_si_binary_operator (op, mode)
5008 enum machine_mode mode;
5010 enum machine_mode op_mode = GET_MODE (op);
5012 if (mode != VOIDmode && op_mode != mode)
5015 switch (GET_CODE (op))
5032 /* Return true if operator is an integer binary operator that can be
5033 executed conditionally by a media instruction. */
5036 condexec_si_media_operator (op, mode)
5038 enum machine_mode mode;
5040 enum machine_mode op_mode = GET_MODE (op);
5042 if (mode != VOIDmode && op_mode != mode)
5045 switch (GET_CODE (op))
5057 /* Return true if operator is an integer division operator that can executed
5061 condexec_si_divide_operator (op, mode)
5063 enum machine_mode mode;
5065 enum machine_mode op_mode = GET_MODE (op);
5067 if (mode != VOIDmode && op_mode != mode)
5070 switch (GET_CODE (op))
5081 /* Return true if operator is an integer unary operator that can executed
5085 condexec_si_unary_operator (op, mode)
5087 enum machine_mode mode;
5089 enum machine_mode op_mode = GET_MODE (op);
5091 if (mode != VOIDmode && op_mode != mode)
5094 switch (GET_CODE (op))
5105 /* Return true if operator is a conversion-type expression that can be
5106 evaluated conditionally by floating-point instructions. */
5109 condexec_sf_conv_operator (op, mode)
5111 enum machine_mode mode;
5113 enum machine_mode op_mode = GET_MODE (op);
5115 if (mode != VOIDmode && op_mode != mode)
5118 switch (GET_CODE (op))
5129 /* Return true if operator is an addition or subtraction expression.
5130 Such expressions can be evaluated conditionally by floating-point
5134 condexec_sf_add_operator (op, mode)
5136 enum machine_mode mode;
5138 enum machine_mode op_mode = GET_MODE (op);
5140 if (mode != VOIDmode && op_mode != mode)
5143 switch (GET_CODE (op))
5154 /* Return true if the memory operand is one that can be conditionally
5158 condexec_memory_operand (op, mode)
5160 enum machine_mode mode;
5162 enum machine_mode op_mode = GET_MODE (op);
5165 if (mode != VOIDmode && op_mode != mode)
5180 if (GET_CODE (op) != MEM)
5183 addr = XEXP (op, 0);
5184 if (GET_CODE (addr) == ADDRESSOF)
5187 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE);
5190 /* Return true if operator is an integer binary operator that can be combined
5191 with a setcc operation. Do not allow the arithmetic operations that could
5192 potentially overflow since the FR-V sets the condition code based on the
5193 "true" value of the result, not the result after truncating to a 32-bit
5197 intop_compare_operator (op, mode)
5199 enum machine_mode mode;
5201 enum machine_mode op_mode = GET_MODE (op);
5203 if (mode != VOIDmode && op_mode != mode)
5206 switch (GET_CODE (op))
5219 if (! integer_register_operand (XEXP (op, 0), SImode))
5222 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5228 /* Return true if operator is an integer binary operator that can be combined
5229 with a setcc operation inside of a conditional execution. */
5232 condexec_intop_cmp_operator (op, mode)
5234 enum machine_mode mode;
5236 enum machine_mode op_mode = GET_MODE (op);
5238 if (mode != VOIDmode && op_mode != mode)
5241 switch (GET_CODE (op))
5254 if (! integer_register_operand (XEXP (op, 0), SImode))
5257 if (! integer_register_operand (XEXP (op, 1), SImode))
5263 /* Return 1 if operand is a valid ACC register number */
5266 acc_operand (op, mode)
5268 enum machine_mode mode;
5272 if (GET_MODE (op) != mode && mode != VOIDmode)
5275 if (GET_CODE (op) == SUBREG)
5277 if (GET_CODE (SUBREG_REG (op)) != REG)
5278 return register_operand (op, mode);
5280 op = SUBREG_REG (op);
5283 if (GET_CODE (op) != REG)
5287 return ACC_OR_PSEUDO_P (regno);
5290 /* Return 1 if operand is a valid even ACC register number */
5293 even_acc_operand (op, mode)
5295 enum machine_mode mode;
5299 if (GET_MODE (op) != mode && mode != VOIDmode)
5302 if (GET_CODE (op) == SUBREG)
5304 if (GET_CODE (SUBREG_REG (op)) != REG)
5305 return register_operand (op, mode);
5307 op = SUBREG_REG (op);
5310 if (GET_CODE (op) != REG)
5314 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5317 /* Return 1 if operand is zero or four */
5320 quad_acc_operand (op, mode)
5322 enum machine_mode mode;
5326 if (GET_MODE (op) != mode && mode != VOIDmode)
5329 if (GET_CODE (op) == SUBREG)
5331 if (GET_CODE (SUBREG_REG (op)) != REG)
5332 return register_operand (op, mode);
5334 op = SUBREG_REG (op);
5337 if (GET_CODE (op) != REG)
5341 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5344 /* Return 1 if operand is a valid ACCG register number */
5347 accg_operand (op, mode)
5349 enum machine_mode mode;
5351 if (GET_MODE (op) != mode && mode != VOIDmode)
5354 if (GET_CODE (op) == SUBREG)
5356 if (GET_CODE (SUBREG_REG (op)) != REG)
5357 return register_operand (op, mode);
5359 op = SUBREG_REG (op);
5362 if (GET_CODE (op) != REG)
5365 return ACCG_OR_PSEUDO_P (REGNO (op));
5369 /* Return true if the bare return instruction can be used outside of the
5370 epilog code. For frv, we only do it if there was no stack allocation. */
5377 if (!reload_completed)
5380 info = frv_stack_info ();
5381 return (info->total_size == 0);
5385 /* Emit code to handle a MOVSI, adding in the small data register or pic
5386 register if needed to load up addresses. Return TRUE if the appropriate
5387 instructions are emitted. */
5390 frv_emit_movsi (dest, src)
5394 int base_regno = -1;
5396 if (!reload_in_progress
5397 && !reload_completed
5398 && !register_operand (dest, SImode)
5399 && (!reg_or_0_operand (src, SImode)
5400 /* Virtual registers will almost always be replaced by an
5401 add instruction, so expose this to CSE by copying to
5402 an intermediate register */
5403 || (GET_CODE (src) == REG
5404 && IN_RANGE_P (REGNO (src),
5405 FIRST_VIRTUAL_REGISTER,
5406 LAST_VIRTUAL_REGISTER))))
5408 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5412 /* Explicitly add in the PIC or small data register if needed. */
5413 switch (GET_CODE (src))
5420 base_regno = PIC_REGNO;
5425 if (const_small_data_p (src))
5426 base_regno = SDA_BASE_REG;
5429 base_regno = PIC_REGNO;
5434 if (SYMBOL_REF_SMALL_P (src))
5435 base_regno = SDA_BASE_REG;
5438 base_regno = PIC_REGNO;
5443 if (base_regno >= 0)
5445 emit_insn (gen_rtx_SET (VOIDmode, dest,
5446 gen_rtx_PLUS (Pmode,
5447 gen_rtx_REG (Pmode, base_regno),
5450 if (base_regno == PIC_REGNO)
5451 cfun->uses_pic_offset_table = TRUE;
5460 /* Return a string to output a single word move. */
5463 output_move_single (operands, insn)
5467 rtx dest = operands[0];
5468 rtx src = operands[1];
5470 if (GET_CODE (dest) == REG)
5472 int dest_regno = REGNO (dest);
5473 enum machine_mode mode = GET_MODE (dest);
5475 if (GPR_P (dest_regno))
5477 if (GET_CODE (src) == REG)
5479 /* gpr <- some sort of register */
5480 int src_regno = REGNO (src);
5482 if (GPR_P (src_regno))
5483 return "mov %1, %0";
5485 else if (FPR_P (src_regno))
5486 return "movfg %1, %0";
5488 else if (SPR_P (src_regno))
5489 return "movsg %1, %0";
5492 else if (GET_CODE (src) == MEM)
5501 return "ldsb%I1%U1 %M1,%0";
5504 return "ldsh%I1%U1 %M1,%0";
5508 return "ld%I1%U1 %M1, %0";
5512 else if (GET_CODE (src) == CONST_INT
5513 || GET_CODE (src) == CONST_DOUBLE)
5515 /* gpr <- integer/floating constant */
5516 HOST_WIDE_INT value;
5518 if (GET_CODE (src) == CONST_INT)
5519 value = INTVAL (src);
5521 else if (mode == SFmode)
5526 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5527 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5532 value = CONST_DOUBLE_LOW (src);
5534 if (IN_RANGE_P (value, -32768, 32767))
5535 return "setlos %1, %0";
5540 else if (GET_CODE (src) == SYMBOL_REF
5541 || GET_CODE (src) == LABEL_REF
5542 || GET_CODE (src) == CONST)
5544 /* Silently fix up instances where the small data pointer is not
5545 used in the address. */
5546 if (small_data_symbolic_operand (src, GET_MODE (src)))
5547 return "addi %@, #gprel12(%1), %0";
5553 else if (FPR_P (dest_regno))
5555 if (GET_CODE (src) == REG)
5557 /* fpr <- some sort of register */
5558 int src_regno = REGNO (src);
5560 if (GPR_P (src_regno))
5561 return "movgf %1, %0";
5563 else if (FPR_P (src_regno))
5565 if (TARGET_HARD_FLOAT)
5566 return "fmovs %1, %0";
5568 return "mor %1, %1, %0";
5572 else if (GET_CODE (src) == MEM)
5581 return "ldbf%I1%U1 %M1,%0";
5584 return "ldhf%I1%U1 %M1,%0";
5588 return "ldf%I1%U1 %M1, %0";
5592 else if (ZERO_P (src))
5593 return "movgf %., %0";
5596 else if (SPR_P (dest_regno))
5598 if (GET_CODE (src) == REG)
5600 /* spr <- some sort of register */
5601 int src_regno = REGNO (src);
5603 if (GPR_P (src_regno))
5604 return "movgs %1, %0";
5609 else if (GET_CODE (dest) == MEM)
5611 if (GET_CODE (src) == REG)
5613 int src_regno = REGNO (src);
5614 enum machine_mode mode = GET_MODE (dest);
5616 if (GPR_P (src_regno))
5624 return "stb%I0%U0 %1, %M0";
5627 return "sth%I0%U0 %1, %M0";
5631 return "st%I0%U0 %1, %M0";
5635 else if (FPR_P (src_regno))
5643 return "stbf%I0%U0 %1, %M0";
5646 return "sthf%I0%U0 %1, %M0";
5650 return "stf%I0%U0 %1, %M0";
5655 else if (ZERO_P (src))
5657 switch (GET_MODE (dest))
5663 return "stb%I0%U0 %., %M0";
5666 return "sth%I0%U0 %., %M0";
5670 return "st%I0%U0 %., %M0";
5675 fatal_insn ("Bad output_move_single operand", insn);
5680 /* Return a string to output a double word move. */
5683 output_move_double (operands, insn)
5687 rtx dest = operands[0];
5688 rtx src = operands[1];
5689 enum machine_mode mode = GET_MODE (dest);
5691 if (GET_CODE (dest) == REG)
5693 int dest_regno = REGNO (dest);
5695 if (GPR_P (dest_regno))
5697 if (GET_CODE (src) == REG)
5699 /* gpr <- some sort of register */
5700 int src_regno = REGNO (src);
5702 if (GPR_P (src_regno))
5705 else if (FPR_P (src_regno))
5707 if (((dest_regno - GPR_FIRST) & 1) == 0
5708 && ((src_regno - FPR_FIRST) & 1) == 0)
5709 return "movfgd %1, %0";
5715 else if (GET_CODE (src) == MEM)
5718 if (dbl_memory_one_insn_operand (src, mode))
5719 return "ldd%I1%U1 %M1, %0";
5724 else if (GET_CODE (src) == CONST_INT
5725 || GET_CODE (src) == CONST_DOUBLE)
5729 else if (FPR_P (dest_regno))
5731 if (GET_CODE (src) == REG)
5733 /* fpr <- some sort of register */
5734 int src_regno = REGNO (src);
5736 if (GPR_P (src_regno))
5738 if (((dest_regno - FPR_FIRST) & 1) == 0
5739 && ((src_regno - GPR_FIRST) & 1) == 0)
5740 return "movgfd %1, %0";
5745 else if (FPR_P (src_regno))
5748 && ((dest_regno - FPR_FIRST) & 1) == 0
5749 && ((src_regno - FPR_FIRST) & 1) == 0)
5750 return "fmovd %1, %0";
5756 else if (GET_CODE (src) == MEM)
5759 if (dbl_memory_one_insn_operand (src, mode))
5760 return "lddf%I1%U1 %M1, %0";
5765 else if (ZERO_P (src))
5770 else if (GET_CODE (dest) == MEM)
5772 if (GET_CODE (src) == REG)
5774 int src_regno = REGNO (src);
5776 if (GPR_P (src_regno))
5778 if (((src_regno - GPR_FIRST) & 1) == 0
5779 && dbl_memory_one_insn_operand (dest, mode))
5780 return "std%I0%U0 %1, %M0";
5785 if (FPR_P (src_regno))
5787 if (((src_regno - FPR_FIRST) & 1) == 0
5788 && dbl_memory_one_insn_operand (dest, mode))
5789 return "stdf%I0%U0 %1, %M0";
5795 else if (ZERO_P (src))
5797 if (dbl_memory_one_insn_operand (dest, mode))
5798 return "std%I0%U0 %., %M0";
5804 fatal_insn ("Bad output_move_double operand", insn);
5809 /* Return a string to output a single word conditional move.
5810 Operand0 -- EQ/NE of ccr register and 0
5811 Operand1 -- CCR register
5812 Operand2 -- destination
5813 Operand3 -- source */
5816 output_condmove_single (operands, insn)
5820 rtx dest = operands[2];
5821 rtx src = operands[3];
5823 if (GET_CODE (dest) == REG)
5825 int dest_regno = REGNO (dest);
5826 enum machine_mode mode = GET_MODE (dest);
5828 if (GPR_P (dest_regno))
5830 if (GET_CODE (src) == REG)
5832 /* gpr <- some sort of register */
5833 int src_regno = REGNO (src);
5835 if (GPR_P (src_regno))
5836 return "cmov %z3, %2, %1, %e0";
5838 else if (FPR_P (src_regno))
5839 return "cmovfg %3, %2, %1, %e0";
5842 else if (GET_CODE (src) == MEM)
5851 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5854 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5858 return "cld%I3%U3 %M3, %2, %1, %e0";
5862 else if (ZERO_P (src))
5863 return "cmov %., %2, %1, %e0";
5866 else if (FPR_P (dest_regno))
5868 if (GET_CODE (src) == REG)
5870 /* fpr <- some sort of register */
5871 int src_regno = REGNO (src);
5873 if (GPR_P (src_regno))
5874 return "cmovgf %3, %2, %1, %e0";
5876 else if (FPR_P (src_regno))
5878 if (TARGET_HARD_FLOAT)
5879 return "cfmovs %3,%2,%1,%e0";
5881 return "cmor %3, %3, %2, %1, %e0";
5885 else if (GET_CODE (src) == MEM)
5888 if (mode == SImode || mode == SFmode)
5889 return "cldf%I3%U3 %M3, %2, %1, %e0";
5892 else if (ZERO_P (src))
5893 return "cmovgf %., %2, %1, %e0";
5897 else if (GET_CODE (dest) == MEM)
5899 if (GET_CODE (src) == REG)
5901 int src_regno = REGNO (src);
5902 enum machine_mode mode = GET_MODE (dest);
5904 if (GPR_P (src_regno))
5912 return "cstb%I2%U2 %3, %M2, %1, %e0";
5915 return "csth%I2%U2 %3, %M2, %1, %e0";
5919 return "cst%I2%U2 %3, %M2, %1, %e0";
5923 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5924 return "cstf%I2%U2 %3, %M2, %1, %e0";
5927 else if (ZERO_P (src))
5929 enum machine_mode mode = GET_MODE (dest);
5936 return "cstb%I2%U2 %., %M2, %1, %e0";
5939 return "csth%I2%U2 %., %M2, %1, %e0";
5943 return "cst%I2%U2 %., %M2, %1, %e0";
5948 fatal_insn ("Bad output_condmove_single operand", insn);
5953 /* Emit the appropriate code to do a comparison, returning the register the
5954 comparison was done it. */
5957 frv_emit_comparison (test, op0, op1)
5962 enum machine_mode cc_mode;
5965 /* Floating point doesn't have comparison against a constant */
5966 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
5967 op1 = force_reg (GET_MODE (op0), op1);
5969 /* Possibly disable using anything but a fixed register in order to work
5970 around cse moving comparisons past function calls. */
5971 cc_mode = SELECT_CC_MODE (test, op0, op1);
5972 cc_reg = ((TARGET_ALLOC_CC)
5973 ? gen_reg_rtx (cc_mode)
5974 : gen_rtx_REG (cc_mode,
5975 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
5977 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5978 gen_rtx_COMPARE (cc_mode, op0, op1)));
5984 /* Emit code for a conditional branch. The comparison operands were previously
5985 stored in frv_compare_op0 and frv_compare_op1.
5987 XXX: I originally wanted to add a clobber of a CCR register to use in
5988 conditional execution, but that confuses the rest of the compiler. */
5991 frv_emit_cond_branch (test, label)
5998 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5999 enum machine_mode cc_mode = GET_MODE (cc_reg);
6001 /* Branches generate:
6003 (if_then_else (<test>, <cc_reg>, (const_int 0))
6004 (label_ref <branch_label>)
6006 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6007 test_rtx = gen_rtx (test, cc_mode, cc_reg, const0_rtx);
6008 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6009 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6014 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6015 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6018 frv_emit_scc (test, target)
6026 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6028 /* SCC instructions generate:
6029 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6030 (clobber (<ccr_reg>))]) */
6031 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6032 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6034 cr_reg = ((TARGET_ALLOC_CC)
6035 ? gen_reg_rtx (CC_CCRmode)
6036 : gen_rtx_REG (CC_CCRmode,
6037 ((GET_MODE (cc_reg) == CC_FPmode)
6041 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6042 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6047 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6048 the seperate insns. */
6051 frv_split_scc (dest, test, cc_reg, cr_reg, value)
6056 HOST_WIDE_INT value;
6062 /* Set the appropriate CCR bit. */
6063 emit_insn (gen_rtx_SET (VOIDmode,
6065 gen_rtx_fmt_ee (GET_CODE (test),
6070 /* Move the value into the destination. */
6071 emit_move_insn (dest, GEN_INT (value));
6073 /* Move 0 into the destination if the test failed */
6074 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6075 gen_rtx_EQ (GET_MODE (cr_reg),
6078 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6080 /* Finish up, return sequence. */
6087 /* Emit the code for a conditional move, return TRUE if we could do the
6091 frv_emit_cond_move (dest, test_rtx, src1, src2)
6102 enum rtx_code test = GET_CODE (test_rtx);
6103 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6104 enum machine_mode cc_mode = GET_MODE (cc_reg);
6106 /* Conditional move instructions generate:
6107 (parallel [(set <target>
6108 (if_then_else (<test> <cc_reg> (const_int 0))
6111 (clobber (<ccr_reg>))]) */
6113 /* Handle various cases of conditional move involving two constants. */
6114 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6116 HOST_WIDE_INT value1 = INTVAL (src1);
6117 HOST_WIDE_INT value2 = INTVAL (src2);
6119 /* having 0 as one of the constants can be done by loading the other
6120 constant, and optionally moving in gr0. */
6121 if (value1 == 0 || value2 == 0)
6124 /* If the first value is within an addi range and also the difference
6125 between the two fits in an addi's range, load up the difference, then
6126 conditionally move in 0, and then unconditionally add the first
6128 else if (IN_RANGE_P (value1, -2048, 2047)
6129 && IN_RANGE_P (value2 - value1, -2048, 2047))
6132 /* If neither condition holds, just force the constant into a
6136 src1 = force_reg (GET_MODE (dest), src1);
6137 src2 = force_reg (GET_MODE (dest), src2);
6141 /* If one value is a register, insure the other value is either 0 or a
6145 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6146 src1 = force_reg (GET_MODE (dest), src1);
6148 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6149 src2 = force_reg (GET_MODE (dest), src2);
6152 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6153 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6155 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6157 cr_reg = ((TARGET_ALLOC_CC)
6158 ? gen_reg_rtx (CC_CCRmode)
6159 : gen_rtx_REG (CC_CCRmode,
6160 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6162 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6163 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6168 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6169 containing all of the insns. */
6172 frv_split_cond_move (operands)
6175 rtx dest = operands[0];
6176 rtx test = operands[1];
6177 rtx cc_reg = operands[2];
6178 rtx src1 = operands[3];
6179 rtx src2 = operands[4];
6180 rtx cr_reg = operands[5];
6182 enum machine_mode cr_mode = GET_MODE (cr_reg);
6186 /* Set the appropriate CCR bit. */
6187 emit_insn (gen_rtx_SET (VOIDmode,
6189 gen_rtx_fmt_ee (GET_CODE (test),
6194 /* Handle various cases of conditional move involving two constants. */
6195 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6197 HOST_WIDE_INT value1 = INTVAL (src1);
6198 HOST_WIDE_INT value2 = INTVAL (src2);
6200 /* having 0 as one of the constants can be done by loading the other
6201 constant, and optionally moving in gr0. */
6204 emit_move_insn (dest, src2);
6205 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6206 gen_rtx_NE (cr_mode, cr_reg,
6208 gen_rtx_SET (VOIDmode, dest, src1)));
6211 else if (value2 == 0)
6213 emit_move_insn (dest, src1);
6214 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6215 gen_rtx_EQ (cr_mode, cr_reg,
6217 gen_rtx_SET (VOIDmode, dest, src2)));
6220 /* If the first value is within an addi range and also the difference
6221 between the two fits in an addi's range, load up the difference, then
6222 conditionally move in 0, and then unconditionally add the first
6224 else if (IN_RANGE_P (value1, -2048, 2047)
6225 && IN_RANGE_P (value2 - value1, -2048, 2047))
6227 rtx dest_si = ((GET_MODE (dest) == SImode)
6229 : gen_rtx_SUBREG (SImode, dest, 0));
6231 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6232 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6233 gen_rtx_NE (cr_mode, cr_reg,
6235 gen_rtx_SET (VOIDmode, dest_si,
6237 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6245 /* Emit the conditional move for the test being true if needed. */
6246 if (! rtx_equal_p (dest, src1))
6247 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6248 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6249 gen_rtx_SET (VOIDmode, dest, src1)));
6251 /* Emit the conditional move for the test being false if needed. */
6252 if (! rtx_equal_p (dest, src2))
6253 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6254 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6255 gen_rtx_SET (VOIDmode, dest, src2)));
6258 /* Finish up, return sequence. */
6265 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6266 memory location that is not known to be dword-aligned. */
6268 frv_split_double_load (dest, source)
6272 int regno = REGNO (dest);
6273 rtx dest1 = gen_highpart (SImode, dest);
6274 rtx dest2 = gen_lowpart (SImode, dest);
6275 rtx address = XEXP (source, 0);
6277 /* If the address is pre-modified, load the lower-numbered register
6278 first, then load the other register using an integer offset from
6279 the modified base register. This order should always be safe,
6280 since the pre-modification cannot affect the same registers as the
6283 The situation for other loads is more complicated. Loading one
6284 of the registers could affect the value of ADDRESS, so we must
6285 be careful which order we do them in. */
6286 if (GET_CODE (address) == PRE_MODIFY
6287 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6289 /* It is safe to load the lower-numbered register first. */
6290 emit_move_insn (dest1, change_address (source, SImode, NULL));
6291 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6295 /* ADDRESS is not pre-modified and the address depends on the
6296 lower-numbered register. Load the higher-numbered register
6298 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6299 emit_move_insn (dest1, change_address (source, SImode, NULL));
6303 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6304 and SOURCE is either a double register or the constant zero. */
6306 frv_split_double_store (dest, source)
6310 rtx dest1 = change_address (dest, SImode, NULL);
6311 rtx dest2 = frv_index_memory (dest, SImode, 1);
6312 if (ZERO_P (source))
6314 emit_move_insn (dest1, CONST0_RTX (SImode));
6315 emit_move_insn (dest2, CONST0_RTX (SImode));
6319 emit_move_insn (dest1, gen_highpart (SImode, source));
6320 emit_move_insn (dest2, gen_lowpart (SImode, source));
6325 /* Split a min/max operation returning a SEQUENCE containing all of the
6329 frv_split_minmax (operands)
6332 rtx dest = operands[0];
6333 rtx minmax = operands[1];
6334 rtx src1 = operands[2];
6335 rtx src2 = operands[3];
6336 rtx cc_reg = operands[4];
6337 rtx cr_reg = operands[5];
6339 enum rtx_code test_code;
6340 enum machine_mode cr_mode = GET_MODE (cr_reg);
6344 /* Figure out which test to use */
6345 switch (GET_CODE (minmax))
6350 case SMIN: test_code = LT; break;
6351 case SMAX: test_code = GT; break;
6352 case UMIN: test_code = LTU; break;
6353 case UMAX: test_code = GTU; break;
6356 /* Issue the compare instruction. */
6357 emit_insn (gen_rtx_SET (VOIDmode,
6359 gen_rtx_COMPARE (GET_MODE (cc_reg),
6362 /* Set the appropriate CCR bit. */
6363 emit_insn (gen_rtx_SET (VOIDmode,
6365 gen_rtx_fmt_ee (test_code,
6370 /* If are taking the min/max of a nonzero constant, load that first, and
6371 then do a conditional move of the other value. */
6372 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6374 if (rtx_equal_p (dest, src1))
6377 emit_move_insn (dest, src2);
6378 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6379 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6380 gen_rtx_SET (VOIDmode, dest, src1)));
6383 /* Otherwise, do each half of the move. */
6386 /* Emit the conditional move for the test being true if needed. */
6387 if (! rtx_equal_p (dest, src1))
6388 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6389 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6390 gen_rtx_SET (VOIDmode, dest, src1)));
6392 /* Emit the conditional move for the test being false if needed. */
6393 if (! rtx_equal_p (dest, src2))
6394 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6395 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6396 gen_rtx_SET (VOIDmode, dest, src2)));
6399 /* Finish up, return sequence. */
6406 /* Split an integer abs operation returning a SEQUENCE containing all of the
6410 frv_split_abs (operands)
6413 rtx dest = operands[0];
6414 rtx src = operands[1];
6415 rtx cc_reg = operands[2];
6416 rtx cr_reg = operands[3];
6421 /* Issue the compare < 0 instruction. */
6422 emit_insn (gen_rtx_SET (VOIDmode,
6424 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6426 /* Set the appropriate CCR bit. */
6427 emit_insn (gen_rtx_SET (VOIDmode,
6429 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6431 /* Emit the conditional negate if the value is negative */
6432 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6433 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6434 gen_negsi2 (dest, src)));
6436 /* Emit the conditional move for the test being false if needed. */
6437 if (! rtx_equal_p (dest, src))
6438 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6439 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6440 gen_rtx_SET (VOIDmode, dest, src)));
6442 /* Finish up, return sequence. */
6449 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6450 register used in an insn. */
6453 frv_clear_registers_used (ptr, data)
6457 if (GET_CODE (*ptr) == REG)
6459 int regno = REGNO (*ptr);
6460 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6462 if (regno < FIRST_PSEUDO_REGISTER)
6464 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6466 while (regno < reg_max)
6468 CLEAR_HARD_REG_BIT (*p_regs, regno);
6478 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6480 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6481 initialize the static storage. */
6483 frv_ifcvt_init_extra_fields (ce_info)
6484 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
6486 frv_ifcvt.added_insns_list = NULL_RTX;
6487 frv_ifcvt.cur_scratch_regs = 0;
6488 frv_ifcvt.num_nested_cond_exec = 0;
6489 frv_ifcvt.cr_reg = NULL_RTX;
6490 frv_ifcvt.nested_cc_reg = NULL_RTX;
6491 frv_ifcvt.extra_int_cr = NULL_RTX;
6492 frv_ifcvt.extra_fp_cr = NULL_RTX;
6493 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6497 /* Internal function to add a potenial insn to the list of insns to be inserted
6498 if the conditional execution conversion is successful. */
6501 frv_ifcvt_add_insn (pattern, insn, before_p)
6506 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6508 link->jump = before_p; /* mark to add this before or after insn */
6509 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6510 frv_ifcvt.added_insns_list);
6512 if (TARGET_DEBUG_COND_EXEC)
6515 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6516 (before_p) ? "before" : "after",
6517 (int)INSN_UID (insn));
6519 debug_rtx (pattern);
6524 /* A C expression to modify the code described by the conditional if
6525 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6526 FALSE_EXPR for converting if-then and if-then-else code to conditional
6527 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6528 tests cannot be converted. */
6531 frv_ifcvt_modify_tests (ce_info, p_true, p_false)
6532 ce_if_block_t *ce_info;
6536 basic_block test_bb = ce_info->test_bb; /* test basic block */
6537 basic_block then_bb = ce_info->then_bb; /* THEN */
6538 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6539 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6540 rtx true_expr = *p_true;
6544 enum machine_mode mode = GET_MODE (true_expr);
6548 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6550 rtx sub_cond_exec_reg;
6552 enum rtx_code code_true;
6553 enum rtx_code code_false;
6554 enum reg_class cc_class;
6555 enum reg_class cr_class;
6559 /* Make sure we are only dealing with hard registers. Also honor the
6560 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6562 if (!reload_completed || TARGET_NO_COND_EXEC
6563 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6566 /* Figure out which registers we can allocate for our own purposes. Only
6567 consider registers that are not preserved across function calls and are
6568 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6569 if we did not need to use them in reloading other registers. */
6570 memset ((PTR) &tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6571 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6572 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6573 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6574 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6576 /* If this is a nested IF, we need to discover whether the CC registers that
6577 are set/used inside of the block are used anywhere else. If not, we can
6578 change them to be the CC register that is paired with the CR register that
6579 controls the outermost IF block. */
6580 if (ce_info->pass > 1)
6582 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6583 for (j = CC_FIRST; j <= CC_LAST; j++)
6584 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6586 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6589 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6592 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6595 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6599 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6600 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6602 frv_ifcvt.added_insns_list = NULL_RTX;
6603 frv_ifcvt.cur_scratch_regs = 0;
6605 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6606 * sizeof (basic_block));
6612 /* Remove anything live at the beginning of the join block from being
6613 available for allocation. */
6614 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6616 if (regno < FIRST_PSEUDO_REGISTER)
6617 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6621 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6623 if (ce_info->num_multiple_test_blocks)
6625 basic_block multiple_test_bb = ce_info->last_test_bb;
6627 while (multiple_test_bb != test_bb)
6629 bb[num_bb++] = multiple_test_bb;
6630 multiple_test_bb = multiple_test_bb->pred->src;
6634 /* Add in the THEN and ELSE blocks to be scanned. */
6635 bb[num_bb++] = then_bb;
6637 bb[num_bb++] = else_bb;
6639 sub_cond_exec_reg = NULL_RTX;
6640 frv_ifcvt.num_nested_cond_exec = 0;
6642 /* Scan all of the blocks for registers that must not be allocated. */
6643 for (j = 0; j < num_bb; j++)
6645 rtx last_insn = bb[j]->end;
6646 rtx insn = bb[j]->head;
6650 fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n",
6651 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6653 (int) INSN_UID (bb[j]->head),
6654 (int) INSN_UID (bb[j]->end));
6656 /* Anything live at the beginning of the block is obviously unavailable
6658 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6660 if (regno < FIRST_PSEUDO_REGISTER)
6661 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6664 /* loop through the insns in the block. */
6667 /* Mark any new registers that are created as being unavailable for
6668 allocation. Also see if the CC register used in nested IFs can be
6674 int skip_nested_if = FALSE;
6676 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6677 (void *)&tmp_reg->regs);
6679 pattern = PATTERN (insn);
6680 if (GET_CODE (pattern) == COND_EXEC)
6682 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6684 if (reg != sub_cond_exec_reg)
6686 sub_cond_exec_reg = reg;
6687 frv_ifcvt.num_nested_cond_exec++;
6691 set = single_set_pattern (pattern);
6694 rtx dest = SET_DEST (set);
6695 rtx src = SET_SRC (set);
6697 if (GET_CODE (dest) == REG)
6699 int regno = REGNO (dest);
6700 enum rtx_code src_code = GET_CODE (src);
6702 if (CC_P (regno) && src_code == COMPARE)
6703 skip_nested_if = TRUE;
6705 else if (CR_P (regno)
6706 && (src_code == IF_THEN_ELSE
6707 || GET_RTX_CLASS (src_code) == '<'))
6708 skip_nested_if = TRUE;
6712 if (! skip_nested_if)
6713 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6714 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6717 if (insn == last_insn)
6720 insn = NEXT_INSN (insn);
6724 /* If this is a nested if, rewrite the CC registers that are available to
6725 include the ones that can be rewritten, to increase the chance of being
6726 able to allocate a paired CC/CR register combination. */
6727 if (ce_info->pass > 1)
6729 for (j = CC_FIRST; j <= CC_LAST; j++)
6730 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6731 SET_HARD_REG_BIT (tmp_reg->regs, j);
6733 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6739 fprintf (rtl_dump_file, "Available GPRs: ");
6741 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6742 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6744 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6745 if (++num_gprs > GPR_TEMP_NUM+2)
6749 fprintf (rtl_dump_file, "%s\nAvailable CRs: ",
6750 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6752 for (j = CR_FIRST; j <= CR_LAST; j++)
6753 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6754 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6756 fputs ("\n", rtl_dump_file);
6758 if (ce_info->pass > 1)
6760 fprintf (rtl_dump_file, "Modifiable CCs: ");
6761 for (j = CC_FIRST; j <= CC_LAST; j++)
6762 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6763 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6765 fprintf (rtl_dump_file, "\n%d nested COND_EXEC statements\n",
6766 frv_ifcvt.num_nested_cond_exec);
6770 /* Allocate the appropriate temporary condition code register. Try to
6771 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6772 that conditional cmp's can be done. */
6773 if (mode == CCmode || mode == CC_UNSmode)
6775 cr_class = ICR_REGS;
6776 cc_class = ICC_REGS;
6777 cc_first = ICC_FIRST;
6780 else if (mode == CC_FPmode)
6782 cr_class = FCR_REGS;
6783 cc_class = FCC_REGS;
6784 cc_first = FCC_FIRST;
6789 cc_first = cc_last = 0;
6790 cr_class = cc_class = NO_REGS;
6793 cc = XEXP (true_expr, 0);
6794 nested_cc = cr = NULL_RTX;
6795 if (cc_class != NO_REGS)
6797 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6798 so we can execute a csubcc/caddcc/cfcmps instruction. */
6801 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6803 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6805 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6806 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6808 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6809 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6812 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6813 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6823 fprintf (rtl_dump_file, "Could not allocate a CR temporary register\n");
6829 fprintf (rtl_dump_file,
6830 "Will use %s for conditional execution, %s for nested comparisons\n",
6831 reg_names[ REGNO (cr)],
6832 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6834 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6835 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6836 bit being true. We don't do this for floating point, because of NaNs. */
6837 code = GET_CODE (true_expr);
6838 if (GET_MODE (cc) != CC_FPmode)
6840 code = reverse_condition (code);
6850 check_insn = gen_rtx_SET (VOIDmode, cr,
6851 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6853 /* Record the check insn to be inserted later. */
6854 frv_ifcvt_add_insn (check_insn, test_bb->end, TRUE);
6856 /* Update the tests. */
6857 frv_ifcvt.cr_reg = cr;
6858 frv_ifcvt.nested_cc_reg = nested_cc;
6859 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6860 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6863 /* Fail, don't do this conditional execution. */
6866 *p_false = NULL_RTX;
6868 fprintf (rtl_dump_file, "Disabling this conditional execution.\n");
6874 /* A C expression to modify the code described by the conditional if
6875 information CE_INFO, for the basic block BB, possibly updating the tests in
6876 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6877 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6878 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6880 /* p_true and p_false are given expressions of the form:
6882 (and (eq:CC_CCR (reg:CC_CCR)
6888 frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false)
6889 ce_if_block_t *ce_info;
6894 rtx old_true = XEXP (*p_true, 0);
6895 rtx old_false = XEXP (*p_false, 0);
6896 rtx true_expr = XEXP (*p_true, 1);
6897 rtx false_expr = XEXP (*p_false, 1);
6900 rtx cr = XEXP (old_true, 0);
6902 rtx new_cr = NULL_RTX;
6903 rtx *p_new_cr = (rtx *)0;
6907 enum reg_class cr_class;
6908 enum machine_mode mode = GET_MODE (true_expr);
6909 rtx (*logical_func)(rtx, rtx, rtx);
6911 if (TARGET_DEBUG_COND_EXEC)
6914 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6915 ce_info->and_and_p ? "&&" : "||");
6917 debug_rtx (*p_true);
6919 fputs ("\nfalse insn:\n", stderr);
6920 debug_rtx (*p_false);
6923 if (TARGET_NO_MULTI_CE)
6926 if (GET_CODE (cr) != REG)
6929 if (mode == CCmode || mode == CC_UNSmode)
6931 cr_class = ICR_REGS;
6932 p_new_cr = &frv_ifcvt.extra_int_cr;
6934 else if (mode == CC_FPmode)
6936 cr_class = FCR_REGS;
6937 p_new_cr = &frv_ifcvt.extra_fp_cr;
6942 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6943 more &&/|| tests. */
6947 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
6948 CC_CCRmode, TRUE, TRUE);
6953 if (ce_info->and_and_p)
6955 old_test = old_false;
6956 test_expr = true_expr;
6957 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
6958 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6959 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6963 old_test = old_false;
6964 test_expr = false_expr;
6965 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
6966 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6967 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6970 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6971 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6973 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), bb->end, TRUE);
6975 /* Now add the conditional check insn. */
6976 cc = XEXP (test_expr, 0);
6977 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
6978 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
6980 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
6982 /* add the new check insn to the list of check insns that need to be
6984 frv_ifcvt_add_insn (check_insn, bb->end, TRUE);
6986 if (TARGET_DEBUG_COND_EXEC)
6988 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6991 debug_rtx (*p_true);
6993 fputs ("\nfalse insn:\n", stderr);
6994 debug_rtx (*p_false);
7000 *p_true = *p_false = NULL_RTX;
7002 /* If we allocated a CR register, release it. */
7005 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7006 *p_new_cr = NULL_RTX;
7009 if (TARGET_DEBUG_COND_EXEC)
7010 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7016 /* Return a register which will be loaded with a value if an IF block is
7017 converted to conditional execution. This is used to rewrite instructions
7018 that use constants to ones that just use registers. */
7021 frv_ifcvt_load_value (value, insn)
7023 rtx insn ATTRIBUTE_UNUSED;
7025 int num_alloc = frv_ifcvt.cur_scratch_regs;
7029 /* We know gr0 == 0, so replace any errant uses. */
7030 if (value == const0_rtx)
7031 return gen_rtx_REG (SImode, GPR_FIRST);
7033 /* First search all registers currently loaded to see if we have an
7034 applicable constant. */
7035 if (CONSTANT_P (value)
7036 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7038 for (i = 0; i < num_alloc; i++)
7040 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7041 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7045 /* Have we exhausted the number of registers available? */
7046 if (num_alloc >= GPR_TEMP_NUM)
7049 fprintf (rtl_dump_file, "Too many temporary registers allocated\n");
7054 /* Allocate the new register. */
7055 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7059 fputs ("Could not find a scratch register\n", rtl_dump_file);
7064 frv_ifcvt.cur_scratch_regs++;
7065 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7069 if (GET_CODE (value) == CONST_INT)
7070 fprintf (rtl_dump_file, "Register %s will hold %ld\n",
7071 reg_names[ REGNO (reg)], (long)INTVAL (value));
7073 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7074 fprintf (rtl_dump_file, "Register %s will hold LR\n",
7075 reg_names[ REGNO (reg)]);
7078 fprintf (rtl_dump_file, "Register %s will hold a saved value\n",
7079 reg_names[ REGNO (reg)]);
7086 /* Update a MEM used in conditional code that might contain an offset to put
7087 the offset into a scratch register, so that the conditional load/store
7088 operations can be used. This function returns the original pointer if the
7089 MEM is valid to use in conditional code, NULL if we can't load up the offset
7090 into a temporary register, or the new MEM if we were successful. */
7093 frv_ifcvt_rewrite_mem (mem, mode, insn)
7095 enum machine_mode mode;
7098 rtx addr = XEXP (mem, 0);
7100 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE))
7102 if (GET_CODE (addr) == PLUS)
7104 rtx addr_op0 = XEXP (addr, 0);
7105 rtx addr_op1 = XEXP (addr, 1);
7107 if (plus_small_data_p (addr_op0, addr_op1))
7108 addr = frv_ifcvt_load_value (addr, insn);
7110 else if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7112 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7116 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7123 else if (CONSTANT_P (addr))
7124 addr = frv_ifcvt_load_value (addr, insn);
7129 if (addr == NULL_RTX)
7132 else if (XEXP (mem, 0) != addr)
7133 return change_address (mem, mode, addr);
7140 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7141 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7144 single_set_pattern (pattern)
7150 if (GET_CODE (pattern) == COND_EXEC)
7151 pattern = COND_EXEC_CODE (pattern);
7153 if (GET_CODE (pattern) == SET)
7156 else if (GET_CODE (pattern) == PARALLEL)
7158 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7160 rtx sub = XVECEXP (pattern, 0, i);
7162 switch (GET_CODE (sub))
7186 /* A C expression to modify the code described by the conditional if
7187 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7188 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7189 insn cannot be converted to be executed conditionally. */
7192 frv_ifcvt_modify_insn (ce_info, pattern, insn)
7193 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7197 rtx orig_ce_pattern = pattern;
7203 if (GET_CODE (pattern) != COND_EXEC)
7206 test = COND_EXEC_TEST (pattern);
7207 if (GET_CODE (test) == AND)
7209 rtx cr = frv_ifcvt.cr_reg;
7212 op0 = XEXP (test, 0);
7213 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7216 op1 = XEXP (test, 1);
7217 test_reg = XEXP (op1, 0);
7218 if (GET_CODE (test_reg) != REG)
7221 /* Is this the first nested if block in this sequence? If so, generate
7222 an andcr or andncr. */
7223 if (! frv_ifcvt.last_nested_if_cr)
7227 frv_ifcvt.last_nested_if_cr = test_reg;
7228 if (GET_CODE (op0) == NE)
7229 and_op = gen_andcr (test_reg, cr, test_reg);
7231 and_op = gen_andncr (test_reg, cr, test_reg);
7233 frv_ifcvt_add_insn (and_op, insn, TRUE);
7236 /* If this isn't the first statement in the nested if sequence, see if we
7237 are dealing with the same register. */
7238 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7241 COND_EXEC_TEST (pattern) = test = op1;
7244 /* If this isn't a nested if, reset state variables. */
7247 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7250 set = single_set_pattern (pattern);
7253 rtx dest = SET_DEST (set);
7254 rtx src = SET_SRC (set);
7255 enum machine_mode mode = GET_MODE (dest);
7257 /* Check for normal binary operators */
7259 && (GET_RTX_CLASS (GET_CODE (src)) == '2'
7260 || GET_RTX_CLASS (GET_CODE (src)) == 'c'))
7262 op0 = XEXP (src, 0);
7263 op1 = XEXP (src, 1);
7265 /* Special case load of small data address which looks like:
7267 if (GET_CODE (src) == PLUS && plus_small_data_p (op0, op1))
7269 src = frv_ifcvt_load_value (src, insn);
7271 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7276 else if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7278 op1 = frv_ifcvt_load_value (op1, insn);
7280 COND_EXEC_CODE (pattern)
7281 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7289 /* For multiply by a constant, we need to handle the sign extending
7290 correctly. Add a USE of the value after the multiply to prevent flow
7291 from cratering because only one register out of the two were used. */
7292 else if (mode == DImode && GET_CODE (src) == MULT)
7294 op0 = XEXP (src, 0);
7295 op1 = XEXP (src, 1);
7296 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7298 op1 = frv_ifcvt_load_value (op1, insn);
7301 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7302 COND_EXEC_CODE (pattern)
7303 = gen_rtx_SET (VOIDmode, dest,
7304 gen_rtx_MULT (DImode, op0, op1));
7310 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7313 /* If we are just loading a constant created for a nested conditional
7314 execution statement, just load the constant without any conditional
7315 execution, since we know that the constant will not interfere with any
7317 else if (frv_ifcvt.scratch_insns_bitmap
7318 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7322 else if (mode == QImode || mode == HImode || mode == SImode
7325 int changed_p = FALSE;
7327 /* Check for just loading up a constant */
7328 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7330 src = frv_ifcvt_load_value (src, insn);
7337 /* See if we need to fix up stores */
7338 if (GET_CODE (dest) == MEM)
7340 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7345 else if (new_mem != dest)
7352 /* See if we need to fix up loads */
7353 if (GET_CODE (src) == MEM)
7355 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7360 else if (new_mem != src)
7367 /* If either src or destination changed, redo SET. */
7369 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7372 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7373 rewriting the CC register to be the same as the paired CC/CR register
7375 else if (mode == CC_CCRmode && GET_RTX_CLASS (GET_CODE (src)) == '<')
7377 int regno = REGNO (XEXP (src, 0));
7380 if (ce_info->pass > 1
7381 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7382 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7384 src = gen_rtx_fmt_ee (GET_CODE (src),
7386 frv_ifcvt.nested_cc_reg,
7390 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7391 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7394 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7395 else if (ce_info->pass > 1
7396 && GET_CODE (dest) == REG
7397 && CC_P (REGNO (dest))
7398 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7399 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7401 && GET_CODE (src) == COMPARE)
7403 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7404 COND_EXEC_CODE (pattern)
7405 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7409 if (TARGET_DEBUG_COND_EXEC)
7411 rtx orig_pattern = PATTERN (insn);
7413 PATTERN (insn) = pattern;
7415 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7419 PATTERN (insn) = orig_pattern;
7425 if (TARGET_DEBUG_COND_EXEC)
7427 rtx orig_pattern = PATTERN (insn);
7429 PATTERN (insn) = orig_ce_pattern;
7431 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7435 PATTERN (insn) = orig_pattern;
7442 /* A C expression to perform any final machine dependent modifications in
7443 converting code to conditional execution in the code described by the
7444 conditional if information CE_INFO. */
7447 frv_ifcvt_modify_final (ce_info)
7448 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7452 rtx p = frv_ifcvt.added_insns_list;
7455 /* Loop inserting the check insns. The last check insn is the first test,
7456 and is the appropriate place to insert constants. */
7462 rtx check_and_insert_insns = XEXP (p, 0);
7465 check_insn = XEXP (check_and_insert_insns, 0);
7466 existing_insn = XEXP (check_and_insert_insns, 1);
7469 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7470 the existing insn, otherwise it is to be inserted AFTER. */
7471 if (check_and_insert_insns->jump)
7473 emit_insn_before (check_insn, existing_insn);
7474 check_and_insert_insns->jump = 0;
7477 emit_insn_after (check_insn, existing_insn);
7479 free_EXPR_LIST_node (check_and_insert_insns);
7480 free_EXPR_LIST_node (old_p);
7482 while (p != NULL_RTX);
7484 /* Load up any constants needed into temp gprs */
7485 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7487 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7488 if (! frv_ifcvt.scratch_insns_bitmap)
7489 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7490 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7491 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7494 frv_ifcvt.added_insns_list = NULL_RTX;
7495 frv_ifcvt.cur_scratch_regs = 0;
7499 /* A C expression to cancel any machine dependent modifications in converting
7500 code to conditional execution in the code described by the conditional if
7501 information CE_INFO. */
7504 frv_ifcvt_modify_cancel (ce_info)
7505 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7508 rtx p = frv_ifcvt.added_insns_list;
7510 /* Loop freeing up the EXPR_LIST's allocated. */
7511 while (p != NULL_RTX)
7513 rtx check_and_jump = XEXP (p, 0);
7517 free_EXPR_LIST_node (check_and_jump);
7518 free_EXPR_LIST_node (old_p);
7521 /* Release any temporary gprs allocated. */
7522 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7523 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7525 frv_ifcvt.added_insns_list = NULL_RTX;
7526 frv_ifcvt.cur_scratch_regs = 0;
7530 /* A C expression for the size in bytes of the trampoline, as an integer.
7534 setlo #0, <static_chain>
7536 sethi #0, <static_chain>
7537 jmpl @(gr0,<jmp_reg>) */
7540 frv_trampoline_size ()
7542 return 5 /* instructions */ * 4 /* instruction size */;
7546 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7547 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7548 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7549 should be passed to the function when it is called.
7554 setlo #0, <static_chain>
7556 sethi #0, <static_chain>
7557 jmpl @(gr0,<jmp_reg>) */
7560 frv_initialize_trampoline (addr, fnaddr, static_chain)
7565 rtx sc_reg = force_reg (Pmode, static_chain);
7567 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7570 GEN_INT (frv_trampoline_size ()), SImode,
7576 /* Many machines have some registers that cannot be copied directly to or from
7577 memory or even from other types of registers. An example is the `MQ'
7578 register, which on most machines, can only be copied to or from general
7579 registers, but not memory. Some machines allow copying all registers to and
7580 from memory, but require a scratch register for stores to some memory
7581 locations (e.g., those with symbolic address on the RT, and those with
7582 certain symbolic address on the SPARC when compiling PIC). In some cases,
7583 both an intermediate and a scratch register are required.
7585 You should define these macros to indicate to the reload phase that it may
7586 need to allocate at least one register for a reload in addition to the
7587 register to contain the data. Specifically, if copying X to a register
7588 CLASS in MODE requires an intermediate register, you should define
7589 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7590 whose registers can be used as intermediate registers or scratch registers.
7592 If copying a register CLASS in MODE to X requires an intermediate or scratch
7593 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7594 largest register class required. If the requirements for input and output
7595 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7596 instead of defining both macros identically.
7598 The values returned by these macros are often `GENERAL_REGS'. Return
7599 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7600 to or from a register of CLASS in MODE without requiring a scratch register.
7601 Do not define this macro if it would always return `NO_REGS'.
7603 If a scratch register is required (either with or without an intermediate
7604 register), you should define patterns for `reload_inM' or `reload_outM', as
7605 required.. These patterns, which will normally be implemented with a
7606 `define_expand', should be similar to the `movM' patterns, except that
7607 operand 2 is the scratch register.
7609 Define constraints for the reload register and scratch register that contain
7610 a single register class. If the original reload register (whose class is
7611 CLASS) can meet the constraint given in the pattern, the value returned by
7612 these macros is used for the class of the scratch register. Otherwise, two
7613 additional reload registers are required. Their classes are obtained from
7614 the constraints in the insn pattern.
7616 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7617 either be in a hard register or in memory. Use `true_regnum' to find out;
7618 it will return -1 if the pseudo is in memory and the hard register number if
7619 it is in a register.
7621 These macros should not be used in the case where a particular class of
7622 registers can only be copied to memory and not to another class of
7623 registers. In that case, secondary reload registers are not needed and
7624 would not be helpful. Instead, a stack location must be used to perform the
7625 copy and the `movM' pattern should use memory as an intermediate storage.
7626 This case often occurs between floating-point and general registers. */
7629 frv_secondary_reload_class (class, mode, x, in_p)
7630 enum reg_class class;
7631 enum machine_mode mode ATTRIBUTE_UNUSED;
7633 int in_p ATTRIBUTE_UNUSED;
7643 /* Accumulators/Accumulator guard registers need to go through floating
7649 if (x && GET_CODE (x) == REG)
7651 int regno = REGNO (x);
7653 if (ACC_P (regno) || ACCG_P (regno))
7658 /* Nonzero constants should be loaded into an FPR through a GPR. */
7662 if (x && CONSTANT_P (x) && !ZERO_P (x))
7668 /* All of these types need gpr registers. */
7680 /* The accumulators need fpr registers */
7693 /* A C expression whose value is nonzero if pseudos that have been assigned to
7694 registers of class CLASS would likely be spilled because registers of CLASS
7695 are needed for spill registers.
7697 The default value of this macro returns 1 if CLASS has exactly one register
7698 and zero otherwise. On most machines, this default should be used. Only
7699 define this macro to some other expression if pseudo allocated by
7700 `local-alloc.c' end up in memory because their hard registers were needed
7701 for spill registers. If this macro returns nonzero for those classes, those
7702 pseudos will only be allocated by `global.c', which knows how to reallocate
7703 the pseudo to another register. If there would not be another register
7704 available for reallocation, you should not change the definition of this
7705 macro since the only effect of such a definition would be to slow down
7706 register allocation. */
7709 frv_class_likely_spilled_p (class)
7710 enum reg_class class;
7737 /* An expression for the alignment of a structure field FIELD if the
7738 alignment computed in the usual way is COMPUTED. GNU CC uses this
7739 value instead of the value in `BIGGEST_ALIGNMENT' or
7740 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7742 /* The definition type of the bit field data is either char, short, long or
7743 long long. The maximum bit size is the number of bits of its own type.
7745 The bit field data is assigned to a storage unit that has an adequate size
7746 for bit field data retention and is located at the smallest address.
7748 Consecutive bit field data are packed at consecutive bits having the same
7749 storage unit, with regard to the type, beginning with the MSB and continuing
7752 If a field to be assigned lies over a bit field type boundary, its
7753 assignment is completed by aligning it with a boundary suitable for the
7756 When a bit field having a bit length of 0 is declared, it is forcibly
7757 assigned to the next storage unit.
7770 &x 00000000 00000000 00000000 00000000
7773 &x+4 00000000 00000000 00000000 00000000
7776 &x+8 00000000 00000000 00000000 00000000
7779 &x+12 00000000 00000000 00000000 00000000
7785 frv_adjust_field_align (field, computed)
7789 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7791 if (DECL_BIT_FIELD (field) && DECL_CONTEXT (field))
7793 tree parent = DECL_CONTEXT (field);
7794 tree prev = NULL_TREE;
7797 /* Loop finding the previous field to the current one */
7798 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7800 if (TREE_CODE (cur) != FIELD_DECL)
7809 /* If this isn't a :0 field and if the previous element is a bitfield
7810 also, see if the type is different, if so, we will need to align the
7811 bit-field to the next boundary */
7813 && ! DECL_PACKED (field)
7814 && ! integer_zerop (DECL_SIZE (field))
7815 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7817 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7818 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7819 computed = (prev_align > cur_align) ? prev_align : cur_align;
7827 /* A C expression that is nonzero if it is permissible to store a value of mode
7828 MODE in hard register number REGNO (or in several registers starting with
7829 that one). For a machine where all registers are equivalent, a suitable
7832 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7834 It is not necessary for this macro to check for the numbers of fixed
7835 registers, because the allocation mechanism considers them to be always
7838 On some machines, double-precision values must be kept in even/odd register
7839 pairs. The way to implement that is to define this macro to reject odd
7840 register numbers for such modes.
7842 The minimum requirement for a mode to be OK in a register is that the
7843 `movMODE' instruction pattern support moves between the register and any
7844 other hard register for which the mode is OK; and that moving a value into
7845 the register and back out not alter it.
7847 Since the same instruction used to move `SImode' will work for all narrower
7848 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7849 to distinguish between these modes, provided you define patterns `movhi',
7850 etc., to take advantage of this. This is useful because of the interaction
7851 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7852 all integer modes to be tieable.
7854 Many machines have special registers for floating point arithmetic. Often
7855 people assume that floating point machine modes are allowed only in floating
7856 point registers. This is not true. Any registers that can hold integers
7857 can safely *hold* a floating point machine mode, whether or not floating
7858 arithmetic can be done on it in those registers. Integer move instructions
7859 can be used to move the values.
7861 On some machines, though, the converse is true: fixed-point machine modes
7862 may not go in floating registers. This is true if the floating registers
7863 normalize any value stored in them, because storing a non-floating value
7864 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7865 fixed-point machine modes in floating registers. But if the floating
7866 registers do not automatically normalize, if you can store any bit pattern
7867 in one and retrieve it unchanged without a trap, then any machine mode may
7868 go in a floating register, so you can define this macro to say so.
7870 The primary significance of special floating registers is rather that they
7871 are the registers acceptable in floating point arithmetic instructions.
7872 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7873 writing the proper constraints for those instructions.
7875 On some machines, the floating registers are especially slow to access, so
7876 that it is better to store a value in a stack frame than in such a register
7877 if floating point arithmetic is not being done. As long as the floating
7878 registers are not in class `GENERAL_REGS', they will not be used unless some
7879 pattern's constraint asks for one. */
7882 frv_hard_regno_mode_ok (regno, mode)
7884 enum machine_mode mode;
7893 return ICC_P (regno) || GPR_P (regno);
7896 return CR_P (regno) || GPR_P (regno);
7899 return FCC_P (regno) || GPR_P (regno);
7905 /* Set BASE to the first register in REGNO's class. Set MASK to the
7906 bits that must be clear in (REGNO - BASE) for the register to be
7908 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7912 /* ACCGs store one byte. Two-byte quantities must start in
7913 even-numbered registers, four-byte ones in registers whose
7914 numbers are divisible by four, and so on. */
7916 mask = GET_MODE_SIZE (mode) - 1;
7920 /* The other registers store one word. */
7924 else if (FPR_P (regno))
7927 else if (ACC_P (regno))
7933 /* Anything smaller than an SI is OK in any word-sized register. */
7934 if (GET_MODE_SIZE (mode) < 4)
7937 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7939 return (((regno - base) & mask) == 0);
7946 /* A C expression for the number of consecutive hard registers, starting at
7947 register number REGNO, required to hold a value of mode MODE.
7949 On a machine where all registers are exactly one word, a suitable definition
7952 #define HARD_REGNO_NREGS(REGNO, MODE) \
7953 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7954 / UNITS_PER_WORD)) */
7956 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7957 that we can build the appropriate instructions to properly reload the
7958 values. Also, make the byte-sized accumulator guards use one guard
7962 frv_hard_regno_nregs (regno, mode)
7964 enum machine_mode mode;
7967 return GET_MODE_SIZE (mode);
7969 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7973 /* A C expression for the maximum number of consecutive registers of
7974 class CLASS needed to hold a value of mode MODE.
7976 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7977 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7978 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7980 This macro helps control the handling of multiple-word values in
7983 This declaration is required. */
7986 frv_class_max_nregs (class, mode)
7987 enum reg_class class;
7988 enum machine_mode mode;
7990 if (class == ACCG_REGS)
7991 /* An N-byte value requires N accumulator guards. */
7992 return GET_MODE_SIZE (mode);
7994 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7998 /* A C expression that is nonzero if X is a legitimate constant for an
7999 immediate operand on the target machine. You can assume that X satisfies
8000 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8001 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8004 frv_legitimate_constant_p (x)
8007 enum machine_mode mode = GET_MODE (x);
8009 /* All of the integer constants are ok */
8010 if (GET_CODE (x) != CONST_DOUBLE)
8013 /* double integer constants are ok */
8014 if (mode == VOIDmode || mode == DImode)
8017 /* 0 is always ok */
8018 if (x == CONST0_RTX (mode))
8021 /* If floating point is just emulated, allow any constant, since it will be
8022 constructed in the GPRs */
8023 if (!TARGET_HAS_FPRS)
8026 if (mode == DFmode && !TARGET_DOUBLE)
8029 /* Otherwise store the constant away and do a load. */
8033 /* A C expression for the cost of moving data from a register in class FROM to
8034 one in class TO. The classes are expressed using the enumeration values
8035 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8036 interpreted relative to that.
8038 It is not required that the cost always equal 2 when FROM is the same as TO;
8039 on some machines it is expensive to move between registers if they are not
8042 If reload sees an insn consisting of a single `set' between two hard
8043 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8044 value of 2, reload does not check to ensure that the constraints of the insn
8045 are met. Setting a cost of other than 2 will allow reload to verify that
8046 the constraints are met. You should do this if the `movM' pattern's
8047 constraints do not allow such copying. */
8049 #define HIGH_COST 40
8050 #define MEDIUM_COST 3
8054 frv_register_move_cost (from, to)
8055 enum reg_class from;
8140 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8141 use ".picptr" to generate safe relocations for PIC code. We also
8142 need a fixup entry for aligned (non-debugging) code. */
8145 frv_assemble_integer (value, size, aligned_p)
8150 if (flag_pic && size == UNITS_PER_WORD)
8152 if (GET_CODE (value) == CONST
8153 || GET_CODE (value) == SYMBOL_REF
8154 || GET_CODE (value) == LABEL_REF)
8158 static int label_num = 0;
8162 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8163 p = (* targetm.strip_name_encoding) (buf);
8165 fprintf (asm_out_file, "%s:\n", p);
8166 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8167 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8168 fprintf (asm_out_file, "\t.previous\n");
8170 assemble_integer_with_op ("\t.picptr\t", value);
8175 /* We've set the unaligned SI op to NULL, so we always have to
8176 handle the unaligned case here. */
8177 assemble_integer_with_op ("\t.4byte\t", value);
8181 return default_assemble_integer (value, size, aligned_p);
8184 /* Function to set up the backend function structure. */
8186 static struct machine_function *
8187 frv_init_machine_status ()
8189 return ggc_alloc_cleared (sizeof (struct machine_function));
8193 /* Update the register state information, to know about which registers are set
8197 frv_registers_update (x, reg_state, modified, p_num_mod, flag)
8199 unsigned char reg_state[];
8211 switch (GET_CODE (x))
8216 /* Clobber just modifies a register, it doesn't make it live. */
8218 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8219 flag | REGSTATE_MODIFIED);
8222 /* Pre modify updates the first argument, just references the second. */
8225 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8226 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8227 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8230 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8231 statement, but just to be sure, make sure it is the type of cond_exec
8235 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8236 && GET_CODE (XEXP (cond, 0)) == REG
8237 && CR_P (REGNO (XEXP (cond, 0)))
8238 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8239 && INTVAL (XEXP (cond, 1)) == 0
8240 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8242 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8243 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8244 | ((GET_CODE (cond) == NE)
8246 : REGSTATE_IF_FALSE));
8248 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8253 fatal_insn ("frv_registers_update", x);
8255 /* MEM resets the modification bits. */
8257 flag &= ~REGSTATE_MODIFIED;
8260 /* See if we need to set the modified flag. */
8262 reg = SUBREG_REG (x);
8263 if (GET_CODE (reg) == REG)
8265 regno = subreg_regno (x);
8266 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8273 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8277 if (flag & REGSTATE_MODIFIED)
8279 flag &= REGSTATE_MASK;
8280 while (regno < reg_max)
8282 int rs = reg_state[regno];
8286 if ((rs & REGSTATE_MODIFIED) == 0)
8288 modified[ *p_num_mod ] = regno;
8292 /* If the previous register state had the register as
8293 modified, possibly in some conditional execution context,
8294 and the current insn modifies in some other context, or
8295 outside of conditional execution, just mark the variable
8298 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8300 reg_state[regno] = (rs | flag);
8309 length = GET_RTX_LENGTH (GET_CODE (x));
8310 format = GET_RTX_FORMAT (GET_CODE (x));
8312 for (j = 0; j < length; ++j)
8317 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8323 if (XVEC (x, j) != 0)
8326 for (k = 0; k < XVECLEN (x, j); ++k)
8327 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8333 /* Nothing to do. */
8342 /* Return if any registers in a hard register set were used an insn. */
8345 frv_registers_used_p (x, reg_state, flag)
8347 unsigned char reg_state[];
8359 switch (GET_CODE (x))
8364 /* Skip clobber, that doesn't use the previous value */
8368 /* For SET, if a conditional jump has occurred in the same insn, only
8369 allow a set of a CR register if that register is not currently live.
8370 This is because on the FR-V, B0/B1 instructions are always last.
8371 Otherwise, don't look at the result, except within a MEM, but do look
8374 dest = SET_DEST (x);
8375 if (flag & REGSTATE_CONDJUMP
8376 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8377 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8380 if (GET_CODE (dest) == MEM)
8382 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8387 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8389 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8390 statement, but just to be sure, make sure it is the type of cond_exec
8394 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8395 && GET_CODE (XEXP (cond, 0)) == REG
8396 && CR_P (REGNO (XEXP (cond, 0)))
8397 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8398 && INTVAL (XEXP (cond, 1)) == 0
8399 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8401 result = frv_registers_used_p (cond, reg_state, flag);
8405 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8406 | ((GET_CODE (cond) == NE)
8408 : REGSTATE_IF_FALSE));
8410 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8413 fatal_insn ("frv_registers_used_p", x);
8415 /* See if a register or subreg was modified in the same VLIW insn. */
8417 reg = SUBREG_REG (x);
8418 if (GET_CODE (reg) == REG)
8420 regno = subreg_regno (x);
8421 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8428 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8432 while (regno < reg_max)
8434 int rs = reg_state[regno];
8436 if (rs & REGSTATE_MODIFIED)
8438 int rs_if = rs & REGSTATE_IF_EITHER;
8439 int flag_if = flag & REGSTATE_IF_EITHER;
8441 /* Simple modification, no conditional execution */
8442 if ((rs & REGSTATE_IF_EITHER) == 0)
8445 /* See if the variable is only modified in a conditional
8446 execution expression opposite to the conditional execution
8447 expression that governs this expression (ie, true vs. false
8448 for the same CC register). If this isn't two halves of the
8449 same conditional expression, consider the register
8451 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8452 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8453 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8465 length = GET_RTX_LENGTH (GET_CODE (x));
8466 format = GET_RTX_FORMAT (GET_CODE (x));
8468 for (j = 0; j < length; ++j)
8473 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8480 if (XVEC (x, j) != 0)
8483 for (k = 0; k < XVECLEN (x, j); ++k)
8485 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8494 /* Nothing to do. */
8502 /* Return if any registers in a hard register set were set in an insn. */
8505 frv_registers_set_p (x, reg_state, modify_p)
8507 unsigned char reg_state[];
8517 switch (GET_CODE (x))
8523 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8527 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8528 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8532 /* just to be sure, make sure it is the type of cond_exec we
8534 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8535 && GET_CODE (XEXP (cond, 0)) == REG
8536 && CR_P (REGNO (XEXP (cond, 0)))
8537 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8538 && INTVAL (XEXP (cond, 1)) == 0
8540 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8542 fatal_insn ("frv_registers_set_p", x);
8544 /* MEM resets the modification bits. */
8549 /* See if we need to set the modified modify_p. */
8551 reg = SUBREG_REG (x);
8552 if (GET_CODE (reg) == REG)
8554 regno = subreg_regno (x);
8555 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8562 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8567 while (regno < reg_max)
8569 int rs = reg_state[regno];
8571 if (rs & REGSTATE_MODIFIED)
8579 length = GET_RTX_LENGTH (GET_CODE (x));
8580 format = GET_RTX_FORMAT (GET_CODE (x));
8582 for (j = 0; j < length; ++j)
8587 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8593 if (XVEC (x, j) != 0)
8596 for (k = 0; k < XVECLEN (x, j); ++k)
8597 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8604 /* Nothing to do. */
8613 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8614 conditional branches/calls/jumps, etc. with previous insns where it can. It
8615 does not reorder the instructions. We assume the scheduler left the flow
8616 information in a reasonable state. */
8621 state_t frv_state; /* frv state machine */
8622 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8623 int next_start_vliw_p; /* next insn starts a VLIW insn */
8624 int cur_condjump_p; /* flag if current insn is a cond jump*/
8625 int next_condjump_p; /* flag if next insn is a cond jump */
8629 int num_mod = 0; /* # of modified registers */
8630 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8631 /* register state information */
8632 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8634 /* If we weren't going to pack the insns, don't bother with this pass. */
8635 if (!optimize || !flag_schedule_insns_after_reload || TARGET_NO_VLIW_BRANCH)
8638 switch (frv_cpu_type)
8641 case FRV_CPU_FR300: /* FR300/simple are single issue */
8642 case FRV_CPU_SIMPLE:
8645 case FRV_CPU_GENERIC: /* FR-V and FR500 are multi-issue */
8648 case FRV_CPU_TOMCAT:
8652 /* Set up the instruction and register states. */
8654 frv_state = (state_t) xmalloc (state_size ());
8655 memset ((PTR) reg_state, REGSTATE_DEAD, sizeof (reg_state));
8657 /* Go through the insns, and repack the insns. */
8658 state_reset (frv_state);
8659 cur_start_vliw_p = FALSE;
8660 next_start_vliw_p = TRUE;
8662 next_condjump_p = 0;
8664 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8666 enum rtx_code code = GET_CODE (insn);
8667 enum rtx_code pattern_code;
8669 /* For basic block begin notes redo the live information, and skip other
8673 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8677 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8678 reg_state[j] &= ~ REGSTATE_LIVE;
8680 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8681 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8683 reg_state[j] |= REGSTATE_LIVE;
8690 /* things like labels reset everything. */
8691 if (GET_RTX_CLASS (code) != 'i')
8693 next_start_vliw_p = TRUE;
8697 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8698 set on the USE insn that preceeds the return, and potentially on
8699 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8700 holding the case table labels. */
8701 pattern_code = GET_CODE (PATTERN (insn));
8702 if (pattern_code == USE || pattern_code == CLOBBER
8703 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8705 CLEAR_VLIW_START (insn);
8709 cur_start_vliw_p = next_start_vliw_p;
8710 next_start_vliw_p = FALSE;
8712 cur_condjump_p |= next_condjump_p;
8713 next_condjump_p = 0;
8715 /* Unconditional branches and calls end the current VLIW insn. */
8716 if (code == CALL_INSN)
8718 next_start_vliw_p = TRUE;
8720 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8721 if (frv_cpu_type == FRV_CPU_TOMCAT)
8722 cur_start_vliw_p = TRUE;
8724 else if (code == JUMP_INSN)
8726 if (any_condjump_p (insn))
8727 next_condjump_p = REGSTATE_CONDJUMP;
8729 next_start_vliw_p = TRUE;
8732 /* Only allow setting a CCR register after a conditional branch. */
8733 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8734 && get_attr_type (insn) != TYPE_CCR)
8735 cur_start_vliw_p = TRUE;
8737 /* Determine if we need to start a new VLIW instruction. */
8738 if (cur_start_vliw_p
8739 /* Do not check for register conflicts in a setlo instruction
8740 because any output or true dependencies will be with the
8741 partnering sethi instruction, with which it can be packed.
8743 Although output dependencies are rare they are still
8744 possible. So check output dependencies in VLIW insn. */
8745 || (get_attr_type (insn) != TYPE_SETLO
8746 && (frv_registers_used_p (PATTERN (insn),
8749 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8750 || state_transition (frv_state, insn) >= 0)
8752 SET_VLIW_START (insn);
8753 state_reset (frv_state);
8754 state_transition (frv_state, insn);
8757 /* Update the modified registers. */
8758 for (j = 0; j < num_mod; j++)
8759 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8760 | REGSTATE_IF_EITHER
8761 | REGSTATE_MODIFIED);
8766 CLEAR_VLIW_START (insn);
8768 /* Record which registers are modified. */
8769 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8771 /* Process the death notices */
8772 for (link = REG_NOTES (insn);
8774 link = XEXP (link, 1))
8776 rtx reg = XEXP (link, 0);
8778 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8780 int regno = REGNO (reg);
8781 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8782 for (; regno < n; regno++)
8783 reg_state[regno] &= ~REGSTATE_LIVE;
8788 free ((PTR) frv_state);
8794 #define def_builtin(name, type, code) \
8795 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8797 struct builtin_description
8799 enum insn_code icode;
8801 enum frv_builtins code;
8802 enum rtx_code comparison;
8806 /* Media intrinsics that take a single, constant argument. */
8808 static struct builtin_description bdesc_set[] =
8810 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8813 /* Media intrinsics that take just one argument. */
8815 static struct builtin_description bdesc_1arg[] =
8817 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8818 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8819 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8820 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8821 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8824 /* Media intrinsics that take two arguments. */
8826 static struct builtin_description bdesc_2arg[] =
8828 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8829 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8830 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8831 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8832 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8833 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8834 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8835 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8836 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8837 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8838 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8839 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8840 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8841 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8842 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8843 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8844 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8845 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8846 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8847 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8850 /* Media intrinsics that take two arguments, the first being an ACC number. */
8852 static struct builtin_description bdesc_cut[] =
8854 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8855 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8856 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8859 /* Two-argument media intrinsics with an immediate second argument. */
8861 static struct builtin_description bdesc_2argimm[] =
8863 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8864 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8865 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8866 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8867 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8868 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8869 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8870 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8871 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8872 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8873 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8874 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8875 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8876 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8877 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8880 /* Media intrinsics that take two arguments and return void, the first argument
8881 being a pointer to 4 words in memory. */
8883 static struct builtin_description bdesc_void2arg[] =
8885 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8886 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8889 /* Media intrinsics that take three arguments, the first being a const_int that
8890 denotes an accumulator, and that return void. */
8892 static struct builtin_description bdesc_void3arg[] =
8894 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8895 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8896 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8897 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8898 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8899 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8900 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8901 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8902 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8903 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8904 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8905 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8906 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8907 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8908 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8909 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8910 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8911 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8912 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8913 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8914 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8915 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8916 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8917 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8918 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8921 /* Media intrinsics that take two accumulator numbers as argument and
8924 static struct builtin_description bdesc_voidacc[] =
8926 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8927 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8928 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8929 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8930 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8931 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8934 /* Initialize media builtins. */
8937 frv_init_builtins ()
8939 tree endlink = void_list_node;
8940 tree accumulator = integer_type_node;
8941 tree integer = integer_type_node;
8942 tree voidt = void_type_node;
8943 tree uhalf = short_unsigned_type_node;
8944 tree sword1 = long_integer_type_node;
8945 tree uword1 = long_unsigned_type_node;
8946 tree sword2 = long_long_integer_type_node;
8947 tree uword2 = long_long_unsigned_type_node;
8948 tree uword4 = build_pointer_type (uword1);
8950 #define UNARY(RET, T1) \
8951 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8953 #define BINARY(RET, T1, T2) \
8954 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8955 tree_cons (NULL_TREE, T2, endlink)))
8957 #define TRINARY(RET, T1, T2, T3) \
8958 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8959 tree_cons (NULL_TREE, T2, \
8960 tree_cons (NULL_TREE, T3, endlink))))
8962 tree void_ftype_void = build_function_type (voidt, endlink);
8964 tree void_ftype_acc = UNARY (voidt, accumulator);
8965 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8966 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8967 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8968 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8969 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8970 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8971 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8972 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8974 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8975 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8976 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8977 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8978 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8979 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8980 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8981 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8982 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8983 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8984 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8986 tree sw1_ftype_int = UNARY (sword1, integer);
8987 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8988 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8990 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8991 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8992 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8993 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8994 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8996 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8998 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8999 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9000 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9001 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9002 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9003 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9004 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9005 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9006 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9007 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9008 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9009 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9010 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9011 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9012 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9013 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9014 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9015 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9016 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9017 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9018 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9019 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9020 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9021 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9022 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9023 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9024 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9025 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9026 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9027 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9028 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9029 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9030 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9031 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9032 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9033 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9034 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9035 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9036 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9037 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9038 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9039 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9040 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9041 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9042 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9043 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9044 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9045 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9046 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9047 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9048 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9049 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9050 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9051 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9052 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9053 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9054 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9055 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9056 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9057 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9058 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9059 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9060 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9061 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9062 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9063 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9064 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9065 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9066 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9067 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9068 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9069 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9070 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9071 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9072 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9073 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9074 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9075 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9076 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9077 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9078 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9079 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9080 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9081 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9088 /* Convert an integer constant to an accumulator register. ICODE is the
9089 code of the target instruction, OPNUM is the number of the
9090 accumulator operand and OPVAL is the constant integer. Try both
9091 ACC and ACCG registers; only report an error if neither fit the
9095 frv_int_to_acc (icode, opnum, opval)
9096 enum insn_code icode;
9102 if (GET_CODE (opval) != CONST_INT)
9104 error ("accumulator is not a constant integer");
9107 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9109 error ("accumulator number is out of bounds");
9113 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9114 ACC_FIRST + INTVAL (opval));
9115 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9116 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9118 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9120 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9126 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9129 static enum machine_mode
9130 frv_matching_accg_mode (mode)
9131 enum machine_mode mode;
9149 /* Return the accumulator guard that should be paired with accumulator
9150 register ACC. The mode of the returned register is in the same
9151 class as ACC, but is four times smaller. */
9154 frv_matching_accg_for_acc (acc)
9157 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9158 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9161 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9162 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9166 frv_read_argument (arglistptr)
9169 tree next = TREE_VALUE (*arglistptr);
9170 *arglistptr = TREE_CHAIN (*arglistptr);
9171 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9174 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9175 The instruction should require a constant operand of some sort. The
9176 function prints an error if OPVAL is not valid. */
9179 frv_check_constant_argument (icode, opnum, opval)
9180 enum insn_code icode;
9184 if (GET_CODE (opval) != CONST_INT)
9186 error ("`%s' expects a constant argument", insn_data[icode].name);
9189 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9191 error ("constant argument out of range for `%s'", insn_data[icode].name);
9197 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9198 if it's not null, has the right mode, and satisfies operand 0's
9202 frv_legitimize_target (icode, target)
9203 enum insn_code icode;
9206 enum machine_mode mode = insn_data[icode].operand[0].mode;
9209 || GET_MODE (target) != mode
9210 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9211 return gen_reg_rtx (mode);
9216 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9217 check whether ARG satisfies the operand's contraints. If it doesn't,
9218 copy ARG to a temporary register and return that. Otherwise return ARG
9222 frv_legitimize_argument (icode, opnum, arg)
9223 enum insn_code icode;
9227 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9229 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9232 return copy_to_mode_reg (mode, arg);
9235 /* Expand builtins that take a single, constant argument. At the moment,
9236 only MHDSETS falls into this category. */
9239 frv_expand_set_builtin (icode, arglist, target)
9240 enum insn_code icode;
9245 rtx op0 = frv_read_argument (&arglist);
9247 if (! frv_check_constant_argument (icode, 1, op0))
9250 target = frv_legitimize_target (icode, target);
9251 pat = GEN_FCN (icode) (target, op0);
9259 /* Expand builtins that take one operand. */
9262 frv_expand_unop_builtin (icode, arglist, target)
9263 enum insn_code icode;
9268 rtx op0 = frv_read_argument (&arglist);
9270 target = frv_legitimize_target (icode, target);
9271 op0 = frv_legitimize_argument (icode, 1, op0);
9272 pat = GEN_FCN (icode) (target, op0);
9280 /* Expand builtins that take two operands. */
9283 frv_expand_binop_builtin (icode, arglist, target)
9284 enum insn_code icode;
9289 rtx op0 = frv_read_argument (&arglist);
9290 rtx op1 = frv_read_argument (&arglist);
9292 target = frv_legitimize_target (icode, target);
9293 op0 = frv_legitimize_argument (icode, 1, op0);
9294 op1 = frv_legitimize_argument (icode, 2, op1);
9295 pat = GEN_FCN (icode) (target, op0, op1);
9303 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9307 frv_expand_cut_builtin (icode, arglist, target)
9308 enum insn_code icode;
9313 rtx op0 = frv_read_argument (&arglist);
9314 rtx op1 = frv_read_argument (&arglist);
9317 target = frv_legitimize_target (icode, target);
9318 op0 = frv_int_to_acc (icode, 1, op0);
9322 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9324 if (! frv_check_constant_argument (icode, 2, op1))
9328 op1 = frv_legitimize_argument (icode, 2, op1);
9330 op2 = frv_matching_accg_for_acc (op0);
9331 pat = GEN_FCN (icode) (target, op0, op1, op2);
9339 /* Expand builtins that take two operands and the second is immediate. */
9342 frv_expand_binopimm_builtin (icode, arglist, target)
9343 enum insn_code icode;
9348 rtx op0 = frv_read_argument (&arglist);
9349 rtx op1 = frv_read_argument (&arglist);
9351 if (! frv_check_constant_argument (icode, 2, op1))
9354 target = frv_legitimize_target (icode, target);
9355 op0 = frv_legitimize_argument (icode, 1, op0);
9356 pat = GEN_FCN (icode) (target, op0, op1);
9364 /* Expand builtins that take two operands, the first operand being a pointer to
9365 ints and return void. */
9368 frv_expand_voidbinop_builtin (icode, arglist)
9369 enum insn_code icode;
9373 rtx op0 = frv_read_argument (&arglist);
9374 rtx op1 = frv_read_argument (&arglist);
9375 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9378 if (GET_CODE (op0) != MEM)
9382 if (! offsettable_address_p (0, mode0, op0))
9384 reg = gen_reg_rtx (Pmode);
9385 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9388 op0 = gen_rtx_MEM (SImode, reg);
9391 addr = XEXP (op0, 0);
9392 if (! offsettable_address_p (0, mode0, addr))
9393 addr = copy_to_mode_reg (Pmode, op0);
9395 op0 = change_address (op0, V4SImode, addr);
9396 op1 = frv_legitimize_argument (icode, 1, op1);
9397 pat = GEN_FCN (icode) (op0, op1);
9405 /* Expand builtins that take three operands and return void. The first
9406 argument must be a constant that describes a pair or quad accumulators. A
9407 fourth argument is created that is the accumulator guard register that
9408 corresponds to the accumulator. */
9411 frv_expand_voidtriop_builtin (icode, arglist)
9412 enum insn_code icode;
9416 rtx op0 = frv_read_argument (&arglist);
9417 rtx op1 = frv_read_argument (&arglist);
9418 rtx op2 = frv_read_argument (&arglist);
9421 op0 = frv_int_to_acc (icode, 0, op0);
9425 op1 = frv_legitimize_argument (icode, 1, op1);
9426 op2 = frv_legitimize_argument (icode, 2, op2);
9427 op3 = frv_matching_accg_for_acc (op0);
9428 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9436 /* Expand builtins that perform accumulator-to-accumulator operations.
9437 These builtins take two accumulator numbers as argument and return
9441 frv_expand_voidaccop_builtin (icode, arglist)
9442 enum insn_code icode;
9446 rtx op0 = frv_read_argument (&arglist);
9447 rtx op1 = frv_read_argument (&arglist);
9451 op0 = frv_int_to_acc (icode, 0, op0);
9455 op1 = frv_int_to_acc (icode, 1, op1);
9459 op2 = frv_matching_accg_for_acc (op0);
9460 op3 = frv_matching_accg_for_acc (op1);
9461 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9469 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9470 number as argument. */
9473 frv_expand_mclracc_builtin (arglist)
9476 enum insn_code icode = CODE_FOR_mclracc;
9478 rtx op0 = frv_read_argument (&arglist);
9480 op0 = frv_int_to_acc (icode, 0, op0);
9484 pat = GEN_FCN (icode) (op0);
9491 /* Expand builtins that take no arguments. */
9494 frv_expand_noargs_builtin (icode)
9495 enum insn_code icode;
9497 rtx pat = GEN_FCN (icode) (GEN_INT (0));
9504 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9505 number or accumulator guard number as argument and return an SI integer. */
9508 frv_expand_mrdacc_builtin (icode, arglist)
9509 enum insn_code icode;
9513 rtx target = gen_reg_rtx (SImode);
9514 rtx op0 = frv_read_argument (&arglist);
9516 op0 = frv_int_to_acc (icode, 1, op0);
9520 pat = GEN_FCN (icode) (target, op0);
9528 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9529 accumulator guard as their first argument and an SImode value as their
9533 frv_expand_mwtacc_builtin (icode, arglist)
9534 enum insn_code icode;
9538 rtx op0 = frv_read_argument (&arglist);
9539 rtx op1 = frv_read_argument (&arglist);
9541 op0 = frv_int_to_acc (icode, 0, op0);
9545 op1 = frv_legitimize_argument (icode, 1, op1);
9546 pat = GEN_FCN (icode) (op0, op1);
9553 /* Expand builtins. */
9556 frv_expand_builtin (exp, target, subtarget, mode, ignore)
9559 rtx subtarget ATTRIBUTE_UNUSED;
9560 enum machine_mode mode ATTRIBUTE_UNUSED;
9561 int ignore ATTRIBUTE_UNUSED;
9563 tree arglist = TREE_OPERAND (exp, 1);
9564 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9565 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9567 struct builtin_description *d;
9571 error ("media functions are not available unless -mmedia is used");
9577 case FRV_BUILTIN_MCOP1:
9578 case FRV_BUILTIN_MCOP2:
9579 case FRV_BUILTIN_MDUNPACKH:
9580 case FRV_BUILTIN_MBTOHE:
9581 if (! TARGET_MEDIA_REV1)
9583 error ("this media function is only available on the fr500");
9588 case FRV_BUILTIN_MQXMACHS:
9589 case FRV_BUILTIN_MQXMACXHS:
9590 case FRV_BUILTIN_MQMACXHS:
9591 case FRV_BUILTIN_MADDACCS:
9592 case FRV_BUILTIN_MSUBACCS:
9593 case FRV_BUILTIN_MASACCS:
9594 case FRV_BUILTIN_MDADDACCS:
9595 case FRV_BUILTIN_MDSUBACCS:
9596 case FRV_BUILTIN_MDASACCS:
9597 case FRV_BUILTIN_MABSHS:
9598 case FRV_BUILTIN_MDROTLI:
9599 case FRV_BUILTIN_MCPLHI:
9600 case FRV_BUILTIN_MCPLI:
9601 case FRV_BUILTIN_MDCUTSSI:
9602 case FRV_BUILTIN_MQSATHS:
9603 case FRV_BUILTIN_MHSETLOS:
9604 case FRV_BUILTIN_MHSETLOH:
9605 case FRV_BUILTIN_MHSETHIS:
9606 case FRV_BUILTIN_MHSETHIH:
9607 case FRV_BUILTIN_MHDSETS:
9608 case FRV_BUILTIN_MHDSETH:
9609 if (! TARGET_MEDIA_REV2)
9611 error ("this media function is only available on the fr400");
9620 /* Expand unique builtins. */
9624 case FRV_BUILTIN_MTRAP:
9625 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9627 case FRV_BUILTIN_MCLRACC:
9628 return frv_expand_mclracc_builtin (arglist);
9630 case FRV_BUILTIN_MCLRACCA:
9632 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9634 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9636 case FRV_BUILTIN_MRDACC:
9637 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9639 case FRV_BUILTIN_MRDACCG:
9640 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9642 case FRV_BUILTIN_MWTACC:
9643 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9645 case FRV_BUILTIN_MWTACCG:
9646 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9652 /* Expand groups of builtins. */
9654 for (i = 0, d = bdesc_set; i < sizeof (bdesc_set) / sizeof *d; i++, d++)
9655 if (d->code == fcode)
9656 return frv_expand_set_builtin (d->icode, arglist, target);
9658 for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++)
9659 if (d->code == fcode)
9660 return frv_expand_unop_builtin (d->icode, arglist, target);
9662 for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
9663 if (d->code == fcode)
9664 return frv_expand_binop_builtin (d->icode, arglist, target);
9666 for (i = 0, d = bdesc_cut; i < sizeof (bdesc_cut) / sizeof *d; i++, d++)
9667 if (d->code == fcode)
9668 return frv_expand_cut_builtin (d->icode, arglist, target);
9670 for (i = 0, d = bdesc_2argimm;
9671 i < sizeof (bdesc_2argimm) / sizeof *d;
9674 if (d->code == fcode)
9675 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9678 for (i = 0, d = bdesc_void2arg;
9679 i < sizeof (bdesc_void2arg) / sizeof *d;
9682 if (d->code == fcode)
9683 return frv_expand_voidbinop_builtin (d->icode, arglist);
9686 for (i = 0, d = bdesc_void3arg;
9687 i < sizeof (bdesc_void3arg) / sizeof *d;
9690 if (d->code == fcode)
9691 return frv_expand_voidtriop_builtin (d->icode, arglist);
9694 for (i = 0, d = bdesc_voidacc;
9695 i < sizeof (bdesc_voidacc) / sizeof *d;
9698 if (d->code == fcode)
9699 return frv_expand_voidaccop_builtin (d->icode, arglist);
9705 frv_in_small_data_p (decl)
9711 /* Don't apply the -G flag to internal compiler structures. We
9712 should leave such structures in the main data section, partly
9713 for efficiency and partly because the size of some of them
9714 (such as C++ typeinfos) is not known until later. */
9715 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9718 size = int_size_in_bytes (TREE_TYPE (decl));
9719 if (size > 0 && size <= g_switch_value)
9722 /* If we already know which section the decl should be in, see if
9723 it's a small data section. */
9724 section_name = DECL_SECTION_NAME (decl);
9727 if (TREE_CODE (section_name) != STRING_CST)
9729 if (frv_string_begins_with (section_name, ".sdata"))
9731 if (frv_string_begins_with (section_name, ".sbss"))
9739 frv_rtx_costs (x, code, outer_code, total)
9741 int code, outer_code ATTRIBUTE_UNUSED;
9747 /* Make 12 bit integers really cheap. */
9748 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9759 *total = COSTS_N_INSNS (2);
9773 if (GET_MODE (x) == SImode)
9774 *total = COSTS_N_INSNS (1);
9775 else if (GET_MODE (x) == DImode)
9776 *total = COSTS_N_INSNS (2);
9778 *total = COSTS_N_INSNS (3);
9782 if (GET_MODE (x) == SImode)
9783 *total = COSTS_N_INSNS (2);
9785 *total = COSTS_N_INSNS (6); /* guess */
9792 *total = COSTS_N_INSNS (18);
9801 frv_asm_out_constructor (symbol, priority)
9803 int priority ATTRIBUTE_UNUSED;
9806 assemble_align (POINTER_SIZE);
9807 assemble_integer_with_op ("\t.picptr\t", symbol);
9811 frv_asm_out_destructor (symbol, priority)
9813 int priority ATTRIBUTE_UNUSED;
9816 assemble_align (POINTER_SIZE);
9817 assemble_integer_with_op ("\t.picptr\t", symbol);