1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Information about a relocation unspec. SYMBOL is the relocation symbol
127 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
128 is the constant addend. */
132 HOST_WIDE_INT offset;
135 /* Temporary register allocation support structure. */
136 typedef struct frv_tmp_reg_struct
138 HARD_REG_SET regs; /* possible registers to allocate */
139 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
143 /* Register state information for VLIW re-packing phase. */
144 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
145 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
146 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
147 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
149 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
151 typedef unsigned char regstate_t;
153 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
161 /* Information required by frv_frame_access. */
164 /* This field is FRV_LOAD if registers are to be loaded from the stack and
165 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
166 the move is being done by the prologue code while FRV_LOAD implies it
167 is being done by the epilogue. */
168 enum frv_stack_op op;
170 /* The base register to use when accessing the stack. This may be the
171 frame pointer, stack pointer, or a temporary. The choice of register
172 depends on which part of the frame is being accessed and how big the
176 /* The offset of BASE from the bottom of the current frame, in bytes. */
178 } frv_frame_accessor_t;
180 /* Define the information needed to generate branch and scc insns. This is
181 stored from the compare operation. */
185 /* Conditional execution support gathered together in one structure. */
188 /* Linked list of insns to add if the conditional execution conversion was
189 successful. Each link points to an EXPR_LIST which points to the pattern
190 of the insn to add, and the insn to be inserted before. */
191 rtx added_insns_list;
193 /* Identify which registers are safe to allocate for if conversions to
194 conditional execution. We keep the last allocated register in the
195 register classes between COND_EXEC statements. This will mean we allocate
196 different registers for each different COND_EXEC group if we can. This
197 might allow the scheduler to intermix two different COND_EXEC sections. */
198 frv_tmp_reg_t tmp_reg;
200 /* For nested IFs, identify which CC registers are used outside of setting
201 via a compare isnsn, and using via a check insn. This will allow us to
202 know if we can rewrite the register to use a different register that will
203 be paired with the CR register controlling the nested IF-THEN blocks. */
204 HARD_REG_SET nested_cc_ok_rewrite;
206 /* Temporary registers allocated to hold constants during conditional
208 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
210 /* Current number of temp registers available. */
211 int cur_scratch_regs;
213 /* Number of nested conditional execution blocks. */
214 int num_nested_cond_exec;
216 /* Map of insns that set up constants in scratch registers. */
217 bitmap scratch_insns_bitmap;
219 /* Conditional execution test register (CC0..CC7). */
222 /* Conditional execution compare register that is paired with cr_reg, so that
223 nested compares can be done. The csubcc and caddcc instructions don't
224 have enough bits to specify both a CC register to be set and a CR register
225 to do the test on, so the same bit number is used for both. Needless to
226 say, this is rather inconvenient for GCC. */
229 /* Extra CR registers used for &&, ||. */
233 /* Previous CR used in nested if, to make sure we are dealing with the same
234 nested if as the previous statement. */
235 rtx last_nested_if_cr;
239 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
241 /* Map register number to smallest register class. */
242 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
244 /* Map class letter into register class. */
245 enum reg_class reg_class_from_letter[256];
247 /* Cached value of frv_stack_info. */
248 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
250 /* -mbranch-cost= support */
251 const char *frv_branch_cost_string;
252 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
255 const char *frv_cpu_string; /* -mcpu= option */
256 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
258 /* -mcond-exec-insns= support */
259 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
260 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
262 /* -mcond-exec-temps= support */
263 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
264 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
266 /* -msched-lookahead=n */
267 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
268 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
270 /* Forward references */
271 static int frv_default_flags_for_cpu (void);
272 static int frv_string_begins_with (tree, const char *);
273 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
274 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
281 static rtx single_set_pattern (rtx);
282 static int frv_function_contains_far_jump (void);
283 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
287 static rtx frv_frame_offset_rtx (int);
288 static rtx frv_frame_mem (enum machine_mode, rtx, int);
289 static rtx frv_dwarf_store (rtx, int);
290 static void frv_frame_insn (rtx, rtx);
291 static void frv_frame_access (frv_frame_accessor_t*,
293 static void frv_frame_access_multi (frv_frame_accessor_t*,
295 static void frv_frame_access_standard_regs (enum frv_stack_op,
297 static struct machine_function *frv_init_machine_status (void);
298 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
299 static rtx frv_int_to_acc (enum insn_code, int, rtx);
300 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
301 static rtx frv_read_argument (tree *);
302 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
303 static int frv_check_constant_argument (enum insn_code, int, rtx);
304 static rtx frv_legitimize_target (enum insn_code, rtx);
305 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
306 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
307 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
313 static rtx frv_expand_int_void2arg (enum insn_code, tree);
314 static rtx frv_expand_prefetches (enum insn_code, tree);
315 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
316 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
317 static rtx frv_expand_mclracc_builtin (tree);
318 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
320 static rtx frv_expand_noargs_builtin (enum insn_code);
321 static void frv_split_iacc_move (rtx, rtx);
322 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
323 static int frv_clear_registers_used (rtx *, void *);
324 static void frv_ifcvt_add_insn (rtx, rtx, int);
325 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
326 static rtx frv_ifcvt_load_value (rtx, rtx);
327 static int frv_acc_group_1 (rtx *, void *);
328 static unsigned int frv_insn_unit (rtx);
329 static bool frv_issues_to_branch_unit_p (rtx);
330 static int frv_cond_flags (rtx);
331 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
332 static int frv_registers_conflict_p_1 (rtx *, void *);
333 static bool frv_registers_conflict_p (rtx);
334 static void frv_registers_update_1 (rtx, rtx, void *);
335 static void frv_registers_update (rtx);
336 static void frv_start_packet (void);
337 static void frv_start_packet_block (void);
338 static void frv_finish_packet (void (*) (void));
339 static bool frv_pack_insn_p (rtx);
340 static void frv_add_insn_to_packet (rtx);
341 static void frv_insert_nop_in_packet (rtx);
342 static bool frv_for_each_packet (void (*) (void));
343 static bool frv_sort_insn_group_1 (enum frv_insn_group,
344 unsigned int, unsigned int,
345 unsigned int, unsigned int,
347 static int frv_compare_insns (const void *, const void *);
348 static void frv_sort_insn_group (enum frv_insn_group);
349 static void frv_reorder_packet (void);
350 static void frv_fill_unused_units (enum frv_insn_group);
351 static void frv_align_label (void);
352 static void frv_reorg_packet (void);
353 static void frv_register_nop (rtx);
354 static void frv_reorg (void);
355 static void frv_pack_insns (void);
356 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
357 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
358 static bool frv_assemble_integer (rtx, unsigned, int);
359 static void frv_init_builtins (void);
360 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
361 static void frv_init_libfuncs (void);
362 static bool frv_in_small_data_p (tree);
363 static void frv_asm_output_mi_thunk
364 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
365 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
368 static rtx frv_expand_builtin_saveregs (void);
369 static bool frv_rtx_costs (rtx, int, int, int*);
370 static void frv_asm_out_constructor (rtx, int);
371 static void frv_asm_out_destructor (rtx, int);
372 static bool frv_function_symbol_referenced_p (rtx);
373 static bool frv_cannot_force_const_mem (rtx);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec *);
377 static bool frv_function_ok_for_sibcall (tree, tree);
378 static rtx frv_struct_value_rtx (tree, int);
379 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
380 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
383 /* Initialize the GCC target structure. */
384 #undef TARGET_ASM_FUNCTION_PROLOGUE
385 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
386 #undef TARGET_ASM_FUNCTION_EPILOGUE
387 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
388 #undef TARGET_ASM_INTEGER
389 #define TARGET_ASM_INTEGER frv_assemble_integer
390 #undef TARGET_INIT_BUILTINS
391 #define TARGET_INIT_BUILTINS frv_init_builtins
392 #undef TARGET_EXPAND_BUILTIN
393 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
394 #undef TARGET_INIT_LIBFUNCS
395 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
396 #undef TARGET_IN_SMALL_DATA_P
397 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
398 #undef TARGET_RTX_COSTS
399 #define TARGET_RTX_COSTS frv_rtx_costs
400 #undef TARGET_ASM_CONSTRUCTOR
401 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
402 #undef TARGET_ASM_DESTRUCTOR
403 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
405 #undef TARGET_ASM_OUTPUT_MI_THUNK
406 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
407 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
408 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
410 #undef TARGET_SCHED_ISSUE_RATE
411 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
413 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
414 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
415 #undef TARGET_CANNOT_FORCE_CONST_MEM
416 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
418 #undef TARGET_HAVE_TLS
419 #define TARGET_HAVE_TLS HAVE_AS_TLS
421 #undef TARGET_STRUCT_VALUE_RTX
422 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
423 #undef TARGET_MUST_PASS_IN_STACK
424 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
425 #undef TARGET_PASS_BY_REFERENCE
426 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
427 #undef TARGET_ARG_PARTIAL_BYTES
428 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
430 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
431 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
432 #undef TARGET_SETUP_INCOMING_VARARGS
433 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
434 #undef TARGET_MACHINE_DEPENDENT_REORG
435 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
437 struct gcc_target targetm = TARGET_INITIALIZER;
439 #define FRV_SYMBOL_REF_TLS_P(RTX) \
440 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
443 /* Any function call that satisfies the machine-independent
444 requirements is eligible on FR-V. */
447 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
448 tree exp ATTRIBUTE_UNUSED)
453 /* Return true if SYMBOL is a small data symbol and relocation RELOC
454 can be used to access it directly in a load or store. */
456 static FRV_INLINE bool
457 frv_small_data_reloc_p (rtx symbol, int reloc)
459 return (GET_CODE (symbol) == SYMBOL_REF
460 && SYMBOL_REF_SMALL_P (symbol)
461 && (!TARGET_FDPIC || flag_pic == 1)
462 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
465 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
468 static FRV_INLINE bool
469 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
471 if (GET_CODE (x) == CONST)
475 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
477 unspec->offset += INTVAL (XEXP (x, 1));
480 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
482 unspec->symbol = XVECEXP (x, 0, 0);
483 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
485 if (unspec->offset == 0)
488 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
489 && unspec->offset > 0
490 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
497 /* Decide whether we can force certain constants to memory. If we
498 decide we can't, the caller should be able to cope with it in
501 We never allow constants to be forced into memory for TARGET_FDPIC.
502 This is necessary for several reasons:
504 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
505 target-independent code will try to force them into the constant
506 pool, thus leading to infinite recursion.
508 2. We can never introduce new constant pool references during reload.
509 Any such reference would require use of the pseudo FDPIC register.
511 3. We can't represent a constant added to a function pointer (which is
512 not the same as a pointer to a function+constant).
514 4. In many cases, it's more efficient to calculate the constant in-line. */
517 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
523 frv_default_flags_for_cpu (void)
525 switch (frv_cpu_type)
527 case FRV_CPU_GENERIC:
528 return MASK_DEFAULT_FRV;
531 return MASK_DEFAULT_FR550;
535 return MASK_DEFAULT_FR500;
538 return MASK_DEFAULT_FR450;
542 return MASK_DEFAULT_FR400;
546 return MASK_DEFAULT_SIMPLE;
551 /* Sometimes certain combinations of command options do not make
552 sense on a particular target machine. You can define a macro
553 `OVERRIDE_OPTIONS' to take account of this. This macro, if
554 defined, is executed once just after all the command options have
557 Don't use this macro to turn on various extra optimizations for
558 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
561 frv_override_options (void)
566 /* Set the cpu type. */
569 if (strcmp (frv_cpu_string, "simple") == 0)
570 frv_cpu_type = FRV_CPU_SIMPLE;
572 else if (strcmp (frv_cpu_string, "tomcat") == 0)
573 frv_cpu_type = FRV_CPU_TOMCAT;
575 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
576 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
580 const char *p = frv_cpu_string + sizeof ("fr") - 1;
581 if (strcmp (p, "550") == 0)
582 frv_cpu_type = FRV_CPU_FR550;
584 else if (strcmp (p, "500") == 0)
585 frv_cpu_type = FRV_CPU_FR500;
587 else if (strcmp (p, "450") == 0)
588 frv_cpu_type = FRV_CPU_FR450;
590 else if (strcmp (p, "405") == 0)
591 frv_cpu_type = FRV_CPU_FR405;
593 else if (strcmp (p, "400") == 0)
594 frv_cpu_type = FRV_CPU_FR400;
596 else if (strcmp (p, "300") == 0)
597 frv_cpu_type = FRV_CPU_FR300;
599 else if (strcmp (p, "v") == 0)
600 frv_cpu_type = FRV_CPU_GENERIC;
603 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
607 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
609 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
610 linker about linking pic and non-pic code. */
613 if (!flag_pic) /* -fPIC */
616 if (! g_switch_set) /* -G0 */
623 /* Change the branch cost value. */
624 if (frv_branch_cost_string)
625 frv_branch_cost_int = atoi (frv_branch_cost_string);
627 /* Change the # of insns to be converted to conditional execution. */
628 if (frv_condexec_insns_str)
629 frv_condexec_insns = atoi (frv_condexec_insns_str);
631 /* Change # of temporary registers used to hold integer constants. */
632 if (frv_condexec_temps_str)
633 frv_condexec_temps = atoi (frv_condexec_temps_str);
635 /* Change scheduling look ahead. */
636 if (frv_sched_lookahead_str)
637 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
639 /* A C expression whose value is a register class containing hard
640 register REGNO. In general there is more than one such class;
641 choose a class which is "minimal", meaning that no smaller class
642 also contains the register. */
644 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
646 enum reg_class class;
650 int gpr_reg = regno - GPR_FIRST;
652 if (gpr_reg == GR8_REG)
655 else if (gpr_reg == GR9_REG)
658 else if (gpr_reg == GR14_REG)
659 class = FDPIC_FPTR_REGS;
661 else if (gpr_reg == FDPIC_REGNO)
664 else if ((gpr_reg & 3) == 0)
667 else if ((gpr_reg & 1) == 0)
674 else if (FPR_P (regno))
676 int fpr_reg = regno - GPR_FIRST;
677 if ((fpr_reg & 3) == 0)
678 class = QUAD_FPR_REGS;
680 else if ((fpr_reg & 1) == 0)
687 else if (regno == LR_REGNO)
690 else if (regno == LCR_REGNO)
693 else if (ICC_P (regno))
696 else if (FCC_P (regno))
699 else if (ICR_P (regno))
702 else if (FCR_P (regno))
705 else if (ACC_P (regno))
707 int r = regno - ACC_FIRST;
709 class = QUAD_ACC_REGS;
710 else if ((r & 1) == 0)
711 class = EVEN_ACC_REGS;
716 else if (ACCG_P (regno))
722 regno_reg_class[regno] = class;
725 /* Check for small data option */
727 g_switch_value = SDATA_DEFAULT_SIZE;
729 /* A C expression which defines the machine-dependent operand
730 constraint letters for register classes. If CHAR is such a
731 letter, the value should be the register class corresponding to
732 it. Otherwise, the value should be `NO_REGS'. The register
733 letter `r', corresponding to class `GENERAL_REGS', will not be
734 passed to this macro; you do not need to handle it.
736 The following letters are unavailable, due to being used as
741 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
742 'Q', 'R', 'S', 'T', 'U'
744 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
746 for (i = 0; i < 256; i++)
747 reg_class_from_letter[i] = NO_REGS;
749 reg_class_from_letter['a'] = ACC_REGS;
750 reg_class_from_letter['b'] = EVEN_ACC_REGS;
751 reg_class_from_letter['c'] = CC_REGS;
752 reg_class_from_letter['d'] = GPR_REGS;
753 reg_class_from_letter['e'] = EVEN_REGS;
754 reg_class_from_letter['f'] = FPR_REGS;
755 reg_class_from_letter['h'] = FEVEN_REGS;
756 reg_class_from_letter['l'] = LR_REG;
757 reg_class_from_letter['q'] = QUAD_REGS;
758 reg_class_from_letter['t'] = ICC_REGS;
759 reg_class_from_letter['u'] = FCC_REGS;
760 reg_class_from_letter['v'] = ICR_REGS;
761 reg_class_from_letter['w'] = FCR_REGS;
762 reg_class_from_letter['x'] = QUAD_FPR_REGS;
763 reg_class_from_letter['y'] = LCR_REG;
764 reg_class_from_letter['z'] = SPR_REGS;
765 reg_class_from_letter['A'] = QUAD_ACC_REGS;
766 reg_class_from_letter['B'] = ACCG_REGS;
767 reg_class_from_letter['C'] = CR_REGS;
768 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
769 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
771 /* There is no single unaligned SI op for PIC code. Sometimes we
772 need to use ".4byte" and sometimes we need to use ".picptr".
773 See frv_assemble_integer for details. */
774 if (flag_pic || TARGET_FDPIC)
775 targetm.asm_out.unaligned_op.si = 0;
777 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
778 target_flags |= MASK_LINKED_FP;
780 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
781 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
783 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
784 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
786 init_machine_status = frv_init_machine_status;
790 /* Some machines may desire to change what optimizations are performed for
791 various optimization levels. This macro, if defined, is executed once just
792 after the optimization level is determined and before the remainder of the
793 command options have been parsed. Values set in this macro are used as the
794 default values for the other command line options.
796 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
797 `-O' is specified, and 0 if neither is specified.
799 SIZE is nonzero if `-Os' is specified, 0 otherwise.
801 You should not use this macro to change options that are not
802 machine-specific. These should uniformly selected by the same optimization
803 level on all supported machines. Use this macro to enable machbine-specific
806 *Do not examine `write_symbols' in this macro!* The debugging options are
807 *not supposed to alter the generated code. */
809 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
810 scheduling pass at the current time. */
812 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
816 #ifdef DISABLE_SCHED2
817 flag_schedule_insns_after_reload = 0;
826 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
829 frv_string_begins_with (tree name, const char *prefix)
831 int prefix_len = strlen (prefix);
833 /* Remember: NAME's length includes the null terminator. */
834 return (TREE_STRING_LENGTH (name) > prefix_len
835 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
838 /* Zero or more C statements that may conditionally modify two variables
839 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
840 been initialized from the two preceding macros.
842 This is necessary in case the fixed or call-clobbered registers depend on
845 You need not define this macro if it has no work to do.
847 If the usage of an entire class of registers depends on the target flags,
848 you may indicate this to GCC by using this macro to modify `fixed_regs' and
849 `call_used_regs' to 1 for each of the registers in the classes which should
850 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
851 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
853 (However, if this class is not included in `GENERAL_REGS' and all of the
854 insn patterns whose constraints permit this class are controlled by target
855 switches, then GCC will automatically avoid using these registers when the
856 target switches are opposed to them.) */
859 frv_conditional_register_usage (void)
863 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
864 fixed_regs[i] = call_used_regs[i] = 1;
866 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
867 fixed_regs[i] = call_used_regs[i] = 1;
869 /* Reserve the registers used for conditional execution. At present, we need
870 1 ICC and 1 ICR register. */
871 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
872 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
876 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
877 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
878 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
879 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
883 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
884 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
887 /* If -fpic, SDA_BASE_REG is the PIC register. */
888 if (g_switch_value == 0 && !flag_pic)
889 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
892 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
898 * Compute the stack frame layout
901 * +---------------+-----------------------+-----------------------+
902 * |Register |type |caller-save/callee-save|
903 * +---------------+-----------------------+-----------------------+
904 * |GR0 |Zero register | - |
905 * |GR1 |Stack pointer(SP) | - |
906 * |GR2 |Frame pointer(FP) | - |
907 * |GR3 |Hidden parameter | caller save |
908 * |GR4-GR7 | - | caller save |
909 * |GR8-GR13 |Argument register | caller save |
910 * |GR14-GR15 | - | caller save |
911 * |GR16-GR31 | - | callee save |
912 * |GR32-GR47 | - | caller save |
913 * |GR48-GR63 | - | callee save |
914 * |FR0-FR15 | - | caller save |
915 * |FR16-FR31 | - | callee save |
916 * |FR32-FR47 | - | caller save |
917 * |FR48-FR63 | - | callee save |
918 * +---------------+-----------------------+-----------------------+
922 * SP-> |-----------------------------------|
924 * |-----------------------------------|
925 * | Register save area |
926 * |-----------------------------------|
927 * | Local variable save area |
928 * FP-> |-----------------------------------|
930 * |-----------------------------------|
931 * | Hidden parameter save area |
932 * |-----------------------------------|
933 * | Return address(LR) storage area |
934 * |-----------------------------------|
935 * | Padding for alignment |
936 * |-----------------------------------|
937 * | Register argument area |
938 * OLD SP-> |-----------------------------------|
940 * |-----------------------------------|
943 * Argument area/Parameter area:
945 * When a function is called, this area is used for argument transfer. When
946 * the argument is set up by the caller function, this area is referred to as
947 * the argument area. When the argument is referenced by the callee function,
948 * this area is referred to as the parameter area. The area is allocated when
949 * all arguments cannot be placed on the argument register at the time of
952 * Register save area:
954 * This is a register save area that must be guaranteed for the caller
955 * function. This area is not secured when the register save operation is not
958 * Local variable save area:
960 * This is the area for local variables and temporary variables.
964 * This area stores the FP value of the caller function.
966 * Hidden parameter save area:
968 * This area stores the start address of the return value storage
969 * area for a struct/union return function.
970 * When a struct/union is used as the return value, the caller
971 * function stores the return value storage area start address in
972 * register GR3 and passes it to the caller function.
973 * The callee function interprets the address stored in the GR3
974 * as the return value storage area start address.
975 * When register GR3 needs to be saved into memory, the callee
976 * function saves it in the hidden parameter save area. This
977 * area is not secured when the save operation is not needed.
979 * Return address(LR) storage area:
981 * This area saves the LR. The LR stores the address of a return to the caller
982 * function for the purpose of function calling.
984 * Argument register area:
986 * This area saves the argument register. This area is not secured when the
987 * save operation is not needed.
991 * Arguments, the count of which equals the count of argument registers (6
992 * words), are positioned in registers GR8 to GR13 and delivered to the callee
993 * function. When a struct/union return function is called, the return value
994 * area address is stored in register GR3. Arguments not placed in the
995 * argument registers will be stored in the stack argument area for transfer
996 * purposes. When an 8-byte type argument is to be delivered using registers,
997 * it is divided into two and placed in two registers for transfer. When
998 * argument registers must be saved to memory, the callee function secures an
999 * argument register save area in the stack. In this case, a continuous
1000 * argument register save area must be established in the parameter area. The
1001 * argument register save area must be allocated as needed to cover the size of
1002 * the argument register to be saved. If the function has a variable count of
1003 * arguments, it saves all argument registers in the argument register save
1006 * Argument Extension Format:
1008 * When an argument is to be stored in the stack, its type is converted to an
1009 * extended type in accordance with the individual argument type. The argument
1010 * is freed by the caller function after the return from the callee function is
1013 * +-----------------------+---------------+------------------------+
1014 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1015 * +-----------------------+---------------+------------------------+
1017 * |signed char |int | 4 |
1018 * |unsigned char |int | 4 |
1019 * |[signed] short int |int | 4 |
1020 * |unsigned short int |int | 4 |
1021 * |[signed] int |No extension | 4 |
1022 * |unsigned int |No extension | 4 |
1023 * |[signed] long int |No extension | 4 |
1024 * |unsigned long int |No extension | 4 |
1025 * |[signed] long long int |No extension | 8 |
1026 * |unsigned long long int |No extension | 8 |
1027 * |float |double | 8 |
1028 * |double |No extension | 8 |
1029 * |long double |No extension | 8 |
1030 * |pointer |No extension | 4 |
1031 * |struct/union |- | 4 (*1) |
1032 * +-----------------------+---------------+------------------------+
1034 * When a struct/union is to be delivered as an argument, the caller copies it
1035 * to the local variable area and delivers the address of that area.
1039 * +-------------------------------+----------------------+
1040 * |Return Value Type |Return Value Interface|
1041 * +-------------------------------+----------------------+
1043 * |[signed|unsigned] char |GR8 |
1044 * |[signed|unsigned] short int |GR8 |
1045 * |[signed|unsigned] int |GR8 |
1046 * |[signed|unsigned] long int |GR8 |
1048 * |[signed|unsigned] long long int|GR8 & GR9 |
1050 * |double |GR8 & GR9 |
1051 * |long double |GR8 & GR9 |
1052 * |struct/union |(*1) |
1053 * +-------------------------------+----------------------+
1055 * When a struct/union is used as the return value, the caller function stores
1056 * the start address of the return value storage area into GR3 and then passes
1057 * it to the callee function. The callee function interprets GR3 as the start
1058 * address of the return value storage area. When this address needs to be
1059 * saved in memory, the callee function secures the hidden parameter save area
1060 * and saves the address in that area.
1064 frv_stack_info (void)
1066 static frv_stack_t info, zero_info;
1067 frv_stack_t *info_ptr = &info;
1068 tree fndecl = current_function_decl;
1076 /* If we've already calculated the values and reload is complete,
1078 if (frv_stack_cache)
1079 return frv_stack_cache;
1081 /* Zero all fields. */
1084 /* Set up the register range information. */
1085 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1086 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1087 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1088 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1090 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1091 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1092 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1093 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1095 info_ptr->regs[STACK_REGS_LR].name = "lr";
1096 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1097 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1098 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1100 info_ptr->regs[STACK_REGS_CC].name = "cc";
1101 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1102 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1103 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1105 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1106 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1107 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1109 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1110 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1111 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1112 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1113 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1115 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1116 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1117 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1118 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1120 info_ptr->regs[STACK_REGS_FP].name = "fp";
1121 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1122 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1123 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1125 /* Determine if this is a stdarg function. If so, allocate space to store
1132 /* Find the last argument, and see if it is __builtin_va_alist. */
1133 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1135 next_arg = TREE_CHAIN (cur_arg);
1136 if (next_arg == (tree)0)
1138 if (DECL_NAME (cur_arg)
1139 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1147 /* Iterate over all of the register ranges. */
1148 for (range = 0; range < STACK_REGS_MAX; range++)
1150 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1151 int first = reg_ptr->first;
1152 int last = reg_ptr->last;
1154 int size_2words = 0;
1157 /* Calculate which registers need to be saved & save area size. */
1161 for (regno = first; regno <= last; regno++)
1163 if ((regs_ever_live[regno] && !call_used_regs[regno])
1164 || (current_function_calls_eh_return
1165 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1166 || (!TARGET_FDPIC && flag_pic
1167 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1169 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1170 size_1word += UNITS_PER_WORD;
1175 /* Calculate whether we need to create a frame after everything else
1176 has been processed. */
1181 if (regs_ever_live[LR_REGNO]
1183 /* This is set for __builtin_return_address, etc. */
1184 || cfun->machine->frame_needed
1185 || (TARGET_LINKED_FP && frame_pointer_needed)
1186 || (!TARGET_FDPIC && flag_pic
1187 && cfun->uses_pic_offset_table))
1189 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1190 size_1word += UNITS_PER_WORD;
1194 case STACK_REGS_STDARG:
1197 /* If this is a stdarg function with a non varardic
1198 argument split between registers and the stack,
1199 adjust the saved registers downward. */
1200 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1203 for (regno = first; regno <= last; regno++)
1205 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1206 size_1word += UNITS_PER_WORD;
1209 info_ptr->stdarg_size = size_1word;
1213 case STACK_REGS_STRUCT:
1214 if (cfun->returns_struct)
1216 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1217 size_1word += UNITS_PER_WORD;
1225 /* If this is a field, it only takes one word. */
1226 if (reg_ptr->field_p)
1227 size_1word = UNITS_PER_WORD;
1229 /* Determine which register pairs can be saved together. */
1230 else if (reg_ptr->dword_p && TARGET_DWORD)
1232 for (regno = first; regno < last; regno += 2)
1234 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1236 size_2words += 2 * UNITS_PER_WORD;
1237 size_1word -= 2 * UNITS_PER_WORD;
1238 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1239 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1244 reg_ptr->size_1word = size_1word;
1245 reg_ptr->size_2words = size_2words;
1247 if (! reg_ptr->special_p)
1249 info_ptr->regs_size_1word += size_1word;
1250 info_ptr->regs_size_2words += size_2words;
1255 /* Set up the sizes of each each field in the frame body, making the sizes
1256 of each be divisible by the size of a dword if dword operations might
1257 be used, or the size of a word otherwise. */
1258 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1260 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1261 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1262 + info_ptr->regs_size_1word,
1264 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1266 info_ptr->pretend_size = cfun->pretend_args_size;
1268 /* Work out the size of the frame, excluding the header. Both the frame
1269 body and register parameter area will be dword-aligned. */
1270 info_ptr->total_size
1271 = (ADDR_ALIGN (info_ptr->parameter_size
1272 + info_ptr->regs_size
1273 + info_ptr->vars_size,
1275 + ADDR_ALIGN (info_ptr->pretend_size
1276 + info_ptr->stdarg_size,
1277 2 * UNITS_PER_WORD));
1279 /* See if we need to create a frame at all, if so add header area. */
1280 if (info_ptr->total_size > 0
1281 || frame_pointer_needed
1282 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1283 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1285 offset = info_ptr->parameter_size;
1286 info_ptr->header_size = 4 * UNITS_PER_WORD;
1287 info_ptr->total_size += 4 * UNITS_PER_WORD;
1289 /* Calculate the offsets to save normal register pairs. */
1290 for (range = 0; range < STACK_REGS_MAX; range++)
1292 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1293 if (! reg_ptr->special_p)
1295 int first = reg_ptr->first;
1296 int last = reg_ptr->last;
1299 for (regno = first; regno <= last; regno++)
1300 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1301 && regno != FRAME_POINTER_REGNUM
1302 && (regno < FIRST_ARG_REGNUM
1303 || regno > LAST_ARG_REGNUM))
1305 info_ptr->reg_offset[regno] = offset;
1306 offset += 2 * UNITS_PER_WORD;
1311 /* Calculate the offsets to save normal single registers. */
1312 for (range = 0; range < STACK_REGS_MAX; range++)
1314 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1315 if (! reg_ptr->special_p)
1317 int first = reg_ptr->first;
1318 int last = reg_ptr->last;
1321 for (regno = first; regno <= last; regno++)
1322 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1323 && regno != FRAME_POINTER_REGNUM
1324 && (regno < FIRST_ARG_REGNUM
1325 || regno > LAST_ARG_REGNUM))
1327 info_ptr->reg_offset[regno] = offset;
1328 offset += UNITS_PER_WORD;
1333 /* Calculate the offset to save the local variables at. */
1334 offset = ADDR_ALIGN (offset, alignment);
1335 if (info_ptr->vars_size)
1337 info_ptr->vars_offset = offset;
1338 offset += info_ptr->vars_size;
1341 /* Align header to a dword-boundary. */
1342 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1344 /* Calculate the offsets in the fixed frame. */
1345 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1346 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1347 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1349 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1350 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1351 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1353 if (cfun->returns_struct)
1355 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1356 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1357 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1360 /* Calculate the offsets to store the arguments passed in registers
1361 for stdarg functions. The register pairs are first and the single
1362 register if any is last. The register save area starts on a
1364 if (info_ptr->stdarg_size)
1366 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1367 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1370 /* Skip the header. */
1371 offset += 4 * UNITS_PER_WORD;
1372 for (regno = first; regno <= last; regno++)
1374 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1376 info_ptr->reg_offset[regno] = offset;
1377 offset += 2 * UNITS_PER_WORD;
1379 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1381 info_ptr->reg_offset[regno] = offset;
1382 offset += UNITS_PER_WORD;
1388 if (reload_completed)
1389 frv_stack_cache = info_ptr;
1395 /* Print the information about the frv stack offsets, etc. when debugging. */
1398 frv_debug_stack (frv_stack_t *info)
1403 info = frv_stack_info ();
1405 fprintf (stderr, "\nStack information for function %s:\n",
1406 ((current_function_decl && DECL_NAME (current_function_decl))
1407 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1410 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1411 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1412 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1413 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1414 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1416 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1417 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1418 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1419 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1421 for (range = 0; range < STACK_REGS_MAX; range++)
1423 frv_stack_regs_t *regs = &(info->regs[range]);
1424 if ((regs->size_1word + regs->size_2words) > 0)
1426 int first = regs->first;
1427 int last = regs->last;
1430 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1431 regs->name, regs->size_1word + regs->size_2words,
1432 regs->size_1word, regs->size_2words);
1434 for (regno = first; regno <= last; regno++)
1436 if (info->save_p[regno] == REG_SAVE_1WORD)
1437 fprintf (stderr, " %s (%d)", reg_names[regno],
1438 info->reg_offset[regno]);
1440 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1441 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1442 reg_names[regno+1], info->reg_offset[regno]);
1445 fputc ('\n', stderr);
1455 /* Used during final to control the packing of insns. The value is
1456 1 if the current instruction should be packed with the next one,
1457 0 if it shouldn't or -1 if packing is disabled altogether. */
1459 static int frv_insn_packing_flag;
1461 /* True if the current function contains a far jump. */
1464 frv_function_contains_far_jump (void)
1466 rtx insn = get_insns ();
1468 && !(GET_CODE (insn) == JUMP_INSN
1469 /* Ignore tablejump patterns. */
1470 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1471 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1472 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1473 insn = NEXT_INSN (insn);
1474 return (insn != NULL);
1477 /* For the FRV, this function makes sure that a function with far jumps
1478 will return correctly. It also does the VLIW packing. */
1481 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1483 /* If no frame was created, check whether the function uses a call
1484 instruction to implement a far jump. If so, save the link in gr3 and
1485 replace all returns to LR with returns to GR3. GR3 is used because it
1486 is call-clobbered, because is not available to the register allocator,
1487 and because all functions that take a hidden argument pointer will have
1489 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1493 /* Just to check that the above comment is true. */
1494 if (regs_ever_live[GPR_FIRST + 3])
1497 /* Generate the instruction that saves the link register. */
1498 fprintf (file, "\tmovsg lr,gr3\n");
1500 /* Replace the LR with GR3 in *return_internal patterns. The insn
1501 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1502 simply emit a different assembly directive because bralr and jmpl
1503 execute in different units. */
1504 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1505 if (GET_CODE (insn) == JUMP_INSN)
1507 rtx pattern = PATTERN (insn);
1508 if (GET_CODE (pattern) == PARALLEL
1509 && XVECLEN (pattern, 0) >= 2
1510 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1511 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1513 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1514 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1515 REGNO (address) = GPR_FIRST + 3;
1522 /* Allow the garbage collector to free the nops created by frv_reorg. */
1523 memset (frv_nops, 0, sizeof (frv_nops));
1527 /* Return the next available temporary register in a given class. */
1530 frv_alloc_temp_reg (
1531 frv_tmp_reg_t *info, /* which registers are available */
1532 enum reg_class class, /* register class desired */
1533 enum machine_mode mode, /* mode to allocate register with */
1534 int mark_as_used, /* register not available after allocation */
1535 int no_abort) /* return NULL instead of aborting */
1537 int regno = info->next_reg[ (int)class ];
1538 int orig_regno = regno;
1539 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1544 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1545 && TEST_HARD_REG_BIT (info->regs, regno))
1548 if (++regno >= FIRST_PSEUDO_REGISTER)
1550 if (regno == orig_regno)
1559 nr = HARD_REGNO_NREGS (regno, mode);
1560 info->next_reg[ (int)class ] = regno + nr;
1563 for (i = 0; i < nr; i++)
1564 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1566 return gen_rtx_REG (mode, regno);
1570 /* Return an rtx with the value OFFSET, which will either be a register or a
1571 signed 12-bit integer. It can be used as the second operand in an "add"
1572 instruction, or as the index in a load or store.
1574 The function returns a constant rtx if OFFSET is small enough, otherwise
1575 it loads the constant into register OFFSET_REGNO and returns that. */
1577 frv_frame_offset_rtx (int offset)
1579 rtx offset_rtx = GEN_INT (offset);
1580 if (IN_RANGE_P (offset, -2048, 2047))
1584 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1585 if (IN_RANGE_P (offset, -32768, 32767))
1586 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1589 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1590 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1596 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1597 prologue and epilogue uses such expressions to access the stack. */
1599 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1601 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1603 frv_frame_offset_rtx (offset)));
1606 /* Generate a frame-related expression:
1608 (set REG (mem (plus (sp) (const_int OFFSET)))).
1610 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1611 instructions. Marking the expressions as frame-related is superfluous if
1612 the note contains just a single set. But if the note contains a PARALLEL
1613 or SEQUENCE that has several sets, each set must be individually marked
1614 as frame-related. */
1616 frv_dwarf_store (rtx reg, int offset)
1618 rtx set = gen_rtx_SET (VOIDmode,
1619 gen_rtx_MEM (GET_MODE (reg),
1620 plus_constant (stack_pointer_rtx,
1623 RTX_FRAME_RELATED_P (set) = 1;
1627 /* Emit a frame-related instruction whose pattern is PATTERN. The
1628 instruction is the last in a sequence that cumulatively performs the
1629 operation described by DWARF_PATTERN. The instruction is marked as
1630 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1633 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1635 rtx insn = emit_insn (pattern);
1636 RTX_FRAME_RELATED_P (insn) = 1;
1637 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1642 /* Emit instructions that transfer REG to or from the memory location (sp +
1643 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1644 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1645 function to store registers and only the epilogue uses it to load them.
1647 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1648 The generated instruction will use BASE as its base register. BASE may
1649 simply be the stack pointer, but if several accesses are being made to a
1650 region far away from the stack pointer, it may be more efficient to set
1651 up a temporary instead.
1653 Store instructions will be frame-related and will be annotated with the
1654 overall effect of the store. Load instructions will be followed by a
1655 (use) to prevent later optimizations from zapping them.
1657 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1658 as a temporary in such cases. */
1660 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1662 enum machine_mode mode = GET_MODE (reg);
1663 rtx mem = frv_frame_mem (mode,
1665 stack_offset - accessor->base_offset);
1667 if (accessor->op == FRV_LOAD)
1669 if (SPR_P (REGNO (reg)))
1671 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1672 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1673 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1676 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1677 emit_insn (gen_rtx_USE (VOIDmode, reg));
1681 if (SPR_P (REGNO (reg)))
1683 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1684 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1685 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1686 frv_dwarf_store (reg, stack_offset));
1688 else if (GET_MODE (reg) == DImode)
1690 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1691 with a separate save for each register. */
1692 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1693 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1694 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1695 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1696 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1697 gen_rtx_PARALLEL (VOIDmode,
1698 gen_rtvec (2, set1, set2)));
1701 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1702 frv_dwarf_store (reg, stack_offset));
1706 /* A function that uses frv_frame_access to transfer a group of registers to
1707 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1708 is the stack information generated by frv_stack_info, and REG_SET is the
1709 number of the register set to transfer. */
1711 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1715 frv_stack_regs_t *regs_info;
1718 regs_info = &info->regs[reg_set];
1719 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1720 if (info->save_p[regno])
1721 frv_frame_access (accessor,
1722 info->save_p[regno] == REG_SAVE_2WORDS
1723 ? gen_rtx_REG (DImode, regno)
1724 : gen_rtx_REG (SImode, regno),
1725 info->reg_offset[regno]);
1728 /* Save or restore callee-saved registers that are kept outside the frame
1729 header. The function saves the registers if OP is FRV_STORE and restores
1730 them if OP is FRV_LOAD. INFO is the stack information generated by
1733 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1735 frv_frame_accessor_t accessor;
1738 accessor.base = stack_pointer_rtx;
1739 accessor.base_offset = 0;
1740 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1741 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1742 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1746 /* Called after register allocation to add any instructions needed for the
1747 prologue. Using a prologue insn is favored compared to putting all of the
1748 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1749 it allows the scheduler to intermix instructions with the saves of
1750 the caller saved registers. In some cases, it might be necessary
1751 to emit a barrier instruction as the last insn to prevent such
1754 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1755 so that the debug info generation code can handle them properly. */
1757 frv_expand_prologue (void)
1759 frv_stack_t *info = frv_stack_info ();
1760 rtx sp = stack_pointer_rtx;
1761 rtx fp = frame_pointer_rtx;
1762 frv_frame_accessor_t accessor;
1764 if (TARGET_DEBUG_STACK)
1765 frv_debug_stack (info);
1767 if (info->total_size == 0)
1770 /* We're interested in three areas of the frame here:
1772 A: the register save area
1774 C: the header after B
1776 If the frame pointer isn't used, we'll have to set up A, B and C
1777 using the stack pointer. If the frame pointer is used, we'll access
1781 B: set up using sp or a temporary (see below)
1784 We set up B using the stack pointer if the frame is small enough.
1785 Otherwise, it's more efficient to copy the old stack pointer into a
1786 temporary and use that.
1788 Note that it's important to make sure the prologue and epilogue use the
1789 same registers to access A and C, since doing otherwise will confuse
1790 the aliasing code. */
1792 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1793 isn't used, the same method will serve for C. */
1794 accessor.op = FRV_STORE;
1795 if (frame_pointer_needed && info->total_size > 2048)
1799 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1800 accessor.base_offset = info->total_size;
1801 insn = emit_insn (gen_movsi (accessor.base, sp));
1805 accessor.base = stack_pointer_rtx;
1806 accessor.base_offset = 0;
1809 /* Allocate the stack space. */
1811 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1812 rtx dwarf_offset = GEN_INT (-info->total_size);
1814 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1817 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1820 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1821 and point the new one to that location. */
1822 if (frame_pointer_needed)
1824 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1826 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1827 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1829 rtx asm_src = plus_constant (accessor.base,
1830 fp_offset - accessor.base_offset);
1831 rtx dwarf_src = plus_constant (sp, fp_offset);
1833 /* Store the old frame pointer at (sp + FP_OFFSET). */
1834 frv_frame_access (&accessor, fp, fp_offset);
1836 /* Set up the new frame pointer. */
1837 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1838 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1840 /* Access region C from the frame pointer. */
1842 accessor.base_offset = fp_offset;
1845 /* Set up region C. */
1846 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1847 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1848 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1850 /* Set up region A. */
1851 frv_frame_access_standard_regs (FRV_STORE, info);
1853 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1854 scheduler from moving loads before the stores saving the registers. */
1855 if (info->stdarg_size > 0)
1856 emit_insn (gen_blockage ());
1858 /* Set up pic register/small data register for this function. */
1859 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1860 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1861 gen_rtx_REG (Pmode, LR_REGNO),
1862 gen_rtx_REG (SImode, OFFSET_REGNO)));
1866 /* Under frv, all of the work is done via frv_expand_epilogue, but
1867 this function provides a convenient place to do cleanup. */
1870 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1871 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1873 frv_stack_cache = (frv_stack_t *)0;
1875 /* Zap last used registers for conditional execution. */
1876 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1878 /* Release the bitmap of created insns. */
1879 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1883 /* Called after register allocation to add any instructions needed for the
1884 epilogue. Using an epilogue insn is favored compared to putting all of the
1885 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1886 it allows the scheduler to intermix instructions with the saves of
1887 the caller saved registers. In some cases, it might be necessary
1888 to emit a barrier instruction as the last insn to prevent such
1892 frv_expand_epilogue (bool emit_return)
1894 frv_stack_t *info = frv_stack_info ();
1895 rtx fp = frame_pointer_rtx;
1896 rtx sp = stack_pointer_rtx;
1900 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1902 /* Restore the stack pointer to its original value if alloca or the like
1904 if (! current_function_sp_is_unchanging)
1905 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1907 /* Restore the callee-saved registers that were used in this function. */
1908 frv_frame_access_standard_regs (FRV_LOAD, info);
1910 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1911 no return instruction should be emitted. */
1912 if (info->save_p[LR_REGNO])
1917 /* Use the same method to access the link register's slot as we did in
1918 the prologue. In other words, use the frame pointer if available,
1919 otherwise use the stack pointer.
1921 LR_OFFSET is the offset of the link register's slot from the start
1922 of the frame and MEM is a memory rtx for it. */
1923 lr_offset = info->reg_offset[LR_REGNO];
1924 if (frame_pointer_needed)
1925 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1927 mem = frv_frame_mem (Pmode, sp, lr_offset);
1929 /* Load the old link register into a GPR. */
1930 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1931 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1934 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1936 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1937 the load is preserved. */
1938 if (frame_pointer_needed)
1940 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1941 emit_insn (gen_rtx_USE (VOIDmode, fp));
1944 /* Deallocate the stack frame. */
1945 if (info->total_size != 0)
1947 rtx offset = frv_frame_offset_rtx (info->total_size);
1948 emit_insn (gen_stack_adjust (sp, sp, offset));
1951 /* If this function uses eh_return, add the final stack adjustment now. */
1952 if (current_function_calls_eh_return)
1953 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1956 emit_jump_insn (gen_epilogue_return (return_addr));
1959 rtx lr = return_addr;
1961 if (REGNO (return_addr) != LR_REGNO)
1963 lr = gen_rtx_REG (Pmode, LR_REGNO);
1964 emit_move_insn (lr, return_addr);
1967 emit_insn (gen_rtx_USE (VOIDmode, lr));
1972 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1975 frv_asm_output_mi_thunk (FILE *file,
1976 tree thunk_fndecl ATTRIBUTE_UNUSED,
1977 HOST_WIDE_INT delta,
1978 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1981 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1982 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1983 const char *name_jmp = reg_names[JUMP_REGNO];
1984 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1986 /* Do the add using an addi if possible. */
1987 if (IN_RANGE_P (delta, -2048, 2047))
1988 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1991 const char *const name_add = reg_names[TEMP_REGNO];
1992 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1993 parallel, delta, name_add);
1994 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1996 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2001 const char *name_pic = reg_names[FDPIC_REGNO];
2002 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2006 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2007 assemble_name (file, name_func);
2008 fprintf (file, "),%s\n", name_jmp);
2010 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2011 assemble_name (file, name_func);
2012 fprintf (file, "),%s\n", name_jmp);
2014 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2018 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2019 assemble_name (file, name_func);
2020 fprintf (file, "\t)), %s\n", name_jmp);
2025 fprintf (file, "\tsethi%s #hi(", parallel);
2026 assemble_name (file, name_func);
2027 fprintf (file, "),%s\n", name_jmp);
2029 fprintf (file, "\tsetlo #lo(");
2030 assemble_name (file, name_func);
2031 fprintf (file, "),%s\n", name_jmp);
2035 /* Use JUMP_REGNO as a temporary PIC register. */
2036 const char *name_lr = reg_names[LR_REGNO];
2037 const char *name_gppic = name_jmp;
2038 const char *name_tmp = reg_names[TEMP_REGNO];
2040 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2041 fprintf (file, "\tcall 1f\n");
2042 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2043 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2044 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2045 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2046 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2048 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2049 assemble_name (file, name_func);
2050 fprintf (file, "),%s\n", name_tmp);
2052 fprintf (file, "\tsetlo #gprello(");
2053 assemble_name (file, name_func);
2054 fprintf (file, "),%s\n", name_tmp);
2056 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2059 /* Jump to the function address. */
2060 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2064 /* A C expression which is nonzero if a function must have and use a frame
2065 pointer. This expression is evaluated in the reload pass. If its value is
2066 nonzero the function will have a frame pointer.
2068 The expression can in principle examine the current function and decide
2069 according to the facts, but on most machines the constant 0 or the constant
2070 1 suffices. Use 0 when the machine allows code to be generated with no
2071 frame pointer, and doing so saves some time or space. Use 1 when there is
2072 no possible advantage to avoiding a frame pointer.
2074 In certain cases, the compiler does not know how to produce valid code
2075 without a frame pointer. The compiler recognizes those cases and
2076 automatically gives the function a frame pointer regardless of what
2077 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2079 In a function that does not require a frame pointer, the frame pointer
2080 register can be allocated for ordinary usage, unless you mark it as a fixed
2081 register. See `FIXED_REGISTERS' for more information. */
2083 /* On frv, create a frame whenever we need to create stack. */
2086 frv_frame_pointer_required (void)
2088 /* If we forgoing the usual linkage requirements, we only need
2089 a frame pointer if the stack pointer might change. */
2090 if (!TARGET_LINKED_FP)
2091 return !current_function_sp_is_unchanging;
2093 if (! current_function_is_leaf)
2096 if (get_frame_size () != 0)
2102 if (!current_function_sp_is_unchanging)
2105 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2111 if (cfun->machine->frame_needed)
2118 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2119 initial difference between the specified pair of registers. This macro must
2120 be defined if `ELIMINABLE_REGS' is defined. */
2122 /* See frv_stack_info for more details on the frv stack frame. */
2125 frv_initial_elimination_offset (int from, int to)
2127 frv_stack_t *info = frv_stack_info ();
2130 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2131 ret = info->total_size - info->pretend_size;
2133 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2134 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2136 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2137 ret = (info->total_size
2138 - info->reg_offset[FRAME_POINTER_REGNUM]
2139 - info->pretend_size);
2144 if (TARGET_DEBUG_STACK)
2145 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2146 reg_names [from], reg_names[to], ret);
2152 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2155 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2156 enum machine_mode mode,
2157 tree type ATTRIBUTE_UNUSED,
2161 if (TARGET_DEBUG_ARG)
2163 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2164 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2168 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2171 frv_expand_builtin_saveregs (void)
2173 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2175 if (TARGET_DEBUG_ARG)
2176 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2179 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2183 /* Expand __builtin_va_start to do the va_start macro. */
2186 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2189 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2191 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2192 GEN_INT (UNITS_PER_WORD * num));
2194 if (TARGET_DEBUG_ARG)
2196 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2197 cfun->args_info, num);
2199 debug_rtx (nextarg);
2202 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2203 make_tree (ptr_type_node, nextarg));
2204 TREE_SIDE_EFFECTS (t) = 1;
2206 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2210 /* Expand a block move operation, and return 1 if successful. Return 0
2211 if we should let the compiler generate normal code.
2213 operands[0] is the destination
2214 operands[1] is the source
2215 operands[2] is the length
2216 operands[3] is the alignment */
2218 /* Maximum number of loads to do before doing the stores */
2219 #ifndef MAX_MOVE_REG
2220 #define MAX_MOVE_REG 4
2223 /* Maximum number of total loads to do. */
2224 #ifndef TOTAL_MOVE_REG
2225 #define TOTAL_MOVE_REG 8
2229 frv_expand_block_move (rtx operands[])
2231 rtx orig_dest = operands[0];
2232 rtx orig_src = operands[1];
2233 rtx bytes_rtx = operands[2];
2234 rtx align_rtx = operands[3];
2235 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2248 rtx stores[MAX_MOVE_REG];
2250 enum machine_mode mode;
2252 /* If this is not a fixed size move, just call memcpy. */
2256 /* If this is not a fixed size alignment, abort. */
2257 if (GET_CODE (align_rtx) != CONST_INT)
2260 align = INTVAL (align_rtx);
2262 /* Anything to move? */
2263 bytes = INTVAL (bytes_rtx);
2267 /* Don't support real large moves. */
2268 if (bytes > TOTAL_MOVE_REG*align)
2271 /* Move the address into scratch registers. */
2272 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2273 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2275 num_reg = offset = 0;
2276 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2278 /* Calculate the correct offset for src/dest. */
2282 dest_addr = dest_reg;
2286 src_addr = plus_constant (src_reg, offset);
2287 dest_addr = plus_constant (dest_reg, offset);
2290 /* Generate the appropriate load and store, saving the stores
2292 if (bytes >= 4 && align >= 4)
2294 else if (bytes >= 2 && align >= 2)
2299 move_bytes = GET_MODE_SIZE (mode);
2300 tmp_reg = gen_reg_rtx (mode);
2301 src_mem = change_address (orig_src, mode, src_addr);
2302 dest_mem = change_address (orig_dest, mode, dest_addr);
2303 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2304 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2306 if (num_reg >= MAX_MOVE_REG)
2308 for (i = 0; i < num_reg; i++)
2309 emit_insn (stores[i]);
2314 for (i = 0; i < num_reg; i++)
2315 emit_insn (stores[i]);
2321 /* Expand a block clear operation, and return 1 if successful. Return 0
2322 if we should let the compiler generate normal code.
2324 operands[0] is the destination
2325 operands[1] is the length
2326 operands[2] is the alignment */
2329 frv_expand_block_clear (rtx operands[])
2331 rtx orig_dest = operands[0];
2332 rtx bytes_rtx = operands[1];
2333 rtx align_rtx = operands[2];
2334 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2343 enum machine_mode mode;
2345 /* If this is not a fixed size move, just call memcpy. */
2349 /* If this is not a fixed size alignment, abort. */
2350 if (GET_CODE (align_rtx) != CONST_INT)
2353 align = INTVAL (align_rtx);
2355 /* Anything to move? */
2356 bytes = INTVAL (bytes_rtx);
2360 /* Don't support real large clears. */
2361 if (bytes > TOTAL_MOVE_REG*align)
2364 /* Move the address into a scratch register. */
2365 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2367 num_reg = offset = 0;
2368 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2370 /* Calculate the correct offset for src/dest. */
2371 dest_addr = ((offset == 0)
2373 : plus_constant (dest_reg, offset));
2375 /* Generate the appropriate store of gr0. */
2376 if (bytes >= 4 && align >= 4)
2378 else if (bytes >= 2 && align >= 2)
2383 clear_bytes = GET_MODE_SIZE (mode);
2384 dest_mem = change_address (orig_dest, mode, dest_addr);
2385 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2392 /* The following variable is used to output modifiers of assembler
2393 code of the current output insn. */
2395 static rtx *frv_insn_operands;
2397 /* The following function is used to add assembler insn code suffix .p
2398 if it is necessary. */
2401 frv_asm_output_opcode (FILE *f, const char *ptr)
2405 if (frv_insn_packing_flag <= 0)
2408 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2411 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2412 || (*ptr >= 'A' && *ptr <= 'Z')))
2414 int letter = *ptr++;
2417 frv_print_operand (f, frv_insn_operands [c], letter);
2418 while ((c = *ptr) >= '0' && c <= '9')
2430 /* Set up the packing bit for the current output insn. Note that this
2431 function is not called for asm insns. */
2434 frv_final_prescan_insn (rtx insn, rtx *opvec,
2435 int noperands ATTRIBUTE_UNUSED)
2439 if (frv_insn_packing_flag >= 0)
2441 frv_insn_operands = opvec;
2442 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2444 else if (recog_memoized (insn) >= 0
2445 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2446 /* Packing optimizations have been disabled, but INSN can only
2447 be issued in M1. Insert an mnop in M0. */
2448 fprintf (asm_out_file, "\tmnop.p\n");
2454 /* A C expression whose value is RTL representing the address in a stack frame
2455 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2456 an RTL expression for the address of the stack frame itself.
2458 If you don't define this macro, the default is to return the value of
2459 FRAMEADDR--that is, the stack frame address is also the address of the stack
2460 word that points to the previous frame. */
2462 /* The default is correct, but we need to make sure the frame gets created. */
2464 frv_dynamic_chain_address (rtx frame)
2466 cfun->machine->frame_needed = 1;
2471 /* A C expression whose value is RTL representing the value of the return
2472 address for the frame COUNT steps up from the current frame, after the
2473 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2474 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2477 The value of the expression must always be the correct address when COUNT is
2478 zero, but may be `NULL_RTX' if there is not way to determine the return
2479 address of other frames. */
2482 frv_return_addr_rtx (int count, rtx frame)
2486 cfun->machine->frame_needed = 1;
2487 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2490 /* Given a memory reference MEMREF, interpret the referenced memory as
2491 an array of MODE values, and return a reference to the element
2492 specified by INDEX. Assume that any pre-modification implicit in
2493 MEMREF has already happened.
2495 MEMREF must be a legitimate operand for modes larger than SImode.
2496 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2497 this function cannot handle. */
2499 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2501 rtx base = XEXP (memref, 0);
2502 if (GET_CODE (base) == PRE_MODIFY)
2503 base = XEXP (base, 0);
2504 return change_address (memref, mode,
2505 plus_constant (base, index * GET_MODE_SIZE (mode)));
2509 /* Print a memory address as an operand to reference that memory location. */
2511 frv_print_operand_address (FILE * stream, rtx x)
2513 if (GET_CODE (x) == MEM)
2516 switch (GET_CODE (x))
2519 fputs (reg_names [ REGNO (x)], stream);
2523 fprintf (stream, "%ld", (long) INTVAL (x));
2527 assemble_name (stream, XSTR (x, 0));
2532 output_addr_const (stream, x);
2539 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2544 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2546 int regno = true_regnum (x);
2548 fputs (reg_names[regno], stream);
2550 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2553 /* Print a memory reference suitable for the ld/st instructions. */
2556 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2558 struct frv_unspec unspec;
2562 switch (GET_CODE (x))
2569 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2571 x1 = XEXP (XEXP (x, 1), 1);
2581 if (GET_CODE (x0) == CONST_INT)
2589 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2598 else if (GET_CODE (x1) != CONST_INT)
2599 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2602 fputs ("@(", stream);
2604 fputs (reg_names[GPR_R0], stream);
2605 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2606 frv_print_operand_memory_reference_reg (stream, x0);
2608 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2610 fputs (",", stream);
2612 fputs (reg_names [GPR_R0], stream);
2616 switch (GET_CODE (x1))
2620 frv_print_operand_memory_reference_reg (stream, x1);
2624 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2628 if (!frv_const_unspec_p (x1, &unspec))
2629 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2630 frv_output_const_unspec (stream, &unspec);
2634 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2638 fputs (")", stream);
2642 /* Return 2 for likely branches and 0 for non-likely branches */
2644 #define FRV_JUMP_LIKELY 2
2645 #define FRV_JUMP_NOT_LIKELY 0
2648 frv_print_operand_jump_hint (rtx insn)
2653 HOST_WIDE_INT prob = -1;
2654 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2656 if (GET_CODE (insn) != JUMP_INSN)
2659 /* Assume any non-conditional jump is likely. */
2660 if (! any_condjump_p (insn))
2661 ret = FRV_JUMP_LIKELY;
2665 labelref = condjump_label (insn);
2668 rtx label = XEXP (labelref, 0);
2669 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2674 note = find_reg_note (insn, REG_BR_PROB, 0);
2676 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2680 prob = INTVAL (XEXP (note, 0));
2681 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2683 : FRV_JUMP_NOT_LIKELY);
2695 case UNKNOWN: direction = "unknown jump direction"; break;
2696 case BACKWARD: direction = "jump backward"; break;
2697 case FORWARD: direction = "jump forward"; break;
2701 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2702 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2703 (long)INSN_UID (insn), direction, (long)prob,
2704 (long)REG_BR_PROB_BASE, ret);
2712 /* Return the comparison operator to use for CODE given that the ICC
2716 comparison_string (enum rtx_code code, rtx op0)
2718 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2721 default: output_operand_lossage ("bad condition code");
2722 case EQ: return "eq";
2723 case NE: return "ne";
2724 case LT: return is_nz_p ? "n" : "lt";
2725 case LE: return "le";
2726 case GT: return "gt";
2727 case GE: return is_nz_p ? "p" : "ge";
2728 case LTU: return is_nz_p ? "no" : "c";
2729 case LEU: return is_nz_p ? "eq" : "ls";
2730 case GTU: return is_nz_p ? "ne" : "hi";
2731 case GEU: return is_nz_p ? "ra" : "nc";
2735 /* Print an operand to an assembler instruction.
2737 `%' followed by a letter and a digit says to output an operand in an
2738 alternate fashion. Four letters have standard, built-in meanings described
2739 below. The machine description macro `PRINT_OPERAND' can define additional
2740 letters with nonstandard meanings.
2742 `%cDIGIT' can be used to substitute an operand that is a constant value
2743 without the syntax that normally indicates an immediate operand.
2745 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2748 `%aDIGIT' can be used to substitute an operand as if it were a memory
2749 reference, with the actual operand treated as the address. This may be
2750 useful when outputting a "load address" instruction, because often the
2751 assembler syntax for such an instruction requires you to write the operand
2752 as if it were a memory reference.
2754 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2756 `%=' outputs a number which is unique to each instruction in the entire
2757 compilation. This is useful for making local labels to be referred to more
2758 than once in a single template that generates multiple assembler
2761 `%' followed by a punctuation character specifies a substitution that does
2762 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2763 assembler code. Other nonstandard cases can be defined in the
2764 `PRINT_OPERAND' macro. You must also define which punctuation characters
2765 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2768 frv_print_operand (FILE * file, rtx x, int code)
2770 struct frv_unspec unspec;
2771 HOST_WIDE_INT value;
2774 if (code != 0 && !isalpha (code))
2777 else if (GET_CODE (x) == CONST_INT)
2780 else if (GET_CODE (x) == CONST_DOUBLE)
2782 if (GET_MODE (x) == SFmode)
2787 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2788 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2792 else if (GET_MODE (x) == VOIDmode)
2793 value = CONST_DOUBLE_LOW (x);
2796 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2807 fputs (reg_names[GPR_R0], file);
2811 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2815 /* Output small data area base register (gr16). */
2816 fputs (reg_names[SDA_BASE_REG], file);
2820 /* Output pic register (gr17). */
2821 fputs (reg_names[PIC_REGNO], file);
2825 /* Output the temporary integer CCR register. */
2826 fputs (reg_names[ICR_TEMP], file);
2830 /* Output the temporary integer CC register. */
2831 fputs (reg_names[ICC_TEMP], file);
2834 /* case 'a': print an address. */
2837 /* Print appropriate test for integer branch false operation. */
2838 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2839 XEXP (x, 0)), file);
2843 /* Print appropriate test for integer branch true operation. */
2844 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2848 /* Print 1 for a NE and 0 for an EQ to give the final argument
2849 for a conditional instruction. */
2850 if (GET_CODE (x) == NE)
2853 else if (GET_CODE (x) == EQ)
2857 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2861 /* Print appropriate test for floating point branch false operation. */
2862 switch (GET_CODE (x))
2865 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2867 case EQ: fputs ("ne", file); break;
2868 case NE: fputs ("eq", file); break;
2869 case LT: fputs ("uge", file); break;
2870 case LE: fputs ("ug", file); break;
2871 case GT: fputs ("ule", file); break;
2872 case GE: fputs ("ul", file); break;
2877 /* Print appropriate test for floating point branch true operation. */
2878 switch (GET_CODE (x))
2881 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2883 case EQ: fputs ("eq", file); break;
2884 case NE: fputs ("ne", file); break;
2885 case LT: fputs ("lt", file); break;
2886 case LE: fputs ("le", file); break;
2887 case GT: fputs ("gt", file); break;
2888 case GE: fputs ("ge", file); break;
2893 /* Print appropriate GOT function. */
2894 if (GET_CODE (x) != CONST_INT)
2895 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2896 fputs (unspec_got_name (INTVAL (x)), file);
2900 /* Print 'i' if the operand is a constant, or is a memory reference that
2902 if (GET_CODE (x) == MEM)
2903 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2904 ? XEXP (XEXP (x, 0), 1)
2906 else if (GET_CODE (x) == PLUS)
2909 switch (GET_CODE (x))
2923 /* For jump instructions, print 'i' if the operand is a constant or
2924 is an expression that adds a constant. */
2925 if (GET_CODE (x) == CONST_INT)
2930 if (GET_CODE (x) == CONST_INT
2931 || (GET_CODE (x) == PLUS
2932 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2933 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2939 /* Print the lower register of a double word register pair */
2940 if (GET_CODE (x) == REG)
2941 fputs (reg_names[ REGNO (x)+1 ], file);
2943 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2946 /* case 'l': print a LABEL_REF. */
2950 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2951 for the second word of double memory operations. */
2952 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2953 switch (GET_CODE (x))
2956 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2959 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2967 frv_print_operand_memory_reference (file, x, offset);
2973 /* Print the opcode of a command. */
2974 switch (GET_CODE (x))
2977 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2979 case PLUS: fputs ("add", file); break;
2980 case MINUS: fputs ("sub", file); break;
2981 case AND: fputs ("and", file); break;
2982 case IOR: fputs ("or", file); break;
2983 case XOR: fputs ("xor", file); break;
2984 case ASHIFT: fputs ("sll", file); break;
2985 case ASHIFTRT: fputs ("sra", file); break;
2986 case LSHIFTRT: fputs ("srl", file); break;
2990 /* case 'n': negate and print a constant int. */
2993 /* Print PIC label using operand as the number. */
2994 if (GET_CODE (x) != CONST_INT)
2995 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2997 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3001 /* Print 'u' if the operand is a update load/store. */
3002 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3007 /* If value is 0, print gr0, otherwise it must be a register. */
3008 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3009 fputs (reg_names[GPR_R0], file);
3011 else if (GET_CODE (x) == REG)
3012 fputs (reg_names [REGNO (x)], file);
3015 fatal_insn ("Bad insn in frv_print_operand, z case", x);
3019 /* Print constant in hex. */
3020 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3022 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3029 if (GET_CODE (x) == REG)
3030 fputs (reg_names [REGNO (x)], file);
3032 else if (GET_CODE (x) == CONST_INT
3033 || GET_CODE (x) == CONST_DOUBLE)
3034 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3036 else if (frv_const_unspec_p (x, &unspec))
3037 frv_output_const_unspec (file, &unspec);
3039 else if (GET_CODE (x) == MEM)
3040 frv_print_operand_address (file, XEXP (x, 0));
3042 else if (CONSTANT_ADDRESS_P (x))
3043 frv_print_operand_address (file, x);
3046 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3051 fatal_insn ("frv_print_operand: unknown code", x);
3059 /* A C statement (sans semicolon) for initializing the variable CUM for the
3060 state at the beginning of the argument list. The variable has type
3061 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3062 of the function which will receive the args, or 0 if the args are to a
3063 compiler support library function. The value of INDIRECT is nonzero when
3064 processing an indirect call, for example a call through a function pointer.
3065 The value of INDIRECT is zero for a call to an explicitly named function, a
3066 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3067 arguments for the function being compiled.
3069 When processing a call to a compiler support library function, LIBNAME
3070 identifies which one. It is a `symbol_ref' rtx which contains the name of
3071 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3072 being processed. Thus, each time this macro is called, either LIBNAME or
3073 FNTYPE is nonzero, but never both of them at once. */
3076 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3082 *cum = FIRST_ARG_REGNUM;
3084 if (TARGET_DEBUG_ARG)
3086 fprintf (stderr, "\ninit_cumulative_args:");
3087 if (!fndecl && fntype)
3088 fputs (" indirect", stderr);
3091 fputs (" incoming", stderr);
3095 tree ret_type = TREE_TYPE (fntype);
3096 fprintf (stderr, " return=%s,",
3097 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3100 if (libname && GET_CODE (libname) == SYMBOL_REF)
3101 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3103 if (cfun->returns_struct)
3104 fprintf (stderr, " return-struct");
3106 putc ('\n', stderr);
3111 /* Return true if we should pass an argument on the stack rather than
3115 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3117 if (mode == BLKmode)
3121 return AGGREGATE_TYPE_P (type);
3124 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3125 argument with the specified mode and type. If it is not defined,
3126 `PARM_BOUNDARY' is used for all arguments. */
3129 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3130 tree type ATTRIBUTE_UNUSED)
3132 return BITS_PER_WORD;
3136 frv_function_arg (CUMULATIVE_ARGS *cum,
3137 enum machine_mode mode,
3138 tree type ATTRIBUTE_UNUSED,
3140 int incoming ATTRIBUTE_UNUSED)
3142 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3147 /* Return a marker for use in the call instruction. */
3148 if (xmode == VOIDmode)
3154 else if (arg_num <= LAST_ARG_REGNUM)
3156 ret = gen_rtx_REG (xmode, arg_num);
3157 debstr = reg_names[arg_num];
3166 if (TARGET_DEBUG_ARG)
3168 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3169 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3175 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3176 advance past an argument in the argument list. The values MODE, TYPE and
3177 NAMED describe that argument. Once this is done, the variable CUM is
3178 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3180 This macro need not do anything if the argument in question was passed on
3181 the stack. The compiler knows how to track the amount of stack space used
3182 for arguments without any special help. */
3185 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3186 enum machine_mode mode,
3187 tree type ATTRIBUTE_UNUSED,
3190 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3191 int bytes = GET_MODE_SIZE (xmode);
3192 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3195 *cum = arg_num + words;
3197 if (TARGET_DEBUG_ARG)
3199 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3200 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3204 /* A C expression for the number of words, at the beginning of an argument,
3205 must be put in registers. The value must be zero for arguments that are
3206 passed entirely in registers or that are entirely pushed on the stack.
3208 On some machines, certain arguments must be passed partially in registers
3209 and partially in memory. On these machines, typically the first N words of
3210 arguments are passed in registers, and the rest on the stack. If a
3211 multi-word argument (a `double' or a structure) crosses that boundary, its
3212 first few words must be passed in registers and the rest must be pushed.
3213 This macro tells the compiler when this occurs, and how many of the words
3214 should go in registers.
3216 `FUNCTION_ARG' for these arguments should return the first register to be
3217 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3218 the called function. */
3221 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3222 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3224 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3225 int bytes = GET_MODE_SIZE (xmode);
3226 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3230 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3231 ? LAST_ARG_REGNUM - arg_num + 1
3233 ret *= UNITS_PER_WORD;
3235 if (TARGET_DEBUG_ARG && ret)
3236 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3242 /* Return true if a register is ok to use as a base or index register. */
3244 static FRV_INLINE int
3245 frv_regno_ok_for_base_p (int regno, int strict_p)
3251 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3253 if (regno == ARG_POINTER_REGNUM)
3256 return (regno >= FIRST_PSEUDO_REGISTER);
3260 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3261 RTX) is a legitimate memory address on the target machine for a memory
3262 operand of mode MODE.
3264 It usually pays to define several simpler macros to serve as subroutines for
3265 this one. Otherwise it may be too complicated to understand.
3267 This macro must exist in two variants: a strict variant and a non-strict
3268 one. The strict variant is used in the reload pass. It must be defined so
3269 that any pseudo-register that has not been allocated a hard register is
3270 considered a memory reference. In contexts where some kind of register is
3271 required, a pseudo-register with no hard register must be rejected.
3273 The non-strict variant is used in other passes. It must be defined to
3274 accept all pseudo-registers in every context where some kind of register is
3277 Compiler source files that want to use the strict variant of this macro
3278 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3279 conditional to define the strict variant in that case and the non-strict
3282 Subroutines to check for acceptable registers for various purposes (one for
3283 base registers, one for index registers, and so on) are typically among the
3284 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3285 subroutine macros need have two variants; the higher levels of macros may be
3286 the same whether strict or not.
3288 Normally, constant addresses which are the sum of a `symbol_ref' and an
3289 integer are stored inside a `const' RTX to mark them as constant.
3290 Therefore, there is no need to recognize such sums specifically as
3291 legitimate addresses. Normally you would simply recognize any `const' as
3294 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3295 are not marked with `const'. It assumes that a naked `plus' indicates
3296 indexing. If so, then you *must* reject such naked constant sums as
3297 illegitimate addresses, so that none of them will be given to
3298 `PRINT_OPERAND_ADDRESS'.
3300 On some machines, whether a symbolic address is legitimate depends on the
3301 section that the address refers to. On these machines, define the macro
3302 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3303 then check for it here. When you see a `const', you will have to look
3304 inside it to find the `symbol_ref' in order to determine the section.
3306 The best way to modify the name string is by adding text to the beginning,
3307 with suitable punctuation to prevent any ambiguity. Allocate the new name
3308 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3309 remove and decode the added text and output the name accordingly, and define
3310 `(* targetm.strip_name_encoding)' to access the original name string.
3312 You can check the information stored here into the `symbol_ref' in the
3313 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3314 `PRINT_OPERAND_ADDRESS'. */
3317 frv_legitimate_address_p (enum machine_mode mode,
3321 int allow_double_reg_p)
3325 HOST_WIDE_INT value;
3328 if (FRV_SYMBOL_REF_TLS_P (x))
3331 switch (GET_CODE (x))
3338 if (GET_CODE (x) != REG)
3344 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3350 if (GET_CODE (x0) != REG
3351 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3352 || GET_CODE (x1) != PLUS
3353 || ! rtx_equal_p (x0, XEXP (x1, 0))
3354 || GET_CODE (XEXP (x1, 1)) != REG
3355 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3362 /* 12 bit immediate */
3367 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3369 /* If we can't use load/store double operations, make sure we can
3370 address the second word. */
3371 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3372 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3381 if (GET_CODE (x0) == SUBREG)
3382 x0 = SUBREG_REG (x0);
3384 if (GET_CODE (x0) != REG)
3387 regno0 = REGNO (x0);
3388 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3391 switch (GET_CODE (x1))
3397 x1 = SUBREG_REG (x1);
3398 if (GET_CODE (x1) != REG)
3404 /* Do not allow reg+reg addressing for modes > 1 word if we
3405 can't depend on having move double instructions. */
3406 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3409 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3413 /* 12 bit immediate */
3418 value = INTVAL (x1);
3419 ret = IN_RANGE_P (value, -2048, 2047);
3421 /* If we can't use load/store double operations, make sure we can
3422 address the second word. */
3423 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3424 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3429 if (!condexec_p && got12_operand (x1, VOIDmode))
3437 if (TARGET_DEBUG_ADDR)
3439 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3440 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3441 (condexec_p) ? ", inside conditional code" : "");
3448 /* Given an ADDR, generate code to inline the PLT. */
3450 gen_inlined_tls_plt (rtx addr)
3452 rtx mem, retval, dest;
3453 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3456 dest = gen_reg_rtx (DImode);
3463 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3464 calll #gettlsoff(ADDR)@(gr8, gr0)
3466 emit_insn (gen_tls_lddi (dest, addr, picreg));
3473 sethi.p #gottlsdeschi(ADDR), gr8
3474 setlo #gottlsdesclo(ADDR), gr8
3475 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3476 calll #gettlsoff(ADDR)@(gr8, gr0)
3478 rtx reguse = gen_reg_rtx (Pmode);
3479 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3480 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3483 retval = gen_reg_rtx (Pmode);
3484 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3488 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3489 the destination address. */
3491 gen_tlsmoff (rtx addr, rtx reg)
3493 rtx dest = gen_reg_rtx (Pmode);
3497 /* sethi.p #tlsmoffhi(x), grA
3498 setlo #tlsmofflo(x), grA
3500 dest = gen_reg_rtx (Pmode);
3501 emit_insn (gen_tlsoff_hilo (dest, addr,
3502 GEN_INT (R_FRV_TLSMOFFHI)));
3503 dest = gen_rtx_PLUS (Pmode, dest, reg);
3507 /* addi grB, #tlsmoff12(x), grC
3509 ld/st @(grB, #tlsmoff12(x)), grC
3511 dest = gen_reg_rtx (Pmode);
3512 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3513 GEN_INT (R_FRV_TLSMOFF12)));
3518 /* Generate code for a TLS address. */
3520 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3522 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3523 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3527 case TLS_MODEL_INITIAL_EXEC:
3531 ldi @(gr15, #gottlsoff12(x)), gr5
3533 dest = gen_reg_rtx (Pmode);
3534 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3535 dest = gen_rtx_PLUS (Pmode, tp, dest);
3539 /* -fPIC or anything else.
3541 sethi.p #gottlsoffhi(x), gr14
3542 setlo #gottlsofflo(x), gr14
3543 ld #tlsoff(x)@(gr15, gr14), gr9
3545 rtx tmp = gen_reg_rtx (Pmode);
3546 dest = gen_reg_rtx (Pmode);
3547 emit_insn (gen_tlsoff_hilo (tmp, addr,
3548 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3550 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3551 dest = gen_rtx_PLUS (Pmode, tp, dest);
3554 case TLS_MODEL_LOCAL_DYNAMIC:
3558 if (TARGET_INLINE_PLT)
3559 retval = gen_inlined_tls_plt (GEN_INT (0));
3562 /* call #gettlsoff(0) */
3563 retval = gen_reg_rtx (Pmode);
3564 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3567 reg = gen_reg_rtx (Pmode);
3568 emit_insn (gen_rtx_SET (VOIDmode, reg,
3569 gen_rtx_PLUS (Pmode,
3572 dest = gen_tlsmoff (addr, reg);
3575 dest = gen_reg_rtx (Pmode);
3576 emit_insn (gen_tlsoff_hilo (dest, addr,
3577 GEN_INT (R_FRV_TLSMOFFHI)));
3578 dest = gen_rtx_PLUS (Pmode, dest, reg);
3582 case TLS_MODEL_LOCAL_EXEC:
3583 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3585 case TLS_MODEL_GLOBAL_DYNAMIC:
3589 if (TARGET_INLINE_PLT)
3590 retval = gen_inlined_tls_plt (addr);
3593 /* call #gettlsoff(x) */
3594 retval = gen_reg_rtx (Pmode);
3595 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3597 dest = gen_rtx_PLUS (Pmode, retval, tp);
3608 frv_legitimize_address (rtx x,
3609 rtx oldx ATTRIBUTE_UNUSED,
3610 enum machine_mode mode ATTRIBUTE_UNUSED)
3612 if (GET_CODE (x) == SYMBOL_REF)
3614 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3616 return frv_legitimize_tls_address (x, model);
3622 /* Test whether a local function descriptor is canonical, i.e.,
3623 whether we can use FUNCDESC_GOTOFF to compute the address of the
3627 frv_local_funcdesc_p (rtx fnx)
3630 enum symbol_visibility vis;
3633 if (! SYMBOL_REF_LOCAL_P (fnx))
3636 fn = SYMBOL_REF_DECL (fnx);
3641 vis = DECL_VISIBILITY (fn);
3643 if (vis == VISIBILITY_PROTECTED)
3644 /* Private function descriptors for protected functions are not
3645 canonical. Temporarily change the visibility to global. */
3646 vis = VISIBILITY_DEFAULT;
3647 else if (flag_shlib)
3648 /* If we're already compiling for a shared library (that, unlike
3649 executables, can't assume that the existence of a definition
3650 implies local binding), we can skip the re-testing. */
3653 ret = default_binds_local_p_1 (fn, flag_pic);
3655 DECL_VISIBILITY (fn) = vis;
3660 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3664 frv_gen_GPsym2reg (rtx dest, rtx src)
3666 tree gp = get_identifier ("_gp");
3667 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3669 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3673 unspec_got_name (int i)
3677 case R_FRV_GOT12: return "got12";
3678 case R_FRV_GOTHI: return "gothi";
3679 case R_FRV_GOTLO: return "gotlo";
3680 case R_FRV_FUNCDESC: return "funcdesc";
3681 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3682 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3683 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3684 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3685 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3686 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3687 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3688 case R_FRV_GOTOFF12: return "gotoff12";
3689 case R_FRV_GOTOFFHI: return "gotoffhi";
3690 case R_FRV_GOTOFFLO: return "gotofflo";
3691 case R_FRV_GPREL12: return "gprel12";
3692 case R_FRV_GPRELHI: return "gprelhi";
3693 case R_FRV_GPRELLO: return "gprello";
3694 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3695 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3696 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3697 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3698 case R_FRV_TLSMOFF12: return "tlsmoff12";
3699 case R_FRV_TLSDESCHI: return "tlsdeschi";
3700 case R_FRV_TLSDESCLO: return "tlsdesclo";
3701 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3702 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3707 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3708 is added inside the relocation operator. */
3711 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3713 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3714 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3715 fputs (")", stream);
3718 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3719 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3720 otherwise return ORIG_X. */
3723 frv_find_base_term (rtx x)
3725 struct frv_unspec unspec;
3727 if (frv_const_unspec_p (x, &unspec)
3728 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3729 return plus_constant (unspec.symbol, unspec.offset);
3734 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3735 the operand is used by a predicated instruction. */
3738 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3740 return ((GET_MODE (op) == mode || mode == VOIDmode)
3741 && GET_CODE (op) == MEM
3742 && frv_legitimate_address_p (mode, XEXP (op, 0),
3743 reload_completed, condexec_p, FALSE));
3747 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3749 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3750 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3756 rvrtx = operands[0];
3760 addr = XEXP (operands[0], 0);
3762 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3763 any calls that would involve a PLT, but can't tell, since we
3764 don't know whether an extern function is going to be provided by
3765 a separate translation unit or imported from a separate module.
3766 When compiling for shared libraries, if the function has default
3767 visibility, we assume it's overridable, so we inline the PLT, but
3768 for executables, we don't really have a way to make a good
3769 decision: a function is as likely to be imported from a shared
3770 library as it is to be defined in the executable itself. We
3771 assume executables will get global functions defined locally,
3772 whereas shared libraries will have them potentially overridden,
3773 so we only inline PLTs when compiling for shared libraries.
3775 In order to mark a function as local to a shared library, any
3776 non-default visibility attribute suffices. Unfortunately,
3777 there's no simple way to tag a function declaration as ``in a
3778 different module'', which we could then use to trigger PLT
3779 inlining on executables. There's -minline-plt, but it affects
3780 all external functions, so one would have to also mark function
3781 declarations available in the same module with non-default
3782 visibility, which is advantageous in itself. */
3783 if (GET_CODE (addr) == SYMBOL_REF
3784 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3788 dest = gen_reg_rtx (SImode);
3790 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3791 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3793 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3794 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3796 cfun->uses_pic_offset_table = TRUE;
3799 else if (GET_CODE (addr) == SYMBOL_REF)
3801 /* These are always either local, or handled through a local
3804 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3805 operands[2], picreg, lr);
3807 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3811 else if (! ldd_address_operand (addr, Pmode))
3812 addr = force_reg (Pmode, addr);
3814 picreg = gen_reg_rtx (DImode);
3815 emit_insn (gen_movdi_ldd (picreg, addr));
3817 if (sibcall && ret_value)
3818 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3820 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3822 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3824 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3828 /* An address operand that may use a pair of registers, an addressing
3829 mode that we reject in general. */
3832 ldd_address_operand (rtx x, enum machine_mode mode)
3834 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3837 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3841 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3843 if (GET_MODE (op) != mode && mode != VOIDmode)
3845 if (GET_CODE (op) != REG)
3847 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3852 /* Return 1 is OP is a memory operand, or will be turned into one by
3856 frv_load_operand (rtx op, enum machine_mode mode)
3858 if (GET_MODE (op) != mode && mode != VOIDmode)
3861 if (reload_in_progress)
3864 if (GET_CODE (tmp) == SUBREG)
3865 tmp = SUBREG_REG (tmp);
3866 if (GET_CODE (tmp) == REG
3867 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3868 op = reg_equiv_memory_loc[REGNO (tmp)];
3871 return op && memory_operand (op, mode);
3875 /* Return 1 if operand is a GPR register or a FPR register. */
3878 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3882 if (GET_MODE (op) != mode && mode != VOIDmode)
3885 if (GET_CODE (op) == SUBREG)
3887 if (GET_CODE (SUBREG_REG (op)) != REG)
3888 return register_operand (op, mode);
3890 op = SUBREG_REG (op);
3893 if (GET_CODE (op) != REG)
3897 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3903 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3906 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3908 if (GET_CODE (op) == CONST_INT)
3909 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3911 if (got12_operand (op, mode))
3914 if (GET_MODE (op) != mode && mode != VOIDmode)
3917 if (GET_CODE (op) == SUBREG)
3919 if (GET_CODE (SUBREG_REG (op)) != REG)
3920 return register_operand (op, mode);
3922 op = SUBREG_REG (op);
3925 if (GET_CODE (op) != REG)
3928 return GPR_OR_PSEUDO_P (REGNO (op));
3931 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3932 signed immediate. */
3935 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3939 if (GET_CODE (op) == CONST_INT)
3940 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3942 if (GET_MODE (op) != mode && mode != VOIDmode)
3945 if (GET_CODE (op) == SUBREG)
3947 if (GET_CODE (SUBREG_REG (op)) != REG)
3948 return register_operand (op, mode);
3950 op = SUBREG_REG (op);
3953 if (GET_CODE (op) != REG)
3957 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3963 /* Return 1 if operand is a register or 6 bit signed immediate. */
3966 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3968 if (GET_CODE (op) == CONST_INT)
3969 return IN_RANGE_P (INTVAL (op), -32, 31);
3971 if (GET_MODE (op) != mode && mode != VOIDmode)
3974 if (GET_CODE (op) == SUBREG)
3976 if (GET_CODE (SUBREG_REG (op)) != REG)
3977 return register_operand (op, mode);
3979 op = SUBREG_REG (op);
3982 if (GET_CODE (op) != REG)
3985 return FPR_OR_PSEUDO_P (REGNO (op));
3988 /* Return 1 if operand is a register or 10 bit signed immediate. */
3991 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3993 if (GET_CODE (op) == CONST_INT)
3994 return IN_RANGE_P (INTVAL (op), -512, 511);
3996 if (GET_MODE (op) != mode && mode != VOIDmode)
3999 if (GET_CODE (op) == SUBREG)
4001 if (GET_CODE (SUBREG_REG (op)) != REG)
4002 return register_operand (op, mode);
4004 op = SUBREG_REG (op);
4007 if (GET_CODE (op) != REG)
4010 return GPR_OR_PSEUDO_P (REGNO (op));
4013 /* Return 1 if operand is a register or an integer immediate. */
4016 gpr_or_int_operand (rtx op, enum machine_mode mode)
4018 if (GET_CODE (op) == CONST_INT)
4021 if (GET_MODE (op) != mode && mode != VOIDmode)
4024 if (GET_CODE (op) == SUBREG)
4026 if (GET_CODE (SUBREG_REG (op)) != REG)
4027 return register_operand (op, mode);
4029 op = SUBREG_REG (op);
4032 if (GET_CODE (op) != REG)
4035 return GPR_OR_PSEUDO_P (REGNO (op));
4038 /* Return 1 if operand is a 12 bit signed immediate. */
4041 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4043 if (GET_CODE (op) != CONST_INT)
4046 return IN_RANGE_P (INTVAL (op), -2048, 2047);
4049 /* Return 1 if operand is a 6 bit signed immediate. */
4052 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4054 if (GET_CODE (op) != CONST_INT)
4057 return IN_RANGE_P (INTVAL (op), -32, 31);
4060 /* Return 1 if operand is a 5 bit signed immediate. */
4063 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4065 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
4068 /* Return 1 if operand is a 5 bit unsigned immediate. */
4071 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4073 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
4076 /* Return 1 if operand is a 4 bit unsigned immediate. */
4079 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4081 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
4084 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
4087 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4089 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
4092 /* Return 1 if operand is an integer constant that takes 2 instructions
4093 to load up and can be split into sethi/setlo instructions.. */
4096 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4098 HOST_WIDE_INT value;
4102 switch (GET_CODE (op))
4111 return (flag_pic == 0);
4114 if (flag_pic || TARGET_FDPIC)
4118 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
4120 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
4126 /* small data references are already 1 word */
4127 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
4130 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
4133 if (GET_MODE (op) == SFmode)
4135 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4136 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4138 return ! IN_RANGE_P (value, -32768, 32767);
4140 else if (GET_MODE (op) == VOIDmode)
4142 value = CONST_DOUBLE_LOW (op);
4143 return ! IN_RANGE_P (value, -32768, 32767);
4151 /* Return 1 if operand is a 16 bit unsigned immediate. */
4154 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4156 if (GET_CODE (op) != CONST_INT)
4159 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
4162 /* Return 1 if operand is an integer constant with the bottom 16 bits
4166 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4168 if (GET_CODE (op) != CONST_INT)
4171 return ((INTVAL (op) & 0xffff) == 0);
4174 /* Return true if operand is a GPR register. */
4177 integer_register_operand (rtx op, enum machine_mode mode)
4179 if (GET_MODE (op) != mode && mode != VOIDmode)
4182 if (GET_CODE (op) == SUBREG)
4184 if (GET_CODE (SUBREG_REG (op)) != REG)
4185 return register_operand (op, mode);
4187 op = SUBREG_REG (op);
4190 if (GET_CODE (op) != REG)
4193 return GPR_OR_PSEUDO_P (REGNO (op));
4196 /* Return true if operand is a GPR register. Do not allow SUBREG's
4197 here, in order to prevent a combine bug. */
4200 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
4202 if (GET_MODE (op) != mode && mode != VOIDmode)
4205 if (GET_CODE (op) != REG)
4208 return GPR_OR_PSEUDO_P (REGNO (op));
4211 /* Return true if operand is a FPR register. */
4214 fpr_operand (rtx op, enum machine_mode mode)
4216 if (GET_MODE (op) != mode && mode != VOIDmode)
4219 if (GET_CODE (op) == SUBREG)
4221 if (GET_CODE (SUBREG_REG (op)) != REG)
4222 return register_operand (op, mode);
4224 op = SUBREG_REG (op);
4227 if (GET_CODE (op) != REG)
4230 return FPR_OR_PSEUDO_P (REGNO (op));
4233 /* Return true if operand is an even GPR or FPR register. */
4236 even_reg_operand (rtx op, enum machine_mode mode)
4240 if (GET_MODE (op) != mode && mode != VOIDmode)
4243 if (GET_CODE (op) == SUBREG)
4245 if (GET_CODE (SUBREG_REG (op)) != REG)
4246 return register_operand (op, mode);
4248 op = SUBREG_REG (op);
4251 if (GET_CODE (op) != REG)
4255 if (regno >= FIRST_PSEUDO_REGISTER)
4259 return (((regno - GPR_FIRST) & 1) == 0);
4262 return (((regno - FPR_FIRST) & 1) == 0);
4267 /* Return true if operand is an odd GPR register. */
4270 odd_reg_operand (rtx op, enum machine_mode mode)
4274 if (GET_MODE (op) != mode && mode != VOIDmode)
4277 if (GET_CODE (op) == SUBREG)
4279 if (GET_CODE (SUBREG_REG (op)) != REG)
4280 return register_operand (op, mode);
4282 op = SUBREG_REG (op);
4285 if (GET_CODE (op) != REG)
4289 /* Assume that reload will give us an even register. */
4290 if (regno >= FIRST_PSEUDO_REGISTER)
4294 return (((regno - GPR_FIRST) & 1) != 0);
4297 return (((regno - FPR_FIRST) & 1) != 0);
4302 /* Return true if operand is an even GPR register. */
4305 even_gpr_operand (rtx op, enum machine_mode mode)
4309 if (GET_MODE (op) != mode && mode != VOIDmode)
4312 if (GET_CODE (op) == SUBREG)
4314 if (GET_CODE (SUBREG_REG (op)) != REG)
4315 return register_operand (op, mode);
4317 op = SUBREG_REG (op);
4320 if (GET_CODE (op) != REG)
4324 if (regno >= FIRST_PSEUDO_REGISTER)
4327 if (! GPR_P (regno))
4330 return (((regno - GPR_FIRST) & 1) == 0);
4333 /* Return true if operand is an odd GPR register. */
4336 odd_gpr_operand (rtx op, enum machine_mode mode)
4340 if (GET_MODE (op) != mode && mode != VOIDmode)
4343 if (GET_CODE (op) == SUBREG)
4345 if (GET_CODE (SUBREG_REG (op)) != REG)
4346 return register_operand (op, mode);
4348 op = SUBREG_REG (op);
4351 if (GET_CODE (op) != REG)
4355 /* Assume that reload will give us an even register. */
4356 if (regno >= FIRST_PSEUDO_REGISTER)
4359 if (! GPR_P (regno))
4362 return (((regno - GPR_FIRST) & 1) != 0);
4365 /* Return true if operand is a quad aligned FPR register. */
4368 quad_fpr_operand (rtx op, enum machine_mode mode)
4372 if (GET_MODE (op) != mode && mode != VOIDmode)
4375 if (GET_CODE (op) == SUBREG)
4377 if (GET_CODE (SUBREG_REG (op)) != REG)
4378 return register_operand (op, mode);
4380 op = SUBREG_REG (op);
4383 if (GET_CODE (op) != REG)
4387 if (regno >= FIRST_PSEUDO_REGISTER)
4390 if (! FPR_P (regno))
4393 return (((regno - FPR_FIRST) & 3) == 0);
4396 /* Return true if operand is an even FPR register. */
4399 even_fpr_operand (rtx op, enum machine_mode mode)
4403 if (GET_MODE (op) != mode && mode != VOIDmode)
4406 if (GET_CODE (op) == SUBREG)
4408 if (GET_CODE (SUBREG_REG (op)) != REG)
4409 return register_operand (op, mode);
4411 op = SUBREG_REG (op);
4414 if (GET_CODE (op) != REG)
4418 if (regno >= FIRST_PSEUDO_REGISTER)
4421 if (! FPR_P (regno))
4424 return (((regno - FPR_FIRST) & 1) == 0);
4427 /* Return true if operand is an odd FPR register. */
4430 odd_fpr_operand (rtx op, enum machine_mode mode)
4434 if (GET_MODE (op) != mode && mode != VOIDmode)
4437 if (GET_CODE (op) == SUBREG)
4439 if (GET_CODE (SUBREG_REG (op)) != REG)
4440 return register_operand (op, mode);
4442 op = SUBREG_REG (op);
4445 if (GET_CODE (op) != REG)
4449 /* Assume that reload will give us an even register. */
4450 if (regno >= FIRST_PSEUDO_REGISTER)
4453 if (! FPR_P (regno))
4456 return (((regno - FPR_FIRST) & 1) != 0);
4459 /* Return true if operand is a 2 word memory address that can be loaded in one
4460 instruction to load or store. We assume the stack and frame pointers are
4461 suitably aligned, and variables in the small data area. FIXME -- at some we
4462 should recognize other globals and statics. We can't assume that any old
4463 pointer is aligned, given that arguments could be passed on an odd word on
4464 the stack and the address taken and passed through to another function. */
4467 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4475 if (GET_CODE (op) != MEM)
4478 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4481 addr = XEXP (op, 0);
4482 if (GET_CODE (addr) == REG)
4485 else if (GET_CODE (addr) == PLUS)
4487 rtx addr0 = XEXP (addr, 0);
4488 rtx addr1 = XEXP (addr, 1);
4490 if (GET_CODE (addr0) != REG)
4493 if (got12_operand (addr1, VOIDmode))
4496 if (GET_CODE (addr1) != CONST_INT)
4499 if ((INTVAL (addr1) & 7) != 0)
4508 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4514 /* Return true if operand is a 2 word memory address that needs to
4515 use two instructions to load or store. */
4518 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4520 if (GET_CODE (op) != MEM)
4523 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4529 return ! dbl_memory_one_insn_operand (op, mode);
4532 /* Return true if operand is something that can be an output for a move
4536 move_destination_operand (rtx op, enum machine_mode mode)
4541 switch (GET_CODE (op))
4547 if (GET_MODE (op) != mode && mode != VOIDmode)
4550 subreg = SUBREG_REG (op);
4551 code = GET_CODE (subreg);
4553 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4554 reload_completed, FALSE, FALSE);
4556 return (code == REG);
4559 if (GET_MODE (op) != mode && mode != VOIDmode)
4565 return frv_legitimate_memory_operand (op, mode, FALSE);
4571 /* Return true if we the operand is a valid destination for a movcc_fp
4572 instruction. This means rejecting fcc_operands, since we need
4573 scratch registers to write to them. */
4576 movcc_fp_destination_operand (rtx op, enum machine_mode mode)
4578 if (fcc_operand (op, mode))
4581 return move_destination_operand (op, mode);
4584 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4585 process these separately from any offsets, such that we add any
4586 offsets to the function descriptor (the actual pointer), not to the
4587 function address. */
4590 frv_function_symbol_referenced_p (rtx x)
4596 if (GET_CODE (x) == SYMBOL_REF)
4597 return SYMBOL_REF_FUNCTION_P (x);
4599 length = GET_RTX_LENGTH (GET_CODE (x));
4600 format = GET_RTX_FORMAT (GET_CODE (x));
4602 for (j = 0; j < length; ++j)
4607 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4613 if (XVEC (x, j) != 0)
4616 for (k = 0; k < XVECLEN (x, j); ++k)
4617 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4623 /* Nothing to do. */
4631 /* Return true if operand is something that can be an input for a move
4635 move_source_operand (rtx op, enum machine_mode mode)
4640 switch (GET_CODE (op))
4647 return immediate_operand (op, mode);
4650 if (GET_MODE (op) != mode && mode != VOIDmode)
4653 subreg = SUBREG_REG (op);
4654 code = GET_CODE (subreg);
4656 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4657 reload_completed, FALSE, FALSE);
4659 return (code == REG);
4662 if (GET_MODE (op) != mode && mode != VOIDmode)
4668 return frv_legitimate_memory_operand (op, mode, FALSE);
4674 /* Return true if operand is something that can be an output for a conditional
4678 condexec_dest_operand (rtx op, enum machine_mode mode)
4683 switch (GET_CODE (op))
4689 if (GET_MODE (op) != mode && mode != VOIDmode)
4692 subreg = SUBREG_REG (op);
4693 code = GET_CODE (subreg);
4695 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4696 reload_completed, TRUE, FALSE);
4698 return (code == REG);
4701 if (GET_MODE (op) != mode && mode != VOIDmode)
4707 return frv_legitimate_memory_operand (op, mode, TRUE);
4713 /* Return true if operand is something that can be an input for a conditional
4717 condexec_source_operand (rtx op, enum machine_mode mode)
4722 switch (GET_CODE (op))
4732 if (GET_MODE (op) != mode && mode != VOIDmode)
4735 subreg = SUBREG_REG (op);
4736 code = GET_CODE (subreg);
4738 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4739 reload_completed, TRUE, FALSE);
4741 return (code == REG);
4744 if (GET_MODE (op) != mode && mode != VOIDmode)
4750 return frv_legitimate_memory_operand (op, mode, TRUE);
4756 /* Return true if operand is a register of any flavor or a 0 of the
4757 appropriate type. */
4760 reg_or_0_operand (rtx op, enum machine_mode mode)
4762 switch (GET_CODE (op))
4769 if (GET_MODE (op) != mode && mode != VOIDmode)
4772 return register_operand (op, mode);
4782 /* Return true if operand is the link register. */
4785 lr_operand (rtx op, enum machine_mode mode)
4787 if (GET_CODE (op) != REG)
4790 if (GET_MODE (op) != mode && mode != VOIDmode)
4793 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4799 /* Return true if operand is the uClinux PIC register. */
4802 fdpic_operand (rtx op, enum machine_mode mode)
4807 if (GET_CODE (op) != REG)
4810 if (GET_MODE (op) != mode && mode != VOIDmode)
4813 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4820 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4822 struct frv_unspec unspec;
4824 if (frv_const_unspec_p (op, &unspec))
4825 switch (unspec.reloc)
4828 case R_FRV_GOTOFF12:
4829 case R_FRV_FUNCDESC_GOT12:
4830 case R_FRV_FUNCDESC_GOTOFF12:
4832 case R_FRV_TLSMOFF12:
4838 /* Return true if OP is a valid const-unspec expression. */
4841 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4843 struct frv_unspec unspec;
4845 return frv_const_unspec_p (op, &unspec);
4848 /* Return true if operand is a gpr register or a valid memory operand. */
4851 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4853 return (integer_register_operand (op, mode)
4854 || frv_legitimate_memory_operand (op, mode, FALSE));
4857 /* Return true if operand is a gpr register, a valid memory operand,
4858 or a memory operand that can be made valid using an additional gpr
4862 gpr_or_memory_operand_with_scratch (rtx op, enum machine_mode mode)
4866 if (gpr_or_memory_operand (op, mode))
4869 if (GET_CODE (op) != MEM)
4872 if (GET_MODE (op) != mode)
4875 addr = XEXP (op, 0);
4877 if (GET_CODE (addr) != PLUS)
4880 if (!integer_register_operand (XEXP (addr, 0), Pmode))
4883 if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
4889 /* Return true if operand is a fpr register or a valid memory operation. */
4892 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4894 return (fpr_operand (op, mode)
4895 || frv_legitimate_memory_operand (op, mode, FALSE));
4898 /* Return true if operand is an icc register. */
4901 icc_operand (rtx op, enum machine_mode mode)
4905 if (GET_MODE (op) != mode && mode != VOIDmode)
4908 if (GET_CODE (op) != REG)
4912 return ICC_OR_PSEUDO_P (regno);
4915 /* Return true if operand is an fcc register. */
4918 fcc_operand (rtx op, enum machine_mode mode)
4922 if (GET_MODE (op) != mode && mode != VOIDmode)
4925 if (GET_CODE (op) != REG)
4929 return FCC_OR_PSEUDO_P (regno);
4932 /* Return true if operand is either an fcc or icc register. */
4935 cc_operand (rtx op, enum machine_mode mode)
4939 if (GET_MODE (op) != mode && mode != VOIDmode)
4942 if (GET_CODE (op) != REG)
4946 if (CC_OR_PSEUDO_P (regno))
4952 /* Return true if operand is an integer CCR register. */
4955 icr_operand (rtx op, enum machine_mode mode)
4959 if (GET_MODE (op) != mode && mode != VOIDmode)
4962 if (GET_CODE (op) != REG)
4966 return ICR_OR_PSEUDO_P (regno);
4969 /* Return true if operand is an fcc register. */
4972 fcr_operand (rtx op, enum machine_mode mode)
4976 if (GET_MODE (op) != mode && mode != VOIDmode)
4979 if (GET_CODE (op) != REG)
4983 return FCR_OR_PSEUDO_P (regno);
4986 /* Return true if operand is either an fcc or icc register. */
4989 cr_operand (rtx op, enum machine_mode mode)
4993 if (GET_MODE (op) != mode && mode != VOIDmode)
4996 if (GET_CODE (op) != REG)
5000 if (CR_OR_PSEUDO_P (regno))
5006 /* Return true if operand is a memory reference suitable for a call. */
5009 call_operand (rtx op, enum machine_mode mode)
5011 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
5014 if (GET_CODE (op) == SYMBOL_REF)
5015 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
5017 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
5018 never occur anyway), but prevents reload from not handling the case
5019 properly of a call through a pointer on a function that calls
5020 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
5021 return gpr_or_int12_operand (op, mode);
5024 /* Return true if operand is a memory reference suitable for a sibcall. */
5027 sibcall_operand (rtx op, enum machine_mode mode)
5029 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
5032 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
5033 never occur anyway), but prevents reload from not handling the case
5034 properly of a call through a pointer on a function that calls
5035 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
5036 return gpr_or_int12_operand (op, mode);
5039 /* Returns 1 if OP is either a SYMBOL_REF or a constant. */
5041 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5043 enum rtx_code c = GET_CODE (op);
5047 /* Allow (const:SI (plus:SI (symbol_ref) (const_int))). */
5048 return GET_MODE (op) == SImode
5049 && GET_CODE (XEXP (op, 0)) == PLUS
5050 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
5051 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
5054 return c == SYMBOL_REF || c == CONST_INT;
5057 /* Return true if operator is a kind of relational operator. */
5060 relational_operator (rtx op, enum machine_mode mode)
5062 return (integer_relational_operator (op, mode)
5063 || float_relational_operator (op, mode));
5066 /* Return true if OP is a relational operator suitable for CCmode,
5067 CC_UNSmode or CC_NZmode. */
5070 integer_relational_operator (rtx op, enum machine_mode mode)
5072 if (mode != VOIDmode && mode != GET_MODE (op))
5075 /* The allowable relations depend on the mode of the ICC register. */
5076 switch (GET_CODE (op))
5085 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
5086 || GET_MODE (XEXP (op, 0)) == CCmode);
5090 return GET_MODE (XEXP (op, 0)) == CCmode;
5096 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
5097 || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
5101 /* Return true if operator is a floating point relational operator. */
5104 float_relational_operator (rtx op, enum machine_mode mode)
5106 if (mode != VOIDmode && mode != GET_MODE (op))
5109 switch (GET_CODE (op))
5124 return GET_MODE (XEXP (op, 0)) == CC_FPmode;
5128 /* Return true if operator is EQ/NE of a conditional execution register. */
5131 ccr_eqne_operator (rtx op, enum machine_mode mode)
5133 enum machine_mode op_mode = GET_MODE (op);
5138 if (mode != VOIDmode && op_mode != mode)
5141 switch (GET_CODE (op))
5152 if (op1 != const0_rtx)
5156 if (GET_CODE (op0) != REG)
5159 regno = REGNO (op0);
5160 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
5166 /* Return true if operator is a minimum or maximum operator (both signed and
5170 minmax_operator (rtx op, enum machine_mode mode)
5172 if (mode != VOIDmode && mode != GET_MODE (op))
5175 switch (GET_CODE (op))
5187 if (! integer_register_operand (XEXP (op, 0), mode))
5190 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5196 /* Return true if operator is an integer binary operator that can executed
5197 conditionally and takes 1 cycle. */
5200 condexec_si_binary_operator (rtx op, enum machine_mode mode)
5202 enum machine_mode op_mode = GET_MODE (op);
5204 if (mode != VOIDmode && op_mode != mode)
5207 switch (GET_CODE (op))
5224 /* Return true if operator is an integer binary operator that can be
5225 executed conditionally by a media instruction. */
5228 condexec_si_media_operator (rtx op, enum machine_mode mode)
5230 enum machine_mode op_mode = GET_MODE (op);
5232 if (mode != VOIDmode && op_mode != mode)
5235 switch (GET_CODE (op))
5247 /* Return true if operator is an integer division operator that can executed
5251 condexec_si_divide_operator (rtx op, enum machine_mode mode)
5253 enum machine_mode op_mode = GET_MODE (op);
5255 if (mode != VOIDmode && op_mode != mode)
5258 switch (GET_CODE (op))
5269 /* Return true if operator is an integer unary operator that can executed
5273 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5275 enum machine_mode op_mode = GET_MODE (op);
5277 if (mode != VOIDmode && op_mode != mode)
5280 switch (GET_CODE (op))
5291 /* Return true if operator is a conversion-type expression that can be
5292 evaluated conditionally by floating-point instructions. */
5295 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5297 enum machine_mode op_mode = GET_MODE (op);
5299 if (mode != VOIDmode && op_mode != mode)
5302 switch (GET_CODE (op))
5313 /* Return true if operator is an addition or subtraction expression.
5314 Such expressions can be evaluated conditionally by floating-point
5318 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5320 enum machine_mode op_mode = GET_MODE (op);
5322 if (mode != VOIDmode && op_mode != mode)
5325 switch (GET_CODE (op))
5336 /* Return true if the memory operand is one that can be conditionally
5340 condexec_memory_operand (rtx op, enum machine_mode mode)
5342 enum machine_mode op_mode = GET_MODE (op);
5345 if (mode != VOIDmode && op_mode != mode)
5360 if (GET_CODE (op) != MEM)
5363 addr = XEXP (op, 0);
5364 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5367 /* Return true if OP is an integer binary operator that can be combined
5368 with a (set ... (compare:CC_NZ ...)) pattern. */
5371 intop_compare_operator (rtx op, enum machine_mode mode)
5373 if (mode != VOIDmode && GET_MODE (op) != mode)
5376 switch (GET_CODE (op))
5388 return GET_MODE (op) == SImode;
5392 /* Return 1 if operand is a valid ACC register number. */
5395 acc_operand (rtx op, enum machine_mode mode)
5397 return ((mode == VOIDmode || mode == GET_MODE (op))
5398 && REG_P (op) && ACC_P (REGNO (op))
5399 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
5402 /* Return 1 if operand is a valid even ACC register number. */
5405 even_acc_operand (rtx op, enum machine_mode mode)
5407 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
5410 /* Return 1 if operand is zero or four. */
5413 quad_acc_operand (rtx op, enum machine_mode mode)
5415 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
5418 /* Return 1 if operand is a valid ACCG register number. */
5421 accg_operand (rtx op, enum machine_mode mode)
5423 return ((mode == VOIDmode || mode == GET_MODE (op))
5424 && REG_P (op) && ACCG_P (REGNO (op))
5425 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
5429 /* Return true if the bare return instruction can be used outside of the
5430 epilog code. For frv, we only do it if there was no stack allocation. */
5433 direct_return_p (void)
5437 if (!reload_completed)
5440 info = frv_stack_info ();
5441 return (info->total_size == 0);
5446 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
5448 if (GET_CODE (src) == SYMBOL_REF)
5450 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
5452 src = frv_legitimize_tls_address (src, model);
5458 if (frv_emit_movsi (dest, src))
5467 if (!reload_in_progress
5468 && !reload_completed
5469 && !register_operand (dest, mode)
5470 && !reg_or_0_operand (src, mode))
5471 src = copy_to_mode_reg (mode, src);
5478 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
5481 /* Emit code to handle a MOVSI, adding in the small data register or pic
5482 register if needed to load up addresses. Return TRUE if the appropriate
5483 instructions are emitted. */
5486 frv_emit_movsi (rtx dest, rtx src)
5488 int base_regno = -1;
5491 struct frv_unspec old_unspec;
5493 if (!reload_in_progress
5494 && !reload_completed
5495 && !register_operand (dest, SImode)
5496 && (!reg_or_0_operand (src, SImode)
5497 /* Virtual registers will almost always be replaced by an
5498 add instruction, so expose this to CSE by copying to
5499 an intermediate register. */
5500 || (GET_CODE (src) == REG
5501 && IN_RANGE_P (REGNO (src),
5502 FIRST_VIRTUAL_REGISTER,
5503 LAST_VIRTUAL_REGISTER))))
5505 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5509 /* Explicitly add in the PIC or small data register if needed. */
5510 switch (GET_CODE (src))
5519 /* Using GPREL12, we use a single GOT entry for all symbols
5520 in read-only sections, but trade sequences such as:
5522 sethi #gothi(label), gr#
5523 setlo #gotlo(label), gr#
5528 ld @(gr15,#got12(_gp)), gr#
5529 sethi #gprelhi(label), gr##
5530 setlo #gprello(label), gr##
5533 We may often be able to share gr# for multiple
5534 computations of GPREL addresses, and we may often fold
5535 the final add into the pair of registers of a load or
5536 store instruction, so it's often profitable. Even when
5537 optimizing for size, we're trading a GOT entry for an
5538 additional instruction, which trades GOT space
5539 (read-write) for code size (read-only, shareable), as
5540 long as the symbol is not used in more than two different
5543 With -fpie/-fpic, we'd be trading a single load for a
5544 sequence of 4 instructions, because the offset of the
5545 label can't be assumed to be addressable with 12 bits, so
5546 we don't do this. */
5547 if (TARGET_GPREL_RO)
5548 unspec = R_FRV_GPREL12;
5550 unspec = R_FRV_GOT12;
5553 base_regno = PIC_REGNO;
5558 if (frv_const_unspec_p (src, &old_unspec))
5561 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5564 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5565 emit_move_insn (dest, src);
5570 sym = XEXP (sym, 0);
5571 if (GET_CODE (sym) == PLUS
5572 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5573 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5574 sym = XEXP (sym, 0);
5575 if (GET_CODE (sym) == SYMBOL_REF)
5577 else if (GET_CODE (sym) == LABEL_REF)
5580 goto handle_whatever;
5588 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
5592 src = frv_legitimize_tls_address (src, model);
5593 emit_move_insn (dest, src);
5597 if (SYMBOL_REF_FUNCTION_P (sym))
5599 if (frv_local_funcdesc_p (sym))
5600 unspec = R_FRV_FUNCDESC_GOTOFF12;
5602 unspec = R_FRV_FUNCDESC_GOT12;
5606 if (CONSTANT_POOL_ADDRESS_P (sym))
5607 switch (GET_CODE (get_pool_constant (sym)))
5614 unspec = R_FRV_GOTOFF12;
5619 if (TARGET_GPREL_RO)
5620 unspec = R_FRV_GPREL12;
5622 unspec = R_FRV_GOT12;
5625 else if (SYMBOL_REF_LOCAL_P (sym)
5626 && !SYMBOL_REF_EXTERNAL_P (sym)
5627 && SYMBOL_REF_DECL (sym)
5628 && (!DECL_P (SYMBOL_REF_DECL (sym))
5629 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5631 tree decl = SYMBOL_REF_DECL (sym);
5632 tree init = TREE_CODE (decl) == VAR_DECL
5633 ? DECL_INITIAL (decl)
5634 : TREE_CODE (decl) == CONSTRUCTOR
5637 bool named_section, readonly;
5639 if (init && init != error_mark_node)
5640 reloc = compute_reloc_for_constant (init);
5642 named_section = TREE_CODE (decl) == VAR_DECL
5643 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5644 readonly = decl_readonly_section (decl, reloc);
5647 unspec = R_FRV_GOT12;
5649 unspec = R_FRV_GOTOFF12;
5650 else if (readonly && TARGET_GPREL_RO)
5651 unspec = R_FRV_GPREL12;
5653 unspec = R_FRV_GOT12;
5656 unspec = R_FRV_GOT12;
5660 else if (SYMBOL_REF_SMALL_P (sym))
5661 base_regno = SDA_BASE_REG;
5664 base_regno = PIC_REGNO;
5669 if (base_regno >= 0)
5671 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5672 emit_insn (gen_symGOTOFF2reg (dest, src,
5673 gen_rtx_REG (Pmode, base_regno),
5674 GEN_INT (R_FRV_GPREL12)));
5676 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5677 gen_rtx_REG (Pmode, base_regno),
5678 GEN_INT (R_FRV_GPREL12)));
5679 if (base_regno == PIC_REGNO)
5680 cfun->uses_pic_offset_table = TRUE;
5688 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5689 new uses of it once reload has begun. */
5690 if (reload_in_progress || reload_completed)
5695 case R_FRV_GOTOFF12:
5696 if (!frv_small_data_reloc_p (sym, unspec))
5697 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5700 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5703 if (!frv_small_data_reloc_p (sym, unspec))
5704 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5707 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5709 case R_FRV_FUNCDESC_GOTOFF12:
5711 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5714 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5718 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5721 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5725 cfun->uses_pic_offset_table = TRUE;
5734 /* Return a string to output a single word move. */
5737 output_move_single (rtx operands[], rtx insn)
5739 rtx dest = operands[0];
5740 rtx src = operands[1];
5742 if (GET_CODE (dest) == REG)
5744 int dest_regno = REGNO (dest);
5745 enum machine_mode mode = GET_MODE (dest);
5747 if (GPR_P (dest_regno))
5749 if (GET_CODE (src) == REG)
5751 /* gpr <- some sort of register */
5752 int src_regno = REGNO (src);
5754 if (GPR_P (src_regno))
5755 return "mov %1, %0";
5757 else if (FPR_P (src_regno))
5758 return "movfg %1, %0";
5760 else if (SPR_P (src_regno))
5761 return "movsg %1, %0";
5764 else if (GET_CODE (src) == MEM)
5773 return "ldsb%I1%U1 %M1,%0";
5776 return "ldsh%I1%U1 %M1,%0";
5780 return "ld%I1%U1 %M1, %0";
5784 else if (GET_CODE (src) == CONST_INT
5785 || GET_CODE (src) == CONST_DOUBLE)
5787 /* gpr <- integer/floating constant */
5788 HOST_WIDE_INT value;
5790 if (GET_CODE (src) == CONST_INT)
5791 value = INTVAL (src);
5793 else if (mode == SFmode)
5798 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5799 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5804 value = CONST_DOUBLE_LOW (src);
5806 if (IN_RANGE_P (value, -32768, 32767))
5807 return "setlos %1, %0";
5812 else if (GET_CODE (src) == SYMBOL_REF
5813 || GET_CODE (src) == LABEL_REF
5814 || GET_CODE (src) == CONST)
5820 else if (FPR_P (dest_regno))
5822 if (GET_CODE (src) == REG)
5824 /* fpr <- some sort of register */
5825 int src_regno = REGNO (src);
5827 if (GPR_P (src_regno))
5828 return "movgf %1, %0";
5830 else if (FPR_P (src_regno))
5832 if (TARGET_HARD_FLOAT)
5833 return "fmovs %1, %0";
5835 return "mor %1, %1, %0";
5839 else if (GET_CODE (src) == MEM)
5848 return "ldbf%I1%U1 %M1,%0";
5851 return "ldhf%I1%U1 %M1,%0";
5855 return "ldf%I1%U1 %M1, %0";
5859 else if (ZERO_P (src))
5860 return "movgf %., %0";
5863 else if (SPR_P (dest_regno))
5865 if (GET_CODE (src) == REG)
5867 /* spr <- some sort of register */
5868 int src_regno = REGNO (src);
5870 if (GPR_P (src_regno))
5871 return "movgs %1, %0";
5873 else if (ZERO_P (src))
5874 return "movgs %., %0";
5878 else if (GET_CODE (dest) == MEM)
5880 if (GET_CODE (src) == REG)
5882 int src_regno = REGNO (src);
5883 enum machine_mode mode = GET_MODE (dest);
5885 if (GPR_P (src_regno))
5893 return "stb%I0%U0 %1, %M0";
5896 return "sth%I0%U0 %1, %M0";
5900 return "st%I0%U0 %1, %M0";
5904 else if (FPR_P (src_regno))
5912 return "stbf%I0%U0 %1, %M0";
5915 return "sthf%I0%U0 %1, %M0";
5919 return "stf%I0%U0 %1, %M0";
5924 else if (ZERO_P (src))
5926 switch (GET_MODE (dest))
5932 return "stb%I0%U0 %., %M0";
5935 return "sth%I0%U0 %., %M0";
5939 return "st%I0%U0 %., %M0";
5944 fatal_insn ("Bad output_move_single operand", insn);
5949 /* Return a string to output a double word move. */
5952 output_move_double (rtx operands[], rtx insn)
5954 rtx dest = operands[0];
5955 rtx src = operands[1];
5956 enum machine_mode mode = GET_MODE (dest);
5958 if (GET_CODE (dest) == REG)
5960 int dest_regno = REGNO (dest);
5962 if (GPR_P (dest_regno))
5964 if (GET_CODE (src) == REG)
5966 /* gpr <- some sort of register */
5967 int src_regno = REGNO (src);
5969 if (GPR_P (src_regno))
5972 else if (FPR_P (src_regno))
5974 if (((dest_regno - GPR_FIRST) & 1) == 0
5975 && ((src_regno - FPR_FIRST) & 1) == 0)
5976 return "movfgd %1, %0";
5982 else if (GET_CODE (src) == MEM)
5985 if (dbl_memory_one_insn_operand (src, mode))
5986 return "ldd%I1%U1 %M1, %0";
5991 else if (GET_CODE (src) == CONST_INT
5992 || GET_CODE (src) == CONST_DOUBLE)
5996 else if (FPR_P (dest_regno))
5998 if (GET_CODE (src) == REG)
6000 /* fpr <- some sort of register */
6001 int src_regno = REGNO (src);
6003 if (GPR_P (src_regno))
6005 if (((dest_regno - FPR_FIRST) & 1) == 0
6006 && ((src_regno - GPR_FIRST) & 1) == 0)
6007 return "movgfd %1, %0";
6012 else if (FPR_P (src_regno))
6015 && ((dest_regno - FPR_FIRST) & 1) == 0
6016 && ((src_regno - FPR_FIRST) & 1) == 0)
6017 return "fmovd %1, %0";
6023 else if (GET_CODE (src) == MEM)
6026 if (dbl_memory_one_insn_operand (src, mode))
6027 return "lddf%I1%U1 %M1, %0";
6032 else if (ZERO_P (src))
6037 else if (GET_CODE (dest) == MEM)
6039 if (GET_CODE (src) == REG)
6041 int src_regno = REGNO (src);
6043 if (GPR_P (src_regno))
6045 if (((src_regno - GPR_FIRST) & 1) == 0
6046 && dbl_memory_one_insn_operand (dest, mode))
6047 return "std%I0%U0 %1, %M0";
6052 if (FPR_P (src_regno))
6054 if (((src_regno - FPR_FIRST) & 1) == 0
6055 && dbl_memory_one_insn_operand (dest, mode))
6056 return "stdf%I0%U0 %1, %M0";
6062 else if (ZERO_P (src))
6064 if (dbl_memory_one_insn_operand (dest, mode))
6065 return "std%I0%U0 %., %M0";
6071 fatal_insn ("Bad output_move_double operand", insn);
6076 /* Return a string to output a single word conditional move.
6077 Operand0 -- EQ/NE of ccr register and 0
6078 Operand1 -- CCR register
6079 Operand2 -- destination
6080 Operand3 -- source */
6083 output_condmove_single (rtx operands[], rtx insn)
6085 rtx dest = operands[2];
6086 rtx src = operands[3];
6088 if (GET_CODE (dest) == REG)
6090 int dest_regno = REGNO (dest);
6091 enum machine_mode mode = GET_MODE (dest);
6093 if (GPR_P (dest_regno))
6095 if (GET_CODE (src) == REG)
6097 /* gpr <- some sort of register */
6098 int src_regno = REGNO (src);
6100 if (GPR_P (src_regno))
6101 return "cmov %z3, %2, %1, %e0";
6103 else if (FPR_P (src_regno))
6104 return "cmovfg %3, %2, %1, %e0";
6107 else if (GET_CODE (src) == MEM)
6116 return "cldsb%I3%U3 %M3, %2, %1, %e0";
6119 return "cldsh%I3%U3 %M3, %2, %1, %e0";
6123 return "cld%I3%U3 %M3, %2, %1, %e0";
6127 else if (ZERO_P (src))
6128 return "cmov %., %2, %1, %e0";
6131 else if (FPR_P (dest_regno))
6133 if (GET_CODE (src) == REG)
6135 /* fpr <- some sort of register */
6136 int src_regno = REGNO (src);
6138 if (GPR_P (src_regno))
6139 return "cmovgf %3, %2, %1, %e0";
6141 else if (FPR_P (src_regno))
6143 if (TARGET_HARD_FLOAT)
6144 return "cfmovs %3,%2,%1,%e0";
6146 return "cmor %3, %3, %2, %1, %e0";
6150 else if (GET_CODE (src) == MEM)
6153 if (mode == SImode || mode == SFmode)
6154 return "cldf%I3%U3 %M3, %2, %1, %e0";
6157 else if (ZERO_P (src))
6158 return "cmovgf %., %2, %1, %e0";
6162 else if (GET_CODE (dest) == MEM)
6164 if (GET_CODE (src) == REG)
6166 int src_regno = REGNO (src);
6167 enum machine_mode mode = GET_MODE (dest);
6169 if (GPR_P (src_regno))
6177 return "cstb%I2%U2 %3, %M2, %1, %e0";
6180 return "csth%I2%U2 %3, %M2, %1, %e0";
6184 return "cst%I2%U2 %3, %M2, %1, %e0";
6188 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
6189 return "cstf%I2%U2 %3, %M2, %1, %e0";
6192 else if (ZERO_P (src))
6194 enum machine_mode mode = GET_MODE (dest);
6201 return "cstb%I2%U2 %., %M2, %1, %e0";
6204 return "csth%I2%U2 %., %M2, %1, %e0";
6208 return "cst%I2%U2 %., %M2, %1, %e0";
6213 fatal_insn ("Bad output_condmove_single operand", insn);
6218 /* Emit the appropriate code to do a comparison, returning the register the
6219 comparison was done it. */
6222 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
6224 enum machine_mode cc_mode;
6227 /* Floating point doesn't have comparison against a constant. */
6228 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6229 op1 = force_reg (GET_MODE (op0), op1);
6231 /* Possibly disable using anything but a fixed register in order to work
6232 around cse moving comparisons past function calls. */
6233 cc_mode = SELECT_CC_MODE (test, op0, op1);
6234 cc_reg = ((TARGET_ALLOC_CC)
6235 ? gen_reg_rtx (cc_mode)
6236 : gen_rtx_REG (cc_mode,
6237 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6239 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6240 gen_rtx_COMPARE (cc_mode, op0, op1)));
6246 /* Emit code for a conditional branch. The comparison operands were previously
6247 stored in frv_compare_op0 and frv_compare_op1.
6249 XXX: I originally wanted to add a clobber of a CCR register to use in
6250 conditional execution, but that confuses the rest of the compiler. */
6253 frv_emit_cond_branch (enum rtx_code test, rtx label)
6258 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6259 enum machine_mode cc_mode = GET_MODE (cc_reg);
6261 /* Branches generate:
6263 (if_then_else (<test>, <cc_reg>, (const_int 0))
6264 (label_ref <branch_label>)
6266 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6267 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6268 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6269 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6274 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6275 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6278 frv_emit_scc (enum rtx_code test, rtx target)
6284 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6286 /* SCC instructions generate:
6287 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6288 (clobber (<ccr_reg>))]) */
6289 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6290 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6292 cr_reg = ((TARGET_ALLOC_CC)
6293 ? gen_reg_rtx (CC_CCRmode)
6294 : gen_rtx_REG (CC_CCRmode,
6295 ((GET_MODE (cc_reg) == CC_FPmode)
6299 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6300 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6305 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6306 the separate insns. */
6309 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6315 /* Set the appropriate CCR bit. */
6316 emit_insn (gen_rtx_SET (VOIDmode,
6318 gen_rtx_fmt_ee (GET_CODE (test),
6323 /* Move the value into the destination. */
6324 emit_move_insn (dest, GEN_INT (value));
6326 /* Move 0 into the destination if the test failed */
6327 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6328 gen_rtx_EQ (GET_MODE (cr_reg),
6331 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6333 /* Finish up, return sequence. */
6340 /* Emit the code for a conditional move, return TRUE if we could do the
6344 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6351 enum rtx_code test = GET_CODE (test_rtx);
6352 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6353 enum machine_mode cc_mode = GET_MODE (cc_reg);
6355 /* Conditional move instructions generate:
6356 (parallel [(set <target>
6357 (if_then_else (<test> <cc_reg> (const_int 0))
6360 (clobber (<ccr_reg>))]) */
6362 /* Handle various cases of conditional move involving two constants. */
6363 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6365 HOST_WIDE_INT value1 = INTVAL (src1);
6366 HOST_WIDE_INT value2 = INTVAL (src2);
6368 /* Having 0 as one of the constants can be done by loading the other
6369 constant, and optionally moving in gr0. */
6370 if (value1 == 0 || value2 == 0)
6373 /* If the first value is within an addi range and also the difference
6374 between the two fits in an addi's range, load up the difference, then
6375 conditionally move in 0, and then unconditionally add the first
6377 else if (IN_RANGE_P (value1, -2048, 2047)
6378 && IN_RANGE_P (value2 - value1, -2048, 2047))
6381 /* If neither condition holds, just force the constant into a
6385 src1 = force_reg (GET_MODE (dest), src1);
6386 src2 = force_reg (GET_MODE (dest), src2);
6390 /* If one value is a register, insure the other value is either 0 or a
6394 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6395 src1 = force_reg (GET_MODE (dest), src1);
6397 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6398 src2 = force_reg (GET_MODE (dest), src2);
6401 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6402 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6404 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6406 cr_reg = ((TARGET_ALLOC_CC)
6407 ? gen_reg_rtx (CC_CCRmode)
6408 : gen_rtx_REG (CC_CCRmode,
6409 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6411 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6412 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6417 /* Split a conditional move into constituent parts, returning a SEQUENCE
6418 containing all of the insns. */
6421 frv_split_cond_move (rtx operands[])
6423 rtx dest = operands[0];
6424 rtx test = operands[1];
6425 rtx cc_reg = operands[2];
6426 rtx src1 = operands[3];
6427 rtx src2 = operands[4];
6428 rtx cr_reg = operands[5];
6430 enum machine_mode cr_mode = GET_MODE (cr_reg);
6434 /* Set the appropriate CCR bit. */
6435 emit_insn (gen_rtx_SET (VOIDmode,
6437 gen_rtx_fmt_ee (GET_CODE (test),
6442 /* Handle various cases of conditional move involving two constants. */
6443 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6445 HOST_WIDE_INT value1 = INTVAL (src1);
6446 HOST_WIDE_INT value2 = INTVAL (src2);
6448 /* Having 0 as one of the constants can be done by loading the other
6449 constant, and optionally moving in gr0. */
6452 emit_move_insn (dest, src2);
6453 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6454 gen_rtx_NE (cr_mode, cr_reg,
6456 gen_rtx_SET (VOIDmode, dest, src1)));
6459 else if (value2 == 0)
6461 emit_move_insn (dest, src1);
6462 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6463 gen_rtx_EQ (cr_mode, cr_reg,
6465 gen_rtx_SET (VOIDmode, dest, src2)));
6468 /* If the first value is within an addi range and also the difference
6469 between the two fits in an addi's range, load up the difference, then
6470 conditionally move in 0, and then unconditionally add the first
6472 else if (IN_RANGE_P (value1, -2048, 2047)
6473 && IN_RANGE_P (value2 - value1, -2048, 2047))
6475 rtx dest_si = ((GET_MODE (dest) == SImode)
6477 : gen_rtx_SUBREG (SImode, dest, 0));
6479 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6480 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6481 gen_rtx_NE (cr_mode, cr_reg,
6483 gen_rtx_SET (VOIDmode, dest_si,
6485 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6493 /* Emit the conditional move for the test being true if needed. */
6494 if (! rtx_equal_p (dest, src1))
6495 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6496 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6497 gen_rtx_SET (VOIDmode, dest, src1)));
6499 /* Emit the conditional move for the test being false if needed. */
6500 if (! rtx_equal_p (dest, src2))
6501 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6502 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6503 gen_rtx_SET (VOIDmode, dest, src2)));
6506 /* Finish up, return sequence. */
6513 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6514 memory location that is not known to be dword-aligned. */
6516 frv_split_double_load (rtx dest, rtx source)
6518 int regno = REGNO (dest);
6519 rtx dest1 = gen_highpart (SImode, dest);
6520 rtx dest2 = gen_lowpart (SImode, dest);
6521 rtx address = XEXP (source, 0);
6523 /* If the address is pre-modified, load the lower-numbered register
6524 first, then load the other register using an integer offset from
6525 the modified base register. This order should always be safe,
6526 since the pre-modification cannot affect the same registers as the
6529 The situation for other loads is more complicated. Loading one
6530 of the registers could affect the value of ADDRESS, so we must
6531 be careful which order we do them in. */
6532 if (GET_CODE (address) == PRE_MODIFY
6533 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6535 /* It is safe to load the lower-numbered register first. */
6536 emit_move_insn (dest1, change_address (source, SImode, NULL));
6537 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6541 /* ADDRESS is not pre-modified and the address depends on the
6542 lower-numbered register. Load the higher-numbered register
6544 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6545 emit_move_insn (dest1, change_address (source, SImode, NULL));
6549 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6550 and SOURCE is either a double register or the constant zero. */
6552 frv_split_double_store (rtx dest, rtx source)
6554 rtx dest1 = change_address (dest, SImode, NULL);
6555 rtx dest2 = frv_index_memory (dest, SImode, 1);
6556 if (ZERO_P (source))
6558 emit_move_insn (dest1, CONST0_RTX (SImode));
6559 emit_move_insn (dest2, CONST0_RTX (SImode));
6563 emit_move_insn (dest1, gen_highpart (SImode, source));
6564 emit_move_insn (dest2, gen_lowpart (SImode, source));
6569 /* Split a min/max operation returning a SEQUENCE containing all of the
6573 frv_split_minmax (rtx operands[])
6575 rtx dest = operands[0];
6576 rtx minmax = operands[1];
6577 rtx src1 = operands[2];
6578 rtx src2 = operands[3];
6579 rtx cc_reg = operands[4];
6580 rtx cr_reg = operands[5];
6582 enum rtx_code test_code;
6583 enum machine_mode cr_mode = GET_MODE (cr_reg);
6587 /* Figure out which test to use. */
6588 switch (GET_CODE (minmax))
6593 case SMIN: test_code = LT; break;
6594 case SMAX: test_code = GT; break;
6595 case UMIN: test_code = LTU; break;
6596 case UMAX: test_code = GTU; break;
6599 /* Issue the compare instruction. */
6600 emit_insn (gen_rtx_SET (VOIDmode,
6602 gen_rtx_COMPARE (GET_MODE (cc_reg),
6605 /* Set the appropriate CCR bit. */
6606 emit_insn (gen_rtx_SET (VOIDmode,
6608 gen_rtx_fmt_ee (test_code,
6613 /* If are taking the min/max of a nonzero constant, load that first, and
6614 then do a conditional move of the other value. */
6615 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6617 if (rtx_equal_p (dest, src1))
6620 emit_move_insn (dest, src2);
6621 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6622 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6623 gen_rtx_SET (VOIDmode, dest, src1)));
6626 /* Otherwise, do each half of the move. */
6629 /* Emit the conditional move for the test being true if needed. */
6630 if (! rtx_equal_p (dest, src1))
6631 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6632 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6633 gen_rtx_SET (VOIDmode, dest, src1)));
6635 /* Emit the conditional move for the test being false if needed. */
6636 if (! rtx_equal_p (dest, src2))
6637 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6638 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6639 gen_rtx_SET (VOIDmode, dest, src2)));
6642 /* Finish up, return sequence. */
6649 /* Split an integer abs operation returning a SEQUENCE containing all of the
6653 frv_split_abs (rtx operands[])
6655 rtx dest = operands[0];
6656 rtx src = operands[1];
6657 rtx cc_reg = operands[2];
6658 rtx cr_reg = operands[3];
6663 /* Issue the compare < 0 instruction. */
6664 emit_insn (gen_rtx_SET (VOIDmode,
6666 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6668 /* Set the appropriate CCR bit. */
6669 emit_insn (gen_rtx_SET (VOIDmode,
6671 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6673 /* Emit the conditional negate if the value is negative. */
6674 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6675 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6676 gen_negsi2 (dest, src)));
6678 /* Emit the conditional move for the test being false if needed. */
6679 if (! rtx_equal_p (dest, src))
6680 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6681 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6682 gen_rtx_SET (VOIDmode, dest, src)));
6684 /* Finish up, return sequence. */
6691 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6692 register used in an insn. */
6695 frv_clear_registers_used (rtx *ptr, void *data)
6697 if (GET_CODE (*ptr) == REG)
6699 int regno = REGNO (*ptr);
6700 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6702 if (regno < FIRST_PSEUDO_REGISTER)
6704 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6706 while (regno < reg_max)
6708 CLEAR_HARD_REG_BIT (*p_regs, regno);
6718 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6720 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6721 initialize the static storage. */
6723 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6725 frv_ifcvt.added_insns_list = NULL_RTX;
6726 frv_ifcvt.cur_scratch_regs = 0;
6727 frv_ifcvt.num_nested_cond_exec = 0;
6728 frv_ifcvt.cr_reg = NULL_RTX;
6729 frv_ifcvt.nested_cc_reg = NULL_RTX;
6730 frv_ifcvt.extra_int_cr = NULL_RTX;
6731 frv_ifcvt.extra_fp_cr = NULL_RTX;
6732 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6736 /* Internal function to add a potential insn to the list of insns to be inserted
6737 if the conditional execution conversion is successful. */
6740 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6742 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6744 link->jump = before_p; /* Mark to add this before or after insn. */
6745 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6746 frv_ifcvt.added_insns_list);
6748 if (TARGET_DEBUG_COND_EXEC)
6751 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6752 (before_p) ? "before" : "after",
6753 (int)INSN_UID (insn));
6755 debug_rtx (pattern);
6760 /* A C expression to modify the code described by the conditional if
6761 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6762 FALSE_EXPR for converting if-then and if-then-else code to conditional
6763 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6764 tests cannot be converted. */
6767 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6769 basic_block test_bb = ce_info->test_bb; /* test basic block */
6770 basic_block then_bb = ce_info->then_bb; /* THEN */
6771 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6772 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6773 rtx true_expr = *p_true;
6777 enum machine_mode mode = GET_MODE (true_expr);
6781 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6783 rtx sub_cond_exec_reg;
6785 enum rtx_code code_true;
6786 enum rtx_code code_false;
6787 enum reg_class cc_class;
6788 enum reg_class cr_class;
6791 reg_set_iterator rsi;
6793 /* Make sure we are only dealing with hard registers. Also honor the
6794 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6796 if (!reload_completed || TARGET_NO_COND_EXEC
6797 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6800 /* Figure out which registers we can allocate for our own purposes. Only
6801 consider registers that are not preserved across function calls and are
6802 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6803 if we did not need to use them in reloading other registers. */
6804 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6805 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6806 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6807 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6808 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6810 /* If this is a nested IF, we need to discover whether the CC registers that
6811 are set/used inside of the block are used anywhere else. If not, we can
6812 change them to be the CC register that is paired with the CR register that
6813 controls the outermost IF block. */
6814 if (ce_info->pass > 1)
6816 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6817 for (j = CC_FIRST; j <= CC_LAST; j++)
6818 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6820 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6823 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6826 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6829 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6833 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6834 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6836 frv_ifcvt.added_insns_list = NULL_RTX;
6837 frv_ifcvt.cur_scratch_regs = 0;
6839 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6840 * sizeof (basic_block));
6846 /* Remove anything live at the beginning of the join block from being
6847 available for allocation. */
6848 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
6850 if (regno < FIRST_PSEUDO_REGISTER)
6851 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6855 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6857 if (ce_info->num_multiple_test_blocks)
6859 basic_block multiple_test_bb = ce_info->last_test_bb;
6861 while (multiple_test_bb != test_bb)
6863 bb[num_bb++] = multiple_test_bb;
6864 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
6868 /* Add in the THEN and ELSE blocks to be scanned. */
6869 bb[num_bb++] = then_bb;
6871 bb[num_bb++] = else_bb;
6873 sub_cond_exec_reg = NULL_RTX;
6874 frv_ifcvt.num_nested_cond_exec = 0;
6876 /* Scan all of the blocks for registers that must not be allocated. */
6877 for (j = 0; j < num_bb; j++)
6879 rtx last_insn = BB_END (bb[j]);
6880 rtx insn = BB_HEAD (bb[j]);
6884 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6885 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6887 (int) INSN_UID (BB_HEAD (bb[j])),
6888 (int) INSN_UID (BB_END (bb[j])));
6890 /* Anything live at the beginning of the block is obviously unavailable
6892 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
6894 if (regno < FIRST_PSEUDO_REGISTER)
6895 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6898 /* Loop through the insns in the block. */
6901 /* Mark any new registers that are created as being unavailable for
6902 allocation. Also see if the CC register used in nested IFs can be
6908 int skip_nested_if = FALSE;
6910 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6911 (void *)&tmp_reg->regs);
6913 pattern = PATTERN (insn);
6914 if (GET_CODE (pattern) == COND_EXEC)
6916 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6918 if (reg != sub_cond_exec_reg)
6920 sub_cond_exec_reg = reg;
6921 frv_ifcvt.num_nested_cond_exec++;
6925 set = single_set_pattern (pattern);
6928 rtx dest = SET_DEST (set);
6929 rtx src = SET_SRC (set);
6931 if (GET_CODE (dest) == REG)
6933 int regno = REGNO (dest);
6934 enum rtx_code src_code = GET_CODE (src);
6936 if (CC_P (regno) && src_code == COMPARE)
6937 skip_nested_if = TRUE;
6939 else if (CR_P (regno)
6940 && (src_code == IF_THEN_ELSE
6941 || COMPARISON_P (src)))
6942 skip_nested_if = TRUE;
6946 if (! skip_nested_if)
6947 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6948 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6951 if (insn == last_insn)
6954 insn = NEXT_INSN (insn);
6958 /* If this is a nested if, rewrite the CC registers that are available to
6959 include the ones that can be rewritten, to increase the chance of being
6960 able to allocate a paired CC/CR register combination. */
6961 if (ce_info->pass > 1)
6963 for (j = CC_FIRST; j <= CC_LAST; j++)
6964 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6965 SET_HARD_REG_BIT (tmp_reg->regs, j);
6967 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6973 fprintf (dump_file, "Available GPRs: ");
6975 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6976 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6978 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6979 if (++num_gprs > GPR_TEMP_NUM+2)
6983 fprintf (dump_file, "%s\nAvailable CRs: ",
6984 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6986 for (j = CR_FIRST; j <= CR_LAST; j++)
6987 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6988 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6990 fputs ("\n", dump_file);
6992 if (ce_info->pass > 1)
6994 fprintf (dump_file, "Modifiable CCs: ");
6995 for (j = CC_FIRST; j <= CC_LAST; j++)
6996 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6997 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6999 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
7000 frv_ifcvt.num_nested_cond_exec);
7004 /* Allocate the appropriate temporary condition code register. Try to
7005 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
7006 that conditional cmp's can be done. */
7007 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
7009 cr_class = ICR_REGS;
7010 cc_class = ICC_REGS;
7011 cc_first = ICC_FIRST;
7014 else if (mode == CC_FPmode)
7016 cr_class = FCR_REGS;
7017 cc_class = FCC_REGS;
7018 cc_first = FCC_FIRST;
7023 cc_first = cc_last = 0;
7024 cr_class = cc_class = NO_REGS;
7027 cc = XEXP (true_expr, 0);
7028 nested_cc = cr = NULL_RTX;
7029 if (cc_class != NO_REGS)
7031 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
7032 so we can execute a csubcc/caddcc/cfcmps instruction. */
7035 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
7037 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
7039 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
7040 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
7042 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
7043 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
7046 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
7047 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
7057 fprintf (dump_file, "Could not allocate a CR temporary register\n");
7064 "Will use %s for conditional execution, %s for nested comparisons\n",
7065 reg_names[ REGNO (cr)],
7066 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
7068 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
7069 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
7070 bit being true. We don't do this for floating point, because of NaNs. */
7071 code = GET_CODE (true_expr);
7072 if (GET_MODE (cc) != CC_FPmode)
7074 code = reverse_condition (code);
7084 check_insn = gen_rtx_SET (VOIDmode, cr,
7085 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
7087 /* Record the check insn to be inserted later. */
7088 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
7090 /* Update the tests. */
7091 frv_ifcvt.cr_reg = cr;
7092 frv_ifcvt.nested_cc_reg = nested_cc;
7093 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
7094 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
7097 /* Fail, don't do this conditional execution. */
7100 *p_false = NULL_RTX;
7102 fprintf (dump_file, "Disabling this conditional execution.\n");
7108 /* A C expression to modify the code described by the conditional if
7109 information CE_INFO, for the basic block BB, possibly updating the tests in
7110 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
7111 if-then-else code to conditional instructions. Set either TRUE_EXPR or
7112 FALSE_EXPR to a null pointer if the tests cannot be converted. */
7114 /* p_true and p_false are given expressions of the form:
7116 (and (eq:CC_CCR (reg:CC_CCR)
7122 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
7127 rtx old_true = XEXP (*p_true, 0);
7128 rtx old_false = XEXP (*p_false, 0);
7129 rtx true_expr = XEXP (*p_true, 1);
7130 rtx false_expr = XEXP (*p_false, 1);
7133 rtx cr = XEXP (old_true, 0);
7135 rtx new_cr = NULL_RTX;
7136 rtx *p_new_cr = (rtx *)0;
7140 enum reg_class cr_class;
7141 enum machine_mode mode = GET_MODE (true_expr);
7142 rtx (*logical_func)(rtx, rtx, rtx);
7144 if (TARGET_DEBUG_COND_EXEC)
7147 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7148 ce_info->and_and_p ? "&&" : "||");
7150 debug_rtx (*p_true);
7152 fputs ("\nfalse insn:\n", stderr);
7153 debug_rtx (*p_false);
7156 if (TARGET_NO_MULTI_CE)
7159 if (GET_CODE (cr) != REG)
7162 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
7164 cr_class = ICR_REGS;
7165 p_new_cr = &frv_ifcvt.extra_int_cr;
7167 else if (mode == CC_FPmode)
7169 cr_class = FCR_REGS;
7170 p_new_cr = &frv_ifcvt.extra_fp_cr;
7175 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7176 more &&/|| tests. */
7180 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7181 CC_CCRmode, TRUE, TRUE);
7186 if (ce_info->and_and_p)
7188 old_test = old_false;
7189 test_expr = true_expr;
7190 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7191 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7192 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7196 old_test = old_false;
7197 test_expr = false_expr;
7198 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7199 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7200 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7203 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7204 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7206 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
7208 /* Now add the conditional check insn. */
7209 cc = XEXP (test_expr, 0);
7210 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7211 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7213 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7215 /* Add the new check insn to the list of check insns that need to be
7217 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
7219 if (TARGET_DEBUG_COND_EXEC)
7221 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7224 debug_rtx (*p_true);
7226 fputs ("\nfalse insn:\n", stderr);
7227 debug_rtx (*p_false);
7233 *p_true = *p_false = NULL_RTX;
7235 /* If we allocated a CR register, release it. */
7238 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7239 *p_new_cr = NULL_RTX;
7242 if (TARGET_DEBUG_COND_EXEC)
7243 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7249 /* Return a register which will be loaded with a value if an IF block is
7250 converted to conditional execution. This is used to rewrite instructions
7251 that use constants to ones that just use registers. */
7254 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
7256 int num_alloc = frv_ifcvt.cur_scratch_regs;
7260 /* We know gr0 == 0, so replace any errant uses. */
7261 if (value == const0_rtx)
7262 return gen_rtx_REG (SImode, GPR_FIRST);
7264 /* First search all registers currently loaded to see if we have an
7265 applicable constant. */
7266 if (CONSTANT_P (value)
7267 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7269 for (i = 0; i < num_alloc; i++)
7271 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7272 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7276 /* Have we exhausted the number of registers available? */
7277 if (num_alloc >= GPR_TEMP_NUM)
7280 fprintf (dump_file, "Too many temporary registers allocated\n");
7285 /* Allocate the new register. */
7286 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7290 fputs ("Could not find a scratch register\n", dump_file);
7295 frv_ifcvt.cur_scratch_regs++;
7296 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7300 if (GET_CODE (value) == CONST_INT)
7301 fprintf (dump_file, "Register %s will hold %ld\n",
7302 reg_names[ REGNO (reg)], (long)INTVAL (value));
7304 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7305 fprintf (dump_file, "Register %s will hold LR\n",
7306 reg_names[ REGNO (reg)]);
7309 fprintf (dump_file, "Register %s will hold a saved value\n",
7310 reg_names[ REGNO (reg)]);
7317 /* Update a MEM used in conditional code that might contain an offset to put
7318 the offset into a scratch register, so that the conditional load/store
7319 operations can be used. This function returns the original pointer if the
7320 MEM is valid to use in conditional code, NULL if we can't load up the offset
7321 into a temporary register, or the new MEM if we were successful. */
7324 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7326 rtx addr = XEXP (mem, 0);
7328 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7330 if (GET_CODE (addr) == PLUS)
7332 rtx addr_op0 = XEXP (addr, 0);
7333 rtx addr_op1 = XEXP (addr, 1);
7335 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7337 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7341 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7348 else if (CONSTANT_P (addr))
7349 addr = frv_ifcvt_load_value (addr, insn);
7354 if (addr == NULL_RTX)
7357 else if (XEXP (mem, 0) != addr)
7358 return change_address (mem, mode, addr);
7365 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7366 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7369 single_set_pattern (rtx pattern)
7374 if (GET_CODE (pattern) == COND_EXEC)
7375 pattern = COND_EXEC_CODE (pattern);
7377 if (GET_CODE (pattern) == SET)
7380 else if (GET_CODE (pattern) == PARALLEL)
7382 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7384 rtx sub = XVECEXP (pattern, 0, i);
7386 switch (GET_CODE (sub))
7410 /* A C expression to modify the code described by the conditional if
7411 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7412 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7413 insn cannot be converted to be executed conditionally. */
7416 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7420 rtx orig_ce_pattern = pattern;
7426 if (GET_CODE (pattern) != COND_EXEC)
7429 test = COND_EXEC_TEST (pattern);
7430 if (GET_CODE (test) == AND)
7432 rtx cr = frv_ifcvt.cr_reg;
7435 op0 = XEXP (test, 0);
7436 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7439 op1 = XEXP (test, 1);
7440 test_reg = XEXP (op1, 0);
7441 if (GET_CODE (test_reg) != REG)
7444 /* Is this the first nested if block in this sequence? If so, generate
7445 an andcr or andncr. */
7446 if (! frv_ifcvt.last_nested_if_cr)
7450 frv_ifcvt.last_nested_if_cr = test_reg;
7451 if (GET_CODE (op0) == NE)
7452 and_op = gen_andcr (test_reg, cr, test_reg);
7454 and_op = gen_andncr (test_reg, cr, test_reg);
7456 frv_ifcvt_add_insn (and_op, insn, TRUE);
7459 /* If this isn't the first statement in the nested if sequence, see if we
7460 are dealing with the same register. */
7461 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7464 COND_EXEC_TEST (pattern) = test = op1;
7467 /* If this isn't a nested if, reset state variables. */
7470 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7473 set = single_set_pattern (pattern);
7476 rtx dest = SET_DEST (set);
7477 rtx src = SET_SRC (set);
7478 enum machine_mode mode = GET_MODE (dest);
7480 /* Check for normal binary operators. */
7481 if (mode == SImode && ARITHMETIC_P (src))
7483 op0 = XEXP (src, 0);
7484 op1 = XEXP (src, 1);
7486 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7488 op1 = frv_ifcvt_load_value (op1, insn);
7490 COND_EXEC_CODE (pattern)
7491 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7499 /* For multiply by a constant, we need to handle the sign extending
7500 correctly. Add a USE of the value after the multiply to prevent flow
7501 from cratering because only one register out of the two were used. */
7502 else if (mode == DImode && GET_CODE (src) == MULT)
7504 op0 = XEXP (src, 0);
7505 op1 = XEXP (src, 1);
7506 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7508 op1 = frv_ifcvt_load_value (op1, insn);
7511 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7512 COND_EXEC_CODE (pattern)
7513 = gen_rtx_SET (VOIDmode, dest,
7514 gen_rtx_MULT (DImode, op0, op1));
7520 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7523 /* If we are just loading a constant created for a nested conditional
7524 execution statement, just load the constant without any conditional
7525 execution, since we know that the constant will not interfere with any
7527 else if (frv_ifcvt.scratch_insns_bitmap
7528 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7530 && REG_P (SET_DEST (set))
7531 /* We must not unconditionally set a scratch reg chosen
7532 for a nested if-converted block if its incoming
7533 value from the TEST block (or the result of the THEN
7534 branch) could/should propagate to the JOIN block.
7535 It suffices to test whether the register is live at
7536 the JOIN point: if it's live there, we can infer
7537 that we set it in the former JOIN block of the
7538 nested if-converted block (otherwise it wouldn't
7539 have been available as a scratch register), and it
7540 is either propagated through or set in the other
7541 conditional block. It's probably not worth trying
7542 to catch the latter case, and it could actually
7543 limit scheduling of the combined block quite
7546 && ! (REGNO_REG_SET_P
7547 (ce_info->join_bb->global_live_at_start,
7548 REGNO (SET_DEST (set))))
7549 /* Similarly, we must not unconditionally set a reg
7550 used as scratch in the THEN branch if the same reg
7551 is live in the ELSE branch. */
7552 && (! ce_info->else_bb
7553 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7554 || ! (REGNO_REG_SET_P
7555 (ce_info->else_bb->global_live_at_start,
7556 REGNO (SET_DEST (set))))))
7559 else if (mode == QImode || mode == HImode || mode == SImode
7562 int changed_p = FALSE;
7564 /* Check for just loading up a constant */
7565 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7567 src = frv_ifcvt_load_value (src, insn);
7574 /* See if we need to fix up stores */
7575 if (GET_CODE (dest) == MEM)
7577 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7582 else if (new_mem != dest)
7589 /* See if we need to fix up loads */
7590 if (GET_CODE (src) == MEM)
7592 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7597 else if (new_mem != src)
7604 /* If either src or destination changed, redo SET. */
7606 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7609 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7610 rewriting the CC register to be the same as the paired CC/CR register
7612 else if (mode == CC_CCRmode && COMPARISON_P (src))
7614 int regno = REGNO (XEXP (src, 0));
7617 if (ce_info->pass > 1
7618 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7619 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7621 src = gen_rtx_fmt_ee (GET_CODE (src),
7623 frv_ifcvt.nested_cc_reg,
7627 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7628 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7631 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7632 else if (ce_info->pass > 1
7633 && GET_CODE (dest) == REG
7634 && CC_P (REGNO (dest))
7635 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7636 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7638 && GET_CODE (src) == COMPARE)
7640 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7641 COND_EXEC_CODE (pattern)
7642 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7646 if (TARGET_DEBUG_COND_EXEC)
7648 rtx orig_pattern = PATTERN (insn);
7650 PATTERN (insn) = pattern;
7652 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7656 PATTERN (insn) = orig_pattern;
7662 if (TARGET_DEBUG_COND_EXEC)
7664 rtx orig_pattern = PATTERN (insn);
7666 PATTERN (insn) = orig_ce_pattern;
7668 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7672 PATTERN (insn) = orig_pattern;
7679 /* A C expression to perform any final machine dependent modifications in
7680 converting code to conditional execution in the code described by the
7681 conditional if information CE_INFO. */
7684 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7688 rtx p = frv_ifcvt.added_insns_list;
7691 /* Loop inserting the check insns. The last check insn is the first test,
7692 and is the appropriate place to insert constants. */
7698 rtx check_and_insert_insns = XEXP (p, 0);
7701 check_insn = XEXP (check_and_insert_insns, 0);
7702 existing_insn = XEXP (check_and_insert_insns, 1);
7705 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7706 the existing insn, otherwise it is to be inserted AFTER. */
7707 if (check_and_insert_insns->jump)
7709 emit_insn_before (check_insn, existing_insn);
7710 check_and_insert_insns->jump = 0;
7713 emit_insn_after (check_insn, existing_insn);
7715 free_EXPR_LIST_node (check_and_insert_insns);
7716 free_EXPR_LIST_node (old_p);
7718 while (p != NULL_RTX);
7720 /* Load up any constants needed into temp gprs */
7721 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7723 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7724 if (! frv_ifcvt.scratch_insns_bitmap)
7725 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7726 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7727 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7730 frv_ifcvt.added_insns_list = NULL_RTX;
7731 frv_ifcvt.cur_scratch_regs = 0;
7735 /* A C expression to cancel any machine dependent modifications in converting
7736 code to conditional execution in the code described by the conditional if
7737 information CE_INFO. */
7740 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7743 rtx p = frv_ifcvt.added_insns_list;
7745 /* Loop freeing up the EXPR_LIST's allocated. */
7746 while (p != NULL_RTX)
7748 rtx check_and_jump = XEXP (p, 0);
7752 free_EXPR_LIST_node (check_and_jump);
7753 free_EXPR_LIST_node (old_p);
7756 /* Release any temporary gprs allocated. */
7757 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7758 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7760 frv_ifcvt.added_insns_list = NULL_RTX;
7761 frv_ifcvt.cur_scratch_regs = 0;
7765 /* A C expression for the size in bytes of the trampoline, as an integer.
7769 setlo #0, <static_chain>
7771 sethi #0, <static_chain>
7772 jmpl @(gr0,<jmp_reg>) */
7775 frv_trampoline_size (void)
7778 /* Allocate room for the function descriptor and the lddi
7781 return 5 /* instructions */ * 4 /* instruction size. */;
7785 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7786 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7787 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7788 should be passed to the function when it is called.
7793 setlo #0, <static_chain>
7795 sethi #0, <static_chain>
7796 jmpl @(gr0,<jmp_reg>) */
7799 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7801 rtx sc_reg = force_reg (Pmode, static_chain);
7803 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7806 GEN_INT (frv_trampoline_size ()), SImode,
7812 /* Many machines have some registers that cannot be copied directly to or from
7813 memory or even from other types of registers. An example is the `MQ'
7814 register, which on most machines, can only be copied to or from general
7815 registers, but not memory. Some machines allow copying all registers to and
7816 from memory, but require a scratch register for stores to some memory
7817 locations (e.g., those with symbolic address on the RT, and those with
7818 certain symbolic address on the SPARC when compiling PIC). In some cases,
7819 both an intermediate and a scratch register are required.
7821 You should define these macros to indicate to the reload phase that it may
7822 need to allocate at least one register for a reload in addition to the
7823 register to contain the data. Specifically, if copying X to a register
7824 CLASS in MODE requires an intermediate register, you should define
7825 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7826 whose registers can be used as intermediate registers or scratch registers.
7828 If copying a register CLASS in MODE to X requires an intermediate or scratch
7829 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7830 largest register class required. If the requirements for input and output
7831 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7832 instead of defining both macros identically.
7834 The values returned by these macros are often `GENERAL_REGS'. Return
7835 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7836 to or from a register of CLASS in MODE without requiring a scratch register.
7837 Do not define this macro if it would always return `NO_REGS'.
7839 If a scratch register is required (either with or without an intermediate
7840 register), you should define patterns for `reload_inM' or `reload_outM', as
7841 required.. These patterns, which will normally be implemented with a
7842 `define_expand', should be similar to the `movM' patterns, except that
7843 operand 2 is the scratch register.
7845 Define constraints for the reload register and scratch register that contain
7846 a single register class. If the original reload register (whose class is
7847 CLASS) can meet the constraint given in the pattern, the value returned by
7848 these macros is used for the class of the scratch register. Otherwise, two
7849 additional reload registers are required. Their classes are obtained from
7850 the constraints in the insn pattern.
7852 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7853 either be in a hard register or in memory. Use `true_regnum' to find out;
7854 it will return -1 if the pseudo is in memory and the hard register number if
7855 it is in a register.
7857 These macros should not be used in the case where a particular class of
7858 registers can only be copied to memory and not to another class of
7859 registers. In that case, secondary reload registers are not needed and
7860 would not be helpful. Instead, a stack location must be used to perform the
7861 copy and the `movM' pattern should use memory as an intermediate storage.
7862 This case often occurs between floating-point and general registers. */
7865 frv_secondary_reload_class (enum reg_class class,
7866 enum machine_mode mode ATTRIBUTE_UNUSED,
7868 int in_p ATTRIBUTE_UNUSED)
7878 /* Accumulators/Accumulator guard registers need to go through floating
7884 if (x && GET_CODE (x) == REG)
7886 int regno = REGNO (x);
7888 if (ACC_P (regno) || ACCG_P (regno))
7893 /* Nonzero constants should be loaded into an FPR through a GPR. */
7897 if (x && CONSTANT_P (x) && !ZERO_P (x))
7903 /* All of these types need gpr registers. */
7915 /* The accumulators need fpr registers */
7928 /* A C expression whose value is nonzero if pseudos that have been assigned to
7929 registers of class CLASS would likely be spilled because registers of CLASS
7930 are needed for spill registers.
7932 The default value of this macro returns 1 if CLASS has exactly one register
7933 and zero otherwise. On most machines, this default should be used. Only
7934 define this macro to some other expression if pseudo allocated by
7935 `local-alloc.c' end up in memory because their hard registers were needed
7936 for spill registers. If this macro returns nonzero for those classes, those
7937 pseudos will only be allocated by `global.c', which knows how to reallocate
7938 the pseudo to another register. If there would not be another register
7939 available for reallocation, you should not change the definition of this
7940 macro since the only effect of such a definition would be to slow down
7941 register allocation. */
7944 frv_class_likely_spilled_p (enum reg_class class)
7954 case FDPIC_FPTR_REGS:
7976 /* An expression for the alignment of a structure field FIELD if the
7977 alignment computed in the usual way is COMPUTED. GCC uses this
7978 value instead of the value in `BIGGEST_ALIGNMENT' or
7979 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7981 /* The definition type of the bit field data is either char, short, long or
7982 long long. The maximum bit size is the number of bits of its own type.
7984 The bit field data is assigned to a storage unit that has an adequate size
7985 for bit field data retention and is located at the smallest address.
7987 Consecutive bit field data are packed at consecutive bits having the same
7988 storage unit, with regard to the type, beginning with the MSB and continuing
7991 If a field to be assigned lies over a bit field type boundary, its
7992 assignment is completed by aligning it with a boundary suitable for the
7995 When a bit field having a bit length of 0 is declared, it is forcibly
7996 assigned to the next storage unit.
8009 &x 00000000 00000000 00000000 00000000
8012 &x+4 00000000 00000000 00000000 00000000
8015 &x+8 00000000 00000000 00000000 00000000
8018 &x+12 00000000 00000000 00000000 00000000
8024 frv_adjust_field_align (tree field, int computed)
8026 /* Make sure that the bitfield is not wider than the type. */
8027 if (DECL_BIT_FIELD (field)
8028 && !DECL_ARTIFICIAL (field))
8030 tree parent = DECL_CONTEXT (field);
8031 tree prev = NULL_TREE;
8034 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
8036 if (TREE_CODE (cur) != FIELD_DECL)
8045 /* If this isn't a :0 field and if the previous element is a bitfield
8046 also, see if the type is different, if so, we will need to align the
8047 bit-field to the next boundary. */
8049 && ! DECL_PACKED (field)
8050 && ! integer_zerop (DECL_SIZE (field))
8051 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
8053 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
8054 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
8055 computed = (prev_align > cur_align) ? prev_align : cur_align;
8063 /* A C expression that is nonzero if it is permissible to store a value of mode
8064 MODE in hard register number REGNO (or in several registers starting with
8065 that one). For a machine where all registers are equivalent, a suitable
8068 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
8070 It is not necessary for this macro to check for the numbers of fixed
8071 registers, because the allocation mechanism considers them to be always
8074 On some machines, double-precision values must be kept in even/odd register
8075 pairs. The way to implement that is to define this macro to reject odd
8076 register numbers for such modes.
8078 The minimum requirement for a mode to be OK in a register is that the
8079 `movMODE' instruction pattern support moves between the register and any
8080 other hard register for which the mode is OK; and that moving a value into
8081 the register and back out not alter it.
8083 Since the same instruction used to move `SImode' will work for all narrower
8084 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
8085 to distinguish between these modes, provided you define patterns `movhi',
8086 etc., to take advantage of this. This is useful because of the interaction
8087 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
8088 all integer modes to be tieable.
8090 Many machines have special registers for floating point arithmetic. Often
8091 people assume that floating point machine modes are allowed only in floating
8092 point registers. This is not true. Any registers that can hold integers
8093 can safely *hold* a floating point machine mode, whether or not floating
8094 arithmetic can be done on it in those registers. Integer move instructions
8095 can be used to move the values.
8097 On some machines, though, the converse is true: fixed-point machine modes
8098 may not go in floating registers. This is true if the floating registers
8099 normalize any value stored in them, because storing a non-floating value
8100 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
8101 fixed-point machine modes in floating registers. But if the floating
8102 registers do not automatically normalize, if you can store any bit pattern
8103 in one and retrieve it unchanged without a trap, then any machine mode may
8104 go in a floating register, so you can define this macro to say so.
8106 The primary significance of special floating registers is rather that they
8107 are the registers acceptable in floating point arithmetic instructions.
8108 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
8109 writing the proper constraints for those instructions.
8111 On some machines, the floating registers are especially slow to access, so
8112 that it is better to store a value in a stack frame than in such a register
8113 if floating point arithmetic is not being done. As long as the floating
8114 registers are not in class `GENERAL_REGS', they will not be used unless some
8115 pattern's constraint asks for one. */
8118 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
8128 return ICC_P (regno) || GPR_P (regno);
8131 return CR_P (regno) || GPR_P (regno);
8134 return FCC_P (regno) || GPR_P (regno);
8140 /* Set BASE to the first register in REGNO's class. Set MASK to the
8141 bits that must be clear in (REGNO - BASE) for the register to be
8143 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
8147 /* ACCGs store one byte. Two-byte quantities must start in
8148 even-numbered registers, four-byte ones in registers whose
8149 numbers are divisible by four, and so on. */
8151 mask = GET_MODE_SIZE (mode) - 1;
8155 /* The other registers store one word. */
8156 if (GPR_P (regno) || regno == AP_FIRST)
8159 else if (FPR_P (regno))
8162 else if (ACC_P (regno))
8165 else if (SPR_P (regno))
8166 return mode == SImode;
8168 /* Fill in the table. */
8172 /* Anything smaller than an SI is OK in any word-sized register. */
8173 if (GET_MODE_SIZE (mode) < 4)
8176 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8178 return (((regno - base) & mask) == 0);
8185 /* A C expression for the number of consecutive hard registers, starting at
8186 register number REGNO, required to hold a value of mode MODE.
8188 On a machine where all registers are exactly one word, a suitable definition
8191 #define HARD_REGNO_NREGS(REGNO, MODE) \
8192 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8193 / UNITS_PER_WORD)) */
8195 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8196 that we can build the appropriate instructions to properly reload the
8197 values. Also, make the byte-sized accumulator guards use one guard
8201 frv_hard_regno_nregs (int regno, enum machine_mode mode)
8204 return GET_MODE_SIZE (mode);
8206 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8210 /* A C expression for the maximum number of consecutive registers of
8211 class CLASS needed to hold a value of mode MODE.
8213 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8214 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8215 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8217 This macro helps control the handling of multiple-word values in
8220 This declaration is required. */
8223 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
8225 if (class == ACCG_REGS)
8226 /* An N-byte value requires N accumulator guards. */
8227 return GET_MODE_SIZE (mode);
8229 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8233 /* A C expression that is nonzero if X is a legitimate constant for an
8234 immediate operand on the target machine. You can assume that X satisfies
8235 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8236 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8239 frv_legitimate_constant_p (rtx x)
8241 enum machine_mode mode = GET_MODE (x);
8243 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8244 means that the move expanders will be expected to deal with most
8245 kinds of constant, regardless of what we return here.
8247 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8248 a constant can be entered into reg_equiv_constant[]. If we return true,
8249 reload can create new instances of the constant whenever it likes.
8251 The idea is therefore to accept as many constants as possible (to give
8252 reload more freedom) while rejecting constants that can only be created
8253 at certain times. In particular, anything with a symbolic component will
8254 require use of the pseudo FDPIC register, which is only available before
8257 return LEGITIMATE_PIC_OPERAND_P (x);
8259 /* All of the integer constants are ok. */
8260 if (GET_CODE (x) != CONST_DOUBLE)
8263 /* double integer constants are ok. */
8264 if (mode == VOIDmode || mode == DImode)
8267 /* 0 is always ok. */
8268 if (x == CONST0_RTX (mode))
8271 /* If floating point is just emulated, allow any constant, since it will be
8272 constructed in the GPRs. */
8273 if (!TARGET_HAS_FPRS)
8276 if (mode == DFmode && !TARGET_DOUBLE)
8279 /* Otherwise store the constant away and do a load. */
8283 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
8284 CC_NZ for comparisons against zero in which a single Z or N flag test
8285 is enough, CC_UNS for other unsigned comparisons, and CC for other
8286 signed comparisons. */
8289 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
8291 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
8300 return y == const0_rtx ? CC_NZmode : CCmode;
8306 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
8313 /* A C expression for the cost of moving data from a register in class FROM to
8314 one in class TO. The classes are expressed using the enumeration values
8315 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8316 interpreted relative to that.
8318 It is not required that the cost always equal 2 when FROM is the same as TO;
8319 on some machines it is expensive to move between registers if they are not
8322 If reload sees an insn consisting of a single `set' between two hard
8323 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8324 value of 2, reload does not check to ensure that the constraints of the insn
8325 are met. Setting a cost of other than 2 will allow reload to verify that
8326 the constraints are met. You should do this if the `movM' pattern's
8327 constraints do not allow such copying. */
8329 #define HIGH_COST 40
8330 #define MEDIUM_COST 3
8334 frv_register_move_cost (enum reg_class from, enum reg_class to)
8418 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8419 use ".picptr" to generate safe relocations for PIC code. We also
8420 need a fixup entry for aligned (non-debugging) code. */
8423 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8425 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8427 if (GET_CODE (value) == CONST
8428 || GET_CODE (value) == SYMBOL_REF
8429 || GET_CODE (value) == LABEL_REF)
8431 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8432 && SYMBOL_REF_FUNCTION_P (value))
8434 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8435 output_addr_const (asm_out_file, value);
8436 fputs (")\n", asm_out_file);
8439 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8440 && frv_function_symbol_referenced_p (value))
8442 if (aligned_p && !TARGET_FDPIC)
8444 static int label_num = 0;
8448 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8449 p = (* targetm.strip_name_encoding) (buf);
8451 fprintf (asm_out_file, "%s:\n", p);
8452 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8453 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8454 fprintf (asm_out_file, "\t.previous\n");
8456 assemble_integer_with_op ("\t.picptr\t", value);
8461 /* We've set the unaligned SI op to NULL, so we always have to
8462 handle the unaligned case here. */
8463 assemble_integer_with_op ("\t.4byte\t", value);
8467 return default_assemble_integer (value, size, aligned_p);
8470 /* Function to set up the backend function structure. */
8472 static struct machine_function *
8473 frv_init_machine_status (void)
8475 return ggc_alloc_cleared (sizeof (struct machine_function));
8478 /* Implement TARGET_SCHED_ISSUE_RATE. */
8481 frv_issue_rate (void)
8486 switch (frv_cpu_type)
8490 case FRV_CPU_SIMPLE:
8498 case FRV_CPU_GENERIC:
8500 case FRV_CPU_TOMCAT:
8508 /* A for_each_rtx callback. If X refers to an accumulator, return
8509 ACC_GROUP_ODD if the bit 2 of the register number is set and
8510 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
8514 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
8518 if (ACC_P (REGNO (*x)))
8519 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8520 if (ACCG_P (REGNO (*x)))
8521 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8526 /* Return the value of INSN's acc_group attribute. */
8529 frv_acc_group (rtx insn)
8531 /* This distinction only applies to the FR550 packing constraints. */
8532 if (frv_cpu_type != FRV_CPU_FR550)
8533 return ACC_GROUP_NONE;
8534 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
8537 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
8538 INSN will try to claim first. Since this value depends only on the
8539 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
8542 frv_insn_unit (rtx insn)
8544 enum attr_type type;
8546 type = get_attr_type (insn);
8547 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
8549 /* We haven't seen this type of instruction before. */
8553 /* Issue the instruction on its own to see which unit it prefers. */
8554 state = alloca (state_size ());
8555 state_reset (state);
8556 state_transition (state, insn);
8558 /* Find out which unit was taken. */
8559 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
8560 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
8563 if (unit == ARRAY_SIZE (frv_unit_codes))
8566 frv_type_to_unit[type] = unit;
8568 return frv_type_to_unit[type];
8571 /* Return true if INSN issues to a branch unit. */
8574 frv_issues_to_branch_unit_p (rtx insn)
8576 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
8579 /* The current state of the packing pass, implemented by frv_pack_insns. */
8581 /* The state of the pipeline DFA. */
8584 /* Which hardware registers are set within the current packet,
8585 and the conditions under which they are set. */
8586 regstate_t regstate[FIRST_PSEUDO_REGISTER];
8588 /* The memory locations that have been modified so far in this
8589 packet. MEM is the memref and COND is the regstate_t condition
8590 under which it is set. */
8596 /* The number of valid entries in MEMS. The value is larger than
8597 ARRAY_SIZE (mems) if there were too many mems to record. */
8598 unsigned int num_mems;
8600 /* The maximum number of instructions that can be packed together. */
8601 unsigned int issue_rate;
8603 /* The instructions in the packet, partitioned into groups. */
8604 struct frv_packet_group {
8605 /* How many instructions in the packet belong to this group. */
8606 unsigned int num_insns;
8608 /* A list of the instructions that belong to this group, in the order
8609 they appear in the rtl stream. */
8610 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8612 /* The contents of INSNS after they have been sorted into the correct
8613 assembly-language order. Element X issues to unit X. The list may
8614 contain extra nops. */
8615 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
8617 /* The member of frv_nops[] to use in sorted[]. */
8619 } groups[NUM_GROUPS];
8621 /* The instructions that make up the current packet. */
8622 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8623 unsigned int num_insns;
8626 /* Return the regstate_t flags for the given COND_EXEC condition.
8627 Abort if the condition isn't in the right form. */
8630 frv_cond_flags (rtx cond)
8632 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8633 && GET_CODE (XEXP (cond, 0)) == REG
8634 && CR_P (REGNO (XEXP (cond, 0)))
8635 && XEXP (cond, 1) == const0_rtx)
8636 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8637 | (GET_CODE (cond) == NE
8639 : REGSTATE_IF_FALSE));
8644 /* Return true if something accessed under condition COND2 can
8645 conflict with something written under condition COND1. */
8648 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
8650 /* If either reference was unconditional, we have a conflict. */
8651 if ((cond1 & REGSTATE_IF_EITHER) == 0
8652 || (cond2 & REGSTATE_IF_EITHER) == 0)
8655 /* The references might conflict if they were controlled by
8657 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
8660 /* They definitely conflict if they are controlled by the
8662 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
8669 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
8670 the current packet. DATA points to a regstate_t that describes the
8671 condition under which *X might be set or used. */
8674 frv_registers_conflict_p_1 (rtx *x, void *data)
8676 unsigned int regno, i;
8679 cond = *(regstate_t *) data;
8681 if (GET_CODE (*x) == REG)
8682 FOR_EACH_REGNO (regno, *x)
8683 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
8684 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
8687 if (GET_CODE (*x) == MEM)
8689 /* If we ran out of memory slots, assume a conflict. */
8690 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
8693 /* Check for output or true dependencies with earlier MEMs. */
8694 for (i = 0; i < frv_packet.num_mems; i++)
8695 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
8697 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
8701 if (output_dependence (frv_packet.mems[i].mem, *x))
8706 /* The return values of calls aren't significant: they describe
8707 the effect of the call as a whole, not of the insn itself. */
8708 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
8710 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
8715 /* Check subexpressions. */
8720 /* Return true if something in X might depend on an instruction
8721 in the current packet. */
8724 frv_registers_conflict_p (rtx x)
8729 if (GET_CODE (x) == COND_EXEC)
8731 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
8734 flags |= frv_cond_flags (XEXP (x, 0));
8737 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
8741 /* A note_stores callback. DATA points to the regstate_t condition
8742 under which X is modified. Update FRV_PACKET accordingly. */
8745 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8749 if (GET_CODE (x) == REG)
8750 FOR_EACH_REGNO (regno, x)
8751 frv_packet.regstate[regno] |= *(regstate_t *) data;
8753 if (GET_CODE (x) == MEM)
8755 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
8757 frv_packet.mems[frv_packet.num_mems].mem = x;
8758 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
8760 frv_packet.num_mems++;
8765 /* Update the register state information for an instruction whose
8769 frv_registers_update (rtx x)
8773 flags = REGSTATE_MODIFIED;
8774 if (GET_CODE (x) == COND_EXEC)
8776 flags |= frv_cond_flags (XEXP (x, 0));
8779 note_stores (x, frv_registers_update_1, &flags);
8783 /* Initialize frv_packet for the start of a new packet. */
8786 frv_start_packet (void)
8788 enum frv_insn_group group;
8790 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
8791 frv_packet.num_mems = 0;
8792 frv_packet.num_insns = 0;
8793 for (group = 0; group < NUM_GROUPS; group++)
8794 frv_packet.groups[group].num_insns = 0;
8798 /* Likewise for the start of a new basic block. */
8801 frv_start_packet_block (void)
8803 state_reset (frv_packet.dfa_state);
8804 frv_start_packet ();
8808 /* Finish the current packet, if any, and start a new one. Call
8809 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
8812 frv_finish_packet (void (*handle_packet) (void))
8814 if (frv_packet.num_insns > 0)
8817 state_transition (frv_packet.dfa_state, 0);
8818 frv_start_packet ();
8823 /* Return true if INSN can be added to the current packet. Update
8824 the DFA state on success. */
8827 frv_pack_insn_p (rtx insn)
8829 /* See if the packet is already as long as it can be. */
8830 if (frv_packet.num_insns == frv_packet.issue_rate)
8833 /* If the scheduler thought that an instruction should start a packet,
8834 it's usually a good idea to believe it. It knows much more about
8835 the latencies than we do.
8837 There are some exceptions though:
8839 - Conditional instructions are scheduled on the assumption that
8840 they will be executed. This is usually a good thing, since it
8841 tends to avoid unnecessary stalls in the conditional code.
8842 But we want to pack conditional instructions as tightly as
8843 possible, in order to optimize the case where they aren't
8846 - The scheduler will always put branches on their own, even
8847 if there's no real dependency.
8849 - There's no point putting a call in its own packet unless
8851 if (frv_packet.num_insns > 0
8852 && GET_CODE (insn) == INSN
8853 && GET_MODE (insn) == TImode
8854 && GET_CODE (PATTERN (insn)) != COND_EXEC)
8857 /* Check for register conflicts. Don't do this for setlo since any
8858 conflict will be with the partnering sethi, with which it can
8860 if (get_attr_type (insn) != TYPE_SETLO)
8861 if (frv_registers_conflict_p (PATTERN (insn)))
8864 return state_transition (frv_packet.dfa_state, insn) < 0;
8868 /* Add instruction INSN to the current packet. */
8871 frv_add_insn_to_packet (rtx insn)
8873 struct frv_packet_group *packet_group;
8875 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8876 packet_group->insns[packet_group->num_insns++] = insn;
8877 frv_packet.insns[frv_packet.num_insns++] = insn;
8879 frv_registers_update (PATTERN (insn));
8883 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
8884 packet ends in a branch or call, insert the nop before it, otherwise
8888 frv_insert_nop_in_packet (rtx insn)
8890 struct frv_packet_group *packet_group;
8893 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8894 last = frv_packet.insns[frv_packet.num_insns - 1];
8895 if (GET_CODE (last) != INSN)
8897 insn = emit_insn_before (PATTERN (insn), last);
8898 frv_packet.insns[frv_packet.num_insns - 1] = insn;
8899 frv_packet.insns[frv_packet.num_insns++] = last;
8903 insn = emit_insn_after (PATTERN (insn), last);
8904 frv_packet.insns[frv_packet.num_insns++] = insn;
8906 packet_group->insns[packet_group->num_insns++] = insn;
8910 /* If packing is enabled, divide the instructions into packets and
8911 return true. Call HANDLE_PACKET for each complete packet. */
8914 frv_for_each_packet (void (*handle_packet) (void))
8916 rtx insn, next_insn;
8918 frv_packet.issue_rate = frv_issue_rate ();
8920 /* Early exit if we don't want to pack insns. */
8922 || !flag_schedule_insns_after_reload
8923 || TARGET_NO_VLIW_BRANCH
8924 || frv_packet.issue_rate == 1)
8927 /* Set up the initial packing state. */
8929 frv_packet.dfa_state = alloca (state_size ());
8931 frv_start_packet_block ();
8932 for (insn = get_insns (); insn != 0; insn = next_insn)
8937 code = GET_CODE (insn);
8938 next_insn = NEXT_INSN (insn);
8940 if (code == CODE_LABEL)
8942 frv_finish_packet (handle_packet);
8943 frv_start_packet_block ();
8947 switch (GET_CODE (PATTERN (insn)))
8956 /* Calls mustn't be packed on a TOMCAT. */
8957 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
8958 frv_finish_packet (handle_packet);
8960 /* Since the last instruction in a packet determines the EH
8961 region, any exception-throwing instruction must come at
8962 the end of reordered packet. Insns that issue to a
8963 branch unit are bound to come last; for others it's
8964 too hard to predict. */
8965 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
8966 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
8967 frv_finish_packet (handle_packet);
8969 /* Finish the current packet if we can't add INSN to it.
8970 Simulate cycles until INSN is ready to issue. */
8971 if (!frv_pack_insn_p (insn))
8973 frv_finish_packet (handle_packet);
8974 while (!frv_pack_insn_p (insn))
8975 state_transition (frv_packet.dfa_state, 0);
8978 /* Add the instruction to the packet. */
8979 frv_add_insn_to_packet (insn);
8981 /* Calls and jumps end a packet, as do insns that throw
8983 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
8984 frv_finish_packet (handle_packet);
8988 frv_finish_packet (handle_packet);
8993 /* Subroutine of frv_sort_insn_group. We are trying to sort
8994 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
8995 language order. We have already picked a new position for
8996 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
8997 These instructions will occupy elements [0, LOWER_SLOT) and
8998 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
8999 the DFA state after issuing these instructions.
9001 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
9002 of the unused instructions. Return true if one such permutation gives
9003 a valid ordering, leaving the successful permutation in sorted[].
9004 Do not modify sorted[] until a valid permutation is found. */
9007 frv_sort_insn_group_1 (enum frv_insn_group group,
9008 unsigned int lower_slot, unsigned int upper_slot,
9009 unsigned int issued, unsigned int num_insns,
9012 struct frv_packet_group *packet_group;
9018 /* Early success if we've filled all the slots. */
9019 if (lower_slot == upper_slot)
9022 packet_group = &frv_packet.groups[group];
9023 dfa_size = state_size ();
9024 test_state = alloca (dfa_size);
9026 /* Try issuing each unused instruction. */
9027 for (i = num_insns - 1; i + 1 != 0; i--)
9028 if (~issued & (1 << i))
9030 insn = packet_group->sorted[i];
9031 memcpy (test_state, state, dfa_size);
9032 if (state_transition (test_state, insn) < 0
9033 && cpu_unit_reservation_p (test_state,
9034 NTH_UNIT (group, upper_slot - 1))
9035 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
9036 issued | (1 << i), num_insns,
9039 packet_group->sorted[upper_slot - 1] = insn;
9047 /* Compare two instructions by their frv_insn_unit. */
9050 frv_compare_insns (const void *first, const void *second)
9052 const rtx *insn1 = first, *insn2 = second;
9053 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
9056 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
9057 and sort it into assembly language order. See frv.md for a description of
9061 frv_sort_insn_group (enum frv_insn_group group)
9063 struct frv_packet_group *packet_group;
9064 unsigned int first, i, nop, max_unit, num_slots;
9065 state_t state, test_state;
9068 packet_group = &frv_packet.groups[group];
9070 /* Assume no nop is needed. */
9071 packet_group->nop = 0;
9073 if (packet_group->num_insns == 0)
9076 /* Copy insns[] to sorted[]. */
9077 memcpy (packet_group->sorted, packet_group->insns,
9078 sizeof (rtx) * packet_group->num_insns);
9080 /* Sort sorted[] by the unit that each insn tries to take first. */
9081 if (packet_group->num_insns > 1)
9082 qsort (packet_group->sorted, packet_group->num_insns,
9083 sizeof (rtx), frv_compare_insns);
9085 /* That's always enough for branch and control insns. */
9086 if (group == GROUP_B || group == GROUP_C)
9089 dfa_size = state_size ();
9090 state = alloca (dfa_size);
9091 test_state = alloca (dfa_size);
9093 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
9094 consecutively and such that the DFA takes unit X when sorted[X]
9095 is added. Set STATE to the new DFA state. */
9096 state_reset (test_state);
9097 for (first = 0; first < packet_group->num_insns; first++)
9099 memcpy (state, test_state, dfa_size);
9100 if (state_transition (test_state, packet_group->sorted[first]) >= 0
9101 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
9105 /* If all the instructions issued in ascending order, we're done. */
9106 if (first == packet_group->num_insns)
9109 /* Add nops to the end of sorted[] and try each permutation until
9110 we find one that works. */
9111 for (nop = 0; nop < frv_num_nops; nop++)
9113 max_unit = frv_insn_unit (frv_nops[nop]);
9114 if (frv_unit_groups[max_unit] == group)
9116 packet_group->nop = frv_nops[nop];
9117 num_slots = UNIT_NUMBER (max_unit) + 1;
9118 for (i = packet_group->num_insns; i < num_slots; i++)
9119 packet_group->sorted[i] = frv_nops[nop];
9120 if (frv_sort_insn_group_1 (group, first, num_slots,
9121 (1 << first) - 1, num_slots, state))
9128 /* Sort the current packet into assembly-language order. Set packing
9129 flags as appropriate. */
9132 frv_reorder_packet (void)
9134 unsigned int cursor[NUM_GROUPS];
9135 rtx insns[ARRAY_SIZE (frv_unit_groups)];
9136 unsigned int unit, to, from;
9137 enum frv_insn_group group;
9138 struct frv_packet_group *packet_group;
9140 /* First sort each group individually. */
9141 for (group = 0; group < NUM_GROUPS; group++)
9144 frv_sort_insn_group (group);
9147 /* Go through the unit template and try add an instruction from
9148 that unit's group. */
9150 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
9152 group = frv_unit_groups[unit];
9153 packet_group = &frv_packet.groups[group];
9154 if (cursor[group] < packet_group->num_insns)
9156 /* frv_reorg should have added nops for us. */
9157 if (packet_group->sorted[cursor[group]] == packet_group->nop)
9159 insns[to++] = packet_group->sorted[cursor[group]++];
9163 if (to != frv_packet.num_insns)
9166 /* Clear the last instruction's packing flag, thus marking the end of
9167 a packet. Reorder the other instructions relative to it. */
9168 CLEAR_PACKING_FLAG (insns[to - 1]);
9169 for (from = 0; from < to - 1; from++)
9171 remove_insn (insns[from]);
9172 add_insn_before (insns[from], insns[to - 1]);
9173 SET_PACKING_FLAG (insns[from]);
9178 /* Divide instructions into packets. Reorder the contents of each
9179 packet so that they are in the correct assembly-language order.
9181 Since this pass can change the raw meaning of the rtl stream, it must
9182 only be called at the last minute, just before the instructions are
9186 frv_pack_insns (void)
9188 if (frv_for_each_packet (frv_reorder_packet))
9189 frv_insn_packing_flag = 0;
9191 frv_insn_packing_flag = -1;
9194 /* See whether we need to add nops to group GROUP in order to
9195 make a valid packet. */
9198 frv_fill_unused_units (enum frv_insn_group group)
9200 unsigned int non_nops, nops, i;
9201 struct frv_packet_group *packet_group;
9203 packet_group = &frv_packet.groups[group];
9205 /* Sort the instructions into assembly-language order.
9206 Use nops to fill slots that are otherwise unused. */
9207 frv_sort_insn_group (group);
9209 /* See how many nops are needed before the final useful instruction. */
9211 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
9212 while (packet_group->sorted[i++] == packet_group->nop)
9215 /* Insert that many nops into the instruction stream. */
9217 frv_insert_nop_in_packet (packet_group->nop);
9220 /* Used by frv_reorg to keep track of the current packet's address. */
9221 static unsigned int frv_packet_address;
9223 /* If the current packet falls through to a label, try to pad the packet
9224 with nops in order to fit the label's alignment requirements. */
9227 frv_align_label (void)
9229 unsigned int alignment, target, nop;
9230 rtx x, last, barrier, label;
9232 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
9233 maximum alignment of that packet, LABEL to the last label between
9234 the packets, and BARRIER to the last barrier. */
9235 last = frv_packet.insns[frv_packet.num_insns - 1];
9236 label = barrier = 0;
9238 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
9242 unsigned int subalign = 1 << label_to_alignment (x);
9243 alignment = MAX (alignment, subalign);
9250 /* If -malign-labels, and the packet falls through to an unaligned
9251 label, try introducing a nop to align that label to 8 bytes. */
9252 if (TARGET_ALIGN_LABELS
9255 && frv_packet.num_insns < frv_packet.issue_rate)
9256 alignment = MAX (alignment, 8);
9258 /* Advance the address to the end of the current packet. */
9259 frv_packet_address += frv_packet.num_insns * 4;
9261 /* Work out the target address, after alignment. */
9262 target = (frv_packet_address + alignment - 1) & -alignment;
9264 /* If the packet falls through to the label, try to find an efficient
9265 padding sequence. */
9268 /* First try adding nops to the current packet. */
9269 for (nop = 0; nop < frv_num_nops; nop++)
9270 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
9272 frv_insert_nop_in_packet (frv_nops[nop]);
9273 frv_packet_address += 4;
9276 /* If we still haven't reached the target, add some new packets that
9277 contain only nops. If there are two types of nop, insert an
9278 alternating sequence of frv_nops[0] and frv_nops[1], which will
9279 lead to packets like:
9286 etc. Just emit frv_nops[0] if that's the only nop we have. */
9287 last = frv_packet.insns[frv_packet.num_insns - 1];
9289 while (frv_packet_address < target)
9291 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
9292 frv_packet_address += 4;
9293 if (frv_num_nops > 1)
9298 frv_packet_address = target;
9301 /* Subroutine of frv_reorg, called after each packet has been constructed
9305 frv_reorg_packet (void)
9307 frv_fill_unused_units (GROUP_I);
9308 frv_fill_unused_units (GROUP_FM);
9312 /* Add an instruction with pattern NOP to frv_nops[]. */
9315 frv_register_nop (rtx nop)
9317 nop = make_insn_raw (nop);
9318 NEXT_INSN (nop) = 0;
9319 PREV_INSN (nop) = 0;
9320 frv_nops[frv_num_nops++] = nop;
9323 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
9324 into packets and check whether we need to insert nops in order to
9325 fulfill the processor's issue requirements. Also, if the user has
9326 requested a certain alignment for a label, try to meet that alignment
9327 by inserting nops in the previous packet. */
9333 frv_register_nop (gen_nop ());
9335 frv_register_nop (gen_mnop ());
9336 if (TARGET_HARD_FLOAT)
9337 frv_register_nop (gen_fnop ());
9339 /* Estimate the length of each branch. Although this may change after
9340 we've inserted nops, it will only do so in big functions. */
9341 shorten_branches (get_insns ());
9343 frv_packet_address = 0;
9344 frv_for_each_packet (frv_reorg_packet);
9347 #define def_builtin(name, type, code) \
9348 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
9350 struct builtin_description
9352 enum insn_code icode;
9354 enum frv_builtins code;
9355 enum rtx_code comparison;
9359 /* Media intrinsics that take a single, constant argument. */
9361 static struct builtin_description bdesc_set[] =
9363 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
9366 /* Media intrinsics that take just one argument. */
9368 static struct builtin_description bdesc_1arg[] =
9370 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
9371 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
9372 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
9373 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
9374 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
9375 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
9378 /* Media intrinsics that take two arguments. */
9380 static struct builtin_description bdesc_2arg[] =
9382 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
9383 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
9384 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
9385 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
9386 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
9387 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
9388 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
9389 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
9390 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
9391 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
9392 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
9393 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
9394 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
9395 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
9396 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
9397 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
9398 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
9399 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
9400 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
9401 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
9402 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
9403 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
9404 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
9405 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
9406 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
9407 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
9408 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
9411 /* Integer intrinsics that take two arguments and have no return value. */
9413 static struct builtin_description bdesc_int_void2arg[] =
9415 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
9416 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
9417 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
9420 static struct builtin_description bdesc_prefetches[] =
9422 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
9423 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
9426 /* Media intrinsics that take two arguments, the first being an ACC number. */
9428 static struct builtin_description bdesc_cut[] =
9430 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
9431 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
9432 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
9435 /* Two-argument media intrinsics with an immediate second argument. */
9437 static struct builtin_description bdesc_2argimm[] =
9439 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
9440 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
9441 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
9442 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
9443 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
9444 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
9445 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
9446 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
9447 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
9448 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
9449 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
9450 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
9451 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
9452 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
9453 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
9454 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
9455 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
9458 /* Media intrinsics that take two arguments and return void, the first argument
9459 being a pointer to 4 words in memory. */
9461 static struct builtin_description bdesc_void2arg[] =
9463 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
9464 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
9467 /* Media intrinsics that take three arguments, the first being a const_int that
9468 denotes an accumulator, and that return void. */
9470 static struct builtin_description bdesc_void3arg[] =
9472 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
9473 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
9474 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
9475 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
9476 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
9477 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
9478 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
9479 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
9480 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
9481 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
9482 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9483 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9484 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9485 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9486 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9487 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9488 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9489 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9490 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9491 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9492 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9493 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9494 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9495 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9496 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9499 /* Media intrinsics that take two accumulator numbers as argument and
9502 static struct builtin_description bdesc_voidacc[] =
9504 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9505 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9506 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9507 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9508 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9509 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9512 /* Initialize media builtins. */
9515 frv_init_builtins (void)
9517 tree endlink = void_list_node;
9518 tree accumulator = integer_type_node;
9519 tree integer = integer_type_node;
9520 tree voidt = void_type_node;
9521 tree uhalf = short_unsigned_type_node;
9522 tree sword1 = long_integer_type_node;
9523 tree uword1 = long_unsigned_type_node;
9524 tree sword2 = long_long_integer_type_node;
9525 tree uword2 = long_long_unsigned_type_node;
9526 tree uword4 = build_pointer_type (uword1);
9527 tree iacc = integer_type_node;
9529 #define UNARY(RET, T1) \
9530 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9532 #define BINARY(RET, T1, T2) \
9533 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9534 tree_cons (NULL_TREE, T2, endlink)))
9536 #define TRINARY(RET, T1, T2, T3) \
9537 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9538 tree_cons (NULL_TREE, T2, \
9539 tree_cons (NULL_TREE, T3, endlink))))
9541 #define QUAD(RET, T1, T2, T3, T4) \
9542 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9543 tree_cons (NULL_TREE, T2, \
9544 tree_cons (NULL_TREE, T3, \
9545 tree_cons (NULL_TREE, T4, endlink)))))
9547 tree void_ftype_void = build_function_type (voidt, endlink);
9549 tree void_ftype_acc = UNARY (voidt, accumulator);
9550 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9551 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9552 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9553 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9554 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9555 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9556 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9557 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9559 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9560 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9561 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9562 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9563 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9564 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9565 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9566 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9567 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9568 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9569 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9571 tree sw1_ftype_int = UNARY (sword1, integer);
9572 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9573 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9575 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9576 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9577 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9578 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9579 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9580 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
9582 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9583 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
9584 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
9585 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
9586 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
9587 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
9588 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
9589 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
9590 tree sw2_ftype_iacc = UNARY (sword2, iacc);
9591 tree sw1_ftype_iacc = UNARY (sword1, iacc);
9592 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
9594 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9595 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9596 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9597 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9598 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9599 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9600 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9601 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9602 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9603 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9604 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9605 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9606 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9607 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9608 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9609 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9610 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9611 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9612 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9613 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9614 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9615 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9616 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9617 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9618 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9619 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9620 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9621 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9622 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9623 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9624 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9625 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9626 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9627 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9628 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9629 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9630 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9631 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9632 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9633 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9634 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9635 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9636 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9637 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9638 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9639 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9640 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9641 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9642 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9643 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
9644 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9645 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9646 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9647 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9648 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9649 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9650 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9651 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9652 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9653 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9654 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9655 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9656 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9657 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9658 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9659 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9660 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9661 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9662 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9663 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9664 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9665 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9666 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9667 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9668 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9669 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9670 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9671 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9672 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9673 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9674 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9675 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9676 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9677 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9678 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
9679 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
9680 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
9681 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
9682 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
9683 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
9684 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
9685 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
9686 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
9687 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
9688 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
9689 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
9690 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
9691 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
9692 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
9693 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
9694 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
9695 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
9696 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
9697 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
9705 /* Set the names for various arithmetic operations according to the
9708 frv_init_libfuncs (void)
9710 set_optab_libfunc (smod_optab, SImode, "__modi");
9711 set_optab_libfunc (umod_optab, SImode, "__umodi");
9713 set_optab_libfunc (add_optab, DImode, "__addll");
9714 set_optab_libfunc (sub_optab, DImode, "__subll");
9715 set_optab_libfunc (smul_optab, DImode, "__mulll");
9716 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9717 set_optab_libfunc (smod_optab, DImode, "__modll");
9718 set_optab_libfunc (umod_optab, DImode, "__umodll");
9719 set_optab_libfunc (and_optab, DImode, "__andll");
9720 set_optab_libfunc (ior_optab, DImode, "__orll");
9721 set_optab_libfunc (xor_optab, DImode, "__xorll");
9722 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9724 set_optab_libfunc (add_optab, SFmode, "__addf");
9725 set_optab_libfunc (sub_optab, SFmode, "__subf");
9726 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9727 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9729 set_optab_libfunc (add_optab, DFmode, "__addd");
9730 set_optab_libfunc (sub_optab, DFmode, "__subd");
9731 set_optab_libfunc (smul_optab, DFmode, "__muld");
9732 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9734 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9735 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9737 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9738 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9739 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9740 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9742 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9743 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9744 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9745 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9747 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9748 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9749 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9750 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9753 /* Convert an integer constant to an accumulator register. ICODE is the
9754 code of the target instruction, OPNUM is the number of the
9755 accumulator operand and OPVAL is the constant integer. Try both
9756 ACC and ACCG registers; only report an error if neither fit the
9760 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9765 /* ACCs and ACCGs are implicity global registers if media intrinsics
9766 are being used. We set up this lazily to avoid creating lots of
9767 unnecessary call_insn rtl in non-media code. */
9768 for (i = 0; i <= ACC_MASK; i++)
9769 if ((i & ACC_MASK) == i)
9770 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
9772 if (GET_CODE (opval) != CONST_INT)
9774 error ("accumulator is not a constant integer");
9777 if ((INTVAL (opval) & ~ACC_MASK) != 0)
9779 error ("accumulator number is out of bounds");
9783 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9784 ACC_FIRST + INTVAL (opval));
9785 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9786 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9788 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9790 error ("inappropriate accumulator for %qs", insn_data[icode].name);
9796 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9799 static enum machine_mode
9800 frv_matching_accg_mode (enum machine_mode mode)
9818 /* Return the accumulator guard that should be paired with accumulator
9819 register ACC. The mode of the returned register is in the same
9820 class as ACC, but is four times smaller. */
9823 frv_matching_accg_for_acc (rtx acc)
9825 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9826 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9829 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9830 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9834 frv_read_argument (tree *arglistptr)
9836 tree next = TREE_VALUE (*arglistptr);
9837 *arglistptr = TREE_CHAIN (*arglistptr);
9838 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9841 /* Like frv_read_argument, but interpret the argument as the number
9842 of an IACC register and return a (reg:MODE ...) rtx for it. */
9845 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
9850 op = frv_read_argument (arglistptr);
9851 if (GET_CODE (op) != CONST_INT
9853 || INTVAL (op) > IACC_LAST - IACC_FIRST
9854 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
9856 error ("invalid IACC argument");
9860 /* IACCs are implicity global registers. We set up this lazily to
9861 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
9863 regno = INTVAL (op) + IACC_FIRST;
9864 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
9865 global_regs[regno + i] = 1;
9867 return gen_rtx_REG (mode, regno);
9870 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9871 The instruction should require a constant operand of some sort. The
9872 function prints an error if OPVAL is not valid. */
9875 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9877 if (GET_CODE (opval) != CONST_INT)
9879 error ("%qs expects a constant argument", insn_data[icode].name);
9882 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9884 error ("constant argument out of range for %qs", insn_data[icode].name);
9890 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9891 if it's not null, has the right mode, and satisfies operand 0's
9895 frv_legitimize_target (enum insn_code icode, rtx target)
9897 enum machine_mode mode = insn_data[icode].operand[0].mode;
9900 || GET_MODE (target) != mode
9901 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9902 return gen_reg_rtx (mode);
9907 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9908 check whether ARG satisfies the operand's constraints. If it doesn't,
9909 copy ARG to a temporary register and return that. Otherwise return ARG
9913 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9915 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9917 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9920 return copy_to_mode_reg (mode, arg);
9923 /* Expand builtins that take a single, constant argument. At the moment,
9924 only MHDSETS falls into this category. */
9927 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9930 rtx op0 = frv_read_argument (&arglist);
9932 if (! frv_check_constant_argument (icode, 1, op0))
9935 target = frv_legitimize_target (icode, target);
9936 pat = GEN_FCN (icode) (target, op0);
9944 /* Expand builtins that take one operand. */
9947 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9950 rtx op0 = frv_read_argument (&arglist);
9952 target = frv_legitimize_target (icode, target);
9953 op0 = frv_legitimize_argument (icode, 1, op0);
9954 pat = GEN_FCN (icode) (target, op0);
9962 /* Expand builtins that take two operands. */
9965 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9968 rtx op0 = frv_read_argument (&arglist);
9969 rtx op1 = frv_read_argument (&arglist);
9971 target = frv_legitimize_target (icode, target);
9972 op0 = frv_legitimize_argument (icode, 1, op0);
9973 op1 = frv_legitimize_argument (icode, 2, op1);
9974 pat = GEN_FCN (icode) (target, op0, op1);
9982 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9986 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9989 rtx op0 = frv_read_argument (&arglist);
9990 rtx op1 = frv_read_argument (&arglist);
9993 target = frv_legitimize_target (icode, target);
9994 op0 = frv_int_to_acc (icode, 1, op0);
9998 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
10000 if (! frv_check_constant_argument (icode, 2, op1))
10004 op1 = frv_legitimize_argument (icode, 2, op1);
10006 op2 = frv_matching_accg_for_acc (op0);
10007 pat = GEN_FCN (icode) (target, op0, op1, op2);
10015 /* Expand builtins that take two operands and the second is immediate. */
10018 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
10021 rtx op0 = frv_read_argument (&arglist);
10022 rtx op1 = frv_read_argument (&arglist);
10024 if (! frv_check_constant_argument (icode, 2, op1))
10027 target = frv_legitimize_target (icode, target);
10028 op0 = frv_legitimize_argument (icode, 1, op0);
10029 pat = GEN_FCN (icode) (target, op0, op1);
10037 /* Expand builtins that take two operands, the first operand being a pointer to
10038 ints and return void. */
10041 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
10044 rtx op0 = frv_read_argument (&arglist);
10045 rtx op1 = frv_read_argument (&arglist);
10046 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10049 if (GET_CODE (op0) != MEM)
10053 if (! offsettable_address_p (0, mode0, op0))
10055 reg = gen_reg_rtx (Pmode);
10056 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
10059 op0 = gen_rtx_MEM (SImode, reg);
10062 addr = XEXP (op0, 0);
10063 if (! offsettable_address_p (0, mode0, addr))
10064 addr = copy_to_mode_reg (Pmode, op0);
10066 op0 = change_address (op0, V4SImode, addr);
10067 op1 = frv_legitimize_argument (icode, 1, op1);
10068 pat = GEN_FCN (icode) (op0, op1);
10076 /* Expand builtins that take two long operands and return void. */
10079 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
10082 rtx op0 = frv_read_argument (&arglist);
10083 rtx op1 = frv_read_argument (&arglist);
10085 op0 = frv_legitimize_argument (icode, 1, op0);
10086 op1 = frv_legitimize_argument (icode, 1, op1);
10087 pat = GEN_FCN (icode) (op0, op1);
10095 /* Expand prefetch builtins. These take a single address as argument. */
10098 frv_expand_prefetches (enum insn_code icode, tree arglist)
10101 rtx op0 = frv_read_argument (&arglist);
10103 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
10111 /* Expand builtins that take three operands and return void. The first
10112 argument must be a constant that describes a pair or quad accumulators. A
10113 fourth argument is created that is the accumulator guard register that
10114 corresponds to the accumulator. */
10117 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
10120 rtx op0 = frv_read_argument (&arglist);
10121 rtx op1 = frv_read_argument (&arglist);
10122 rtx op2 = frv_read_argument (&arglist);
10125 op0 = frv_int_to_acc (icode, 0, op0);
10129 op1 = frv_legitimize_argument (icode, 1, op1);
10130 op2 = frv_legitimize_argument (icode, 2, op2);
10131 op3 = frv_matching_accg_for_acc (op0);
10132 pat = GEN_FCN (icode) (op0, op1, op2, op3);
10140 /* Expand builtins that perform accumulator-to-accumulator operations.
10141 These builtins take two accumulator numbers as argument and return
10145 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
10148 rtx op0 = frv_read_argument (&arglist);
10149 rtx op1 = frv_read_argument (&arglist);
10153 op0 = frv_int_to_acc (icode, 0, op0);
10157 op1 = frv_int_to_acc (icode, 1, op1);
10161 op2 = frv_matching_accg_for_acc (op0);
10162 op3 = frv_matching_accg_for_acc (op1);
10163 pat = GEN_FCN (icode) (op0, op1, op2, op3);
10171 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
10172 each argument forms one word of the two double-word input registers.
10173 ARGLIST is a TREE_LIST of the arguments and TARGET, if nonnull,
10174 suggests a good place to put the return value. */
10177 frv_expand_mdpackh_builtin (tree arglist, rtx target)
10179 enum insn_code icode = CODE_FOR_mdpackh;
10181 rtx arg1 = frv_read_argument (&arglist);
10182 rtx arg2 = frv_read_argument (&arglist);
10183 rtx arg3 = frv_read_argument (&arglist);
10184 rtx arg4 = frv_read_argument (&arglist);
10186 target = frv_legitimize_target (icode, target);
10187 op0 = gen_reg_rtx (DImode);
10188 op1 = gen_reg_rtx (DImode);
10190 /* The high half of each word is not explicitly initialised, so indicate
10191 that the input operands are not live before this point. */
10192 emit_insn (gen_rtx_CLOBBER (DImode, op0));
10193 emit_insn (gen_rtx_CLOBBER (DImode, op1));
10195 /* Move each argument into the low half of its associated input word. */
10196 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
10197 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
10198 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
10199 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
10201 pat = GEN_FCN (icode) (target, op0, op1);
10209 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
10210 number as argument. */
10213 frv_expand_mclracc_builtin (tree arglist)
10215 enum insn_code icode = CODE_FOR_mclracc;
10217 rtx op0 = frv_read_argument (&arglist);
10219 op0 = frv_int_to_acc (icode, 0, op0);
10223 pat = GEN_FCN (icode) (op0);
10230 /* Expand builtins that take no arguments. */
10233 frv_expand_noargs_builtin (enum insn_code icode)
10235 rtx pat = GEN_FCN (icode) (const0_rtx);
10242 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
10243 number or accumulator guard number as argument and return an SI integer. */
10246 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
10249 rtx target = gen_reg_rtx (SImode);
10250 rtx op0 = frv_read_argument (&arglist);
10252 op0 = frv_int_to_acc (icode, 1, op0);
10256 pat = GEN_FCN (icode) (target, op0);
10264 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
10265 accumulator guard as their first argument and an SImode value as their
10269 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
10272 rtx op0 = frv_read_argument (&arglist);
10273 rtx op1 = frv_read_argument (&arglist);
10275 op0 = frv_int_to_acc (icode, 0, op0);
10279 op1 = frv_legitimize_argument (icode, 1, op1);
10280 pat = GEN_FCN (icode) (op0, op1);
10287 /* Emit a move from SRC to DEST in SImode chunks. This can be used
10288 to move DImode values into and out of IACC0. */
10291 frv_split_iacc_move (rtx dest, rtx src)
10293 enum machine_mode inner;
10296 inner = GET_MODE (dest);
10297 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
10298 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
10299 simplify_gen_subreg (SImode, src, inner, i));
10302 /* Expand builtins. */
10305 frv_expand_builtin (tree exp,
10307 rtx subtarget ATTRIBUTE_UNUSED,
10308 enum machine_mode mode ATTRIBUTE_UNUSED,
10309 int ignore ATTRIBUTE_UNUSED)
10311 tree arglist = TREE_OPERAND (exp, 1);
10312 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10313 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
10315 struct builtin_description *d;
10317 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
10319 error ("media functions are not available unless -mmedia is used");
10325 case FRV_BUILTIN_MCOP1:
10326 case FRV_BUILTIN_MCOP2:
10327 case FRV_BUILTIN_MDUNPACKH:
10328 case FRV_BUILTIN_MBTOHE:
10329 if (! TARGET_MEDIA_REV1)
10331 error ("this media function is only available on the fr500");
10336 case FRV_BUILTIN_MQXMACHS:
10337 case FRV_BUILTIN_MQXMACXHS:
10338 case FRV_BUILTIN_MQMACXHS:
10339 case FRV_BUILTIN_MADDACCS:
10340 case FRV_BUILTIN_MSUBACCS:
10341 case FRV_BUILTIN_MASACCS:
10342 case FRV_BUILTIN_MDADDACCS:
10343 case FRV_BUILTIN_MDSUBACCS:
10344 case FRV_BUILTIN_MDASACCS:
10345 case FRV_BUILTIN_MABSHS:
10346 case FRV_BUILTIN_MDROTLI:
10347 case FRV_BUILTIN_MCPLHI:
10348 case FRV_BUILTIN_MCPLI:
10349 case FRV_BUILTIN_MDCUTSSI:
10350 case FRV_BUILTIN_MQSATHS:
10351 case FRV_BUILTIN_MHSETLOS:
10352 case FRV_BUILTIN_MHSETLOH:
10353 case FRV_BUILTIN_MHSETHIS:
10354 case FRV_BUILTIN_MHSETHIH:
10355 case FRV_BUILTIN_MHDSETS:
10356 case FRV_BUILTIN_MHDSETH:
10357 if (! TARGET_MEDIA_REV2)
10359 error ("this media function is only available on the fr400"
10365 case FRV_BUILTIN_SMASS:
10366 case FRV_BUILTIN_SMSSS:
10367 case FRV_BUILTIN_SMU:
10368 case FRV_BUILTIN_ADDSS:
10369 case FRV_BUILTIN_SUBSS:
10370 case FRV_BUILTIN_SLASS:
10371 case FRV_BUILTIN_SCUTSS:
10372 case FRV_BUILTIN_IACCreadll:
10373 case FRV_BUILTIN_IACCreadl:
10374 case FRV_BUILTIN_IACCsetll:
10375 case FRV_BUILTIN_IACCsetl:
10376 if (!TARGET_FR405_BUILTINS)
10378 error ("this builtin function is only available"
10379 " on the fr405 and fr450");
10384 case FRV_BUILTIN_PREFETCH:
10385 if (!TARGET_FR500_FR550_BUILTINS)
10387 error ("this builtin function is only available on the fr500"
10393 case FRV_BUILTIN_MQLCLRHS:
10394 case FRV_BUILTIN_MQLMTHS:
10395 case FRV_BUILTIN_MQSLLHI:
10396 case FRV_BUILTIN_MQSRAHI:
10397 if (!TARGET_MEDIA_FR450)
10399 error ("this builtin function is only available on the fr450");
10408 /* Expand unique builtins. */
10412 case FRV_BUILTIN_MTRAP:
10413 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
10415 case FRV_BUILTIN_MCLRACC:
10416 return frv_expand_mclracc_builtin (arglist);
10418 case FRV_BUILTIN_MCLRACCA:
10420 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
10422 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
10424 case FRV_BUILTIN_MRDACC:
10425 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
10427 case FRV_BUILTIN_MRDACCG:
10428 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
10430 case FRV_BUILTIN_MWTACC:
10431 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
10433 case FRV_BUILTIN_MWTACCG:
10434 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
10436 case FRV_BUILTIN_MDPACKH:
10437 return frv_expand_mdpackh_builtin (arglist, target);
10439 case FRV_BUILTIN_IACCreadll:
10441 rtx src = frv_read_iacc_argument (DImode, &arglist);
10442 if (target == 0 || !REG_P (target))
10443 target = gen_reg_rtx (DImode);
10444 frv_split_iacc_move (target, src);
10448 case FRV_BUILTIN_IACCreadl:
10449 return frv_read_iacc_argument (SImode, &arglist);
10451 case FRV_BUILTIN_IACCsetll:
10453 rtx dest = frv_read_iacc_argument (DImode, &arglist);
10454 rtx src = frv_read_argument (&arglist);
10455 frv_split_iacc_move (dest, force_reg (DImode, src));
10459 case FRV_BUILTIN_IACCsetl:
10461 rtx dest = frv_read_iacc_argument (SImode, &arglist);
10462 rtx src = frv_read_argument (&arglist);
10463 emit_move_insn (dest, force_reg (SImode, src));
10471 /* Expand groups of builtins. */
10473 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
10474 if (d->code == fcode)
10475 return frv_expand_set_builtin (d->icode, arglist, target);
10477 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10478 if (d->code == fcode)
10479 return frv_expand_unop_builtin (d->icode, arglist, target);
10481 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10482 if (d->code == fcode)
10483 return frv_expand_binop_builtin (d->icode, arglist, target);
10485 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
10486 if (d->code == fcode)
10487 return frv_expand_cut_builtin (d->icode, arglist, target);
10489 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
10490 if (d->code == fcode)
10491 return frv_expand_binopimm_builtin (d->icode, arglist, target);
10493 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
10494 if (d->code == fcode)
10495 return frv_expand_voidbinop_builtin (d->icode, arglist);
10497 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
10498 if (d->code == fcode)
10499 return frv_expand_voidtriop_builtin (d->icode, arglist);
10501 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
10502 if (d->code == fcode)
10503 return frv_expand_voidaccop_builtin (d->icode, arglist);
10505 for (i = 0, d = bdesc_int_void2arg;
10506 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
10507 if (d->code == fcode)
10508 return frv_expand_int_void2arg (d->icode, arglist);
10510 for (i = 0, d = bdesc_prefetches;
10511 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
10512 if (d->code == fcode)
10513 return frv_expand_prefetches (d->icode, arglist);
10519 frv_in_small_data_p (tree decl)
10521 HOST_WIDE_INT size;
10524 /* Don't apply the -G flag to internal compiler structures. We
10525 should leave such structures in the main data section, partly
10526 for efficiency and partly because the size of some of them
10527 (such as C++ typeinfos) is not known until later. */
10528 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
10531 /* If we already know which section the decl should be in, see if
10532 it's a small data section. */
10533 section_name = DECL_SECTION_NAME (decl);
10536 if (TREE_CODE (section_name) != STRING_CST)
10538 if (frv_string_begins_with (section_name, ".sdata"))
10540 if (frv_string_begins_with (section_name, ".sbss"))
10545 size = int_size_in_bytes (TREE_TYPE (decl));
10546 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
10553 frv_rtx_costs (rtx x,
10554 int code ATTRIBUTE_UNUSED,
10555 int outer_code ATTRIBUTE_UNUSED,
10558 if (outer_code == MEM)
10560 /* Don't differentiate between memory addresses. All the ones
10561 we accept have equal cost. */
10562 *total = COSTS_N_INSNS (0);
10569 /* Make 12 bit integers really cheap. */
10570 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
10575 /* Fall through. */
10581 *total = COSTS_N_INSNS (2);
10595 if (GET_MODE (x) == SImode)
10596 *total = COSTS_N_INSNS (1);
10597 else if (GET_MODE (x) == DImode)
10598 *total = COSTS_N_INSNS (2);
10600 *total = COSTS_N_INSNS (3);
10604 if (GET_MODE (x) == SImode)
10605 *total = COSTS_N_INSNS (2);
10607 *total = COSTS_N_INSNS (6); /* guess */
10614 *total = COSTS_N_INSNS (18);
10618 *total = COSTS_N_INSNS (3);
10627 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10630 assemble_align (POINTER_SIZE);
10633 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10637 assemble_integer_with_op ("\t.picptr\t", symbol);
10641 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10644 assemble_align (POINTER_SIZE);
10647 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10651 assemble_integer_with_op ("\t.picptr\t", symbol);
10654 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10657 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
10658 int incoming ATTRIBUTE_UNUSED)
10660 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
10663 #define TLS_BIAS (2048 - 16)
10665 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
10666 We need to emit DTP-relative relocations. */
10669 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
10673 fputs ("\t.picptr\ttlsmoff(", file);
10674 /* We want the unbiased TLS offset, so add the bias to the
10675 expression, such that the implicit biasing cancels out. */
10676 output_addr_const (file, plus_constant (x, TLS_BIAS));
10680 #include "gt-frv.h"