1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Information about a relocation unspec. SYMBOL is the relocation symbol
127 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
128 is the constant addend. */
132 HOST_WIDE_INT offset;
135 /* Temporary register allocation support structure. */
136 typedef struct frv_tmp_reg_struct
138 HARD_REG_SET regs; /* possible registers to allocate */
139 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
143 /* Register state information for VLIW re-packing phase. */
144 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
145 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
146 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
147 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
149 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
151 typedef unsigned char regstate_t;
153 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
161 /* Information required by frv_frame_access. */
164 /* This field is FRV_LOAD if registers are to be loaded from the stack and
165 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
166 the move is being done by the prologue code while FRV_LOAD implies it
167 is being done by the epilogue. */
168 enum frv_stack_op op;
170 /* The base register to use when accessing the stack. This may be the
171 frame pointer, stack pointer, or a temporary. The choice of register
172 depends on which part of the frame is being accessed and how big the
176 /* The offset of BASE from the bottom of the current frame, in bytes. */
178 } frv_frame_accessor_t;
180 /* Define the information needed to generate branch and scc insns. This is
181 stored from the compare operation. */
185 /* Conditional execution support gathered together in one structure. */
188 /* Linked list of insns to add if the conditional execution conversion was
189 successful. Each link points to an EXPR_LIST which points to the pattern
190 of the insn to add, and the insn to be inserted before. */
191 rtx added_insns_list;
193 /* Identify which registers are safe to allocate for if conversions to
194 conditional execution. We keep the last allocated register in the
195 register classes between COND_EXEC statements. This will mean we allocate
196 different registers for each different COND_EXEC group if we can. This
197 might allow the scheduler to intermix two different COND_EXEC sections. */
198 frv_tmp_reg_t tmp_reg;
200 /* For nested IFs, identify which CC registers are used outside of setting
201 via a compare isnsn, and using via a check insn. This will allow us to
202 know if we can rewrite the register to use a different register that will
203 be paired with the CR register controlling the nested IF-THEN blocks. */
204 HARD_REG_SET nested_cc_ok_rewrite;
206 /* Temporary registers allocated to hold constants during conditional
208 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
210 /* Current number of temp registers available. */
211 int cur_scratch_regs;
213 /* Number of nested conditional execution blocks. */
214 int num_nested_cond_exec;
216 /* Map of insns that set up constants in scratch registers. */
217 bitmap scratch_insns_bitmap;
219 /* Conditional execution test register (CC0..CC7). */
222 /* Conditional execution compare register that is paired with cr_reg, so that
223 nested compares can be done. The csubcc and caddcc instructions don't
224 have enough bits to specify both a CC register to be set and a CR register
225 to do the test on, so the same bit number is used for both. Needless to
226 say, this is rather inconvenient for GCC. */
229 /* Extra CR registers used for &&, ||. */
233 /* Previous CR used in nested if, to make sure we are dealing with the same
234 nested if as the previous statement. */
235 rtx last_nested_if_cr;
239 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
241 /* Map register number to smallest register class. */
242 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
244 /* Map class letter into register class. */
245 enum reg_class reg_class_from_letter[256];
247 /* Cached value of frv_stack_info. */
248 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
250 /* -mbranch-cost= support */
251 const char *frv_branch_cost_string;
252 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
255 const char *frv_cpu_string; /* -mcpu= option */
256 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
258 /* -mcond-exec-insns= support */
259 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
260 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
262 /* -mcond-exec-temps= support */
263 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
264 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
266 /* -msched-lookahead=n */
267 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
268 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
270 /* Forward references */
271 static int frv_default_flags_for_cpu (void);
272 static int frv_string_begins_with (tree, const char *);
273 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
274 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
280 static rtx single_set_pattern (rtx);
281 static int frv_function_contains_far_jump (void);
282 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
286 static rtx frv_frame_offset_rtx (int);
287 static rtx frv_frame_mem (enum machine_mode, rtx, int);
288 static rtx frv_dwarf_store (rtx, int);
289 static void frv_frame_insn (rtx, rtx);
290 static void frv_frame_access (frv_frame_accessor_t*,
292 static void frv_frame_access_multi (frv_frame_accessor_t*,
294 static void frv_frame_access_standard_regs (enum frv_stack_op,
296 static struct machine_function *frv_init_machine_status (void);
297 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
298 static rtx frv_int_to_acc (enum insn_code, int, rtx);
299 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
300 static rtx frv_read_argument (tree *);
301 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
302 static int frv_check_constant_argument (enum insn_code, int, rtx);
303 static rtx frv_legitimize_target (enum insn_code, rtx);
304 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
305 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
306 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
311 static rtx frv_expand_int_void2arg (enum insn_code, tree);
312 static rtx frv_expand_prefetches (enum insn_code, tree);
313 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
314 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
315 static rtx frv_expand_mclracc_builtin (tree);
316 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
317 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_noargs_builtin (enum insn_code);
319 static void frv_split_iacc_move (rtx, rtx);
320 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
321 static int frv_clear_registers_used (rtx *, void *);
322 static void frv_ifcvt_add_insn (rtx, rtx, int);
323 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
324 static rtx frv_ifcvt_load_value (rtx, rtx);
325 static int frv_acc_group_1 (rtx *, void *);
326 static unsigned int frv_insn_unit (rtx);
327 static bool frv_issues_to_branch_unit_p (rtx);
328 static int frv_cond_flags (rtx);
329 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
330 static int frv_registers_conflict_p_1 (rtx *, void *);
331 static bool frv_registers_conflict_p (rtx);
332 static void frv_registers_update_1 (rtx, rtx, void *);
333 static void frv_registers_update (rtx);
334 static void frv_start_packet (void);
335 static void frv_start_packet_block (void);
336 static void frv_finish_packet (void (*) (void));
337 static bool frv_pack_insn_p (rtx);
338 static void frv_add_insn_to_packet (rtx);
339 static void frv_insert_nop_in_packet (rtx);
340 static bool frv_for_each_packet (void (*) (void));
341 static bool frv_sort_insn_group_1 (enum frv_insn_group,
342 unsigned int, unsigned int,
343 unsigned int, unsigned int,
345 static int frv_compare_insns (const void *, const void *);
346 static void frv_sort_insn_group (enum frv_insn_group);
347 static void frv_reorder_packet (void);
348 static void frv_fill_unused_units (enum frv_insn_group);
349 static void frv_align_label (void);
350 static void frv_reorg_packet (void);
351 static void frv_register_nop (rtx);
352 static void frv_reorg (void);
353 static void frv_pack_insns (void);
354 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
355 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
356 static bool frv_assemble_integer (rtx, unsigned, int);
357 static void frv_init_builtins (void);
358 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
359 static void frv_init_libfuncs (void);
360 static bool frv_in_small_data_p (tree);
361 static void frv_asm_output_mi_thunk
362 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
363 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
366 static rtx frv_expand_builtin_saveregs (void);
367 static bool frv_rtx_costs (rtx, int, int, int*);
368 static void frv_asm_out_constructor (rtx, int);
369 static void frv_asm_out_destructor (rtx, int);
370 static bool frv_function_symbol_referenced_p (rtx);
371 static bool frv_cannot_force_const_mem (rtx);
372 static const char *unspec_got_name (int);
373 static void frv_output_const_unspec (FILE *,
374 const struct frv_unspec *);
375 static bool frv_function_ok_for_sibcall (tree, tree);
376 static rtx frv_struct_value_rtx (tree, int);
377 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
379 /* Initialize the GCC target structure. */
380 #undef TARGET_ASM_FUNCTION_PROLOGUE
381 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
382 #undef TARGET_ASM_FUNCTION_EPILOGUE
383 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
384 #undef TARGET_ASM_INTEGER
385 #define TARGET_ASM_INTEGER frv_assemble_integer
386 #undef TARGET_INIT_BUILTINS
387 #define TARGET_INIT_BUILTINS frv_init_builtins
388 #undef TARGET_EXPAND_BUILTIN
389 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
390 #undef TARGET_INIT_LIBFUNCS
391 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
392 #undef TARGET_IN_SMALL_DATA_P
393 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
394 #undef TARGET_RTX_COSTS
395 #define TARGET_RTX_COSTS frv_rtx_costs
396 #undef TARGET_ASM_CONSTRUCTOR
397 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
398 #undef TARGET_ASM_DESTRUCTOR
399 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
401 #undef TARGET_ASM_OUTPUT_MI_THUNK
402 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
403 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
404 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
406 #undef TARGET_SCHED_ISSUE_RATE
407 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
409 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
410 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
411 #undef TARGET_CANNOT_FORCE_CONST_MEM
412 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
414 #undef TARGET_STRUCT_VALUE_RTX
415 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
416 #undef TARGET_MUST_PASS_IN_STACK
417 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
418 #undef TARGET_PASS_BY_REFERENCE
419 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
421 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
422 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
423 #undef TARGET_SETUP_INCOMING_VARARGS
424 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
425 #undef TARGET_MACHINE_DEPENDENT_REORG
426 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
428 struct gcc_target targetm = TARGET_INITIALIZER;
430 /* Any function call that satisfies the machine-independent
431 requirements is eligible on FR-V. */
434 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
435 tree exp ATTRIBUTE_UNUSED)
440 /* Return true if SYMBOL is a small data symbol and relocation RELOC
441 can be used to access it directly in a load or store. */
443 static FRV_INLINE bool
444 frv_small_data_reloc_p (rtx symbol, int reloc)
446 return (GET_CODE (symbol) == SYMBOL_REF
447 && SYMBOL_REF_SMALL_P (symbol)
448 && (!TARGET_FDPIC || flag_pic == 1)
449 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
452 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
455 static FRV_INLINE bool
456 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
458 if (GET_CODE (x) == CONST)
462 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
464 unspec->offset += INTVAL (XEXP (x, 1));
467 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
469 unspec->symbol = XVECEXP (x, 0, 0);
470 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
472 if (unspec->offset == 0)
475 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
476 && unspec->offset > 0
477 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
484 /* Decide whether we can force certain constants to memory. If we
485 decide we can't, the caller should be able to cope with it in
488 We never allow constants to be forced into memory for TARGET_FDPIC.
489 This is necessary for several reasons:
491 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
492 target-independent code will try to force them into the constant
493 pool, thus leading to infinite recursion.
495 2. We can never introduce new constant pool references during reload.
496 Any such reference would require use of the pseudo FDPIC register.
498 3. We can't represent a constant added to a function pointer (which is
499 not the same as a pointer to a function+constant).
501 4. In many cases, it's more efficient to calculate the constant in-line. */
504 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
510 frv_default_flags_for_cpu (void)
512 switch (frv_cpu_type)
514 case FRV_CPU_GENERIC:
515 return MASK_DEFAULT_FRV;
518 return MASK_DEFAULT_FR550;
522 return MASK_DEFAULT_FR500;
525 return MASK_DEFAULT_FR450;
529 return MASK_DEFAULT_FR400;
533 return MASK_DEFAULT_SIMPLE;
538 /* Sometimes certain combinations of command options do not make
539 sense on a particular target machine. You can define a macro
540 `OVERRIDE_OPTIONS' to take account of this. This macro, if
541 defined, is executed once just after all the command options have
544 Don't use this macro to turn on various extra optimizations for
545 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
548 frv_override_options (void)
553 /* Set the cpu type. */
556 if (strcmp (frv_cpu_string, "simple") == 0)
557 frv_cpu_type = FRV_CPU_SIMPLE;
559 else if (strcmp (frv_cpu_string, "tomcat") == 0)
560 frv_cpu_type = FRV_CPU_TOMCAT;
562 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
563 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
567 const char *p = frv_cpu_string + sizeof ("fr") - 1;
568 if (strcmp (p, "550") == 0)
569 frv_cpu_type = FRV_CPU_FR550;
571 else if (strcmp (p, "500") == 0)
572 frv_cpu_type = FRV_CPU_FR500;
574 else if (strcmp (p, "450") == 0)
575 frv_cpu_type = FRV_CPU_FR450;
577 else if (strcmp (p, "405") == 0)
578 frv_cpu_type = FRV_CPU_FR405;
580 else if (strcmp (p, "400") == 0)
581 frv_cpu_type = FRV_CPU_FR400;
583 else if (strcmp (p, "300") == 0)
584 frv_cpu_type = FRV_CPU_FR300;
586 else if (strcmp (p, "v") == 0)
587 frv_cpu_type = FRV_CPU_GENERIC;
590 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
594 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
596 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
597 linker about linking pic and non-pic code. */
600 if (!flag_pic) /* -fPIC */
603 if (! g_switch_set) /* -G0 */
610 /* Change the branch cost value. */
611 if (frv_branch_cost_string)
612 frv_branch_cost_int = atoi (frv_branch_cost_string);
614 /* Change the # of insns to be converted to conditional execution. */
615 if (frv_condexec_insns_str)
616 frv_condexec_insns = atoi (frv_condexec_insns_str);
618 /* Change # of temporary registers used to hold integer constants. */
619 if (frv_condexec_temps_str)
620 frv_condexec_temps = atoi (frv_condexec_temps_str);
622 /* Change scheduling look ahead. */
623 if (frv_sched_lookahead_str)
624 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
626 /* A C expression whose value is a register class containing hard
627 register REGNO. In general there is more than one such class;
628 choose a class which is "minimal", meaning that no smaller class
629 also contains the register. */
631 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
633 enum reg_class class;
637 int gpr_reg = regno - GPR_FIRST;
638 if ((gpr_reg & 3) == 0)
641 else if ((gpr_reg & 1) == 0)
648 else if (FPR_P (regno))
650 int fpr_reg = regno - GPR_FIRST;
651 if ((fpr_reg & 3) == 0)
652 class = QUAD_FPR_REGS;
654 else if ((fpr_reg & 1) == 0)
661 else if (regno == LR_REGNO)
664 else if (regno == LCR_REGNO)
667 else if (ICC_P (regno))
670 else if (FCC_P (regno))
673 else if (ICR_P (regno))
676 else if (FCR_P (regno))
679 else if (ACC_P (regno))
681 int r = regno - ACC_FIRST;
683 class = QUAD_ACC_REGS;
684 else if ((r & 1) == 0)
685 class = EVEN_ACC_REGS;
690 else if (ACCG_P (regno))
696 regno_reg_class[regno] = class;
699 /* Check for small data option */
701 g_switch_value = SDATA_DEFAULT_SIZE;
703 /* A C expression which defines the machine-dependent operand
704 constraint letters for register classes. If CHAR is such a
705 letter, the value should be the register class corresponding to
706 it. Otherwise, the value should be `NO_REGS'. The register
707 letter `r', corresponding to class `GENERAL_REGS', will not be
708 passed to this macro; you do not need to handle it.
710 The following letters are unavailable, due to being used as
715 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
716 'Q', 'R', 'S', 'T', 'U'
718 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
720 for (i = 0; i < 256; i++)
721 reg_class_from_letter[i] = NO_REGS;
723 reg_class_from_letter['a'] = ACC_REGS;
724 reg_class_from_letter['b'] = EVEN_ACC_REGS;
725 reg_class_from_letter['c'] = CC_REGS;
726 reg_class_from_letter['d'] = GPR_REGS;
727 reg_class_from_letter['e'] = EVEN_REGS;
728 reg_class_from_letter['f'] = FPR_REGS;
729 reg_class_from_letter['h'] = FEVEN_REGS;
730 reg_class_from_letter['l'] = LR_REG;
731 reg_class_from_letter['q'] = QUAD_REGS;
732 reg_class_from_letter['t'] = ICC_REGS;
733 reg_class_from_letter['u'] = FCC_REGS;
734 reg_class_from_letter['v'] = ICR_REGS;
735 reg_class_from_letter['w'] = FCR_REGS;
736 reg_class_from_letter['x'] = QUAD_FPR_REGS;
737 reg_class_from_letter['y'] = LCR_REG;
738 reg_class_from_letter['z'] = SPR_REGS;
739 reg_class_from_letter['A'] = QUAD_ACC_REGS;
740 reg_class_from_letter['B'] = ACCG_REGS;
741 reg_class_from_letter['C'] = CR_REGS;
742 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
743 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
745 /* There is no single unaligned SI op for PIC code. Sometimes we
746 need to use ".4byte" and sometimes we need to use ".picptr".
747 See frv_assemble_integer for details. */
748 if (flag_pic || TARGET_FDPIC)
749 targetm.asm_out.unaligned_op.si = 0;
751 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
752 target_flags |= MASK_LINKED_FP;
754 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
755 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
757 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
758 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
760 init_machine_status = frv_init_machine_status;
764 /* Some machines may desire to change what optimizations are performed for
765 various optimization levels. This macro, if defined, is executed once just
766 after the optimization level is determined and before the remainder of the
767 command options have been parsed. Values set in this macro are used as the
768 default values for the other command line options.
770 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
771 `-O' is specified, and 0 if neither is specified.
773 SIZE is nonzero if `-Os' is specified, 0 otherwise.
775 You should not use this macro to change options that are not
776 machine-specific. These should uniformly selected by the same optimization
777 level on all supported machines. Use this macro to enable machbine-specific
780 *Do not examine `write_symbols' in this macro!* The debugging options are
781 *not supposed to alter the generated code. */
783 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
784 scheduling pass at the current time. */
786 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
790 #ifdef DISABLE_SCHED2
791 flag_schedule_insns_after_reload = 0;
800 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
803 frv_string_begins_with (tree name, const char *prefix)
805 int prefix_len = strlen (prefix);
807 /* Remember: NAME's length includes the null terminator. */
808 return (TREE_STRING_LENGTH (name) > prefix_len
809 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
812 /* Zero or more C statements that may conditionally modify two variables
813 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
814 been initialized from the two preceding macros.
816 This is necessary in case the fixed or call-clobbered registers depend on
819 You need not define this macro if it has no work to do.
821 If the usage of an entire class of registers depends on the target flags,
822 you may indicate this to GCC by using this macro to modify `fixed_regs' and
823 `call_used_regs' to 1 for each of the registers in the classes which should
824 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
825 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
827 (However, if this class is not included in `GENERAL_REGS' and all of the
828 insn patterns whose constraints permit this class are controlled by target
829 switches, then GCC will automatically avoid using these registers when the
830 target switches are opposed to them.) */
833 frv_conditional_register_usage (void)
837 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
838 fixed_regs[i] = call_used_regs[i] = 1;
840 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
841 fixed_regs[i] = call_used_regs[i] = 1;
843 /* Reserve the registers used for conditional execution. At present, we need
844 1 ICC and 1 ICR register. */
845 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
846 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
850 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
851 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
852 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
853 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
857 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
858 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
861 /* If -fpic, SDA_BASE_REG is the PIC register. */
862 if (g_switch_value == 0 && !flag_pic)
863 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
866 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
872 * Compute the stack frame layout
875 * +---------------+-----------------------+-----------------------+
876 * |Register |type |caller-save/callee-save|
877 * +---------------+-----------------------+-----------------------+
878 * |GR0 |Zero register | - |
879 * |GR1 |Stack pointer(SP) | - |
880 * |GR2 |Frame pointer(FP) | - |
881 * |GR3 |Hidden parameter | caller save |
882 * |GR4-GR7 | - | caller save |
883 * |GR8-GR13 |Argument register | caller save |
884 * |GR14-GR15 | - | caller save |
885 * |GR16-GR31 | - | callee save |
886 * |GR32-GR47 | - | caller save |
887 * |GR48-GR63 | - | callee save |
888 * |FR0-FR15 | - | caller save |
889 * |FR16-FR31 | - | callee save |
890 * |FR32-FR47 | - | caller save |
891 * |FR48-FR63 | - | callee save |
892 * +---------------+-----------------------+-----------------------+
896 * SP-> |-----------------------------------|
898 * |-----------------------------------|
899 * | Register save area |
900 * |-----------------------------------|
901 * | Local variable save area |
902 * FP-> |-----------------------------------|
904 * |-----------------------------------|
905 * | Hidden parameter save area |
906 * |-----------------------------------|
907 * | Return address(LR) storage area |
908 * |-----------------------------------|
909 * | Padding for alignment |
910 * |-----------------------------------|
911 * | Register argument area |
912 * OLD SP-> |-----------------------------------|
914 * |-----------------------------------|
917 * Argument area/Parameter area:
919 * When a function is called, this area is used for argument transfer. When
920 * the argument is set up by the caller function, this area is referred to as
921 * the argument area. When the argument is referenced by the callee function,
922 * this area is referred to as the parameter area. The area is allocated when
923 * all arguments cannot be placed on the argument register at the time of
926 * Register save area:
928 * This is a register save area that must be guaranteed for the caller
929 * function. This area is not secured when the register save operation is not
932 * Local variable save area:
934 * This is the area for local variables and temporary variables.
938 * This area stores the FP value of the caller function.
940 * Hidden parameter save area:
942 * This area stores the start address of the return value storage
943 * area for a struct/union return function.
944 * When a struct/union is used as the return value, the caller
945 * function stores the return value storage area start address in
946 * register GR3 and passes it to the caller function.
947 * The callee function interprets the address stored in the GR3
948 * as the return value storage area start address.
949 * When register GR3 needs to be saved into memory, the callee
950 * function saves it in the hidden parameter save area. This
951 * area is not secured when the save operation is not needed.
953 * Return address(LR) storage area:
955 * This area saves the LR. The LR stores the address of a return to the caller
956 * function for the purpose of function calling.
958 * Argument register area:
960 * This area saves the argument register. This area is not secured when the
961 * save operation is not needed.
965 * Arguments, the count of which equals the count of argument registers (6
966 * words), are positioned in registers GR8 to GR13 and delivered to the callee
967 * function. When a struct/union return function is called, the return value
968 * area address is stored in register GR3. Arguments not placed in the
969 * argument registers will be stored in the stack argument area for transfer
970 * purposes. When an 8-byte type argument is to be delivered using registers,
971 * it is divided into two and placed in two registers for transfer. When
972 * argument registers must be saved to memory, the callee function secures an
973 * argument register save area in the stack. In this case, a continuous
974 * argument register save area must be established in the parameter area. The
975 * argument register save area must be allocated as needed to cover the size of
976 * the argument register to be saved. If the function has a variable count of
977 * arguments, it saves all argument registers in the argument register save
980 * Argument Extension Format:
982 * When an argument is to be stored in the stack, its type is converted to an
983 * extended type in accordance with the individual argument type. The argument
984 * is freed by the caller function after the return from the callee function is
987 * +-----------------------+---------------+------------------------+
988 * | Argument Type |Extended Type |Stack Storage Size(byte)|
989 * +-----------------------+---------------+------------------------+
991 * |signed char |int | 4 |
992 * |unsigned char |int | 4 |
993 * |[signed] short int |int | 4 |
994 * |unsigned short int |int | 4 |
995 * |[signed] int |No extension | 4 |
996 * |unsigned int |No extension | 4 |
997 * |[signed] long int |No extension | 4 |
998 * |unsigned long int |No extension | 4 |
999 * |[signed] long long int |No extension | 8 |
1000 * |unsigned long long int |No extension | 8 |
1001 * |float |double | 8 |
1002 * |double |No extension | 8 |
1003 * |long double |No extension | 8 |
1004 * |pointer |No extension | 4 |
1005 * |struct/union |- | 4 (*1) |
1006 * +-----------------------+---------------+------------------------+
1008 * When a struct/union is to be delivered as an argument, the caller copies it
1009 * to the local variable area and delivers the address of that area.
1013 * +-------------------------------+----------------------+
1014 * |Return Value Type |Return Value Interface|
1015 * +-------------------------------+----------------------+
1017 * |[signed|unsigned] char |GR8 |
1018 * |[signed|unsigned] short int |GR8 |
1019 * |[signed|unsigned] int |GR8 |
1020 * |[signed|unsigned] long int |GR8 |
1022 * |[signed|unsigned] long long int|GR8 & GR9 |
1024 * |double |GR8 & GR9 |
1025 * |long double |GR8 & GR9 |
1026 * |struct/union |(*1) |
1027 * +-------------------------------+----------------------+
1029 * When a struct/union is used as the return value, the caller function stores
1030 * the start address of the return value storage area into GR3 and then passes
1031 * it to the callee function. The callee function interprets GR3 as the start
1032 * address of the return value storage area. When this address needs to be
1033 * saved in memory, the callee function secures the hidden parameter save area
1034 * and saves the address in that area.
1038 frv_stack_info (void)
1040 static frv_stack_t info, zero_info;
1041 frv_stack_t *info_ptr = &info;
1042 tree fndecl = current_function_decl;
1050 /* If we've already calculated the values and reload is complete,
1052 if (frv_stack_cache)
1053 return frv_stack_cache;
1055 /* Zero all fields. */
1058 /* Set up the register range information. */
1059 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1060 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1061 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1062 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1064 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1065 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1066 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1067 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1069 info_ptr->regs[STACK_REGS_LR].name = "lr";
1070 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1071 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1072 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1074 info_ptr->regs[STACK_REGS_CC].name = "cc";
1075 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1076 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1077 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1079 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1080 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1081 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1083 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1084 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1085 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1086 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1087 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1089 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1090 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1091 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1092 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1094 info_ptr->regs[STACK_REGS_FP].name = "fp";
1095 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1096 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1097 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1099 /* Determine if this is a stdarg function. If so, allocate space to store
1106 /* Find the last argument, and see if it is __builtin_va_alist. */
1107 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1109 next_arg = TREE_CHAIN (cur_arg);
1110 if (next_arg == (tree)0)
1112 if (DECL_NAME (cur_arg)
1113 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1121 /* Iterate over all of the register ranges. */
1122 for (range = 0; range < STACK_REGS_MAX; range++)
1124 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1125 int first = reg_ptr->first;
1126 int last = reg_ptr->last;
1128 int size_2words = 0;
1131 /* Calculate which registers need to be saved & save area size. */
1135 for (regno = first; regno <= last; regno++)
1137 if ((regs_ever_live[regno] && !call_used_regs[regno])
1138 || (current_function_calls_eh_return
1139 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1140 || (!TARGET_FDPIC && flag_pic
1141 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1143 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1144 size_1word += UNITS_PER_WORD;
1149 /* Calculate whether we need to create a frame after everything else
1150 has been processed. */
1155 if (regs_ever_live[LR_REGNO]
1157 /* This is set for __builtin_return_address, etc. */
1158 || cfun->machine->frame_needed
1159 || (TARGET_LINKED_FP && frame_pointer_needed)
1160 || (!TARGET_FDPIC && flag_pic
1161 && cfun->uses_pic_offset_table))
1163 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1164 size_1word += UNITS_PER_WORD;
1168 case STACK_REGS_STDARG:
1171 /* If this is a stdarg function with a non varardic
1172 argument split between registers and the stack,
1173 adjust the saved registers downward. */
1174 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1177 for (regno = first; regno <= last; regno++)
1179 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1180 size_1word += UNITS_PER_WORD;
1183 info_ptr->stdarg_size = size_1word;
1187 case STACK_REGS_STRUCT:
1188 if (cfun->returns_struct)
1190 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1191 size_1word += UNITS_PER_WORD;
1199 /* If this is a field, it only takes one word. */
1200 if (reg_ptr->field_p)
1201 size_1word = UNITS_PER_WORD;
1203 /* Determine which register pairs can be saved together. */
1204 else if (reg_ptr->dword_p && TARGET_DWORD)
1206 for (regno = first; regno < last; regno += 2)
1208 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1210 size_2words += 2 * UNITS_PER_WORD;
1211 size_1word -= 2 * UNITS_PER_WORD;
1212 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1213 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1218 reg_ptr->size_1word = size_1word;
1219 reg_ptr->size_2words = size_2words;
1221 if (! reg_ptr->special_p)
1223 info_ptr->regs_size_1word += size_1word;
1224 info_ptr->regs_size_2words += size_2words;
1229 /* Set up the sizes of each each field in the frame body, making the sizes
1230 of each be divisible by the size of a dword if dword operations might
1231 be used, or the size of a word otherwise. */
1232 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1234 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1235 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1236 + info_ptr->regs_size_1word,
1238 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1240 info_ptr->pretend_size = cfun->pretend_args_size;
1242 /* Work out the size of the frame, excluding the header. Both the frame
1243 body and register parameter area will be dword-aligned. */
1244 info_ptr->total_size
1245 = (ADDR_ALIGN (info_ptr->parameter_size
1246 + info_ptr->regs_size
1247 + info_ptr->vars_size,
1249 + ADDR_ALIGN (info_ptr->pretend_size
1250 + info_ptr->stdarg_size,
1251 2 * UNITS_PER_WORD));
1253 /* See if we need to create a frame at all, if so add header area. */
1254 if (info_ptr->total_size > 0
1255 || frame_pointer_needed
1256 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1257 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1259 offset = info_ptr->parameter_size;
1260 info_ptr->header_size = 4 * UNITS_PER_WORD;
1261 info_ptr->total_size += 4 * UNITS_PER_WORD;
1263 /* Calculate the offsets to save normal register pairs. */
1264 for (range = 0; range < STACK_REGS_MAX; range++)
1266 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1267 if (! reg_ptr->special_p)
1269 int first = reg_ptr->first;
1270 int last = reg_ptr->last;
1273 for (regno = first; regno <= last; regno++)
1274 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1275 && regno != FRAME_POINTER_REGNUM
1276 && (regno < FIRST_ARG_REGNUM
1277 || regno > LAST_ARG_REGNUM))
1279 info_ptr->reg_offset[regno] = offset;
1280 offset += 2 * UNITS_PER_WORD;
1285 /* Calculate the offsets to save normal single registers. */
1286 for (range = 0; range < STACK_REGS_MAX; range++)
1288 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1289 if (! reg_ptr->special_p)
1291 int first = reg_ptr->first;
1292 int last = reg_ptr->last;
1295 for (regno = first; regno <= last; regno++)
1296 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1297 && regno != FRAME_POINTER_REGNUM
1298 && (regno < FIRST_ARG_REGNUM
1299 || regno > LAST_ARG_REGNUM))
1301 info_ptr->reg_offset[regno] = offset;
1302 offset += UNITS_PER_WORD;
1307 /* Calculate the offset to save the local variables at. */
1308 offset = ADDR_ALIGN (offset, alignment);
1309 if (info_ptr->vars_size)
1311 info_ptr->vars_offset = offset;
1312 offset += info_ptr->vars_size;
1315 /* Align header to a dword-boundary. */
1316 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1318 /* Calculate the offsets in the fixed frame. */
1319 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1320 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1321 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1323 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1324 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1325 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1327 if (cfun->returns_struct)
1329 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1330 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1331 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1334 /* Calculate the offsets to store the arguments passed in registers
1335 for stdarg functions. The register pairs are first and the single
1336 register if any is last. The register save area starts on a
1338 if (info_ptr->stdarg_size)
1340 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1341 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1344 /* Skip the header. */
1345 offset += 4 * UNITS_PER_WORD;
1346 for (regno = first; regno <= last; regno++)
1348 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1350 info_ptr->reg_offset[regno] = offset;
1351 offset += 2 * UNITS_PER_WORD;
1353 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1355 info_ptr->reg_offset[regno] = offset;
1356 offset += UNITS_PER_WORD;
1362 if (reload_completed)
1363 frv_stack_cache = info_ptr;
1369 /* Print the information about the frv stack offsets, etc. when debugging. */
1372 frv_debug_stack (frv_stack_t *info)
1377 info = frv_stack_info ();
1379 fprintf (stderr, "\nStack information for function %s:\n",
1380 ((current_function_decl && DECL_NAME (current_function_decl))
1381 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1384 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1385 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1386 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1387 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1388 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1390 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1391 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1392 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1393 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1395 for (range = 0; range < STACK_REGS_MAX; range++)
1397 frv_stack_regs_t *regs = &(info->regs[range]);
1398 if ((regs->size_1word + regs->size_2words) > 0)
1400 int first = regs->first;
1401 int last = regs->last;
1404 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1405 regs->name, regs->size_1word + regs->size_2words,
1406 regs->size_1word, regs->size_2words);
1408 for (regno = first; regno <= last; regno++)
1410 if (info->save_p[regno] == REG_SAVE_1WORD)
1411 fprintf (stderr, " %s (%d)", reg_names[regno],
1412 info->reg_offset[regno]);
1414 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1415 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1416 reg_names[regno+1], info->reg_offset[regno]);
1419 fputc ('\n', stderr);
1429 /* Used during final to control the packing of insns. The value is
1430 1 if the current instruction should be packed with the next one,
1431 0 if it shouldn't or -1 if packing is disabled altogether. */
1433 static int frv_insn_packing_flag;
1435 /* True if the current function contains a far jump. */
1438 frv_function_contains_far_jump (void)
1440 rtx insn = get_insns ();
1442 && !(GET_CODE (insn) == JUMP_INSN
1443 /* Ignore tablejump patterns. */
1444 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1445 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1446 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1447 insn = NEXT_INSN (insn);
1448 return (insn != NULL);
1451 /* For the FRV, this function makes sure that a function with far jumps
1452 will return correctly. It also does the VLIW packing. */
1455 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1457 /* If no frame was created, check whether the function uses a call
1458 instruction to implement a far jump. If so, save the link in gr3 and
1459 replace all returns to LR with returns to GR3. GR3 is used because it
1460 is call-clobbered, because is not available to the register allocator,
1461 and because all functions that take a hidden argument pointer will have
1463 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1467 /* Just to check that the above comment is true. */
1468 if (regs_ever_live[GPR_FIRST + 3])
1471 /* Generate the instruction that saves the link register. */
1472 fprintf (file, "\tmovsg lr,gr3\n");
1474 /* Replace the LR with GR3 in *return_internal patterns. The insn
1475 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1476 simply emit a different assembly directive because bralr and jmpl
1477 execute in different units. */
1478 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1479 if (GET_CODE (insn) == JUMP_INSN)
1481 rtx pattern = PATTERN (insn);
1482 if (GET_CODE (pattern) == PARALLEL
1483 && XVECLEN (pattern, 0) >= 2
1484 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1485 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1487 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1488 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1489 REGNO (address) = GPR_FIRST + 3;
1496 /* Allow the garbage collector to free the nops created by frv_reorg. */
1497 memset (frv_nops, 0, sizeof (frv_nops));
1501 /* Return the next available temporary register in a given class. */
1504 frv_alloc_temp_reg (
1505 frv_tmp_reg_t *info, /* which registers are available */
1506 enum reg_class class, /* register class desired */
1507 enum machine_mode mode, /* mode to allocate register with */
1508 int mark_as_used, /* register not available after allocation */
1509 int no_abort) /* return NULL instead of aborting */
1511 int regno = info->next_reg[ (int)class ];
1512 int orig_regno = regno;
1513 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1518 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1519 && TEST_HARD_REG_BIT (info->regs, regno))
1522 if (++regno >= FIRST_PSEUDO_REGISTER)
1524 if (regno == orig_regno)
1533 nr = HARD_REGNO_NREGS (regno, mode);
1534 info->next_reg[ (int)class ] = regno + nr;
1537 for (i = 0; i < nr; i++)
1538 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1540 return gen_rtx_REG (mode, regno);
1544 /* Return an rtx with the value OFFSET, which will either be a register or a
1545 signed 12-bit integer. It can be used as the second operand in an "add"
1546 instruction, or as the index in a load or store.
1548 The function returns a constant rtx if OFFSET is small enough, otherwise
1549 it loads the constant into register OFFSET_REGNO and returns that. */
1551 frv_frame_offset_rtx (int offset)
1553 rtx offset_rtx = GEN_INT (offset);
1554 if (IN_RANGE_P (offset, -2048, 2047))
1558 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1559 if (IN_RANGE_P (offset, -32768, 32767))
1560 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1563 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1564 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1570 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1571 prologue and epilogue uses such expressions to access the stack. */
1573 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1575 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1577 frv_frame_offset_rtx (offset)));
1580 /* Generate a frame-related expression:
1582 (set REG (mem (plus (sp) (const_int OFFSET)))).
1584 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1585 instructions. Marking the expressions as frame-related is superfluous if
1586 the note contains just a single set. But if the note contains a PARALLEL
1587 or SEQUENCE that has several sets, each set must be individually marked
1588 as frame-related. */
1590 frv_dwarf_store (rtx reg, int offset)
1592 rtx set = gen_rtx_SET (VOIDmode,
1593 gen_rtx_MEM (GET_MODE (reg),
1594 plus_constant (stack_pointer_rtx,
1597 RTX_FRAME_RELATED_P (set) = 1;
1601 /* Emit a frame-related instruction whose pattern is PATTERN. The
1602 instruction is the last in a sequence that cumulatively performs the
1603 operation described by DWARF_PATTERN. The instruction is marked as
1604 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1607 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1609 rtx insn = emit_insn (pattern);
1610 RTX_FRAME_RELATED_P (insn) = 1;
1611 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1616 /* Emit instructions that transfer REG to or from the memory location (sp +
1617 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1618 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1619 function to store registers and only the epilogue uses it to load them.
1621 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1622 The generated instruction will use BASE as its base register. BASE may
1623 simply be the stack pointer, but if several accesses are being made to a
1624 region far away from the stack pointer, it may be more efficient to set
1625 up a temporary instead.
1627 Store instructions will be frame-related and will be annotated with the
1628 overall effect of the store. Load instructions will be followed by a
1629 (use) to prevent later optimizations from zapping them.
1631 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1632 as a temporary in such cases. */
1634 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1636 enum machine_mode mode = GET_MODE (reg);
1637 rtx mem = frv_frame_mem (mode,
1639 stack_offset - accessor->base_offset);
1641 if (accessor->op == FRV_LOAD)
1643 if (SPR_P (REGNO (reg)))
1645 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1646 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1647 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1650 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1651 emit_insn (gen_rtx_USE (VOIDmode, reg));
1655 if (SPR_P (REGNO (reg)))
1657 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1658 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1659 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1660 frv_dwarf_store (reg, stack_offset));
1662 else if (GET_MODE (reg) == DImode)
1664 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1665 with a separate save for each register. */
1666 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1667 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1668 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1669 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1670 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1671 gen_rtx_PARALLEL (VOIDmode,
1672 gen_rtvec (2, set1, set2)));
1675 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1676 frv_dwarf_store (reg, stack_offset));
1680 /* A function that uses frv_frame_access to transfer a group of registers to
1681 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1682 is the stack information generated by frv_stack_info, and REG_SET is the
1683 number of the register set to transfer. */
1685 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1689 frv_stack_regs_t *regs_info;
1692 regs_info = &info->regs[reg_set];
1693 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1694 if (info->save_p[regno])
1695 frv_frame_access (accessor,
1696 info->save_p[regno] == REG_SAVE_2WORDS
1697 ? gen_rtx_REG (DImode, regno)
1698 : gen_rtx_REG (SImode, regno),
1699 info->reg_offset[regno]);
1702 /* Save or restore callee-saved registers that are kept outside the frame
1703 header. The function saves the registers if OP is FRV_STORE and restores
1704 them if OP is FRV_LOAD. INFO is the stack information generated by
1707 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1709 frv_frame_accessor_t accessor;
1712 accessor.base = stack_pointer_rtx;
1713 accessor.base_offset = 0;
1714 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1715 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1716 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1720 /* Called after register allocation to add any instructions needed for the
1721 prologue. Using a prologue insn is favored compared to putting all of the
1722 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1723 it allows the scheduler to intermix instructions with the saves of
1724 the caller saved registers. In some cases, it might be necessary
1725 to emit a barrier instruction as the last insn to prevent such
1728 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1729 so that the debug info generation code can handle them properly. */
1731 frv_expand_prologue (void)
1733 frv_stack_t *info = frv_stack_info ();
1734 rtx sp = stack_pointer_rtx;
1735 rtx fp = frame_pointer_rtx;
1736 frv_frame_accessor_t accessor;
1738 if (TARGET_DEBUG_STACK)
1739 frv_debug_stack (info);
1741 if (info->total_size == 0)
1744 /* We're interested in three areas of the frame here:
1746 A: the register save area
1748 C: the header after B
1750 If the frame pointer isn't used, we'll have to set up A, B and C
1751 using the stack pointer. If the frame pointer is used, we'll access
1755 B: set up using sp or a temporary (see below)
1758 We set up B using the stack pointer if the frame is small enough.
1759 Otherwise, it's more efficient to copy the old stack pointer into a
1760 temporary and use that.
1762 Note that it's important to make sure the prologue and epilogue use the
1763 same registers to access A and C, since doing otherwise will confuse
1764 the aliasing code. */
1766 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1767 isn't used, the same method will serve for C. */
1768 accessor.op = FRV_STORE;
1769 if (frame_pointer_needed && info->total_size > 2048)
1773 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1774 accessor.base_offset = info->total_size;
1775 insn = emit_insn (gen_movsi (accessor.base, sp));
1779 accessor.base = stack_pointer_rtx;
1780 accessor.base_offset = 0;
1783 /* Allocate the stack space. */
1785 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1786 rtx dwarf_offset = GEN_INT (-info->total_size);
1788 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1791 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1794 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1795 and point the new one to that location. */
1796 if (frame_pointer_needed)
1798 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1800 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1801 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1803 rtx asm_src = plus_constant (accessor.base,
1804 fp_offset - accessor.base_offset);
1805 rtx dwarf_src = plus_constant (sp, fp_offset);
1807 /* Store the old frame pointer at (sp + FP_OFFSET). */
1808 frv_frame_access (&accessor, fp, fp_offset);
1810 /* Set up the new frame pointer. */
1811 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1812 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1814 /* Access region C from the frame pointer. */
1816 accessor.base_offset = fp_offset;
1819 /* Set up region C. */
1820 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1821 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1822 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1824 /* Set up region A. */
1825 frv_frame_access_standard_regs (FRV_STORE, info);
1827 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1828 scheduler from moving loads before the stores saving the registers. */
1829 if (info->stdarg_size > 0)
1830 emit_insn (gen_blockage ());
1832 /* Set up pic register/small data register for this function. */
1833 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1834 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1835 gen_rtx_REG (Pmode, LR_REGNO),
1836 gen_rtx_REG (SImode, OFFSET_REGNO)));
1840 /* Under frv, all of the work is done via frv_expand_epilogue, but
1841 this function provides a convenient place to do cleanup. */
1844 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1845 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1847 frv_stack_cache = (frv_stack_t *)0;
1849 /* Zap last used registers for conditional execution. */
1850 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1852 /* Release the bitmap of created insns. */
1853 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1857 /* Called after register allocation to add any instructions needed for the
1858 epilogue. Using an epilogue insn is favored compared to putting all of the
1859 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1860 it allows the scheduler to intermix instructions with the saves of
1861 the caller saved registers. In some cases, it might be necessary
1862 to emit a barrier instruction as the last insn to prevent such
1866 frv_expand_epilogue (bool emit_return)
1868 frv_stack_t *info = frv_stack_info ();
1869 rtx fp = frame_pointer_rtx;
1870 rtx sp = stack_pointer_rtx;
1874 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1876 /* Restore the stack pointer to its original value if alloca or the like
1878 if (! current_function_sp_is_unchanging)
1879 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1881 /* Restore the callee-saved registers that were used in this function. */
1882 frv_frame_access_standard_regs (FRV_LOAD, info);
1884 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1885 no return instruction should be emitted. */
1886 if (info->save_p[LR_REGNO])
1891 /* Use the same method to access the link register's slot as we did in
1892 the prologue. In other words, use the frame pointer if available,
1893 otherwise use the stack pointer.
1895 LR_OFFSET is the offset of the link register's slot from the start
1896 of the frame and MEM is a memory rtx for it. */
1897 lr_offset = info->reg_offset[LR_REGNO];
1898 if (frame_pointer_needed)
1899 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1901 mem = frv_frame_mem (Pmode, sp, lr_offset);
1903 /* Load the old link register into a GPR. */
1904 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1905 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1908 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1910 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1911 the load is preserved. */
1912 if (frame_pointer_needed)
1914 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1915 emit_insn (gen_rtx_USE (VOIDmode, fp));
1918 /* Deallocate the stack frame. */
1919 if (info->total_size != 0)
1921 rtx offset = frv_frame_offset_rtx (info->total_size);
1922 emit_insn (gen_stack_adjust (sp, sp, offset));
1925 /* If this function uses eh_return, add the final stack adjustment now. */
1926 if (current_function_calls_eh_return)
1927 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1930 emit_jump_insn (gen_epilogue_return (return_addr));
1933 rtx lr = return_addr;
1935 if (REGNO (return_addr) != LR_REGNO)
1937 lr = gen_rtx_REG (Pmode, LR_REGNO);
1938 emit_move_insn (lr, return_addr);
1941 emit_insn (gen_rtx_USE (VOIDmode, lr));
1946 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1949 frv_asm_output_mi_thunk (FILE *file,
1950 tree thunk_fndecl ATTRIBUTE_UNUSED,
1951 HOST_WIDE_INT delta,
1952 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1955 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1956 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1957 const char *name_jmp = reg_names[JUMP_REGNO];
1958 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1960 /* Do the add using an addi if possible. */
1961 if (IN_RANGE_P (delta, -2048, 2047))
1962 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1965 const char *const name_add = reg_names[TEMP_REGNO];
1966 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1967 parallel, delta, name_add);
1968 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1970 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1975 const char *name_pic = reg_names[FDPIC_REGNO];
1976 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1980 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1981 assemble_name (file, name_func);
1982 fprintf (file, "),%s\n", name_jmp);
1984 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1985 assemble_name (file, name_func);
1986 fprintf (file, "),%s\n", name_jmp);
1988 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1992 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1993 assemble_name (file, name_func);
1994 fprintf (file, "\t)), %s\n", name_jmp);
1999 fprintf (file, "\tsethi%s #hi(", parallel);
2000 assemble_name (file, name_func);
2001 fprintf (file, "),%s\n", name_jmp);
2003 fprintf (file, "\tsetlo #lo(");
2004 assemble_name (file, name_func);
2005 fprintf (file, "),%s\n", name_jmp);
2009 /* Use JUMP_REGNO as a temporary PIC register. */
2010 const char *name_lr = reg_names[LR_REGNO];
2011 const char *name_gppic = name_jmp;
2012 const char *name_tmp = reg_names[TEMP_REGNO];
2014 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2015 fprintf (file, "\tcall 1f\n");
2016 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2017 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2018 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2019 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2020 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2022 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2023 assemble_name (file, name_func);
2024 fprintf (file, "),%s\n", name_tmp);
2026 fprintf (file, "\tsetlo #gprello(");
2027 assemble_name (file, name_func);
2028 fprintf (file, "),%s\n", name_tmp);
2030 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2033 /* Jump to the function address. */
2034 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2038 /* A C expression which is nonzero if a function must have and use a frame
2039 pointer. This expression is evaluated in the reload pass. If its value is
2040 nonzero the function will have a frame pointer.
2042 The expression can in principle examine the current function and decide
2043 according to the facts, but on most machines the constant 0 or the constant
2044 1 suffices. Use 0 when the machine allows code to be generated with no
2045 frame pointer, and doing so saves some time or space. Use 1 when there is
2046 no possible advantage to avoiding a frame pointer.
2048 In certain cases, the compiler does not know how to produce valid code
2049 without a frame pointer. The compiler recognizes those cases and
2050 automatically gives the function a frame pointer regardless of what
2051 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2053 In a function that does not require a frame pointer, the frame pointer
2054 register can be allocated for ordinary usage, unless you mark it as a fixed
2055 register. See `FIXED_REGISTERS' for more information. */
2057 /* On frv, create a frame whenever we need to create stack. */
2060 frv_frame_pointer_required (void)
2062 /* If we forgoing the usual linkage requirements, we only need
2063 a frame pointer if the stack pointer might change. */
2064 if (!TARGET_LINKED_FP)
2065 return !current_function_sp_is_unchanging;
2067 if (! current_function_is_leaf)
2070 if (get_frame_size () != 0)
2076 if (!current_function_sp_is_unchanging)
2079 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2085 if (cfun->machine->frame_needed)
2092 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2093 initial difference between the specified pair of registers. This macro must
2094 be defined if `ELIMINABLE_REGS' is defined. */
2096 /* See frv_stack_info for more details on the frv stack frame. */
2099 frv_initial_elimination_offset (int from, int to)
2101 frv_stack_t *info = frv_stack_info ();
2104 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2105 ret = info->total_size - info->pretend_size;
2107 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2108 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2110 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2111 ret = (info->total_size
2112 - info->reg_offset[FRAME_POINTER_REGNUM]
2113 - info->pretend_size);
2118 if (TARGET_DEBUG_STACK)
2119 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2120 reg_names [from], reg_names[to], ret);
2126 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2129 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2130 enum machine_mode mode,
2131 tree type ATTRIBUTE_UNUSED,
2135 if (TARGET_DEBUG_ARG)
2137 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2138 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2142 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2145 frv_expand_builtin_saveregs (void)
2147 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2149 if (TARGET_DEBUG_ARG)
2150 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2153 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2157 /* Expand __builtin_va_start to do the va_start macro. */
2160 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2163 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2165 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2166 GEN_INT (UNITS_PER_WORD * num));
2168 if (TARGET_DEBUG_ARG)
2170 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2171 cfun->args_info, num);
2173 debug_rtx (nextarg);
2176 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2177 make_tree (ptr_type_node, nextarg));
2178 TREE_SIDE_EFFECTS (t) = 1;
2180 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2184 /* Expand a block move operation, and return 1 if successful. Return 0
2185 if we should let the compiler generate normal code.
2187 operands[0] is the destination
2188 operands[1] is the source
2189 operands[2] is the length
2190 operands[3] is the alignment */
2192 /* Maximum number of loads to do before doing the stores */
2193 #ifndef MAX_MOVE_REG
2194 #define MAX_MOVE_REG 4
2197 /* Maximum number of total loads to do. */
2198 #ifndef TOTAL_MOVE_REG
2199 #define TOTAL_MOVE_REG 8
2203 frv_expand_block_move (rtx operands[])
2205 rtx orig_dest = operands[0];
2206 rtx orig_src = operands[1];
2207 rtx bytes_rtx = operands[2];
2208 rtx align_rtx = operands[3];
2209 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2222 rtx stores[MAX_MOVE_REG];
2224 enum machine_mode mode;
2226 /* If this is not a fixed size move, just call memcpy. */
2230 /* If this is not a fixed size alignment, abort. */
2231 if (GET_CODE (align_rtx) != CONST_INT)
2234 align = INTVAL (align_rtx);
2236 /* Anything to move? */
2237 bytes = INTVAL (bytes_rtx);
2241 /* Don't support real large moves. */
2242 if (bytes > TOTAL_MOVE_REG*align)
2245 /* Move the address into scratch registers. */
2246 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2247 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2249 num_reg = offset = 0;
2250 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2252 /* Calculate the correct offset for src/dest. */
2256 dest_addr = dest_reg;
2260 src_addr = plus_constant (src_reg, offset);
2261 dest_addr = plus_constant (dest_reg, offset);
2264 /* Generate the appropriate load and store, saving the stores
2266 if (bytes >= 4 && align >= 4)
2268 else if (bytes >= 2 && align >= 2)
2273 move_bytes = GET_MODE_SIZE (mode);
2274 tmp_reg = gen_reg_rtx (mode);
2275 src_mem = change_address (orig_src, mode, src_addr);
2276 dest_mem = change_address (orig_dest, mode, dest_addr);
2277 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2278 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2280 if (num_reg >= MAX_MOVE_REG)
2282 for (i = 0; i < num_reg; i++)
2283 emit_insn (stores[i]);
2288 for (i = 0; i < num_reg; i++)
2289 emit_insn (stores[i]);
2295 /* Expand a block clear operation, and return 1 if successful. Return 0
2296 if we should let the compiler generate normal code.
2298 operands[0] is the destination
2299 operands[1] is the length
2300 operands[2] is the alignment */
2303 frv_expand_block_clear (rtx operands[])
2305 rtx orig_dest = operands[0];
2306 rtx bytes_rtx = operands[1];
2307 rtx align_rtx = operands[2];
2308 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2317 enum machine_mode mode;
2319 /* If this is not a fixed size move, just call memcpy. */
2323 /* If this is not a fixed size alignment, abort. */
2324 if (GET_CODE (align_rtx) != CONST_INT)
2327 align = INTVAL (align_rtx);
2329 /* Anything to move? */
2330 bytes = INTVAL (bytes_rtx);
2334 /* Don't support real large clears. */
2335 if (bytes > TOTAL_MOVE_REG*align)
2338 /* Move the address into a scratch register. */
2339 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2341 num_reg = offset = 0;
2342 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2344 /* Calculate the correct offset for src/dest. */
2345 dest_addr = ((offset == 0)
2347 : plus_constant (dest_reg, offset));
2349 /* Generate the appropriate store of gr0. */
2350 if (bytes >= 4 && align >= 4)
2352 else if (bytes >= 2 && align >= 2)
2357 clear_bytes = GET_MODE_SIZE (mode);
2358 dest_mem = change_address (orig_dest, mode, dest_addr);
2359 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2366 /* The following variable is used to output modifiers of assembler
2367 code of the current output insn. */
2369 static rtx *frv_insn_operands;
2371 /* The following function is used to add assembler insn code suffix .p
2372 if it is necessary. */
2375 frv_asm_output_opcode (FILE *f, const char *ptr)
2379 if (frv_insn_packing_flag <= 0)
2382 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2385 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2386 || (*ptr >= 'A' && *ptr <= 'Z')))
2388 int letter = *ptr++;
2391 frv_print_operand (f, frv_insn_operands [c], letter);
2392 while ((c = *ptr) >= '0' && c <= '9')
2404 /* Set up the packing bit for the current output insn. Note that this
2405 function is not called for asm insns. */
2408 frv_final_prescan_insn (rtx insn, rtx *opvec,
2409 int noperands ATTRIBUTE_UNUSED)
2413 if (frv_insn_packing_flag >= 0)
2415 frv_insn_operands = opvec;
2416 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2418 else if (recog_memoized (insn) >= 0
2419 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2420 /* Packing optimizations have been disabled, but INSN can only
2421 be issued in M1. Insert an mnop in M0. */
2422 fprintf (asm_out_file, "\tmnop.p\n");
2428 /* A C expression whose value is RTL representing the address in a stack frame
2429 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2430 an RTL expression for the address of the stack frame itself.
2432 If you don't define this macro, the default is to return the value of
2433 FRAMEADDR--that is, the stack frame address is also the address of the stack
2434 word that points to the previous frame. */
2436 /* The default is correct, but we need to make sure the frame gets created. */
2438 frv_dynamic_chain_address (rtx frame)
2440 cfun->machine->frame_needed = 1;
2445 /* A C expression whose value is RTL representing the value of the return
2446 address for the frame COUNT steps up from the current frame, after the
2447 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2448 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2451 The value of the expression must always be the correct address when COUNT is
2452 zero, but may be `NULL_RTX' if there is not way to determine the return
2453 address of other frames. */
2456 frv_return_addr_rtx (int count, rtx frame)
2460 cfun->machine->frame_needed = 1;
2461 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2464 /* Given a memory reference MEMREF, interpret the referenced memory as
2465 an array of MODE values, and return a reference to the element
2466 specified by INDEX. Assume that any pre-modification implicit in
2467 MEMREF has already happened.
2469 MEMREF must be a legitimate operand for modes larger than SImode.
2470 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2471 this function cannot handle. */
2473 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2475 rtx base = XEXP (memref, 0);
2476 if (GET_CODE (base) == PRE_MODIFY)
2477 base = XEXP (base, 0);
2478 return change_address (memref, mode,
2479 plus_constant (base, index * GET_MODE_SIZE (mode)));
2483 /* Print a memory address as an operand to reference that memory location. */
2485 frv_print_operand_address (FILE * stream, rtx x)
2487 if (GET_CODE (x) == MEM)
2490 switch (GET_CODE (x))
2493 fputs (reg_names [ REGNO (x)], stream);
2497 fprintf (stream, "%ld", (long) INTVAL (x));
2501 assemble_name (stream, XSTR (x, 0));
2506 output_addr_const (stream, x);
2513 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2518 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2520 int regno = true_regnum (x);
2522 fputs (reg_names[regno], stream);
2524 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2527 /* Print a memory reference suitable for the ld/st instructions. */
2530 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2532 struct frv_unspec unspec;
2536 switch (GET_CODE (x))
2543 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2545 x1 = XEXP (XEXP (x, 1), 1);
2555 if (GET_CODE (x0) == CONST_INT)
2563 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2572 else if (GET_CODE (x1) != CONST_INT)
2573 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2576 fputs ("@(", stream);
2578 fputs (reg_names[GPR_R0], stream);
2579 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2580 frv_print_operand_memory_reference_reg (stream, x0);
2582 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2584 fputs (",", stream);
2586 fputs (reg_names [GPR_R0], stream);
2590 switch (GET_CODE (x1))
2594 frv_print_operand_memory_reference_reg (stream, x1);
2598 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2602 if (!frv_const_unspec_p (x1, &unspec))
2603 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2604 frv_output_const_unspec (stream, &unspec);
2608 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2612 fputs (")", stream);
2616 /* Return 2 for likely branches and 0 for non-likely branches */
2618 #define FRV_JUMP_LIKELY 2
2619 #define FRV_JUMP_NOT_LIKELY 0
2622 frv_print_operand_jump_hint (rtx insn)
2627 HOST_WIDE_INT prob = -1;
2628 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2630 if (GET_CODE (insn) != JUMP_INSN)
2633 /* Assume any non-conditional jump is likely. */
2634 if (! any_condjump_p (insn))
2635 ret = FRV_JUMP_LIKELY;
2639 labelref = condjump_label (insn);
2642 rtx label = XEXP (labelref, 0);
2643 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2648 note = find_reg_note (insn, REG_BR_PROB, 0);
2650 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2654 prob = INTVAL (XEXP (note, 0));
2655 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2657 : FRV_JUMP_NOT_LIKELY);
2669 case UNKNOWN: direction = "unknown jump direction"; break;
2670 case BACKWARD: direction = "jump backward"; break;
2671 case FORWARD: direction = "jump forward"; break;
2675 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2676 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2677 (long)INSN_UID (insn), direction, (long)prob,
2678 (long)REG_BR_PROB_BASE, ret);
2686 /* Print an operand to an assembler instruction.
2688 `%' followed by a letter and a digit says to output an operand in an
2689 alternate fashion. Four letters have standard, built-in meanings described
2690 below. The machine description macro `PRINT_OPERAND' can define additional
2691 letters with nonstandard meanings.
2693 `%cDIGIT' can be used to substitute an operand that is a constant value
2694 without the syntax that normally indicates an immediate operand.
2696 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2699 `%aDIGIT' can be used to substitute an operand as if it were a memory
2700 reference, with the actual operand treated as the address. This may be
2701 useful when outputting a "load address" instruction, because often the
2702 assembler syntax for such an instruction requires you to write the operand
2703 as if it were a memory reference.
2705 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2707 `%=' outputs a number which is unique to each instruction in the entire
2708 compilation. This is useful for making local labels to be referred to more
2709 than once in a single template that generates multiple assembler
2712 `%' followed by a punctuation character specifies a substitution that does
2713 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2714 assembler code. Other nonstandard cases can be defined in the
2715 `PRINT_OPERAND' macro. You must also define which punctuation characters
2716 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2719 frv_print_operand (FILE * file, rtx x, int code)
2721 struct frv_unspec unspec;
2722 HOST_WIDE_INT value;
2725 if (code != 0 && !isalpha (code))
2728 else if (GET_CODE (x) == CONST_INT)
2731 else if (GET_CODE (x) == CONST_DOUBLE)
2733 if (GET_MODE (x) == SFmode)
2738 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2739 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2743 else if (GET_MODE (x) == VOIDmode)
2744 value = CONST_DOUBLE_LOW (x);
2747 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2758 fputs (reg_names[GPR_R0], file);
2762 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2766 /* Output small data area base register (gr16). */
2767 fputs (reg_names[SDA_BASE_REG], file);
2771 /* Output pic register (gr17). */
2772 fputs (reg_names[PIC_REGNO], file);
2776 /* Output the temporary integer CCR register. */
2777 fputs (reg_names[ICR_TEMP], file);
2781 /* Output the temporary integer CC register. */
2782 fputs (reg_names[ICC_TEMP], file);
2785 /* case 'a': print an address. */
2788 /* Print appropriate test for integer branch false operation. */
2789 switch (GET_CODE (x))
2792 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2794 case EQ: fputs ("ne", file); break;
2795 case NE: fputs ("eq", file); break;
2796 case LT: fputs ("ge", file); break;
2797 case LE: fputs ("gt", file); break;
2798 case GT: fputs ("le", file); break;
2799 case GE: fputs ("lt", file); break;
2800 case LTU: fputs ("nc", file); break;
2801 case LEU: fputs ("hi", file); break;
2802 case GTU: fputs ("ls", file); break;
2803 case GEU: fputs ("c", file); break;
2807 /* case 'c': print a constant without the constant prefix. If
2808 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2811 /* Print appropriate test for integer branch true operation. */
2812 switch (GET_CODE (x))
2815 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2817 case EQ: fputs ("eq", file); break;
2818 case NE: fputs ("ne", file); break;
2819 case LT: fputs ("lt", file); break;
2820 case LE: fputs ("le", file); break;
2821 case GT: fputs ("gt", file); break;
2822 case GE: fputs ("ge", file); break;
2823 case LTU: fputs ("c", file); break;
2824 case LEU: fputs ("ls", file); break;
2825 case GTU: fputs ("hi", file); break;
2826 case GEU: fputs ("nc", file); break;
2831 /* Print 1 for a NE and 0 for an EQ to give the final argument
2832 for a conditional instruction. */
2833 if (GET_CODE (x) == NE)
2836 else if (GET_CODE (x) == EQ)
2840 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2844 /* Print appropriate test for floating point branch false operation. */
2845 switch (GET_CODE (x))
2848 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2850 case EQ: fputs ("ne", file); break;
2851 case NE: fputs ("eq", file); break;
2852 case LT: fputs ("uge", file); break;
2853 case LE: fputs ("ug", file); break;
2854 case GT: fputs ("ule", file); break;
2855 case GE: fputs ("ul", file); break;
2860 /* Print appropriate test for floating point branch true operation. */
2861 switch (GET_CODE (x))
2864 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2866 case EQ: fputs ("eq", file); break;
2867 case NE: fputs ("ne", file); break;
2868 case LT: fputs ("lt", file); break;
2869 case LE: fputs ("le", file); break;
2870 case GT: fputs ("gt", file); break;
2871 case GE: fputs ("ge", file); break;
2876 /* Print appropriate GOT function. */
2877 if (GET_CODE (x) != CONST_INT)
2878 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2879 fputs (unspec_got_name (INTVAL (x)), file);
2883 /* Print 'i' if the operand is a constant, or is a memory reference that
2885 if (GET_CODE (x) == MEM)
2886 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2887 ? XEXP (XEXP (x, 0), 1)
2889 else if (GET_CODE (x) == PLUS)
2892 switch (GET_CODE (x))
2906 /* For jump instructions, print 'i' if the operand is a constant or
2907 is an expression that adds a constant. */
2908 if (GET_CODE (x) == CONST_INT)
2913 if (GET_CODE (x) == CONST_INT
2914 || (GET_CODE (x) == PLUS
2915 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2916 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2922 /* Print the lower register of a double word register pair */
2923 if (GET_CODE (x) == REG)
2924 fputs (reg_names[ REGNO (x)+1 ], file);
2926 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2929 /* case 'l': print a LABEL_REF. */
2933 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2934 for the second word of double memory operations. */
2935 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2936 switch (GET_CODE (x))
2939 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2942 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2950 frv_print_operand_memory_reference (file, x, offset);
2956 /* Print the opcode of a command. */
2957 switch (GET_CODE (x))
2960 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2962 case PLUS: fputs ("add", file); break;
2963 case MINUS: fputs ("sub", file); break;
2964 case AND: fputs ("and", file); break;
2965 case IOR: fputs ("or", file); break;
2966 case XOR: fputs ("xor", file); break;
2967 case ASHIFT: fputs ("sll", file); break;
2968 case ASHIFTRT: fputs ("sra", file); break;
2969 case LSHIFTRT: fputs ("srl", file); break;
2973 /* case 'n': negate and print a constant int. */
2976 /* Print PIC label using operand as the number. */
2977 if (GET_CODE (x) != CONST_INT)
2978 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2980 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2984 /* Print 'u' if the operand is a update load/store. */
2985 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2990 /* If value is 0, print gr0, otherwise it must be a register. */
2991 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2992 fputs (reg_names[GPR_R0], file);
2994 else if (GET_CODE (x) == REG)
2995 fputs (reg_names [REGNO (x)], file);
2998 fatal_insn ("Bad insn in frv_print_operand, z case", x);
3002 /* Print constant in hex. */
3003 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3005 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3012 if (GET_CODE (x) == REG)
3013 fputs (reg_names [REGNO (x)], file);
3015 else if (GET_CODE (x) == CONST_INT
3016 || GET_CODE (x) == CONST_DOUBLE)
3017 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3019 else if (frv_const_unspec_p (x, &unspec))
3020 frv_output_const_unspec (file, &unspec);
3022 else if (GET_CODE (x) == MEM)
3023 frv_print_operand_address (file, XEXP (x, 0));
3025 else if (CONSTANT_ADDRESS_P (x))
3026 frv_print_operand_address (file, x);
3029 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3034 fatal_insn ("frv_print_operand: unknown code", x);
3042 /* A C statement (sans semicolon) for initializing the variable CUM for the
3043 state at the beginning of the argument list. The variable has type
3044 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3045 of the function which will receive the args, or 0 if the args are to a
3046 compiler support library function. The value of INDIRECT is nonzero when
3047 processing an indirect call, for example a call through a function pointer.
3048 The value of INDIRECT is zero for a call to an explicitly named function, a
3049 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3050 arguments for the function being compiled.
3052 When processing a call to a compiler support library function, LIBNAME
3053 identifies which one. It is a `symbol_ref' rtx which contains the name of
3054 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3055 being processed. Thus, each time this macro is called, either LIBNAME or
3056 FNTYPE is nonzero, but never both of them at once. */
3059 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3065 *cum = FIRST_ARG_REGNUM;
3067 if (TARGET_DEBUG_ARG)
3069 fprintf (stderr, "\ninit_cumulative_args:");
3070 if (!fndecl && fntype)
3071 fputs (" indirect", stderr);
3074 fputs (" incoming", stderr);
3078 tree ret_type = TREE_TYPE (fntype);
3079 fprintf (stderr, " return=%s,",
3080 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3083 if (libname && GET_CODE (libname) == SYMBOL_REF)
3084 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3086 if (cfun->returns_struct)
3087 fprintf (stderr, " return-struct");
3089 putc ('\n', stderr);
3094 /* Return true if we should pass an argument on the stack rather than
3098 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3100 if (mode == BLKmode)
3104 return AGGREGATE_TYPE_P (type);
3107 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3108 argument with the specified mode and type. If it is not defined,
3109 `PARM_BOUNDARY' is used for all arguments. */
3112 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3113 tree type ATTRIBUTE_UNUSED)
3115 return BITS_PER_WORD;
3119 frv_function_arg (CUMULATIVE_ARGS *cum,
3120 enum machine_mode mode,
3121 tree type ATTRIBUTE_UNUSED,
3123 int incoming ATTRIBUTE_UNUSED)
3125 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3130 /* Return a marker for use in the call instruction. */
3131 if (xmode == VOIDmode)
3137 else if (arg_num <= LAST_ARG_REGNUM)
3139 ret = gen_rtx_REG (xmode, arg_num);
3140 debstr = reg_names[arg_num];
3149 if (TARGET_DEBUG_ARG)
3151 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3152 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3158 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3159 advance past an argument in the argument list. The values MODE, TYPE and
3160 NAMED describe that argument. Once this is done, the variable CUM is
3161 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3163 This macro need not do anything if the argument in question was passed on
3164 the stack. The compiler knows how to track the amount of stack space used
3165 for arguments without any special help. */
3168 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3169 enum machine_mode mode,
3170 tree type ATTRIBUTE_UNUSED,
3173 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3174 int bytes = GET_MODE_SIZE (xmode);
3175 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3178 *cum = arg_num + words;
3180 if (TARGET_DEBUG_ARG)
3182 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3183 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3187 /* A C expression for the number of words, at the beginning of an argument,
3188 must be put in registers. The value must be zero for arguments that are
3189 passed entirely in registers or that are entirely pushed on the stack.
3191 On some machines, certain arguments must be passed partially in registers
3192 and partially in memory. On these machines, typically the first N words of
3193 arguments are passed in registers, and the rest on the stack. If a
3194 multi-word argument (a `double' or a structure) crosses that boundary, its
3195 first few words must be passed in registers and the rest must be pushed.
3196 This macro tells the compiler when this occurs, and how many of the words
3197 should go in registers.
3199 `FUNCTION_ARG' for these arguments should return the first register to be
3200 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3201 the called function. */
3204 frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum,
3205 enum machine_mode mode,
3206 tree type ATTRIBUTE_UNUSED,
3207 int named ATTRIBUTE_UNUSED)
3209 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3210 int bytes = GET_MODE_SIZE (xmode);
3211 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3215 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3216 ? LAST_ARG_REGNUM - arg_num + 1
3219 if (TARGET_DEBUG_ARG && ret)
3220 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3227 /* Return true if a register is ok to use as a base or index register. */
3229 static FRV_INLINE int
3230 frv_regno_ok_for_base_p (int regno, int strict_p)
3236 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3238 if (regno == ARG_POINTER_REGNUM)
3241 return (regno >= FIRST_PSEUDO_REGISTER);
3245 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3246 RTX) is a legitimate memory address on the target machine for a memory
3247 operand of mode MODE.
3249 It usually pays to define several simpler macros to serve as subroutines for
3250 this one. Otherwise it may be too complicated to understand.
3252 This macro must exist in two variants: a strict variant and a non-strict
3253 one. The strict variant is used in the reload pass. It must be defined so
3254 that any pseudo-register that has not been allocated a hard register is
3255 considered a memory reference. In contexts where some kind of register is
3256 required, a pseudo-register with no hard register must be rejected.
3258 The non-strict variant is used in other passes. It must be defined to
3259 accept all pseudo-registers in every context where some kind of register is
3262 Compiler source files that want to use the strict variant of this macro
3263 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3264 conditional to define the strict variant in that case and the non-strict
3267 Subroutines to check for acceptable registers for various purposes (one for
3268 base registers, one for index registers, and so on) are typically among the
3269 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3270 subroutine macros need have two variants; the higher levels of macros may be
3271 the same whether strict or not.
3273 Normally, constant addresses which are the sum of a `symbol_ref' and an
3274 integer are stored inside a `const' RTX to mark them as constant.
3275 Therefore, there is no need to recognize such sums specifically as
3276 legitimate addresses. Normally you would simply recognize any `const' as
3279 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3280 are not marked with `const'. It assumes that a naked `plus' indicates
3281 indexing. If so, then you *must* reject such naked constant sums as
3282 illegitimate addresses, so that none of them will be given to
3283 `PRINT_OPERAND_ADDRESS'.
3285 On some machines, whether a symbolic address is legitimate depends on the
3286 section that the address refers to. On these machines, define the macro
3287 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3288 then check for it here. When you see a `const', you will have to look
3289 inside it to find the `symbol_ref' in order to determine the section.
3291 The best way to modify the name string is by adding text to the beginning,
3292 with suitable punctuation to prevent any ambiguity. Allocate the new name
3293 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3294 remove and decode the added text and output the name accordingly, and define
3295 `(* targetm.strip_name_encoding)' to access the original name string.
3297 You can check the information stored here into the `symbol_ref' in the
3298 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3299 `PRINT_OPERAND_ADDRESS'. */
3302 frv_legitimate_address_p (enum machine_mode mode,
3306 int allow_double_reg_p)
3310 HOST_WIDE_INT value;
3313 switch (GET_CODE (x))
3320 if (GET_CODE (x) != REG)
3326 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3332 if (GET_CODE (x0) != REG
3333 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3334 || GET_CODE (x1) != PLUS
3335 || ! rtx_equal_p (x0, XEXP (x1, 0))
3336 || GET_CODE (XEXP (x1, 1)) != REG
3337 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3344 /* 12 bit immediate */
3349 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3351 /* If we can't use load/store double operations, make sure we can
3352 address the second word. */
3353 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3354 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3363 if (GET_CODE (x0) == SUBREG)
3364 x0 = SUBREG_REG (x0);
3366 if (GET_CODE (x0) != REG)
3369 regno0 = REGNO (x0);
3370 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3373 switch (GET_CODE (x1))
3379 x1 = SUBREG_REG (x1);
3380 if (GET_CODE (x1) != REG)
3386 /* Do not allow reg+reg addressing for modes > 1 word if we
3387 can't depend on having move double instructions. */
3388 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3391 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3395 /* 12 bit immediate */
3400 value = INTVAL (x1);
3401 ret = IN_RANGE_P (value, -2048, 2047);
3403 /* If we can't use load/store double operations, make sure we can
3404 address the second word. */
3405 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3406 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3411 if (!condexec_p && got12_operand (x1, VOIDmode))
3419 if (TARGET_DEBUG_ADDR)
3421 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3422 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3423 (condexec_p) ? ", inside conditional code" : "");
3431 frv_legitimize_address (rtx x ATTRIBUTE_UNUSED,
3432 rtx oldx ATTRIBUTE_UNUSED,
3433 enum machine_mode mode ATTRIBUTE_UNUSED)
3438 /* Test whether a local function descriptor is canonical, i.e.,
3439 whether we can use FUNCDESC_GOTOFF to compute the address of the
3443 frv_local_funcdesc_p (rtx fnx)
3446 enum symbol_visibility vis;
3449 if (! SYMBOL_REF_LOCAL_P (fnx))
3452 fn = SYMBOL_REF_DECL (fnx);
3457 vis = DECL_VISIBILITY (fn);
3459 if (vis == VISIBILITY_PROTECTED)
3460 /* Private function descriptors for protected functions are not
3461 canonical. Temporarily change the visibility to global. */
3462 vis = VISIBILITY_DEFAULT;
3463 else if (flag_shlib)
3464 /* If we're already compiling for a shared library (that, unlike
3465 executables, can't assume that the existence of a definition
3466 implies local binding), we can skip the re-testing. */
3469 ret = default_binds_local_p_1 (fn, flag_pic);
3471 DECL_VISIBILITY (fn) = vis;
3476 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3480 frv_gen_GPsym2reg (rtx dest, rtx src)
3482 tree gp = get_identifier ("_gp");
3483 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3485 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3489 unspec_got_name (int i)
3493 case R_FRV_GOT12: return "got12";
3494 case R_FRV_GOTHI: return "gothi";
3495 case R_FRV_GOTLO: return "gotlo";
3496 case R_FRV_FUNCDESC: return "funcdesc";
3497 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3498 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3499 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3500 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3501 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3502 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3503 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3504 case R_FRV_GOTOFF12: return "gotoff12";
3505 case R_FRV_GOTOFFHI: return "gotoffhi";
3506 case R_FRV_GOTOFFLO: return "gotofflo";
3507 case R_FRV_GPREL12: return "gprel12";
3508 case R_FRV_GPRELHI: return "gprelhi";
3509 case R_FRV_GPRELLO: return "gprello";
3514 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3515 is added inside the relocation operator. */
3518 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3520 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3521 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3522 fputs (")", stream);
3525 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3526 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3527 otherwise return ORIG_X. */
3530 frv_find_base_term (rtx x)
3532 struct frv_unspec unspec;
3534 if (frv_const_unspec_p (x, &unspec)
3535 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3536 return plus_constant (unspec.symbol, unspec.offset);
3541 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3542 the operand is used by a predicated instruction. */
3545 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3547 return ((GET_MODE (op) == mode || mode == VOIDmode)
3548 && GET_CODE (op) == MEM
3549 && frv_legitimate_address_p (mode, XEXP (op, 0),
3550 reload_completed, condexec_p, FALSE));
3554 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3556 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3557 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3563 rvrtx = operands[0];
3567 addr = XEXP (operands[0], 0);
3569 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3570 any calls that would involve a PLT, but can't tell, since we
3571 don't know whether an extern function is going to be provided by
3572 a separate translation unit or imported from a separate module.
3573 When compiling for shared libraries, if the function has default
3574 visibility, we assume it's overridable, so we inline the PLT, but
3575 for executables, we don't really have a way to make a good
3576 decision: a function is as likely to be imported from a shared
3577 library as it is to be defined in the executable itself. We
3578 assume executables will get global functions defined locally,
3579 whereas shared libraries will have them potentially overridden,
3580 so we only inline PLTs when compiling for shared libraries.
3582 In order to mark a function as local to a shared library, any
3583 non-default visibility attribute suffices. Unfortunately,
3584 there's no simple way to tag a function declaration as ``in a
3585 different module'', which we could then use to trigger PLT
3586 inlining on executables. There's -minline-plt, but it affects
3587 all external functions, so one would have to also mark function
3588 declarations available in the same module with non-default
3589 visibility, which is advantageous in itself. */
3590 if (GET_CODE (addr) == SYMBOL_REF
3591 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3595 dest = gen_reg_rtx (SImode);
3597 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3598 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3600 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3601 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3603 cfun->uses_pic_offset_table = TRUE;
3606 else if (GET_CODE (addr) == SYMBOL_REF)
3608 /* These are always either local, or handled through a local
3611 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3612 operands[2], picreg, lr);
3614 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3618 else if (! ldd_address_operand (addr, Pmode))
3619 addr = force_reg (Pmode, addr);
3621 picreg = gen_reg_rtx (DImode);
3622 emit_insn (gen_movdi_ldd (picreg, addr));
3624 if (sibcall && ret_value)
3625 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3627 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3629 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3631 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3635 /* An address operand that may use a pair of registers, an addressing
3636 mode that we reject in general. */
3639 ldd_address_operand (rtx x, enum machine_mode mode)
3641 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3644 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3648 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3650 if (GET_MODE (op) != mode && mode != VOIDmode)
3652 if (GET_CODE (op) != REG)
3654 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3659 /* Return 1 is OP is a memory operand, or will be turned into one by
3663 frv_load_operand (rtx op, enum machine_mode mode)
3665 if (GET_MODE (op) != mode && mode != VOIDmode)
3668 if (reload_in_progress)
3671 if (GET_CODE (tmp) == SUBREG)
3672 tmp = SUBREG_REG (tmp);
3673 if (GET_CODE (tmp) == REG
3674 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3675 op = reg_equiv_memory_loc[REGNO (tmp)];
3678 return op && memory_operand (op, mode);
3682 /* Return 1 if operand is a GPR register or a FPR register. */
3685 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3689 if (GET_MODE (op) != mode && mode != VOIDmode)
3692 if (GET_CODE (op) == SUBREG)
3694 if (GET_CODE (SUBREG_REG (op)) != REG)
3695 return register_operand (op, mode);
3697 op = SUBREG_REG (op);
3700 if (GET_CODE (op) != REG)
3704 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3710 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3713 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3715 if (GET_CODE (op) == CONST_INT)
3716 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3718 if (got12_operand (op, mode))
3721 if (GET_MODE (op) != mode && mode != VOIDmode)
3724 if (GET_CODE (op) == SUBREG)
3726 if (GET_CODE (SUBREG_REG (op)) != REG)
3727 return register_operand (op, mode);
3729 op = SUBREG_REG (op);
3732 if (GET_CODE (op) != REG)
3735 return GPR_OR_PSEUDO_P (REGNO (op));
3738 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3739 signed immediate. */
3742 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3746 if (GET_CODE (op) == CONST_INT)
3747 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3749 if (GET_MODE (op) != mode && mode != VOIDmode)
3752 if (GET_CODE (op) == SUBREG)
3754 if (GET_CODE (SUBREG_REG (op)) != REG)
3755 return register_operand (op, mode);
3757 op = SUBREG_REG (op);
3760 if (GET_CODE (op) != REG)
3764 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3770 /* Return 1 if operand is a register or 6 bit signed immediate. */
3773 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3775 if (GET_CODE (op) == CONST_INT)
3776 return IN_RANGE_P (INTVAL (op), -32, 31);
3778 if (GET_MODE (op) != mode && mode != VOIDmode)
3781 if (GET_CODE (op) == SUBREG)
3783 if (GET_CODE (SUBREG_REG (op)) != REG)
3784 return register_operand (op, mode);
3786 op = SUBREG_REG (op);
3789 if (GET_CODE (op) != REG)
3792 return FPR_OR_PSEUDO_P (REGNO (op));
3795 /* Return 1 if operand is a register or 10 bit signed immediate. */
3798 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3800 if (GET_CODE (op) == CONST_INT)
3801 return IN_RANGE_P (INTVAL (op), -512, 511);
3803 if (GET_MODE (op) != mode && mode != VOIDmode)
3806 if (GET_CODE (op) == SUBREG)
3808 if (GET_CODE (SUBREG_REG (op)) != REG)
3809 return register_operand (op, mode);
3811 op = SUBREG_REG (op);
3814 if (GET_CODE (op) != REG)
3817 return GPR_OR_PSEUDO_P (REGNO (op));
3820 /* Return 1 if operand is a register or an integer immediate. */
3823 gpr_or_int_operand (rtx op, enum machine_mode mode)
3825 if (GET_CODE (op) == CONST_INT)
3828 if (GET_MODE (op) != mode && mode != VOIDmode)
3831 if (GET_CODE (op) == SUBREG)
3833 if (GET_CODE (SUBREG_REG (op)) != REG)
3834 return register_operand (op, mode);
3836 op = SUBREG_REG (op);
3839 if (GET_CODE (op) != REG)
3842 return GPR_OR_PSEUDO_P (REGNO (op));
3845 /* Return 1 if operand is a 12 bit signed immediate. */
3848 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3850 if (GET_CODE (op) != CONST_INT)
3853 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3856 /* Return 1 if operand is a 6 bit signed immediate. */
3859 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3861 if (GET_CODE (op) != CONST_INT)
3864 return IN_RANGE_P (INTVAL (op), -32, 31);
3867 /* Return 1 if operand is a 5 bit signed immediate. */
3870 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3872 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3875 /* Return 1 if operand is a 5 bit unsigned immediate. */
3878 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3880 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3883 /* Return 1 if operand is a 4 bit unsigned immediate. */
3886 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3888 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3891 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3894 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3896 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3899 /* Return 1 if operand is an integer constant that takes 2 instructions
3900 to load up and can be split into sethi/setlo instructions.. */
3903 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3905 HOST_WIDE_INT value;
3909 switch (GET_CODE (op))
3918 return (flag_pic == 0);
3921 if (flag_pic || TARGET_FDPIC)
3925 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3927 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
3933 /* small data references are already 1 word */
3934 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3937 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3940 if (GET_MODE (op) == SFmode)
3942 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3943 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3945 return ! IN_RANGE_P (value, -32768, 32767);
3947 else if (GET_MODE (op) == VOIDmode)
3949 value = CONST_DOUBLE_LOW (op);
3950 return ! IN_RANGE_P (value, -32768, 32767);
3958 /* Return 1 if operand is a 16 bit unsigned immediate. */
3961 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3963 if (GET_CODE (op) != CONST_INT)
3966 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3969 /* Return 1 if operand is an integer constant with the bottom 16 bits
3973 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3975 if (GET_CODE (op) != CONST_INT)
3978 return ((INTVAL (op) & 0xffff) == 0);
3981 /* Return true if operand is a GPR register. */
3984 integer_register_operand (rtx op, enum machine_mode mode)
3986 if (GET_MODE (op) != mode && mode != VOIDmode)
3989 if (GET_CODE (op) == SUBREG)
3991 if (GET_CODE (SUBREG_REG (op)) != REG)
3992 return register_operand (op, mode);
3994 op = SUBREG_REG (op);
3997 if (GET_CODE (op) != REG)
4000 return GPR_OR_PSEUDO_P (REGNO (op));
4003 /* Return true if operand is a GPR register. Do not allow SUBREG's
4004 here, in order to prevent a combine bug. */
4007 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
4009 if (GET_MODE (op) != mode && mode != VOIDmode)
4012 if (GET_CODE (op) != REG)
4015 return GPR_OR_PSEUDO_P (REGNO (op));
4018 /* Return true if operand is a FPR register. */
4021 fpr_operand (rtx op, enum machine_mode mode)
4023 if (GET_MODE (op) != mode && mode != VOIDmode)
4026 if (GET_CODE (op) == SUBREG)
4028 if (GET_CODE (SUBREG_REG (op)) != REG)
4029 return register_operand (op, mode);
4031 op = SUBREG_REG (op);
4034 if (GET_CODE (op) != REG)
4037 return FPR_OR_PSEUDO_P (REGNO (op));
4040 /* Return true if operand is an even GPR or FPR register. */
4043 even_reg_operand (rtx op, enum machine_mode mode)
4047 if (GET_MODE (op) != mode && mode != VOIDmode)
4050 if (GET_CODE (op) == SUBREG)
4052 if (GET_CODE (SUBREG_REG (op)) != REG)
4053 return register_operand (op, mode);
4055 op = SUBREG_REG (op);
4058 if (GET_CODE (op) != REG)
4062 if (regno >= FIRST_PSEUDO_REGISTER)
4066 return (((regno - GPR_FIRST) & 1) == 0);
4069 return (((regno - FPR_FIRST) & 1) == 0);
4074 /* Return true if operand is an odd GPR register. */
4077 odd_reg_operand (rtx op, enum machine_mode mode)
4081 if (GET_MODE (op) != mode && mode != VOIDmode)
4084 if (GET_CODE (op) == SUBREG)
4086 if (GET_CODE (SUBREG_REG (op)) != REG)
4087 return register_operand (op, mode);
4089 op = SUBREG_REG (op);
4092 if (GET_CODE (op) != REG)
4096 /* Assume that reload will give us an even register. */
4097 if (regno >= FIRST_PSEUDO_REGISTER)
4101 return (((regno - GPR_FIRST) & 1) != 0);
4104 return (((regno - FPR_FIRST) & 1) != 0);
4109 /* Return true if operand is an even GPR register. */
4112 even_gpr_operand (rtx op, enum machine_mode mode)
4116 if (GET_MODE (op) != mode && mode != VOIDmode)
4119 if (GET_CODE (op) == SUBREG)
4121 if (GET_CODE (SUBREG_REG (op)) != REG)
4122 return register_operand (op, mode);
4124 op = SUBREG_REG (op);
4127 if (GET_CODE (op) != REG)
4131 if (regno >= FIRST_PSEUDO_REGISTER)
4134 if (! GPR_P (regno))
4137 return (((regno - GPR_FIRST) & 1) == 0);
4140 /* Return true if operand is an odd GPR register. */
4143 odd_gpr_operand (rtx op, enum machine_mode mode)
4147 if (GET_MODE (op) != mode && mode != VOIDmode)
4150 if (GET_CODE (op) == SUBREG)
4152 if (GET_CODE (SUBREG_REG (op)) != REG)
4153 return register_operand (op, mode);
4155 op = SUBREG_REG (op);
4158 if (GET_CODE (op) != REG)
4162 /* Assume that reload will give us an even register. */
4163 if (regno >= FIRST_PSEUDO_REGISTER)
4166 if (! GPR_P (regno))
4169 return (((regno - GPR_FIRST) & 1) != 0);
4172 /* Return true if operand is a quad aligned FPR register. */
4175 quad_fpr_operand (rtx op, enum machine_mode mode)
4179 if (GET_MODE (op) != mode && mode != VOIDmode)
4182 if (GET_CODE (op) == SUBREG)
4184 if (GET_CODE (SUBREG_REG (op)) != REG)
4185 return register_operand (op, mode);
4187 op = SUBREG_REG (op);
4190 if (GET_CODE (op) != REG)
4194 if (regno >= FIRST_PSEUDO_REGISTER)
4197 if (! FPR_P (regno))
4200 return (((regno - FPR_FIRST) & 3) == 0);
4203 /* Return true if operand is an even FPR register. */
4206 even_fpr_operand (rtx op, enum machine_mode mode)
4210 if (GET_MODE (op) != mode && mode != VOIDmode)
4213 if (GET_CODE (op) == SUBREG)
4215 if (GET_CODE (SUBREG_REG (op)) != REG)
4216 return register_operand (op, mode);
4218 op = SUBREG_REG (op);
4221 if (GET_CODE (op) != REG)
4225 if (regno >= FIRST_PSEUDO_REGISTER)
4228 if (! FPR_P (regno))
4231 return (((regno - FPR_FIRST) & 1) == 0);
4234 /* Return true if operand is an odd FPR register. */
4237 odd_fpr_operand (rtx op, enum machine_mode mode)
4241 if (GET_MODE (op) != mode && mode != VOIDmode)
4244 if (GET_CODE (op) == SUBREG)
4246 if (GET_CODE (SUBREG_REG (op)) != REG)
4247 return register_operand (op, mode);
4249 op = SUBREG_REG (op);
4252 if (GET_CODE (op) != REG)
4256 /* Assume that reload will give us an even register. */
4257 if (regno >= FIRST_PSEUDO_REGISTER)
4260 if (! FPR_P (regno))
4263 return (((regno - FPR_FIRST) & 1) != 0);
4266 /* Return true if operand is a 2 word memory address that can be loaded in one
4267 instruction to load or store. We assume the stack and frame pointers are
4268 suitably aligned, and variables in the small data area. FIXME -- at some we
4269 should recognize other globals and statics. We can't assume that any old
4270 pointer is aligned, given that arguments could be passed on an odd word on
4271 the stack and the address taken and passed through to another function. */
4274 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4282 if (GET_CODE (op) != MEM)
4285 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4288 addr = XEXP (op, 0);
4289 if (GET_CODE (addr) == REG)
4292 else if (GET_CODE (addr) == PLUS)
4294 rtx addr0 = XEXP (addr, 0);
4295 rtx addr1 = XEXP (addr, 1);
4297 if (GET_CODE (addr0) != REG)
4300 if (got12_operand (addr1, VOIDmode))
4303 if (GET_CODE (addr1) != CONST_INT)
4306 if ((INTVAL (addr1) & 7) != 0)
4315 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4321 /* Return true if operand is a 2 word memory address that needs to
4322 use two instructions to load or store. */
4325 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4327 if (GET_CODE (op) != MEM)
4330 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4336 return ! dbl_memory_one_insn_operand (op, mode);
4339 /* Return true if operand is something that can be an output for a move
4343 move_destination_operand (rtx op, enum machine_mode mode)
4348 switch (GET_CODE (op))
4354 if (GET_MODE (op) != mode && mode != VOIDmode)
4357 subreg = SUBREG_REG (op);
4358 code = GET_CODE (subreg);
4360 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4361 reload_completed, FALSE, FALSE);
4363 return (code == REG);
4366 if (GET_MODE (op) != mode && mode != VOIDmode)
4372 return frv_legitimate_memory_operand (op, mode, FALSE);
4378 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4379 process these separately from any offsets, such that we add any
4380 offsets to the function descriptor (the actual pointer), not to the
4381 function address. */
4384 frv_function_symbol_referenced_p (rtx x)
4390 if (GET_CODE (x) == SYMBOL_REF)
4391 return SYMBOL_REF_FUNCTION_P (x);
4393 length = GET_RTX_LENGTH (GET_CODE (x));
4394 format = GET_RTX_FORMAT (GET_CODE (x));
4396 for (j = 0; j < length; ++j)
4401 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4407 if (XVEC (x, j) != 0)
4410 for (k = 0; k < XVECLEN (x, j); ++k)
4411 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4417 /* Nothing to do. */
4425 /* Return true if operand is something that can be an input for a move
4429 move_source_operand (rtx op, enum machine_mode mode)
4434 switch (GET_CODE (op))
4441 return immediate_operand (op, mode);
4444 if (GET_MODE (op) != mode && mode != VOIDmode)
4447 subreg = SUBREG_REG (op);
4448 code = GET_CODE (subreg);
4450 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4451 reload_completed, FALSE, FALSE);
4453 return (code == REG);
4456 if (GET_MODE (op) != mode && mode != VOIDmode)
4462 return frv_legitimate_memory_operand (op, mode, FALSE);
4468 /* Return true if operand is something that can be an output for a conditional
4472 condexec_dest_operand (rtx op, enum machine_mode mode)
4477 switch (GET_CODE (op))
4483 if (GET_MODE (op) != mode && mode != VOIDmode)
4486 subreg = SUBREG_REG (op);
4487 code = GET_CODE (subreg);
4489 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4490 reload_completed, TRUE, FALSE);
4492 return (code == REG);
4495 if (GET_MODE (op) != mode && mode != VOIDmode)
4501 return frv_legitimate_memory_operand (op, mode, TRUE);
4507 /* Return true if operand is something that can be an input for a conditional
4511 condexec_source_operand (rtx op, enum machine_mode mode)
4516 switch (GET_CODE (op))
4526 if (GET_MODE (op) != mode && mode != VOIDmode)
4529 subreg = SUBREG_REG (op);
4530 code = GET_CODE (subreg);
4532 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4533 reload_completed, TRUE, FALSE);
4535 return (code == REG);
4538 if (GET_MODE (op) != mode && mode != VOIDmode)
4544 return frv_legitimate_memory_operand (op, mode, TRUE);
4550 /* Return true if operand is a register of any flavor or a 0 of the
4551 appropriate type. */
4554 reg_or_0_operand (rtx op, enum machine_mode mode)
4556 switch (GET_CODE (op))
4563 if (GET_MODE (op) != mode && mode != VOIDmode)
4566 return register_operand (op, mode);
4576 /* Return true if operand is the link register. */
4579 lr_operand (rtx op, enum machine_mode mode)
4581 if (GET_CODE (op) != REG)
4584 if (GET_MODE (op) != mode && mode != VOIDmode)
4587 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4593 /* Return true if operand is the uClinux PIC register. */
4596 fdpic_operand (rtx op, enum machine_mode mode)
4601 if (GET_CODE (op) != REG)
4604 if (GET_MODE (op) != mode && mode != VOIDmode)
4607 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4614 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4616 struct frv_unspec unspec;
4618 if (frv_const_unspec_p (op, &unspec))
4619 switch (unspec.reloc)
4622 case R_FRV_GOTOFF12:
4623 case R_FRV_FUNCDESC_GOT12:
4624 case R_FRV_FUNCDESC_GOTOFF12:
4631 /* Return true if OP is a valid const-unspec expression. */
4634 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4636 struct frv_unspec unspec;
4638 return frv_const_unspec_p (op, &unspec);
4640 /* Return true if operand is a gpr register or a valid memory operation. */
4643 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4645 return (integer_register_operand (op, mode)
4646 || frv_legitimate_memory_operand (op, mode, FALSE));
4649 /* Return true if operand is a fpr register or a valid memory operation. */
4652 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4654 return (fpr_operand (op, mode)
4655 || frv_legitimate_memory_operand (op, mode, FALSE));
4658 /* Return true if operand is an icc register. */
4661 icc_operand (rtx op, enum machine_mode mode)
4665 if (GET_MODE (op) != mode && mode != VOIDmode)
4668 if (GET_CODE (op) != REG)
4672 return ICC_OR_PSEUDO_P (regno);
4675 /* Return true if operand is an fcc register. */
4678 fcc_operand (rtx op, enum machine_mode mode)
4682 if (GET_MODE (op) != mode && mode != VOIDmode)
4685 if (GET_CODE (op) != REG)
4689 return FCC_OR_PSEUDO_P (regno);
4692 /* Return true if operand is either an fcc or icc register. */
4695 cc_operand (rtx op, enum machine_mode mode)
4699 if (GET_MODE (op) != mode && mode != VOIDmode)
4702 if (GET_CODE (op) != REG)
4706 if (CC_OR_PSEUDO_P (regno))
4712 /* Return true if operand is an integer CCR register. */
4715 icr_operand (rtx op, enum machine_mode mode)
4719 if (GET_MODE (op) != mode && mode != VOIDmode)
4722 if (GET_CODE (op) != REG)
4726 return ICR_OR_PSEUDO_P (regno);
4729 /* Return true if operand is an fcc register. */
4732 fcr_operand (rtx op, enum machine_mode mode)
4736 if (GET_MODE (op) != mode && mode != VOIDmode)
4739 if (GET_CODE (op) != REG)
4743 return FCR_OR_PSEUDO_P (regno);
4746 /* Return true if operand is either an fcc or icc register. */
4749 cr_operand (rtx op, enum machine_mode mode)
4753 if (GET_MODE (op) != mode && mode != VOIDmode)
4756 if (GET_CODE (op) != REG)
4760 if (CR_OR_PSEUDO_P (regno))
4766 /* Return true if operand is a memory reference suitable for a call. */
4769 call_operand (rtx op, enum machine_mode mode)
4771 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4774 if (GET_CODE (op) == SYMBOL_REF)
4775 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
4777 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4778 never occur anyway), but prevents reload from not handling the case
4779 properly of a call through a pointer on a function that calls
4780 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4781 return gpr_or_int12_operand (op, mode);
4784 /* Return true if operand is a memory reference suitable for a sibcall. */
4787 sibcall_operand (rtx op, enum machine_mode mode)
4789 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4792 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4793 never occur anyway), but prevents reload from not handling the case
4794 properly of a call through a pointer on a function that calls
4795 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4796 return gpr_or_int12_operand (op, mode);
4799 /* Return true if operator is a kind of relational operator. */
4802 relational_operator (rtx op, enum machine_mode mode)
4808 if (mode != VOIDmode && mode != GET_MODE (op))
4811 switch (GET_CODE (op))
4830 if (op1 != const0_rtx)
4834 if (GET_CODE (op0) != REG)
4837 regno = REGNO (op0);
4838 switch (GET_MODE (op0))
4845 return ICC_OR_PSEUDO_P (regno);
4848 return FCC_OR_PSEUDO_P (regno);
4851 return CR_OR_PSEUDO_P (regno);
4857 /* Return true if operator is a signed integer relational operator. */
4860 signed_relational_operator (rtx op, enum machine_mode mode)
4866 if (mode != VOIDmode && mode != GET_MODE (op))
4869 switch (GET_CODE (op))
4884 if (op1 != const0_rtx)
4888 if (GET_CODE (op0) != REG)
4891 regno = REGNO (op0);
4892 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4895 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4901 /* Return true if operator is a signed integer relational operator. */
4904 unsigned_relational_operator (rtx op, enum machine_mode mode)
4910 if (mode != VOIDmode && mode != GET_MODE (op))
4913 switch (GET_CODE (op))
4926 if (op1 != const0_rtx)
4930 if (GET_CODE (op0) != REG)
4933 regno = REGNO (op0);
4934 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4937 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4943 /* Return true if operator is a floating point relational operator. */
4946 float_relational_operator (rtx op, enum machine_mode mode)
4952 if (mode != VOIDmode && mode != GET_MODE (op))
4955 switch (GET_CODE (op))
4974 if (op1 != const0_rtx)
4978 if (GET_CODE (op0) != REG)
4981 regno = REGNO (op0);
4982 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4985 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4991 /* Return true if operator is EQ/NE of a conditional execution register. */
4994 ccr_eqne_operator (rtx op, enum machine_mode mode)
4996 enum machine_mode op_mode = GET_MODE (op);
5001 if (mode != VOIDmode && op_mode != mode)
5004 switch (GET_CODE (op))
5015 if (op1 != const0_rtx)
5019 if (GET_CODE (op0) != REG)
5022 regno = REGNO (op0);
5023 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
5029 /* Return true if operator is a minimum or maximum operator (both signed and
5033 minmax_operator (rtx op, enum machine_mode mode)
5035 if (mode != VOIDmode && mode != GET_MODE (op))
5038 switch (GET_CODE (op))
5050 if (! integer_register_operand (XEXP (op, 0), mode))
5053 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5059 /* Return true if operator is an integer binary operator that can executed
5060 conditionally and takes 1 cycle. */
5063 condexec_si_binary_operator (rtx op, enum machine_mode mode)
5065 enum machine_mode op_mode = GET_MODE (op);
5067 if (mode != VOIDmode && op_mode != mode)
5070 switch (GET_CODE (op))
5087 /* Return true if operator is an integer binary operator that can be
5088 executed conditionally by a media instruction. */
5091 condexec_si_media_operator (rtx op, enum machine_mode mode)
5093 enum machine_mode op_mode = GET_MODE (op);
5095 if (mode != VOIDmode && op_mode != mode)
5098 switch (GET_CODE (op))
5110 /* Return true if operator is an integer division operator that can executed
5114 condexec_si_divide_operator (rtx op, enum machine_mode mode)
5116 enum machine_mode op_mode = GET_MODE (op);
5118 if (mode != VOIDmode && op_mode != mode)
5121 switch (GET_CODE (op))
5132 /* Return true if operator is an integer unary operator that can executed
5136 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5138 enum machine_mode op_mode = GET_MODE (op);
5140 if (mode != VOIDmode && op_mode != mode)
5143 switch (GET_CODE (op))
5154 /* Return true if operator is a conversion-type expression that can be
5155 evaluated conditionally by floating-point instructions. */
5158 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5160 enum machine_mode op_mode = GET_MODE (op);
5162 if (mode != VOIDmode && op_mode != mode)
5165 switch (GET_CODE (op))
5176 /* Return true if operator is an addition or subtraction expression.
5177 Such expressions can be evaluated conditionally by floating-point
5181 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5183 enum machine_mode op_mode = GET_MODE (op);
5185 if (mode != VOIDmode && op_mode != mode)
5188 switch (GET_CODE (op))
5199 /* Return true if the memory operand is one that can be conditionally
5203 condexec_memory_operand (rtx op, enum machine_mode mode)
5205 enum machine_mode op_mode = GET_MODE (op);
5208 if (mode != VOIDmode && op_mode != mode)
5223 if (GET_CODE (op) != MEM)
5226 addr = XEXP (op, 0);
5227 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5230 /* Return true if operator is an integer binary operator that can be combined
5231 with a setcc operation. Do not allow the arithmetic operations that could
5232 potentially overflow since the FR-V sets the condition code based on the
5233 "true" value of the result, not the result after truncating to a 32-bit
5237 intop_compare_operator (rtx op, enum machine_mode mode)
5239 enum machine_mode op_mode = GET_MODE (op);
5241 if (mode != VOIDmode && op_mode != mode)
5244 switch (GET_CODE (op))
5257 if (! integer_register_operand (XEXP (op, 0), SImode))
5260 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5266 /* Return true if operator is an integer binary operator that can be combined
5267 with a setcc operation inside of a conditional execution. */
5270 condexec_intop_cmp_operator (rtx op, enum machine_mode mode)
5272 enum machine_mode op_mode = GET_MODE (op);
5274 if (mode != VOIDmode && op_mode != mode)
5277 switch (GET_CODE (op))
5290 if (! integer_register_operand (XEXP (op, 0), SImode))
5293 if (! integer_register_operand (XEXP (op, 1), SImode))
5299 /* Return 1 if operand is a valid ACC register number. */
5302 acc_operand (rtx op, enum machine_mode mode)
5304 return ((mode == VOIDmode || mode == GET_MODE (op))
5305 && REG_P (op) && ACC_P (REGNO (op))
5306 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
5309 /* Return 1 if operand is a valid even ACC register number. */
5312 even_acc_operand (rtx op, enum machine_mode mode)
5314 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
5317 /* Return 1 if operand is zero or four. */
5320 quad_acc_operand (rtx op, enum machine_mode mode)
5322 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
5325 /* Return 1 if operand is a valid ACCG register number. */
5328 accg_operand (rtx op, enum machine_mode mode)
5330 return ((mode == VOIDmode || mode == GET_MODE (op))
5331 && REG_P (op) && ACCG_P (REGNO (op))
5332 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
5336 /* Return true if the bare return instruction can be used outside of the
5337 epilog code. For frv, we only do it if there was no stack allocation. */
5340 direct_return_p (void)
5344 if (!reload_completed)
5347 info = frv_stack_info ();
5348 return (info->total_size == 0);
5353 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
5358 if (frv_emit_movsi (dest, src))
5367 if (!reload_in_progress
5368 && !reload_completed
5369 && !register_operand (dest, mode)
5370 && !reg_or_0_operand (src, mode))
5371 src = copy_to_mode_reg (mode, src);
5378 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
5381 /* Emit code to handle a MOVSI, adding in the small data register or pic
5382 register if needed to load up addresses. Return TRUE if the appropriate
5383 instructions are emitted. */
5386 frv_emit_movsi (rtx dest, rtx src)
5388 int base_regno = -1;
5391 struct frv_unspec old_unspec;
5393 if (!reload_in_progress
5394 && !reload_completed
5395 && !register_operand (dest, SImode)
5396 && (!reg_or_0_operand (src, SImode)
5397 /* Virtual registers will almost always be replaced by an
5398 add instruction, so expose this to CSE by copying to
5399 an intermediate register. */
5400 || (GET_CODE (src) == REG
5401 && IN_RANGE_P (REGNO (src),
5402 FIRST_VIRTUAL_REGISTER,
5403 LAST_VIRTUAL_REGISTER))))
5405 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5409 /* Explicitly add in the PIC or small data register if needed. */
5410 switch (GET_CODE (src))
5419 /* Using GPREL12, we use a single GOT entry for all symbols
5420 in read-only sections, but trade sequences such as:
5422 sethi #gothi(label), gr#
5423 setlo #gotlo(label), gr#
5428 ld @(gr15,#got12(_gp)), gr#
5429 sethi #gprelhi(label), gr##
5430 setlo #gprello(label), gr##
5433 We may often be able to share gr# for multiple
5434 computations of GPREL addresses, and we may often fold
5435 the final add into the pair of registers of a load or
5436 store instruction, so it's often profitable. Even when
5437 optimizing for size, we're trading a GOT entry for an
5438 additional instruction, which trades GOT space
5439 (read-write) for code size (read-only, shareable), as
5440 long as the symbol is not used in more than two different
5443 With -fpie/-fpic, we'd be trading a single load for a
5444 sequence of 4 instructions, because the offset of the
5445 label can't be assumed to be addressable with 12 bits, so
5446 we don't do this. */
5447 if (TARGET_GPREL_RO)
5448 unspec = R_FRV_GPREL12;
5450 unspec = R_FRV_GOT12;
5453 base_regno = PIC_REGNO;
5458 if (frv_const_unspec_p (src, &old_unspec))
5461 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5464 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5465 emit_move_insn (dest, src);
5470 sym = XEXP (sym, 0);
5471 if (GET_CODE (sym) == PLUS
5472 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5473 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5474 sym = XEXP (sym, 0);
5475 if (GET_CODE (sym) == SYMBOL_REF)
5477 else if (GET_CODE (sym) == LABEL_REF)
5480 goto handle_whatever;
5488 if (SYMBOL_REF_FUNCTION_P (sym))
5490 if (frv_local_funcdesc_p (sym))
5491 unspec = R_FRV_FUNCDESC_GOTOFF12;
5493 unspec = R_FRV_FUNCDESC_GOT12;
5497 if (CONSTANT_POOL_ADDRESS_P (sym))
5498 switch (GET_CODE (get_pool_constant (sym)))
5505 unspec = R_FRV_GOTOFF12;
5510 if (TARGET_GPREL_RO)
5511 unspec = R_FRV_GPREL12;
5513 unspec = R_FRV_GOT12;
5516 else if (SYMBOL_REF_LOCAL_P (sym)
5517 && !SYMBOL_REF_EXTERNAL_P (sym)
5518 && SYMBOL_REF_DECL (sym)
5519 && (!DECL_P (SYMBOL_REF_DECL (sym))
5520 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5522 tree decl = SYMBOL_REF_DECL (sym);
5523 tree init = TREE_CODE (decl) == VAR_DECL
5524 ? DECL_INITIAL (decl)
5525 : TREE_CODE (decl) == CONSTRUCTOR
5528 bool named_section, readonly;
5530 if (init && init != error_mark_node)
5531 reloc = compute_reloc_for_constant (init);
5533 named_section = TREE_CODE (decl) == VAR_DECL
5534 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5535 readonly = decl_readonly_section (decl, reloc);
5538 unspec = R_FRV_GOT12;
5540 unspec = R_FRV_GOTOFF12;
5541 else if (readonly && TARGET_GPREL_RO)
5542 unspec = R_FRV_GPREL12;
5544 unspec = R_FRV_GOT12;
5547 unspec = R_FRV_GOT12;
5551 else if (SYMBOL_REF_SMALL_P (sym))
5552 base_regno = SDA_BASE_REG;
5555 base_regno = PIC_REGNO;
5560 if (base_regno >= 0)
5562 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5563 emit_insn (gen_symGOTOFF2reg (dest, src,
5564 gen_rtx_REG (Pmode, base_regno),
5565 GEN_INT (R_FRV_GPREL12)));
5567 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5568 gen_rtx_REG (Pmode, base_regno),
5569 GEN_INT (R_FRV_GPREL12)));
5570 if (base_regno == PIC_REGNO)
5571 cfun->uses_pic_offset_table = TRUE;
5579 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5580 new uses of it once reload has begun. */
5581 if (reload_in_progress || reload_completed)
5586 case R_FRV_GOTOFF12:
5587 if (!frv_small_data_reloc_p (sym, unspec))
5588 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5591 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5594 if (!frv_small_data_reloc_p (sym, unspec))
5595 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5598 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5600 case R_FRV_FUNCDESC_GOTOFF12:
5602 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5605 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5609 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5612 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5616 cfun->uses_pic_offset_table = TRUE;
5625 /* Return a string to output a single word move. */
5628 output_move_single (rtx operands[], rtx insn)
5630 rtx dest = operands[0];
5631 rtx src = operands[1];
5633 if (GET_CODE (dest) == REG)
5635 int dest_regno = REGNO (dest);
5636 enum machine_mode mode = GET_MODE (dest);
5638 if (GPR_P (dest_regno))
5640 if (GET_CODE (src) == REG)
5642 /* gpr <- some sort of register */
5643 int src_regno = REGNO (src);
5645 if (GPR_P (src_regno))
5646 return "mov %1, %0";
5648 else if (FPR_P (src_regno))
5649 return "movfg %1, %0";
5651 else if (SPR_P (src_regno))
5652 return "movsg %1, %0";
5655 else if (GET_CODE (src) == MEM)
5664 return "ldsb%I1%U1 %M1,%0";
5667 return "ldsh%I1%U1 %M1,%0";
5671 return "ld%I1%U1 %M1, %0";
5675 else if (GET_CODE (src) == CONST_INT
5676 || GET_CODE (src) == CONST_DOUBLE)
5678 /* gpr <- integer/floating constant */
5679 HOST_WIDE_INT value;
5681 if (GET_CODE (src) == CONST_INT)
5682 value = INTVAL (src);
5684 else if (mode == SFmode)
5689 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5690 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5695 value = CONST_DOUBLE_LOW (src);
5697 if (IN_RANGE_P (value, -32768, 32767))
5698 return "setlos %1, %0";
5703 else if (GET_CODE (src) == SYMBOL_REF
5704 || GET_CODE (src) == LABEL_REF
5705 || GET_CODE (src) == CONST)
5711 else if (FPR_P (dest_regno))
5713 if (GET_CODE (src) == REG)
5715 /* fpr <- some sort of register */
5716 int src_regno = REGNO (src);
5718 if (GPR_P (src_regno))
5719 return "movgf %1, %0";
5721 else if (FPR_P (src_regno))
5723 if (TARGET_HARD_FLOAT)
5724 return "fmovs %1, %0";
5726 return "mor %1, %1, %0";
5730 else if (GET_CODE (src) == MEM)
5739 return "ldbf%I1%U1 %M1,%0";
5742 return "ldhf%I1%U1 %M1,%0";
5746 return "ldf%I1%U1 %M1, %0";
5750 else if (ZERO_P (src))
5751 return "movgf %., %0";
5754 else if (SPR_P (dest_regno))
5756 if (GET_CODE (src) == REG)
5758 /* spr <- some sort of register */
5759 int src_regno = REGNO (src);
5761 if (GPR_P (src_regno))
5762 return "movgs %1, %0";
5764 else if (ZERO_P (src))
5765 return "movgs %., %0";
5769 else if (GET_CODE (dest) == MEM)
5771 if (GET_CODE (src) == REG)
5773 int src_regno = REGNO (src);
5774 enum machine_mode mode = GET_MODE (dest);
5776 if (GPR_P (src_regno))
5784 return "stb%I0%U0 %1, %M0";
5787 return "sth%I0%U0 %1, %M0";
5791 return "st%I0%U0 %1, %M0";
5795 else if (FPR_P (src_regno))
5803 return "stbf%I0%U0 %1, %M0";
5806 return "sthf%I0%U0 %1, %M0";
5810 return "stf%I0%U0 %1, %M0";
5815 else if (ZERO_P (src))
5817 switch (GET_MODE (dest))
5823 return "stb%I0%U0 %., %M0";
5826 return "sth%I0%U0 %., %M0";
5830 return "st%I0%U0 %., %M0";
5835 fatal_insn ("Bad output_move_single operand", insn);
5840 /* Return a string to output a double word move. */
5843 output_move_double (rtx operands[], rtx insn)
5845 rtx dest = operands[0];
5846 rtx src = operands[1];
5847 enum machine_mode mode = GET_MODE (dest);
5849 if (GET_CODE (dest) == REG)
5851 int dest_regno = REGNO (dest);
5853 if (GPR_P (dest_regno))
5855 if (GET_CODE (src) == REG)
5857 /* gpr <- some sort of register */
5858 int src_regno = REGNO (src);
5860 if (GPR_P (src_regno))
5863 else if (FPR_P (src_regno))
5865 if (((dest_regno - GPR_FIRST) & 1) == 0
5866 && ((src_regno - FPR_FIRST) & 1) == 0)
5867 return "movfgd %1, %0";
5873 else if (GET_CODE (src) == MEM)
5876 if (dbl_memory_one_insn_operand (src, mode))
5877 return "ldd%I1%U1 %M1, %0";
5882 else if (GET_CODE (src) == CONST_INT
5883 || GET_CODE (src) == CONST_DOUBLE)
5887 else if (FPR_P (dest_regno))
5889 if (GET_CODE (src) == REG)
5891 /* fpr <- some sort of register */
5892 int src_regno = REGNO (src);
5894 if (GPR_P (src_regno))
5896 if (((dest_regno - FPR_FIRST) & 1) == 0
5897 && ((src_regno - GPR_FIRST) & 1) == 0)
5898 return "movgfd %1, %0";
5903 else if (FPR_P (src_regno))
5906 && ((dest_regno - FPR_FIRST) & 1) == 0
5907 && ((src_regno - FPR_FIRST) & 1) == 0)
5908 return "fmovd %1, %0";
5914 else if (GET_CODE (src) == MEM)
5917 if (dbl_memory_one_insn_operand (src, mode))
5918 return "lddf%I1%U1 %M1, %0";
5923 else if (ZERO_P (src))
5928 else if (GET_CODE (dest) == MEM)
5930 if (GET_CODE (src) == REG)
5932 int src_regno = REGNO (src);
5934 if (GPR_P (src_regno))
5936 if (((src_regno - GPR_FIRST) & 1) == 0
5937 && dbl_memory_one_insn_operand (dest, mode))
5938 return "std%I0%U0 %1, %M0";
5943 if (FPR_P (src_regno))
5945 if (((src_regno - FPR_FIRST) & 1) == 0
5946 && dbl_memory_one_insn_operand (dest, mode))
5947 return "stdf%I0%U0 %1, %M0";
5953 else if (ZERO_P (src))
5955 if (dbl_memory_one_insn_operand (dest, mode))
5956 return "std%I0%U0 %., %M0";
5962 fatal_insn ("Bad output_move_double operand", insn);
5967 /* Return a string to output a single word conditional move.
5968 Operand0 -- EQ/NE of ccr register and 0
5969 Operand1 -- CCR register
5970 Operand2 -- destination
5971 Operand3 -- source */
5974 output_condmove_single (rtx operands[], rtx insn)
5976 rtx dest = operands[2];
5977 rtx src = operands[3];
5979 if (GET_CODE (dest) == REG)
5981 int dest_regno = REGNO (dest);
5982 enum machine_mode mode = GET_MODE (dest);
5984 if (GPR_P (dest_regno))
5986 if (GET_CODE (src) == REG)
5988 /* gpr <- some sort of register */
5989 int src_regno = REGNO (src);
5991 if (GPR_P (src_regno))
5992 return "cmov %z3, %2, %1, %e0";
5994 else if (FPR_P (src_regno))
5995 return "cmovfg %3, %2, %1, %e0";
5998 else if (GET_CODE (src) == MEM)
6007 return "cldsb%I3%U3 %M3, %2, %1, %e0";
6010 return "cldsh%I3%U3 %M3, %2, %1, %e0";
6014 return "cld%I3%U3 %M3, %2, %1, %e0";
6018 else if (ZERO_P (src))
6019 return "cmov %., %2, %1, %e0";
6022 else if (FPR_P (dest_regno))
6024 if (GET_CODE (src) == REG)
6026 /* fpr <- some sort of register */
6027 int src_regno = REGNO (src);
6029 if (GPR_P (src_regno))
6030 return "cmovgf %3, %2, %1, %e0";
6032 else if (FPR_P (src_regno))
6034 if (TARGET_HARD_FLOAT)
6035 return "cfmovs %3,%2,%1,%e0";
6037 return "cmor %3, %3, %2, %1, %e0";
6041 else if (GET_CODE (src) == MEM)
6044 if (mode == SImode || mode == SFmode)
6045 return "cldf%I3%U3 %M3, %2, %1, %e0";
6048 else if (ZERO_P (src))
6049 return "cmovgf %., %2, %1, %e0";
6053 else if (GET_CODE (dest) == MEM)
6055 if (GET_CODE (src) == REG)
6057 int src_regno = REGNO (src);
6058 enum machine_mode mode = GET_MODE (dest);
6060 if (GPR_P (src_regno))
6068 return "cstb%I2%U2 %3, %M2, %1, %e0";
6071 return "csth%I2%U2 %3, %M2, %1, %e0";
6075 return "cst%I2%U2 %3, %M2, %1, %e0";
6079 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
6080 return "cstf%I2%U2 %3, %M2, %1, %e0";
6083 else if (ZERO_P (src))
6085 enum machine_mode mode = GET_MODE (dest);
6092 return "cstb%I2%U2 %., %M2, %1, %e0";
6095 return "csth%I2%U2 %., %M2, %1, %e0";
6099 return "cst%I2%U2 %., %M2, %1, %e0";
6104 fatal_insn ("Bad output_condmove_single operand", insn);
6109 /* Emit the appropriate code to do a comparison, returning the register the
6110 comparison was done it. */
6113 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
6115 enum machine_mode cc_mode;
6118 /* Floating point doesn't have comparison against a constant. */
6119 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6120 op1 = force_reg (GET_MODE (op0), op1);
6122 /* Possibly disable using anything but a fixed register in order to work
6123 around cse moving comparisons past function calls. */
6124 cc_mode = SELECT_CC_MODE (test, op0, op1);
6125 cc_reg = ((TARGET_ALLOC_CC)
6126 ? gen_reg_rtx (cc_mode)
6127 : gen_rtx_REG (cc_mode,
6128 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6130 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6131 gen_rtx_COMPARE (cc_mode, op0, op1)));
6137 /* Emit code for a conditional branch. The comparison operands were previously
6138 stored in frv_compare_op0 and frv_compare_op1.
6140 XXX: I originally wanted to add a clobber of a CCR register to use in
6141 conditional execution, but that confuses the rest of the compiler. */
6144 frv_emit_cond_branch (enum rtx_code test, rtx label)
6149 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6150 enum machine_mode cc_mode = GET_MODE (cc_reg);
6152 /* Branches generate:
6154 (if_then_else (<test>, <cc_reg>, (const_int 0))
6155 (label_ref <branch_label>)
6157 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6158 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6159 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6160 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6165 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6166 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6169 frv_emit_scc (enum rtx_code test, rtx target)
6175 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6177 /* SCC instructions generate:
6178 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6179 (clobber (<ccr_reg>))]) */
6180 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6181 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6183 cr_reg = ((TARGET_ALLOC_CC)
6184 ? gen_reg_rtx (CC_CCRmode)
6185 : gen_rtx_REG (CC_CCRmode,
6186 ((GET_MODE (cc_reg) == CC_FPmode)
6190 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6191 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6196 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6197 the separate insns. */
6200 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6206 /* Set the appropriate CCR bit. */
6207 emit_insn (gen_rtx_SET (VOIDmode,
6209 gen_rtx_fmt_ee (GET_CODE (test),
6214 /* Move the value into the destination. */
6215 emit_move_insn (dest, GEN_INT (value));
6217 /* Move 0 into the destination if the test failed */
6218 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6219 gen_rtx_EQ (GET_MODE (cr_reg),
6222 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6224 /* Finish up, return sequence. */
6231 /* Emit the code for a conditional move, return TRUE if we could do the
6235 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6242 enum rtx_code test = GET_CODE (test_rtx);
6243 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6244 enum machine_mode cc_mode = GET_MODE (cc_reg);
6246 /* Conditional move instructions generate:
6247 (parallel [(set <target>
6248 (if_then_else (<test> <cc_reg> (const_int 0))
6251 (clobber (<ccr_reg>))]) */
6253 /* Handle various cases of conditional move involving two constants. */
6254 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6256 HOST_WIDE_INT value1 = INTVAL (src1);
6257 HOST_WIDE_INT value2 = INTVAL (src2);
6259 /* Having 0 as one of the constants can be done by loading the other
6260 constant, and optionally moving in gr0. */
6261 if (value1 == 0 || value2 == 0)
6264 /* If the first value is within an addi range and also the difference
6265 between the two fits in an addi's range, load up the difference, then
6266 conditionally move in 0, and then unconditionally add the first
6268 else if (IN_RANGE_P (value1, -2048, 2047)
6269 && IN_RANGE_P (value2 - value1, -2048, 2047))
6272 /* If neither condition holds, just force the constant into a
6276 src1 = force_reg (GET_MODE (dest), src1);
6277 src2 = force_reg (GET_MODE (dest), src2);
6281 /* If one value is a register, insure the other value is either 0 or a
6285 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6286 src1 = force_reg (GET_MODE (dest), src1);
6288 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6289 src2 = force_reg (GET_MODE (dest), src2);
6292 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6293 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6295 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6297 cr_reg = ((TARGET_ALLOC_CC)
6298 ? gen_reg_rtx (CC_CCRmode)
6299 : gen_rtx_REG (CC_CCRmode,
6300 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6302 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6303 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6308 /* Split a conditional move into constituent parts, returning a SEQUENCE
6309 containing all of the insns. */
6312 frv_split_cond_move (rtx operands[])
6314 rtx dest = operands[0];
6315 rtx test = operands[1];
6316 rtx cc_reg = operands[2];
6317 rtx src1 = operands[3];
6318 rtx src2 = operands[4];
6319 rtx cr_reg = operands[5];
6321 enum machine_mode cr_mode = GET_MODE (cr_reg);
6325 /* Set the appropriate CCR bit. */
6326 emit_insn (gen_rtx_SET (VOIDmode,
6328 gen_rtx_fmt_ee (GET_CODE (test),
6333 /* Handle various cases of conditional move involving two constants. */
6334 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6336 HOST_WIDE_INT value1 = INTVAL (src1);
6337 HOST_WIDE_INT value2 = INTVAL (src2);
6339 /* Having 0 as one of the constants can be done by loading the other
6340 constant, and optionally moving in gr0. */
6343 emit_move_insn (dest, src2);
6344 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6345 gen_rtx_NE (cr_mode, cr_reg,
6347 gen_rtx_SET (VOIDmode, dest, src1)));
6350 else if (value2 == 0)
6352 emit_move_insn (dest, src1);
6353 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6354 gen_rtx_EQ (cr_mode, cr_reg,
6356 gen_rtx_SET (VOIDmode, dest, src2)));
6359 /* If the first value is within an addi range and also the difference
6360 between the two fits in an addi's range, load up the difference, then
6361 conditionally move in 0, and then unconditionally add the first
6363 else if (IN_RANGE_P (value1, -2048, 2047)
6364 && IN_RANGE_P (value2 - value1, -2048, 2047))
6366 rtx dest_si = ((GET_MODE (dest) == SImode)
6368 : gen_rtx_SUBREG (SImode, dest, 0));
6370 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6371 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6372 gen_rtx_NE (cr_mode, cr_reg,
6374 gen_rtx_SET (VOIDmode, dest_si,
6376 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6384 /* Emit the conditional move for the test being true if needed. */
6385 if (! rtx_equal_p (dest, src1))
6386 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6387 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6388 gen_rtx_SET (VOIDmode, dest, src1)));
6390 /* Emit the conditional move for the test being false if needed. */
6391 if (! rtx_equal_p (dest, src2))
6392 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6393 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6394 gen_rtx_SET (VOIDmode, dest, src2)));
6397 /* Finish up, return sequence. */
6404 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6405 memory location that is not known to be dword-aligned. */
6407 frv_split_double_load (rtx dest, rtx source)
6409 int regno = REGNO (dest);
6410 rtx dest1 = gen_highpart (SImode, dest);
6411 rtx dest2 = gen_lowpart (SImode, dest);
6412 rtx address = XEXP (source, 0);
6414 /* If the address is pre-modified, load the lower-numbered register
6415 first, then load the other register using an integer offset from
6416 the modified base register. This order should always be safe,
6417 since the pre-modification cannot affect the same registers as the
6420 The situation for other loads is more complicated. Loading one
6421 of the registers could affect the value of ADDRESS, so we must
6422 be careful which order we do them in. */
6423 if (GET_CODE (address) == PRE_MODIFY
6424 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6426 /* It is safe to load the lower-numbered register first. */
6427 emit_move_insn (dest1, change_address (source, SImode, NULL));
6428 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6432 /* ADDRESS is not pre-modified and the address depends on the
6433 lower-numbered register. Load the higher-numbered register
6435 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6436 emit_move_insn (dest1, change_address (source, SImode, NULL));
6440 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6441 and SOURCE is either a double register or the constant zero. */
6443 frv_split_double_store (rtx dest, rtx source)
6445 rtx dest1 = change_address (dest, SImode, NULL);
6446 rtx dest2 = frv_index_memory (dest, SImode, 1);
6447 if (ZERO_P (source))
6449 emit_move_insn (dest1, CONST0_RTX (SImode));
6450 emit_move_insn (dest2, CONST0_RTX (SImode));
6454 emit_move_insn (dest1, gen_highpart (SImode, source));
6455 emit_move_insn (dest2, gen_lowpart (SImode, source));
6460 /* Split a min/max operation returning a SEQUENCE containing all of the
6464 frv_split_minmax (rtx operands[])
6466 rtx dest = operands[0];
6467 rtx minmax = operands[1];
6468 rtx src1 = operands[2];
6469 rtx src2 = operands[3];
6470 rtx cc_reg = operands[4];
6471 rtx cr_reg = operands[5];
6473 enum rtx_code test_code;
6474 enum machine_mode cr_mode = GET_MODE (cr_reg);
6478 /* Figure out which test to use. */
6479 switch (GET_CODE (minmax))
6484 case SMIN: test_code = LT; break;
6485 case SMAX: test_code = GT; break;
6486 case UMIN: test_code = LTU; break;
6487 case UMAX: test_code = GTU; break;
6490 /* Issue the compare instruction. */
6491 emit_insn (gen_rtx_SET (VOIDmode,
6493 gen_rtx_COMPARE (GET_MODE (cc_reg),
6496 /* Set the appropriate CCR bit. */
6497 emit_insn (gen_rtx_SET (VOIDmode,
6499 gen_rtx_fmt_ee (test_code,
6504 /* If are taking the min/max of a nonzero constant, load that first, and
6505 then do a conditional move of the other value. */
6506 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6508 if (rtx_equal_p (dest, src1))
6511 emit_move_insn (dest, src2);
6512 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6513 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6514 gen_rtx_SET (VOIDmode, dest, src1)));
6517 /* Otherwise, do each half of the move. */
6520 /* Emit the conditional move for the test being true if needed. */
6521 if (! rtx_equal_p (dest, src1))
6522 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6523 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6524 gen_rtx_SET (VOIDmode, dest, src1)));
6526 /* Emit the conditional move for the test being false if needed. */
6527 if (! rtx_equal_p (dest, src2))
6528 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6529 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6530 gen_rtx_SET (VOIDmode, dest, src2)));
6533 /* Finish up, return sequence. */
6540 /* Split an integer abs operation returning a SEQUENCE containing all of the
6544 frv_split_abs (rtx operands[])
6546 rtx dest = operands[0];
6547 rtx src = operands[1];
6548 rtx cc_reg = operands[2];
6549 rtx cr_reg = operands[3];
6554 /* Issue the compare < 0 instruction. */
6555 emit_insn (gen_rtx_SET (VOIDmode,
6557 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6559 /* Set the appropriate CCR bit. */
6560 emit_insn (gen_rtx_SET (VOIDmode,
6562 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6564 /* Emit the conditional negate if the value is negative. */
6565 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6566 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6567 gen_negsi2 (dest, src)));
6569 /* Emit the conditional move for the test being false if needed. */
6570 if (! rtx_equal_p (dest, src))
6571 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6572 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6573 gen_rtx_SET (VOIDmode, dest, src)));
6575 /* Finish up, return sequence. */
6582 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6583 register used in an insn. */
6586 frv_clear_registers_used (rtx *ptr, void *data)
6588 if (GET_CODE (*ptr) == REG)
6590 int regno = REGNO (*ptr);
6591 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6593 if (regno < FIRST_PSEUDO_REGISTER)
6595 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6597 while (regno < reg_max)
6599 CLEAR_HARD_REG_BIT (*p_regs, regno);
6609 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6611 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6612 initialize the static storage. */
6614 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6616 frv_ifcvt.added_insns_list = NULL_RTX;
6617 frv_ifcvt.cur_scratch_regs = 0;
6618 frv_ifcvt.num_nested_cond_exec = 0;
6619 frv_ifcvt.cr_reg = NULL_RTX;
6620 frv_ifcvt.nested_cc_reg = NULL_RTX;
6621 frv_ifcvt.extra_int_cr = NULL_RTX;
6622 frv_ifcvt.extra_fp_cr = NULL_RTX;
6623 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6627 /* Internal function to add a potential insn to the list of insns to be inserted
6628 if the conditional execution conversion is successful. */
6631 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6633 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6635 link->jump = before_p; /* Mark to add this before or after insn. */
6636 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6637 frv_ifcvt.added_insns_list);
6639 if (TARGET_DEBUG_COND_EXEC)
6642 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6643 (before_p) ? "before" : "after",
6644 (int)INSN_UID (insn));
6646 debug_rtx (pattern);
6651 /* A C expression to modify the code described by the conditional if
6652 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6653 FALSE_EXPR for converting if-then and if-then-else code to conditional
6654 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6655 tests cannot be converted. */
6658 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6660 basic_block test_bb = ce_info->test_bb; /* test basic block */
6661 basic_block then_bb = ce_info->then_bb; /* THEN */
6662 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6663 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6664 rtx true_expr = *p_true;
6668 enum machine_mode mode = GET_MODE (true_expr);
6672 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6674 rtx sub_cond_exec_reg;
6676 enum rtx_code code_true;
6677 enum rtx_code code_false;
6678 enum reg_class cc_class;
6679 enum reg_class cr_class;
6682 reg_set_iterator rsi;
6684 /* Make sure we are only dealing with hard registers. Also honor the
6685 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6687 if (!reload_completed || TARGET_NO_COND_EXEC
6688 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6691 /* Figure out which registers we can allocate for our own purposes. Only
6692 consider registers that are not preserved across function calls and are
6693 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6694 if we did not need to use them in reloading other registers. */
6695 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6696 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6697 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6698 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6699 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6701 /* If this is a nested IF, we need to discover whether the CC registers that
6702 are set/used inside of the block are used anywhere else. If not, we can
6703 change them to be the CC register that is paired with the CR register that
6704 controls the outermost IF block. */
6705 if (ce_info->pass > 1)
6707 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6708 for (j = CC_FIRST; j <= CC_LAST; j++)
6709 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6711 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6714 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6717 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6720 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6724 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6725 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6727 frv_ifcvt.added_insns_list = NULL_RTX;
6728 frv_ifcvt.cur_scratch_regs = 0;
6730 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6731 * sizeof (basic_block));
6737 /* Remove anything live at the beginning of the join block from being
6738 available for allocation. */
6739 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
6741 if (regno < FIRST_PSEUDO_REGISTER)
6742 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6746 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6748 if (ce_info->num_multiple_test_blocks)
6750 basic_block multiple_test_bb = ce_info->last_test_bb;
6752 while (multiple_test_bb != test_bb)
6754 bb[num_bb++] = multiple_test_bb;
6755 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
6759 /* Add in the THEN and ELSE blocks to be scanned. */
6760 bb[num_bb++] = then_bb;
6762 bb[num_bb++] = else_bb;
6764 sub_cond_exec_reg = NULL_RTX;
6765 frv_ifcvt.num_nested_cond_exec = 0;
6767 /* Scan all of the blocks for registers that must not be allocated. */
6768 for (j = 0; j < num_bb; j++)
6770 rtx last_insn = BB_END (bb[j]);
6771 rtx insn = BB_HEAD (bb[j]);
6775 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6776 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6778 (int) INSN_UID (BB_HEAD (bb[j])),
6779 (int) INSN_UID (BB_END (bb[j])));
6781 /* Anything live at the beginning of the block is obviously unavailable
6783 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
6785 if (regno < FIRST_PSEUDO_REGISTER)
6786 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6789 /* Loop through the insns in the block. */
6792 /* Mark any new registers that are created as being unavailable for
6793 allocation. Also see if the CC register used in nested IFs can be
6799 int skip_nested_if = FALSE;
6801 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6802 (void *)&tmp_reg->regs);
6804 pattern = PATTERN (insn);
6805 if (GET_CODE (pattern) == COND_EXEC)
6807 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6809 if (reg != sub_cond_exec_reg)
6811 sub_cond_exec_reg = reg;
6812 frv_ifcvt.num_nested_cond_exec++;
6816 set = single_set_pattern (pattern);
6819 rtx dest = SET_DEST (set);
6820 rtx src = SET_SRC (set);
6822 if (GET_CODE (dest) == REG)
6824 int regno = REGNO (dest);
6825 enum rtx_code src_code = GET_CODE (src);
6827 if (CC_P (regno) && src_code == COMPARE)
6828 skip_nested_if = TRUE;
6830 else if (CR_P (regno)
6831 && (src_code == IF_THEN_ELSE
6832 || COMPARISON_P (src)))
6833 skip_nested_if = TRUE;
6837 if (! skip_nested_if)
6838 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6839 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6842 if (insn == last_insn)
6845 insn = NEXT_INSN (insn);
6849 /* If this is a nested if, rewrite the CC registers that are available to
6850 include the ones that can be rewritten, to increase the chance of being
6851 able to allocate a paired CC/CR register combination. */
6852 if (ce_info->pass > 1)
6854 for (j = CC_FIRST; j <= CC_LAST; j++)
6855 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6856 SET_HARD_REG_BIT (tmp_reg->regs, j);
6858 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6864 fprintf (dump_file, "Available GPRs: ");
6866 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6867 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6869 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6870 if (++num_gprs > GPR_TEMP_NUM+2)
6874 fprintf (dump_file, "%s\nAvailable CRs: ",
6875 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6877 for (j = CR_FIRST; j <= CR_LAST; j++)
6878 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6879 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6881 fputs ("\n", dump_file);
6883 if (ce_info->pass > 1)
6885 fprintf (dump_file, "Modifiable CCs: ");
6886 for (j = CC_FIRST; j <= CC_LAST; j++)
6887 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6888 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6890 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6891 frv_ifcvt.num_nested_cond_exec);
6895 /* Allocate the appropriate temporary condition code register. Try to
6896 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6897 that conditional cmp's can be done. */
6898 if (mode == CCmode || mode == CC_UNSmode)
6900 cr_class = ICR_REGS;
6901 cc_class = ICC_REGS;
6902 cc_first = ICC_FIRST;
6905 else if (mode == CC_FPmode)
6907 cr_class = FCR_REGS;
6908 cc_class = FCC_REGS;
6909 cc_first = FCC_FIRST;
6914 cc_first = cc_last = 0;
6915 cr_class = cc_class = NO_REGS;
6918 cc = XEXP (true_expr, 0);
6919 nested_cc = cr = NULL_RTX;
6920 if (cc_class != NO_REGS)
6922 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6923 so we can execute a csubcc/caddcc/cfcmps instruction. */
6926 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6928 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6930 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6931 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6933 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6934 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6937 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6938 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6948 fprintf (dump_file, "Could not allocate a CR temporary register\n");
6955 "Will use %s for conditional execution, %s for nested comparisons\n",
6956 reg_names[ REGNO (cr)],
6957 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6959 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6960 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6961 bit being true. We don't do this for floating point, because of NaNs. */
6962 code = GET_CODE (true_expr);
6963 if (GET_MODE (cc) != CC_FPmode)
6965 code = reverse_condition (code);
6975 check_insn = gen_rtx_SET (VOIDmode, cr,
6976 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6978 /* Record the check insn to be inserted later. */
6979 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6981 /* Update the tests. */
6982 frv_ifcvt.cr_reg = cr;
6983 frv_ifcvt.nested_cc_reg = nested_cc;
6984 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6985 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6988 /* Fail, don't do this conditional execution. */
6991 *p_false = NULL_RTX;
6993 fprintf (dump_file, "Disabling this conditional execution.\n");
6999 /* A C expression to modify the code described by the conditional if
7000 information CE_INFO, for the basic block BB, possibly updating the tests in
7001 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
7002 if-then-else code to conditional instructions. Set either TRUE_EXPR or
7003 FALSE_EXPR to a null pointer if the tests cannot be converted. */
7005 /* p_true and p_false are given expressions of the form:
7007 (and (eq:CC_CCR (reg:CC_CCR)
7013 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
7018 rtx old_true = XEXP (*p_true, 0);
7019 rtx old_false = XEXP (*p_false, 0);
7020 rtx true_expr = XEXP (*p_true, 1);
7021 rtx false_expr = XEXP (*p_false, 1);
7024 rtx cr = XEXP (old_true, 0);
7026 rtx new_cr = NULL_RTX;
7027 rtx *p_new_cr = (rtx *)0;
7031 enum reg_class cr_class;
7032 enum machine_mode mode = GET_MODE (true_expr);
7033 rtx (*logical_func)(rtx, rtx, rtx);
7035 if (TARGET_DEBUG_COND_EXEC)
7038 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7039 ce_info->and_and_p ? "&&" : "||");
7041 debug_rtx (*p_true);
7043 fputs ("\nfalse insn:\n", stderr);
7044 debug_rtx (*p_false);
7047 if (TARGET_NO_MULTI_CE)
7050 if (GET_CODE (cr) != REG)
7053 if (mode == CCmode || mode == CC_UNSmode)
7055 cr_class = ICR_REGS;
7056 p_new_cr = &frv_ifcvt.extra_int_cr;
7058 else if (mode == CC_FPmode)
7060 cr_class = FCR_REGS;
7061 p_new_cr = &frv_ifcvt.extra_fp_cr;
7066 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7067 more &&/|| tests. */
7071 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7072 CC_CCRmode, TRUE, TRUE);
7077 if (ce_info->and_and_p)
7079 old_test = old_false;
7080 test_expr = true_expr;
7081 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7082 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7083 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7087 old_test = old_false;
7088 test_expr = false_expr;
7089 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7090 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7091 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7094 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7095 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7097 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
7099 /* Now add the conditional check insn. */
7100 cc = XEXP (test_expr, 0);
7101 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7102 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7104 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7106 /* Add the new check insn to the list of check insns that need to be
7108 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
7110 if (TARGET_DEBUG_COND_EXEC)
7112 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7115 debug_rtx (*p_true);
7117 fputs ("\nfalse insn:\n", stderr);
7118 debug_rtx (*p_false);
7124 *p_true = *p_false = NULL_RTX;
7126 /* If we allocated a CR register, release it. */
7129 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7130 *p_new_cr = NULL_RTX;
7133 if (TARGET_DEBUG_COND_EXEC)
7134 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7140 /* Return a register which will be loaded with a value if an IF block is
7141 converted to conditional execution. This is used to rewrite instructions
7142 that use constants to ones that just use registers. */
7145 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
7147 int num_alloc = frv_ifcvt.cur_scratch_regs;
7151 /* We know gr0 == 0, so replace any errant uses. */
7152 if (value == const0_rtx)
7153 return gen_rtx_REG (SImode, GPR_FIRST);
7155 /* First search all registers currently loaded to see if we have an
7156 applicable constant. */
7157 if (CONSTANT_P (value)
7158 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7160 for (i = 0; i < num_alloc; i++)
7162 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7163 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7167 /* Have we exhausted the number of registers available? */
7168 if (num_alloc >= GPR_TEMP_NUM)
7171 fprintf (dump_file, "Too many temporary registers allocated\n");
7176 /* Allocate the new register. */
7177 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7181 fputs ("Could not find a scratch register\n", dump_file);
7186 frv_ifcvt.cur_scratch_regs++;
7187 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7191 if (GET_CODE (value) == CONST_INT)
7192 fprintf (dump_file, "Register %s will hold %ld\n",
7193 reg_names[ REGNO (reg)], (long)INTVAL (value));
7195 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7196 fprintf (dump_file, "Register %s will hold LR\n",
7197 reg_names[ REGNO (reg)]);
7200 fprintf (dump_file, "Register %s will hold a saved value\n",
7201 reg_names[ REGNO (reg)]);
7208 /* Update a MEM used in conditional code that might contain an offset to put
7209 the offset into a scratch register, so that the conditional load/store
7210 operations can be used. This function returns the original pointer if the
7211 MEM is valid to use in conditional code, NULL if we can't load up the offset
7212 into a temporary register, or the new MEM if we were successful. */
7215 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7217 rtx addr = XEXP (mem, 0);
7219 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7221 if (GET_CODE (addr) == PLUS)
7223 rtx addr_op0 = XEXP (addr, 0);
7224 rtx addr_op1 = XEXP (addr, 1);
7226 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7228 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7232 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7239 else if (CONSTANT_P (addr))
7240 addr = frv_ifcvt_load_value (addr, insn);
7245 if (addr == NULL_RTX)
7248 else if (XEXP (mem, 0) != addr)
7249 return change_address (mem, mode, addr);
7256 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7257 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7260 single_set_pattern (rtx pattern)
7265 if (GET_CODE (pattern) == COND_EXEC)
7266 pattern = COND_EXEC_CODE (pattern);
7268 if (GET_CODE (pattern) == SET)
7271 else if (GET_CODE (pattern) == PARALLEL)
7273 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7275 rtx sub = XVECEXP (pattern, 0, i);
7277 switch (GET_CODE (sub))
7301 /* A C expression to modify the code described by the conditional if
7302 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7303 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7304 insn cannot be converted to be executed conditionally. */
7307 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7311 rtx orig_ce_pattern = pattern;
7317 if (GET_CODE (pattern) != COND_EXEC)
7320 test = COND_EXEC_TEST (pattern);
7321 if (GET_CODE (test) == AND)
7323 rtx cr = frv_ifcvt.cr_reg;
7326 op0 = XEXP (test, 0);
7327 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7330 op1 = XEXP (test, 1);
7331 test_reg = XEXP (op1, 0);
7332 if (GET_CODE (test_reg) != REG)
7335 /* Is this the first nested if block in this sequence? If so, generate
7336 an andcr or andncr. */
7337 if (! frv_ifcvt.last_nested_if_cr)
7341 frv_ifcvt.last_nested_if_cr = test_reg;
7342 if (GET_CODE (op0) == NE)
7343 and_op = gen_andcr (test_reg, cr, test_reg);
7345 and_op = gen_andncr (test_reg, cr, test_reg);
7347 frv_ifcvt_add_insn (and_op, insn, TRUE);
7350 /* If this isn't the first statement in the nested if sequence, see if we
7351 are dealing with the same register. */
7352 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7355 COND_EXEC_TEST (pattern) = test = op1;
7358 /* If this isn't a nested if, reset state variables. */
7361 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7364 set = single_set_pattern (pattern);
7367 rtx dest = SET_DEST (set);
7368 rtx src = SET_SRC (set);
7369 enum machine_mode mode = GET_MODE (dest);
7371 /* Check for normal binary operators. */
7372 if (mode == SImode && ARITHMETIC_P (src))
7374 op0 = XEXP (src, 0);
7375 op1 = XEXP (src, 1);
7377 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7379 op1 = frv_ifcvt_load_value (op1, insn);
7381 COND_EXEC_CODE (pattern)
7382 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7390 /* For multiply by a constant, we need to handle the sign extending
7391 correctly. Add a USE of the value after the multiply to prevent flow
7392 from cratering because only one register out of the two were used. */
7393 else if (mode == DImode && GET_CODE (src) == MULT)
7395 op0 = XEXP (src, 0);
7396 op1 = XEXP (src, 1);
7397 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7399 op1 = frv_ifcvt_load_value (op1, insn);
7402 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7403 COND_EXEC_CODE (pattern)
7404 = gen_rtx_SET (VOIDmode, dest,
7405 gen_rtx_MULT (DImode, op0, op1));
7411 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7414 /* If we are just loading a constant created for a nested conditional
7415 execution statement, just load the constant without any conditional
7416 execution, since we know that the constant will not interfere with any
7418 else if (frv_ifcvt.scratch_insns_bitmap
7419 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7421 /* We must not unconditionally set a reg set used as
7422 scratch in the THEN branch if the same reg is live
7423 in the ELSE branch. */
7424 && REG_P (SET_DEST (set))
7425 && (! ce_info->else_bb
7426 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7427 || ! (REGNO_REG_SET_P
7428 (ce_info->else_bb->global_live_at_start,
7429 REGNO (SET_DEST (set))))))
7432 else if (mode == QImode || mode == HImode || mode == SImode
7435 int changed_p = FALSE;
7437 /* Check for just loading up a constant */
7438 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7440 src = frv_ifcvt_load_value (src, insn);
7447 /* See if we need to fix up stores */
7448 if (GET_CODE (dest) == MEM)
7450 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7455 else if (new_mem != dest)
7462 /* See if we need to fix up loads */
7463 if (GET_CODE (src) == MEM)
7465 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7470 else if (new_mem != src)
7477 /* If either src or destination changed, redo SET. */
7479 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7482 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7483 rewriting the CC register to be the same as the paired CC/CR register
7485 else if (mode == CC_CCRmode && COMPARISON_P (src))
7487 int regno = REGNO (XEXP (src, 0));
7490 if (ce_info->pass > 1
7491 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7492 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7494 src = gen_rtx_fmt_ee (GET_CODE (src),
7496 frv_ifcvt.nested_cc_reg,
7500 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7501 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7504 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7505 else if (ce_info->pass > 1
7506 && GET_CODE (dest) == REG
7507 && CC_P (REGNO (dest))
7508 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7509 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7511 && GET_CODE (src) == COMPARE)
7513 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7514 COND_EXEC_CODE (pattern)
7515 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7519 if (TARGET_DEBUG_COND_EXEC)
7521 rtx orig_pattern = PATTERN (insn);
7523 PATTERN (insn) = pattern;
7525 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7529 PATTERN (insn) = orig_pattern;
7535 if (TARGET_DEBUG_COND_EXEC)
7537 rtx orig_pattern = PATTERN (insn);
7539 PATTERN (insn) = orig_ce_pattern;
7541 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7545 PATTERN (insn) = orig_pattern;
7552 /* A C expression to perform any final machine dependent modifications in
7553 converting code to conditional execution in the code described by the
7554 conditional if information CE_INFO. */
7557 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7561 rtx p = frv_ifcvt.added_insns_list;
7564 /* Loop inserting the check insns. The last check insn is the first test,
7565 and is the appropriate place to insert constants. */
7571 rtx check_and_insert_insns = XEXP (p, 0);
7574 check_insn = XEXP (check_and_insert_insns, 0);
7575 existing_insn = XEXP (check_and_insert_insns, 1);
7578 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7579 the existing insn, otherwise it is to be inserted AFTER. */
7580 if (check_and_insert_insns->jump)
7582 emit_insn_before (check_insn, existing_insn);
7583 check_and_insert_insns->jump = 0;
7586 emit_insn_after (check_insn, existing_insn);
7588 free_EXPR_LIST_node (check_and_insert_insns);
7589 free_EXPR_LIST_node (old_p);
7591 while (p != NULL_RTX);
7593 /* Load up any constants needed into temp gprs */
7594 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7596 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7597 if (! frv_ifcvt.scratch_insns_bitmap)
7598 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7599 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7600 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7603 frv_ifcvt.added_insns_list = NULL_RTX;
7604 frv_ifcvt.cur_scratch_regs = 0;
7608 /* A C expression to cancel any machine dependent modifications in converting
7609 code to conditional execution in the code described by the conditional if
7610 information CE_INFO. */
7613 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7616 rtx p = frv_ifcvt.added_insns_list;
7618 /* Loop freeing up the EXPR_LIST's allocated. */
7619 while (p != NULL_RTX)
7621 rtx check_and_jump = XEXP (p, 0);
7625 free_EXPR_LIST_node (check_and_jump);
7626 free_EXPR_LIST_node (old_p);
7629 /* Release any temporary gprs allocated. */
7630 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7631 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7633 frv_ifcvt.added_insns_list = NULL_RTX;
7634 frv_ifcvt.cur_scratch_regs = 0;
7638 /* A C expression for the size in bytes of the trampoline, as an integer.
7642 setlo #0, <static_chain>
7644 sethi #0, <static_chain>
7645 jmpl @(gr0,<jmp_reg>) */
7648 frv_trampoline_size (void)
7651 /* Allocate room for the function descriptor and the lddi
7654 return 5 /* instructions */ * 4 /* instruction size. */;
7658 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7659 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7660 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7661 should be passed to the function when it is called.
7666 setlo #0, <static_chain>
7668 sethi #0, <static_chain>
7669 jmpl @(gr0,<jmp_reg>) */
7672 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7674 rtx sc_reg = force_reg (Pmode, static_chain);
7676 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7679 GEN_INT (frv_trampoline_size ()), SImode,
7685 /* Many machines have some registers that cannot be copied directly to or from
7686 memory or even from other types of registers. An example is the `MQ'
7687 register, which on most machines, can only be copied to or from general
7688 registers, but not memory. Some machines allow copying all registers to and
7689 from memory, but require a scratch register for stores to some memory
7690 locations (e.g., those with symbolic address on the RT, and those with
7691 certain symbolic address on the SPARC when compiling PIC). In some cases,
7692 both an intermediate and a scratch register are required.
7694 You should define these macros to indicate to the reload phase that it may
7695 need to allocate at least one register for a reload in addition to the
7696 register to contain the data. Specifically, if copying X to a register
7697 CLASS in MODE requires an intermediate register, you should define
7698 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7699 whose registers can be used as intermediate registers or scratch registers.
7701 If copying a register CLASS in MODE to X requires an intermediate or scratch
7702 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7703 largest register class required. If the requirements for input and output
7704 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7705 instead of defining both macros identically.
7707 The values returned by these macros are often `GENERAL_REGS'. Return
7708 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7709 to or from a register of CLASS in MODE without requiring a scratch register.
7710 Do not define this macro if it would always return `NO_REGS'.
7712 If a scratch register is required (either with or without an intermediate
7713 register), you should define patterns for `reload_inM' or `reload_outM', as
7714 required.. These patterns, which will normally be implemented with a
7715 `define_expand', should be similar to the `movM' patterns, except that
7716 operand 2 is the scratch register.
7718 Define constraints for the reload register and scratch register that contain
7719 a single register class. If the original reload register (whose class is
7720 CLASS) can meet the constraint given in the pattern, the value returned by
7721 these macros is used for the class of the scratch register. Otherwise, two
7722 additional reload registers are required. Their classes are obtained from
7723 the constraints in the insn pattern.
7725 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7726 either be in a hard register or in memory. Use `true_regnum' to find out;
7727 it will return -1 if the pseudo is in memory and the hard register number if
7728 it is in a register.
7730 These macros should not be used in the case where a particular class of
7731 registers can only be copied to memory and not to another class of
7732 registers. In that case, secondary reload registers are not needed and
7733 would not be helpful. Instead, a stack location must be used to perform the
7734 copy and the `movM' pattern should use memory as an intermediate storage.
7735 This case often occurs between floating-point and general registers. */
7738 frv_secondary_reload_class (enum reg_class class,
7739 enum machine_mode mode ATTRIBUTE_UNUSED,
7741 int in_p ATTRIBUTE_UNUSED)
7751 /* Accumulators/Accumulator guard registers need to go through floating
7757 if (x && GET_CODE (x) == REG)
7759 int regno = REGNO (x);
7761 if (ACC_P (regno) || ACCG_P (regno))
7766 /* Nonzero constants should be loaded into an FPR through a GPR. */
7770 if (x && CONSTANT_P (x) && !ZERO_P (x))
7776 /* All of these types need gpr registers. */
7788 /* The accumulators need fpr registers */
7801 /* A C expression whose value is nonzero if pseudos that have been assigned to
7802 registers of class CLASS would likely be spilled because registers of CLASS
7803 are needed for spill registers.
7805 The default value of this macro returns 1 if CLASS has exactly one register
7806 and zero otherwise. On most machines, this default should be used. Only
7807 define this macro to some other expression if pseudo allocated by
7808 `local-alloc.c' end up in memory because their hard registers were needed
7809 for spill registers. If this macro returns nonzero for those classes, those
7810 pseudos will only be allocated by `global.c', which knows how to reallocate
7811 the pseudo to another register. If there would not be another register
7812 available for reallocation, you should not change the definition of this
7813 macro since the only effect of such a definition would be to slow down
7814 register allocation. */
7817 frv_class_likely_spilled_p (enum reg_class class)
7844 /* An expression for the alignment of a structure field FIELD if the
7845 alignment computed in the usual way is COMPUTED. GCC uses this
7846 value instead of the value in `BIGGEST_ALIGNMENT' or
7847 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7849 /* The definition type of the bit field data is either char, short, long or
7850 long long. The maximum bit size is the number of bits of its own type.
7852 The bit field data is assigned to a storage unit that has an adequate size
7853 for bit field data retention and is located at the smallest address.
7855 Consecutive bit field data are packed at consecutive bits having the same
7856 storage unit, with regard to the type, beginning with the MSB and continuing
7859 If a field to be assigned lies over a bit field type boundary, its
7860 assignment is completed by aligning it with a boundary suitable for the
7863 When a bit field having a bit length of 0 is declared, it is forcibly
7864 assigned to the next storage unit.
7877 &x 00000000 00000000 00000000 00000000
7880 &x+4 00000000 00000000 00000000 00000000
7883 &x+8 00000000 00000000 00000000 00000000
7886 &x+12 00000000 00000000 00000000 00000000
7892 frv_adjust_field_align (tree field, int computed)
7894 /* Make sure that the bitfield is not wider than the type. */
7895 if (DECL_BIT_FIELD (field)
7896 && !DECL_ARTIFICIAL (field))
7898 tree parent = DECL_CONTEXT (field);
7899 tree prev = NULL_TREE;
7902 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7904 if (TREE_CODE (cur) != FIELD_DECL)
7913 /* If this isn't a :0 field and if the previous element is a bitfield
7914 also, see if the type is different, if so, we will need to align the
7915 bit-field to the next boundary. */
7917 && ! DECL_PACKED (field)
7918 && ! integer_zerop (DECL_SIZE (field))
7919 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7921 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7922 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7923 computed = (prev_align > cur_align) ? prev_align : cur_align;
7931 /* A C expression that is nonzero if it is permissible to store a value of mode
7932 MODE in hard register number REGNO (or in several registers starting with
7933 that one). For a machine where all registers are equivalent, a suitable
7936 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7938 It is not necessary for this macro to check for the numbers of fixed
7939 registers, because the allocation mechanism considers them to be always
7942 On some machines, double-precision values must be kept in even/odd register
7943 pairs. The way to implement that is to define this macro to reject odd
7944 register numbers for such modes.
7946 The minimum requirement for a mode to be OK in a register is that the
7947 `movMODE' instruction pattern support moves between the register and any
7948 other hard register for which the mode is OK; and that moving a value into
7949 the register and back out not alter it.
7951 Since the same instruction used to move `SImode' will work for all narrower
7952 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7953 to distinguish between these modes, provided you define patterns `movhi',
7954 etc., to take advantage of this. This is useful because of the interaction
7955 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7956 all integer modes to be tieable.
7958 Many machines have special registers for floating point arithmetic. Often
7959 people assume that floating point machine modes are allowed only in floating
7960 point registers. This is not true. Any registers that can hold integers
7961 can safely *hold* a floating point machine mode, whether or not floating
7962 arithmetic can be done on it in those registers. Integer move instructions
7963 can be used to move the values.
7965 On some machines, though, the converse is true: fixed-point machine modes
7966 may not go in floating registers. This is true if the floating registers
7967 normalize any value stored in them, because storing a non-floating value
7968 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7969 fixed-point machine modes in floating registers. But if the floating
7970 registers do not automatically normalize, if you can store any bit pattern
7971 in one and retrieve it unchanged without a trap, then any machine mode may
7972 go in a floating register, so you can define this macro to say so.
7974 The primary significance of special floating registers is rather that they
7975 are the registers acceptable in floating point arithmetic instructions.
7976 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7977 writing the proper constraints for those instructions.
7979 On some machines, the floating registers are especially slow to access, so
7980 that it is better to store a value in a stack frame than in such a register
7981 if floating point arithmetic is not being done. As long as the floating
7982 registers are not in class `GENERAL_REGS', they will not be used unless some
7983 pattern's constraint asks for one. */
7986 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7995 return ICC_P (regno) || GPR_P (regno);
7998 return CR_P (regno) || GPR_P (regno);
8001 return FCC_P (regno) || GPR_P (regno);
8007 /* Set BASE to the first register in REGNO's class. Set MASK to the
8008 bits that must be clear in (REGNO - BASE) for the register to be
8010 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
8014 /* ACCGs store one byte. Two-byte quantities must start in
8015 even-numbered registers, four-byte ones in registers whose
8016 numbers are divisible by four, and so on. */
8018 mask = GET_MODE_SIZE (mode) - 1;
8022 /* The other registers store one word. */
8023 if (GPR_P (regno) || regno == AP_FIRST)
8026 else if (FPR_P (regno))
8029 else if (ACC_P (regno))
8032 else if (SPR_P (regno))
8033 return mode == SImode;
8035 /* Fill in the table. */
8039 /* Anything smaller than an SI is OK in any word-sized register. */
8040 if (GET_MODE_SIZE (mode) < 4)
8043 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8045 return (((regno - base) & mask) == 0);
8052 /* A C expression for the number of consecutive hard registers, starting at
8053 register number REGNO, required to hold a value of mode MODE.
8055 On a machine where all registers are exactly one word, a suitable definition
8058 #define HARD_REGNO_NREGS(REGNO, MODE) \
8059 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8060 / UNITS_PER_WORD)) */
8062 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8063 that we can build the appropriate instructions to properly reload the
8064 values. Also, make the byte-sized accumulator guards use one guard
8068 frv_hard_regno_nregs (int regno, enum machine_mode mode)
8071 return GET_MODE_SIZE (mode);
8073 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8077 /* A C expression for the maximum number of consecutive registers of
8078 class CLASS needed to hold a value of mode MODE.
8080 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8081 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8082 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8084 This macro helps control the handling of multiple-word values in
8087 This declaration is required. */
8090 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
8092 if (class == ACCG_REGS)
8093 /* An N-byte value requires N accumulator guards. */
8094 return GET_MODE_SIZE (mode);
8096 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8100 /* A C expression that is nonzero if X is a legitimate constant for an
8101 immediate operand on the target machine. You can assume that X satisfies
8102 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8103 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8106 frv_legitimate_constant_p (rtx x)
8108 enum machine_mode mode = GET_MODE (x);
8110 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8111 means that the move expanders will be expected to deal with most
8112 kinds of constant, regardless of what we return here.
8114 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8115 a constant can be entered into reg_equiv_constant[]. If we return true,
8116 reload can create new instances of the constant whenever it likes.
8118 The idea is therefore to accept as many constants as possible (to give
8119 reload more freedom) while rejecting constants that can only be created
8120 at certain times. In particular, anything with a symbolic component will
8121 require use of the pseudo FDPIC register, which is only available before
8124 return LEGITIMATE_PIC_OPERAND_P (x);
8126 /* All of the integer constants are ok. */
8127 if (GET_CODE (x) != CONST_DOUBLE)
8130 /* double integer constants are ok. */
8131 if (mode == VOIDmode || mode == DImode)
8134 /* 0 is always ok. */
8135 if (x == CONST0_RTX (mode))
8138 /* If floating point is just emulated, allow any constant, since it will be
8139 constructed in the GPRs. */
8140 if (!TARGET_HAS_FPRS)
8143 if (mode == DFmode && !TARGET_DOUBLE)
8146 /* Otherwise store the constant away and do a load. */
8150 /* A C expression for the cost of moving data from a register in class FROM to
8151 one in class TO. The classes are expressed using the enumeration values
8152 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8153 interpreted relative to that.
8155 It is not required that the cost always equal 2 when FROM is the same as TO;
8156 on some machines it is expensive to move between registers if they are not
8159 If reload sees an insn consisting of a single `set' between two hard
8160 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8161 value of 2, reload does not check to ensure that the constraints of the insn
8162 are met. Setting a cost of other than 2 will allow reload to verify that
8163 the constraints are met. You should do this if the `movM' pattern's
8164 constraints do not allow such copying. */
8166 #define HIGH_COST 40
8167 #define MEDIUM_COST 3
8171 frv_register_move_cost (enum reg_class from, enum reg_class to)
8255 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8256 use ".picptr" to generate safe relocations for PIC code. We also
8257 need a fixup entry for aligned (non-debugging) code. */
8260 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8262 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8264 if (GET_CODE (value) == CONST
8265 || GET_CODE (value) == SYMBOL_REF
8266 || GET_CODE (value) == LABEL_REF)
8268 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8269 && SYMBOL_REF_FUNCTION_P (value))
8271 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8272 output_addr_const (asm_out_file, value);
8273 fputs (")\n", asm_out_file);
8276 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8277 && frv_function_symbol_referenced_p (value))
8279 if (aligned_p && !TARGET_FDPIC)
8281 static int label_num = 0;
8285 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8286 p = (* targetm.strip_name_encoding) (buf);
8288 fprintf (asm_out_file, "%s:\n", p);
8289 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8290 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8291 fprintf (asm_out_file, "\t.previous\n");
8293 assemble_integer_with_op ("\t.picptr\t", value);
8298 /* We've set the unaligned SI op to NULL, so we always have to
8299 handle the unaligned case here. */
8300 assemble_integer_with_op ("\t.4byte\t", value);
8304 return default_assemble_integer (value, size, aligned_p);
8307 /* Function to set up the backend function structure. */
8309 static struct machine_function *
8310 frv_init_machine_status (void)
8312 return ggc_alloc_cleared (sizeof (struct machine_function));
8315 /* Implement TARGET_SCHED_ISSUE_RATE. */
8318 frv_issue_rate (void)
8323 switch (frv_cpu_type)
8327 case FRV_CPU_SIMPLE:
8335 case FRV_CPU_GENERIC:
8337 case FRV_CPU_TOMCAT:
8345 /* A for_each_rtx callback. If X refers to an accumulator, return
8346 ACC_GROUP_ODD if the bit 2 of the register number is set and
8347 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
8351 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
8355 if (ACC_P (REGNO (*x)))
8356 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8357 if (ACCG_P (REGNO (*x)))
8358 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8363 /* Return the value of INSN's acc_group attribute. */
8366 frv_acc_group (rtx insn)
8368 /* This distinction only applies to the FR550 packing constraints. */
8369 if (frv_cpu_type != FRV_CPU_FR550)
8370 return ACC_GROUP_NONE;
8371 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
8374 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
8375 INSN will try to claim first. Since this value depends only on the
8376 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
8379 frv_insn_unit (rtx insn)
8381 enum attr_type type;
8383 type = get_attr_type (insn);
8384 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
8386 /* We haven't seen this type of instruction before. */
8390 /* Issue the instruction on its own to see which unit it prefers. */
8391 state = alloca (state_size ());
8392 state_reset (state);
8393 state_transition (state, insn);
8395 /* Find out which unit was taken. */
8396 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
8397 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
8400 if (unit == ARRAY_SIZE (frv_unit_codes))
8403 frv_type_to_unit[type] = unit;
8405 return frv_type_to_unit[type];
8408 /* Return true if INSN issues to a branch unit. */
8411 frv_issues_to_branch_unit_p (rtx insn)
8413 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
8416 /* The current state of the packing pass, implemented by frv_pack_insns. */
8418 /* The state of the pipeline DFA. */
8421 /* Which hardware registers are set within the current packet,
8422 and the conditions under which they are set. */
8423 regstate_t regstate[FIRST_PSEUDO_REGISTER];
8425 /* The memory locations that have been modified so far in this
8426 packet. MEM is the memref and COND is the regstate_t condition
8427 under which it is set. */
8433 /* The number of valid entries in MEMS. The value is larger than
8434 ARRAY_SIZE (mems) if there were too many mems to record. */
8435 unsigned int num_mems;
8437 /* The maximum number of instructions that can be packed together. */
8438 unsigned int issue_rate;
8440 /* The instructions in the packet, partitioned into groups. */
8441 struct frv_packet_group {
8442 /* How many instructions in the packet belong to this group. */
8443 unsigned int num_insns;
8445 /* A list of the instructions that belong to this group, in the order
8446 they appear in the rtl stream. */
8447 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8449 /* The contents of INSNS after they have been sorted into the correct
8450 assembly-language order. Element X issues to unit X. The list may
8451 contain extra nops. */
8452 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
8454 /* The member of frv_nops[] to use in sorted[]. */
8456 } groups[NUM_GROUPS];
8458 /* The instructions that make up the current packet. */
8459 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8460 unsigned int num_insns;
8463 /* Return the regstate_t flags for the given COND_EXEC condition.
8464 Abort if the condition isn't in the right form. */
8467 frv_cond_flags (rtx cond)
8469 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8470 && GET_CODE (XEXP (cond, 0)) == REG
8471 && CR_P (REGNO (XEXP (cond, 0)))
8472 && XEXP (cond, 1) == const0_rtx)
8473 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8474 | (GET_CODE (cond) == NE
8476 : REGSTATE_IF_FALSE));
8481 /* Return true if something accessed under condition COND2 can
8482 conflict with something written under condition COND1. */
8485 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
8487 /* If either reference was unconditional, we have a conflict. */
8488 if ((cond1 & REGSTATE_IF_EITHER) == 0
8489 || (cond2 & REGSTATE_IF_EITHER) == 0)
8492 /* The references might conflict if they were controlled by
8494 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
8497 /* They definitely conflict if they are controlled by the
8499 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
8506 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
8507 the current packet. DATA points to a regstate_t that describes the
8508 condition under which *X might be set or used. */
8511 frv_registers_conflict_p_1 (rtx *x, void *data)
8513 unsigned int regno, i;
8516 cond = *(regstate_t *) data;
8518 if (GET_CODE (*x) == REG)
8519 FOR_EACH_REGNO (regno, *x)
8520 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
8521 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
8524 if (GET_CODE (*x) == MEM)
8526 /* If we ran out of memory slots, assume a conflict. */
8527 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
8530 /* Check for output or true dependencies with earlier MEMs. */
8531 for (i = 0; i < frv_packet.num_mems; i++)
8532 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
8534 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
8538 if (output_dependence (frv_packet.mems[i].mem, *x))
8543 /* The return values of calls aren't significant: they describe
8544 the effect of the call as a whole, not of the insn itself. */
8545 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
8547 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
8552 /* Check subexpressions. */
8557 /* Return true if something in X might depend on an instruction
8558 in the current packet. */
8561 frv_registers_conflict_p (rtx x)
8566 if (GET_CODE (x) == COND_EXEC)
8568 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
8571 flags |= frv_cond_flags (XEXP (x, 0));
8574 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
8578 /* A note_stores callback. DATA points to the regstate_t condition
8579 under which X is modified. Update FRV_PACKET accordingly. */
8582 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8586 if (GET_CODE (x) == REG)
8587 FOR_EACH_REGNO (regno, x)
8588 frv_packet.regstate[regno] |= *(regstate_t *) data;
8590 if (GET_CODE (x) == MEM)
8592 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
8594 frv_packet.mems[frv_packet.num_mems].mem = x;
8595 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
8597 frv_packet.num_mems++;
8602 /* Update the register state information for an instruction whose
8606 frv_registers_update (rtx x)
8610 flags = REGSTATE_MODIFIED;
8611 if (GET_CODE (x) == COND_EXEC)
8613 flags |= frv_cond_flags (XEXP (x, 0));
8616 note_stores (x, frv_registers_update_1, &flags);
8620 /* Initialize frv_packet for the start of a new packet. */
8623 frv_start_packet (void)
8625 enum frv_insn_group group;
8627 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
8628 frv_packet.num_mems = 0;
8629 frv_packet.num_insns = 0;
8630 for (group = 0; group < NUM_GROUPS; group++)
8631 frv_packet.groups[group].num_insns = 0;
8635 /* Likewise for the start of a new basic block. */
8638 frv_start_packet_block (void)
8640 state_reset (frv_packet.dfa_state);
8641 frv_start_packet ();
8645 /* Finish the current packet, if any, and start a new one. Call
8646 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
8649 frv_finish_packet (void (*handle_packet) (void))
8651 if (frv_packet.num_insns > 0)
8654 state_transition (frv_packet.dfa_state, 0);
8655 frv_start_packet ();
8660 /* Return true if INSN can be added to the current packet. Update
8661 the DFA state on success. */
8664 frv_pack_insn_p (rtx insn)
8666 /* See if the packet is already as long as it can be. */
8667 if (frv_packet.num_insns == frv_packet.issue_rate)
8670 /* If the scheduler thought that an instruction should start a packet,
8671 it's usually a good idea to believe it. It knows much more about
8672 the latencies than we do.
8674 There are some exceptions though:
8676 - Conditional instructions are scheduled on the assumption that
8677 they will be executed. This is usually a good thing, since it
8678 tends to avoid unnecessary stalls in the conditional code.
8679 But we want to pack conditional instructions as tightly as
8680 possible, in order to optimize the case where they aren't
8683 - The scheduler will always put branches on their own, even
8684 if there's no real dependency.
8686 - There's no point putting a call in its own packet unless
8688 if (frv_packet.num_insns > 0
8689 && GET_CODE (insn) == INSN
8690 && GET_MODE (insn) == TImode
8691 && GET_CODE (PATTERN (insn)) != COND_EXEC)
8694 /* Check for register conflicts. Don't do this for setlo since any
8695 conflict will be with the partnering sethi, with which it can
8697 if (get_attr_type (insn) != TYPE_SETLO)
8698 if (frv_registers_conflict_p (PATTERN (insn)))
8701 return state_transition (frv_packet.dfa_state, insn) < 0;
8705 /* Add instruction INSN to the current packet. */
8708 frv_add_insn_to_packet (rtx insn)
8710 struct frv_packet_group *packet_group;
8712 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8713 packet_group->insns[packet_group->num_insns++] = insn;
8714 frv_packet.insns[frv_packet.num_insns++] = insn;
8716 frv_registers_update (PATTERN (insn));
8720 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
8721 packet ends in a branch or call, insert the nop before it, otherwise
8725 frv_insert_nop_in_packet (rtx insn)
8727 struct frv_packet_group *packet_group;
8730 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8731 last = frv_packet.insns[frv_packet.num_insns - 1];
8732 if (GET_CODE (last) != INSN)
8734 insn = emit_insn_before (PATTERN (insn), last);
8735 frv_packet.insns[frv_packet.num_insns - 1] = insn;
8736 frv_packet.insns[frv_packet.num_insns++] = last;
8740 insn = emit_insn_after (PATTERN (insn), last);
8741 frv_packet.insns[frv_packet.num_insns++] = insn;
8743 packet_group->insns[packet_group->num_insns++] = insn;
8747 /* If packing is enabled, divide the instructions into packets and
8748 return true. Call HANDLE_PACKET for each complete packet. */
8751 frv_for_each_packet (void (*handle_packet) (void))
8753 rtx insn, next_insn;
8755 frv_packet.issue_rate = frv_issue_rate ();
8757 /* Early exit if we don't want to pack insns. */
8759 || !flag_schedule_insns_after_reload
8760 || TARGET_NO_VLIW_BRANCH
8761 || frv_packet.issue_rate == 1)
8764 /* Set up the initial packing state. */
8766 frv_packet.dfa_state = alloca (state_size ());
8768 frv_start_packet_block ();
8769 for (insn = get_insns (); insn != 0; insn = next_insn)
8774 code = GET_CODE (insn);
8775 next_insn = NEXT_INSN (insn);
8777 if (code == CODE_LABEL)
8779 frv_finish_packet (handle_packet);
8780 frv_start_packet_block ();
8784 switch (GET_CODE (PATTERN (insn)))
8793 /* Calls mustn't be packed on a TOMCAT. */
8794 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
8795 frv_finish_packet (handle_packet);
8797 /* Since the last instruction in a packet determines the EH
8798 region, any exception-throwing instruction must come at
8799 the end of reordered packet. Insns that issue to a
8800 branch unit are bound to come last; for others it's
8801 too hard to predict. */
8802 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
8803 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
8804 frv_finish_packet (handle_packet);
8806 /* Finish the current packet if we can't add INSN to it.
8807 Simulate cycles until INSN is ready to issue. */
8808 if (!frv_pack_insn_p (insn))
8810 frv_finish_packet (handle_packet);
8811 while (!frv_pack_insn_p (insn))
8812 state_transition (frv_packet.dfa_state, 0);
8815 /* Add the instruction to the packet. */
8816 frv_add_insn_to_packet (insn);
8818 /* Calls and jumps end a packet, as do insns that throw
8820 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
8821 frv_finish_packet (handle_packet);
8825 frv_finish_packet (handle_packet);
8830 /* Subroutine of frv_sort_insn_group. We are trying to sort
8831 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
8832 language order. We have already picked a new position for
8833 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
8834 These instructions will occupy elements [0, LOWER_SLOT) and
8835 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
8836 the DFA state after issuing these instructions.
8838 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
8839 of the unused instructions. Return true if one such permutation gives
8840 a valid ordering, leaving the successful permutation in sorted[].
8841 Do not modify sorted[] until a valid permutation is found. */
8844 frv_sort_insn_group_1 (enum frv_insn_group group,
8845 unsigned int lower_slot, unsigned int upper_slot,
8846 unsigned int issued, unsigned int num_insns,
8849 struct frv_packet_group *packet_group;
8855 /* Early success if we've filled all the slots. */
8856 if (lower_slot == upper_slot)
8859 packet_group = &frv_packet.groups[group];
8860 dfa_size = state_size ();
8861 test_state = alloca (dfa_size);
8863 /* Try issuing each unused instruction. */
8864 for (i = num_insns - 1; i + 1 != 0; i--)
8865 if (~issued & (1 << i))
8867 insn = packet_group->sorted[i];
8868 memcpy (test_state, state, dfa_size);
8869 if (state_transition (test_state, insn) < 0
8870 && cpu_unit_reservation_p (test_state,
8871 NTH_UNIT (group, upper_slot - 1))
8872 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
8873 issued | (1 << i), num_insns,
8876 packet_group->sorted[upper_slot - 1] = insn;
8884 /* Compare two instructions by their frv_insn_unit. */
8887 frv_compare_insns (const void *first, const void *second)
8889 const rtx *insn1 = first, *insn2 = second;
8890 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
8893 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
8894 and sort it into assembly language order. See frv.md for a description of
8898 frv_sort_insn_group (enum frv_insn_group group)
8900 struct frv_packet_group *packet_group;
8901 unsigned int first, i, nop, max_unit, num_slots;
8902 state_t state, test_state;
8905 packet_group = &frv_packet.groups[group];
8906 if (packet_group->num_insns == 0)
8909 /* Copy insns[] to sorted[]. */
8910 memcpy (packet_group->sorted, packet_group->insns,
8911 sizeof (rtx) * packet_group->num_insns);
8913 /* Sort sorted[] by the unit that each insn tries to take first. */
8914 if (packet_group->num_insns > 1)
8915 qsort (packet_group->sorted, packet_group->num_insns,
8916 sizeof (rtx), frv_compare_insns);
8918 /* That's always enough for branch and control insns. */
8919 if (group == GROUP_B || group == GROUP_C)
8922 dfa_size = state_size ();
8923 state = alloca (dfa_size);
8924 test_state = alloca (dfa_size);
8926 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
8927 consecutively and such that the DFA takes unit X when sorted[X]
8928 is added. Set STATE to the new DFA state. */
8929 state_reset (test_state);
8930 for (first = 0; first < packet_group->num_insns; first++)
8932 memcpy (state, test_state, dfa_size);
8933 if (state_transition (test_state, packet_group->sorted[first]) >= 0
8934 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
8938 /* If all the instructions issued in ascending order, we're done. */
8939 if (first == packet_group->num_insns)
8942 /* Add nops to the end of sorted[] and try each permutation until
8943 we find one that works. */
8944 for (nop = 0; nop < frv_num_nops; nop++)
8946 max_unit = frv_insn_unit (frv_nops[nop]);
8947 if (frv_unit_groups[max_unit] == group)
8949 packet_group->nop = frv_nops[nop];
8950 num_slots = UNIT_NUMBER (max_unit) + 1;
8951 for (i = packet_group->num_insns; i < num_slots; i++)
8952 packet_group->sorted[i] = frv_nops[nop];
8953 if (frv_sort_insn_group_1 (group, first, num_slots,
8954 (1 << first) - 1, num_slots, state))
8961 /* Sort the current packet into assembly-language order. Set packing
8962 flags as appropriate. */
8965 frv_reorder_packet (void)
8967 unsigned int cursor[NUM_GROUPS];
8968 rtx insns[ARRAY_SIZE (frv_unit_groups)];
8969 unsigned int unit, to, from;
8970 enum frv_insn_group group;
8971 struct frv_packet_group *packet_group;
8973 /* First sort each group individually. */
8974 for (group = 0; group < NUM_GROUPS; group++)
8977 frv_sort_insn_group (group);
8980 /* Go through the unit template and try add an instruction from
8981 that unit's group. */
8983 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
8985 group = frv_unit_groups[unit];
8986 packet_group = &frv_packet.groups[group];
8987 if (cursor[group] < packet_group->num_insns)
8989 /* frv_reorg should have added nops for us. */
8990 if (packet_group->sorted[cursor[group]] == packet_group->nop)
8992 insns[to++] = packet_group->sorted[cursor[group]++];
8996 if (to != frv_packet.num_insns)
8999 /* Clear the last instruction's packing flag, thus marking the end of
9000 a packet. Reorder the other instructions relative to it. */
9001 CLEAR_PACKING_FLAG (insns[to - 1]);
9002 for (from = 0; from < to - 1; from++)
9004 remove_insn (insns[from]);
9005 add_insn_before (insns[from], insns[to - 1]);
9006 SET_PACKING_FLAG (insns[from]);
9011 /* Divide instructions into packets. Reorder the contents of each
9012 packet so that they are in the correct assembly-language order.
9014 Since this pass can change the raw meaning of the rtl stream, it must
9015 only be called at the last minute, just before the instructions are
9019 frv_pack_insns (void)
9021 if (frv_for_each_packet (frv_reorder_packet))
9022 frv_insn_packing_flag = 0;
9024 frv_insn_packing_flag = -1;
9027 /* See whether we need to add nops to group GROUP in order to
9028 make a valid packet. */
9031 frv_fill_unused_units (enum frv_insn_group group)
9033 unsigned int non_nops, nops, i;
9034 struct frv_packet_group *packet_group;
9036 packet_group = &frv_packet.groups[group];
9038 /* Sort the instructions into assembly-language order.
9039 Use nops to fill slots that are otherwise unused. */
9040 frv_sort_insn_group (group);
9042 /* See how many nops are needed before the final useful instruction. */
9044 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
9045 while (packet_group->sorted[i++] == packet_group->nop)
9048 /* Insert that many nops into the instruction stream. */
9050 frv_insert_nop_in_packet (packet_group->nop);
9053 /* Used by frv_reorg to keep track of the current packet's address. */
9054 static unsigned int frv_packet_address;
9056 /* If the current packet falls through to a label, try to pad the packet
9057 with nops in order to fit the label's alignment requirements. */
9060 frv_align_label (void)
9062 unsigned int alignment, target, nop;
9063 rtx x, last, barrier, label;
9065 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
9066 maximum alignment of that packet, LABEL to the last label between
9067 the packets, and BARRIER to the last barrier. */
9068 last = frv_packet.insns[frv_packet.num_insns - 1];
9069 label = barrier = 0;
9071 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
9075 unsigned int subalign = 1 << label_to_alignment (x);
9076 alignment = MAX (alignment, subalign);
9083 /* If -malign-labels, and the packet falls through to an unaligned
9084 label, try introducing a nop to align that label to 8 bytes. */
9085 if (TARGET_ALIGN_LABELS
9088 && frv_packet.num_insns < frv_packet.issue_rate)
9089 alignment = MAX (alignment, 8);
9091 /* Advance the address to the end of the current packet. */
9092 frv_packet_address += frv_packet.num_insns * 4;
9094 /* Work out the target address, after alignment. */
9095 target = (frv_packet_address + alignment - 1) & -alignment;
9097 /* If the packet falls through to the label, try to find an efficient
9098 padding sequence. */
9101 /* First try adding nops to the current packet. */
9102 for (nop = 0; nop < frv_num_nops; nop++)
9103 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
9105 frv_insert_nop_in_packet (frv_nops[nop]);
9106 frv_packet_address += 4;
9109 /* If we still haven't reached the target, add some new packets that
9110 contain only nops. If there are two types of nop, insert an
9111 alternating sequence of frv_nops[0] and frv_nops[1], which will
9112 lead to packets like:
9119 etc. Just emit frv_nops[0] if that's the only nop we have. */
9120 last = frv_packet.insns[frv_packet.num_insns - 1];
9122 while (frv_packet_address < target)
9124 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
9125 frv_packet_address += 4;
9126 if (frv_num_nops > 1)
9131 frv_packet_address = target;
9134 /* Subroutine of frv_reorg, called after each packet has been constructed
9138 frv_reorg_packet (void)
9140 frv_fill_unused_units (GROUP_I);
9141 frv_fill_unused_units (GROUP_FM);
9145 /* Add an instruction with pattern NOP to frv_nops[]. */
9148 frv_register_nop (rtx nop)
9150 nop = make_insn_raw (nop);
9151 NEXT_INSN (nop) = 0;
9152 PREV_INSN (nop) = 0;
9153 frv_nops[frv_num_nops++] = nop;
9156 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
9157 into packets and check whether we need to insert nops in order to
9158 fulfill the processor's issue requirements. Also, if the user has
9159 requested a certain alignment for a label, try to meet that alignment
9160 by inserting nops in the previous packet. */
9166 frv_register_nop (gen_nop ());
9168 frv_register_nop (gen_mnop ());
9169 if (TARGET_HARD_FLOAT)
9170 frv_register_nop (gen_fnop ());
9172 /* Estimate the length of each branch. Although this may change after
9173 we've inserted nops, it will only do so in big functions. */
9174 shorten_branches (get_insns ());
9176 frv_packet_address = 0;
9177 frv_for_each_packet (frv_reorg_packet);
9180 #define def_builtin(name, type, code) \
9181 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
9183 struct builtin_description
9185 enum insn_code icode;
9187 enum frv_builtins code;
9188 enum rtx_code comparison;
9192 /* Media intrinsics that take a single, constant argument. */
9194 static struct builtin_description bdesc_set[] =
9196 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
9199 /* Media intrinsics that take just one argument. */
9201 static struct builtin_description bdesc_1arg[] =
9203 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
9204 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
9205 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
9206 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
9207 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
9208 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
9211 /* Media intrinsics that take two arguments. */
9213 static struct builtin_description bdesc_2arg[] =
9215 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
9216 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
9217 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
9218 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
9219 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
9220 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
9221 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
9222 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
9223 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
9224 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
9225 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
9226 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
9227 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
9228 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
9229 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
9230 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
9231 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
9232 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
9233 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
9234 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
9235 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
9236 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
9237 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
9238 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
9239 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
9240 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
9241 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
9242 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
9245 /* Integer intrinsics that take two arguments and have no return value. */
9247 static struct builtin_description bdesc_int_void2arg[] =
9249 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
9250 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
9251 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
9254 static struct builtin_description bdesc_prefetches[] =
9256 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
9257 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
9260 /* Media intrinsics that take two arguments, the first being an ACC number. */
9262 static struct builtin_description bdesc_cut[] =
9264 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
9265 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
9266 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
9269 /* Two-argument media intrinsics with an immediate second argument. */
9271 static struct builtin_description bdesc_2argimm[] =
9273 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
9274 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
9275 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
9276 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
9277 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
9278 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
9279 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
9280 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
9281 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
9282 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
9283 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
9284 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
9285 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
9286 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
9287 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
9288 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
9289 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
9292 /* Media intrinsics that take two arguments and return void, the first argument
9293 being a pointer to 4 words in memory. */
9295 static struct builtin_description bdesc_void2arg[] =
9297 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
9298 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
9301 /* Media intrinsics that take three arguments, the first being a const_int that
9302 denotes an accumulator, and that return void. */
9304 static struct builtin_description bdesc_void3arg[] =
9306 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
9307 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
9308 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
9309 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
9310 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
9311 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
9312 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
9313 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
9314 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
9315 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
9316 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9317 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9318 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9319 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9320 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9321 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9322 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9323 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9324 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9325 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9326 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9327 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9328 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9329 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9330 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9333 /* Media intrinsics that take two accumulator numbers as argument and
9336 static struct builtin_description bdesc_voidacc[] =
9338 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9339 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9340 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9341 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9342 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9343 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9346 /* Initialize media builtins. */
9349 frv_init_builtins (void)
9351 tree endlink = void_list_node;
9352 tree accumulator = integer_type_node;
9353 tree integer = integer_type_node;
9354 tree voidt = void_type_node;
9355 tree uhalf = short_unsigned_type_node;
9356 tree sword1 = long_integer_type_node;
9357 tree uword1 = long_unsigned_type_node;
9358 tree sword2 = long_long_integer_type_node;
9359 tree uword2 = long_long_unsigned_type_node;
9360 tree uword4 = build_pointer_type (uword1);
9361 tree iacc = integer_type_node;
9363 #define UNARY(RET, T1) \
9364 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9366 #define BINARY(RET, T1, T2) \
9367 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9368 tree_cons (NULL_TREE, T2, endlink)))
9370 #define TRINARY(RET, T1, T2, T3) \
9371 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9372 tree_cons (NULL_TREE, T2, \
9373 tree_cons (NULL_TREE, T3, endlink))))
9375 tree void_ftype_void = build_function_type (voidt, endlink);
9377 tree void_ftype_acc = UNARY (voidt, accumulator);
9378 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9379 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9380 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9381 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9382 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9383 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9384 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9385 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9387 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9388 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9389 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9390 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9391 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9392 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9393 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9394 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9395 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9396 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9397 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9399 tree sw1_ftype_int = UNARY (sword1, integer);
9400 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9401 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9403 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9404 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9405 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9406 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9407 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9409 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9410 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
9411 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
9412 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
9413 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
9414 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
9415 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
9416 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
9417 tree sw2_ftype_iacc = UNARY (sword2, iacc);
9418 tree sw1_ftype_iacc = UNARY (sword1, iacc);
9419 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
9421 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9422 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9423 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9424 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9425 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9426 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9427 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9428 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9429 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9430 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9431 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9432 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9433 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9434 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9435 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9436 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9437 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9438 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9439 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9440 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9441 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9442 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9443 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9444 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9445 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9446 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9447 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9448 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9449 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9450 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9451 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9452 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9453 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9454 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9455 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9456 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9457 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9458 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9459 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9460 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9461 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9462 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9463 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9464 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9465 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9466 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9467 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9468 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9469 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9470 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9471 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9472 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9473 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9474 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9475 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9476 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9477 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9478 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9479 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9480 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9481 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9482 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9483 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9484 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9485 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9486 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9487 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9488 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9489 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9490 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9491 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9492 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9493 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9494 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9495 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9496 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9497 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9498 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9499 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9500 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9501 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9502 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9503 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9504 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9505 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
9506 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
9507 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
9508 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
9509 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
9510 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
9511 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
9512 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
9513 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
9514 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
9515 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
9516 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
9517 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
9518 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
9519 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
9520 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
9521 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
9522 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
9523 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
9524 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
9531 /* Set the names for various arithmetic operations according to the
9534 frv_init_libfuncs (void)
9536 set_optab_libfunc (smod_optab, SImode, "__modi");
9537 set_optab_libfunc (umod_optab, SImode, "__umodi");
9539 set_optab_libfunc (add_optab, DImode, "__addll");
9540 set_optab_libfunc (sub_optab, DImode, "__subll");
9541 set_optab_libfunc (smul_optab, DImode, "__mulll");
9542 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9543 set_optab_libfunc (smod_optab, DImode, "__modll");
9544 set_optab_libfunc (umod_optab, DImode, "__umodll");
9545 set_optab_libfunc (and_optab, DImode, "__andll");
9546 set_optab_libfunc (ior_optab, DImode, "__orll");
9547 set_optab_libfunc (xor_optab, DImode, "__xorll");
9548 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9550 set_optab_libfunc (add_optab, SFmode, "__addf");
9551 set_optab_libfunc (sub_optab, SFmode, "__subf");
9552 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9553 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9555 set_optab_libfunc (add_optab, DFmode, "__addd");
9556 set_optab_libfunc (sub_optab, DFmode, "__subd");
9557 set_optab_libfunc (smul_optab, DFmode, "__muld");
9558 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9560 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9561 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9563 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9564 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9565 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9566 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9568 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9569 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9570 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9571 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9573 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9574 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9575 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9576 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9579 /* Convert an integer constant to an accumulator register. ICODE is the
9580 code of the target instruction, OPNUM is the number of the
9581 accumulator operand and OPVAL is the constant integer. Try both
9582 ACC and ACCG registers; only report an error if neither fit the
9586 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9591 /* ACCs and ACCGs are implicity global registers if media intrinsics
9592 are being used. We set up this lazily to avoid creating lots of
9593 unnecessary call_insn rtl in non-media code. */
9594 for (i = 0; i <= ACC_MASK; i++)
9595 if ((i & ACC_MASK) == i)
9596 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
9598 if (GET_CODE (opval) != CONST_INT)
9600 error ("accumulator is not a constant integer");
9603 if ((INTVAL (opval) & ~ACC_MASK) != 0)
9605 error ("accumulator number is out of bounds");
9609 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9610 ACC_FIRST + INTVAL (opval));
9611 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9612 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9614 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9616 error ("inappropriate accumulator for %qs", insn_data[icode].name);
9622 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9625 static enum machine_mode
9626 frv_matching_accg_mode (enum machine_mode mode)
9644 /* Return the accumulator guard that should be paired with accumulator
9645 register ACC. The mode of the returned register is in the same
9646 class as ACC, but is four times smaller. */
9649 frv_matching_accg_for_acc (rtx acc)
9651 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9652 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9655 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9656 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9660 frv_read_argument (tree *arglistptr)
9662 tree next = TREE_VALUE (*arglistptr);
9663 *arglistptr = TREE_CHAIN (*arglistptr);
9664 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9667 /* Like frv_read_argument, but interpret the argument as the number
9668 of an IACC register and return a (reg:MODE ...) rtx for it. */
9671 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
9676 op = frv_read_argument (arglistptr);
9677 if (GET_CODE (op) != CONST_INT
9679 || INTVAL (op) > IACC_LAST - IACC_FIRST
9680 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
9682 error ("invalid IACC argument");
9686 /* IACCs are implicity global registers. We set up this lazily to
9687 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
9689 regno = INTVAL (op) + IACC_FIRST;
9690 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
9691 global_regs[regno + i] = 1;
9693 return gen_rtx_REG (mode, regno);
9696 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9697 The instruction should require a constant operand of some sort. The
9698 function prints an error if OPVAL is not valid. */
9701 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9703 if (GET_CODE (opval) != CONST_INT)
9705 error ("%qs expects a constant argument", insn_data[icode].name);
9708 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9710 error ("constant argument out of range for %qs", insn_data[icode].name);
9716 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9717 if it's not null, has the right mode, and satisfies operand 0's
9721 frv_legitimize_target (enum insn_code icode, rtx target)
9723 enum machine_mode mode = insn_data[icode].operand[0].mode;
9726 || GET_MODE (target) != mode
9727 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9728 return gen_reg_rtx (mode);
9733 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9734 check whether ARG satisfies the operand's constraints. If it doesn't,
9735 copy ARG to a temporary register and return that. Otherwise return ARG
9739 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9741 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9743 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9746 return copy_to_mode_reg (mode, arg);
9749 /* Expand builtins that take a single, constant argument. At the moment,
9750 only MHDSETS falls into this category. */
9753 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9756 rtx op0 = frv_read_argument (&arglist);
9758 if (! frv_check_constant_argument (icode, 1, op0))
9761 target = frv_legitimize_target (icode, target);
9762 pat = GEN_FCN (icode) (target, op0);
9770 /* Expand builtins that take one operand. */
9773 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9776 rtx op0 = frv_read_argument (&arglist);
9778 target = frv_legitimize_target (icode, target);
9779 op0 = frv_legitimize_argument (icode, 1, op0);
9780 pat = GEN_FCN (icode) (target, op0);
9788 /* Expand builtins that take two operands. */
9791 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9794 rtx op0 = frv_read_argument (&arglist);
9795 rtx op1 = frv_read_argument (&arglist);
9797 target = frv_legitimize_target (icode, target);
9798 op0 = frv_legitimize_argument (icode, 1, op0);
9799 op1 = frv_legitimize_argument (icode, 2, op1);
9800 pat = GEN_FCN (icode) (target, op0, op1);
9808 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9812 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9815 rtx op0 = frv_read_argument (&arglist);
9816 rtx op1 = frv_read_argument (&arglist);
9819 target = frv_legitimize_target (icode, target);
9820 op0 = frv_int_to_acc (icode, 1, op0);
9824 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9826 if (! frv_check_constant_argument (icode, 2, op1))
9830 op1 = frv_legitimize_argument (icode, 2, op1);
9832 op2 = frv_matching_accg_for_acc (op0);
9833 pat = GEN_FCN (icode) (target, op0, op1, op2);
9841 /* Expand builtins that take two operands and the second is immediate. */
9844 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9847 rtx op0 = frv_read_argument (&arglist);
9848 rtx op1 = frv_read_argument (&arglist);
9850 if (! frv_check_constant_argument (icode, 2, op1))
9853 target = frv_legitimize_target (icode, target);
9854 op0 = frv_legitimize_argument (icode, 1, op0);
9855 pat = GEN_FCN (icode) (target, op0, op1);
9863 /* Expand builtins that take two operands, the first operand being a pointer to
9864 ints and return void. */
9867 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9870 rtx op0 = frv_read_argument (&arglist);
9871 rtx op1 = frv_read_argument (&arglist);
9872 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9875 if (GET_CODE (op0) != MEM)
9879 if (! offsettable_address_p (0, mode0, op0))
9881 reg = gen_reg_rtx (Pmode);
9882 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9885 op0 = gen_rtx_MEM (SImode, reg);
9888 addr = XEXP (op0, 0);
9889 if (! offsettable_address_p (0, mode0, addr))
9890 addr = copy_to_mode_reg (Pmode, op0);
9892 op0 = change_address (op0, V4SImode, addr);
9893 op1 = frv_legitimize_argument (icode, 1, op1);
9894 pat = GEN_FCN (icode) (op0, op1);
9902 /* Expand builtins that take two long operands and return void. */
9905 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
9908 rtx op0 = frv_read_argument (&arglist);
9909 rtx op1 = frv_read_argument (&arglist);
9911 op0 = frv_legitimize_argument (icode, 1, op0);
9912 op1 = frv_legitimize_argument (icode, 1, op1);
9913 pat = GEN_FCN (icode) (op0, op1);
9921 /* Expand prefetch builtins. These take a single address as argument. */
9924 frv_expand_prefetches (enum insn_code icode, tree arglist)
9927 rtx op0 = frv_read_argument (&arglist);
9929 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9937 /* Expand builtins that take three operands and return void. The first
9938 argument must be a constant that describes a pair or quad accumulators. A
9939 fourth argument is created that is the accumulator guard register that
9940 corresponds to the accumulator. */
9943 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9946 rtx op0 = frv_read_argument (&arglist);
9947 rtx op1 = frv_read_argument (&arglist);
9948 rtx op2 = frv_read_argument (&arglist);
9951 op0 = frv_int_to_acc (icode, 0, op0);
9955 op1 = frv_legitimize_argument (icode, 1, op1);
9956 op2 = frv_legitimize_argument (icode, 2, op2);
9957 op3 = frv_matching_accg_for_acc (op0);
9958 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9966 /* Expand builtins that perform accumulator-to-accumulator operations.
9967 These builtins take two accumulator numbers as argument and return
9971 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9974 rtx op0 = frv_read_argument (&arglist);
9975 rtx op1 = frv_read_argument (&arglist);
9979 op0 = frv_int_to_acc (icode, 0, op0);
9983 op1 = frv_int_to_acc (icode, 1, op1);
9987 op2 = frv_matching_accg_for_acc (op0);
9988 op3 = frv_matching_accg_for_acc (op1);
9989 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9997 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9998 number as argument. */
10001 frv_expand_mclracc_builtin (tree arglist)
10003 enum insn_code icode = CODE_FOR_mclracc;
10005 rtx op0 = frv_read_argument (&arglist);
10007 op0 = frv_int_to_acc (icode, 0, op0);
10011 pat = GEN_FCN (icode) (op0);
10018 /* Expand builtins that take no arguments. */
10021 frv_expand_noargs_builtin (enum insn_code icode)
10023 rtx pat = GEN_FCN (icode) (const0_rtx);
10030 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
10031 number or accumulator guard number as argument and return an SI integer. */
10034 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
10037 rtx target = gen_reg_rtx (SImode);
10038 rtx op0 = frv_read_argument (&arglist);
10040 op0 = frv_int_to_acc (icode, 1, op0);
10044 pat = GEN_FCN (icode) (target, op0);
10052 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
10053 accumulator guard as their first argument and an SImode value as their
10057 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
10060 rtx op0 = frv_read_argument (&arglist);
10061 rtx op1 = frv_read_argument (&arglist);
10063 op0 = frv_int_to_acc (icode, 0, op0);
10067 op1 = frv_legitimize_argument (icode, 1, op1);
10068 pat = GEN_FCN (icode) (op0, op1);
10075 /* Emit a move from SRC to DEST in SImode chunks. This can be used
10076 to move DImode values into and out of IACC0. */
10079 frv_split_iacc_move (rtx dest, rtx src)
10081 enum machine_mode inner;
10084 inner = GET_MODE (dest);
10085 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
10086 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
10087 simplify_gen_subreg (SImode, src, inner, i));
10090 /* Expand builtins. */
10093 frv_expand_builtin (tree exp,
10095 rtx subtarget ATTRIBUTE_UNUSED,
10096 enum machine_mode mode ATTRIBUTE_UNUSED,
10097 int ignore ATTRIBUTE_UNUSED)
10099 tree arglist = TREE_OPERAND (exp, 1);
10100 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10101 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
10103 struct builtin_description *d;
10105 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
10107 error ("media functions are not available unless -mmedia is used");
10113 case FRV_BUILTIN_MCOP1:
10114 case FRV_BUILTIN_MCOP2:
10115 case FRV_BUILTIN_MDUNPACKH:
10116 case FRV_BUILTIN_MBTOHE:
10117 if (! TARGET_MEDIA_REV1)
10119 error ("this media function is only available on the fr500");
10124 case FRV_BUILTIN_MQXMACHS:
10125 case FRV_BUILTIN_MQXMACXHS:
10126 case FRV_BUILTIN_MQMACXHS:
10127 case FRV_BUILTIN_MADDACCS:
10128 case FRV_BUILTIN_MSUBACCS:
10129 case FRV_BUILTIN_MASACCS:
10130 case FRV_BUILTIN_MDADDACCS:
10131 case FRV_BUILTIN_MDSUBACCS:
10132 case FRV_BUILTIN_MDASACCS:
10133 case FRV_BUILTIN_MABSHS:
10134 case FRV_BUILTIN_MDROTLI:
10135 case FRV_BUILTIN_MCPLHI:
10136 case FRV_BUILTIN_MCPLI:
10137 case FRV_BUILTIN_MDCUTSSI:
10138 case FRV_BUILTIN_MQSATHS:
10139 case FRV_BUILTIN_MHSETLOS:
10140 case FRV_BUILTIN_MHSETLOH:
10141 case FRV_BUILTIN_MHSETHIS:
10142 case FRV_BUILTIN_MHSETHIH:
10143 case FRV_BUILTIN_MHDSETS:
10144 case FRV_BUILTIN_MHDSETH:
10145 if (! TARGET_MEDIA_REV2)
10147 error ("this media function is only available on the fr400"
10153 case FRV_BUILTIN_SMASS:
10154 case FRV_BUILTIN_SMSSS:
10155 case FRV_BUILTIN_SMU:
10156 case FRV_BUILTIN_ADDSS:
10157 case FRV_BUILTIN_SUBSS:
10158 case FRV_BUILTIN_SLASS:
10159 case FRV_BUILTIN_SCUTSS:
10160 case FRV_BUILTIN_IACCreadll:
10161 case FRV_BUILTIN_IACCreadl:
10162 case FRV_BUILTIN_IACCsetll:
10163 case FRV_BUILTIN_IACCsetl:
10164 if (!TARGET_FR405_BUILTINS)
10166 error ("this builtin function is only available"
10167 " on the fr405 and fr450");
10172 case FRV_BUILTIN_PREFETCH:
10173 if (!TARGET_FR500_FR550_BUILTINS)
10175 error ("this builtin function is only available on the fr500"
10181 case FRV_BUILTIN_MQLCLRHS:
10182 case FRV_BUILTIN_MQLMTHS:
10183 case FRV_BUILTIN_MQSLLHI:
10184 case FRV_BUILTIN_MQSRAHI:
10185 if (!TARGET_MEDIA_FR450)
10187 error ("this builtin function is only available on the fr450");
10196 /* Expand unique builtins. */
10200 case FRV_BUILTIN_MTRAP:
10201 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
10203 case FRV_BUILTIN_MCLRACC:
10204 return frv_expand_mclracc_builtin (arglist);
10206 case FRV_BUILTIN_MCLRACCA:
10208 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
10210 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
10212 case FRV_BUILTIN_MRDACC:
10213 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
10215 case FRV_BUILTIN_MRDACCG:
10216 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
10218 case FRV_BUILTIN_MWTACC:
10219 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
10221 case FRV_BUILTIN_MWTACCG:
10222 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
10224 case FRV_BUILTIN_IACCreadll:
10226 rtx src = frv_read_iacc_argument (DImode, &arglist);
10227 if (target == 0 || !REG_P (target))
10228 target = gen_reg_rtx (DImode);
10229 frv_split_iacc_move (target, src);
10233 case FRV_BUILTIN_IACCreadl:
10234 return frv_read_iacc_argument (SImode, &arglist);
10236 case FRV_BUILTIN_IACCsetll:
10238 rtx dest = frv_read_iacc_argument (DImode, &arglist);
10239 rtx src = frv_read_argument (&arglist);
10240 frv_split_iacc_move (dest, force_reg (DImode, src));
10244 case FRV_BUILTIN_IACCsetl:
10246 rtx dest = frv_read_iacc_argument (SImode, &arglist);
10247 rtx src = frv_read_argument (&arglist);
10248 emit_move_insn (dest, force_reg (SImode, src));
10256 /* Expand groups of builtins. */
10258 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
10259 if (d->code == fcode)
10260 return frv_expand_set_builtin (d->icode, arglist, target);
10262 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10263 if (d->code == fcode)
10264 return frv_expand_unop_builtin (d->icode, arglist, target);
10266 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10267 if (d->code == fcode)
10268 return frv_expand_binop_builtin (d->icode, arglist, target);
10270 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
10271 if (d->code == fcode)
10272 return frv_expand_cut_builtin (d->icode, arglist, target);
10274 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
10275 if (d->code == fcode)
10276 return frv_expand_binopimm_builtin (d->icode, arglist, target);
10278 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
10279 if (d->code == fcode)
10280 return frv_expand_voidbinop_builtin (d->icode, arglist);
10282 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
10283 if (d->code == fcode)
10284 return frv_expand_voidtriop_builtin (d->icode, arglist);
10286 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
10287 if (d->code == fcode)
10288 return frv_expand_voidaccop_builtin (d->icode, arglist);
10290 for (i = 0, d = bdesc_int_void2arg;
10291 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
10292 if (d->code == fcode)
10293 return frv_expand_int_void2arg (d->icode, arglist);
10295 for (i = 0, d = bdesc_prefetches;
10296 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
10297 if (d->code == fcode)
10298 return frv_expand_prefetches (d->icode, arglist);
10304 frv_in_small_data_p (tree decl)
10306 HOST_WIDE_INT size;
10309 /* Don't apply the -G flag to internal compiler structures. We
10310 should leave such structures in the main data section, partly
10311 for efficiency and partly because the size of some of them
10312 (such as C++ typeinfos) is not known until later. */
10313 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
10316 /* If we already know which section the decl should be in, see if
10317 it's a small data section. */
10318 section_name = DECL_SECTION_NAME (decl);
10321 if (TREE_CODE (section_name) != STRING_CST)
10323 if (frv_string_begins_with (section_name, ".sdata"))
10325 if (frv_string_begins_with (section_name, ".sbss"))
10330 size = int_size_in_bytes (TREE_TYPE (decl));
10331 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
10338 frv_rtx_costs (rtx x,
10339 int code ATTRIBUTE_UNUSED,
10340 int outer_code ATTRIBUTE_UNUSED,
10343 if (outer_code == MEM)
10345 /* Don't differentiate between memory addresses. All the ones
10346 we accept have equal cost. */
10347 *total = COSTS_N_INSNS (0);
10354 /* Make 12 bit integers really cheap. */
10355 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
10360 /* Fall through. */
10366 *total = COSTS_N_INSNS (2);
10380 if (GET_MODE (x) == SImode)
10381 *total = COSTS_N_INSNS (1);
10382 else if (GET_MODE (x) == DImode)
10383 *total = COSTS_N_INSNS (2);
10385 *total = COSTS_N_INSNS (3);
10389 if (GET_MODE (x) == SImode)
10390 *total = COSTS_N_INSNS (2);
10392 *total = COSTS_N_INSNS (6); /* guess */
10399 *total = COSTS_N_INSNS (18);
10403 *total = COSTS_N_INSNS (3);
10412 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10415 assemble_align (POINTER_SIZE);
10418 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10422 assemble_integer_with_op ("\t.picptr\t", symbol);
10426 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10429 assemble_align (POINTER_SIZE);
10432 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10436 assemble_integer_with_op ("\t.picptr\t", symbol);
10439 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10442 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
10443 int incoming ATTRIBUTE_UNUSED)
10445 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
10448 #include "gt-frv.h"