1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static void frv_option_override (void);
268 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
269 static int frv_default_flags_for_cpu (void);
270 static int frv_string_begins_with (const_tree, const char *);
271 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
272 static void frv_print_operand (FILE *, rtx, int);
273 static void frv_print_operand_address (FILE *, rtx);
274 static bool frv_print_operand_punct_valid_p (unsigned char code);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static rtx frv_function_value (const_tree, const_tree,
282 static rtx frv_libcall_value (enum machine_mode,
284 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
285 static rtx single_set_pattern (rtx);
286 static int frv_function_contains_far_jump (void);
287 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
291 static rtx frv_frame_offset_rtx (int);
292 static rtx frv_frame_mem (enum machine_mode, rtx, int);
293 static rtx frv_dwarf_store (rtx, int);
294 static void frv_frame_insn (rtx, rtx);
295 static void frv_frame_access (frv_frame_accessor_t*,
297 static void frv_frame_access_multi (frv_frame_accessor_t*,
299 static void frv_frame_access_standard_regs (enum frv_stack_op,
301 static struct machine_function *frv_init_machine_status (void);
302 static rtx frv_int_to_acc (enum insn_code, int, rtx);
303 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
304 static rtx frv_read_argument (tree, unsigned int);
305 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
306 static int frv_check_constant_argument (enum insn_code, int, rtx);
307 static rtx frv_legitimize_target (enum insn_code, rtx);
308 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
309 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
310 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
311 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
316 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
317 static rtx frv_expand_int_void2arg (enum insn_code, tree);
318 static rtx frv_expand_prefetches (enum insn_code, tree);
319 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
320 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
321 static rtx frv_expand_mclracc_builtin (tree);
322 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
324 static rtx frv_expand_noargs_builtin (enum insn_code);
325 static void frv_split_iacc_move (rtx, rtx);
326 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
327 static int frv_clear_registers_used (rtx *, void *);
328 static void frv_ifcvt_add_insn (rtx, rtx, int);
329 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
330 static rtx frv_ifcvt_load_value (rtx, rtx);
331 static int frv_acc_group_1 (rtx *, void *);
332 static unsigned int frv_insn_unit (rtx);
333 static bool frv_issues_to_branch_unit_p (rtx);
334 static int frv_cond_flags (rtx);
335 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
336 static int frv_registers_conflict_p_1 (rtx *, void *);
337 static bool frv_registers_conflict_p (rtx);
338 static void frv_registers_update_1 (rtx, const_rtx, void *);
339 static void frv_registers_update (rtx);
340 static void frv_start_packet (void);
341 static void frv_start_packet_block (void);
342 static void frv_finish_packet (void (*) (void));
343 static bool frv_pack_insn_p (rtx);
344 static void frv_add_insn_to_packet (rtx);
345 static void frv_insert_nop_in_packet (rtx);
346 static bool frv_for_each_packet (void (*) (void));
347 static bool frv_sort_insn_group_1 (enum frv_insn_group,
348 unsigned int, unsigned int,
349 unsigned int, unsigned int,
351 static int frv_compare_insns (const void *, const void *);
352 static void frv_sort_insn_group (enum frv_insn_group);
353 static void frv_reorder_packet (void);
354 static void frv_fill_unused_units (enum frv_insn_group);
355 static void frv_align_label (void);
356 static void frv_reorg_packet (void);
357 static void frv_register_nop (rtx);
358 static void frv_reorg (void);
359 static void frv_pack_insns (void);
360 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
361 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
362 static bool frv_assemble_integer (rtx, unsigned, int);
363 static void frv_init_builtins (void);
364 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
365 static void frv_init_libfuncs (void);
366 static bool frv_in_small_data_p (const_tree);
367 static void frv_asm_output_mi_thunk
368 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
369 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
372 static rtx frv_expand_builtin_saveregs (void);
373 static void frv_expand_builtin_va_start (tree, rtx);
374 static bool frv_rtx_costs (rtx, int, int, int*, bool);
375 static int frv_register_move_cost (enum machine_mode,
376 reg_class_t, reg_class_t);
377 static int frv_memory_move_cost (enum machine_mode,
379 static void frv_asm_out_constructor (rtx, int);
380 static void frv_asm_out_destructor (rtx, int);
381 static bool frv_function_symbol_referenced_p (rtx);
382 static bool frv_cannot_force_const_mem (rtx);
383 static const char *unspec_got_name (int);
384 static void frv_output_const_unspec (FILE *,
385 const struct frv_unspec *);
386 static bool frv_function_ok_for_sibcall (tree, tree);
387 static rtx frv_struct_value_rtx (tree, int);
388 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
389 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
391 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
393 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
395 secondary_reload_info *);
396 static bool frv_frame_pointer_required (void);
397 static bool frv_can_eliminate (const int, const int);
398 static void frv_trampoline_init (rtx, tree, rtx);
399 static bool frv_class_likely_spilled_p (reg_class_t);
401 /* Allow us to easily change the default for -malloc-cc. */
402 #ifndef DEFAULT_NO_ALLOC_CC
403 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
405 #define MASK_DEFAULT_ALLOC_CC 0
408 /* Initialize the GCC target structure. */
409 #undef TARGET_PRINT_OPERAND
410 #define TARGET_PRINT_OPERAND frv_print_operand
411 #undef TARGET_PRINT_OPERAND_ADDRESS
412 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
413 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
414 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
415 #undef TARGET_ASM_FUNCTION_PROLOGUE
416 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
417 #undef TARGET_ASM_FUNCTION_EPILOGUE
418 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
419 #undef TARGET_ASM_INTEGER
420 #define TARGET_ASM_INTEGER frv_assemble_integer
421 #undef TARGET_DEFAULT_TARGET_FLAGS
422 #define TARGET_DEFAULT_TARGET_FLAGS \
423 (MASK_DEFAULT_ALLOC_CC \
430 #undef TARGET_HANDLE_OPTION
431 #define TARGET_HANDLE_OPTION frv_handle_option
432 #undef TARGET_OPTION_OVERRIDE
433 #define TARGET_OPTION_OVERRIDE frv_option_override
434 #undef TARGET_INIT_BUILTINS
435 #define TARGET_INIT_BUILTINS frv_init_builtins
436 #undef TARGET_EXPAND_BUILTIN
437 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
438 #undef TARGET_INIT_LIBFUNCS
439 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
440 #undef TARGET_IN_SMALL_DATA_P
441 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
442 #undef TARGET_REGISTER_MOVE_COST
443 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
444 #undef TARGET_MEMORY_MOVE_COST
445 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
446 #undef TARGET_RTX_COSTS
447 #define TARGET_RTX_COSTS frv_rtx_costs
448 #undef TARGET_ASM_CONSTRUCTOR
449 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
450 #undef TARGET_ASM_DESTRUCTOR
451 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
453 #undef TARGET_ASM_OUTPUT_MI_THUNK
454 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
455 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
456 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
458 #undef TARGET_SCHED_ISSUE_RATE
459 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
461 #undef TARGET_LEGITIMIZE_ADDRESS
462 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
464 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
465 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
466 #undef TARGET_CANNOT_FORCE_CONST_MEM
467 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
469 #undef TARGET_HAVE_TLS
470 #define TARGET_HAVE_TLS HAVE_AS_TLS
472 #undef TARGET_STRUCT_VALUE_RTX
473 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
474 #undef TARGET_MUST_PASS_IN_STACK
475 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
476 #undef TARGET_PASS_BY_REFERENCE
477 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
478 #undef TARGET_ARG_PARTIAL_BYTES
479 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
481 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
482 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
483 #undef TARGET_SETUP_INCOMING_VARARGS
484 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
485 #undef TARGET_MACHINE_DEPENDENT_REORG
486 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
488 #undef TARGET_EXPAND_BUILTIN_VA_START
489 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
492 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
493 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
496 #undef TARGET_CLASS_LIKELY_SPILLED_P
497 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
499 #undef TARGET_SECONDARY_RELOAD
500 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
502 #undef TARGET_LEGITIMATE_ADDRESS_P
503 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
505 #undef TARGET_FRAME_POINTER_REQUIRED
506 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
508 #undef TARGET_CAN_ELIMINATE
509 #define TARGET_CAN_ELIMINATE frv_can_eliminate
511 #undef TARGET_TRAMPOLINE_INIT
512 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
514 #undef TARGET_FUNCTION_VALUE
515 #define TARGET_FUNCTION_VALUE frv_function_value
516 #undef TARGET_LIBCALL_VALUE
517 #define TARGET_LIBCALL_VALUE frv_libcall_value
519 struct gcc_target targetm = TARGET_INITIALIZER;
521 #define FRV_SYMBOL_REF_TLS_P(RTX) \
522 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
525 /* Any function call that satisfies the machine-independent
526 requirements is eligible on FR-V. */
529 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
530 tree exp ATTRIBUTE_UNUSED)
535 /* Return true if SYMBOL is a small data symbol and relocation RELOC
536 can be used to access it directly in a load or store. */
538 static FRV_INLINE bool
539 frv_small_data_reloc_p (rtx symbol, int reloc)
541 return (GET_CODE (symbol) == SYMBOL_REF
542 && SYMBOL_REF_SMALL_P (symbol)
543 && (!TARGET_FDPIC || flag_pic == 1)
544 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
547 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
551 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
553 if (GET_CODE (x) == CONST)
557 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
559 unspec->offset += INTVAL (XEXP (x, 1));
562 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
564 unspec->symbol = XVECEXP (x, 0, 0);
565 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
567 if (unspec->offset == 0)
570 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
571 && unspec->offset > 0
572 && unspec->offset < g_switch_value)
579 /* Decide whether we can force certain constants to memory. If we
580 decide we can't, the caller should be able to cope with it in
583 We never allow constants to be forced into memory for TARGET_FDPIC.
584 This is necessary for several reasons:
586 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
587 target-independent code will try to force them into the constant
588 pool, thus leading to infinite recursion.
590 2. We can never introduce new constant pool references during reload.
591 Any such reference would require use of the pseudo FDPIC register.
593 3. We can't represent a constant added to a function pointer (which is
594 not the same as a pointer to a function+constant).
596 4. In many cases, it's more efficient to calculate the constant in-line. */
599 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
604 /* Implement TARGET_HANDLE_OPTION. */
607 frv_handle_option (size_t code, const char *arg, int value)
612 if (strcmp (arg, "simple") == 0)
613 frv_cpu_type = FRV_CPU_SIMPLE;
614 else if (strcmp (arg, "tomcat") == 0)
615 frv_cpu_type = FRV_CPU_TOMCAT;
616 else if (strcmp (arg, "fr550") == 0)
617 frv_cpu_type = FRV_CPU_FR550;
618 else if (strcmp (arg, "fr500") == 0)
619 frv_cpu_type = FRV_CPU_FR500;
620 else if (strcmp (arg, "fr450") == 0)
621 frv_cpu_type = FRV_CPU_FR450;
622 else if (strcmp (arg, "fr405") == 0)
623 frv_cpu_type = FRV_CPU_FR405;
624 else if (strcmp (arg, "fr400") == 0)
625 frv_cpu_type = FRV_CPU_FR400;
626 else if (strcmp (arg, "fr300") == 0)
627 frv_cpu_type = FRV_CPU_FR300;
628 else if (strcmp (arg, "frv") == 0)
629 frv_cpu_type = FRV_CPU_GENERIC;
640 frv_default_flags_for_cpu (void)
642 switch (frv_cpu_type)
644 case FRV_CPU_GENERIC:
645 return MASK_DEFAULT_FRV;
648 return MASK_DEFAULT_FR550;
652 return MASK_DEFAULT_FR500;
655 return MASK_DEFAULT_FR450;
659 return MASK_DEFAULT_FR400;
663 return MASK_DEFAULT_SIMPLE;
670 /* Implement TARGET_OPTION_OVERRIDE. */
673 frv_option_override (void)
678 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
680 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
681 linker about linking pic and non-pic code. */
684 if (!flag_pic) /* -fPIC */
687 if (!global_options_set.x_g_switch_value) /* -G0 */
693 /* A C expression whose value is a register class containing hard
694 register REGNO. In general there is more than one such class;
695 choose a class which is "minimal", meaning that no smaller class
696 also contains the register. */
698 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
700 enum reg_class rclass;
704 int gpr_reg = regno - GPR_FIRST;
706 if (gpr_reg == GR8_REG)
709 else if (gpr_reg == GR9_REG)
712 else if (gpr_reg == GR14_REG)
713 rclass = FDPIC_FPTR_REGS;
715 else if (gpr_reg == FDPIC_REGNO)
718 else if ((gpr_reg & 3) == 0)
721 else if ((gpr_reg & 1) == 0)
728 else if (FPR_P (regno))
730 int fpr_reg = regno - GPR_FIRST;
731 if ((fpr_reg & 3) == 0)
732 rclass = QUAD_FPR_REGS;
734 else if ((fpr_reg & 1) == 0)
741 else if (regno == LR_REGNO)
744 else if (regno == LCR_REGNO)
747 else if (ICC_P (regno))
750 else if (FCC_P (regno))
753 else if (ICR_P (regno))
756 else if (FCR_P (regno))
759 else if (ACC_P (regno))
761 int r = regno - ACC_FIRST;
763 rclass = QUAD_ACC_REGS;
764 else if ((r & 1) == 0)
765 rclass = EVEN_ACC_REGS;
770 else if (ACCG_P (regno))
776 regno_reg_class[regno] = rclass;
779 /* Check for small data option */
780 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
781 g_switch_value = SDATA_DEFAULT_SIZE;
783 /* A C expression which defines the machine-dependent operand
784 constraint letters for register classes. If CHAR is such a
785 letter, the value should be the register class corresponding to
786 it. Otherwise, the value should be `NO_REGS'. The register
787 letter `r', corresponding to class `GENERAL_REGS', will not be
788 passed to this macro; you do not need to handle it.
790 The following letters are unavailable, due to being used as
795 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
796 'Q', 'R', 'S', 'T', 'U'
798 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
800 for (i = 0; i < 256; i++)
801 reg_class_from_letter[i] = NO_REGS;
803 reg_class_from_letter['a'] = ACC_REGS;
804 reg_class_from_letter['b'] = EVEN_ACC_REGS;
805 reg_class_from_letter['c'] = CC_REGS;
806 reg_class_from_letter['d'] = GPR_REGS;
807 reg_class_from_letter['e'] = EVEN_REGS;
808 reg_class_from_letter['f'] = FPR_REGS;
809 reg_class_from_letter['h'] = FEVEN_REGS;
810 reg_class_from_letter['l'] = LR_REG;
811 reg_class_from_letter['q'] = QUAD_REGS;
812 reg_class_from_letter['t'] = ICC_REGS;
813 reg_class_from_letter['u'] = FCC_REGS;
814 reg_class_from_letter['v'] = ICR_REGS;
815 reg_class_from_letter['w'] = FCR_REGS;
816 reg_class_from_letter['x'] = QUAD_FPR_REGS;
817 reg_class_from_letter['y'] = LCR_REG;
818 reg_class_from_letter['z'] = SPR_REGS;
819 reg_class_from_letter['A'] = QUAD_ACC_REGS;
820 reg_class_from_letter['B'] = ACCG_REGS;
821 reg_class_from_letter['C'] = CR_REGS;
822 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
823 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
825 /* There is no single unaligned SI op for PIC code. Sometimes we
826 need to use ".4byte" and sometimes we need to use ".picptr".
827 See frv_assemble_integer for details. */
828 if (flag_pic || TARGET_FDPIC)
829 targetm.asm_out.unaligned_op.si = 0;
831 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
832 target_flags |= MASK_LINKED_FP;
834 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
835 target_flags |= MASK_OPTIMIZE_MEMBAR;
837 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
838 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
840 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
841 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
843 init_machine_status = frv_init_machine_status;
847 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
850 frv_string_begins_with (const_tree name, const char *prefix)
852 const int prefix_len = strlen (prefix);
854 /* Remember: NAME's length includes the null terminator. */
855 return (TREE_STRING_LENGTH (name) > prefix_len
856 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
859 /* Zero or more C statements that may conditionally modify two variables
860 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
861 been initialized from the two preceding macros.
863 This is necessary in case the fixed or call-clobbered registers depend on
866 You need not define this macro if it has no work to do.
868 If the usage of an entire class of registers depends on the target flags,
869 you may indicate this to GCC by using this macro to modify `fixed_regs' and
870 `call_used_regs' to 1 for each of the registers in the classes which should
871 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
872 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
874 (However, if this class is not included in `GENERAL_REGS' and all of the
875 insn patterns whose constraints permit this class are controlled by target
876 switches, then GCC will automatically avoid using these registers when the
877 target switches are opposed to them.) */
880 frv_conditional_register_usage (void)
884 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
885 fixed_regs[i] = call_used_regs[i] = 1;
887 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
888 fixed_regs[i] = call_used_regs[i] = 1;
890 /* Reserve the registers used for conditional execution. At present, we need
891 1 ICC and 1 ICR register. */
892 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
893 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
897 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
898 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
899 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
900 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
904 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
905 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
908 /* If -fpic, SDA_BASE_REG is the PIC register. */
909 if (g_switch_value == 0 && !flag_pic)
910 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
913 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
919 * Compute the stack frame layout
922 * +---------------+-----------------------+-----------------------+
923 * |Register |type |caller-save/callee-save|
924 * +---------------+-----------------------+-----------------------+
925 * |GR0 |Zero register | - |
926 * |GR1 |Stack pointer(SP) | - |
927 * |GR2 |Frame pointer(FP) | - |
928 * |GR3 |Hidden parameter | caller save |
929 * |GR4-GR7 | - | caller save |
930 * |GR8-GR13 |Argument register | caller save |
931 * |GR14-GR15 | - | caller save |
932 * |GR16-GR31 | - | callee save |
933 * |GR32-GR47 | - | caller save |
934 * |GR48-GR63 | - | callee save |
935 * |FR0-FR15 | - | caller save |
936 * |FR16-FR31 | - | callee save |
937 * |FR32-FR47 | - | caller save |
938 * |FR48-FR63 | - | callee save |
939 * +---------------+-----------------------+-----------------------+
943 * SP-> |-----------------------------------|
945 * |-----------------------------------|
946 * | Register save area |
947 * |-----------------------------------|
948 * | Local variable save area |
949 * FP-> |-----------------------------------|
951 * |-----------------------------------|
952 * | Hidden parameter save area |
953 * |-----------------------------------|
954 * | Return address(LR) storage area |
955 * |-----------------------------------|
956 * | Padding for alignment |
957 * |-----------------------------------|
958 * | Register argument area |
959 * OLD SP-> |-----------------------------------|
961 * |-----------------------------------|
964 * Argument area/Parameter area:
966 * When a function is called, this area is used for argument transfer. When
967 * the argument is set up by the caller function, this area is referred to as
968 * the argument area. When the argument is referenced by the callee function,
969 * this area is referred to as the parameter area. The area is allocated when
970 * all arguments cannot be placed on the argument register at the time of
973 * Register save area:
975 * This is a register save area that must be guaranteed for the caller
976 * function. This area is not secured when the register save operation is not
979 * Local variable save area:
981 * This is the area for local variables and temporary variables.
985 * This area stores the FP value of the caller function.
987 * Hidden parameter save area:
989 * This area stores the start address of the return value storage
990 * area for a struct/union return function.
991 * When a struct/union is used as the return value, the caller
992 * function stores the return value storage area start address in
993 * register GR3 and passes it to the caller function.
994 * The callee function interprets the address stored in the GR3
995 * as the return value storage area start address.
996 * When register GR3 needs to be saved into memory, the callee
997 * function saves it in the hidden parameter save area. This
998 * area is not secured when the save operation is not needed.
1000 * Return address(LR) storage area:
1002 * This area saves the LR. The LR stores the address of a return to the caller
1003 * function for the purpose of function calling.
1005 * Argument register area:
1007 * This area saves the argument register. This area is not secured when the
1008 * save operation is not needed.
1012 * Arguments, the count of which equals the count of argument registers (6
1013 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1014 * function. When a struct/union return function is called, the return value
1015 * area address is stored in register GR3. Arguments not placed in the
1016 * argument registers will be stored in the stack argument area for transfer
1017 * purposes. When an 8-byte type argument is to be delivered using registers,
1018 * it is divided into two and placed in two registers for transfer. When
1019 * argument registers must be saved to memory, the callee function secures an
1020 * argument register save area in the stack. In this case, a continuous
1021 * argument register save area must be established in the parameter area. The
1022 * argument register save area must be allocated as needed to cover the size of
1023 * the argument register to be saved. If the function has a variable count of
1024 * arguments, it saves all argument registers in the argument register save
1027 * Argument Extension Format:
1029 * When an argument is to be stored in the stack, its type is converted to an
1030 * extended type in accordance with the individual argument type. The argument
1031 * is freed by the caller function after the return from the callee function is
1034 * +-----------------------+---------------+------------------------+
1035 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1036 * +-----------------------+---------------+------------------------+
1038 * |signed char |int | 4 |
1039 * |unsigned char |int | 4 |
1040 * |[signed] short int |int | 4 |
1041 * |unsigned short int |int | 4 |
1042 * |[signed] int |No extension | 4 |
1043 * |unsigned int |No extension | 4 |
1044 * |[signed] long int |No extension | 4 |
1045 * |unsigned long int |No extension | 4 |
1046 * |[signed] long long int |No extension | 8 |
1047 * |unsigned long long int |No extension | 8 |
1048 * |float |double | 8 |
1049 * |double |No extension | 8 |
1050 * |long double |No extension | 8 |
1051 * |pointer |No extension | 4 |
1052 * |struct/union |- | 4 (*1) |
1053 * +-----------------------+---------------+------------------------+
1055 * When a struct/union is to be delivered as an argument, the caller copies it
1056 * to the local variable area and delivers the address of that area.
1060 * +-------------------------------+----------------------+
1061 * |Return Value Type |Return Value Interface|
1062 * +-------------------------------+----------------------+
1064 * |[signed|unsigned] char |GR8 |
1065 * |[signed|unsigned] short int |GR8 |
1066 * |[signed|unsigned] int |GR8 |
1067 * |[signed|unsigned] long int |GR8 |
1069 * |[signed|unsigned] long long int|GR8 & GR9 |
1071 * |double |GR8 & GR9 |
1072 * |long double |GR8 & GR9 |
1073 * |struct/union |(*1) |
1074 * +-------------------------------+----------------------+
1076 * When a struct/union is used as the return value, the caller function stores
1077 * the start address of the return value storage area into GR3 and then passes
1078 * it to the callee function. The callee function interprets GR3 as the start
1079 * address of the return value storage area. When this address needs to be
1080 * saved in memory, the callee function secures the hidden parameter save area
1081 * and saves the address in that area.
1085 frv_stack_info (void)
1087 static frv_stack_t info, zero_info;
1088 frv_stack_t *info_ptr = &info;
1089 tree fndecl = current_function_decl;
1097 /* If we've already calculated the values and reload is complete,
1099 if (frv_stack_cache)
1100 return frv_stack_cache;
1102 /* Zero all fields. */
1105 /* Set up the register range information. */
1106 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1107 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1108 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1109 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1111 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1112 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1113 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1114 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1116 info_ptr->regs[STACK_REGS_LR].name = "lr";
1117 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1118 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1119 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1121 info_ptr->regs[STACK_REGS_CC].name = "cc";
1122 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1123 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1124 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1126 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1127 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1128 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1130 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1131 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1132 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1133 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1134 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1136 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1137 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1138 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1139 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1141 info_ptr->regs[STACK_REGS_FP].name = "fp";
1142 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1143 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1144 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1146 /* Determine if this is a stdarg function. If so, allocate space to store
1153 /* Find the last argument, and see if it is __builtin_va_alist. */
1154 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1156 next_arg = DECL_CHAIN (cur_arg);
1157 if (next_arg == (tree)0)
1159 if (DECL_NAME (cur_arg)
1160 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1168 /* Iterate over all of the register ranges. */
1169 for (range = 0; range < STACK_REGS_MAX; range++)
1171 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1172 int first = reg_ptr->first;
1173 int last = reg_ptr->last;
1175 int size_2words = 0;
1178 /* Calculate which registers need to be saved & save area size. */
1182 for (regno = first; regno <= last; regno++)
1184 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1185 || (crtl->calls_eh_return
1186 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1187 || (!TARGET_FDPIC && flag_pic
1188 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1190 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1191 size_1word += UNITS_PER_WORD;
1196 /* Calculate whether we need to create a frame after everything else
1197 has been processed. */
1202 if (df_regs_ever_live_p (LR_REGNO)
1204 /* This is set for __builtin_return_address, etc. */
1205 || cfun->machine->frame_needed
1206 || (TARGET_LINKED_FP && frame_pointer_needed)
1207 || (!TARGET_FDPIC && flag_pic
1208 && crtl->uses_pic_offset_table))
1210 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1211 size_1word += UNITS_PER_WORD;
1215 case STACK_REGS_STDARG:
1218 /* If this is a stdarg function with a non varardic
1219 argument split between registers and the stack,
1220 adjust the saved registers downward. */
1221 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1224 for (regno = first; regno <= last; regno++)
1226 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1227 size_1word += UNITS_PER_WORD;
1230 info_ptr->stdarg_size = size_1word;
1234 case STACK_REGS_STRUCT:
1235 if (cfun->returns_struct)
1237 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1238 size_1word += UNITS_PER_WORD;
1246 /* If this is a field, it only takes one word. */
1247 if (reg_ptr->field_p)
1248 size_1word = UNITS_PER_WORD;
1250 /* Determine which register pairs can be saved together. */
1251 else if (reg_ptr->dword_p && TARGET_DWORD)
1253 for (regno = first; regno < last; regno += 2)
1255 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1257 size_2words += 2 * UNITS_PER_WORD;
1258 size_1word -= 2 * UNITS_PER_WORD;
1259 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1260 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1265 reg_ptr->size_1word = size_1word;
1266 reg_ptr->size_2words = size_2words;
1268 if (! reg_ptr->special_p)
1270 info_ptr->regs_size_1word += size_1word;
1271 info_ptr->regs_size_2words += size_2words;
1276 /* Set up the sizes of each each field in the frame body, making the sizes
1277 of each be divisible by the size of a dword if dword operations might
1278 be used, or the size of a word otherwise. */
1279 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1281 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1282 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1283 + info_ptr->regs_size_1word,
1285 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1287 info_ptr->pretend_size = crtl->args.pretend_args_size;
1289 /* Work out the size of the frame, excluding the header. Both the frame
1290 body and register parameter area will be dword-aligned. */
1291 info_ptr->total_size
1292 = (ADDR_ALIGN (info_ptr->parameter_size
1293 + info_ptr->regs_size
1294 + info_ptr->vars_size,
1296 + ADDR_ALIGN (info_ptr->pretend_size
1297 + info_ptr->stdarg_size,
1298 2 * UNITS_PER_WORD));
1300 /* See if we need to create a frame at all, if so add header area. */
1301 if (info_ptr->total_size > 0
1302 || frame_pointer_needed
1303 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1304 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1306 offset = info_ptr->parameter_size;
1307 info_ptr->header_size = 4 * UNITS_PER_WORD;
1308 info_ptr->total_size += 4 * UNITS_PER_WORD;
1310 /* Calculate the offsets to save normal register pairs. */
1311 for (range = 0; range < STACK_REGS_MAX; range++)
1313 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1314 if (! reg_ptr->special_p)
1316 int first = reg_ptr->first;
1317 int last = reg_ptr->last;
1320 for (regno = first; regno <= last; regno++)
1321 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1322 && regno != FRAME_POINTER_REGNUM
1323 && (regno < FIRST_ARG_REGNUM
1324 || regno > LAST_ARG_REGNUM))
1326 info_ptr->reg_offset[regno] = offset;
1327 offset += 2 * UNITS_PER_WORD;
1332 /* Calculate the offsets to save normal single registers. */
1333 for (range = 0; range < STACK_REGS_MAX; range++)
1335 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1336 if (! reg_ptr->special_p)
1338 int first = reg_ptr->first;
1339 int last = reg_ptr->last;
1342 for (regno = first; regno <= last; regno++)
1343 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1344 && regno != FRAME_POINTER_REGNUM
1345 && (regno < FIRST_ARG_REGNUM
1346 || regno > LAST_ARG_REGNUM))
1348 info_ptr->reg_offset[regno] = offset;
1349 offset += UNITS_PER_WORD;
1354 /* Calculate the offset to save the local variables at. */
1355 offset = ADDR_ALIGN (offset, alignment);
1356 if (info_ptr->vars_size)
1358 info_ptr->vars_offset = offset;
1359 offset += info_ptr->vars_size;
1362 /* Align header to a dword-boundary. */
1363 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1365 /* Calculate the offsets in the fixed frame. */
1366 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1367 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1368 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1370 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1371 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1372 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1374 if (cfun->returns_struct)
1376 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1377 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1378 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1381 /* Calculate the offsets to store the arguments passed in registers
1382 for stdarg functions. The register pairs are first and the single
1383 register if any is last. The register save area starts on a
1385 if (info_ptr->stdarg_size)
1387 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1388 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1391 /* Skip the header. */
1392 offset += 4 * UNITS_PER_WORD;
1393 for (regno = first; regno <= last; regno++)
1395 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1397 info_ptr->reg_offset[regno] = offset;
1398 offset += 2 * UNITS_PER_WORD;
1400 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1402 info_ptr->reg_offset[regno] = offset;
1403 offset += UNITS_PER_WORD;
1409 if (reload_completed)
1410 frv_stack_cache = info_ptr;
1416 /* Print the information about the frv stack offsets, etc. when debugging. */
1419 frv_debug_stack (frv_stack_t *info)
1424 info = frv_stack_info ();
1426 fprintf (stderr, "\nStack information for function %s:\n",
1427 ((current_function_decl && DECL_NAME (current_function_decl))
1428 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1431 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1432 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1433 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1434 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1435 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1437 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1438 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1439 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1440 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1442 for (range = 0; range < STACK_REGS_MAX; range++)
1444 frv_stack_regs_t *regs = &(info->regs[range]);
1445 if ((regs->size_1word + regs->size_2words) > 0)
1447 int first = regs->first;
1448 int last = regs->last;
1451 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1452 regs->name, regs->size_1word + regs->size_2words,
1453 regs->size_1word, regs->size_2words);
1455 for (regno = first; regno <= last; regno++)
1457 if (info->save_p[regno] == REG_SAVE_1WORD)
1458 fprintf (stderr, " %s (%d)", reg_names[regno],
1459 info->reg_offset[regno]);
1461 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1462 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1463 reg_names[regno+1], info->reg_offset[regno]);
1466 fputc ('\n', stderr);
1476 /* Used during final to control the packing of insns. The value is
1477 1 if the current instruction should be packed with the next one,
1478 0 if it shouldn't or -1 if packing is disabled altogether. */
1480 static int frv_insn_packing_flag;
1482 /* True if the current function contains a far jump. */
1485 frv_function_contains_far_jump (void)
1487 rtx insn = get_insns ();
1489 && !(GET_CODE (insn) == JUMP_INSN
1490 /* Ignore tablejump patterns. */
1491 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1492 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1493 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1494 insn = NEXT_INSN (insn);
1495 return (insn != NULL);
1498 /* For the FRV, this function makes sure that a function with far jumps
1499 will return correctly. It also does the VLIW packing. */
1502 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1504 /* If no frame was created, check whether the function uses a call
1505 instruction to implement a far jump. If so, save the link in gr3 and
1506 replace all returns to LR with returns to GR3. GR3 is used because it
1507 is call-clobbered, because is not available to the register allocator,
1508 and because all functions that take a hidden argument pointer will have
1510 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1514 /* Just to check that the above comment is true. */
1515 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1517 /* Generate the instruction that saves the link register. */
1518 fprintf (file, "\tmovsg lr,gr3\n");
1520 /* Replace the LR with GR3 in *return_internal patterns. The insn
1521 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1522 simply emit a different assembly directive because bralr and jmpl
1523 execute in different units. */
1524 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1525 if (GET_CODE (insn) == JUMP_INSN)
1527 rtx pattern = PATTERN (insn);
1528 if (GET_CODE (pattern) == PARALLEL
1529 && XVECLEN (pattern, 0) >= 2
1530 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1531 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1533 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1534 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1535 SET_REGNO (address, GPR_FIRST + 3);
1542 /* Allow the garbage collector to free the nops created by frv_reorg. */
1543 memset (frv_nops, 0, sizeof (frv_nops));
1547 /* Return the next available temporary register in a given class. */
1550 frv_alloc_temp_reg (
1551 frv_tmp_reg_t *info, /* which registers are available */
1552 enum reg_class rclass, /* register class desired */
1553 enum machine_mode mode, /* mode to allocate register with */
1554 int mark_as_used, /* register not available after allocation */
1555 int no_abort) /* return NULL instead of aborting */
1557 int regno = info->next_reg[ (int)rclass ];
1558 int orig_regno = regno;
1559 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1564 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1565 && TEST_HARD_REG_BIT (info->regs, regno))
1568 if (++regno >= FIRST_PSEUDO_REGISTER)
1570 if (regno == orig_regno)
1572 gcc_assert (no_abort);
1577 nr = HARD_REGNO_NREGS (regno, mode);
1578 info->next_reg[ (int)rclass ] = regno + nr;
1581 for (i = 0; i < nr; i++)
1582 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1584 return gen_rtx_REG (mode, regno);
1588 /* Return an rtx with the value OFFSET, which will either be a register or a
1589 signed 12-bit integer. It can be used as the second operand in an "add"
1590 instruction, or as the index in a load or store.
1592 The function returns a constant rtx if OFFSET is small enough, otherwise
1593 it loads the constant into register OFFSET_REGNO and returns that. */
1595 frv_frame_offset_rtx (int offset)
1597 rtx offset_rtx = GEN_INT (offset);
1598 if (IN_RANGE_P (offset, -2048, 2047))
1602 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1603 if (IN_RANGE_P (offset, -32768, 32767))
1604 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1607 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1608 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1614 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1615 prologue and epilogue uses such expressions to access the stack. */
1617 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1619 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1621 frv_frame_offset_rtx (offset)));
1624 /* Generate a frame-related expression:
1626 (set REG (mem (plus (sp) (const_int OFFSET)))).
1628 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1629 instructions. Marking the expressions as frame-related is superfluous if
1630 the note contains just a single set. But if the note contains a PARALLEL
1631 or SEQUENCE that has several sets, each set must be individually marked
1632 as frame-related. */
1634 frv_dwarf_store (rtx reg, int offset)
1636 rtx set = gen_rtx_SET (VOIDmode,
1637 gen_rtx_MEM (GET_MODE (reg),
1638 plus_constant (stack_pointer_rtx,
1641 RTX_FRAME_RELATED_P (set) = 1;
1645 /* Emit a frame-related instruction whose pattern is PATTERN. The
1646 instruction is the last in a sequence that cumulatively performs the
1647 operation described by DWARF_PATTERN. The instruction is marked as
1648 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1651 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1653 rtx insn = emit_insn (pattern);
1654 RTX_FRAME_RELATED_P (insn) = 1;
1655 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1660 /* Emit instructions that transfer REG to or from the memory location (sp +
1661 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1662 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1663 function to store registers and only the epilogue uses it to load them.
1665 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1666 The generated instruction will use BASE as its base register. BASE may
1667 simply be the stack pointer, but if several accesses are being made to a
1668 region far away from the stack pointer, it may be more efficient to set
1669 up a temporary instead.
1671 Store instructions will be frame-related and will be annotated with the
1672 overall effect of the store. Load instructions will be followed by a
1673 (use) to prevent later optimizations from zapping them.
1675 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1676 as a temporary in such cases. */
1678 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1680 enum machine_mode mode = GET_MODE (reg);
1681 rtx mem = frv_frame_mem (mode,
1683 stack_offset - accessor->base_offset);
1685 if (accessor->op == FRV_LOAD)
1687 if (SPR_P (REGNO (reg)))
1689 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1690 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1691 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1695 /* We cannot use reg+reg addressing for DImode access. */
1697 && GET_CODE (XEXP (mem, 0)) == PLUS
1698 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1699 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1701 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1702 rtx insn = emit_move_insn (temp,
1703 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1704 XEXP (XEXP (mem, 0), 1)));
1705 mem = gen_rtx_MEM (DImode, temp);
1707 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1713 if (SPR_P (REGNO (reg)))
1715 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1716 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1717 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1718 frv_dwarf_store (reg, stack_offset));
1720 else if (mode == DImode)
1722 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1723 with a separate save for each register. */
1724 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1725 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1726 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1727 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1729 /* Also we cannot use reg+reg addressing. */
1730 if (GET_CODE (XEXP (mem, 0)) == PLUS
1731 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1732 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1734 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1735 rtx insn = emit_move_insn (temp,
1736 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1737 XEXP (XEXP (mem, 0), 1)));
1738 mem = gen_rtx_MEM (DImode, temp);
1741 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1742 gen_rtx_PARALLEL (VOIDmode,
1743 gen_rtvec (2, set1, set2)));
1746 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1747 frv_dwarf_store (reg, stack_offset));
1751 /* A function that uses frv_frame_access to transfer a group of registers to
1752 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1753 is the stack information generated by frv_stack_info, and REG_SET is the
1754 number of the register set to transfer. */
1756 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1760 frv_stack_regs_t *regs_info;
1763 regs_info = &info->regs[reg_set];
1764 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1765 if (info->save_p[regno])
1766 frv_frame_access (accessor,
1767 info->save_p[regno] == REG_SAVE_2WORDS
1768 ? gen_rtx_REG (DImode, regno)
1769 : gen_rtx_REG (SImode, regno),
1770 info->reg_offset[regno]);
1773 /* Save or restore callee-saved registers that are kept outside the frame
1774 header. The function saves the registers if OP is FRV_STORE and restores
1775 them if OP is FRV_LOAD. INFO is the stack information generated by
1778 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1780 frv_frame_accessor_t accessor;
1783 accessor.base = stack_pointer_rtx;
1784 accessor.base_offset = 0;
1785 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1786 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1787 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1791 /* Called after register allocation to add any instructions needed for the
1792 prologue. Using a prologue insn is favored compared to putting all of the
1793 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1794 it allows the scheduler to intermix instructions with the saves of
1795 the caller saved registers. In some cases, it might be necessary
1796 to emit a barrier instruction as the last insn to prevent such
1799 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1800 so that the debug info generation code can handle them properly. */
1802 frv_expand_prologue (void)
1804 frv_stack_t *info = frv_stack_info ();
1805 rtx sp = stack_pointer_rtx;
1806 rtx fp = frame_pointer_rtx;
1807 frv_frame_accessor_t accessor;
1809 if (TARGET_DEBUG_STACK)
1810 frv_debug_stack (info);
1812 if (info->total_size == 0)
1815 /* We're interested in three areas of the frame here:
1817 A: the register save area
1819 C: the header after B
1821 If the frame pointer isn't used, we'll have to set up A, B and C
1822 using the stack pointer. If the frame pointer is used, we'll access
1826 B: set up using sp or a temporary (see below)
1829 We set up B using the stack pointer if the frame is small enough.
1830 Otherwise, it's more efficient to copy the old stack pointer into a
1831 temporary and use that.
1833 Note that it's important to make sure the prologue and epilogue use the
1834 same registers to access A and C, since doing otherwise will confuse
1835 the aliasing code. */
1837 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1838 isn't used, the same method will serve for C. */
1839 accessor.op = FRV_STORE;
1840 if (frame_pointer_needed && info->total_size > 2048)
1844 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1845 accessor.base_offset = info->total_size;
1846 insn = emit_insn (gen_movsi (accessor.base, sp));
1850 accessor.base = stack_pointer_rtx;
1851 accessor.base_offset = 0;
1854 /* Allocate the stack space. */
1856 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1857 rtx dwarf_offset = GEN_INT (-info->total_size);
1859 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1862 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1865 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1866 and point the new one to that location. */
1867 if (frame_pointer_needed)
1869 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1871 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1872 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1874 rtx asm_src = plus_constant (accessor.base,
1875 fp_offset - accessor.base_offset);
1876 rtx dwarf_src = plus_constant (sp, fp_offset);
1878 /* Store the old frame pointer at (sp + FP_OFFSET). */
1879 frv_frame_access (&accessor, fp, fp_offset);
1881 /* Set up the new frame pointer. */
1882 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1883 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1885 /* Access region C from the frame pointer. */
1887 accessor.base_offset = fp_offset;
1890 /* Set up region C. */
1891 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1892 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1893 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1895 /* Set up region A. */
1896 frv_frame_access_standard_regs (FRV_STORE, info);
1898 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1899 scheduler from moving loads before the stores saving the registers. */
1900 if (info->stdarg_size > 0)
1901 emit_insn (gen_blockage ());
1903 /* Set up pic register/small data register for this function. */
1904 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1905 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1906 gen_rtx_REG (Pmode, LR_REGNO),
1907 gen_rtx_REG (SImode, OFFSET_REGNO)));
1911 /* Under frv, all of the work is done via frv_expand_epilogue, but
1912 this function provides a convenient place to do cleanup. */
1915 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1916 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1918 frv_stack_cache = (frv_stack_t *)0;
1920 /* Zap last used registers for conditional execution. */
1921 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1923 /* Release the bitmap of created insns. */
1924 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1928 /* Called after register allocation to add any instructions needed for the
1929 epilogue. Using an epilogue insn is favored compared to putting all of the
1930 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1931 it allows the scheduler to intermix instructions with the saves of
1932 the caller saved registers. In some cases, it might be necessary
1933 to emit a barrier instruction as the last insn to prevent such
1937 frv_expand_epilogue (bool emit_return)
1939 frv_stack_t *info = frv_stack_info ();
1940 rtx fp = frame_pointer_rtx;
1941 rtx sp = stack_pointer_rtx;
1945 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1947 /* Restore the stack pointer to its original value if alloca or the like
1949 if (! current_function_sp_is_unchanging)
1950 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1952 /* Restore the callee-saved registers that were used in this function. */
1953 frv_frame_access_standard_regs (FRV_LOAD, info);
1955 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1956 no return instruction should be emitted. */
1957 if (info->save_p[LR_REGNO])
1962 /* Use the same method to access the link register's slot as we did in
1963 the prologue. In other words, use the frame pointer if available,
1964 otherwise use the stack pointer.
1966 LR_OFFSET is the offset of the link register's slot from the start
1967 of the frame and MEM is a memory rtx for it. */
1968 lr_offset = info->reg_offset[LR_REGNO];
1969 if (frame_pointer_needed)
1970 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1972 mem = frv_frame_mem (Pmode, sp, lr_offset);
1974 /* Load the old link register into a GPR. */
1975 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1976 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1979 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1981 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1982 the load is preserved. */
1983 if (frame_pointer_needed)
1985 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1989 /* Deallocate the stack frame. */
1990 if (info->total_size != 0)
1992 rtx offset = frv_frame_offset_rtx (info->total_size);
1993 emit_insn (gen_stack_adjust (sp, sp, offset));
1996 /* If this function uses eh_return, add the final stack adjustment now. */
1997 if (crtl->calls_eh_return)
1998 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2001 emit_jump_insn (gen_epilogue_return (return_addr));
2004 rtx lr = return_addr;
2006 if (REGNO (return_addr) != LR_REGNO)
2008 lr = gen_rtx_REG (Pmode, LR_REGNO);
2009 emit_move_insn (lr, return_addr);
2017 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2020 frv_asm_output_mi_thunk (FILE *file,
2021 tree thunk_fndecl ATTRIBUTE_UNUSED,
2022 HOST_WIDE_INT delta,
2023 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2026 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2027 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2028 const char *name_jmp = reg_names[JUMP_REGNO];
2029 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2031 /* Do the add using an addi if possible. */
2032 if (IN_RANGE_P (delta, -2048, 2047))
2033 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2036 const char *const name_add = reg_names[TEMP_REGNO];
2037 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2038 parallel, delta, name_add);
2039 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2041 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2046 const char *name_pic = reg_names[FDPIC_REGNO];
2047 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2051 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2052 assemble_name (file, name_func);
2053 fprintf (file, "),%s\n", name_jmp);
2055 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2056 assemble_name (file, name_func);
2057 fprintf (file, "),%s\n", name_jmp);
2059 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2063 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2064 assemble_name (file, name_func);
2065 fprintf (file, "\t)), %s\n", name_jmp);
2070 fprintf (file, "\tsethi%s #hi(", parallel);
2071 assemble_name (file, name_func);
2072 fprintf (file, "),%s\n", name_jmp);
2074 fprintf (file, "\tsetlo #lo(");
2075 assemble_name (file, name_func);
2076 fprintf (file, "),%s\n", name_jmp);
2080 /* Use JUMP_REGNO as a temporary PIC register. */
2081 const char *name_lr = reg_names[LR_REGNO];
2082 const char *name_gppic = name_jmp;
2083 const char *name_tmp = reg_names[TEMP_REGNO];
2085 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2086 fprintf (file, "\tcall 1f\n");
2087 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2088 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2089 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2090 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2091 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2093 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2094 assemble_name (file, name_func);
2095 fprintf (file, "),%s\n", name_tmp);
2097 fprintf (file, "\tsetlo #gprello(");
2098 assemble_name (file, name_func);
2099 fprintf (file, "),%s\n", name_tmp);
2101 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2104 /* Jump to the function address. */
2105 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2110 /* On frv, create a frame whenever we need to create stack. */
2113 frv_frame_pointer_required (void)
2115 /* If we forgoing the usual linkage requirements, we only need
2116 a frame pointer if the stack pointer might change. */
2117 if (!TARGET_LINKED_FP)
2118 return !current_function_sp_is_unchanging;
2120 if (! current_function_is_leaf)
2123 if (get_frame_size () != 0)
2129 if (!current_function_sp_is_unchanging)
2132 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2138 if (cfun->machine->frame_needed)
2145 /* Worker function for TARGET_CAN_ELIMINATE. */
2148 frv_can_eliminate (const int from, const int to)
2150 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2151 ? ! frame_pointer_needed
2155 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2156 initial difference between the specified pair of registers. This macro must
2157 be defined if `ELIMINABLE_REGS' is defined. */
2159 /* See frv_stack_info for more details on the frv stack frame. */
2162 frv_initial_elimination_offset (int from, int to)
2164 frv_stack_t *info = frv_stack_info ();
2167 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2168 ret = info->total_size - info->pretend_size;
2170 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2171 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2173 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2174 ret = (info->total_size
2175 - info->reg_offset[FRAME_POINTER_REGNUM]
2176 - info->pretend_size);
2181 if (TARGET_DEBUG_STACK)
2182 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2183 reg_names [from], reg_names[to], ret);
2189 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2192 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2193 enum machine_mode mode,
2194 tree type ATTRIBUTE_UNUSED,
2198 if (TARGET_DEBUG_ARG)
2200 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2201 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2205 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2208 frv_expand_builtin_saveregs (void)
2210 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2212 if (TARGET_DEBUG_ARG)
2213 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2216 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2220 /* Expand __builtin_va_start to do the va_start macro. */
2223 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2226 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2228 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2229 GEN_INT (UNITS_PER_WORD * num));
2231 if (TARGET_DEBUG_ARG)
2233 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2234 crtl->args.info, num);
2236 debug_rtx (nextarg);
2239 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2240 fold_convert (TREE_TYPE (valist),
2241 make_tree (sizetype, nextarg)));
2242 TREE_SIDE_EFFECTS (t) = 1;
2244 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2248 /* Expand a block move operation, and return 1 if successful. Return 0
2249 if we should let the compiler generate normal code.
2251 operands[0] is the destination
2252 operands[1] is the source
2253 operands[2] is the length
2254 operands[3] is the alignment */
2256 /* Maximum number of loads to do before doing the stores */
2257 #ifndef MAX_MOVE_REG
2258 #define MAX_MOVE_REG 4
2261 /* Maximum number of total loads to do. */
2262 #ifndef TOTAL_MOVE_REG
2263 #define TOTAL_MOVE_REG 8
2267 frv_expand_block_move (rtx operands[])
2269 rtx orig_dest = operands[0];
2270 rtx orig_src = operands[1];
2271 rtx bytes_rtx = operands[2];
2272 rtx align_rtx = operands[3];
2273 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2286 rtx stores[MAX_MOVE_REG];
2288 enum machine_mode mode;
2290 /* If this is not a fixed size move, just call memcpy. */
2294 /* This should be a fixed size alignment. */
2295 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2297 align = INTVAL (align_rtx);
2299 /* Anything to move? */
2300 bytes = INTVAL (bytes_rtx);
2304 /* Don't support real large moves. */
2305 if (bytes > TOTAL_MOVE_REG*align)
2308 /* Move the address into scratch registers. */
2309 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2310 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2312 num_reg = offset = 0;
2313 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2315 /* Calculate the correct offset for src/dest. */
2319 dest_addr = dest_reg;
2323 src_addr = plus_constant (src_reg, offset);
2324 dest_addr = plus_constant (dest_reg, offset);
2327 /* Generate the appropriate load and store, saving the stores
2329 if (bytes >= 4 && align >= 4)
2331 else if (bytes >= 2 && align >= 2)
2336 move_bytes = GET_MODE_SIZE (mode);
2337 tmp_reg = gen_reg_rtx (mode);
2338 src_mem = change_address (orig_src, mode, src_addr);
2339 dest_mem = change_address (orig_dest, mode, dest_addr);
2340 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2341 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2343 if (num_reg >= MAX_MOVE_REG)
2345 for (i = 0; i < num_reg; i++)
2346 emit_insn (stores[i]);
2351 for (i = 0; i < num_reg; i++)
2352 emit_insn (stores[i]);
2358 /* Expand a block clear operation, and return 1 if successful. Return 0
2359 if we should let the compiler generate normal code.
2361 operands[0] is the destination
2362 operands[1] is the length
2363 operands[3] is the alignment */
2366 frv_expand_block_clear (rtx operands[])
2368 rtx orig_dest = operands[0];
2369 rtx bytes_rtx = operands[1];
2370 rtx align_rtx = operands[3];
2371 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2380 enum machine_mode mode;
2382 /* If this is not a fixed size move, just call memcpy. */
2386 /* This should be a fixed size alignment. */
2387 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2389 align = INTVAL (align_rtx);
2391 /* Anything to move? */
2392 bytes = INTVAL (bytes_rtx);
2396 /* Don't support real large clears. */
2397 if (bytes > TOTAL_MOVE_REG*align)
2400 /* Move the address into a scratch register. */
2401 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2403 num_reg = offset = 0;
2404 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2406 /* Calculate the correct offset for src/dest. */
2407 dest_addr = ((offset == 0)
2409 : plus_constant (dest_reg, offset));
2411 /* Generate the appropriate store of gr0. */
2412 if (bytes >= 4 && align >= 4)
2414 else if (bytes >= 2 && align >= 2)
2419 clear_bytes = GET_MODE_SIZE (mode);
2420 dest_mem = change_address (orig_dest, mode, dest_addr);
2421 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2428 /* The following variable is used to output modifiers of assembler
2429 code of the current output insn. */
2431 static rtx *frv_insn_operands;
2433 /* The following function is used to add assembler insn code suffix .p
2434 if it is necessary. */
2437 frv_asm_output_opcode (FILE *f, const char *ptr)
2441 if (frv_insn_packing_flag <= 0)
2444 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2447 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2448 || (*ptr >= 'A' && *ptr <= 'Z')))
2450 int letter = *ptr++;
2453 frv_print_operand (f, frv_insn_operands [c], letter);
2454 while ((c = *ptr) >= '0' && c <= '9')
2466 /* Set up the packing bit for the current output insn. Note that this
2467 function is not called for asm insns. */
2470 frv_final_prescan_insn (rtx insn, rtx *opvec,
2471 int noperands ATTRIBUTE_UNUSED)
2475 if (frv_insn_packing_flag >= 0)
2477 frv_insn_operands = opvec;
2478 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2480 else if (recog_memoized (insn) >= 0
2481 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2482 /* Packing optimizations have been disabled, but INSN can only
2483 be issued in M1. Insert an mnop in M0. */
2484 fprintf (asm_out_file, "\tmnop.p\n");
2490 /* A C expression whose value is RTL representing the address in a stack frame
2491 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2492 an RTL expression for the address of the stack frame itself.
2494 If you don't define this macro, the default is to return the value of
2495 FRAMEADDR--that is, the stack frame address is also the address of the stack
2496 word that points to the previous frame. */
2498 /* The default is correct, but we need to make sure the frame gets created. */
2500 frv_dynamic_chain_address (rtx frame)
2502 cfun->machine->frame_needed = 1;
2507 /* A C expression whose value is RTL representing the value of the return
2508 address for the frame COUNT steps up from the current frame, after the
2509 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2510 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2513 The value of the expression must always be the correct address when COUNT is
2514 zero, but may be `NULL_RTX' if there is not way to determine the return
2515 address of other frames. */
2518 frv_return_addr_rtx (int count, rtx frame)
2522 cfun->machine->frame_needed = 1;
2523 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2526 /* Given a memory reference MEMREF, interpret the referenced memory as
2527 an array of MODE values, and return a reference to the element
2528 specified by INDEX. Assume that any pre-modification implicit in
2529 MEMREF has already happened.
2531 MEMREF must be a legitimate operand for modes larger than SImode.
2532 frv_legitimate_address_p forbids register+register addresses, which
2533 this function cannot handle. */
2535 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2537 rtx base = XEXP (memref, 0);
2538 if (GET_CODE (base) == PRE_MODIFY)
2539 base = XEXP (base, 0);
2540 return change_address (memref, mode,
2541 plus_constant (base, index * GET_MODE_SIZE (mode)));
2545 /* Print a memory address as an operand to reference that memory location. */
2547 frv_print_operand_address (FILE * stream, rtx x)
2549 if (GET_CODE (x) == MEM)
2552 switch (GET_CODE (x))
2555 fputs (reg_names [ REGNO (x)], stream);
2559 fprintf (stream, "%ld", (long) INTVAL (x));
2563 assemble_name (stream, XSTR (x, 0));
2568 output_addr_const (stream, x);
2572 /* Poorly constructed asm statements can trigger this alternative.
2573 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2574 frv_print_operand_memory_reference (stream, x, 0);
2581 fatal_insn ("bad insn to frv_print_operand_address:", x);
2586 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2588 int regno = true_regnum (x);
2590 fputs (reg_names[regno], stream);
2592 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2595 /* Print a memory reference suitable for the ld/st instructions. */
2598 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2600 struct frv_unspec unspec;
2604 switch (GET_CODE (x))
2611 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2613 x1 = XEXP (XEXP (x, 1), 1);
2623 if (GET_CODE (x0) == CONST_INT)
2631 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2640 else if (GET_CODE (x1) != CONST_INT)
2641 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2644 fputs ("@(", stream);
2646 fputs (reg_names[GPR_R0], stream);
2647 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2648 frv_print_operand_memory_reference_reg (stream, x0);
2650 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2652 fputs (",", stream);
2654 fputs (reg_names [GPR_R0], stream);
2658 switch (GET_CODE (x1))
2662 frv_print_operand_memory_reference_reg (stream, x1);
2666 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2670 if (!frv_const_unspec_p (x1, &unspec))
2671 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2672 frv_output_const_unspec (stream, &unspec);
2676 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2680 fputs (")", stream);
2684 /* Return 2 for likely branches and 0 for non-likely branches */
2686 #define FRV_JUMP_LIKELY 2
2687 #define FRV_JUMP_NOT_LIKELY 0
2690 frv_print_operand_jump_hint (rtx insn)
2695 HOST_WIDE_INT prob = -1;
2696 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2698 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2700 /* Assume any non-conditional jump is likely. */
2701 if (! any_condjump_p (insn))
2702 ret = FRV_JUMP_LIKELY;
2706 labelref = condjump_label (insn);
2709 rtx label = XEXP (labelref, 0);
2710 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2715 note = find_reg_note (insn, REG_BR_PROB, 0);
2717 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2721 prob = INTVAL (XEXP (note, 0));
2722 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2724 : FRV_JUMP_NOT_LIKELY);
2736 case UNKNOWN: direction = "unknown jump direction"; break;
2737 case BACKWARD: direction = "jump backward"; break;
2738 case FORWARD: direction = "jump forward"; break;
2742 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2743 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2744 (long)INSN_UID (insn), direction, (long)prob,
2745 (long)REG_BR_PROB_BASE, ret);
2753 /* Return the comparison operator to use for CODE given that the ICC
2757 comparison_string (enum rtx_code code, rtx op0)
2759 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2762 default: output_operand_lossage ("bad condition code");
2763 case EQ: return "eq";
2764 case NE: return "ne";
2765 case LT: return is_nz_p ? "n" : "lt";
2766 case LE: return "le";
2767 case GT: return "gt";
2768 case GE: return is_nz_p ? "p" : "ge";
2769 case LTU: return is_nz_p ? "no" : "c";
2770 case LEU: return is_nz_p ? "eq" : "ls";
2771 case GTU: return is_nz_p ? "ne" : "hi";
2772 case GEU: return is_nz_p ? "ra" : "nc";
2776 /* Print an operand to an assembler instruction.
2778 `%' followed by a letter and a digit says to output an operand in an
2779 alternate fashion. Four letters have standard, built-in meanings
2780 described below. The hook `TARGET_PRINT_OPERAND' can define
2781 additional letters with nonstandard meanings.
2783 `%cDIGIT' can be used to substitute an operand that is a constant value
2784 without the syntax that normally indicates an immediate operand.
2786 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2789 `%aDIGIT' can be used to substitute an operand as if it were a memory
2790 reference, with the actual operand treated as the address. This may be
2791 useful when outputting a "load address" instruction, because often the
2792 assembler syntax for such an instruction requires you to write the operand
2793 as if it were a memory reference.
2795 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2797 `%=' outputs a number which is unique to each instruction in the entire
2798 compilation. This is useful for making local labels to be referred to more
2799 than once in a single template that generates multiple assembler
2802 `%' followed by a punctuation character specifies a substitution that
2803 does not use an operand. Only one case is standard: `%%' outputs a
2804 `%' into the assembler code. Other nonstandard cases can be defined
2805 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2806 punctuation characters are valid with the
2807 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2810 frv_print_operand (FILE * file, rtx x, int code)
2812 struct frv_unspec unspec;
2813 HOST_WIDE_INT value;
2816 if (code != 0 && !ISALPHA (code))
2819 else if (GET_CODE (x) == CONST_INT)
2822 else if (GET_CODE (x) == CONST_DOUBLE)
2824 if (GET_MODE (x) == SFmode)
2829 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2830 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2834 else if (GET_MODE (x) == VOIDmode)
2835 value = CONST_DOUBLE_LOW (x);
2838 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2849 fputs (reg_names[GPR_R0], file);
2853 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2857 /* Output small data area base register (gr16). */
2858 fputs (reg_names[SDA_BASE_REG], file);
2862 /* Output pic register (gr17). */
2863 fputs (reg_names[PIC_REGNO], file);
2867 /* Output the temporary integer CCR register. */
2868 fputs (reg_names[ICR_TEMP], file);
2872 /* Output the temporary integer CC register. */
2873 fputs (reg_names[ICC_TEMP], file);
2876 /* case 'a': print an address. */
2879 /* Print appropriate test for integer branch false operation. */
2880 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2881 XEXP (x, 0)), file);
2885 /* Print appropriate test for integer branch true operation. */
2886 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2890 /* Print 1 for a NE and 0 for an EQ to give the final argument
2891 for a conditional instruction. */
2892 if (GET_CODE (x) == NE)
2895 else if (GET_CODE (x) == EQ)
2899 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2903 /* Print appropriate test for floating point branch false operation. */
2904 switch (GET_CODE (x))
2907 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2909 case EQ: fputs ("ne", file); break;
2910 case NE: fputs ("eq", file); break;
2911 case LT: fputs ("uge", file); break;
2912 case LE: fputs ("ug", file); break;
2913 case GT: fputs ("ule", file); break;
2914 case GE: fputs ("ul", file); break;
2919 /* Print appropriate test for floating point branch true operation. */
2920 switch (GET_CODE (x))
2923 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2925 case EQ: fputs ("eq", file); break;
2926 case NE: fputs ("ne", file); break;
2927 case LT: fputs ("lt", file); break;
2928 case LE: fputs ("le", file); break;
2929 case GT: fputs ("gt", file); break;
2930 case GE: fputs ("ge", file); break;
2935 /* Print appropriate GOT function. */
2936 if (GET_CODE (x) != CONST_INT)
2937 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2938 fputs (unspec_got_name (INTVAL (x)), file);
2942 /* Print 'i' if the operand is a constant, or is a memory reference that
2944 if (GET_CODE (x) == MEM)
2945 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2946 ? XEXP (XEXP (x, 0), 1)
2948 else if (GET_CODE (x) == PLUS)
2951 switch (GET_CODE (x))
2965 /* For jump instructions, print 'i' if the operand is a constant or
2966 is an expression that adds a constant. */
2967 if (GET_CODE (x) == CONST_INT)
2972 if (GET_CODE (x) == CONST_INT
2973 || (GET_CODE (x) == PLUS
2974 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2975 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2981 /* Print the lower register of a double word register pair */
2982 if (GET_CODE (x) == REG)
2983 fputs (reg_names[ REGNO (x)+1 ], file);
2985 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2988 /* case 'l': print a LABEL_REF. */
2992 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2993 for the second word of double memory operations. */
2994 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2995 switch (GET_CODE (x))
2998 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3001 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3009 frv_print_operand_memory_reference (file, x, offset);
3015 /* Print the opcode of a command. */
3016 switch (GET_CODE (x))
3019 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3021 case PLUS: fputs ("add", file); break;
3022 case MINUS: fputs ("sub", file); break;
3023 case AND: fputs ("and", file); break;
3024 case IOR: fputs ("or", file); break;
3025 case XOR: fputs ("xor", file); break;
3026 case ASHIFT: fputs ("sll", file); break;
3027 case ASHIFTRT: fputs ("sra", file); break;
3028 case LSHIFTRT: fputs ("srl", file); break;
3032 /* case 'n': negate and print a constant int. */
3035 /* Print PIC label using operand as the number. */
3036 if (GET_CODE (x) != CONST_INT)
3037 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3039 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3043 /* Print 'u' if the operand is a update load/store. */
3044 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3049 /* If value is 0, print gr0, otherwise it must be a register. */
3050 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3051 fputs (reg_names[GPR_R0], file);
3053 else if (GET_CODE (x) == REG)
3054 fputs (reg_names [REGNO (x)], file);
3057 fatal_insn ("bad insn in frv_print_operand, z case", x);
3061 /* Print constant in hex. */
3062 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3064 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3071 if (GET_CODE (x) == REG)
3072 fputs (reg_names [REGNO (x)], file);
3074 else if (GET_CODE (x) == CONST_INT
3075 || GET_CODE (x) == CONST_DOUBLE)
3076 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3078 else if (frv_const_unspec_p (x, &unspec))
3079 frv_output_const_unspec (file, &unspec);
3081 else if (GET_CODE (x) == MEM)
3082 frv_print_operand_address (file, XEXP (x, 0));
3084 else if (CONSTANT_ADDRESS_P (x))
3085 frv_print_operand_address (file, x);
3088 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3093 fatal_insn ("frv_print_operand: unknown code", x);
3101 frv_print_operand_punct_valid_p (unsigned char code)
3103 return (code == '.' || code == '#' || code == '@' || code == '~'
3104 || code == '*' || code == '&');
3108 /* A C statement (sans semicolon) for initializing the variable CUM for the
3109 state at the beginning of the argument list. The variable has type
3110 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3111 of the function which will receive the args, or 0 if the args are to a
3112 compiler support library function. The value of INDIRECT is nonzero when
3113 processing an indirect call, for example a call through a function pointer.
3114 The value of INDIRECT is zero for a call to an explicitly named function, a
3115 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3116 arguments for the function being compiled.
3118 When processing a call to a compiler support library function, LIBNAME
3119 identifies which one. It is a `symbol_ref' rtx which contains the name of
3120 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3121 being processed. Thus, each time this macro is called, either LIBNAME or
3122 FNTYPE is nonzero, but never both of them at once. */
3125 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3131 *cum = FIRST_ARG_REGNUM;
3133 if (TARGET_DEBUG_ARG)
3135 fprintf (stderr, "\ninit_cumulative_args:");
3136 if (!fndecl && fntype)
3137 fputs (" indirect", stderr);
3140 fputs (" incoming", stderr);
3144 tree ret_type = TREE_TYPE (fntype);
3145 fprintf (stderr, " return=%s,",
3146 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3149 if (libname && GET_CODE (libname) == SYMBOL_REF)
3150 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3152 if (cfun->returns_struct)
3153 fprintf (stderr, " return-struct");
3155 putc ('\n', stderr);
3160 /* Return true if we should pass an argument on the stack rather than
3164 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3166 if (mode == BLKmode)
3170 return AGGREGATE_TYPE_P (type);
3173 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3174 argument with the specified mode and type. If it is not defined,
3175 `PARM_BOUNDARY' is used for all arguments. */
3178 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3179 tree type ATTRIBUTE_UNUSED)
3181 return BITS_PER_WORD;
3185 frv_function_arg (CUMULATIVE_ARGS *cum,
3186 enum machine_mode mode,
3187 tree type ATTRIBUTE_UNUSED,
3189 int incoming ATTRIBUTE_UNUSED)
3191 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3196 /* Return a marker for use in the call instruction. */
3197 if (xmode == VOIDmode)
3203 else if (arg_num <= LAST_ARG_REGNUM)
3205 ret = gen_rtx_REG (xmode, arg_num);
3206 debstr = reg_names[arg_num];
3215 if (TARGET_DEBUG_ARG)
3217 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3218 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3224 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3225 advance past an argument in the argument list. The values MODE, TYPE and
3226 NAMED describe that argument. Once this is done, the variable CUM is
3227 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3229 This macro need not do anything if the argument in question was passed on
3230 the stack. The compiler knows how to track the amount of stack space used
3231 for arguments without any special help. */
3234 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3235 enum machine_mode mode,
3236 tree type ATTRIBUTE_UNUSED,
3239 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3240 int bytes = GET_MODE_SIZE (xmode);
3241 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3244 *cum = arg_num + words;
3246 if (TARGET_DEBUG_ARG)
3248 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3249 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3253 /* A C expression for the number of words, at the beginning of an argument,
3254 must be put in registers. The value must be zero for arguments that are
3255 passed entirely in registers or that are entirely pushed on the stack.
3257 On some machines, certain arguments must be passed partially in registers
3258 and partially in memory. On these machines, typically the first N words of
3259 arguments are passed in registers, and the rest on the stack. If a
3260 multi-word argument (a `double' or a structure) crosses that boundary, its
3261 first few words must be passed in registers and the rest must be pushed.
3262 This macro tells the compiler when this occurs, and how many of the words
3263 should go in registers.
3265 `FUNCTION_ARG' for these arguments should return the first register to be
3266 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3267 the called function. */
3270 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3271 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3273 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3274 int bytes = GET_MODE_SIZE (xmode);
3275 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3279 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3280 ? LAST_ARG_REGNUM - arg_num + 1
3282 ret *= UNITS_PER_WORD;
3284 if (TARGET_DEBUG_ARG && ret)
3285 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3291 /* Implements TARGET_FUNCTION_VALUE. */
3294 frv_function_value (const_tree valtype,
3295 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3296 bool outgoing ATTRIBUTE_UNUSED)
3298 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3302 /* Implements TARGET_LIBCALL_VALUE. */
3305 frv_libcall_value (enum machine_mode mode,
3306 const_rtx fun ATTRIBUTE_UNUSED)
3308 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3312 /* Implements FUNCTION_VALUE_REGNO_P. */
3315 frv_function_value_regno_p (const unsigned int regno)
3317 return (regno == RETURN_VALUE_REGNUM);
3320 /* Return true if a register is ok to use as a base or index register. */
3322 static FRV_INLINE int
3323 frv_regno_ok_for_base_p (int regno, int strict_p)
3329 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3331 if (regno == ARG_POINTER_REGNUM)
3334 return (regno >= FIRST_PSEUDO_REGISTER);
3338 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3339 RTX) is a legitimate memory address on the target machine for a memory
3340 operand of mode MODE.
3342 It usually pays to define several simpler macros to serve as subroutines for
3343 this one. Otherwise it may be too complicated to understand.
3345 This macro must exist in two variants: a strict variant and a non-strict
3346 one. The strict variant is used in the reload pass. It must be defined so
3347 that any pseudo-register that has not been allocated a hard register is
3348 considered a memory reference. In contexts where some kind of register is
3349 required, a pseudo-register with no hard register must be rejected.
3351 The non-strict variant is used in other passes. It must be defined to
3352 accept all pseudo-registers in every context where some kind of register is
3355 Compiler source files that want to use the strict variant of this macro
3356 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3357 conditional to define the strict variant in that case and the non-strict
3360 Normally, constant addresses which are the sum of a `symbol_ref' and an
3361 integer are stored inside a `const' RTX to mark them as constant.
3362 Therefore, there is no need to recognize such sums specifically as
3363 legitimate addresses. Normally you would simply recognize any `const' as
3366 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3367 constant sums that are not marked with `const'. It assumes that a
3368 naked `plus' indicates indexing. If so, then you *must* reject such
3369 naked constant sums as illegitimate addresses, so that none of them
3370 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3373 frv_legitimate_address_p_1 (enum machine_mode mode,
3377 int allow_double_reg_p)
3381 HOST_WIDE_INT value;
3384 if (FRV_SYMBOL_REF_TLS_P (x))
3387 switch (GET_CODE (x))
3394 if (GET_CODE (x) != REG)
3400 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3406 if (GET_CODE (x0) != REG
3407 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3408 || GET_CODE (x1) != PLUS
3409 || ! rtx_equal_p (x0, XEXP (x1, 0))
3410 || GET_CODE (XEXP (x1, 1)) != REG
3411 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3418 /* 12-bit immediate */
3423 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3425 /* If we can't use load/store double operations, make sure we can
3426 address the second word. */
3427 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3428 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3437 if (GET_CODE (x0) == SUBREG)
3438 x0 = SUBREG_REG (x0);
3440 if (GET_CODE (x0) != REG)
3443 regno0 = REGNO (x0);
3444 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3447 switch (GET_CODE (x1))
3453 x1 = SUBREG_REG (x1);
3454 if (GET_CODE (x1) != REG)
3460 /* Do not allow reg+reg addressing for modes > 1 word if we
3461 can't depend on having move double instructions. */
3462 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3465 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3469 /* 12-bit immediate */
3474 value = INTVAL (x1);
3475 ret = IN_RANGE_P (value, -2048, 2047);
3477 /* If we can't use load/store double operations, make sure we can
3478 address the second word. */
3479 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3480 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3485 if (!condexec_p && got12_operand (x1, VOIDmode))
3493 if (TARGET_DEBUG_ADDR)
3495 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3496 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3497 (condexec_p) ? ", inside conditional code" : "");
3505 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3507 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3510 /* Given an ADDR, generate code to inline the PLT. */
3512 gen_inlined_tls_plt (rtx addr)
3515 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3518 dest = gen_reg_rtx (DImode);
3525 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3526 calll #gettlsoff(ADDR)@(gr8, gr0)
3528 emit_insn (gen_tls_lddi (dest, addr, picreg));
3535 sethi.p #gottlsdeschi(ADDR), gr8
3536 setlo #gottlsdesclo(ADDR), gr8
3537 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3538 calll #gettlsoff(ADDR)@(gr8, gr0)
3540 rtx reguse = gen_reg_rtx (Pmode);
3541 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3542 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3545 retval = gen_reg_rtx (Pmode);
3546 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3550 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3551 the destination address. */
3553 gen_tlsmoff (rtx addr, rtx reg)
3555 rtx dest = gen_reg_rtx (Pmode);
3559 /* sethi.p #tlsmoffhi(x), grA
3560 setlo #tlsmofflo(x), grA
3562 dest = gen_reg_rtx (Pmode);
3563 emit_insn (gen_tlsoff_hilo (dest, addr,
3564 GEN_INT (R_FRV_TLSMOFFHI)));
3565 dest = gen_rtx_PLUS (Pmode, dest, reg);
3569 /* addi grB, #tlsmoff12(x), grC
3571 ld/st @(grB, #tlsmoff12(x)), grC
3573 dest = gen_reg_rtx (Pmode);
3574 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3575 GEN_INT (R_FRV_TLSMOFF12)));
3580 /* Generate code for a TLS address. */
3582 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3584 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3585 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3589 case TLS_MODEL_INITIAL_EXEC:
3593 ldi @(gr15, #gottlsoff12(x)), gr5
3595 dest = gen_reg_rtx (Pmode);
3596 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3597 dest = gen_rtx_PLUS (Pmode, tp, dest);
3601 /* -fPIC or anything else.
3603 sethi.p #gottlsoffhi(x), gr14
3604 setlo #gottlsofflo(x), gr14
3605 ld #tlsoff(x)@(gr15, gr14), gr9
3607 rtx tmp = gen_reg_rtx (Pmode);
3608 dest = gen_reg_rtx (Pmode);
3609 emit_insn (gen_tlsoff_hilo (tmp, addr,
3610 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3612 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3613 dest = gen_rtx_PLUS (Pmode, tp, dest);
3616 case TLS_MODEL_LOCAL_DYNAMIC:
3620 if (TARGET_INLINE_PLT)
3621 retval = gen_inlined_tls_plt (GEN_INT (0));
3624 /* call #gettlsoff(0) */
3625 retval = gen_reg_rtx (Pmode);
3626 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3629 reg = gen_reg_rtx (Pmode);
3630 emit_insn (gen_rtx_SET (VOIDmode, reg,
3631 gen_rtx_PLUS (Pmode,
3634 dest = gen_tlsmoff (addr, reg);
3637 dest = gen_reg_rtx (Pmode);
3638 emit_insn (gen_tlsoff_hilo (dest, addr,
3639 GEN_INT (R_FRV_TLSMOFFHI)));
3640 dest = gen_rtx_PLUS (Pmode, dest, reg);
3644 case TLS_MODEL_LOCAL_EXEC:
3645 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3647 case TLS_MODEL_GLOBAL_DYNAMIC:
3651 if (TARGET_INLINE_PLT)
3652 retval = gen_inlined_tls_plt (addr);
3655 /* call #gettlsoff(x) */
3656 retval = gen_reg_rtx (Pmode);
3657 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3659 dest = gen_rtx_PLUS (Pmode, retval, tp);
3670 frv_legitimize_address (rtx x,
3671 rtx oldx ATTRIBUTE_UNUSED,
3672 enum machine_mode mode ATTRIBUTE_UNUSED)
3674 if (GET_CODE (x) == SYMBOL_REF)
3676 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3678 return frv_legitimize_tls_address (x, model);
3684 /* Test whether a local function descriptor is canonical, i.e.,
3685 whether we can use FUNCDESC_GOTOFF to compute the address of the
3689 frv_local_funcdesc_p (rtx fnx)
3692 enum symbol_visibility vis;
3695 if (! SYMBOL_REF_LOCAL_P (fnx))
3698 fn = SYMBOL_REF_DECL (fnx);
3703 vis = DECL_VISIBILITY (fn);
3705 if (vis == VISIBILITY_PROTECTED)
3706 /* Private function descriptors for protected functions are not
3707 canonical. Temporarily change the visibility to global. */
3708 vis = VISIBILITY_DEFAULT;
3709 else if (flag_shlib)
3710 /* If we're already compiling for a shared library (that, unlike
3711 executables, can't assume that the existence of a definition
3712 implies local binding), we can skip the re-testing. */
3715 ret = default_binds_local_p_1 (fn, flag_pic);
3717 DECL_VISIBILITY (fn) = vis;
3722 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3726 frv_gen_GPsym2reg (rtx dest, rtx src)
3728 tree gp = get_identifier ("_gp");
3729 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3731 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3735 unspec_got_name (int i)
3739 case R_FRV_GOT12: return "got12";
3740 case R_FRV_GOTHI: return "gothi";
3741 case R_FRV_GOTLO: return "gotlo";
3742 case R_FRV_FUNCDESC: return "funcdesc";
3743 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3744 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3745 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3746 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3747 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3748 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3749 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3750 case R_FRV_GOTOFF12: return "gotoff12";
3751 case R_FRV_GOTOFFHI: return "gotoffhi";
3752 case R_FRV_GOTOFFLO: return "gotofflo";
3753 case R_FRV_GPREL12: return "gprel12";
3754 case R_FRV_GPRELHI: return "gprelhi";
3755 case R_FRV_GPRELLO: return "gprello";
3756 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3757 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3758 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3759 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3760 case R_FRV_TLSMOFF12: return "tlsmoff12";
3761 case R_FRV_TLSDESCHI: return "tlsdeschi";
3762 case R_FRV_TLSDESCLO: return "tlsdesclo";
3763 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3764 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3765 default: gcc_unreachable ();
3769 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3770 is added inside the relocation operator. */
3773 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3775 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3776 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3777 fputs (")", stream);
3780 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3781 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3782 otherwise return ORIG_X. */
3785 frv_find_base_term (rtx x)
3787 struct frv_unspec unspec;
3789 if (frv_const_unspec_p (x, &unspec)
3790 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3791 return plus_constant (unspec.symbol, unspec.offset);
3796 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3797 the operand is used by a predicated instruction. */
3800 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3802 return ((GET_MODE (op) == mode || mode == VOIDmode)
3803 && GET_CODE (op) == MEM
3804 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3805 reload_completed, condexec_p, FALSE));
3809 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3811 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3812 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3818 rvrtx = operands[0];
3822 addr = XEXP (operands[0], 0);
3824 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3825 any calls that would involve a PLT, but can't tell, since we
3826 don't know whether an extern function is going to be provided by
3827 a separate translation unit or imported from a separate module.
3828 When compiling for shared libraries, if the function has default
3829 visibility, we assume it's overridable, so we inline the PLT, but
3830 for executables, we don't really have a way to make a good
3831 decision: a function is as likely to be imported from a shared
3832 library as it is to be defined in the executable itself. We
3833 assume executables will get global functions defined locally,
3834 whereas shared libraries will have them potentially overridden,
3835 so we only inline PLTs when compiling for shared libraries.
3837 In order to mark a function as local to a shared library, any
3838 non-default visibility attribute suffices. Unfortunately,
3839 there's no simple way to tag a function declaration as ``in a
3840 different module'', which we could then use to trigger PLT
3841 inlining on executables. There's -minline-plt, but it affects
3842 all external functions, so one would have to also mark function
3843 declarations available in the same module with non-default
3844 visibility, which is advantageous in itself. */
3845 if (GET_CODE (addr) == SYMBOL_REF
3846 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3850 dest = gen_reg_rtx (SImode);
3852 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3853 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3855 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3856 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3858 crtl->uses_pic_offset_table = TRUE;
3861 else if (GET_CODE (addr) == SYMBOL_REF)
3863 /* These are always either local, or handled through a local
3866 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3867 operands[2], picreg, lr);
3869 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3873 else if (! ldd_address_operand (addr, Pmode))
3874 addr = force_reg (Pmode, addr);
3876 picreg = gen_reg_rtx (DImode);
3877 emit_insn (gen_movdi_ldd (picreg, addr));
3879 if (sibcall && ret_value)
3880 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3882 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3884 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3886 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3890 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3891 process these separately from any offsets, such that we add any
3892 offsets to the function descriptor (the actual pointer), not to the
3893 function address. */
3896 frv_function_symbol_referenced_p (rtx x)
3902 if (GET_CODE (x) == SYMBOL_REF)
3903 return SYMBOL_REF_FUNCTION_P (x);
3905 length = GET_RTX_LENGTH (GET_CODE (x));
3906 format = GET_RTX_FORMAT (GET_CODE (x));
3908 for (j = 0; j < length; ++j)
3913 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3919 if (XVEC (x, j) != 0)
3922 for (k = 0; k < XVECLEN (x, j); ++k)
3923 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3929 /* Nothing to do. */
3937 /* Return true if the memory operand is one that can be conditionally
3941 condexec_memory_operand (rtx op, enum machine_mode mode)
3943 enum machine_mode op_mode = GET_MODE (op);
3946 if (mode != VOIDmode && op_mode != mode)
3961 if (GET_CODE (op) != MEM)
3964 addr = XEXP (op, 0);
3965 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3968 /* Return true if the bare return instruction can be used outside of the
3969 epilog code. For frv, we only do it if there was no stack allocation. */
3972 direct_return_p (void)
3976 if (!reload_completed)
3979 info = frv_stack_info ();
3980 return (info->total_size == 0);
3985 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3987 if (GET_CODE (src) == SYMBOL_REF)
3989 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3991 src = frv_legitimize_tls_address (src, model);
3997 if (frv_emit_movsi (dest, src))
4006 if (!reload_in_progress
4007 && !reload_completed
4008 && !register_operand (dest, mode)
4009 && !reg_or_0_operand (src, mode))
4010 src = copy_to_mode_reg (mode, src);
4017 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4020 /* Emit code to handle a MOVSI, adding in the small data register or pic
4021 register if needed to load up addresses. Return TRUE if the appropriate
4022 instructions are emitted. */
4025 frv_emit_movsi (rtx dest, rtx src)
4027 int base_regno = -1;
4030 struct frv_unspec old_unspec;
4032 if (!reload_in_progress
4033 && !reload_completed
4034 && !register_operand (dest, SImode)
4035 && (!reg_or_0_operand (src, SImode)
4036 /* Virtual registers will almost always be replaced by an
4037 add instruction, so expose this to CSE by copying to
4038 an intermediate register. */
4039 || (GET_CODE (src) == REG
4040 && IN_RANGE_P (REGNO (src),
4041 FIRST_VIRTUAL_REGISTER,
4042 LAST_VIRTUAL_POINTER_REGISTER))))
4044 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4048 /* Explicitly add in the PIC or small data register if needed. */
4049 switch (GET_CODE (src))
4058 /* Using GPREL12, we use a single GOT entry for all symbols
4059 in read-only sections, but trade sequences such as:
4061 sethi #gothi(label), gr#
4062 setlo #gotlo(label), gr#
4067 ld @(gr15,#got12(_gp)), gr#
4068 sethi #gprelhi(label), gr##
4069 setlo #gprello(label), gr##
4072 We may often be able to share gr# for multiple
4073 computations of GPREL addresses, and we may often fold
4074 the final add into the pair of registers of a load or
4075 store instruction, so it's often profitable. Even when
4076 optimizing for size, we're trading a GOT entry for an
4077 additional instruction, which trades GOT space
4078 (read-write) for code size (read-only, shareable), as
4079 long as the symbol is not used in more than two different
4082 With -fpie/-fpic, we'd be trading a single load for a
4083 sequence of 4 instructions, because the offset of the
4084 label can't be assumed to be addressable with 12 bits, so
4085 we don't do this. */
4086 if (TARGET_GPREL_RO)
4087 unspec = R_FRV_GPREL12;
4089 unspec = R_FRV_GOT12;
4092 base_regno = PIC_REGNO;
4097 if (frv_const_unspec_p (src, &old_unspec))
4100 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4103 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4104 emit_move_insn (dest, src);
4109 sym = XEXP (sym, 0);
4110 if (GET_CODE (sym) == PLUS
4111 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4112 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4113 sym = XEXP (sym, 0);
4114 if (GET_CODE (sym) == SYMBOL_REF)
4116 else if (GET_CODE (sym) == LABEL_REF)
4119 goto handle_whatever;
4127 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4131 src = frv_legitimize_tls_address (src, model);
4132 emit_move_insn (dest, src);
4136 if (SYMBOL_REF_FUNCTION_P (sym))
4138 if (frv_local_funcdesc_p (sym))
4139 unspec = R_FRV_FUNCDESC_GOTOFF12;
4141 unspec = R_FRV_FUNCDESC_GOT12;
4145 if (CONSTANT_POOL_ADDRESS_P (sym))
4146 switch (GET_CODE (get_pool_constant (sym)))
4153 unspec = R_FRV_GOTOFF12;
4158 if (TARGET_GPREL_RO)
4159 unspec = R_FRV_GPREL12;
4161 unspec = R_FRV_GOT12;
4164 else if (SYMBOL_REF_LOCAL_P (sym)
4165 && !SYMBOL_REF_EXTERNAL_P (sym)
4166 && SYMBOL_REF_DECL (sym)
4167 && (!DECL_P (SYMBOL_REF_DECL (sym))
4168 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4170 tree decl = SYMBOL_REF_DECL (sym);
4171 tree init = TREE_CODE (decl) == VAR_DECL
4172 ? DECL_INITIAL (decl)
4173 : TREE_CODE (decl) == CONSTRUCTOR
4176 bool named_section, readonly;
4178 if (init && init != error_mark_node)
4179 reloc = compute_reloc_for_constant (init);
4181 named_section = TREE_CODE (decl) == VAR_DECL
4182 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4183 readonly = decl_readonly_section (decl, reloc);
4186 unspec = R_FRV_GOT12;
4188 unspec = R_FRV_GOTOFF12;
4189 else if (readonly && TARGET_GPREL_RO)
4190 unspec = R_FRV_GPREL12;
4192 unspec = R_FRV_GOT12;
4195 unspec = R_FRV_GOT12;
4199 else if (SYMBOL_REF_SMALL_P (sym))
4200 base_regno = SDA_BASE_REG;
4203 base_regno = PIC_REGNO;
4208 if (base_regno >= 0)
4210 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4211 emit_insn (gen_symGOTOFF2reg (dest, src,
4212 gen_rtx_REG (Pmode, base_regno),
4213 GEN_INT (R_FRV_GPREL12)));
4215 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4216 gen_rtx_REG (Pmode, base_regno),
4217 GEN_INT (R_FRV_GPREL12)));
4218 if (base_regno == PIC_REGNO)
4219 crtl->uses_pic_offset_table = TRUE;
4227 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4228 new uses of it once reload has begun. */
4229 gcc_assert (!reload_in_progress && !reload_completed);
4233 case R_FRV_GOTOFF12:
4234 if (!frv_small_data_reloc_p (sym, unspec))
4235 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4238 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4241 if (!frv_small_data_reloc_p (sym, unspec))
4242 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4245 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4247 case R_FRV_FUNCDESC_GOTOFF12:
4249 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4252 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4256 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4259 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4263 crtl->uses_pic_offset_table = TRUE;
4272 /* Return a string to output a single word move. */
4275 output_move_single (rtx operands[], rtx insn)
4277 rtx dest = operands[0];
4278 rtx src = operands[1];
4280 if (GET_CODE (dest) == REG)
4282 int dest_regno = REGNO (dest);
4283 enum machine_mode mode = GET_MODE (dest);
4285 if (GPR_P (dest_regno))
4287 if (GET_CODE (src) == REG)
4289 /* gpr <- some sort of register */
4290 int src_regno = REGNO (src);
4292 if (GPR_P (src_regno))
4293 return "mov %1, %0";
4295 else if (FPR_P (src_regno))
4296 return "movfg %1, %0";
4298 else if (SPR_P (src_regno))
4299 return "movsg %1, %0";
4302 else if (GET_CODE (src) == MEM)
4311 return "ldsb%I1%U1 %M1,%0";
4314 return "ldsh%I1%U1 %M1,%0";
4318 return "ld%I1%U1 %M1, %0";
4322 else if (GET_CODE (src) == CONST_INT
4323 || GET_CODE (src) == CONST_DOUBLE)
4325 /* gpr <- integer/floating constant */
4326 HOST_WIDE_INT value;
4328 if (GET_CODE (src) == CONST_INT)
4329 value = INTVAL (src);
4331 else if (mode == SFmode)
4336 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4337 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4342 value = CONST_DOUBLE_LOW (src);
4344 if (IN_RANGE_P (value, -32768, 32767))
4345 return "setlos %1, %0";
4350 else if (GET_CODE (src) == SYMBOL_REF
4351 || GET_CODE (src) == LABEL_REF
4352 || GET_CODE (src) == CONST)
4358 else if (FPR_P (dest_regno))
4360 if (GET_CODE (src) == REG)
4362 /* fpr <- some sort of register */
4363 int src_regno = REGNO (src);
4365 if (GPR_P (src_regno))
4366 return "movgf %1, %0";
4368 else if (FPR_P (src_regno))
4370 if (TARGET_HARD_FLOAT)
4371 return "fmovs %1, %0";
4373 return "mor %1, %1, %0";
4377 else if (GET_CODE (src) == MEM)
4386 return "ldbf%I1%U1 %M1,%0";
4389 return "ldhf%I1%U1 %M1,%0";
4393 return "ldf%I1%U1 %M1, %0";
4397 else if (ZERO_P (src))
4398 return "movgf %., %0";
4401 else if (SPR_P (dest_regno))
4403 if (GET_CODE (src) == REG)
4405 /* spr <- some sort of register */
4406 int src_regno = REGNO (src);
4408 if (GPR_P (src_regno))
4409 return "movgs %1, %0";
4411 else if (ZERO_P (src))
4412 return "movgs %., %0";
4416 else if (GET_CODE (dest) == MEM)
4418 if (GET_CODE (src) == REG)
4420 int src_regno = REGNO (src);
4421 enum machine_mode mode = GET_MODE (dest);
4423 if (GPR_P (src_regno))
4431 return "stb%I0%U0 %1, %M0";
4434 return "sth%I0%U0 %1, %M0";
4438 return "st%I0%U0 %1, %M0";
4442 else if (FPR_P (src_regno))
4450 return "stbf%I0%U0 %1, %M0";
4453 return "sthf%I0%U0 %1, %M0";
4457 return "stf%I0%U0 %1, %M0";
4462 else if (ZERO_P (src))
4464 switch (GET_MODE (dest))
4470 return "stb%I0%U0 %., %M0";
4473 return "sth%I0%U0 %., %M0";
4477 return "st%I0%U0 %., %M0";
4482 fatal_insn ("bad output_move_single operand", insn);
4487 /* Return a string to output a double word move. */
4490 output_move_double (rtx operands[], rtx insn)
4492 rtx dest = operands[0];
4493 rtx src = operands[1];
4494 enum machine_mode mode = GET_MODE (dest);
4496 if (GET_CODE (dest) == REG)
4498 int dest_regno = REGNO (dest);
4500 if (GPR_P (dest_regno))
4502 if (GET_CODE (src) == REG)
4504 /* gpr <- some sort of register */
4505 int src_regno = REGNO (src);
4507 if (GPR_P (src_regno))
4510 else if (FPR_P (src_regno))
4512 if (((dest_regno - GPR_FIRST) & 1) == 0
4513 && ((src_regno - FPR_FIRST) & 1) == 0)
4514 return "movfgd %1, %0";
4520 else if (GET_CODE (src) == MEM)
4523 if (dbl_memory_one_insn_operand (src, mode))
4524 return "ldd%I1%U1 %M1, %0";
4529 else if (GET_CODE (src) == CONST_INT
4530 || GET_CODE (src) == CONST_DOUBLE)
4534 else if (FPR_P (dest_regno))
4536 if (GET_CODE (src) == REG)
4538 /* fpr <- some sort of register */
4539 int src_regno = REGNO (src);
4541 if (GPR_P (src_regno))
4543 if (((dest_regno - FPR_FIRST) & 1) == 0
4544 && ((src_regno - GPR_FIRST) & 1) == 0)
4545 return "movgfd %1, %0";
4550 else if (FPR_P (src_regno))
4553 && ((dest_regno - FPR_FIRST) & 1) == 0
4554 && ((src_regno - FPR_FIRST) & 1) == 0)
4555 return "fmovd %1, %0";
4561 else if (GET_CODE (src) == MEM)
4564 if (dbl_memory_one_insn_operand (src, mode))
4565 return "lddf%I1%U1 %M1, %0";
4570 else if (ZERO_P (src))
4575 else if (GET_CODE (dest) == MEM)
4577 if (GET_CODE (src) == REG)
4579 int src_regno = REGNO (src);
4581 if (GPR_P (src_regno))
4583 if (((src_regno - GPR_FIRST) & 1) == 0
4584 && dbl_memory_one_insn_operand (dest, mode))
4585 return "std%I0%U0 %1, %M0";
4590 if (FPR_P (src_regno))
4592 if (((src_regno - FPR_FIRST) & 1) == 0
4593 && dbl_memory_one_insn_operand (dest, mode))
4594 return "stdf%I0%U0 %1, %M0";
4600 else if (ZERO_P (src))
4602 if (dbl_memory_one_insn_operand (dest, mode))
4603 return "std%I0%U0 %., %M0";
4609 fatal_insn ("bad output_move_double operand", insn);
4614 /* Return a string to output a single word conditional move.
4615 Operand0 -- EQ/NE of ccr register and 0
4616 Operand1 -- CCR register
4617 Operand2 -- destination
4618 Operand3 -- source */
4621 output_condmove_single (rtx operands[], rtx insn)
4623 rtx dest = operands[2];
4624 rtx src = operands[3];
4626 if (GET_CODE (dest) == REG)
4628 int dest_regno = REGNO (dest);
4629 enum machine_mode mode = GET_MODE (dest);
4631 if (GPR_P (dest_regno))
4633 if (GET_CODE (src) == REG)
4635 /* gpr <- some sort of register */
4636 int src_regno = REGNO (src);
4638 if (GPR_P (src_regno))
4639 return "cmov %z3, %2, %1, %e0";
4641 else if (FPR_P (src_regno))
4642 return "cmovfg %3, %2, %1, %e0";
4645 else if (GET_CODE (src) == MEM)
4654 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4657 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4661 return "cld%I3%U3 %M3, %2, %1, %e0";
4665 else if (ZERO_P (src))
4666 return "cmov %., %2, %1, %e0";
4669 else if (FPR_P (dest_regno))
4671 if (GET_CODE (src) == REG)
4673 /* fpr <- some sort of register */
4674 int src_regno = REGNO (src);
4676 if (GPR_P (src_regno))
4677 return "cmovgf %3, %2, %1, %e0";
4679 else if (FPR_P (src_regno))
4681 if (TARGET_HARD_FLOAT)
4682 return "cfmovs %3,%2,%1,%e0";
4684 return "cmor %3, %3, %2, %1, %e0";
4688 else if (GET_CODE (src) == MEM)
4691 if (mode == SImode || mode == SFmode)
4692 return "cldf%I3%U3 %M3, %2, %1, %e0";
4695 else if (ZERO_P (src))
4696 return "cmovgf %., %2, %1, %e0";
4700 else if (GET_CODE (dest) == MEM)
4702 if (GET_CODE (src) == REG)
4704 int src_regno = REGNO (src);
4705 enum machine_mode mode = GET_MODE (dest);
4707 if (GPR_P (src_regno))
4715 return "cstb%I2%U2 %3, %M2, %1, %e0";
4718 return "csth%I2%U2 %3, %M2, %1, %e0";
4722 return "cst%I2%U2 %3, %M2, %1, %e0";
4726 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4727 return "cstf%I2%U2 %3, %M2, %1, %e0";
4730 else if (ZERO_P (src))
4732 enum machine_mode mode = GET_MODE (dest);
4739 return "cstb%I2%U2 %., %M2, %1, %e0";
4742 return "csth%I2%U2 %., %M2, %1, %e0";
4746 return "cst%I2%U2 %., %M2, %1, %e0";
4751 fatal_insn ("bad output_condmove_single operand", insn);
4756 /* Emit the appropriate code to do a comparison, returning the register the
4757 comparison was done it. */
4760 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4762 enum machine_mode cc_mode;
4765 /* Floating point doesn't have comparison against a constant. */
4766 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4767 op1 = force_reg (GET_MODE (op0), op1);
4769 /* Possibly disable using anything but a fixed register in order to work
4770 around cse moving comparisons past function calls. */
4771 cc_mode = SELECT_CC_MODE (test, op0, op1);
4772 cc_reg = ((TARGET_ALLOC_CC)
4773 ? gen_reg_rtx (cc_mode)
4774 : gen_rtx_REG (cc_mode,
4775 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4777 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4778 gen_rtx_COMPARE (cc_mode, op0, op1)));
4784 /* Emit code for a conditional branch.
4785 XXX: I originally wanted to add a clobber of a CCR register to use in
4786 conditional execution, but that confuses the rest of the compiler. */
4789 frv_emit_cond_branch (rtx operands[])
4794 enum rtx_code test = GET_CODE (operands[0]);
4795 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4796 enum machine_mode cc_mode = GET_MODE (cc_reg);
4798 /* Branches generate:
4800 (if_then_else (<test>, <cc_reg>, (const_int 0))
4801 (label_ref <branch_label>)
4803 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4804 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4805 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4806 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4811 /* Emit code to set a gpr to 1/0 based on a comparison. */
4814 frv_emit_scc (rtx operands[])
4820 enum rtx_code test = GET_CODE (operands[1]);
4821 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4823 /* SCC instructions generate:
4824 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4825 (clobber (<ccr_reg>))]) */
4826 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4827 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4829 cr_reg = ((TARGET_ALLOC_CC)
4830 ? gen_reg_rtx (CC_CCRmode)
4831 : gen_rtx_REG (CC_CCRmode,
4832 ((GET_MODE (cc_reg) == CC_FPmode)
4836 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4837 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4842 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4843 the separate insns. */
4846 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4852 /* Set the appropriate CCR bit. */
4853 emit_insn (gen_rtx_SET (VOIDmode,
4855 gen_rtx_fmt_ee (GET_CODE (test),
4860 /* Move the value into the destination. */
4861 emit_move_insn (dest, GEN_INT (value));
4863 /* Move 0 into the destination if the test failed */
4864 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4865 gen_rtx_EQ (GET_MODE (cr_reg),
4868 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4870 /* Finish up, return sequence. */
4877 /* Emit the code for a conditional move, return TRUE if we could do the
4881 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4888 enum rtx_code test = GET_CODE (test_rtx);
4889 rtx cc_reg = frv_emit_comparison (test,
4890 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4891 enum machine_mode cc_mode = GET_MODE (cc_reg);
4893 /* Conditional move instructions generate:
4894 (parallel [(set <target>
4895 (if_then_else (<test> <cc_reg> (const_int 0))
4898 (clobber (<ccr_reg>))]) */
4900 /* Handle various cases of conditional move involving two constants. */
4901 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4903 HOST_WIDE_INT value1 = INTVAL (src1);
4904 HOST_WIDE_INT value2 = INTVAL (src2);
4906 /* Having 0 as one of the constants can be done by loading the other
4907 constant, and optionally moving in gr0. */
4908 if (value1 == 0 || value2 == 0)
4911 /* If the first value is within an addi range and also the difference
4912 between the two fits in an addi's range, load up the difference, then
4913 conditionally move in 0, and then unconditionally add the first
4915 else if (IN_RANGE_P (value1, -2048, 2047)
4916 && IN_RANGE_P (value2 - value1, -2048, 2047))
4919 /* If neither condition holds, just force the constant into a
4923 src1 = force_reg (GET_MODE (dest), src1);
4924 src2 = force_reg (GET_MODE (dest), src2);
4928 /* If one value is a register, insure the other value is either 0 or a
4932 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4933 src1 = force_reg (GET_MODE (dest), src1);
4935 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4936 src2 = force_reg (GET_MODE (dest), src2);
4939 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4940 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4942 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4944 cr_reg = ((TARGET_ALLOC_CC)
4945 ? gen_reg_rtx (CC_CCRmode)
4946 : gen_rtx_REG (CC_CCRmode,
4947 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4949 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4950 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4955 /* Split a conditional move into constituent parts, returning a SEQUENCE
4956 containing all of the insns. */
4959 frv_split_cond_move (rtx operands[])
4961 rtx dest = operands[0];
4962 rtx test = operands[1];
4963 rtx cc_reg = operands[2];
4964 rtx src1 = operands[3];
4965 rtx src2 = operands[4];
4966 rtx cr_reg = operands[5];
4968 enum machine_mode cr_mode = GET_MODE (cr_reg);
4972 /* Set the appropriate CCR bit. */
4973 emit_insn (gen_rtx_SET (VOIDmode,
4975 gen_rtx_fmt_ee (GET_CODE (test),
4980 /* Handle various cases of conditional move involving two constants. */
4981 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4983 HOST_WIDE_INT value1 = INTVAL (src1);
4984 HOST_WIDE_INT value2 = INTVAL (src2);
4986 /* Having 0 as one of the constants can be done by loading the other
4987 constant, and optionally moving in gr0. */
4990 emit_move_insn (dest, src2);
4991 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4992 gen_rtx_NE (cr_mode, cr_reg,
4994 gen_rtx_SET (VOIDmode, dest, src1)));
4997 else if (value2 == 0)
4999 emit_move_insn (dest, src1);
5000 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5001 gen_rtx_EQ (cr_mode, cr_reg,
5003 gen_rtx_SET (VOIDmode, dest, src2)));
5006 /* If the first value is within an addi range and also the difference
5007 between the two fits in an addi's range, load up the difference, then
5008 conditionally move in 0, and then unconditionally add the first
5010 else if (IN_RANGE_P (value1, -2048, 2047)
5011 && IN_RANGE_P (value2 - value1, -2048, 2047))
5013 rtx dest_si = ((GET_MODE (dest) == SImode)
5015 : gen_rtx_SUBREG (SImode, dest, 0));
5017 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5018 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5019 gen_rtx_NE (cr_mode, cr_reg,
5021 gen_rtx_SET (VOIDmode, dest_si,
5023 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5031 /* Emit the conditional move for the test being true if needed. */
5032 if (! rtx_equal_p (dest, src1))
5033 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5034 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5035 gen_rtx_SET (VOIDmode, dest, src1)));
5037 /* Emit the conditional move for the test being false if needed. */
5038 if (! rtx_equal_p (dest, src2))
5039 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5040 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5041 gen_rtx_SET (VOIDmode, dest, src2)));
5044 /* Finish up, return sequence. */
5051 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5052 memory location that is not known to be dword-aligned. */
5054 frv_split_double_load (rtx dest, rtx source)
5056 int regno = REGNO (dest);
5057 rtx dest1 = gen_highpart (SImode, dest);
5058 rtx dest2 = gen_lowpart (SImode, dest);
5059 rtx address = XEXP (source, 0);
5061 /* If the address is pre-modified, load the lower-numbered register
5062 first, then load the other register using an integer offset from
5063 the modified base register. This order should always be safe,
5064 since the pre-modification cannot affect the same registers as the
5067 The situation for other loads is more complicated. Loading one
5068 of the registers could affect the value of ADDRESS, so we must
5069 be careful which order we do them in. */
5070 if (GET_CODE (address) == PRE_MODIFY
5071 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5073 /* It is safe to load the lower-numbered register first. */
5074 emit_move_insn (dest1, change_address (source, SImode, NULL));
5075 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5079 /* ADDRESS is not pre-modified and the address depends on the
5080 lower-numbered register. Load the higher-numbered register
5082 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5083 emit_move_insn (dest1, change_address (source, SImode, NULL));
5087 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5088 and SOURCE is either a double register or the constant zero. */
5090 frv_split_double_store (rtx dest, rtx source)
5092 rtx dest1 = change_address (dest, SImode, NULL);
5093 rtx dest2 = frv_index_memory (dest, SImode, 1);
5094 if (ZERO_P (source))
5096 emit_move_insn (dest1, CONST0_RTX (SImode));
5097 emit_move_insn (dest2, CONST0_RTX (SImode));
5101 emit_move_insn (dest1, gen_highpart (SImode, source));
5102 emit_move_insn (dest2, gen_lowpart (SImode, source));
5107 /* Split a min/max operation returning a SEQUENCE containing all of the
5111 frv_split_minmax (rtx operands[])
5113 rtx dest = operands[0];
5114 rtx minmax = operands[1];
5115 rtx src1 = operands[2];
5116 rtx src2 = operands[3];
5117 rtx cc_reg = operands[4];
5118 rtx cr_reg = operands[5];
5120 enum rtx_code test_code;
5121 enum machine_mode cr_mode = GET_MODE (cr_reg);
5125 /* Figure out which test to use. */
5126 switch (GET_CODE (minmax))
5131 case SMIN: test_code = LT; break;
5132 case SMAX: test_code = GT; break;
5133 case UMIN: test_code = LTU; break;
5134 case UMAX: test_code = GTU; break;
5137 /* Issue the compare instruction. */
5138 emit_insn (gen_rtx_SET (VOIDmode,
5140 gen_rtx_COMPARE (GET_MODE (cc_reg),
5143 /* Set the appropriate CCR bit. */
5144 emit_insn (gen_rtx_SET (VOIDmode,
5146 gen_rtx_fmt_ee (test_code,
5151 /* If are taking the min/max of a nonzero constant, load that first, and
5152 then do a conditional move of the other value. */
5153 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5155 gcc_assert (!rtx_equal_p (dest, src1));
5157 emit_move_insn (dest, src2);
5158 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5159 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5160 gen_rtx_SET (VOIDmode, dest, src1)));
5163 /* Otherwise, do each half of the move. */
5166 /* Emit the conditional move for the test being true if needed. */
5167 if (! rtx_equal_p (dest, src1))
5168 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5169 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5170 gen_rtx_SET (VOIDmode, dest, src1)));
5172 /* Emit the conditional move for the test being false if needed. */
5173 if (! rtx_equal_p (dest, src2))
5174 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5175 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5176 gen_rtx_SET (VOIDmode, dest, src2)));
5179 /* Finish up, return sequence. */
5186 /* Split an integer abs operation returning a SEQUENCE containing all of the
5190 frv_split_abs (rtx operands[])
5192 rtx dest = operands[0];
5193 rtx src = operands[1];
5194 rtx cc_reg = operands[2];
5195 rtx cr_reg = operands[3];
5200 /* Issue the compare < 0 instruction. */
5201 emit_insn (gen_rtx_SET (VOIDmode,
5203 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5205 /* Set the appropriate CCR bit. */
5206 emit_insn (gen_rtx_SET (VOIDmode,
5208 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5210 /* Emit the conditional negate if the value is negative. */
5211 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5212 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5213 gen_negsi2 (dest, src)));
5215 /* Emit the conditional move for the test being false if needed. */
5216 if (! rtx_equal_p (dest, src))
5217 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5218 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5219 gen_rtx_SET (VOIDmode, dest, src)));
5221 /* Finish up, return sequence. */
5228 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5229 register used in an insn. */
5232 frv_clear_registers_used (rtx *ptr, void *data)
5234 if (GET_CODE (*ptr) == REG)
5236 int regno = REGNO (*ptr);
5237 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5239 if (regno < FIRST_PSEUDO_REGISTER)
5241 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5243 while (regno < reg_max)
5245 CLEAR_HARD_REG_BIT (*p_regs, regno);
5255 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5257 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5258 initialize the static storage. */
5260 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5262 frv_ifcvt.added_insns_list = NULL_RTX;
5263 frv_ifcvt.cur_scratch_regs = 0;
5264 frv_ifcvt.num_nested_cond_exec = 0;
5265 frv_ifcvt.cr_reg = NULL_RTX;
5266 frv_ifcvt.nested_cc_reg = NULL_RTX;
5267 frv_ifcvt.extra_int_cr = NULL_RTX;
5268 frv_ifcvt.extra_fp_cr = NULL_RTX;
5269 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5273 /* Internal function to add a potential insn to the list of insns to be inserted
5274 if the conditional execution conversion is successful. */
5277 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5279 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5281 link->jump = before_p; /* Mark to add this before or after insn. */
5282 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5283 frv_ifcvt.added_insns_list);
5285 if (TARGET_DEBUG_COND_EXEC)
5288 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5289 (before_p) ? "before" : "after",
5290 (int)INSN_UID (insn));
5292 debug_rtx (pattern);
5297 /* A C expression to modify the code described by the conditional if
5298 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5299 FALSE_EXPR for converting if-then and if-then-else code to conditional
5300 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5301 tests cannot be converted. */
5304 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5306 basic_block test_bb = ce_info->test_bb; /* test basic block */
5307 basic_block then_bb = ce_info->then_bb; /* THEN */
5308 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5309 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5310 rtx true_expr = *p_true;
5314 enum machine_mode mode = GET_MODE (true_expr);
5318 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5320 rtx sub_cond_exec_reg;
5322 enum rtx_code code_true;
5323 enum rtx_code code_false;
5324 enum reg_class cc_class;
5325 enum reg_class cr_class;
5328 reg_set_iterator rsi;
5330 /* Make sure we are only dealing with hard registers. Also honor the
5331 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5333 if (!reload_completed || !TARGET_COND_EXEC
5334 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5337 /* Figure out which registers we can allocate for our own purposes. Only
5338 consider registers that are not preserved across function calls and are
5339 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5340 if we did not need to use them in reloading other registers. */
5341 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5342 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5343 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5344 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5345 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5347 /* If this is a nested IF, we need to discover whether the CC registers that
5348 are set/used inside of the block are used anywhere else. If not, we can
5349 change them to be the CC register that is paired with the CR register that
5350 controls the outermost IF block. */
5351 if (ce_info->pass > 1)
5353 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5354 for (j = CC_FIRST; j <= CC_LAST; j++)
5355 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5357 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5361 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5365 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5368 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5372 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5373 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5375 frv_ifcvt.added_insns_list = NULL_RTX;
5376 frv_ifcvt.cur_scratch_regs = 0;
5378 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5379 * sizeof (basic_block));
5385 /* Remove anything live at the beginning of the join block from being
5386 available for allocation. */
5387 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5389 if (regno < FIRST_PSEUDO_REGISTER)
5390 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5394 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5396 if (ce_info->num_multiple_test_blocks)
5398 basic_block multiple_test_bb = ce_info->last_test_bb;
5400 while (multiple_test_bb != test_bb)
5402 bb[num_bb++] = multiple_test_bb;
5403 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5407 /* Add in the THEN and ELSE blocks to be scanned. */
5408 bb[num_bb++] = then_bb;
5410 bb[num_bb++] = else_bb;
5412 sub_cond_exec_reg = NULL_RTX;
5413 frv_ifcvt.num_nested_cond_exec = 0;
5415 /* Scan all of the blocks for registers that must not be allocated. */
5416 for (j = 0; j < num_bb; j++)
5418 rtx last_insn = BB_END (bb[j]);
5419 rtx insn = BB_HEAD (bb[j]);
5423 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5424 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5426 (int) INSN_UID (BB_HEAD (bb[j])),
5427 (int) INSN_UID (BB_END (bb[j])));
5429 /* Anything live at the beginning of the block is obviously unavailable
5431 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5433 if (regno < FIRST_PSEUDO_REGISTER)
5434 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5437 /* Loop through the insns in the block. */
5440 /* Mark any new registers that are created as being unavailable for
5441 allocation. Also see if the CC register used in nested IFs can be
5447 int skip_nested_if = FALSE;
5449 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5450 (void *)&tmp_reg->regs);
5452 pattern = PATTERN (insn);
5453 if (GET_CODE (pattern) == COND_EXEC)
5455 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5457 if (reg != sub_cond_exec_reg)
5459 sub_cond_exec_reg = reg;
5460 frv_ifcvt.num_nested_cond_exec++;
5464 set = single_set_pattern (pattern);
5467 rtx dest = SET_DEST (set);
5468 rtx src = SET_SRC (set);
5470 if (GET_CODE (dest) == REG)
5472 int regno = REGNO (dest);
5473 enum rtx_code src_code = GET_CODE (src);
5475 if (CC_P (regno) && src_code == COMPARE)
5476 skip_nested_if = TRUE;
5478 else if (CR_P (regno)
5479 && (src_code == IF_THEN_ELSE
5480 || COMPARISON_P (src)))
5481 skip_nested_if = TRUE;
5485 if (! skip_nested_if)
5486 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5487 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5490 if (insn == last_insn)
5493 insn = NEXT_INSN (insn);
5497 /* If this is a nested if, rewrite the CC registers that are available to
5498 include the ones that can be rewritten, to increase the chance of being
5499 able to allocate a paired CC/CR register combination. */
5500 if (ce_info->pass > 1)
5502 for (j = CC_FIRST; j <= CC_LAST; j++)
5503 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5504 SET_HARD_REG_BIT (tmp_reg->regs, j);
5506 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5512 fprintf (dump_file, "Available GPRs: ");
5514 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5515 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5517 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5518 if (++num_gprs > GPR_TEMP_NUM+2)
5522 fprintf (dump_file, "%s\nAvailable CRs: ",
5523 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5525 for (j = CR_FIRST; j <= CR_LAST; j++)
5526 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5527 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5529 fputs ("\n", dump_file);
5531 if (ce_info->pass > 1)
5533 fprintf (dump_file, "Modifiable CCs: ");
5534 for (j = CC_FIRST; j <= CC_LAST; j++)
5535 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5536 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5538 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5539 frv_ifcvt.num_nested_cond_exec);
5543 /* Allocate the appropriate temporary condition code register. Try to
5544 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5545 that conditional cmp's can be done. */
5546 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5548 cr_class = ICR_REGS;
5549 cc_class = ICC_REGS;
5550 cc_first = ICC_FIRST;
5553 else if (mode == CC_FPmode)
5555 cr_class = FCR_REGS;
5556 cc_class = FCC_REGS;
5557 cc_first = FCC_FIRST;
5562 cc_first = cc_last = 0;
5563 cr_class = cc_class = NO_REGS;
5566 cc = XEXP (true_expr, 0);
5567 nested_cc = cr = NULL_RTX;
5568 if (cc_class != NO_REGS)
5570 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5571 so we can execute a csubcc/caddcc/cfcmps instruction. */
5574 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5576 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5578 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5579 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5581 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5582 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5585 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5586 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5596 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5603 "Will use %s for conditional execution, %s for nested comparisons\n",
5604 reg_names[ REGNO (cr)],
5605 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5607 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5608 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5609 bit being true. We don't do this for floating point, because of NaNs. */
5610 code = GET_CODE (true_expr);
5611 if (GET_MODE (cc) != CC_FPmode)
5613 code = reverse_condition (code);
5623 check_insn = gen_rtx_SET (VOIDmode, cr,
5624 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5626 /* Record the check insn to be inserted later. */
5627 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5629 /* Update the tests. */
5630 frv_ifcvt.cr_reg = cr;
5631 frv_ifcvt.nested_cc_reg = nested_cc;
5632 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5633 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5636 /* Fail, don't do this conditional execution. */
5639 *p_false = NULL_RTX;
5641 fprintf (dump_file, "Disabling this conditional execution.\n");
5647 /* A C expression to modify the code described by the conditional if
5648 information CE_INFO, for the basic block BB, possibly updating the tests in
5649 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5650 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5651 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5653 /* p_true and p_false are given expressions of the form:
5655 (and (eq:CC_CCR (reg:CC_CCR)
5661 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5666 rtx old_true = XEXP (*p_true, 0);
5667 rtx old_false = XEXP (*p_false, 0);
5668 rtx true_expr = XEXP (*p_true, 1);
5669 rtx false_expr = XEXP (*p_false, 1);
5672 rtx cr = XEXP (old_true, 0);
5674 rtx new_cr = NULL_RTX;
5675 rtx *p_new_cr = (rtx *)0;
5679 enum reg_class cr_class;
5680 enum machine_mode mode = GET_MODE (true_expr);
5681 rtx (*logical_func)(rtx, rtx, rtx);
5683 if (TARGET_DEBUG_COND_EXEC)
5686 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5687 ce_info->and_and_p ? "&&" : "||");
5689 debug_rtx (*p_true);
5691 fputs ("\nfalse insn:\n", stderr);
5692 debug_rtx (*p_false);
5695 if (!TARGET_MULTI_CE)
5698 if (GET_CODE (cr) != REG)
5701 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5703 cr_class = ICR_REGS;
5704 p_new_cr = &frv_ifcvt.extra_int_cr;
5706 else if (mode == CC_FPmode)
5708 cr_class = FCR_REGS;
5709 p_new_cr = &frv_ifcvt.extra_fp_cr;
5714 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5715 more &&/|| tests. */
5719 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5720 CC_CCRmode, TRUE, TRUE);
5725 if (ce_info->and_and_p)
5727 old_test = old_false;
5728 test_expr = true_expr;
5729 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5730 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5731 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5735 old_test = old_false;
5736 test_expr = false_expr;
5737 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5738 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5739 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5742 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5743 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5745 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5747 /* Now add the conditional check insn. */
5748 cc = XEXP (test_expr, 0);
5749 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5750 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5752 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5754 /* Add the new check insn to the list of check insns that need to be
5756 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5758 if (TARGET_DEBUG_COND_EXEC)
5760 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5763 debug_rtx (*p_true);
5765 fputs ("\nfalse insn:\n", stderr);
5766 debug_rtx (*p_false);
5772 *p_true = *p_false = NULL_RTX;
5774 /* If we allocated a CR register, release it. */
5777 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5778 *p_new_cr = NULL_RTX;
5781 if (TARGET_DEBUG_COND_EXEC)
5782 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5788 /* Return a register which will be loaded with a value if an IF block is
5789 converted to conditional execution. This is used to rewrite instructions
5790 that use constants to ones that just use registers. */
5793 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5795 int num_alloc = frv_ifcvt.cur_scratch_regs;
5799 /* We know gr0 == 0, so replace any errant uses. */
5800 if (value == const0_rtx)
5801 return gen_rtx_REG (SImode, GPR_FIRST);
5803 /* First search all registers currently loaded to see if we have an
5804 applicable constant. */
5805 if (CONSTANT_P (value)
5806 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5808 for (i = 0; i < num_alloc; i++)
5810 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5811 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5815 /* Have we exhausted the number of registers available? */
5816 if (num_alloc >= GPR_TEMP_NUM)
5819 fprintf (dump_file, "Too many temporary registers allocated\n");
5824 /* Allocate the new register. */
5825 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5829 fputs ("Could not find a scratch register\n", dump_file);
5834 frv_ifcvt.cur_scratch_regs++;
5835 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5839 if (GET_CODE (value) == CONST_INT)
5840 fprintf (dump_file, "Register %s will hold %ld\n",
5841 reg_names[ REGNO (reg)], (long)INTVAL (value));
5843 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5844 fprintf (dump_file, "Register %s will hold LR\n",
5845 reg_names[ REGNO (reg)]);
5848 fprintf (dump_file, "Register %s will hold a saved value\n",
5849 reg_names[ REGNO (reg)]);
5856 /* Update a MEM used in conditional code that might contain an offset to put
5857 the offset into a scratch register, so that the conditional load/store
5858 operations can be used. This function returns the original pointer if the
5859 MEM is valid to use in conditional code, NULL if we can't load up the offset
5860 into a temporary register, or the new MEM if we were successful. */
5863 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5865 rtx addr = XEXP (mem, 0);
5867 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5869 if (GET_CODE (addr) == PLUS)
5871 rtx addr_op0 = XEXP (addr, 0);
5872 rtx addr_op1 = XEXP (addr, 1);
5874 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5876 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5880 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5887 else if (CONSTANT_P (addr))
5888 addr = frv_ifcvt_load_value (addr, insn);
5893 if (addr == NULL_RTX)
5896 else if (XEXP (mem, 0) != addr)
5897 return change_address (mem, mode, addr);
5904 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5905 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5908 single_set_pattern (rtx pattern)
5913 if (GET_CODE (pattern) == COND_EXEC)
5914 pattern = COND_EXEC_CODE (pattern);
5916 if (GET_CODE (pattern) == SET)
5919 else if (GET_CODE (pattern) == PARALLEL)
5921 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5923 rtx sub = XVECEXP (pattern, 0, i);
5925 switch (GET_CODE (sub))
5949 /* A C expression to modify the code described by the conditional if
5950 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5951 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5952 insn cannot be converted to be executed conditionally. */
5955 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5959 rtx orig_ce_pattern = pattern;
5965 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5967 test = COND_EXEC_TEST (pattern);
5968 if (GET_CODE (test) == AND)
5970 rtx cr = frv_ifcvt.cr_reg;
5973 op0 = XEXP (test, 0);
5974 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5977 op1 = XEXP (test, 1);
5978 test_reg = XEXP (op1, 0);
5979 if (GET_CODE (test_reg) != REG)
5982 /* Is this the first nested if block in this sequence? If so, generate
5983 an andcr or andncr. */
5984 if (! frv_ifcvt.last_nested_if_cr)
5988 frv_ifcvt.last_nested_if_cr = test_reg;
5989 if (GET_CODE (op0) == NE)
5990 and_op = gen_andcr (test_reg, cr, test_reg);
5992 and_op = gen_andncr (test_reg, cr, test_reg);
5994 frv_ifcvt_add_insn (and_op, insn, TRUE);
5997 /* If this isn't the first statement in the nested if sequence, see if we
5998 are dealing with the same register. */
5999 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6002 COND_EXEC_TEST (pattern) = test = op1;
6005 /* If this isn't a nested if, reset state variables. */
6008 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6011 set = single_set_pattern (pattern);
6014 rtx dest = SET_DEST (set);
6015 rtx src = SET_SRC (set);
6016 enum machine_mode mode = GET_MODE (dest);
6018 /* Check for normal binary operators. */
6019 if (mode == SImode && ARITHMETIC_P (src))
6021 op0 = XEXP (src, 0);
6022 op1 = XEXP (src, 1);
6024 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6026 op1 = frv_ifcvt_load_value (op1, insn);
6028 COND_EXEC_CODE (pattern)
6029 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6037 /* For multiply by a constant, we need to handle the sign extending
6038 correctly. Add a USE of the value after the multiply to prevent flow
6039 from cratering because only one register out of the two were used. */
6040 else if (mode == DImode && GET_CODE (src) == MULT)
6042 op0 = XEXP (src, 0);
6043 op1 = XEXP (src, 1);
6044 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6046 op1 = frv_ifcvt_load_value (op1, insn);
6049 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6050 COND_EXEC_CODE (pattern)
6051 = gen_rtx_SET (VOIDmode, dest,
6052 gen_rtx_MULT (DImode, op0, op1));
6058 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6061 /* If we are just loading a constant created for a nested conditional
6062 execution statement, just load the constant without any conditional
6063 execution, since we know that the constant will not interfere with any
6065 else if (frv_ifcvt.scratch_insns_bitmap
6066 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6068 && REG_P (SET_DEST (set))
6069 /* We must not unconditionally set a scratch reg chosen
6070 for a nested if-converted block if its incoming
6071 value from the TEST block (or the result of the THEN
6072 branch) could/should propagate to the JOIN block.
6073 It suffices to test whether the register is live at
6074 the JOIN point: if it's live there, we can infer
6075 that we set it in the former JOIN block of the
6076 nested if-converted block (otherwise it wouldn't
6077 have been available as a scratch register), and it
6078 is either propagated through or set in the other
6079 conditional block. It's probably not worth trying
6080 to catch the latter case, and it could actually
6081 limit scheduling of the combined block quite
6084 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6085 REGNO (SET_DEST (set))))
6086 /* Similarly, we must not unconditionally set a reg
6087 used as scratch in the THEN branch if the same reg
6088 is live in the ELSE branch. */
6089 && (! ce_info->else_bb
6090 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6091 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6092 REGNO (SET_DEST (set))))))
6095 else if (mode == QImode || mode == HImode || mode == SImode
6098 int changed_p = FALSE;
6100 /* Check for just loading up a constant */
6101 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6103 src = frv_ifcvt_load_value (src, insn);
6110 /* See if we need to fix up stores */
6111 if (GET_CODE (dest) == MEM)
6113 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6118 else if (new_mem != dest)
6125 /* See if we need to fix up loads */
6126 if (GET_CODE (src) == MEM)
6128 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6133 else if (new_mem != src)
6140 /* If either src or destination changed, redo SET. */
6142 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6145 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6146 rewriting the CC register to be the same as the paired CC/CR register
6148 else if (mode == CC_CCRmode && COMPARISON_P (src))
6150 int regno = REGNO (XEXP (src, 0));
6153 if (ce_info->pass > 1
6154 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6155 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6157 src = gen_rtx_fmt_ee (GET_CODE (src),
6159 frv_ifcvt.nested_cc_reg,
6163 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6164 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6167 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6168 else if (ce_info->pass > 1
6169 && GET_CODE (dest) == REG
6170 && CC_P (REGNO (dest))
6171 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6172 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6174 && GET_CODE (src) == COMPARE)
6176 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6177 COND_EXEC_CODE (pattern)
6178 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6182 if (TARGET_DEBUG_COND_EXEC)
6184 rtx orig_pattern = PATTERN (insn);
6186 PATTERN (insn) = pattern;
6188 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6192 PATTERN (insn) = orig_pattern;
6198 if (TARGET_DEBUG_COND_EXEC)
6200 rtx orig_pattern = PATTERN (insn);
6202 PATTERN (insn) = orig_ce_pattern;
6204 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6208 PATTERN (insn) = orig_pattern;
6215 /* A C expression to perform any final machine dependent modifications in
6216 converting code to conditional execution in the code described by the
6217 conditional if information CE_INFO. */
6220 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6224 rtx p = frv_ifcvt.added_insns_list;
6227 /* Loop inserting the check insns. The last check insn is the first test,
6228 and is the appropriate place to insert constants. */
6233 rtx check_and_insert_insns = XEXP (p, 0);
6236 check_insn = XEXP (check_and_insert_insns, 0);
6237 existing_insn = XEXP (check_and_insert_insns, 1);
6240 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6241 the existing insn, otherwise it is to be inserted AFTER. */
6242 if (check_and_insert_insns->jump)
6244 emit_insn_before (check_insn, existing_insn);
6245 check_and_insert_insns->jump = 0;
6248 emit_insn_after (check_insn, existing_insn);
6250 free_EXPR_LIST_node (check_and_insert_insns);
6251 free_EXPR_LIST_node (old_p);
6253 while (p != NULL_RTX);
6255 /* Load up any constants needed into temp gprs */
6256 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6258 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6259 if (! frv_ifcvt.scratch_insns_bitmap)
6260 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6261 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6262 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6265 frv_ifcvt.added_insns_list = NULL_RTX;
6266 frv_ifcvt.cur_scratch_regs = 0;
6270 /* A C expression to cancel any machine dependent modifications in converting
6271 code to conditional execution in the code described by the conditional if
6272 information CE_INFO. */
6275 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6278 rtx p = frv_ifcvt.added_insns_list;
6280 /* Loop freeing up the EXPR_LIST's allocated. */
6281 while (p != NULL_RTX)
6283 rtx check_and_jump = XEXP (p, 0);
6287 free_EXPR_LIST_node (check_and_jump);
6288 free_EXPR_LIST_node (old_p);
6291 /* Release any temporary gprs allocated. */
6292 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6293 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6295 frv_ifcvt.added_insns_list = NULL_RTX;
6296 frv_ifcvt.cur_scratch_regs = 0;
6300 /* A C expression for the size in bytes of the trampoline, as an integer.
6304 setlo #0, <static_chain>
6306 sethi #0, <static_chain>
6307 jmpl @(gr0,<jmp_reg>) */
6310 frv_trampoline_size (void)
6313 /* Allocate room for the function descriptor and the lddi
6316 return 5 /* instructions */ * 4 /* instruction size. */;
6320 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6321 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6322 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6323 should be passed to the function when it is called.
6328 setlo #0, <static_chain>
6330 sethi #0, <static_chain>
6331 jmpl @(gr0,<jmp_reg>) */
6334 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6336 rtx addr = XEXP (m_tramp, 0);
6337 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6338 rtx sc_reg = force_reg (Pmode, static_chain);
6340 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6343 GEN_INT (frv_trampoline_size ()), SImode,
6349 /* Many machines have some registers that cannot be copied directly to or from
6350 memory or even from other types of registers. An example is the `MQ'
6351 register, which on most machines, can only be copied to or from general
6352 registers, but not memory. Some machines allow copying all registers to and
6353 from memory, but require a scratch register for stores to some memory
6354 locations (e.g., those with symbolic address on the RT, and those with
6355 certain symbolic address on the SPARC when compiling PIC). In some cases,
6356 both an intermediate and a scratch register are required.
6358 You should define these macros to indicate to the reload phase that it may
6359 need to allocate at least one register for a reload in addition to the
6360 register to contain the data. Specifically, if copying X to a register
6361 RCLASS in MODE requires an intermediate register, you should define
6362 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6363 whose registers can be used as intermediate registers or scratch registers.
6365 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6366 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6367 largest register class required. If the requirements for input and output
6368 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6369 instead of defining both macros identically.
6371 The values returned by these macros are often `GENERAL_REGS'. Return
6372 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6373 to or from a register of RCLASS in MODE without requiring a scratch register.
6374 Do not define this macro if it would always return `NO_REGS'.
6376 If a scratch register is required (either with or without an intermediate
6377 register), you should define patterns for `reload_inM' or `reload_outM', as
6378 required.. These patterns, which will normally be implemented with a
6379 `define_expand', should be similar to the `movM' patterns, except that
6380 operand 2 is the scratch register.
6382 Define constraints for the reload register and scratch register that contain
6383 a single register class. If the original reload register (whose class is
6384 RCLASS) can meet the constraint given in the pattern, the value returned by
6385 these macros is used for the class of the scratch register. Otherwise, two
6386 additional reload registers are required. Their classes are obtained from
6387 the constraints in the insn pattern.
6389 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6390 either be in a hard register or in memory. Use `true_regnum' to find out;
6391 it will return -1 if the pseudo is in memory and the hard register number if
6392 it is in a register.
6394 These macros should not be used in the case where a particular class of
6395 registers can only be copied to memory and not to another class of
6396 registers. In that case, secondary reload registers are not needed and
6397 would not be helpful. Instead, a stack location must be used to perform the
6398 copy and the `movM' pattern should use memory as an intermediate storage.
6399 This case often occurs between floating-point and general registers. */
6402 frv_secondary_reload_class (enum reg_class rclass,
6403 enum machine_mode mode ATTRIBUTE_UNUSED,
6414 /* Accumulators/Accumulator guard registers need to go through floating
6420 if (x && GET_CODE (x) == REG)
6422 int regno = REGNO (x);
6424 if (ACC_P (regno) || ACCG_P (regno))
6429 /* Nonzero constants should be loaded into an FPR through a GPR. */
6433 if (x && CONSTANT_P (x) && !ZERO_P (x))
6439 /* All of these types need gpr registers. */
6451 /* The accumulators need fpr registers. */
6463 /* This hook exists to catch the case where secondary_reload_class() is
6464 called from init_reg_autoinc() in regclass.c - before the reload optabs
6465 have been initialised. */
6468 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6469 enum machine_mode reload_mode,
6470 secondary_reload_info * sri)
6472 enum reg_class rclass = NO_REGS;
6473 enum reg_class reload_class = (enum reg_class) reload_class_i;
6475 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6477 sri->icode = sri->prev_sri->t_icode;
6481 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6483 if (rclass != NO_REGS)
6485 enum insn_code icode
6486 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6490 /* This happens when then the reload_[in|out]_optabs have
6491 not been initialised. */
6492 sri->t_icode = CODE_FOR_nothing;
6497 /* Fall back to the default secondary reload handler. */
6498 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6502 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6505 frv_class_likely_spilled_p (reg_class_t rclass)
6515 case FDPIC_FPTR_REGS:
6537 /* An expression for the alignment of a structure field FIELD if the
6538 alignment computed in the usual way is COMPUTED. GCC uses this
6539 value instead of the value in `BIGGEST_ALIGNMENT' or
6540 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6542 /* The definition type of the bit field data is either char, short, long or
6543 long long. The maximum bit size is the number of bits of its own type.
6545 The bit field data is assigned to a storage unit that has an adequate size
6546 for bit field data retention and is located at the smallest address.
6548 Consecutive bit field data are packed at consecutive bits having the same
6549 storage unit, with regard to the type, beginning with the MSB and continuing
6552 If a field to be assigned lies over a bit field type boundary, its
6553 assignment is completed by aligning it with a boundary suitable for the
6556 When a bit field having a bit length of 0 is declared, it is forcibly
6557 assigned to the next storage unit.
6570 &x 00000000 00000000 00000000 00000000
6573 &x+4 00000000 00000000 00000000 00000000
6576 &x+8 00000000 00000000 00000000 00000000
6579 &x+12 00000000 00000000 00000000 00000000
6585 frv_adjust_field_align (tree field, int computed)
6587 /* Make sure that the bitfield is not wider than the type. */
6588 if (DECL_BIT_FIELD (field)
6589 && !DECL_ARTIFICIAL (field))
6591 tree parent = DECL_CONTEXT (field);
6592 tree prev = NULL_TREE;
6595 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6597 if (TREE_CODE (cur) != FIELD_DECL)
6605 /* If this isn't a :0 field and if the previous element is a bitfield
6606 also, see if the type is different, if so, we will need to align the
6607 bit-field to the next boundary. */
6609 && ! DECL_PACKED (field)
6610 && ! integer_zerop (DECL_SIZE (field))
6611 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6613 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6614 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6615 computed = (prev_align > cur_align) ? prev_align : cur_align;
6623 /* A C expression that is nonzero if it is permissible to store a value of mode
6624 MODE in hard register number REGNO (or in several registers starting with
6625 that one). For a machine where all registers are equivalent, a suitable
6628 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6630 It is not necessary for this macro to check for the numbers of fixed
6631 registers, because the allocation mechanism considers them to be always
6634 On some machines, double-precision values must be kept in even/odd register
6635 pairs. The way to implement that is to define this macro to reject odd
6636 register numbers for such modes.
6638 The minimum requirement for a mode to be OK in a register is that the
6639 `movMODE' instruction pattern support moves between the register and any
6640 other hard register for which the mode is OK; and that moving a value into
6641 the register and back out not alter it.
6643 Since the same instruction used to move `SImode' will work for all narrower
6644 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6645 to distinguish between these modes, provided you define patterns `movhi',
6646 etc., to take advantage of this. This is useful because of the interaction
6647 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6648 all integer modes to be tieable.
6650 Many machines have special registers for floating point arithmetic. Often
6651 people assume that floating point machine modes are allowed only in floating
6652 point registers. This is not true. Any registers that can hold integers
6653 can safely *hold* a floating point machine mode, whether or not floating
6654 arithmetic can be done on it in those registers. Integer move instructions
6655 can be used to move the values.
6657 On some machines, though, the converse is true: fixed-point machine modes
6658 may not go in floating registers. This is true if the floating registers
6659 normalize any value stored in them, because storing a non-floating value
6660 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6661 fixed-point machine modes in floating registers. But if the floating
6662 registers do not automatically normalize, if you can store any bit pattern
6663 in one and retrieve it unchanged without a trap, then any machine mode may
6664 go in a floating register, so you can define this macro to say so.
6666 The primary significance of special floating registers is rather that they
6667 are the registers acceptable in floating point arithmetic instructions.
6668 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6669 writing the proper constraints for those instructions.
6671 On some machines, the floating registers are especially slow to access, so
6672 that it is better to store a value in a stack frame than in such a register
6673 if floating point arithmetic is not being done. As long as the floating
6674 registers are not in class `GENERAL_REGS', they will not be used unless some
6675 pattern's constraint asks for one. */
6678 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6688 return ICC_P (regno) || GPR_P (regno);
6691 return CR_P (regno) || GPR_P (regno);
6694 return FCC_P (regno) || GPR_P (regno);
6700 /* Set BASE to the first register in REGNO's class. Set MASK to the
6701 bits that must be clear in (REGNO - BASE) for the register to be
6703 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6707 /* ACCGs store one byte. Two-byte quantities must start in
6708 even-numbered registers, four-byte ones in registers whose
6709 numbers are divisible by four, and so on. */
6711 mask = GET_MODE_SIZE (mode) - 1;
6715 /* The other registers store one word. */
6716 if (GPR_P (regno) || regno == AP_FIRST)
6719 else if (FPR_P (regno))
6722 else if (ACC_P (regno))
6725 else if (SPR_P (regno))
6726 return mode == SImode;
6728 /* Fill in the table. */
6732 /* Anything smaller than an SI is OK in any word-sized register. */
6733 if (GET_MODE_SIZE (mode) < 4)
6736 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6738 return (((regno - base) & mask) == 0);
6745 /* A C expression for the number of consecutive hard registers, starting at
6746 register number REGNO, required to hold a value of mode MODE.
6748 On a machine where all registers are exactly one word, a suitable definition
6751 #define HARD_REGNO_NREGS(REGNO, MODE) \
6752 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6753 / UNITS_PER_WORD)) */
6755 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6756 that we can build the appropriate instructions to properly reload the
6757 values. Also, make the byte-sized accumulator guards use one guard
6761 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6764 return GET_MODE_SIZE (mode);
6766 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6770 /* A C expression for the maximum number of consecutive registers of
6771 class RCLASS needed to hold a value of mode MODE.
6773 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6774 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6775 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6777 This macro helps control the handling of multiple-word values in
6780 This declaration is required. */
6783 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6785 if (rclass == ACCG_REGS)
6786 /* An N-byte value requires N accumulator guards. */
6787 return GET_MODE_SIZE (mode);
6789 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6793 /* A C expression that is nonzero if X is a legitimate constant for an
6794 immediate operand on the target machine. You can assume that X satisfies
6795 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6796 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6799 frv_legitimate_constant_p (rtx x)
6801 enum machine_mode mode = GET_MODE (x);
6803 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6804 means that the move expanders will be expected to deal with most
6805 kinds of constant, regardless of what we return here.
6807 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6808 a constant can be entered into reg_equiv_constant[]. If we return true,
6809 reload can create new instances of the constant whenever it likes.
6811 The idea is therefore to accept as many constants as possible (to give
6812 reload more freedom) while rejecting constants that can only be created
6813 at certain times. In particular, anything with a symbolic component will
6814 require use of the pseudo FDPIC register, which is only available before
6817 return LEGITIMATE_PIC_OPERAND_P (x);
6819 /* All of the integer constants are ok. */
6820 if (GET_CODE (x) != CONST_DOUBLE)
6823 /* double integer constants are ok. */
6824 if (mode == VOIDmode || mode == DImode)
6827 /* 0 is always ok. */
6828 if (x == CONST0_RTX (mode))
6831 /* If floating point is just emulated, allow any constant, since it will be
6832 constructed in the GPRs. */
6833 if (!TARGET_HAS_FPRS)
6836 if (mode == DFmode && !TARGET_DOUBLE)
6839 /* Otherwise store the constant away and do a load. */
6843 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6844 CC_NZ for comparisons against zero in which a single Z or N flag test
6845 is enough, CC_UNS for other unsigned comparisons, and CC for other
6846 signed comparisons. */
6849 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6851 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6860 return y == const0_rtx ? CC_NZmode : CCmode;
6866 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6874 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6876 #define HIGH_COST 40
6877 #define MEDIUM_COST 3
6881 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6882 reg_class_t from, reg_class_t to)
6966 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6969 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6970 reg_class_t rclass ATTRIBUTE_UNUSED,
6971 bool in ATTRIBUTE_UNUSED)
6977 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6978 use ".picptr" to generate safe relocations for PIC code. We also
6979 need a fixup entry for aligned (non-debugging) code. */
6982 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6984 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6986 if (GET_CODE (value) == CONST
6987 || GET_CODE (value) == SYMBOL_REF
6988 || GET_CODE (value) == LABEL_REF)
6990 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6991 && SYMBOL_REF_FUNCTION_P (value))
6993 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6994 output_addr_const (asm_out_file, value);
6995 fputs (")\n", asm_out_file);
6998 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6999 && frv_function_symbol_referenced_p (value))
7001 if (aligned_p && !TARGET_FDPIC)
7003 static int label_num = 0;
7007 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7008 p = (* targetm.strip_name_encoding) (buf);
7010 fprintf (asm_out_file, "%s:\n", p);
7011 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7012 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7013 fprintf (asm_out_file, "\t.previous\n");
7015 assemble_integer_with_op ("\t.picptr\t", value);
7020 /* We've set the unaligned SI op to NULL, so we always have to
7021 handle the unaligned case here. */
7022 assemble_integer_with_op ("\t.4byte\t", value);
7026 return default_assemble_integer (value, size, aligned_p);
7029 /* Function to set up the backend function structure. */
7031 static struct machine_function *
7032 frv_init_machine_status (void)
7034 return ggc_alloc_cleared_machine_function ();
7037 /* Implement TARGET_SCHED_ISSUE_RATE. */
7040 frv_issue_rate (void)
7045 switch (frv_cpu_type)
7049 case FRV_CPU_SIMPLE:
7057 case FRV_CPU_GENERIC:
7059 case FRV_CPU_TOMCAT:
7067 /* A for_each_rtx callback. If X refers to an accumulator, return
7068 ACC_GROUP_ODD if the bit 2 of the register number is set and
7069 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7073 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7077 if (ACC_P (REGNO (*x)))
7078 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7079 if (ACCG_P (REGNO (*x)))
7080 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7085 /* Return the value of INSN's acc_group attribute. */
7088 frv_acc_group (rtx insn)
7090 /* This distinction only applies to the FR550 packing constraints. */
7091 if (frv_cpu_type != FRV_CPU_FR550)
7092 return ACC_GROUP_NONE;
7093 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7096 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7097 INSN will try to claim first. Since this value depends only on the
7098 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7101 frv_insn_unit (rtx insn)
7103 enum attr_type type;
7105 type = get_attr_type (insn);
7106 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7108 /* We haven't seen this type of instruction before. */
7112 /* Issue the instruction on its own to see which unit it prefers. */
7113 state = alloca (state_size ());
7114 state_reset (state);
7115 state_transition (state, insn);
7117 /* Find out which unit was taken. */
7118 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7119 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7122 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7124 frv_type_to_unit[type] = unit;
7126 return frv_type_to_unit[type];
7129 /* Return true if INSN issues to a branch unit. */
7132 frv_issues_to_branch_unit_p (rtx insn)
7134 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7137 /* The current state of the packing pass, implemented by frv_pack_insns. */
7139 /* The state of the pipeline DFA. */
7142 /* Which hardware registers are set within the current packet,
7143 and the conditions under which they are set. */
7144 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7146 /* The memory locations that have been modified so far in this
7147 packet. MEM is the memref and COND is the regstate_t condition
7148 under which it is set. */
7154 /* The number of valid entries in MEMS. The value is larger than
7155 ARRAY_SIZE (mems) if there were too many mems to record. */
7156 unsigned int num_mems;
7158 /* The maximum number of instructions that can be packed together. */
7159 unsigned int issue_rate;
7161 /* The instructions in the packet, partitioned into groups. */
7162 struct frv_packet_group {
7163 /* How many instructions in the packet belong to this group. */
7164 unsigned int num_insns;
7166 /* A list of the instructions that belong to this group, in the order
7167 they appear in the rtl stream. */
7168 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7170 /* The contents of INSNS after they have been sorted into the correct
7171 assembly-language order. Element X issues to unit X. The list may
7172 contain extra nops. */
7173 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7175 /* The member of frv_nops[] to use in sorted[]. */
7177 } groups[NUM_GROUPS];
7179 /* The instructions that make up the current packet. */
7180 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7181 unsigned int num_insns;
7184 /* Return the regstate_t flags for the given COND_EXEC condition.
7185 Abort if the condition isn't in the right form. */
7188 frv_cond_flags (rtx cond)
7190 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7191 && GET_CODE (XEXP (cond, 0)) == REG
7192 && CR_P (REGNO (XEXP (cond, 0)))
7193 && XEXP (cond, 1) == const0_rtx);
7194 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7195 | (GET_CODE (cond) == NE
7197 : REGSTATE_IF_FALSE));
7201 /* Return true if something accessed under condition COND2 can
7202 conflict with something written under condition COND1. */
7205 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7207 /* If either reference was unconditional, we have a conflict. */
7208 if ((cond1 & REGSTATE_IF_EITHER) == 0
7209 || (cond2 & REGSTATE_IF_EITHER) == 0)
7212 /* The references might conflict if they were controlled by
7214 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7217 /* They definitely conflict if they are controlled by the
7219 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7226 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7227 the current packet. DATA points to a regstate_t that describes the
7228 condition under which *X might be set or used. */
7231 frv_registers_conflict_p_1 (rtx *x, void *data)
7233 unsigned int regno, i;
7236 cond = *(regstate_t *) data;
7238 if (GET_CODE (*x) == REG)
7239 FOR_EACH_REGNO (regno, *x)
7240 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7241 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7244 if (GET_CODE (*x) == MEM)
7246 /* If we ran out of memory slots, assume a conflict. */
7247 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7250 /* Check for output or true dependencies with earlier MEMs. */
7251 for (i = 0; i < frv_packet.num_mems; i++)
7252 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7254 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7258 if (output_dependence (frv_packet.mems[i].mem, *x))
7263 /* The return values of calls aren't significant: they describe
7264 the effect of the call as a whole, not of the insn itself. */
7265 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7267 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7272 /* Check subexpressions. */
7277 /* Return true if something in X might depend on an instruction
7278 in the current packet. */
7281 frv_registers_conflict_p (rtx x)
7286 if (GET_CODE (x) == COND_EXEC)
7288 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7291 flags |= frv_cond_flags (XEXP (x, 0));
7294 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7298 /* A note_stores callback. DATA points to the regstate_t condition
7299 under which X is modified. Update FRV_PACKET accordingly. */
7302 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7306 if (GET_CODE (x) == REG)
7307 FOR_EACH_REGNO (regno, x)
7308 frv_packet.regstate[regno] |= *(regstate_t *) data;
7310 if (GET_CODE (x) == MEM)
7312 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7314 frv_packet.mems[frv_packet.num_mems].mem = x;
7315 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7317 frv_packet.num_mems++;
7322 /* Update the register state information for an instruction whose
7326 frv_registers_update (rtx x)
7330 flags = REGSTATE_MODIFIED;
7331 if (GET_CODE (x) == COND_EXEC)
7333 flags |= frv_cond_flags (XEXP (x, 0));
7336 note_stores (x, frv_registers_update_1, &flags);
7340 /* Initialize frv_packet for the start of a new packet. */
7343 frv_start_packet (void)
7345 enum frv_insn_group group;
7347 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7348 frv_packet.num_mems = 0;
7349 frv_packet.num_insns = 0;
7350 for (group = 0; group < NUM_GROUPS; group++)
7351 frv_packet.groups[group].num_insns = 0;
7355 /* Likewise for the start of a new basic block. */
7358 frv_start_packet_block (void)
7360 state_reset (frv_packet.dfa_state);
7361 frv_start_packet ();
7365 /* Finish the current packet, if any, and start a new one. Call
7366 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7369 frv_finish_packet (void (*handle_packet) (void))
7371 if (frv_packet.num_insns > 0)
7374 state_transition (frv_packet.dfa_state, 0);
7375 frv_start_packet ();
7380 /* Return true if INSN can be added to the current packet. Update
7381 the DFA state on success. */
7384 frv_pack_insn_p (rtx insn)
7386 /* See if the packet is already as long as it can be. */
7387 if (frv_packet.num_insns == frv_packet.issue_rate)
7390 /* If the scheduler thought that an instruction should start a packet,
7391 it's usually a good idea to believe it. It knows much more about
7392 the latencies than we do.
7394 There are some exceptions though:
7396 - Conditional instructions are scheduled on the assumption that
7397 they will be executed. This is usually a good thing, since it
7398 tends to avoid unnecessary stalls in the conditional code.
7399 But we want to pack conditional instructions as tightly as
7400 possible, in order to optimize the case where they aren't
7403 - The scheduler will always put branches on their own, even
7404 if there's no real dependency.
7406 - There's no point putting a call in its own packet unless
7408 if (frv_packet.num_insns > 0
7409 && GET_CODE (insn) == INSN
7410 && GET_MODE (insn) == TImode
7411 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7414 /* Check for register conflicts. Don't do this for setlo since any
7415 conflict will be with the partnering sethi, with which it can
7417 if (get_attr_type (insn) != TYPE_SETLO)
7418 if (frv_registers_conflict_p (PATTERN (insn)))
7421 return state_transition (frv_packet.dfa_state, insn) < 0;
7425 /* Add instruction INSN to the current packet. */
7428 frv_add_insn_to_packet (rtx insn)
7430 struct frv_packet_group *packet_group;
7432 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7433 packet_group->insns[packet_group->num_insns++] = insn;
7434 frv_packet.insns[frv_packet.num_insns++] = insn;
7436 frv_registers_update (PATTERN (insn));
7440 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7441 packet ends in a branch or call, insert the nop before it, otherwise
7445 frv_insert_nop_in_packet (rtx insn)
7447 struct frv_packet_group *packet_group;
7450 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7451 last = frv_packet.insns[frv_packet.num_insns - 1];
7452 if (GET_CODE (last) != INSN)
7454 insn = emit_insn_before (PATTERN (insn), last);
7455 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7456 frv_packet.insns[frv_packet.num_insns++] = last;
7460 insn = emit_insn_after (PATTERN (insn), last);
7461 frv_packet.insns[frv_packet.num_insns++] = insn;
7463 packet_group->insns[packet_group->num_insns++] = insn;
7467 /* If packing is enabled, divide the instructions into packets and
7468 return true. Call HANDLE_PACKET for each complete packet. */
7471 frv_for_each_packet (void (*handle_packet) (void))
7473 rtx insn, next_insn;
7475 frv_packet.issue_rate = frv_issue_rate ();
7477 /* Early exit if we don't want to pack insns. */
7479 || !flag_schedule_insns_after_reload
7480 || !TARGET_VLIW_BRANCH
7481 || frv_packet.issue_rate == 1)
7484 /* Set up the initial packing state. */
7486 frv_packet.dfa_state = alloca (state_size ());
7488 frv_start_packet_block ();
7489 for (insn = get_insns (); insn != 0; insn = next_insn)
7494 code = GET_CODE (insn);
7495 next_insn = NEXT_INSN (insn);
7497 if (code == CODE_LABEL)
7499 frv_finish_packet (handle_packet);
7500 frv_start_packet_block ();
7504 switch (GET_CODE (PATTERN (insn)))
7513 /* Calls mustn't be packed on a TOMCAT. */
7514 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7515 frv_finish_packet (handle_packet);
7517 /* Since the last instruction in a packet determines the EH
7518 region, any exception-throwing instruction must come at
7519 the end of reordered packet. Insns that issue to a
7520 branch unit are bound to come last; for others it's
7521 too hard to predict. */
7522 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7523 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7524 frv_finish_packet (handle_packet);
7526 /* Finish the current packet if we can't add INSN to it.
7527 Simulate cycles until INSN is ready to issue. */
7528 if (!frv_pack_insn_p (insn))
7530 frv_finish_packet (handle_packet);
7531 while (!frv_pack_insn_p (insn))
7532 state_transition (frv_packet.dfa_state, 0);
7535 /* Add the instruction to the packet. */
7536 frv_add_insn_to_packet (insn);
7538 /* Calls and jumps end a packet, as do insns that throw
7540 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7541 frv_finish_packet (handle_packet);
7545 frv_finish_packet (handle_packet);
7550 /* Subroutine of frv_sort_insn_group. We are trying to sort
7551 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7552 language order. We have already picked a new position for
7553 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7554 These instructions will occupy elements [0, LOWER_SLOT) and
7555 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7556 the DFA state after issuing these instructions.
7558 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7559 of the unused instructions. Return true if one such permutation gives
7560 a valid ordering, leaving the successful permutation in sorted[].
7561 Do not modify sorted[] until a valid permutation is found. */
7564 frv_sort_insn_group_1 (enum frv_insn_group group,
7565 unsigned int lower_slot, unsigned int upper_slot,
7566 unsigned int issued, unsigned int num_insns,
7569 struct frv_packet_group *packet_group;
7575 /* Early success if we've filled all the slots. */
7576 if (lower_slot == upper_slot)
7579 packet_group = &frv_packet.groups[group];
7580 dfa_size = state_size ();
7581 test_state = alloca (dfa_size);
7583 /* Try issuing each unused instruction. */
7584 for (i = num_insns - 1; i + 1 != 0; i--)
7585 if (~issued & (1 << i))
7587 insn = packet_group->sorted[i];
7588 memcpy (test_state, state, dfa_size);
7589 if (state_transition (test_state, insn) < 0
7590 && cpu_unit_reservation_p (test_state,
7591 NTH_UNIT (group, upper_slot - 1))
7592 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7593 issued | (1 << i), num_insns,
7596 packet_group->sorted[upper_slot - 1] = insn;
7604 /* Compare two instructions by their frv_insn_unit. */
7607 frv_compare_insns (const void *first, const void *second)
7609 const rtx *const insn1 = (rtx const *) first,
7610 *const insn2 = (rtx const *) second;
7611 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7614 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7615 and sort it into assembly language order. See frv.md for a description of
7619 frv_sort_insn_group (enum frv_insn_group group)
7621 struct frv_packet_group *packet_group;
7622 unsigned int first, i, nop, max_unit, num_slots;
7623 state_t state, test_state;
7626 packet_group = &frv_packet.groups[group];
7628 /* Assume no nop is needed. */
7629 packet_group->nop = 0;
7631 if (packet_group->num_insns == 0)
7634 /* Copy insns[] to sorted[]. */
7635 memcpy (packet_group->sorted, packet_group->insns,
7636 sizeof (rtx) * packet_group->num_insns);
7638 /* Sort sorted[] by the unit that each insn tries to take first. */
7639 if (packet_group->num_insns > 1)
7640 qsort (packet_group->sorted, packet_group->num_insns,
7641 sizeof (rtx), frv_compare_insns);
7643 /* That's always enough for branch and control insns. */
7644 if (group == GROUP_B || group == GROUP_C)
7647 dfa_size = state_size ();
7648 state = alloca (dfa_size);
7649 test_state = alloca (dfa_size);
7651 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7652 consecutively and such that the DFA takes unit X when sorted[X]
7653 is added. Set STATE to the new DFA state. */
7654 state_reset (test_state);
7655 for (first = 0; first < packet_group->num_insns; first++)
7657 memcpy (state, test_state, dfa_size);
7658 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7659 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7663 /* If all the instructions issued in ascending order, we're done. */
7664 if (first == packet_group->num_insns)
7667 /* Add nops to the end of sorted[] and try each permutation until
7668 we find one that works. */
7669 for (nop = 0; nop < frv_num_nops; nop++)
7671 max_unit = frv_insn_unit (frv_nops[nop]);
7672 if (frv_unit_groups[max_unit] == group)
7674 packet_group->nop = frv_nops[nop];
7675 num_slots = UNIT_NUMBER (max_unit) + 1;
7676 for (i = packet_group->num_insns; i < num_slots; i++)
7677 packet_group->sorted[i] = frv_nops[nop];
7678 if (frv_sort_insn_group_1 (group, first, num_slots,
7679 (1 << first) - 1, num_slots, state))
7686 /* Sort the current packet into assembly-language order. Set packing
7687 flags as appropriate. */
7690 frv_reorder_packet (void)
7692 unsigned int cursor[NUM_GROUPS];
7693 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7694 unsigned int unit, to, from;
7695 enum frv_insn_group group;
7696 struct frv_packet_group *packet_group;
7698 /* First sort each group individually. */
7699 for (group = 0; group < NUM_GROUPS; group++)
7702 frv_sort_insn_group (group);
7705 /* Go through the unit template and try add an instruction from
7706 that unit's group. */
7708 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7710 group = frv_unit_groups[unit];
7711 packet_group = &frv_packet.groups[group];
7712 if (cursor[group] < packet_group->num_insns)
7714 /* frv_reorg should have added nops for us. */
7715 gcc_assert (packet_group->sorted[cursor[group]]
7716 != packet_group->nop);
7717 insns[to++] = packet_group->sorted[cursor[group]++];
7721 gcc_assert (to == frv_packet.num_insns);
7723 /* Clear the last instruction's packing flag, thus marking the end of
7724 a packet. Reorder the other instructions relative to it. */
7725 CLEAR_PACKING_FLAG (insns[to - 1]);
7726 for (from = 0; from < to - 1; from++)
7728 remove_insn (insns[from]);
7729 add_insn_before (insns[from], insns[to - 1], NULL);
7730 SET_PACKING_FLAG (insns[from]);
7735 /* Divide instructions into packets. Reorder the contents of each
7736 packet so that they are in the correct assembly-language order.
7738 Since this pass can change the raw meaning of the rtl stream, it must
7739 only be called at the last minute, just before the instructions are
7743 frv_pack_insns (void)
7745 if (frv_for_each_packet (frv_reorder_packet))
7746 frv_insn_packing_flag = 0;
7748 frv_insn_packing_flag = -1;
7751 /* See whether we need to add nops to group GROUP in order to
7752 make a valid packet. */
7755 frv_fill_unused_units (enum frv_insn_group group)
7757 unsigned int non_nops, nops, i;
7758 struct frv_packet_group *packet_group;
7760 packet_group = &frv_packet.groups[group];
7762 /* Sort the instructions into assembly-language order.
7763 Use nops to fill slots that are otherwise unused. */
7764 frv_sort_insn_group (group);
7766 /* See how many nops are needed before the final useful instruction. */
7768 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7769 while (packet_group->sorted[i++] == packet_group->nop)
7772 /* Insert that many nops into the instruction stream. */
7774 frv_insert_nop_in_packet (packet_group->nop);
7777 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7780 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7782 if (io1->const_address != 0 && io2->const_address != 0)
7783 return io1->const_address == io2->const_address;
7785 if (io1->var_address != 0 && io2->var_address != 0)
7786 return rtx_equal_p (io1->var_address, io2->var_address);
7791 /* Return true if operations IO1 and IO2 are guaranteed to complete
7795 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7797 /* The order of writes is always preserved. */
7798 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7801 /* The order of reads isn't preserved. */
7802 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7805 /* One operation is a write and the other is (or could be) a read.
7806 The order is only guaranteed if the accesses are to the same
7808 return frv_same_doubleword_p (io1, io2);
7811 /* Generalize I/O operation X so that it covers both X and Y. */
7814 frv_io_union (struct frv_io *x, const struct frv_io *y)
7816 if (x->type != y->type)
7817 x->type = FRV_IO_UNKNOWN;
7818 if (!frv_same_doubleword_p (x, y))
7820 x->const_address = 0;
7825 /* Fill IO with information about the load or store associated with
7826 membar instruction INSN. */
7829 frv_extract_membar (struct frv_io *io, rtx insn)
7831 extract_insn (insn);
7832 io->type = INTVAL (recog_data.operand[2]);
7833 io->const_address = INTVAL (recog_data.operand[1]);
7834 io->var_address = XEXP (recog_data.operand[0], 0);
7837 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7838 if X is a register and *DATA depends on X. */
7841 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7843 rtx *other = (rtx *) data;
7845 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7849 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7850 Remove every modified register from the set. */
7853 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7855 HARD_REG_SET *set = (HARD_REG_SET *) data;
7859 FOR_EACH_REGNO (regno, x)
7860 CLEAR_HARD_REG_BIT (*set, regno);
7863 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7864 Add every register in *X to the set. */
7867 frv_io_handle_use_1 (rtx *x, void *data)
7869 HARD_REG_SET *set = (HARD_REG_SET *) data;
7873 FOR_EACH_REGNO (regno, *x)
7874 SET_HARD_REG_BIT (*set, regno);
7879 /* A note_stores callback that applies frv_io_handle_use_1 to an
7880 entire rhs value. */
7883 frv_io_handle_use (rtx *x, void *data)
7885 for_each_rtx (x, frv_io_handle_use_1, data);
7888 /* Go through block BB looking for membars to remove. There are two
7889 cases where intra-block analysis is enough:
7891 - a membar is redundant if it occurs between two consecutive I/O
7892 operations and if those operations are guaranteed to complete
7895 - a membar for a __builtin_read is redundant if the result is
7896 used before the next I/O operation is issued.
7898 If the last membar in the block could not be removed, and there
7899 are guaranteed to be no I/O operations between that membar and
7900 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7903 Describe the block's first I/O operation in *NEXT_IO. Describe
7904 an unknown operation if the block doesn't do any I/O. */
7907 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7910 HARD_REG_SET used_regs;
7911 rtx next_membar, set, insn;
7914 /* NEXT_IO is the next I/O operation to be performed after the current
7915 instruction. It starts off as being an unknown operation. */
7916 memset (next_io, 0, sizeof (*next_io));
7918 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7919 next_is_end_p = true;
7921 /* If the current instruction is a __builtin_read or __builtin_write,
7922 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7923 is null if the membar has already been deleted.
7925 Note that the initialization here should only be needed to
7926 suppress warnings. */
7929 /* USED_REGS is the set of registers that are used before the
7930 next I/O instruction. */
7931 CLEAR_HARD_REG_SET (used_regs);
7933 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7934 if (GET_CODE (insn) == CALL_INSN)
7936 /* We can't predict what a call will do to volatile memory. */
7937 memset (next_io, 0, sizeof (struct frv_io));
7938 next_is_end_p = false;
7939 CLEAR_HARD_REG_SET (used_regs);
7941 else if (INSN_P (insn))
7942 switch (recog_memoized (insn))
7944 case CODE_FOR_optional_membar_qi:
7945 case CODE_FOR_optional_membar_hi:
7946 case CODE_FOR_optional_membar_si:
7947 case CODE_FOR_optional_membar_di:
7951 /* Local information isn't enough to decide whether this
7952 membar is needed. Stash it away for later. */
7953 *last_membar = insn;
7954 frv_extract_membar (next_io, insn);
7955 next_is_end_p = false;
7959 /* Check whether the I/O operation before INSN could be
7960 reordered with one described by NEXT_IO. If it can't,
7961 INSN will not be needed. */
7962 struct frv_io prev_io;
7964 frv_extract_membar (&prev_io, insn);
7965 if (frv_io_fixed_order_p (&prev_io, next_io))
7969 ";; [Local] Removing membar %d since order"
7970 " of accesses is guaranteed\n",
7971 INSN_UID (next_membar));
7973 insn = NEXT_INSN (insn);
7974 delete_insn (next_membar);
7982 /* Invalidate NEXT_IO's address if it depends on something that
7983 is clobbered by INSN. */
7984 if (next_io->var_address)
7985 note_stores (PATTERN (insn), frv_io_check_address,
7986 &next_io->var_address);
7988 /* If the next membar is associated with a __builtin_read,
7989 see if INSN reads from that address. If it does, and if
7990 the destination register is used before the next I/O access,
7991 there is no need for the membar. */
7992 set = PATTERN (insn);
7993 if (next_io->type == FRV_IO_READ
7994 && next_io->var_address != 0
7996 && GET_CODE (set) == SET
7997 && GET_CODE (SET_DEST (set)) == REG
7998 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8002 src = SET_SRC (set);
8003 if (GET_CODE (src) == ZERO_EXTEND)
8004 src = XEXP (src, 0);
8006 if (GET_CODE (src) == MEM
8007 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8011 ";; [Local] Removing membar %d since the target"
8012 " of %d is used before the I/O operation\n",
8013 INSN_UID (next_membar), INSN_UID (insn));
8015 if (next_membar == *last_membar)
8018 delete_insn (next_membar);
8023 /* If INSN has volatile references, forget about any registers
8024 that are used after it. Otherwise forget about uses that
8025 are (or might be) defined by INSN. */
8026 if (volatile_refs_p (PATTERN (insn)))
8027 CLEAR_HARD_REG_SET (used_regs);
8029 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8031 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8036 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8037 FIRST_IO[X] describes the first operation performed by basic block X. */
8040 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8043 struct frv_io this_io, next_io;
8047 /* We need to keep the membar if there is an edge to the exit block. */
8048 FOR_EACH_EDGE (succ, ei, bb->succs)
8049 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8050 if (succ->dest == EXIT_BLOCK_PTR)
8053 /* Work out the union of all successor blocks. */
8054 ei = ei_start (bb->succs);
8055 ei_cond (ei, &succ);
8056 /* next_io = first_io[bb->succ->dest->index]; */
8057 next_io = first_io[succ->dest->index];
8058 ei = ei_start (bb->succs);
8059 if (ei_cond (ei, &succ))
8061 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8062 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8063 frv_io_union (&next_io, &first_io[succ->dest->index]);
8068 frv_extract_membar (&this_io, membar);
8069 if (frv_io_fixed_order_p (&this_io, &next_io))
8073 ";; [Global] Removing membar %d since order of accesses"
8074 " is guaranteed\n", INSN_UID (membar));
8076 delete_insn (membar);
8080 /* Remove redundant membars from the current function. */
8083 frv_optimize_membar (void)
8086 struct frv_io *first_io;
8089 compute_bb_for_insn ();
8090 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8091 last_membar = XCNEWVEC (rtx, last_basic_block);
8094 frv_optimize_membar_local (bb, &first_io[bb->index],
8095 &last_membar[bb->index]);
8098 if (last_membar[bb->index] != 0)
8099 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8105 /* Used by frv_reorg to keep track of the current packet's address. */
8106 static unsigned int frv_packet_address;
8108 /* If the current packet falls through to a label, try to pad the packet
8109 with nops in order to fit the label's alignment requirements. */
8112 frv_align_label (void)
8114 unsigned int alignment, target, nop;
8115 rtx x, last, barrier, label;
8117 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8118 maximum alignment of that packet, LABEL to the last label between
8119 the packets, and BARRIER to the last barrier. */
8120 last = frv_packet.insns[frv_packet.num_insns - 1];
8121 label = barrier = 0;
8123 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8127 unsigned int subalign = 1 << label_to_alignment (x);
8128 alignment = MAX (alignment, subalign);
8135 /* If -malign-labels, and the packet falls through to an unaligned
8136 label, try introducing a nop to align that label to 8 bytes. */
8137 if (TARGET_ALIGN_LABELS
8140 && frv_packet.num_insns < frv_packet.issue_rate)
8141 alignment = MAX (alignment, 8);
8143 /* Advance the address to the end of the current packet. */
8144 frv_packet_address += frv_packet.num_insns * 4;
8146 /* Work out the target address, after alignment. */
8147 target = (frv_packet_address + alignment - 1) & -alignment;
8149 /* If the packet falls through to the label, try to find an efficient
8150 padding sequence. */
8153 /* First try adding nops to the current packet. */
8154 for (nop = 0; nop < frv_num_nops; nop++)
8155 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8157 frv_insert_nop_in_packet (frv_nops[nop]);
8158 frv_packet_address += 4;
8161 /* If we still haven't reached the target, add some new packets that
8162 contain only nops. If there are two types of nop, insert an
8163 alternating sequence of frv_nops[0] and frv_nops[1], which will
8164 lead to packets like:
8171 etc. Just emit frv_nops[0] if that's the only nop we have. */
8172 last = frv_packet.insns[frv_packet.num_insns - 1];
8174 while (frv_packet_address < target)
8176 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8177 frv_packet_address += 4;
8178 if (frv_num_nops > 1)
8183 frv_packet_address = target;
8186 /* Subroutine of frv_reorg, called after each packet has been constructed
8190 frv_reorg_packet (void)
8192 frv_fill_unused_units (GROUP_I);
8193 frv_fill_unused_units (GROUP_FM);
8197 /* Add an instruction with pattern NOP to frv_nops[]. */
8200 frv_register_nop (rtx nop)
8202 nop = make_insn_raw (nop);
8203 NEXT_INSN (nop) = 0;
8204 PREV_INSN (nop) = 0;
8205 frv_nops[frv_num_nops++] = nop;
8208 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8209 into packets and check whether we need to insert nops in order to
8210 fulfill the processor's issue requirements. Also, if the user has
8211 requested a certain alignment for a label, try to meet that alignment
8212 by inserting nops in the previous packet. */
8217 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8218 frv_optimize_membar ();
8221 frv_register_nop (gen_nop ());
8223 frv_register_nop (gen_mnop ());
8224 if (TARGET_HARD_FLOAT)
8225 frv_register_nop (gen_fnop ());
8227 /* Estimate the length of each branch. Although this may change after
8228 we've inserted nops, it will only do so in big functions. */
8229 shorten_branches (get_insns ());
8231 frv_packet_address = 0;
8232 frv_for_each_packet (frv_reorg_packet);
8235 #define def_builtin(name, type, code) \
8236 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8238 struct builtin_description
8240 enum insn_code icode;
8242 enum frv_builtins code;
8243 enum rtx_code comparison;
8247 /* Media intrinsics that take a single, constant argument. */
8249 static struct builtin_description bdesc_set[] =
8251 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8254 /* Media intrinsics that take just one argument. */
8256 static struct builtin_description bdesc_1arg[] =
8258 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8259 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8260 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8261 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8262 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8263 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8266 /* Media intrinsics that take two arguments. */
8268 static struct builtin_description bdesc_2arg[] =
8270 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8271 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8272 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8273 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8274 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8275 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8276 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8277 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8278 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8279 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8280 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8281 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8282 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8283 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8284 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8285 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8286 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8287 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8288 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8289 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8290 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8291 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8292 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8293 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8294 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8295 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8296 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8299 /* Integer intrinsics that take two arguments and have no return value. */
8301 static struct builtin_description bdesc_int_void2arg[] =
8303 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8304 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8305 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8308 static struct builtin_description bdesc_prefetches[] =
8310 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8311 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8314 /* Media intrinsics that take two arguments, the first being an ACC number. */
8316 static struct builtin_description bdesc_cut[] =
8318 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8319 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8320 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8323 /* Two-argument media intrinsics with an immediate second argument. */
8325 static struct builtin_description bdesc_2argimm[] =
8327 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8328 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8329 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8330 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8331 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8332 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8333 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8334 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8335 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8336 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8337 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8338 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8339 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8340 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8341 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8342 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8343 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8346 /* Media intrinsics that take two arguments and return void, the first argument
8347 being a pointer to 4 words in memory. */
8349 static struct builtin_description bdesc_void2arg[] =
8351 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8352 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8355 /* Media intrinsics that take three arguments, the first being a const_int that
8356 denotes an accumulator, and that return void. */
8358 static struct builtin_description bdesc_void3arg[] =
8360 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8361 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8362 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8363 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8364 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8365 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8366 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8367 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8368 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8369 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8370 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8371 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8372 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8373 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8374 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8375 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8376 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8377 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8378 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8379 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8380 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8381 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8382 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8383 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8384 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8387 /* Media intrinsics that take two accumulator numbers as argument and
8390 static struct builtin_description bdesc_voidacc[] =
8392 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8393 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8394 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8395 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8396 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8397 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8400 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8401 a normal move and the ICODE is for the membar. */
8403 static struct builtin_description bdesc_loads[] =
8405 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8406 FRV_BUILTIN_READ8, 0, 0 },
8407 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8408 FRV_BUILTIN_READ16, 0, 0 },
8409 { CODE_FOR_optional_membar_si, "__builtin_read32",
8410 FRV_BUILTIN_READ32, 0, 0 },
8411 { CODE_FOR_optional_membar_di, "__builtin_read64",
8412 FRV_BUILTIN_READ64, 0, 0 }
8415 /* Likewise stores. */
8417 static struct builtin_description bdesc_stores[] =
8419 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8420 FRV_BUILTIN_WRITE8, 0, 0 },
8421 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8422 FRV_BUILTIN_WRITE16, 0, 0 },
8423 { CODE_FOR_optional_membar_si, "__builtin_write32",
8424 FRV_BUILTIN_WRITE32, 0, 0 },
8425 { CODE_FOR_optional_membar_di, "__builtin_write64",
8426 FRV_BUILTIN_WRITE64, 0, 0 },
8429 /* Initialize media builtins. */
8432 frv_init_builtins (void)
8434 tree endlink = void_list_node;
8435 tree accumulator = integer_type_node;
8436 tree integer = integer_type_node;
8437 tree voidt = void_type_node;
8438 tree uhalf = short_unsigned_type_node;
8439 tree sword1 = long_integer_type_node;
8440 tree uword1 = long_unsigned_type_node;
8441 tree sword2 = long_long_integer_type_node;
8442 tree uword2 = long_long_unsigned_type_node;
8443 tree uword4 = build_pointer_type (uword1);
8444 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8445 tree ubyte = unsigned_char_type_node;
8446 tree iacc = integer_type_node;
8448 #define UNARY(RET, T1) \
8449 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8451 #define BINARY(RET, T1, T2) \
8452 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8453 tree_cons (NULL_TREE, T2, endlink)))
8455 #define TRINARY(RET, T1, T2, T3) \
8456 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8457 tree_cons (NULL_TREE, T2, \
8458 tree_cons (NULL_TREE, T3, endlink))))
8460 #define QUAD(RET, T1, T2, T3, T4) \
8461 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8462 tree_cons (NULL_TREE, T2, \
8463 tree_cons (NULL_TREE, T3, \
8464 tree_cons (NULL_TREE, T4, endlink)))))
8466 tree void_ftype_void = build_function_type (voidt, endlink);
8468 tree void_ftype_acc = UNARY (voidt, accumulator);
8469 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8470 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8471 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8472 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8473 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8474 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8475 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8476 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8478 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8479 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8480 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8481 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8482 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8483 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8484 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8485 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8486 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8487 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8488 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8490 tree sw1_ftype_int = UNARY (sword1, integer);
8491 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8492 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8494 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8495 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8496 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8497 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8498 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8499 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8501 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8502 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8503 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8504 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8505 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8506 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8507 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8508 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8509 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8510 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8511 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8512 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8513 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8514 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8515 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8516 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8517 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8519 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8520 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8521 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8522 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8523 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8524 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8525 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8526 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8527 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8528 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8529 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8530 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8531 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8532 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8533 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8534 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8535 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8536 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8537 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8538 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8539 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8540 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8541 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8542 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8543 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8544 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8545 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8546 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8547 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8548 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8549 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8550 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8551 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8552 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8553 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8554 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8555 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8556 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8557 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8558 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8559 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8560 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8561 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8562 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8563 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8564 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8565 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8566 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8567 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8568 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8569 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8570 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8571 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8572 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8573 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8574 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8575 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8576 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8577 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8578 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8579 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8580 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8581 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8582 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8583 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8584 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8585 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8586 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8587 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8588 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8589 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8590 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8591 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8592 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8593 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8594 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8595 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8596 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8597 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8598 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8599 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8600 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8601 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8602 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8603 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8604 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8605 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8606 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8607 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8608 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8609 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8610 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8611 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8612 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8613 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8614 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8615 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8616 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8617 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8618 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8619 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8620 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8621 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8622 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8623 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8624 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8625 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8626 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8628 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8629 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8630 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8631 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8639 /* Set the names for various arithmetic operations according to the
8642 frv_init_libfuncs (void)
8644 set_optab_libfunc (smod_optab, SImode, "__modi");
8645 set_optab_libfunc (umod_optab, SImode, "__umodi");
8647 set_optab_libfunc (add_optab, DImode, "__addll");
8648 set_optab_libfunc (sub_optab, DImode, "__subll");
8649 set_optab_libfunc (smul_optab, DImode, "__mulll");
8650 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8651 set_optab_libfunc (smod_optab, DImode, "__modll");
8652 set_optab_libfunc (umod_optab, DImode, "__umodll");
8653 set_optab_libfunc (and_optab, DImode, "__andll");
8654 set_optab_libfunc (ior_optab, DImode, "__orll");
8655 set_optab_libfunc (xor_optab, DImode, "__xorll");
8656 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8658 set_optab_libfunc (add_optab, SFmode, "__addf");
8659 set_optab_libfunc (sub_optab, SFmode, "__subf");
8660 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8661 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8663 set_optab_libfunc (add_optab, DFmode, "__addd");
8664 set_optab_libfunc (sub_optab, DFmode, "__subd");
8665 set_optab_libfunc (smul_optab, DFmode, "__muld");
8666 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8668 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8669 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8671 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8672 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8673 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8674 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8676 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8677 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8678 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8679 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8681 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8682 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8683 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8684 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8687 /* Convert an integer constant to an accumulator register. ICODE is the
8688 code of the target instruction, OPNUM is the number of the
8689 accumulator operand and OPVAL is the constant integer. Try both
8690 ACC and ACCG registers; only report an error if neither fit the
8694 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8699 /* ACCs and ACCGs are implicit global registers if media intrinsics
8700 are being used. We set up this lazily to avoid creating lots of
8701 unnecessary call_insn rtl in non-media code. */
8702 for (i = 0; i <= ACC_MASK; i++)
8703 if ((i & ACC_MASK) == i)
8704 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8706 if (GET_CODE (opval) != CONST_INT)
8708 error ("accumulator is not a constant integer");
8711 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8713 error ("accumulator number is out of bounds");
8717 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8718 ACC_FIRST + INTVAL (opval));
8719 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8720 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8722 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8724 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8730 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8733 static enum machine_mode
8734 frv_matching_accg_mode (enum machine_mode mode)
8752 /* Given that a __builtin_read or __builtin_write function is accessing
8753 address ADDRESS, return the value that should be used as operand 1
8757 frv_io_address_cookie (rtx address)
8759 return (GET_CODE (address) == CONST_INT
8760 ? GEN_INT (INTVAL (address) / 8 * 8)
8764 /* Return the accumulator guard that should be paired with accumulator
8765 register ACC. The mode of the returned register is in the same
8766 class as ACC, but is four times smaller. */
8769 frv_matching_accg_for_acc (rtx acc)
8771 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8772 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8775 /* Read the requested argument from the call EXP given by INDEX.
8776 Return the value as an rtx. */
8779 frv_read_argument (tree exp, unsigned int index)
8781 return expand_expr (CALL_EXPR_ARG (exp, index),
8782 NULL_RTX, VOIDmode, 0);
8785 /* Like frv_read_argument, but interpret the argument as the number
8786 of an IACC register and return a (reg:MODE ...) rtx for it. */
8789 frv_read_iacc_argument (enum machine_mode mode, tree call,
8795 op = frv_read_argument (call, index);
8796 if (GET_CODE (op) != CONST_INT
8798 || INTVAL (op) > IACC_LAST - IACC_FIRST
8799 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8801 error ("invalid IACC argument");
8805 /* IACCs are implicit global registers. We set up this lazily to
8806 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8808 regno = INTVAL (op) + IACC_FIRST;
8809 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8810 global_regs[regno + i] = 1;
8812 return gen_rtx_REG (mode, regno);
8815 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8816 The instruction should require a constant operand of some sort. The
8817 function prints an error if OPVAL is not valid. */
8820 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8822 if (GET_CODE (opval) != CONST_INT)
8824 error ("%qs expects a constant argument", insn_data[icode].name);
8827 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8829 error ("constant argument out of range for %qs", insn_data[icode].name);
8835 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8836 if it's not null, has the right mode, and satisfies operand 0's
8840 frv_legitimize_target (enum insn_code icode, rtx target)
8842 enum machine_mode mode = insn_data[icode].operand[0].mode;
8845 || GET_MODE (target) != mode
8846 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8847 return gen_reg_rtx (mode);
8852 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8853 check whether ARG satisfies the operand's constraints. If it doesn't,
8854 copy ARG to a temporary register and return that. Otherwise return ARG
8858 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8860 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8862 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8865 return copy_to_mode_reg (mode, arg);
8868 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8871 frv_volatile_memref (enum machine_mode mode, rtx arg)
8875 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8876 MEM_VOLATILE_P (mem) = 1;
8880 /* Expand builtins that take a single, constant argument. At the moment,
8881 only MHDSETS falls into this category. */
8884 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8887 rtx op0 = frv_read_argument (call, 0);
8889 if (! frv_check_constant_argument (icode, 1, op0))
8892 target = frv_legitimize_target (icode, target);
8893 pat = GEN_FCN (icode) (target, op0);
8901 /* Expand builtins that take one operand. */
8904 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8907 rtx op0 = frv_read_argument (call, 0);
8909 target = frv_legitimize_target (icode, target);
8910 op0 = frv_legitimize_argument (icode, 1, op0);
8911 pat = GEN_FCN (icode) (target, op0);
8919 /* Expand builtins that take two operands. */
8922 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8925 rtx op0 = frv_read_argument (call, 0);
8926 rtx op1 = frv_read_argument (call, 1);
8928 target = frv_legitimize_target (icode, target);
8929 op0 = frv_legitimize_argument (icode, 1, op0);
8930 op1 = frv_legitimize_argument (icode, 2, op1);
8931 pat = GEN_FCN (icode) (target, op0, op1);
8939 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8943 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8946 rtx op0 = frv_read_argument (call, 0);
8947 rtx op1 = frv_read_argument (call, 1);
8950 target = frv_legitimize_target (icode, target);
8951 op0 = frv_int_to_acc (icode, 1, op0);
8955 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8957 if (! frv_check_constant_argument (icode, 2, op1))
8961 op1 = frv_legitimize_argument (icode, 2, op1);
8963 op2 = frv_matching_accg_for_acc (op0);
8964 pat = GEN_FCN (icode) (target, op0, op1, op2);
8972 /* Expand builtins that take two operands and the second is immediate. */
8975 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8978 rtx op0 = frv_read_argument (call, 0);
8979 rtx op1 = frv_read_argument (call, 1);
8981 if (! frv_check_constant_argument (icode, 2, op1))
8984 target = frv_legitimize_target (icode, target);
8985 op0 = frv_legitimize_argument (icode, 1, op0);
8986 pat = GEN_FCN (icode) (target, op0, op1);
8994 /* Expand builtins that take two operands, the first operand being a pointer to
8995 ints and return void. */
8998 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9001 rtx op0 = frv_read_argument (call, 0);
9002 rtx op1 = frv_read_argument (call, 1);
9003 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9006 if (GET_CODE (op0) != MEM)
9010 if (! offsettable_address_p (0, mode0, op0))
9012 reg = gen_reg_rtx (Pmode);
9013 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9016 op0 = gen_rtx_MEM (SImode, reg);
9019 addr = XEXP (op0, 0);
9020 if (! offsettable_address_p (0, mode0, addr))
9021 addr = copy_to_mode_reg (Pmode, op0);
9023 op0 = change_address (op0, V4SImode, addr);
9024 op1 = frv_legitimize_argument (icode, 1, op1);
9025 pat = GEN_FCN (icode) (op0, op1);
9033 /* Expand builtins that take two long operands and return void. */
9036 frv_expand_int_void2arg (enum insn_code icode, tree call)
9039 rtx op0 = frv_read_argument (call, 0);
9040 rtx op1 = frv_read_argument (call, 1);
9042 op0 = frv_legitimize_argument (icode, 1, op0);
9043 op1 = frv_legitimize_argument (icode, 1, op1);
9044 pat = GEN_FCN (icode) (op0, op1);
9052 /* Expand prefetch builtins. These take a single address as argument. */
9055 frv_expand_prefetches (enum insn_code icode, tree call)
9058 rtx op0 = frv_read_argument (call, 0);
9060 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9068 /* Expand builtins that take three operands and return void. The first
9069 argument must be a constant that describes a pair or quad accumulators. A
9070 fourth argument is created that is the accumulator guard register that
9071 corresponds to the accumulator. */
9074 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9077 rtx op0 = frv_read_argument (call, 0);
9078 rtx op1 = frv_read_argument (call, 1);
9079 rtx op2 = frv_read_argument (call, 2);
9082 op0 = frv_int_to_acc (icode, 0, op0);
9086 op1 = frv_legitimize_argument (icode, 1, op1);
9087 op2 = frv_legitimize_argument (icode, 2, op2);
9088 op3 = frv_matching_accg_for_acc (op0);
9089 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9097 /* Expand builtins that perform accumulator-to-accumulator operations.
9098 These builtins take two accumulator numbers as argument and return
9102 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9105 rtx op0 = frv_read_argument (call, 0);
9106 rtx op1 = frv_read_argument (call, 1);
9110 op0 = frv_int_to_acc (icode, 0, op0);
9114 op1 = frv_int_to_acc (icode, 1, op1);
9118 op2 = frv_matching_accg_for_acc (op0);
9119 op3 = frv_matching_accg_for_acc (op1);
9120 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9128 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9129 membar and TARGET_MODE is the mode that the loaded value should have. */
9132 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9133 tree call, rtx target)
9135 rtx op0 = frv_read_argument (call, 0);
9136 rtx cookie = frv_io_address_cookie (op0);
9138 if (target == 0 || !REG_P (target))
9139 target = gen_reg_rtx (target_mode);
9140 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9141 convert_move (target, op0, 1);
9142 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9143 cfun->machine->has_membar_p = 1;
9147 /* Likewise __builtin_write* functions. */
9150 frv_expand_store_builtin (enum insn_code icode, tree call)
9152 rtx op0 = frv_read_argument (call, 0);
9153 rtx op1 = frv_read_argument (call, 1);
9154 rtx cookie = frv_io_address_cookie (op0);
9156 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9157 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9158 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9159 cfun->machine->has_membar_p = 1;
9163 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9164 each argument forms one word of the two double-word input registers.
9165 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9166 to put the return value. */
9169 frv_expand_mdpackh_builtin (tree call, rtx target)
9171 enum insn_code icode = CODE_FOR_mdpackh;
9173 rtx arg1 = frv_read_argument (call, 0);
9174 rtx arg2 = frv_read_argument (call, 1);
9175 rtx arg3 = frv_read_argument (call, 2);
9176 rtx arg4 = frv_read_argument (call, 3);
9178 target = frv_legitimize_target (icode, target);
9179 op0 = gen_reg_rtx (DImode);
9180 op1 = gen_reg_rtx (DImode);
9182 /* The high half of each word is not explicitly initialized, so indicate
9183 that the input operands are not live before this point. */
9187 /* Move each argument into the low half of its associated input word. */
9188 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9189 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9190 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9191 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9193 pat = GEN_FCN (icode) (target, op0, op1);
9201 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9202 number as argument. */
9205 frv_expand_mclracc_builtin (tree call)
9207 enum insn_code icode = CODE_FOR_mclracc;
9209 rtx op0 = frv_read_argument (call, 0);
9211 op0 = frv_int_to_acc (icode, 0, op0);
9215 pat = GEN_FCN (icode) (op0);
9222 /* Expand builtins that take no arguments. */
9225 frv_expand_noargs_builtin (enum insn_code icode)
9227 rtx pat = GEN_FCN (icode) (const0_rtx);
9234 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9235 number or accumulator guard number as argument and return an SI integer. */
9238 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9241 rtx target = gen_reg_rtx (SImode);
9242 rtx op0 = frv_read_argument (call, 0);
9244 op0 = frv_int_to_acc (icode, 1, op0);
9248 pat = GEN_FCN (icode) (target, op0);
9256 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9257 accumulator guard as their first argument and an SImode value as their
9261 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9264 rtx op0 = frv_read_argument (call, 0);
9265 rtx op1 = frv_read_argument (call, 1);
9267 op0 = frv_int_to_acc (icode, 0, op0);
9271 op1 = frv_legitimize_argument (icode, 1, op1);
9272 pat = GEN_FCN (icode) (op0, op1);
9279 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9280 to move DImode values into and out of IACC0. */
9283 frv_split_iacc_move (rtx dest, rtx src)
9285 enum machine_mode inner;
9288 inner = GET_MODE (dest);
9289 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9290 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9291 simplify_gen_subreg (SImode, src, inner, i));
9294 /* Expand builtins. */
9297 frv_expand_builtin (tree exp,
9299 rtx subtarget ATTRIBUTE_UNUSED,
9300 enum machine_mode mode ATTRIBUTE_UNUSED,
9301 int ignore ATTRIBUTE_UNUSED)
9303 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9304 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9306 struct builtin_description *d;
9308 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9310 error ("media functions are not available unless -mmedia is used");
9316 case FRV_BUILTIN_MCOP1:
9317 case FRV_BUILTIN_MCOP2:
9318 case FRV_BUILTIN_MDUNPACKH:
9319 case FRV_BUILTIN_MBTOHE:
9320 if (! TARGET_MEDIA_REV1)
9322 error ("this media function is only available on the fr500");
9327 case FRV_BUILTIN_MQXMACHS:
9328 case FRV_BUILTIN_MQXMACXHS:
9329 case FRV_BUILTIN_MQMACXHS:
9330 case FRV_BUILTIN_MADDACCS:
9331 case FRV_BUILTIN_MSUBACCS:
9332 case FRV_BUILTIN_MASACCS:
9333 case FRV_BUILTIN_MDADDACCS:
9334 case FRV_BUILTIN_MDSUBACCS:
9335 case FRV_BUILTIN_MDASACCS:
9336 case FRV_BUILTIN_MABSHS:
9337 case FRV_BUILTIN_MDROTLI:
9338 case FRV_BUILTIN_MCPLHI:
9339 case FRV_BUILTIN_MCPLI:
9340 case FRV_BUILTIN_MDCUTSSI:
9341 case FRV_BUILTIN_MQSATHS:
9342 case FRV_BUILTIN_MHSETLOS:
9343 case FRV_BUILTIN_MHSETLOH:
9344 case FRV_BUILTIN_MHSETHIS:
9345 case FRV_BUILTIN_MHSETHIH:
9346 case FRV_BUILTIN_MHDSETS:
9347 case FRV_BUILTIN_MHDSETH:
9348 if (! TARGET_MEDIA_REV2)
9350 error ("this media function is only available on the fr400"
9356 case FRV_BUILTIN_SMASS:
9357 case FRV_BUILTIN_SMSSS:
9358 case FRV_BUILTIN_SMU:
9359 case FRV_BUILTIN_ADDSS:
9360 case FRV_BUILTIN_SUBSS:
9361 case FRV_BUILTIN_SLASS:
9362 case FRV_BUILTIN_SCUTSS:
9363 case FRV_BUILTIN_IACCreadll:
9364 case FRV_BUILTIN_IACCreadl:
9365 case FRV_BUILTIN_IACCsetll:
9366 case FRV_BUILTIN_IACCsetl:
9367 if (!TARGET_FR405_BUILTINS)
9369 error ("this builtin function is only available"
9370 " on the fr405 and fr450");
9375 case FRV_BUILTIN_PREFETCH:
9376 if (!TARGET_FR500_FR550_BUILTINS)
9378 error ("this builtin function is only available on the fr500"
9384 case FRV_BUILTIN_MQLCLRHS:
9385 case FRV_BUILTIN_MQLMTHS:
9386 case FRV_BUILTIN_MQSLLHI:
9387 case FRV_BUILTIN_MQSRAHI:
9388 if (!TARGET_MEDIA_FR450)
9390 error ("this builtin function is only available on the fr450");
9399 /* Expand unique builtins. */
9403 case FRV_BUILTIN_MTRAP:
9404 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9406 case FRV_BUILTIN_MCLRACC:
9407 return frv_expand_mclracc_builtin (exp);
9409 case FRV_BUILTIN_MCLRACCA:
9411 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9413 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9415 case FRV_BUILTIN_MRDACC:
9416 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9418 case FRV_BUILTIN_MRDACCG:
9419 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9421 case FRV_BUILTIN_MWTACC:
9422 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9424 case FRV_BUILTIN_MWTACCG:
9425 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9427 case FRV_BUILTIN_MDPACKH:
9428 return frv_expand_mdpackh_builtin (exp, target);
9430 case FRV_BUILTIN_IACCreadll:
9432 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9433 if (target == 0 || !REG_P (target))
9434 target = gen_reg_rtx (DImode);
9435 frv_split_iacc_move (target, src);
9439 case FRV_BUILTIN_IACCreadl:
9440 return frv_read_iacc_argument (SImode, exp, 0);
9442 case FRV_BUILTIN_IACCsetll:
9444 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9445 rtx src = frv_read_argument (exp, 1);
9446 frv_split_iacc_move (dest, force_reg (DImode, src));
9450 case FRV_BUILTIN_IACCsetl:
9452 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9453 rtx src = frv_read_argument (exp, 1);
9454 emit_move_insn (dest, force_reg (SImode, src));
9462 /* Expand groups of builtins. */
9464 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9465 if (d->code == fcode)
9466 return frv_expand_set_builtin (d->icode, exp, target);
9468 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9469 if (d->code == fcode)
9470 return frv_expand_unop_builtin (d->icode, exp, target);
9472 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9473 if (d->code == fcode)
9474 return frv_expand_binop_builtin (d->icode, exp, target);
9476 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9477 if (d->code == fcode)
9478 return frv_expand_cut_builtin (d->icode, exp, target);
9480 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9481 if (d->code == fcode)
9482 return frv_expand_binopimm_builtin (d->icode, exp, target);
9484 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9485 if (d->code == fcode)
9486 return frv_expand_voidbinop_builtin (d->icode, exp);
9488 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9489 if (d->code == fcode)
9490 return frv_expand_voidtriop_builtin (d->icode, exp);
9492 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9493 if (d->code == fcode)
9494 return frv_expand_voidaccop_builtin (d->icode, exp);
9496 for (i = 0, d = bdesc_int_void2arg;
9497 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9498 if (d->code == fcode)
9499 return frv_expand_int_void2arg (d->icode, exp);
9501 for (i = 0, d = bdesc_prefetches;
9502 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9503 if (d->code == fcode)
9504 return frv_expand_prefetches (d->icode, exp);
9506 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9507 if (d->code == fcode)
9508 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9511 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9512 if (d->code == fcode)
9513 return frv_expand_store_builtin (d->icode, exp);
9519 frv_in_small_data_p (const_tree decl)
9522 const_tree section_name;
9524 /* Don't apply the -G flag to internal compiler structures. We
9525 should leave such structures in the main data section, partly
9526 for efficiency and partly because the size of some of them
9527 (such as C++ typeinfos) is not known until later. */
9528 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9531 /* If we already know which section the decl should be in, see if
9532 it's a small data section. */
9533 section_name = DECL_SECTION_NAME (decl);
9536 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9537 if (frv_string_begins_with (section_name, ".sdata"))
9539 if (frv_string_begins_with (section_name, ".sbss"))
9544 size = int_size_in_bytes (TREE_TYPE (decl));
9545 if (size > 0 && size <= g_switch_value)
9552 frv_rtx_costs (rtx x,
9553 int code ATTRIBUTE_UNUSED,
9554 int outer_code ATTRIBUTE_UNUSED,
9556 bool speed ATTRIBUTE_UNUSED)
9558 if (outer_code == MEM)
9560 /* Don't differentiate between memory addresses. All the ones
9561 we accept have equal cost. */
9562 *total = COSTS_N_INSNS (0);
9569 /* Make 12-bit integers really cheap. */
9570 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9581 *total = COSTS_N_INSNS (2);
9595 if (GET_MODE (x) == SImode)
9596 *total = COSTS_N_INSNS (1);
9597 else if (GET_MODE (x) == DImode)
9598 *total = COSTS_N_INSNS (2);
9600 *total = COSTS_N_INSNS (3);
9604 if (GET_MODE (x) == SImode)
9605 *total = COSTS_N_INSNS (2);
9607 *total = COSTS_N_INSNS (6); /* guess */
9614 *total = COSTS_N_INSNS (18);
9618 *total = COSTS_N_INSNS (3);
9627 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9629 switch_to_section (ctors_section);
9630 assemble_align (POINTER_SIZE);
9633 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9638 assemble_integer_with_op ("\t.picptr\t", symbol);
9642 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9644 switch_to_section (dtors_section);
9645 assemble_align (POINTER_SIZE);
9648 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9653 assemble_integer_with_op ("\t.picptr\t", symbol);
9656 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9659 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9660 int incoming ATTRIBUTE_UNUSED)
9662 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9665 #define TLS_BIAS (2048 - 16)
9667 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9668 We need to emit DTP-relative relocations. */
9671 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9673 gcc_assert (size == 4);
9674 fputs ("\t.picptr\ttlsmoff(", file);
9675 /* We want the unbiased TLS offset, so add the bias to the
9676 expression, such that the implicit biasing cancels out. */
9677 output_addr_const (file, plus_constant (x, TLS_BIAS));