1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand_memory_reference_reg
273 static void frv_print_operand_memory_reference (FILE *, rtx, int);
274 static int frv_print_operand_jump_hint (rtx);
275 static const char *comparison_string (enum rtx_code, rtx);
276 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
277 static rtx single_set_pattern (rtx);
278 static int frv_function_contains_far_jump (void);
279 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
283 static rtx frv_frame_offset_rtx (int);
284 static rtx frv_frame_mem (enum machine_mode, rtx, int);
285 static rtx frv_dwarf_store (rtx, int);
286 static void frv_frame_insn (rtx, rtx);
287 static void frv_frame_access (frv_frame_accessor_t*,
289 static void frv_frame_access_multi (frv_frame_accessor_t*,
291 static void frv_frame_access_standard_regs (enum frv_stack_op,
293 static struct machine_function *frv_init_machine_status (void);
294 static rtx frv_int_to_acc (enum insn_code, int, rtx);
295 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
296 static rtx frv_read_argument (tree, unsigned int);
297 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
298 static int frv_check_constant_argument (enum insn_code, int, rtx);
299 static rtx frv_legitimize_target (enum insn_code, rtx);
300 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
301 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
302 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
303 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
304 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
305 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
306 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
309 static rtx frv_expand_int_void2arg (enum insn_code, tree);
310 static rtx frv_expand_prefetches (enum insn_code, tree);
311 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
312 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
313 static rtx frv_expand_mclracc_builtin (tree);
314 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
315 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
316 static rtx frv_expand_noargs_builtin (enum insn_code);
317 static void frv_split_iacc_move (rtx, rtx);
318 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
319 static int frv_clear_registers_used (rtx *, void *);
320 static void frv_ifcvt_add_insn (rtx, rtx, int);
321 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
322 static rtx frv_ifcvt_load_value (rtx, rtx);
323 static int frv_acc_group_1 (rtx *, void *);
324 static unsigned int frv_insn_unit (rtx);
325 static bool frv_issues_to_branch_unit_p (rtx);
326 static int frv_cond_flags (rtx);
327 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
328 static int frv_registers_conflict_p_1 (rtx *, void *);
329 static bool frv_registers_conflict_p (rtx);
330 static void frv_registers_update_1 (rtx, const_rtx, void *);
331 static void frv_registers_update (rtx);
332 static void frv_start_packet (void);
333 static void frv_start_packet_block (void);
334 static void frv_finish_packet (void (*) (void));
335 static bool frv_pack_insn_p (rtx);
336 static void frv_add_insn_to_packet (rtx);
337 static void frv_insert_nop_in_packet (rtx);
338 static bool frv_for_each_packet (void (*) (void));
339 static bool frv_sort_insn_group_1 (enum frv_insn_group,
340 unsigned int, unsigned int,
341 unsigned int, unsigned int,
343 static int frv_compare_insns (const void *, const void *);
344 static void frv_sort_insn_group (enum frv_insn_group);
345 static void frv_reorder_packet (void);
346 static void frv_fill_unused_units (enum frv_insn_group);
347 static void frv_align_label (void);
348 static void frv_reorg_packet (void);
349 static void frv_register_nop (rtx);
350 static void frv_reorg (void);
351 static void frv_pack_insns (void);
352 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
353 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
354 static bool frv_assemble_integer (rtx, unsigned, int);
355 static void frv_init_builtins (void);
356 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
357 static void frv_init_libfuncs (void);
358 static bool frv_in_small_data_p (const_tree);
359 static void frv_asm_output_mi_thunk
360 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
361 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
364 static rtx frv_expand_builtin_saveregs (void);
365 static void frv_expand_builtin_va_start (tree, rtx);
366 static bool frv_rtx_costs (rtx, int, int, int*, bool);
367 static void frv_asm_out_constructor (rtx, int);
368 static void frv_asm_out_destructor (rtx, int);
369 static bool frv_function_symbol_referenced_p (rtx);
370 static bool frv_cannot_force_const_mem (rtx);
371 static const char *unspec_got_name (int);
372 static void frv_output_const_unspec (FILE *,
373 const struct frv_unspec *);
374 static bool frv_function_ok_for_sibcall (tree, tree);
375 static rtx frv_struct_value_rtx (tree, int);
376 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
377 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
379 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
381 static bool frv_secondary_reload (bool, rtx, enum reg_class,
383 secondary_reload_info *);
384 static bool frv_frame_pointer_required (void);
386 /* Allow us to easily change the default for -malloc-cc. */
387 #ifndef DEFAULT_NO_ALLOC_CC
388 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
390 #define MASK_DEFAULT_ALLOC_CC 0
393 /* Initialize the GCC target structure. */
394 #undef TARGET_ASM_FUNCTION_PROLOGUE
395 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
396 #undef TARGET_ASM_FUNCTION_EPILOGUE
397 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
398 #undef TARGET_ASM_INTEGER
399 #define TARGET_ASM_INTEGER frv_assemble_integer
400 #undef TARGET_DEFAULT_TARGET_FLAGS
401 #define TARGET_DEFAULT_TARGET_FLAGS \
402 (MASK_DEFAULT_ALLOC_CC \
409 #undef TARGET_HANDLE_OPTION
410 #define TARGET_HANDLE_OPTION frv_handle_option
411 #undef TARGET_INIT_BUILTINS
412 #define TARGET_INIT_BUILTINS frv_init_builtins
413 #undef TARGET_EXPAND_BUILTIN
414 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
415 #undef TARGET_INIT_LIBFUNCS
416 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
417 #undef TARGET_IN_SMALL_DATA_P
418 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
419 #undef TARGET_RTX_COSTS
420 #define TARGET_RTX_COSTS frv_rtx_costs
421 #undef TARGET_ASM_CONSTRUCTOR
422 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
423 #undef TARGET_ASM_DESTRUCTOR
424 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
426 #undef TARGET_ASM_OUTPUT_MI_THUNK
427 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
428 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
429 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
431 #undef TARGET_SCHED_ISSUE_RATE
432 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
434 #undef TARGET_LEGITIMIZE_ADDRESS
435 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
437 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
438 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
439 #undef TARGET_CANNOT_FORCE_CONST_MEM
440 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
442 #undef TARGET_HAVE_TLS
443 #define TARGET_HAVE_TLS HAVE_AS_TLS
445 #undef TARGET_STRUCT_VALUE_RTX
446 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
447 #undef TARGET_MUST_PASS_IN_STACK
448 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
449 #undef TARGET_PASS_BY_REFERENCE
450 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
451 #undef TARGET_ARG_PARTIAL_BYTES
452 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
454 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
455 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
456 #undef TARGET_SETUP_INCOMING_VARARGS
457 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
458 #undef TARGET_MACHINE_DEPENDENT_REORG
459 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
461 #undef TARGET_EXPAND_BUILTIN_VA_START
462 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
465 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
466 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
469 #undef TARGET_SECONDARY_RELOAD
470 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
472 #undef TARGET_LEGITIMATE_ADDRESS_P
473 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
475 #undef TARGET_FRAME_POINTER_REQUIRED
476 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
478 struct gcc_target targetm = TARGET_INITIALIZER;
480 #define FRV_SYMBOL_REF_TLS_P(RTX) \
481 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
484 /* Any function call that satisfies the machine-independent
485 requirements is eligible on FR-V. */
488 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
489 tree exp ATTRIBUTE_UNUSED)
494 /* Return true if SYMBOL is a small data symbol and relocation RELOC
495 can be used to access it directly in a load or store. */
497 static FRV_INLINE bool
498 frv_small_data_reloc_p (rtx symbol, int reloc)
500 return (GET_CODE (symbol) == SYMBOL_REF
501 && SYMBOL_REF_SMALL_P (symbol)
502 && (!TARGET_FDPIC || flag_pic == 1)
503 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
506 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
510 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
512 if (GET_CODE (x) == CONST)
516 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
518 unspec->offset += INTVAL (XEXP (x, 1));
521 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
523 unspec->symbol = XVECEXP (x, 0, 0);
524 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
526 if (unspec->offset == 0)
529 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
530 && unspec->offset > 0
531 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
538 /* Decide whether we can force certain constants to memory. If we
539 decide we can't, the caller should be able to cope with it in
542 We never allow constants to be forced into memory for TARGET_FDPIC.
543 This is necessary for several reasons:
545 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
546 target-independent code will try to force them into the constant
547 pool, thus leading to infinite recursion.
549 2. We can never introduce new constant pool references during reload.
550 Any such reference would require use of the pseudo FDPIC register.
552 3. We can't represent a constant added to a function pointer (which is
553 not the same as a pointer to a function+constant).
555 4. In many cases, it's more efficient to calculate the constant in-line. */
558 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
563 /* Implement TARGET_HANDLE_OPTION. */
566 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
571 if (strcmp (arg, "simple") == 0)
572 frv_cpu_type = FRV_CPU_SIMPLE;
573 else if (strcmp (arg, "tomcat") == 0)
574 frv_cpu_type = FRV_CPU_TOMCAT;
575 else if (strcmp (arg, "fr550") == 0)
576 frv_cpu_type = FRV_CPU_FR550;
577 else if (strcmp (arg, "fr500") == 0)
578 frv_cpu_type = FRV_CPU_FR500;
579 else if (strcmp (arg, "fr450") == 0)
580 frv_cpu_type = FRV_CPU_FR450;
581 else if (strcmp (arg, "fr405") == 0)
582 frv_cpu_type = FRV_CPU_FR405;
583 else if (strcmp (arg, "fr400") == 0)
584 frv_cpu_type = FRV_CPU_FR400;
585 else if (strcmp (arg, "fr300") == 0)
586 frv_cpu_type = FRV_CPU_FR300;
587 else if (strcmp (arg, "frv") == 0)
588 frv_cpu_type = FRV_CPU_GENERIC;
599 frv_default_flags_for_cpu (void)
601 switch (frv_cpu_type)
603 case FRV_CPU_GENERIC:
604 return MASK_DEFAULT_FRV;
607 return MASK_DEFAULT_FR550;
611 return MASK_DEFAULT_FR500;
614 return MASK_DEFAULT_FR450;
618 return MASK_DEFAULT_FR400;
622 return MASK_DEFAULT_SIMPLE;
629 /* Sometimes certain combinations of command options do not make
630 sense on a particular target machine. You can define a macro
631 `OVERRIDE_OPTIONS' to take account of this. This macro, if
632 defined, is executed once just after all the command options have
635 Don't use this macro to turn on various extra optimizations for
636 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
639 frv_override_options (void)
644 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
646 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
647 linker about linking pic and non-pic code. */
650 if (!flag_pic) /* -fPIC */
653 if (! g_switch_set) /* -G0 */
660 /* A C expression whose value is a register class containing hard
661 register REGNO. In general there is more than one such class;
662 choose a class which is "minimal", meaning that no smaller class
663 also contains the register. */
665 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
667 enum reg_class rclass;
671 int gpr_reg = regno - GPR_FIRST;
673 if (gpr_reg == GR8_REG)
676 else if (gpr_reg == GR9_REG)
679 else if (gpr_reg == GR14_REG)
680 rclass = FDPIC_FPTR_REGS;
682 else if (gpr_reg == FDPIC_REGNO)
685 else if ((gpr_reg & 3) == 0)
688 else if ((gpr_reg & 1) == 0)
695 else if (FPR_P (regno))
697 int fpr_reg = regno - GPR_FIRST;
698 if ((fpr_reg & 3) == 0)
699 rclass = QUAD_FPR_REGS;
701 else if ((fpr_reg & 1) == 0)
708 else if (regno == LR_REGNO)
711 else if (regno == LCR_REGNO)
714 else if (ICC_P (regno))
717 else if (FCC_P (regno))
720 else if (ICR_P (regno))
723 else if (FCR_P (regno))
726 else if (ACC_P (regno))
728 int r = regno - ACC_FIRST;
730 rclass = QUAD_ACC_REGS;
731 else if ((r & 1) == 0)
732 rclass = EVEN_ACC_REGS;
737 else if (ACCG_P (regno))
743 regno_reg_class[regno] = rclass;
746 /* Check for small data option */
748 g_switch_value = SDATA_DEFAULT_SIZE;
750 /* A C expression which defines the machine-dependent operand
751 constraint letters for register classes. If CHAR is such a
752 letter, the value should be the register class corresponding to
753 it. Otherwise, the value should be `NO_REGS'. The register
754 letter `r', corresponding to class `GENERAL_REGS', will not be
755 passed to this macro; you do not need to handle it.
757 The following letters are unavailable, due to being used as
762 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
763 'Q', 'R', 'S', 'T', 'U'
765 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
767 for (i = 0; i < 256; i++)
768 reg_class_from_letter[i] = NO_REGS;
770 reg_class_from_letter['a'] = ACC_REGS;
771 reg_class_from_letter['b'] = EVEN_ACC_REGS;
772 reg_class_from_letter['c'] = CC_REGS;
773 reg_class_from_letter['d'] = GPR_REGS;
774 reg_class_from_letter['e'] = EVEN_REGS;
775 reg_class_from_letter['f'] = FPR_REGS;
776 reg_class_from_letter['h'] = FEVEN_REGS;
777 reg_class_from_letter['l'] = LR_REG;
778 reg_class_from_letter['q'] = QUAD_REGS;
779 reg_class_from_letter['t'] = ICC_REGS;
780 reg_class_from_letter['u'] = FCC_REGS;
781 reg_class_from_letter['v'] = ICR_REGS;
782 reg_class_from_letter['w'] = FCR_REGS;
783 reg_class_from_letter['x'] = QUAD_FPR_REGS;
784 reg_class_from_letter['y'] = LCR_REG;
785 reg_class_from_letter['z'] = SPR_REGS;
786 reg_class_from_letter['A'] = QUAD_ACC_REGS;
787 reg_class_from_letter['B'] = ACCG_REGS;
788 reg_class_from_letter['C'] = CR_REGS;
789 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
790 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
792 /* There is no single unaligned SI op for PIC code. Sometimes we
793 need to use ".4byte" and sometimes we need to use ".picptr".
794 See frv_assemble_integer for details. */
795 if (flag_pic || TARGET_FDPIC)
796 targetm.asm_out.unaligned_op.si = 0;
798 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
799 target_flags |= MASK_LINKED_FP;
801 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
802 target_flags |= MASK_OPTIMIZE_MEMBAR;
804 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
805 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
807 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
808 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
810 init_machine_status = frv_init_machine_status;
814 /* Some machines may desire to change what optimizations are performed for
815 various optimization levels. This macro, if defined, is executed once just
816 after the optimization level is determined and before the remainder of the
817 command options have been parsed. Values set in this macro are used as the
818 default values for the other command line options.
820 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
821 `-O' is specified, and 0 if neither is specified.
823 SIZE is nonzero if `-Os' is specified, 0 otherwise.
825 You should not use this macro to change options that are not
826 machine-specific. These should uniformly selected by the same optimization
827 level on all supported machines. Use this macro to enable machine-specific
830 *Do not examine `write_symbols' in this macro!* The debugging options are
831 *not supposed to alter the generated code. */
833 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
834 scheduling pass at the current time. */
836 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
840 #ifdef DISABLE_SCHED2
841 flag_schedule_insns_after_reload = 0;
850 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
853 frv_string_begins_with (const_tree name, const char *prefix)
855 const int prefix_len = strlen (prefix);
857 /* Remember: NAME's length includes the null terminator. */
858 return (TREE_STRING_LENGTH (name) > prefix_len
859 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
862 /* Zero or more C statements that may conditionally modify two variables
863 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
864 been initialized from the two preceding macros.
866 This is necessary in case the fixed or call-clobbered registers depend on
869 You need not define this macro if it has no work to do.
871 If the usage of an entire class of registers depends on the target flags,
872 you may indicate this to GCC by using this macro to modify `fixed_regs' and
873 `call_used_regs' to 1 for each of the registers in the classes which should
874 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
875 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
877 (However, if this class is not included in `GENERAL_REGS' and all of the
878 insn patterns whose constraints permit this class are controlled by target
879 switches, then GCC will automatically avoid using these registers when the
880 target switches are opposed to them.) */
883 frv_conditional_register_usage (void)
887 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
888 fixed_regs[i] = call_used_regs[i] = 1;
890 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
891 fixed_regs[i] = call_used_regs[i] = 1;
893 /* Reserve the registers used for conditional execution. At present, we need
894 1 ICC and 1 ICR register. */
895 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
896 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
900 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
901 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
902 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
903 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
907 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
908 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
911 /* If -fpic, SDA_BASE_REG is the PIC register. */
912 if (g_switch_value == 0 && !flag_pic)
913 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
916 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
922 * Compute the stack frame layout
925 * +---------------+-----------------------+-----------------------+
926 * |Register |type |caller-save/callee-save|
927 * +---------------+-----------------------+-----------------------+
928 * |GR0 |Zero register | - |
929 * |GR1 |Stack pointer(SP) | - |
930 * |GR2 |Frame pointer(FP) | - |
931 * |GR3 |Hidden parameter | caller save |
932 * |GR4-GR7 | - | caller save |
933 * |GR8-GR13 |Argument register | caller save |
934 * |GR14-GR15 | - | caller save |
935 * |GR16-GR31 | - | callee save |
936 * |GR32-GR47 | - | caller save |
937 * |GR48-GR63 | - | callee save |
938 * |FR0-FR15 | - | caller save |
939 * |FR16-FR31 | - | callee save |
940 * |FR32-FR47 | - | caller save |
941 * |FR48-FR63 | - | callee save |
942 * +---------------+-----------------------+-----------------------+
946 * SP-> |-----------------------------------|
948 * |-----------------------------------|
949 * | Register save area |
950 * |-----------------------------------|
951 * | Local variable save area |
952 * FP-> |-----------------------------------|
954 * |-----------------------------------|
955 * | Hidden parameter save area |
956 * |-----------------------------------|
957 * | Return address(LR) storage area |
958 * |-----------------------------------|
959 * | Padding for alignment |
960 * |-----------------------------------|
961 * | Register argument area |
962 * OLD SP-> |-----------------------------------|
964 * |-----------------------------------|
967 * Argument area/Parameter area:
969 * When a function is called, this area is used for argument transfer. When
970 * the argument is set up by the caller function, this area is referred to as
971 * the argument area. When the argument is referenced by the callee function,
972 * this area is referred to as the parameter area. The area is allocated when
973 * all arguments cannot be placed on the argument register at the time of
976 * Register save area:
978 * This is a register save area that must be guaranteed for the caller
979 * function. This area is not secured when the register save operation is not
982 * Local variable save area:
984 * This is the area for local variables and temporary variables.
988 * This area stores the FP value of the caller function.
990 * Hidden parameter save area:
992 * This area stores the start address of the return value storage
993 * area for a struct/union return function.
994 * When a struct/union is used as the return value, the caller
995 * function stores the return value storage area start address in
996 * register GR3 and passes it to the caller function.
997 * The callee function interprets the address stored in the GR3
998 * as the return value storage area start address.
999 * When register GR3 needs to be saved into memory, the callee
1000 * function saves it in the hidden parameter save area. This
1001 * area is not secured when the save operation is not needed.
1003 * Return address(LR) storage area:
1005 * This area saves the LR. The LR stores the address of a return to the caller
1006 * function for the purpose of function calling.
1008 * Argument register area:
1010 * This area saves the argument register. This area is not secured when the
1011 * save operation is not needed.
1015 * Arguments, the count of which equals the count of argument registers (6
1016 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1017 * function. When a struct/union return function is called, the return value
1018 * area address is stored in register GR3. Arguments not placed in the
1019 * argument registers will be stored in the stack argument area for transfer
1020 * purposes. When an 8-byte type argument is to be delivered using registers,
1021 * it is divided into two and placed in two registers for transfer. When
1022 * argument registers must be saved to memory, the callee function secures an
1023 * argument register save area in the stack. In this case, a continuous
1024 * argument register save area must be established in the parameter area. The
1025 * argument register save area must be allocated as needed to cover the size of
1026 * the argument register to be saved. If the function has a variable count of
1027 * arguments, it saves all argument registers in the argument register save
1030 * Argument Extension Format:
1032 * When an argument is to be stored in the stack, its type is converted to an
1033 * extended type in accordance with the individual argument type. The argument
1034 * is freed by the caller function after the return from the callee function is
1037 * +-----------------------+---------------+------------------------+
1038 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1039 * +-----------------------+---------------+------------------------+
1041 * |signed char |int | 4 |
1042 * |unsigned char |int | 4 |
1043 * |[signed] short int |int | 4 |
1044 * |unsigned short int |int | 4 |
1045 * |[signed] int |No extension | 4 |
1046 * |unsigned int |No extension | 4 |
1047 * |[signed] long int |No extension | 4 |
1048 * |unsigned long int |No extension | 4 |
1049 * |[signed] long long int |No extension | 8 |
1050 * |unsigned long long int |No extension | 8 |
1051 * |float |double | 8 |
1052 * |double |No extension | 8 |
1053 * |long double |No extension | 8 |
1054 * |pointer |No extension | 4 |
1055 * |struct/union |- | 4 (*1) |
1056 * +-----------------------+---------------+------------------------+
1058 * When a struct/union is to be delivered as an argument, the caller copies it
1059 * to the local variable area and delivers the address of that area.
1063 * +-------------------------------+----------------------+
1064 * |Return Value Type |Return Value Interface|
1065 * +-------------------------------+----------------------+
1067 * |[signed|unsigned] char |GR8 |
1068 * |[signed|unsigned] short int |GR8 |
1069 * |[signed|unsigned] int |GR8 |
1070 * |[signed|unsigned] long int |GR8 |
1072 * |[signed|unsigned] long long int|GR8 & GR9 |
1074 * |double |GR8 & GR9 |
1075 * |long double |GR8 & GR9 |
1076 * |struct/union |(*1) |
1077 * +-------------------------------+----------------------+
1079 * When a struct/union is used as the return value, the caller function stores
1080 * the start address of the return value storage area into GR3 and then passes
1081 * it to the callee function. The callee function interprets GR3 as the start
1082 * address of the return value storage area. When this address needs to be
1083 * saved in memory, the callee function secures the hidden parameter save area
1084 * and saves the address in that area.
1088 frv_stack_info (void)
1090 static frv_stack_t info, zero_info;
1091 frv_stack_t *info_ptr = &info;
1092 tree fndecl = current_function_decl;
1100 /* If we've already calculated the values and reload is complete,
1102 if (frv_stack_cache)
1103 return frv_stack_cache;
1105 /* Zero all fields. */
1108 /* Set up the register range information. */
1109 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1110 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1111 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1112 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1114 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1115 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1116 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1117 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1119 info_ptr->regs[STACK_REGS_LR].name = "lr";
1120 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1121 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1122 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1124 info_ptr->regs[STACK_REGS_CC].name = "cc";
1125 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1126 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1127 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1129 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1130 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1131 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1133 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1134 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1135 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1136 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1137 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1139 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1140 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1141 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1142 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1144 info_ptr->regs[STACK_REGS_FP].name = "fp";
1145 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1146 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1147 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1149 /* Determine if this is a stdarg function. If so, allocate space to store
1156 /* Find the last argument, and see if it is __builtin_va_alist. */
1157 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1159 next_arg = TREE_CHAIN (cur_arg);
1160 if (next_arg == (tree)0)
1162 if (DECL_NAME (cur_arg)
1163 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1171 /* Iterate over all of the register ranges. */
1172 for (range = 0; range < STACK_REGS_MAX; range++)
1174 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1175 int first = reg_ptr->first;
1176 int last = reg_ptr->last;
1178 int size_2words = 0;
1181 /* Calculate which registers need to be saved & save area size. */
1185 for (regno = first; regno <= last; regno++)
1187 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1188 || (crtl->calls_eh_return
1189 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1190 || (!TARGET_FDPIC && flag_pic
1191 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1193 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1194 size_1word += UNITS_PER_WORD;
1199 /* Calculate whether we need to create a frame after everything else
1200 has been processed. */
1205 if (df_regs_ever_live_p (LR_REGNO)
1207 /* This is set for __builtin_return_address, etc. */
1208 || cfun->machine->frame_needed
1209 || (TARGET_LINKED_FP && frame_pointer_needed)
1210 || (!TARGET_FDPIC && flag_pic
1211 && crtl->uses_pic_offset_table))
1213 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1214 size_1word += UNITS_PER_WORD;
1218 case STACK_REGS_STDARG:
1221 /* If this is a stdarg function with a non varardic
1222 argument split between registers and the stack,
1223 adjust the saved registers downward. */
1224 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1227 for (regno = first; regno <= last; regno++)
1229 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1230 size_1word += UNITS_PER_WORD;
1233 info_ptr->stdarg_size = size_1word;
1237 case STACK_REGS_STRUCT:
1238 if (cfun->returns_struct)
1240 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1241 size_1word += UNITS_PER_WORD;
1249 /* If this is a field, it only takes one word. */
1250 if (reg_ptr->field_p)
1251 size_1word = UNITS_PER_WORD;
1253 /* Determine which register pairs can be saved together. */
1254 else if (reg_ptr->dword_p && TARGET_DWORD)
1256 for (regno = first; regno < last; regno += 2)
1258 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1260 size_2words += 2 * UNITS_PER_WORD;
1261 size_1word -= 2 * UNITS_PER_WORD;
1262 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1263 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1268 reg_ptr->size_1word = size_1word;
1269 reg_ptr->size_2words = size_2words;
1271 if (! reg_ptr->special_p)
1273 info_ptr->regs_size_1word += size_1word;
1274 info_ptr->regs_size_2words += size_2words;
1279 /* Set up the sizes of each each field in the frame body, making the sizes
1280 of each be divisible by the size of a dword if dword operations might
1281 be used, or the size of a word otherwise. */
1282 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1284 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1285 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1286 + info_ptr->regs_size_1word,
1288 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1290 info_ptr->pretend_size = crtl->args.pretend_args_size;
1292 /* Work out the size of the frame, excluding the header. Both the frame
1293 body and register parameter area will be dword-aligned. */
1294 info_ptr->total_size
1295 = (ADDR_ALIGN (info_ptr->parameter_size
1296 + info_ptr->regs_size
1297 + info_ptr->vars_size,
1299 + ADDR_ALIGN (info_ptr->pretend_size
1300 + info_ptr->stdarg_size,
1301 2 * UNITS_PER_WORD));
1303 /* See if we need to create a frame at all, if so add header area. */
1304 if (info_ptr->total_size > 0
1305 || frame_pointer_needed
1306 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1307 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1309 offset = info_ptr->parameter_size;
1310 info_ptr->header_size = 4 * UNITS_PER_WORD;
1311 info_ptr->total_size += 4 * UNITS_PER_WORD;
1313 /* Calculate the offsets to save normal register pairs. */
1314 for (range = 0; range < STACK_REGS_MAX; range++)
1316 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1317 if (! reg_ptr->special_p)
1319 int first = reg_ptr->first;
1320 int last = reg_ptr->last;
1323 for (regno = first; regno <= last; regno++)
1324 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1325 && regno != FRAME_POINTER_REGNUM
1326 && (regno < FIRST_ARG_REGNUM
1327 || regno > LAST_ARG_REGNUM))
1329 info_ptr->reg_offset[regno] = offset;
1330 offset += 2 * UNITS_PER_WORD;
1335 /* Calculate the offsets to save normal single registers. */
1336 for (range = 0; range < STACK_REGS_MAX; range++)
1338 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1339 if (! reg_ptr->special_p)
1341 int first = reg_ptr->first;
1342 int last = reg_ptr->last;
1345 for (regno = first; regno <= last; regno++)
1346 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1347 && regno != FRAME_POINTER_REGNUM
1348 && (regno < FIRST_ARG_REGNUM
1349 || regno > LAST_ARG_REGNUM))
1351 info_ptr->reg_offset[regno] = offset;
1352 offset += UNITS_PER_WORD;
1357 /* Calculate the offset to save the local variables at. */
1358 offset = ADDR_ALIGN (offset, alignment);
1359 if (info_ptr->vars_size)
1361 info_ptr->vars_offset = offset;
1362 offset += info_ptr->vars_size;
1365 /* Align header to a dword-boundary. */
1366 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1368 /* Calculate the offsets in the fixed frame. */
1369 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1370 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1371 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1373 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1374 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1375 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1377 if (cfun->returns_struct)
1379 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1380 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1381 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1384 /* Calculate the offsets to store the arguments passed in registers
1385 for stdarg functions. The register pairs are first and the single
1386 register if any is last. The register save area starts on a
1388 if (info_ptr->stdarg_size)
1390 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1391 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1394 /* Skip the header. */
1395 offset += 4 * UNITS_PER_WORD;
1396 for (regno = first; regno <= last; regno++)
1398 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1400 info_ptr->reg_offset[regno] = offset;
1401 offset += 2 * UNITS_PER_WORD;
1403 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1405 info_ptr->reg_offset[regno] = offset;
1406 offset += UNITS_PER_WORD;
1412 if (reload_completed)
1413 frv_stack_cache = info_ptr;
1419 /* Print the information about the frv stack offsets, etc. when debugging. */
1422 frv_debug_stack (frv_stack_t *info)
1427 info = frv_stack_info ();
1429 fprintf (stderr, "\nStack information for function %s:\n",
1430 ((current_function_decl && DECL_NAME (current_function_decl))
1431 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1434 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1435 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1436 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1437 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1438 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1440 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1441 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1442 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1443 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1445 for (range = 0; range < STACK_REGS_MAX; range++)
1447 frv_stack_regs_t *regs = &(info->regs[range]);
1448 if ((regs->size_1word + regs->size_2words) > 0)
1450 int first = regs->first;
1451 int last = regs->last;
1454 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1455 regs->name, regs->size_1word + regs->size_2words,
1456 regs->size_1word, regs->size_2words);
1458 for (regno = first; regno <= last; regno++)
1460 if (info->save_p[regno] == REG_SAVE_1WORD)
1461 fprintf (stderr, " %s (%d)", reg_names[regno],
1462 info->reg_offset[regno]);
1464 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1465 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1466 reg_names[regno+1], info->reg_offset[regno]);
1469 fputc ('\n', stderr);
1479 /* Used during final to control the packing of insns. The value is
1480 1 if the current instruction should be packed with the next one,
1481 0 if it shouldn't or -1 if packing is disabled altogether. */
1483 static int frv_insn_packing_flag;
1485 /* True if the current function contains a far jump. */
1488 frv_function_contains_far_jump (void)
1490 rtx insn = get_insns ();
1492 && !(GET_CODE (insn) == JUMP_INSN
1493 /* Ignore tablejump patterns. */
1494 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1495 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1496 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1497 insn = NEXT_INSN (insn);
1498 return (insn != NULL);
1501 /* For the FRV, this function makes sure that a function with far jumps
1502 will return correctly. It also does the VLIW packing. */
1505 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1507 /* If no frame was created, check whether the function uses a call
1508 instruction to implement a far jump. If so, save the link in gr3 and
1509 replace all returns to LR with returns to GR3. GR3 is used because it
1510 is call-clobbered, because is not available to the register allocator,
1511 and because all functions that take a hidden argument pointer will have
1513 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1517 /* Just to check that the above comment is true. */
1518 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1520 /* Generate the instruction that saves the link register. */
1521 fprintf (file, "\tmovsg lr,gr3\n");
1523 /* Replace the LR with GR3 in *return_internal patterns. The insn
1524 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1525 simply emit a different assembly directive because bralr and jmpl
1526 execute in different units. */
1527 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1528 if (GET_CODE (insn) == JUMP_INSN)
1530 rtx pattern = PATTERN (insn);
1531 if (GET_CODE (pattern) == PARALLEL
1532 && XVECLEN (pattern, 0) >= 2
1533 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1534 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1536 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1537 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1538 SET_REGNO (address, GPR_FIRST + 3);
1545 /* Allow the garbage collector to free the nops created by frv_reorg. */
1546 memset (frv_nops, 0, sizeof (frv_nops));
1550 /* Return the next available temporary register in a given class. */
1553 frv_alloc_temp_reg (
1554 frv_tmp_reg_t *info, /* which registers are available */
1555 enum reg_class rclass, /* register class desired */
1556 enum machine_mode mode, /* mode to allocate register with */
1557 int mark_as_used, /* register not available after allocation */
1558 int no_abort) /* return NULL instead of aborting */
1560 int regno = info->next_reg[ (int)rclass ];
1561 int orig_regno = regno;
1562 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1567 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1568 && TEST_HARD_REG_BIT (info->regs, regno))
1571 if (++regno >= FIRST_PSEUDO_REGISTER)
1573 if (regno == orig_regno)
1575 gcc_assert (no_abort);
1580 nr = HARD_REGNO_NREGS (regno, mode);
1581 info->next_reg[ (int)rclass ] = regno + nr;
1584 for (i = 0; i < nr; i++)
1585 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1587 return gen_rtx_REG (mode, regno);
1591 /* Return an rtx with the value OFFSET, which will either be a register or a
1592 signed 12-bit integer. It can be used as the second operand in an "add"
1593 instruction, or as the index in a load or store.
1595 The function returns a constant rtx if OFFSET is small enough, otherwise
1596 it loads the constant into register OFFSET_REGNO and returns that. */
1598 frv_frame_offset_rtx (int offset)
1600 rtx offset_rtx = GEN_INT (offset);
1601 if (IN_RANGE_P (offset, -2048, 2047))
1605 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1606 if (IN_RANGE_P (offset, -32768, 32767))
1607 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1610 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1611 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1617 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1618 prologue and epilogue uses such expressions to access the stack. */
1620 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1622 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1624 frv_frame_offset_rtx (offset)));
1627 /* Generate a frame-related expression:
1629 (set REG (mem (plus (sp) (const_int OFFSET)))).
1631 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1632 instructions. Marking the expressions as frame-related is superfluous if
1633 the note contains just a single set. But if the note contains a PARALLEL
1634 or SEQUENCE that has several sets, each set must be individually marked
1635 as frame-related. */
1637 frv_dwarf_store (rtx reg, int offset)
1639 rtx set = gen_rtx_SET (VOIDmode,
1640 gen_rtx_MEM (GET_MODE (reg),
1641 plus_constant (stack_pointer_rtx,
1644 RTX_FRAME_RELATED_P (set) = 1;
1648 /* Emit a frame-related instruction whose pattern is PATTERN. The
1649 instruction is the last in a sequence that cumulatively performs the
1650 operation described by DWARF_PATTERN. The instruction is marked as
1651 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1654 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1656 rtx insn = emit_insn (pattern);
1657 RTX_FRAME_RELATED_P (insn) = 1;
1658 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1663 /* Emit instructions that transfer REG to or from the memory location (sp +
1664 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1665 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1666 function to store registers and only the epilogue uses it to load them.
1668 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1669 The generated instruction will use BASE as its base register. BASE may
1670 simply be the stack pointer, but if several accesses are being made to a
1671 region far away from the stack pointer, it may be more efficient to set
1672 up a temporary instead.
1674 Store instructions will be frame-related and will be annotated with the
1675 overall effect of the store. Load instructions will be followed by a
1676 (use) to prevent later optimizations from zapping them.
1678 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1679 as a temporary in such cases. */
1681 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1683 enum machine_mode mode = GET_MODE (reg);
1684 rtx mem = frv_frame_mem (mode,
1686 stack_offset - accessor->base_offset);
1688 if (accessor->op == FRV_LOAD)
1690 if (SPR_P (REGNO (reg)))
1692 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1693 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1694 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1698 /* We cannot use reg+reg addressing for DImode access. */
1700 && GET_CODE (XEXP (mem, 0)) == PLUS
1701 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1702 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1704 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1705 rtx insn = emit_move_insn (temp,
1706 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1707 XEXP (XEXP (mem, 0), 1)));
1708 mem = gen_rtx_MEM (DImode, temp);
1710 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1716 if (SPR_P (REGNO (reg)))
1718 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1719 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1720 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1721 frv_dwarf_store (reg, stack_offset));
1723 else if (mode == DImode)
1725 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1726 with a separate save for each register. */
1727 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1728 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1729 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1730 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1732 /* Also we cannot use reg+reg addressing. */
1733 if (GET_CODE (XEXP (mem, 0)) == PLUS
1734 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1735 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1737 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1738 rtx insn = emit_move_insn (temp,
1739 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1740 XEXP (XEXP (mem, 0), 1)));
1741 mem = gen_rtx_MEM (DImode, temp);
1744 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1745 gen_rtx_PARALLEL (VOIDmode,
1746 gen_rtvec (2, set1, set2)));
1749 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1750 frv_dwarf_store (reg, stack_offset));
1754 /* A function that uses frv_frame_access to transfer a group of registers to
1755 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1756 is the stack information generated by frv_stack_info, and REG_SET is the
1757 number of the register set to transfer. */
1759 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1763 frv_stack_regs_t *regs_info;
1766 regs_info = &info->regs[reg_set];
1767 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1768 if (info->save_p[regno])
1769 frv_frame_access (accessor,
1770 info->save_p[regno] == REG_SAVE_2WORDS
1771 ? gen_rtx_REG (DImode, regno)
1772 : gen_rtx_REG (SImode, regno),
1773 info->reg_offset[regno]);
1776 /* Save or restore callee-saved registers that are kept outside the frame
1777 header. The function saves the registers if OP is FRV_STORE and restores
1778 them if OP is FRV_LOAD. INFO is the stack information generated by
1781 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1783 frv_frame_accessor_t accessor;
1786 accessor.base = stack_pointer_rtx;
1787 accessor.base_offset = 0;
1788 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1789 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1790 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1794 /* Called after register allocation to add any instructions needed for the
1795 prologue. Using a prologue insn is favored compared to putting all of the
1796 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1797 it allows the scheduler to intermix instructions with the saves of
1798 the caller saved registers. In some cases, it might be necessary
1799 to emit a barrier instruction as the last insn to prevent such
1802 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1803 so that the debug info generation code can handle them properly. */
1805 frv_expand_prologue (void)
1807 frv_stack_t *info = frv_stack_info ();
1808 rtx sp = stack_pointer_rtx;
1809 rtx fp = frame_pointer_rtx;
1810 frv_frame_accessor_t accessor;
1812 if (TARGET_DEBUG_STACK)
1813 frv_debug_stack (info);
1815 if (info->total_size == 0)
1818 /* We're interested in three areas of the frame here:
1820 A: the register save area
1822 C: the header after B
1824 If the frame pointer isn't used, we'll have to set up A, B and C
1825 using the stack pointer. If the frame pointer is used, we'll access
1829 B: set up using sp or a temporary (see below)
1832 We set up B using the stack pointer if the frame is small enough.
1833 Otherwise, it's more efficient to copy the old stack pointer into a
1834 temporary and use that.
1836 Note that it's important to make sure the prologue and epilogue use the
1837 same registers to access A and C, since doing otherwise will confuse
1838 the aliasing code. */
1840 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1841 isn't used, the same method will serve for C. */
1842 accessor.op = FRV_STORE;
1843 if (frame_pointer_needed && info->total_size > 2048)
1847 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1848 accessor.base_offset = info->total_size;
1849 insn = emit_insn (gen_movsi (accessor.base, sp));
1853 accessor.base = stack_pointer_rtx;
1854 accessor.base_offset = 0;
1857 /* Allocate the stack space. */
1859 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1860 rtx dwarf_offset = GEN_INT (-info->total_size);
1862 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1865 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1868 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1869 and point the new one to that location. */
1870 if (frame_pointer_needed)
1872 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1874 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1875 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1877 rtx asm_src = plus_constant (accessor.base,
1878 fp_offset - accessor.base_offset);
1879 rtx dwarf_src = plus_constant (sp, fp_offset);
1881 /* Store the old frame pointer at (sp + FP_OFFSET). */
1882 frv_frame_access (&accessor, fp, fp_offset);
1884 /* Set up the new frame pointer. */
1885 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1886 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1888 /* Access region C from the frame pointer. */
1890 accessor.base_offset = fp_offset;
1893 /* Set up region C. */
1894 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1895 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1896 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1898 /* Set up region A. */
1899 frv_frame_access_standard_regs (FRV_STORE, info);
1901 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1902 scheduler from moving loads before the stores saving the registers. */
1903 if (info->stdarg_size > 0)
1904 emit_insn (gen_blockage ());
1906 /* Set up pic register/small data register for this function. */
1907 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1908 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1909 gen_rtx_REG (Pmode, LR_REGNO),
1910 gen_rtx_REG (SImode, OFFSET_REGNO)));
1914 /* Under frv, all of the work is done via frv_expand_epilogue, but
1915 this function provides a convenient place to do cleanup. */
1918 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1919 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1921 frv_stack_cache = (frv_stack_t *)0;
1923 /* Zap last used registers for conditional execution. */
1924 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1926 /* Release the bitmap of created insns. */
1927 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1931 /* Called after register allocation to add any instructions needed for the
1932 epilogue. Using an epilogue insn is favored compared to putting all of the
1933 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1934 it allows the scheduler to intermix instructions with the saves of
1935 the caller saved registers. In some cases, it might be necessary
1936 to emit a barrier instruction as the last insn to prevent such
1940 frv_expand_epilogue (bool emit_return)
1942 frv_stack_t *info = frv_stack_info ();
1943 rtx fp = frame_pointer_rtx;
1944 rtx sp = stack_pointer_rtx;
1948 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1950 /* Restore the stack pointer to its original value if alloca or the like
1952 if (! current_function_sp_is_unchanging)
1953 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1955 /* Restore the callee-saved registers that were used in this function. */
1956 frv_frame_access_standard_regs (FRV_LOAD, info);
1958 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1959 no return instruction should be emitted. */
1960 if (info->save_p[LR_REGNO])
1965 /* Use the same method to access the link register's slot as we did in
1966 the prologue. In other words, use the frame pointer if available,
1967 otherwise use the stack pointer.
1969 LR_OFFSET is the offset of the link register's slot from the start
1970 of the frame and MEM is a memory rtx for it. */
1971 lr_offset = info->reg_offset[LR_REGNO];
1972 if (frame_pointer_needed)
1973 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1975 mem = frv_frame_mem (Pmode, sp, lr_offset);
1977 /* Load the old link register into a GPR. */
1978 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1979 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1982 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1984 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1985 the load is preserved. */
1986 if (frame_pointer_needed)
1988 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1992 /* Deallocate the stack frame. */
1993 if (info->total_size != 0)
1995 rtx offset = frv_frame_offset_rtx (info->total_size);
1996 emit_insn (gen_stack_adjust (sp, sp, offset));
1999 /* If this function uses eh_return, add the final stack adjustment now. */
2000 if (crtl->calls_eh_return)
2001 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2004 emit_jump_insn (gen_epilogue_return (return_addr));
2007 rtx lr = return_addr;
2009 if (REGNO (return_addr) != LR_REGNO)
2011 lr = gen_rtx_REG (Pmode, LR_REGNO);
2012 emit_move_insn (lr, return_addr);
2020 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2023 frv_asm_output_mi_thunk (FILE *file,
2024 tree thunk_fndecl ATTRIBUTE_UNUSED,
2025 HOST_WIDE_INT delta,
2026 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2029 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2030 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2031 const char *name_jmp = reg_names[JUMP_REGNO];
2032 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2034 /* Do the add using an addi if possible. */
2035 if (IN_RANGE_P (delta, -2048, 2047))
2036 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2039 const char *const name_add = reg_names[TEMP_REGNO];
2040 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2041 parallel, delta, name_add);
2042 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2044 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2049 const char *name_pic = reg_names[FDPIC_REGNO];
2050 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2054 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2055 assemble_name (file, name_func);
2056 fprintf (file, "),%s\n", name_jmp);
2058 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2059 assemble_name (file, name_func);
2060 fprintf (file, "),%s\n", name_jmp);
2062 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2066 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2067 assemble_name (file, name_func);
2068 fprintf (file, "\t)), %s\n", name_jmp);
2073 fprintf (file, "\tsethi%s #hi(", parallel);
2074 assemble_name (file, name_func);
2075 fprintf (file, "),%s\n", name_jmp);
2077 fprintf (file, "\tsetlo #lo(");
2078 assemble_name (file, name_func);
2079 fprintf (file, "),%s\n", name_jmp);
2083 /* Use JUMP_REGNO as a temporary PIC register. */
2084 const char *name_lr = reg_names[LR_REGNO];
2085 const char *name_gppic = name_jmp;
2086 const char *name_tmp = reg_names[TEMP_REGNO];
2088 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2089 fprintf (file, "\tcall 1f\n");
2090 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2091 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2092 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2093 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2094 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2096 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2097 assemble_name (file, name_func);
2098 fprintf (file, "),%s\n", name_tmp);
2100 fprintf (file, "\tsetlo #gprello(");
2101 assemble_name (file, name_func);
2102 fprintf (file, "),%s\n", name_tmp);
2104 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2107 /* Jump to the function address. */
2108 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2113 /* On frv, create a frame whenever we need to create stack. */
2116 frv_frame_pointer_required (void)
2118 /* If we forgoing the usual linkage requirements, we only need
2119 a frame pointer if the stack pointer might change. */
2120 if (!TARGET_LINKED_FP)
2121 return !current_function_sp_is_unchanging;
2123 if (! current_function_is_leaf)
2126 if (get_frame_size () != 0)
2132 if (!current_function_sp_is_unchanging)
2135 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2141 if (cfun->machine->frame_needed)
2148 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2149 initial difference between the specified pair of registers. This macro must
2150 be defined if `ELIMINABLE_REGS' is defined. */
2152 /* See frv_stack_info for more details on the frv stack frame. */
2155 frv_initial_elimination_offset (int from, int to)
2157 frv_stack_t *info = frv_stack_info ();
2160 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2161 ret = info->total_size - info->pretend_size;
2163 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2164 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2166 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2167 ret = (info->total_size
2168 - info->reg_offset[FRAME_POINTER_REGNUM]
2169 - info->pretend_size);
2174 if (TARGET_DEBUG_STACK)
2175 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2176 reg_names [from], reg_names[to], ret);
2182 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2185 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2186 enum machine_mode mode,
2187 tree type ATTRIBUTE_UNUSED,
2191 if (TARGET_DEBUG_ARG)
2193 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2194 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2198 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2201 frv_expand_builtin_saveregs (void)
2203 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2205 if (TARGET_DEBUG_ARG)
2206 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2209 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2213 /* Expand __builtin_va_start to do the va_start macro. */
2216 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2219 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2221 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2222 GEN_INT (UNITS_PER_WORD * num));
2224 if (TARGET_DEBUG_ARG)
2226 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2227 crtl->args.info, num);
2229 debug_rtx (nextarg);
2232 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2233 fold_convert (TREE_TYPE (valist),
2234 make_tree (sizetype, nextarg)));
2235 TREE_SIDE_EFFECTS (t) = 1;
2237 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2241 /* Expand a block move operation, and return 1 if successful. Return 0
2242 if we should let the compiler generate normal code.
2244 operands[0] is the destination
2245 operands[1] is the source
2246 operands[2] is the length
2247 operands[3] is the alignment */
2249 /* Maximum number of loads to do before doing the stores */
2250 #ifndef MAX_MOVE_REG
2251 #define MAX_MOVE_REG 4
2254 /* Maximum number of total loads to do. */
2255 #ifndef TOTAL_MOVE_REG
2256 #define TOTAL_MOVE_REG 8
2260 frv_expand_block_move (rtx operands[])
2262 rtx orig_dest = operands[0];
2263 rtx orig_src = operands[1];
2264 rtx bytes_rtx = operands[2];
2265 rtx align_rtx = operands[3];
2266 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2279 rtx stores[MAX_MOVE_REG];
2281 enum machine_mode mode;
2283 /* If this is not a fixed size move, just call memcpy. */
2287 /* This should be a fixed size alignment. */
2288 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2290 align = INTVAL (align_rtx);
2292 /* Anything to move? */
2293 bytes = INTVAL (bytes_rtx);
2297 /* Don't support real large moves. */
2298 if (bytes > TOTAL_MOVE_REG*align)
2301 /* Move the address into scratch registers. */
2302 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2303 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2305 num_reg = offset = 0;
2306 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2308 /* Calculate the correct offset for src/dest. */
2312 dest_addr = dest_reg;
2316 src_addr = plus_constant (src_reg, offset);
2317 dest_addr = plus_constant (dest_reg, offset);
2320 /* Generate the appropriate load and store, saving the stores
2322 if (bytes >= 4 && align >= 4)
2324 else if (bytes >= 2 && align >= 2)
2329 move_bytes = GET_MODE_SIZE (mode);
2330 tmp_reg = gen_reg_rtx (mode);
2331 src_mem = change_address (orig_src, mode, src_addr);
2332 dest_mem = change_address (orig_dest, mode, dest_addr);
2333 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2334 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2336 if (num_reg >= MAX_MOVE_REG)
2338 for (i = 0; i < num_reg; i++)
2339 emit_insn (stores[i]);
2344 for (i = 0; i < num_reg; i++)
2345 emit_insn (stores[i]);
2351 /* Expand a block clear operation, and return 1 if successful. Return 0
2352 if we should let the compiler generate normal code.
2354 operands[0] is the destination
2355 operands[1] is the length
2356 operands[3] is the alignment */
2359 frv_expand_block_clear (rtx operands[])
2361 rtx orig_dest = operands[0];
2362 rtx bytes_rtx = operands[1];
2363 rtx align_rtx = operands[3];
2364 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2373 enum machine_mode mode;
2375 /* If this is not a fixed size move, just call memcpy. */
2379 /* This should be a fixed size alignment. */
2380 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2382 align = INTVAL (align_rtx);
2384 /* Anything to move? */
2385 bytes = INTVAL (bytes_rtx);
2389 /* Don't support real large clears. */
2390 if (bytes > TOTAL_MOVE_REG*align)
2393 /* Move the address into a scratch register. */
2394 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2396 num_reg = offset = 0;
2397 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2399 /* Calculate the correct offset for src/dest. */
2400 dest_addr = ((offset == 0)
2402 : plus_constant (dest_reg, offset));
2404 /* Generate the appropriate store of gr0. */
2405 if (bytes >= 4 && align >= 4)
2407 else if (bytes >= 2 && align >= 2)
2412 clear_bytes = GET_MODE_SIZE (mode);
2413 dest_mem = change_address (orig_dest, mode, dest_addr);
2414 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2421 /* The following variable is used to output modifiers of assembler
2422 code of the current output insn. */
2424 static rtx *frv_insn_operands;
2426 /* The following function is used to add assembler insn code suffix .p
2427 if it is necessary. */
2430 frv_asm_output_opcode (FILE *f, const char *ptr)
2434 if (frv_insn_packing_flag <= 0)
2437 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2440 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2441 || (*ptr >= 'A' && *ptr <= 'Z')))
2443 int letter = *ptr++;
2446 frv_print_operand (f, frv_insn_operands [c], letter);
2447 while ((c = *ptr) >= '0' && c <= '9')
2459 /* Set up the packing bit for the current output insn. Note that this
2460 function is not called for asm insns. */
2463 frv_final_prescan_insn (rtx insn, rtx *opvec,
2464 int noperands ATTRIBUTE_UNUSED)
2468 if (frv_insn_packing_flag >= 0)
2470 frv_insn_operands = opvec;
2471 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2473 else if (recog_memoized (insn) >= 0
2474 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2475 /* Packing optimizations have been disabled, but INSN can only
2476 be issued in M1. Insert an mnop in M0. */
2477 fprintf (asm_out_file, "\tmnop.p\n");
2483 /* A C expression whose value is RTL representing the address in a stack frame
2484 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2485 an RTL expression for the address of the stack frame itself.
2487 If you don't define this macro, the default is to return the value of
2488 FRAMEADDR--that is, the stack frame address is also the address of the stack
2489 word that points to the previous frame. */
2491 /* The default is correct, but we need to make sure the frame gets created. */
2493 frv_dynamic_chain_address (rtx frame)
2495 cfun->machine->frame_needed = 1;
2500 /* A C expression whose value is RTL representing the value of the return
2501 address for the frame COUNT steps up from the current frame, after the
2502 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2503 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2506 The value of the expression must always be the correct address when COUNT is
2507 zero, but may be `NULL_RTX' if there is not way to determine the return
2508 address of other frames. */
2511 frv_return_addr_rtx (int count, rtx frame)
2515 cfun->machine->frame_needed = 1;
2516 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2519 /* Given a memory reference MEMREF, interpret the referenced memory as
2520 an array of MODE values, and return a reference to the element
2521 specified by INDEX. Assume that any pre-modification implicit in
2522 MEMREF has already happened.
2524 MEMREF must be a legitimate operand for modes larger than SImode.
2525 frv_legitimate_address_p forbids register+register addresses, which
2526 this function cannot handle. */
2528 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2530 rtx base = XEXP (memref, 0);
2531 if (GET_CODE (base) == PRE_MODIFY)
2532 base = XEXP (base, 0);
2533 return change_address (memref, mode,
2534 plus_constant (base, index * GET_MODE_SIZE (mode)));
2538 /* Print a memory address as an operand to reference that memory location. */
2540 frv_print_operand_address (FILE * stream, rtx x)
2542 if (GET_CODE (x) == MEM)
2545 switch (GET_CODE (x))
2548 fputs (reg_names [ REGNO (x)], stream);
2552 fprintf (stream, "%ld", (long) INTVAL (x));
2556 assemble_name (stream, XSTR (x, 0));
2561 output_addr_const (stream, x);
2565 /* Poorly constructed asm statements can trigger this alternative.
2566 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2567 frv_print_operand_memory_reference (stream, x, 0);
2574 fatal_insn ("bad insn to frv_print_operand_address:", x);
2579 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2581 int regno = true_regnum (x);
2583 fputs (reg_names[regno], stream);
2585 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2588 /* Print a memory reference suitable for the ld/st instructions. */
2591 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2593 struct frv_unspec unspec;
2597 switch (GET_CODE (x))
2604 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2606 x1 = XEXP (XEXP (x, 1), 1);
2616 if (GET_CODE (x0) == CONST_INT)
2624 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2633 else if (GET_CODE (x1) != CONST_INT)
2634 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2637 fputs ("@(", stream);
2639 fputs (reg_names[GPR_R0], stream);
2640 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2641 frv_print_operand_memory_reference_reg (stream, x0);
2643 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2645 fputs (",", stream);
2647 fputs (reg_names [GPR_R0], stream);
2651 switch (GET_CODE (x1))
2655 frv_print_operand_memory_reference_reg (stream, x1);
2659 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2663 if (!frv_const_unspec_p (x1, &unspec))
2664 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2665 frv_output_const_unspec (stream, &unspec);
2669 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2673 fputs (")", stream);
2677 /* Return 2 for likely branches and 0 for non-likely branches */
2679 #define FRV_JUMP_LIKELY 2
2680 #define FRV_JUMP_NOT_LIKELY 0
2683 frv_print_operand_jump_hint (rtx insn)
2688 HOST_WIDE_INT prob = -1;
2689 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2691 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2693 /* Assume any non-conditional jump is likely. */
2694 if (! any_condjump_p (insn))
2695 ret = FRV_JUMP_LIKELY;
2699 labelref = condjump_label (insn);
2702 rtx label = XEXP (labelref, 0);
2703 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2708 note = find_reg_note (insn, REG_BR_PROB, 0);
2710 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2714 prob = INTVAL (XEXP (note, 0));
2715 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2717 : FRV_JUMP_NOT_LIKELY);
2729 case UNKNOWN: direction = "unknown jump direction"; break;
2730 case BACKWARD: direction = "jump backward"; break;
2731 case FORWARD: direction = "jump forward"; break;
2735 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2736 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2737 (long)INSN_UID (insn), direction, (long)prob,
2738 (long)REG_BR_PROB_BASE, ret);
2746 /* Return the comparison operator to use for CODE given that the ICC
2750 comparison_string (enum rtx_code code, rtx op0)
2752 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2755 default: output_operand_lossage ("bad condition code");
2756 case EQ: return "eq";
2757 case NE: return "ne";
2758 case LT: return is_nz_p ? "n" : "lt";
2759 case LE: return "le";
2760 case GT: return "gt";
2761 case GE: return is_nz_p ? "p" : "ge";
2762 case LTU: return is_nz_p ? "no" : "c";
2763 case LEU: return is_nz_p ? "eq" : "ls";
2764 case GTU: return is_nz_p ? "ne" : "hi";
2765 case GEU: return is_nz_p ? "ra" : "nc";
2769 /* Print an operand to an assembler instruction.
2771 `%' followed by a letter and a digit says to output an operand in an
2772 alternate fashion. Four letters have standard, built-in meanings described
2773 below. The machine description macro `PRINT_OPERAND' can define additional
2774 letters with nonstandard meanings.
2776 `%cDIGIT' can be used to substitute an operand that is a constant value
2777 without the syntax that normally indicates an immediate operand.
2779 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2782 `%aDIGIT' can be used to substitute an operand as if it were a memory
2783 reference, with the actual operand treated as the address. This may be
2784 useful when outputting a "load address" instruction, because often the
2785 assembler syntax for such an instruction requires you to write the operand
2786 as if it were a memory reference.
2788 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2790 `%=' outputs a number which is unique to each instruction in the entire
2791 compilation. This is useful for making local labels to be referred to more
2792 than once in a single template that generates multiple assembler
2795 `%' followed by a punctuation character specifies a substitution that does
2796 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2797 assembler code. Other nonstandard cases can be defined in the
2798 `PRINT_OPERAND' macro. You must also define which punctuation characters
2799 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2802 frv_print_operand (FILE * file, rtx x, int code)
2804 struct frv_unspec unspec;
2805 HOST_WIDE_INT value;
2808 if (code != 0 && !ISALPHA (code))
2811 else if (GET_CODE (x) == CONST_INT)
2814 else if (GET_CODE (x) == CONST_DOUBLE)
2816 if (GET_MODE (x) == SFmode)
2821 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2822 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2826 else if (GET_MODE (x) == VOIDmode)
2827 value = CONST_DOUBLE_LOW (x);
2830 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2841 fputs (reg_names[GPR_R0], file);
2845 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2849 /* Output small data area base register (gr16). */
2850 fputs (reg_names[SDA_BASE_REG], file);
2854 /* Output pic register (gr17). */
2855 fputs (reg_names[PIC_REGNO], file);
2859 /* Output the temporary integer CCR register. */
2860 fputs (reg_names[ICR_TEMP], file);
2864 /* Output the temporary integer CC register. */
2865 fputs (reg_names[ICC_TEMP], file);
2868 /* case 'a': print an address. */
2871 /* Print appropriate test for integer branch false operation. */
2872 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2873 XEXP (x, 0)), file);
2877 /* Print appropriate test for integer branch true operation. */
2878 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2882 /* Print 1 for a NE and 0 for an EQ to give the final argument
2883 for a conditional instruction. */
2884 if (GET_CODE (x) == NE)
2887 else if (GET_CODE (x) == EQ)
2891 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2895 /* Print appropriate test for floating point branch false operation. */
2896 switch (GET_CODE (x))
2899 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2901 case EQ: fputs ("ne", file); break;
2902 case NE: fputs ("eq", file); break;
2903 case LT: fputs ("uge", file); break;
2904 case LE: fputs ("ug", file); break;
2905 case GT: fputs ("ule", file); break;
2906 case GE: fputs ("ul", file); break;
2911 /* Print appropriate test for floating point branch true operation. */
2912 switch (GET_CODE (x))
2915 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2917 case EQ: fputs ("eq", file); break;
2918 case NE: fputs ("ne", file); break;
2919 case LT: fputs ("lt", file); break;
2920 case LE: fputs ("le", file); break;
2921 case GT: fputs ("gt", file); break;
2922 case GE: fputs ("ge", file); break;
2927 /* Print appropriate GOT function. */
2928 if (GET_CODE (x) != CONST_INT)
2929 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2930 fputs (unspec_got_name (INTVAL (x)), file);
2934 /* Print 'i' if the operand is a constant, or is a memory reference that
2936 if (GET_CODE (x) == MEM)
2937 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2938 ? XEXP (XEXP (x, 0), 1)
2940 else if (GET_CODE (x) == PLUS)
2943 switch (GET_CODE (x))
2957 /* For jump instructions, print 'i' if the operand is a constant or
2958 is an expression that adds a constant. */
2959 if (GET_CODE (x) == CONST_INT)
2964 if (GET_CODE (x) == CONST_INT
2965 || (GET_CODE (x) == PLUS
2966 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2967 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2973 /* Print the lower register of a double word register pair */
2974 if (GET_CODE (x) == REG)
2975 fputs (reg_names[ REGNO (x)+1 ], file);
2977 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2980 /* case 'l': print a LABEL_REF. */
2984 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2985 for the second word of double memory operations. */
2986 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2987 switch (GET_CODE (x))
2990 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
2993 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3001 frv_print_operand_memory_reference (file, x, offset);
3007 /* Print the opcode of a command. */
3008 switch (GET_CODE (x))
3011 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3013 case PLUS: fputs ("add", file); break;
3014 case MINUS: fputs ("sub", file); break;
3015 case AND: fputs ("and", file); break;
3016 case IOR: fputs ("or", file); break;
3017 case XOR: fputs ("xor", file); break;
3018 case ASHIFT: fputs ("sll", file); break;
3019 case ASHIFTRT: fputs ("sra", file); break;
3020 case LSHIFTRT: fputs ("srl", file); break;
3024 /* case 'n': negate and print a constant int. */
3027 /* Print PIC label using operand as the number. */
3028 if (GET_CODE (x) != CONST_INT)
3029 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3031 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3035 /* Print 'u' if the operand is a update load/store. */
3036 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3041 /* If value is 0, print gr0, otherwise it must be a register. */
3042 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3043 fputs (reg_names[GPR_R0], file);
3045 else if (GET_CODE (x) == REG)
3046 fputs (reg_names [REGNO (x)], file);
3049 fatal_insn ("bad insn in frv_print_operand, z case", x);
3053 /* Print constant in hex. */
3054 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3056 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3063 if (GET_CODE (x) == REG)
3064 fputs (reg_names [REGNO (x)], file);
3066 else if (GET_CODE (x) == CONST_INT
3067 || GET_CODE (x) == CONST_DOUBLE)
3068 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3070 else if (frv_const_unspec_p (x, &unspec))
3071 frv_output_const_unspec (file, &unspec);
3073 else if (GET_CODE (x) == MEM)
3074 frv_print_operand_address (file, XEXP (x, 0));
3076 else if (CONSTANT_ADDRESS_P (x))
3077 frv_print_operand_address (file, x);
3080 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3085 fatal_insn ("frv_print_operand: unknown code", x);
3093 /* A C statement (sans semicolon) for initializing the variable CUM for the
3094 state at the beginning of the argument list. The variable has type
3095 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3096 of the function which will receive the args, or 0 if the args are to a
3097 compiler support library function. The value of INDIRECT is nonzero when
3098 processing an indirect call, for example a call through a function pointer.
3099 The value of INDIRECT is zero for a call to an explicitly named function, a
3100 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3101 arguments for the function being compiled.
3103 When processing a call to a compiler support library function, LIBNAME
3104 identifies which one. It is a `symbol_ref' rtx which contains the name of
3105 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3106 being processed. Thus, each time this macro is called, either LIBNAME or
3107 FNTYPE is nonzero, but never both of them at once. */
3110 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3116 *cum = FIRST_ARG_REGNUM;
3118 if (TARGET_DEBUG_ARG)
3120 fprintf (stderr, "\ninit_cumulative_args:");
3121 if (!fndecl && fntype)
3122 fputs (" indirect", stderr);
3125 fputs (" incoming", stderr);
3129 tree ret_type = TREE_TYPE (fntype);
3130 fprintf (stderr, " return=%s,",
3131 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3134 if (libname && GET_CODE (libname) == SYMBOL_REF)
3135 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3137 if (cfun->returns_struct)
3138 fprintf (stderr, " return-struct");
3140 putc ('\n', stderr);
3145 /* Return true if we should pass an argument on the stack rather than
3149 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3151 if (mode == BLKmode)
3155 return AGGREGATE_TYPE_P (type);
3158 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3159 argument with the specified mode and type. If it is not defined,
3160 `PARM_BOUNDARY' is used for all arguments. */
3163 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3164 tree type ATTRIBUTE_UNUSED)
3166 return BITS_PER_WORD;
3170 frv_function_arg (CUMULATIVE_ARGS *cum,
3171 enum machine_mode mode,
3172 tree type ATTRIBUTE_UNUSED,
3174 int incoming ATTRIBUTE_UNUSED)
3176 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3181 /* Return a marker for use in the call instruction. */
3182 if (xmode == VOIDmode)
3188 else if (arg_num <= LAST_ARG_REGNUM)
3190 ret = gen_rtx_REG (xmode, arg_num);
3191 debstr = reg_names[arg_num];
3200 if (TARGET_DEBUG_ARG)
3202 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3203 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3209 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3210 advance past an argument in the argument list. The values MODE, TYPE and
3211 NAMED describe that argument. Once this is done, the variable CUM is
3212 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3214 This macro need not do anything if the argument in question was passed on
3215 the stack. The compiler knows how to track the amount of stack space used
3216 for arguments without any special help. */
3219 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3220 enum machine_mode mode,
3221 tree type ATTRIBUTE_UNUSED,
3224 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3225 int bytes = GET_MODE_SIZE (xmode);
3226 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3229 *cum = arg_num + words;
3231 if (TARGET_DEBUG_ARG)
3233 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3234 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3238 /* A C expression for the number of words, at the beginning of an argument,
3239 must be put in registers. The value must be zero for arguments that are
3240 passed entirely in registers or that are entirely pushed on the stack.
3242 On some machines, certain arguments must be passed partially in registers
3243 and partially in memory. On these machines, typically the first N words of
3244 arguments are passed in registers, and the rest on the stack. If a
3245 multi-word argument (a `double' or a structure) crosses that boundary, its
3246 first few words must be passed in registers and the rest must be pushed.
3247 This macro tells the compiler when this occurs, and how many of the words
3248 should go in registers.
3250 `FUNCTION_ARG' for these arguments should return the first register to be
3251 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3252 the called function. */
3255 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3256 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3258 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3259 int bytes = GET_MODE_SIZE (xmode);
3260 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3264 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3265 ? LAST_ARG_REGNUM - arg_num + 1
3267 ret *= UNITS_PER_WORD;
3269 if (TARGET_DEBUG_ARG && ret)
3270 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3276 /* Return true if a register is ok to use as a base or index register. */
3278 static FRV_INLINE int
3279 frv_regno_ok_for_base_p (int regno, int strict_p)
3285 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3287 if (regno == ARG_POINTER_REGNUM)
3290 return (regno >= FIRST_PSEUDO_REGISTER);
3294 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3295 RTX) is a legitimate memory address on the target machine for a memory
3296 operand of mode MODE.
3298 It usually pays to define several simpler macros to serve as subroutines for
3299 this one. Otherwise it may be too complicated to understand.
3301 This macro must exist in two variants: a strict variant and a non-strict
3302 one. The strict variant is used in the reload pass. It must be defined so
3303 that any pseudo-register that has not been allocated a hard register is
3304 considered a memory reference. In contexts where some kind of register is
3305 required, a pseudo-register with no hard register must be rejected.
3307 The non-strict variant is used in other passes. It must be defined to
3308 accept all pseudo-registers in every context where some kind of register is
3311 Compiler source files that want to use the strict variant of this macro
3312 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3313 conditional to define the strict variant in that case and the non-strict
3316 Normally, constant addresses which are the sum of a `symbol_ref' and an
3317 integer are stored inside a `const' RTX to mark them as constant.
3318 Therefore, there is no need to recognize such sums specifically as
3319 legitimate addresses. Normally you would simply recognize any `const' as
3322 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3323 are not marked with `const'. It assumes that a naked `plus' indicates
3324 indexing. If so, then you *must* reject such naked constant sums as
3325 illegitimate addresses, so that none of them will be given to
3326 `PRINT_OPERAND_ADDRESS'. */
3329 frv_legitimate_address_p_1 (enum machine_mode mode,
3333 int allow_double_reg_p)
3337 HOST_WIDE_INT value;
3340 if (FRV_SYMBOL_REF_TLS_P (x))
3343 switch (GET_CODE (x))
3350 if (GET_CODE (x) != REG)
3356 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3362 if (GET_CODE (x0) != REG
3363 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3364 || GET_CODE (x1) != PLUS
3365 || ! rtx_equal_p (x0, XEXP (x1, 0))
3366 || GET_CODE (XEXP (x1, 1)) != REG
3367 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3374 /* 12-bit immediate */
3379 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3381 /* If we can't use load/store double operations, make sure we can
3382 address the second word. */
3383 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3384 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3393 if (GET_CODE (x0) == SUBREG)
3394 x0 = SUBREG_REG (x0);
3396 if (GET_CODE (x0) != REG)
3399 regno0 = REGNO (x0);
3400 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3403 switch (GET_CODE (x1))
3409 x1 = SUBREG_REG (x1);
3410 if (GET_CODE (x1) != REG)
3416 /* Do not allow reg+reg addressing for modes > 1 word if we
3417 can't depend on having move double instructions. */
3418 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3421 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3425 /* 12-bit immediate */
3430 value = INTVAL (x1);
3431 ret = IN_RANGE_P (value, -2048, 2047);
3433 /* If we can't use load/store double operations, make sure we can
3434 address the second word. */
3435 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3436 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3441 if (!condexec_p && got12_operand (x1, VOIDmode))
3449 if (TARGET_DEBUG_ADDR)
3451 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3452 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3453 (condexec_p) ? ", inside conditional code" : "");
3461 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3463 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3466 /* Given an ADDR, generate code to inline the PLT. */
3468 gen_inlined_tls_plt (rtx addr)
3471 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3474 dest = gen_reg_rtx (DImode);
3481 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3482 calll #gettlsoff(ADDR)@(gr8, gr0)
3484 emit_insn (gen_tls_lddi (dest, addr, picreg));
3491 sethi.p #gottlsdeschi(ADDR), gr8
3492 setlo #gottlsdesclo(ADDR), gr8
3493 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3494 calll #gettlsoff(ADDR)@(gr8, gr0)
3496 rtx reguse = gen_reg_rtx (Pmode);
3497 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3498 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3501 retval = gen_reg_rtx (Pmode);
3502 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3506 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3507 the destination address. */
3509 gen_tlsmoff (rtx addr, rtx reg)
3511 rtx dest = gen_reg_rtx (Pmode);
3515 /* sethi.p #tlsmoffhi(x), grA
3516 setlo #tlsmofflo(x), grA
3518 dest = gen_reg_rtx (Pmode);
3519 emit_insn (gen_tlsoff_hilo (dest, addr,
3520 GEN_INT (R_FRV_TLSMOFFHI)));
3521 dest = gen_rtx_PLUS (Pmode, dest, reg);
3525 /* addi grB, #tlsmoff12(x), grC
3527 ld/st @(grB, #tlsmoff12(x)), grC
3529 dest = gen_reg_rtx (Pmode);
3530 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3531 GEN_INT (R_FRV_TLSMOFF12)));
3536 /* Generate code for a TLS address. */
3538 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3540 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3541 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3545 case TLS_MODEL_INITIAL_EXEC:
3549 ldi @(gr15, #gottlsoff12(x)), gr5
3551 dest = gen_reg_rtx (Pmode);
3552 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3553 dest = gen_rtx_PLUS (Pmode, tp, dest);
3557 /* -fPIC or anything else.
3559 sethi.p #gottlsoffhi(x), gr14
3560 setlo #gottlsofflo(x), gr14
3561 ld #tlsoff(x)@(gr15, gr14), gr9
3563 rtx tmp = gen_reg_rtx (Pmode);
3564 dest = gen_reg_rtx (Pmode);
3565 emit_insn (gen_tlsoff_hilo (tmp, addr,
3566 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3568 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3569 dest = gen_rtx_PLUS (Pmode, tp, dest);
3572 case TLS_MODEL_LOCAL_DYNAMIC:
3576 if (TARGET_INLINE_PLT)
3577 retval = gen_inlined_tls_plt (GEN_INT (0));
3580 /* call #gettlsoff(0) */
3581 retval = gen_reg_rtx (Pmode);
3582 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3585 reg = gen_reg_rtx (Pmode);
3586 emit_insn (gen_rtx_SET (VOIDmode, reg,
3587 gen_rtx_PLUS (Pmode,
3590 dest = gen_tlsmoff (addr, reg);
3593 dest = gen_reg_rtx (Pmode);
3594 emit_insn (gen_tlsoff_hilo (dest, addr,
3595 GEN_INT (R_FRV_TLSMOFFHI)));
3596 dest = gen_rtx_PLUS (Pmode, dest, reg);
3600 case TLS_MODEL_LOCAL_EXEC:
3601 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3603 case TLS_MODEL_GLOBAL_DYNAMIC:
3607 if (TARGET_INLINE_PLT)
3608 retval = gen_inlined_tls_plt (addr);
3611 /* call #gettlsoff(x) */
3612 retval = gen_reg_rtx (Pmode);
3613 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3615 dest = gen_rtx_PLUS (Pmode, retval, tp);
3626 frv_legitimize_address (rtx x,
3627 rtx oldx ATTRIBUTE_UNUSED,
3628 enum machine_mode mode ATTRIBUTE_UNUSED)
3630 if (GET_CODE (x) == SYMBOL_REF)
3632 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3634 return frv_legitimize_tls_address (x, model);
3640 /* Test whether a local function descriptor is canonical, i.e.,
3641 whether we can use FUNCDESC_GOTOFF to compute the address of the
3645 frv_local_funcdesc_p (rtx fnx)
3648 enum symbol_visibility vis;
3651 if (! SYMBOL_REF_LOCAL_P (fnx))
3654 fn = SYMBOL_REF_DECL (fnx);
3659 vis = DECL_VISIBILITY (fn);
3661 if (vis == VISIBILITY_PROTECTED)
3662 /* Private function descriptors for protected functions are not
3663 canonical. Temporarily change the visibility to global. */
3664 vis = VISIBILITY_DEFAULT;
3665 else if (flag_shlib)
3666 /* If we're already compiling for a shared library (that, unlike
3667 executables, can't assume that the existence of a definition
3668 implies local binding), we can skip the re-testing. */
3671 ret = default_binds_local_p_1 (fn, flag_pic);
3673 DECL_VISIBILITY (fn) = vis;
3678 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3682 frv_gen_GPsym2reg (rtx dest, rtx src)
3684 tree gp = get_identifier ("_gp");
3685 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3687 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3691 unspec_got_name (int i)
3695 case R_FRV_GOT12: return "got12";
3696 case R_FRV_GOTHI: return "gothi";
3697 case R_FRV_GOTLO: return "gotlo";
3698 case R_FRV_FUNCDESC: return "funcdesc";
3699 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3700 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3701 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3702 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3703 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3704 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3705 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3706 case R_FRV_GOTOFF12: return "gotoff12";
3707 case R_FRV_GOTOFFHI: return "gotoffhi";
3708 case R_FRV_GOTOFFLO: return "gotofflo";
3709 case R_FRV_GPREL12: return "gprel12";
3710 case R_FRV_GPRELHI: return "gprelhi";
3711 case R_FRV_GPRELLO: return "gprello";
3712 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3713 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3714 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3715 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3716 case R_FRV_TLSMOFF12: return "tlsmoff12";
3717 case R_FRV_TLSDESCHI: return "tlsdeschi";
3718 case R_FRV_TLSDESCLO: return "tlsdesclo";
3719 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3720 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3721 default: gcc_unreachable ();
3725 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3726 is added inside the relocation operator. */
3729 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3731 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3732 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3733 fputs (")", stream);
3736 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3737 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3738 otherwise return ORIG_X. */
3741 frv_find_base_term (rtx x)
3743 struct frv_unspec unspec;
3745 if (frv_const_unspec_p (x, &unspec)
3746 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3747 return plus_constant (unspec.symbol, unspec.offset);
3752 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3753 the operand is used by a predicated instruction. */
3756 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3758 return ((GET_MODE (op) == mode || mode == VOIDmode)
3759 && GET_CODE (op) == MEM
3760 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3761 reload_completed, condexec_p, FALSE));
3765 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3767 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3768 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3774 rvrtx = operands[0];
3778 addr = XEXP (operands[0], 0);
3780 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3781 any calls that would involve a PLT, but can't tell, since we
3782 don't know whether an extern function is going to be provided by
3783 a separate translation unit or imported from a separate module.
3784 When compiling for shared libraries, if the function has default
3785 visibility, we assume it's overridable, so we inline the PLT, but
3786 for executables, we don't really have a way to make a good
3787 decision: a function is as likely to be imported from a shared
3788 library as it is to be defined in the executable itself. We
3789 assume executables will get global functions defined locally,
3790 whereas shared libraries will have them potentially overridden,
3791 so we only inline PLTs when compiling for shared libraries.
3793 In order to mark a function as local to a shared library, any
3794 non-default visibility attribute suffices. Unfortunately,
3795 there's no simple way to tag a function declaration as ``in a
3796 different module'', which we could then use to trigger PLT
3797 inlining on executables. There's -minline-plt, but it affects
3798 all external functions, so one would have to also mark function
3799 declarations available in the same module with non-default
3800 visibility, which is advantageous in itself. */
3801 if (GET_CODE (addr) == SYMBOL_REF
3802 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3806 dest = gen_reg_rtx (SImode);
3808 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3809 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3811 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3812 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3814 crtl->uses_pic_offset_table = TRUE;
3817 else if (GET_CODE (addr) == SYMBOL_REF)
3819 /* These are always either local, or handled through a local
3822 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3823 operands[2], picreg, lr);
3825 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3829 else if (! ldd_address_operand (addr, Pmode))
3830 addr = force_reg (Pmode, addr);
3832 picreg = gen_reg_rtx (DImode);
3833 emit_insn (gen_movdi_ldd (picreg, addr));
3835 if (sibcall && ret_value)
3836 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3838 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3840 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3842 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3846 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3847 process these separately from any offsets, such that we add any
3848 offsets to the function descriptor (the actual pointer), not to the
3849 function address. */
3852 frv_function_symbol_referenced_p (rtx x)
3858 if (GET_CODE (x) == SYMBOL_REF)
3859 return SYMBOL_REF_FUNCTION_P (x);
3861 length = GET_RTX_LENGTH (GET_CODE (x));
3862 format = GET_RTX_FORMAT (GET_CODE (x));
3864 for (j = 0; j < length; ++j)
3869 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3875 if (XVEC (x, j) != 0)
3878 for (k = 0; k < XVECLEN (x, j); ++k)
3879 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3885 /* Nothing to do. */
3893 /* Return true if the memory operand is one that can be conditionally
3897 condexec_memory_operand (rtx op, enum machine_mode mode)
3899 enum machine_mode op_mode = GET_MODE (op);
3902 if (mode != VOIDmode && op_mode != mode)
3917 if (GET_CODE (op) != MEM)
3920 addr = XEXP (op, 0);
3921 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3924 /* Return true if the bare return instruction can be used outside of the
3925 epilog code. For frv, we only do it if there was no stack allocation. */
3928 direct_return_p (void)
3932 if (!reload_completed)
3935 info = frv_stack_info ();
3936 return (info->total_size == 0);
3941 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3943 if (GET_CODE (src) == SYMBOL_REF)
3945 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3947 src = frv_legitimize_tls_address (src, model);
3953 if (frv_emit_movsi (dest, src))
3962 if (!reload_in_progress
3963 && !reload_completed
3964 && !register_operand (dest, mode)
3965 && !reg_or_0_operand (src, mode))
3966 src = copy_to_mode_reg (mode, src);
3973 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3976 /* Emit code to handle a MOVSI, adding in the small data register or pic
3977 register if needed to load up addresses. Return TRUE if the appropriate
3978 instructions are emitted. */
3981 frv_emit_movsi (rtx dest, rtx src)
3983 int base_regno = -1;
3986 struct frv_unspec old_unspec;
3988 if (!reload_in_progress
3989 && !reload_completed
3990 && !register_operand (dest, SImode)
3991 && (!reg_or_0_operand (src, SImode)
3992 /* Virtual registers will almost always be replaced by an
3993 add instruction, so expose this to CSE by copying to
3994 an intermediate register. */
3995 || (GET_CODE (src) == REG
3996 && IN_RANGE_P (REGNO (src),
3997 FIRST_VIRTUAL_REGISTER,
3998 LAST_VIRTUAL_REGISTER))))
4000 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4004 /* Explicitly add in the PIC or small data register if needed. */
4005 switch (GET_CODE (src))
4014 /* Using GPREL12, we use a single GOT entry for all symbols
4015 in read-only sections, but trade sequences such as:
4017 sethi #gothi(label), gr#
4018 setlo #gotlo(label), gr#
4023 ld @(gr15,#got12(_gp)), gr#
4024 sethi #gprelhi(label), gr##
4025 setlo #gprello(label), gr##
4028 We may often be able to share gr# for multiple
4029 computations of GPREL addresses, and we may often fold
4030 the final add into the pair of registers of a load or
4031 store instruction, so it's often profitable. Even when
4032 optimizing for size, we're trading a GOT entry for an
4033 additional instruction, which trades GOT space
4034 (read-write) for code size (read-only, shareable), as
4035 long as the symbol is not used in more than two different
4038 With -fpie/-fpic, we'd be trading a single load for a
4039 sequence of 4 instructions, because the offset of the
4040 label can't be assumed to be addressable with 12 bits, so
4041 we don't do this. */
4042 if (TARGET_GPREL_RO)
4043 unspec = R_FRV_GPREL12;
4045 unspec = R_FRV_GOT12;
4048 base_regno = PIC_REGNO;
4053 if (frv_const_unspec_p (src, &old_unspec))
4056 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4059 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4060 emit_move_insn (dest, src);
4065 sym = XEXP (sym, 0);
4066 if (GET_CODE (sym) == PLUS
4067 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4068 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4069 sym = XEXP (sym, 0);
4070 if (GET_CODE (sym) == SYMBOL_REF)
4072 else if (GET_CODE (sym) == LABEL_REF)
4075 goto handle_whatever;
4083 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4087 src = frv_legitimize_tls_address (src, model);
4088 emit_move_insn (dest, src);
4092 if (SYMBOL_REF_FUNCTION_P (sym))
4094 if (frv_local_funcdesc_p (sym))
4095 unspec = R_FRV_FUNCDESC_GOTOFF12;
4097 unspec = R_FRV_FUNCDESC_GOT12;
4101 if (CONSTANT_POOL_ADDRESS_P (sym))
4102 switch (GET_CODE (get_pool_constant (sym)))
4109 unspec = R_FRV_GOTOFF12;
4114 if (TARGET_GPREL_RO)
4115 unspec = R_FRV_GPREL12;
4117 unspec = R_FRV_GOT12;
4120 else if (SYMBOL_REF_LOCAL_P (sym)
4121 && !SYMBOL_REF_EXTERNAL_P (sym)
4122 && SYMBOL_REF_DECL (sym)
4123 && (!DECL_P (SYMBOL_REF_DECL (sym))
4124 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4126 tree decl = SYMBOL_REF_DECL (sym);
4127 tree init = TREE_CODE (decl) == VAR_DECL
4128 ? DECL_INITIAL (decl)
4129 : TREE_CODE (decl) == CONSTRUCTOR
4132 bool named_section, readonly;
4134 if (init && init != error_mark_node)
4135 reloc = compute_reloc_for_constant (init);
4137 named_section = TREE_CODE (decl) == VAR_DECL
4138 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4139 readonly = decl_readonly_section (decl, reloc);
4142 unspec = R_FRV_GOT12;
4144 unspec = R_FRV_GOTOFF12;
4145 else if (readonly && TARGET_GPREL_RO)
4146 unspec = R_FRV_GPREL12;
4148 unspec = R_FRV_GOT12;
4151 unspec = R_FRV_GOT12;
4155 else if (SYMBOL_REF_SMALL_P (sym))
4156 base_regno = SDA_BASE_REG;
4159 base_regno = PIC_REGNO;
4164 if (base_regno >= 0)
4166 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4167 emit_insn (gen_symGOTOFF2reg (dest, src,
4168 gen_rtx_REG (Pmode, base_regno),
4169 GEN_INT (R_FRV_GPREL12)));
4171 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4172 gen_rtx_REG (Pmode, base_regno),
4173 GEN_INT (R_FRV_GPREL12)));
4174 if (base_regno == PIC_REGNO)
4175 crtl->uses_pic_offset_table = TRUE;
4183 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4184 new uses of it once reload has begun. */
4185 gcc_assert (!reload_in_progress && !reload_completed);
4189 case R_FRV_GOTOFF12:
4190 if (!frv_small_data_reloc_p (sym, unspec))
4191 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4194 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4197 if (!frv_small_data_reloc_p (sym, unspec))
4198 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4201 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4203 case R_FRV_FUNCDESC_GOTOFF12:
4205 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4208 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4212 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4215 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4219 crtl->uses_pic_offset_table = TRUE;
4228 /* Return a string to output a single word move. */
4231 output_move_single (rtx operands[], rtx insn)
4233 rtx dest = operands[0];
4234 rtx src = operands[1];
4236 if (GET_CODE (dest) == REG)
4238 int dest_regno = REGNO (dest);
4239 enum machine_mode mode = GET_MODE (dest);
4241 if (GPR_P (dest_regno))
4243 if (GET_CODE (src) == REG)
4245 /* gpr <- some sort of register */
4246 int src_regno = REGNO (src);
4248 if (GPR_P (src_regno))
4249 return "mov %1, %0";
4251 else if (FPR_P (src_regno))
4252 return "movfg %1, %0";
4254 else if (SPR_P (src_regno))
4255 return "movsg %1, %0";
4258 else if (GET_CODE (src) == MEM)
4267 return "ldsb%I1%U1 %M1,%0";
4270 return "ldsh%I1%U1 %M1,%0";
4274 return "ld%I1%U1 %M1, %0";
4278 else if (GET_CODE (src) == CONST_INT
4279 || GET_CODE (src) == CONST_DOUBLE)
4281 /* gpr <- integer/floating constant */
4282 HOST_WIDE_INT value;
4284 if (GET_CODE (src) == CONST_INT)
4285 value = INTVAL (src);
4287 else if (mode == SFmode)
4292 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4293 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4298 value = CONST_DOUBLE_LOW (src);
4300 if (IN_RANGE_P (value, -32768, 32767))
4301 return "setlos %1, %0";
4306 else if (GET_CODE (src) == SYMBOL_REF
4307 || GET_CODE (src) == LABEL_REF
4308 || GET_CODE (src) == CONST)
4314 else if (FPR_P (dest_regno))
4316 if (GET_CODE (src) == REG)
4318 /* fpr <- some sort of register */
4319 int src_regno = REGNO (src);
4321 if (GPR_P (src_regno))
4322 return "movgf %1, %0";
4324 else if (FPR_P (src_regno))
4326 if (TARGET_HARD_FLOAT)
4327 return "fmovs %1, %0";
4329 return "mor %1, %1, %0";
4333 else if (GET_CODE (src) == MEM)
4342 return "ldbf%I1%U1 %M1,%0";
4345 return "ldhf%I1%U1 %M1,%0";
4349 return "ldf%I1%U1 %M1, %0";
4353 else if (ZERO_P (src))
4354 return "movgf %., %0";
4357 else if (SPR_P (dest_regno))
4359 if (GET_CODE (src) == REG)
4361 /* spr <- some sort of register */
4362 int src_regno = REGNO (src);
4364 if (GPR_P (src_regno))
4365 return "movgs %1, %0";
4367 else if (ZERO_P (src))
4368 return "movgs %., %0";
4372 else if (GET_CODE (dest) == MEM)
4374 if (GET_CODE (src) == REG)
4376 int src_regno = REGNO (src);
4377 enum machine_mode mode = GET_MODE (dest);
4379 if (GPR_P (src_regno))
4387 return "stb%I0%U0 %1, %M0";
4390 return "sth%I0%U0 %1, %M0";
4394 return "st%I0%U0 %1, %M0";
4398 else if (FPR_P (src_regno))
4406 return "stbf%I0%U0 %1, %M0";
4409 return "sthf%I0%U0 %1, %M0";
4413 return "stf%I0%U0 %1, %M0";
4418 else if (ZERO_P (src))
4420 switch (GET_MODE (dest))
4426 return "stb%I0%U0 %., %M0";
4429 return "sth%I0%U0 %., %M0";
4433 return "st%I0%U0 %., %M0";
4438 fatal_insn ("bad output_move_single operand", insn);
4443 /* Return a string to output a double word move. */
4446 output_move_double (rtx operands[], rtx insn)
4448 rtx dest = operands[0];
4449 rtx src = operands[1];
4450 enum machine_mode mode = GET_MODE (dest);
4452 if (GET_CODE (dest) == REG)
4454 int dest_regno = REGNO (dest);
4456 if (GPR_P (dest_regno))
4458 if (GET_CODE (src) == REG)
4460 /* gpr <- some sort of register */
4461 int src_regno = REGNO (src);
4463 if (GPR_P (src_regno))
4466 else if (FPR_P (src_regno))
4468 if (((dest_regno - GPR_FIRST) & 1) == 0
4469 && ((src_regno - FPR_FIRST) & 1) == 0)
4470 return "movfgd %1, %0";
4476 else if (GET_CODE (src) == MEM)
4479 if (dbl_memory_one_insn_operand (src, mode))
4480 return "ldd%I1%U1 %M1, %0";
4485 else if (GET_CODE (src) == CONST_INT
4486 || GET_CODE (src) == CONST_DOUBLE)
4490 else if (FPR_P (dest_regno))
4492 if (GET_CODE (src) == REG)
4494 /* fpr <- some sort of register */
4495 int src_regno = REGNO (src);
4497 if (GPR_P (src_regno))
4499 if (((dest_regno - FPR_FIRST) & 1) == 0
4500 && ((src_regno - GPR_FIRST) & 1) == 0)
4501 return "movgfd %1, %0";
4506 else if (FPR_P (src_regno))
4509 && ((dest_regno - FPR_FIRST) & 1) == 0
4510 && ((src_regno - FPR_FIRST) & 1) == 0)
4511 return "fmovd %1, %0";
4517 else if (GET_CODE (src) == MEM)
4520 if (dbl_memory_one_insn_operand (src, mode))
4521 return "lddf%I1%U1 %M1, %0";
4526 else if (ZERO_P (src))
4531 else if (GET_CODE (dest) == MEM)
4533 if (GET_CODE (src) == REG)
4535 int src_regno = REGNO (src);
4537 if (GPR_P (src_regno))
4539 if (((src_regno - GPR_FIRST) & 1) == 0
4540 && dbl_memory_one_insn_operand (dest, mode))
4541 return "std%I0%U0 %1, %M0";
4546 if (FPR_P (src_regno))
4548 if (((src_regno - FPR_FIRST) & 1) == 0
4549 && dbl_memory_one_insn_operand (dest, mode))
4550 return "stdf%I0%U0 %1, %M0";
4556 else if (ZERO_P (src))
4558 if (dbl_memory_one_insn_operand (dest, mode))
4559 return "std%I0%U0 %., %M0";
4565 fatal_insn ("bad output_move_double operand", insn);
4570 /* Return a string to output a single word conditional move.
4571 Operand0 -- EQ/NE of ccr register and 0
4572 Operand1 -- CCR register
4573 Operand2 -- destination
4574 Operand3 -- source */
4577 output_condmove_single (rtx operands[], rtx insn)
4579 rtx dest = operands[2];
4580 rtx src = operands[3];
4582 if (GET_CODE (dest) == REG)
4584 int dest_regno = REGNO (dest);
4585 enum machine_mode mode = GET_MODE (dest);
4587 if (GPR_P (dest_regno))
4589 if (GET_CODE (src) == REG)
4591 /* gpr <- some sort of register */
4592 int src_regno = REGNO (src);
4594 if (GPR_P (src_regno))
4595 return "cmov %z3, %2, %1, %e0";
4597 else if (FPR_P (src_regno))
4598 return "cmovfg %3, %2, %1, %e0";
4601 else if (GET_CODE (src) == MEM)
4610 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4613 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4617 return "cld%I3%U3 %M3, %2, %1, %e0";
4621 else if (ZERO_P (src))
4622 return "cmov %., %2, %1, %e0";
4625 else if (FPR_P (dest_regno))
4627 if (GET_CODE (src) == REG)
4629 /* fpr <- some sort of register */
4630 int src_regno = REGNO (src);
4632 if (GPR_P (src_regno))
4633 return "cmovgf %3, %2, %1, %e0";
4635 else if (FPR_P (src_regno))
4637 if (TARGET_HARD_FLOAT)
4638 return "cfmovs %3,%2,%1,%e0";
4640 return "cmor %3, %3, %2, %1, %e0";
4644 else if (GET_CODE (src) == MEM)
4647 if (mode == SImode || mode == SFmode)
4648 return "cldf%I3%U3 %M3, %2, %1, %e0";
4651 else if (ZERO_P (src))
4652 return "cmovgf %., %2, %1, %e0";
4656 else if (GET_CODE (dest) == MEM)
4658 if (GET_CODE (src) == REG)
4660 int src_regno = REGNO (src);
4661 enum machine_mode mode = GET_MODE (dest);
4663 if (GPR_P (src_regno))
4671 return "cstb%I2%U2 %3, %M2, %1, %e0";
4674 return "csth%I2%U2 %3, %M2, %1, %e0";
4678 return "cst%I2%U2 %3, %M2, %1, %e0";
4682 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4683 return "cstf%I2%U2 %3, %M2, %1, %e0";
4686 else if (ZERO_P (src))
4688 enum machine_mode mode = GET_MODE (dest);
4695 return "cstb%I2%U2 %., %M2, %1, %e0";
4698 return "csth%I2%U2 %., %M2, %1, %e0";
4702 return "cst%I2%U2 %., %M2, %1, %e0";
4707 fatal_insn ("bad output_condmove_single operand", insn);
4712 /* Emit the appropriate code to do a comparison, returning the register the
4713 comparison was done it. */
4716 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4718 enum machine_mode cc_mode;
4721 /* Floating point doesn't have comparison against a constant. */
4722 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4723 op1 = force_reg (GET_MODE (op0), op1);
4725 /* Possibly disable using anything but a fixed register in order to work
4726 around cse moving comparisons past function calls. */
4727 cc_mode = SELECT_CC_MODE (test, op0, op1);
4728 cc_reg = ((TARGET_ALLOC_CC)
4729 ? gen_reg_rtx (cc_mode)
4730 : gen_rtx_REG (cc_mode,
4731 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4733 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4734 gen_rtx_COMPARE (cc_mode, op0, op1)));
4740 /* Emit code for a conditional branch.
4741 XXX: I originally wanted to add a clobber of a CCR register to use in
4742 conditional execution, but that confuses the rest of the compiler. */
4745 frv_emit_cond_branch (rtx operands[])
4750 enum rtx_code test = GET_CODE (operands[0]);
4751 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4752 enum machine_mode cc_mode = GET_MODE (cc_reg);
4754 /* Branches generate:
4756 (if_then_else (<test>, <cc_reg>, (const_int 0))
4757 (label_ref <branch_label>)
4759 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4760 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4761 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4762 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4767 /* Emit code to set a gpr to 1/0 based on a comparison. */
4770 frv_emit_scc (rtx operands[])
4776 enum rtx_code test = GET_CODE (operands[1]);
4777 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4779 /* SCC instructions generate:
4780 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4781 (clobber (<ccr_reg>))]) */
4782 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4783 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4785 cr_reg = ((TARGET_ALLOC_CC)
4786 ? gen_reg_rtx (CC_CCRmode)
4787 : gen_rtx_REG (CC_CCRmode,
4788 ((GET_MODE (cc_reg) == CC_FPmode)
4792 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4793 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4798 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4799 the separate insns. */
4802 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4808 /* Set the appropriate CCR bit. */
4809 emit_insn (gen_rtx_SET (VOIDmode,
4811 gen_rtx_fmt_ee (GET_CODE (test),
4816 /* Move the value into the destination. */
4817 emit_move_insn (dest, GEN_INT (value));
4819 /* Move 0 into the destination if the test failed */
4820 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4821 gen_rtx_EQ (GET_MODE (cr_reg),
4824 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4826 /* Finish up, return sequence. */
4833 /* Emit the code for a conditional move, return TRUE if we could do the
4837 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4844 enum rtx_code test = GET_CODE (test_rtx);
4845 rtx cc_reg = frv_emit_comparison (test,
4846 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4847 enum machine_mode cc_mode = GET_MODE (cc_reg);
4849 /* Conditional move instructions generate:
4850 (parallel [(set <target>
4851 (if_then_else (<test> <cc_reg> (const_int 0))
4854 (clobber (<ccr_reg>))]) */
4856 /* Handle various cases of conditional move involving two constants. */
4857 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4859 HOST_WIDE_INT value1 = INTVAL (src1);
4860 HOST_WIDE_INT value2 = INTVAL (src2);
4862 /* Having 0 as one of the constants can be done by loading the other
4863 constant, and optionally moving in gr0. */
4864 if (value1 == 0 || value2 == 0)
4867 /* If the first value is within an addi range and also the difference
4868 between the two fits in an addi's range, load up the difference, then
4869 conditionally move in 0, and then unconditionally add the first
4871 else if (IN_RANGE_P (value1, -2048, 2047)
4872 && IN_RANGE_P (value2 - value1, -2048, 2047))
4875 /* If neither condition holds, just force the constant into a
4879 src1 = force_reg (GET_MODE (dest), src1);
4880 src2 = force_reg (GET_MODE (dest), src2);
4884 /* If one value is a register, insure the other value is either 0 or a
4888 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4889 src1 = force_reg (GET_MODE (dest), src1);
4891 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4892 src2 = force_reg (GET_MODE (dest), src2);
4895 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4896 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4898 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4900 cr_reg = ((TARGET_ALLOC_CC)
4901 ? gen_reg_rtx (CC_CCRmode)
4902 : gen_rtx_REG (CC_CCRmode,
4903 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4905 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4906 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4911 /* Split a conditional move into constituent parts, returning a SEQUENCE
4912 containing all of the insns. */
4915 frv_split_cond_move (rtx operands[])
4917 rtx dest = operands[0];
4918 rtx test = operands[1];
4919 rtx cc_reg = operands[2];
4920 rtx src1 = operands[3];
4921 rtx src2 = operands[4];
4922 rtx cr_reg = operands[5];
4924 enum machine_mode cr_mode = GET_MODE (cr_reg);
4928 /* Set the appropriate CCR bit. */
4929 emit_insn (gen_rtx_SET (VOIDmode,
4931 gen_rtx_fmt_ee (GET_CODE (test),
4936 /* Handle various cases of conditional move involving two constants. */
4937 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4939 HOST_WIDE_INT value1 = INTVAL (src1);
4940 HOST_WIDE_INT value2 = INTVAL (src2);
4942 /* Having 0 as one of the constants can be done by loading the other
4943 constant, and optionally moving in gr0. */
4946 emit_move_insn (dest, src2);
4947 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4948 gen_rtx_NE (cr_mode, cr_reg,
4950 gen_rtx_SET (VOIDmode, dest, src1)));
4953 else if (value2 == 0)
4955 emit_move_insn (dest, src1);
4956 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4957 gen_rtx_EQ (cr_mode, cr_reg,
4959 gen_rtx_SET (VOIDmode, dest, src2)));
4962 /* If the first value is within an addi range and also the difference
4963 between the two fits in an addi's range, load up the difference, then
4964 conditionally move in 0, and then unconditionally add the first
4966 else if (IN_RANGE_P (value1, -2048, 2047)
4967 && IN_RANGE_P (value2 - value1, -2048, 2047))
4969 rtx dest_si = ((GET_MODE (dest) == SImode)
4971 : gen_rtx_SUBREG (SImode, dest, 0));
4973 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4974 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4975 gen_rtx_NE (cr_mode, cr_reg,
4977 gen_rtx_SET (VOIDmode, dest_si,
4979 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4987 /* Emit the conditional move for the test being true if needed. */
4988 if (! rtx_equal_p (dest, src1))
4989 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4990 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4991 gen_rtx_SET (VOIDmode, dest, src1)));
4993 /* Emit the conditional move for the test being false if needed. */
4994 if (! rtx_equal_p (dest, src2))
4995 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4996 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4997 gen_rtx_SET (VOIDmode, dest, src2)));
5000 /* Finish up, return sequence. */
5007 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5008 memory location that is not known to be dword-aligned. */
5010 frv_split_double_load (rtx dest, rtx source)
5012 int regno = REGNO (dest);
5013 rtx dest1 = gen_highpart (SImode, dest);
5014 rtx dest2 = gen_lowpart (SImode, dest);
5015 rtx address = XEXP (source, 0);
5017 /* If the address is pre-modified, load the lower-numbered register
5018 first, then load the other register using an integer offset from
5019 the modified base register. This order should always be safe,
5020 since the pre-modification cannot affect the same registers as the
5023 The situation for other loads is more complicated. Loading one
5024 of the registers could affect the value of ADDRESS, so we must
5025 be careful which order we do them in. */
5026 if (GET_CODE (address) == PRE_MODIFY
5027 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5029 /* It is safe to load the lower-numbered register first. */
5030 emit_move_insn (dest1, change_address (source, SImode, NULL));
5031 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5035 /* ADDRESS is not pre-modified and the address depends on the
5036 lower-numbered register. Load the higher-numbered register
5038 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5039 emit_move_insn (dest1, change_address (source, SImode, NULL));
5043 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5044 and SOURCE is either a double register or the constant zero. */
5046 frv_split_double_store (rtx dest, rtx source)
5048 rtx dest1 = change_address (dest, SImode, NULL);
5049 rtx dest2 = frv_index_memory (dest, SImode, 1);
5050 if (ZERO_P (source))
5052 emit_move_insn (dest1, CONST0_RTX (SImode));
5053 emit_move_insn (dest2, CONST0_RTX (SImode));
5057 emit_move_insn (dest1, gen_highpart (SImode, source));
5058 emit_move_insn (dest2, gen_lowpart (SImode, source));
5063 /* Split a min/max operation returning a SEQUENCE containing all of the
5067 frv_split_minmax (rtx operands[])
5069 rtx dest = operands[0];
5070 rtx minmax = operands[1];
5071 rtx src1 = operands[2];
5072 rtx src2 = operands[3];
5073 rtx cc_reg = operands[4];
5074 rtx cr_reg = operands[5];
5076 enum rtx_code test_code;
5077 enum machine_mode cr_mode = GET_MODE (cr_reg);
5081 /* Figure out which test to use. */
5082 switch (GET_CODE (minmax))
5087 case SMIN: test_code = LT; break;
5088 case SMAX: test_code = GT; break;
5089 case UMIN: test_code = LTU; break;
5090 case UMAX: test_code = GTU; break;
5093 /* Issue the compare instruction. */
5094 emit_insn (gen_rtx_SET (VOIDmode,
5096 gen_rtx_COMPARE (GET_MODE (cc_reg),
5099 /* Set the appropriate CCR bit. */
5100 emit_insn (gen_rtx_SET (VOIDmode,
5102 gen_rtx_fmt_ee (test_code,
5107 /* If are taking the min/max of a nonzero constant, load that first, and
5108 then do a conditional move of the other value. */
5109 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5111 gcc_assert (!rtx_equal_p (dest, src1));
5113 emit_move_insn (dest, src2);
5114 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5115 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5116 gen_rtx_SET (VOIDmode, dest, src1)));
5119 /* Otherwise, do each half of the move. */
5122 /* Emit the conditional move for the test being true if needed. */
5123 if (! rtx_equal_p (dest, src1))
5124 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5125 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5126 gen_rtx_SET (VOIDmode, dest, src1)));
5128 /* Emit the conditional move for the test being false if needed. */
5129 if (! rtx_equal_p (dest, src2))
5130 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5131 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5132 gen_rtx_SET (VOIDmode, dest, src2)));
5135 /* Finish up, return sequence. */
5142 /* Split an integer abs operation returning a SEQUENCE containing all of the
5146 frv_split_abs (rtx operands[])
5148 rtx dest = operands[0];
5149 rtx src = operands[1];
5150 rtx cc_reg = operands[2];
5151 rtx cr_reg = operands[3];
5156 /* Issue the compare < 0 instruction. */
5157 emit_insn (gen_rtx_SET (VOIDmode,
5159 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5161 /* Set the appropriate CCR bit. */
5162 emit_insn (gen_rtx_SET (VOIDmode,
5164 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5166 /* Emit the conditional negate if the value is negative. */
5167 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5168 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5169 gen_negsi2 (dest, src)));
5171 /* Emit the conditional move for the test being false if needed. */
5172 if (! rtx_equal_p (dest, src))
5173 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5174 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5175 gen_rtx_SET (VOIDmode, dest, src)));
5177 /* Finish up, return sequence. */
5184 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5185 register used in an insn. */
5188 frv_clear_registers_used (rtx *ptr, void *data)
5190 if (GET_CODE (*ptr) == REG)
5192 int regno = REGNO (*ptr);
5193 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5195 if (regno < FIRST_PSEUDO_REGISTER)
5197 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5199 while (regno < reg_max)
5201 CLEAR_HARD_REG_BIT (*p_regs, regno);
5211 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5213 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5214 initialize the static storage. */
5216 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5218 frv_ifcvt.added_insns_list = NULL_RTX;
5219 frv_ifcvt.cur_scratch_regs = 0;
5220 frv_ifcvt.num_nested_cond_exec = 0;
5221 frv_ifcvt.cr_reg = NULL_RTX;
5222 frv_ifcvt.nested_cc_reg = NULL_RTX;
5223 frv_ifcvt.extra_int_cr = NULL_RTX;
5224 frv_ifcvt.extra_fp_cr = NULL_RTX;
5225 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5229 /* Internal function to add a potential insn to the list of insns to be inserted
5230 if the conditional execution conversion is successful. */
5233 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5235 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5237 link->jump = before_p; /* Mark to add this before or after insn. */
5238 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5239 frv_ifcvt.added_insns_list);
5241 if (TARGET_DEBUG_COND_EXEC)
5244 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5245 (before_p) ? "before" : "after",
5246 (int)INSN_UID (insn));
5248 debug_rtx (pattern);
5253 /* A C expression to modify the code described by the conditional if
5254 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5255 FALSE_EXPR for converting if-then and if-then-else code to conditional
5256 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5257 tests cannot be converted. */
5260 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5262 basic_block test_bb = ce_info->test_bb; /* test basic block */
5263 basic_block then_bb = ce_info->then_bb; /* THEN */
5264 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5265 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5266 rtx true_expr = *p_true;
5270 enum machine_mode mode = GET_MODE (true_expr);
5274 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5276 rtx sub_cond_exec_reg;
5278 enum rtx_code code_true;
5279 enum rtx_code code_false;
5280 enum reg_class cc_class;
5281 enum reg_class cr_class;
5284 reg_set_iterator rsi;
5286 /* Make sure we are only dealing with hard registers. Also honor the
5287 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5289 if (!reload_completed || !TARGET_COND_EXEC
5290 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5293 /* Figure out which registers we can allocate for our own purposes. Only
5294 consider registers that are not preserved across function calls and are
5295 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5296 if we did not need to use them in reloading other registers. */
5297 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5298 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5299 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5300 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5301 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5303 /* If this is a nested IF, we need to discover whether the CC registers that
5304 are set/used inside of the block are used anywhere else. If not, we can
5305 change them to be the CC register that is paired with the CR register that
5306 controls the outermost IF block. */
5307 if (ce_info->pass > 1)
5309 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5310 for (j = CC_FIRST; j <= CC_LAST; j++)
5311 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5313 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5317 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5321 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5324 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5328 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5329 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5331 frv_ifcvt.added_insns_list = NULL_RTX;
5332 frv_ifcvt.cur_scratch_regs = 0;
5334 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5335 * sizeof (basic_block));
5341 /* Remove anything live at the beginning of the join block from being
5342 available for allocation. */
5343 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5345 if (regno < FIRST_PSEUDO_REGISTER)
5346 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5350 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5352 if (ce_info->num_multiple_test_blocks)
5354 basic_block multiple_test_bb = ce_info->last_test_bb;
5356 while (multiple_test_bb != test_bb)
5358 bb[num_bb++] = multiple_test_bb;
5359 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5363 /* Add in the THEN and ELSE blocks to be scanned. */
5364 bb[num_bb++] = then_bb;
5366 bb[num_bb++] = else_bb;
5368 sub_cond_exec_reg = NULL_RTX;
5369 frv_ifcvt.num_nested_cond_exec = 0;
5371 /* Scan all of the blocks for registers that must not be allocated. */
5372 for (j = 0; j < num_bb; j++)
5374 rtx last_insn = BB_END (bb[j]);
5375 rtx insn = BB_HEAD (bb[j]);
5379 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5380 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5382 (int) INSN_UID (BB_HEAD (bb[j])),
5383 (int) INSN_UID (BB_END (bb[j])));
5385 /* Anything live at the beginning of the block is obviously unavailable
5387 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5389 if (regno < FIRST_PSEUDO_REGISTER)
5390 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5393 /* Loop through the insns in the block. */
5396 /* Mark any new registers that are created as being unavailable for
5397 allocation. Also see if the CC register used in nested IFs can be
5403 int skip_nested_if = FALSE;
5405 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5406 (void *)&tmp_reg->regs);
5408 pattern = PATTERN (insn);
5409 if (GET_CODE (pattern) == COND_EXEC)
5411 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5413 if (reg != sub_cond_exec_reg)
5415 sub_cond_exec_reg = reg;
5416 frv_ifcvt.num_nested_cond_exec++;
5420 set = single_set_pattern (pattern);
5423 rtx dest = SET_DEST (set);
5424 rtx src = SET_SRC (set);
5426 if (GET_CODE (dest) == REG)
5428 int regno = REGNO (dest);
5429 enum rtx_code src_code = GET_CODE (src);
5431 if (CC_P (regno) && src_code == COMPARE)
5432 skip_nested_if = TRUE;
5434 else if (CR_P (regno)
5435 && (src_code == IF_THEN_ELSE
5436 || COMPARISON_P (src)))
5437 skip_nested_if = TRUE;
5441 if (! skip_nested_if)
5442 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5443 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5446 if (insn == last_insn)
5449 insn = NEXT_INSN (insn);
5453 /* If this is a nested if, rewrite the CC registers that are available to
5454 include the ones that can be rewritten, to increase the chance of being
5455 able to allocate a paired CC/CR register combination. */
5456 if (ce_info->pass > 1)
5458 for (j = CC_FIRST; j <= CC_LAST; j++)
5459 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5460 SET_HARD_REG_BIT (tmp_reg->regs, j);
5462 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5468 fprintf (dump_file, "Available GPRs: ");
5470 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5471 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5473 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5474 if (++num_gprs > GPR_TEMP_NUM+2)
5478 fprintf (dump_file, "%s\nAvailable CRs: ",
5479 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5481 for (j = CR_FIRST; j <= CR_LAST; j++)
5482 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5483 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5485 fputs ("\n", dump_file);
5487 if (ce_info->pass > 1)
5489 fprintf (dump_file, "Modifiable CCs: ");
5490 for (j = CC_FIRST; j <= CC_LAST; j++)
5491 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5492 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5494 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5495 frv_ifcvt.num_nested_cond_exec);
5499 /* Allocate the appropriate temporary condition code register. Try to
5500 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5501 that conditional cmp's can be done. */
5502 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5504 cr_class = ICR_REGS;
5505 cc_class = ICC_REGS;
5506 cc_first = ICC_FIRST;
5509 else if (mode == CC_FPmode)
5511 cr_class = FCR_REGS;
5512 cc_class = FCC_REGS;
5513 cc_first = FCC_FIRST;
5518 cc_first = cc_last = 0;
5519 cr_class = cc_class = NO_REGS;
5522 cc = XEXP (true_expr, 0);
5523 nested_cc = cr = NULL_RTX;
5524 if (cc_class != NO_REGS)
5526 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5527 so we can execute a csubcc/caddcc/cfcmps instruction. */
5530 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5532 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5534 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5535 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5537 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5538 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5541 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5542 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5552 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5559 "Will use %s for conditional execution, %s for nested comparisons\n",
5560 reg_names[ REGNO (cr)],
5561 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5563 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5564 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5565 bit being true. We don't do this for floating point, because of NaNs. */
5566 code = GET_CODE (true_expr);
5567 if (GET_MODE (cc) != CC_FPmode)
5569 code = reverse_condition (code);
5579 check_insn = gen_rtx_SET (VOIDmode, cr,
5580 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5582 /* Record the check insn to be inserted later. */
5583 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5585 /* Update the tests. */
5586 frv_ifcvt.cr_reg = cr;
5587 frv_ifcvt.nested_cc_reg = nested_cc;
5588 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5589 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5592 /* Fail, don't do this conditional execution. */
5595 *p_false = NULL_RTX;
5597 fprintf (dump_file, "Disabling this conditional execution.\n");
5603 /* A C expression to modify the code described by the conditional if
5604 information CE_INFO, for the basic block BB, possibly updating the tests in
5605 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5606 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5607 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5609 /* p_true and p_false are given expressions of the form:
5611 (and (eq:CC_CCR (reg:CC_CCR)
5617 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5622 rtx old_true = XEXP (*p_true, 0);
5623 rtx old_false = XEXP (*p_false, 0);
5624 rtx true_expr = XEXP (*p_true, 1);
5625 rtx false_expr = XEXP (*p_false, 1);
5628 rtx cr = XEXP (old_true, 0);
5630 rtx new_cr = NULL_RTX;
5631 rtx *p_new_cr = (rtx *)0;
5635 enum reg_class cr_class;
5636 enum machine_mode mode = GET_MODE (true_expr);
5637 rtx (*logical_func)(rtx, rtx, rtx);
5639 if (TARGET_DEBUG_COND_EXEC)
5642 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5643 ce_info->and_and_p ? "&&" : "||");
5645 debug_rtx (*p_true);
5647 fputs ("\nfalse insn:\n", stderr);
5648 debug_rtx (*p_false);
5651 if (!TARGET_MULTI_CE)
5654 if (GET_CODE (cr) != REG)
5657 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5659 cr_class = ICR_REGS;
5660 p_new_cr = &frv_ifcvt.extra_int_cr;
5662 else if (mode == CC_FPmode)
5664 cr_class = FCR_REGS;
5665 p_new_cr = &frv_ifcvt.extra_fp_cr;
5670 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5671 more &&/|| tests. */
5675 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5676 CC_CCRmode, TRUE, TRUE);
5681 if (ce_info->and_and_p)
5683 old_test = old_false;
5684 test_expr = true_expr;
5685 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5686 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5687 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5691 old_test = old_false;
5692 test_expr = false_expr;
5693 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5694 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5695 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5698 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5699 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5701 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5703 /* Now add the conditional check insn. */
5704 cc = XEXP (test_expr, 0);
5705 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5706 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5708 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5710 /* Add the new check insn to the list of check insns that need to be
5712 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5714 if (TARGET_DEBUG_COND_EXEC)
5716 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5719 debug_rtx (*p_true);
5721 fputs ("\nfalse insn:\n", stderr);
5722 debug_rtx (*p_false);
5728 *p_true = *p_false = NULL_RTX;
5730 /* If we allocated a CR register, release it. */
5733 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5734 *p_new_cr = NULL_RTX;
5737 if (TARGET_DEBUG_COND_EXEC)
5738 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5744 /* Return a register which will be loaded with a value if an IF block is
5745 converted to conditional execution. This is used to rewrite instructions
5746 that use constants to ones that just use registers. */
5749 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5751 int num_alloc = frv_ifcvt.cur_scratch_regs;
5755 /* We know gr0 == 0, so replace any errant uses. */
5756 if (value == const0_rtx)
5757 return gen_rtx_REG (SImode, GPR_FIRST);
5759 /* First search all registers currently loaded to see if we have an
5760 applicable constant. */
5761 if (CONSTANT_P (value)
5762 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5764 for (i = 0; i < num_alloc; i++)
5766 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5767 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5771 /* Have we exhausted the number of registers available? */
5772 if (num_alloc >= GPR_TEMP_NUM)
5775 fprintf (dump_file, "Too many temporary registers allocated\n");
5780 /* Allocate the new register. */
5781 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5785 fputs ("Could not find a scratch register\n", dump_file);
5790 frv_ifcvt.cur_scratch_regs++;
5791 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5795 if (GET_CODE (value) == CONST_INT)
5796 fprintf (dump_file, "Register %s will hold %ld\n",
5797 reg_names[ REGNO (reg)], (long)INTVAL (value));
5799 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5800 fprintf (dump_file, "Register %s will hold LR\n",
5801 reg_names[ REGNO (reg)]);
5804 fprintf (dump_file, "Register %s will hold a saved value\n",
5805 reg_names[ REGNO (reg)]);
5812 /* Update a MEM used in conditional code that might contain an offset to put
5813 the offset into a scratch register, so that the conditional load/store
5814 operations can be used. This function returns the original pointer if the
5815 MEM is valid to use in conditional code, NULL if we can't load up the offset
5816 into a temporary register, or the new MEM if we were successful. */
5819 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5821 rtx addr = XEXP (mem, 0);
5823 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5825 if (GET_CODE (addr) == PLUS)
5827 rtx addr_op0 = XEXP (addr, 0);
5828 rtx addr_op1 = XEXP (addr, 1);
5830 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5832 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5836 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5843 else if (CONSTANT_P (addr))
5844 addr = frv_ifcvt_load_value (addr, insn);
5849 if (addr == NULL_RTX)
5852 else if (XEXP (mem, 0) != addr)
5853 return change_address (mem, mode, addr);
5860 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5861 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5864 single_set_pattern (rtx pattern)
5869 if (GET_CODE (pattern) == COND_EXEC)
5870 pattern = COND_EXEC_CODE (pattern);
5872 if (GET_CODE (pattern) == SET)
5875 else if (GET_CODE (pattern) == PARALLEL)
5877 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5879 rtx sub = XVECEXP (pattern, 0, i);
5881 switch (GET_CODE (sub))
5905 /* A C expression to modify the code described by the conditional if
5906 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5907 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5908 insn cannot be converted to be executed conditionally. */
5911 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5915 rtx orig_ce_pattern = pattern;
5921 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5923 test = COND_EXEC_TEST (pattern);
5924 if (GET_CODE (test) == AND)
5926 rtx cr = frv_ifcvt.cr_reg;
5929 op0 = XEXP (test, 0);
5930 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5933 op1 = XEXP (test, 1);
5934 test_reg = XEXP (op1, 0);
5935 if (GET_CODE (test_reg) != REG)
5938 /* Is this the first nested if block in this sequence? If so, generate
5939 an andcr or andncr. */
5940 if (! frv_ifcvt.last_nested_if_cr)
5944 frv_ifcvt.last_nested_if_cr = test_reg;
5945 if (GET_CODE (op0) == NE)
5946 and_op = gen_andcr (test_reg, cr, test_reg);
5948 and_op = gen_andncr (test_reg, cr, test_reg);
5950 frv_ifcvt_add_insn (and_op, insn, TRUE);
5953 /* If this isn't the first statement in the nested if sequence, see if we
5954 are dealing with the same register. */
5955 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5958 COND_EXEC_TEST (pattern) = test = op1;
5961 /* If this isn't a nested if, reset state variables. */
5964 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5967 set = single_set_pattern (pattern);
5970 rtx dest = SET_DEST (set);
5971 rtx src = SET_SRC (set);
5972 enum machine_mode mode = GET_MODE (dest);
5974 /* Check for normal binary operators. */
5975 if (mode == SImode && ARITHMETIC_P (src))
5977 op0 = XEXP (src, 0);
5978 op1 = XEXP (src, 1);
5980 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5982 op1 = frv_ifcvt_load_value (op1, insn);
5984 COND_EXEC_CODE (pattern)
5985 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
5993 /* For multiply by a constant, we need to handle the sign extending
5994 correctly. Add a USE of the value after the multiply to prevent flow
5995 from cratering because only one register out of the two were used. */
5996 else if (mode == DImode && GET_CODE (src) == MULT)
5998 op0 = XEXP (src, 0);
5999 op1 = XEXP (src, 1);
6000 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6002 op1 = frv_ifcvt_load_value (op1, insn);
6005 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6006 COND_EXEC_CODE (pattern)
6007 = gen_rtx_SET (VOIDmode, dest,
6008 gen_rtx_MULT (DImode, op0, op1));
6014 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6017 /* If we are just loading a constant created for a nested conditional
6018 execution statement, just load the constant without any conditional
6019 execution, since we know that the constant will not interfere with any
6021 else if (frv_ifcvt.scratch_insns_bitmap
6022 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6024 && REG_P (SET_DEST (set))
6025 /* We must not unconditionally set a scratch reg chosen
6026 for a nested if-converted block if its incoming
6027 value from the TEST block (or the result of the THEN
6028 branch) could/should propagate to the JOIN block.
6029 It suffices to test whether the register is live at
6030 the JOIN point: if it's live there, we can infer
6031 that we set it in the former JOIN block of the
6032 nested if-converted block (otherwise it wouldn't
6033 have been available as a scratch register), and it
6034 is either propagated through or set in the other
6035 conditional block. It's probably not worth trying
6036 to catch the latter case, and it could actually
6037 limit scheduling of the combined block quite
6040 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6041 REGNO (SET_DEST (set))))
6042 /* Similarly, we must not unconditionally set a reg
6043 used as scratch in the THEN branch if the same reg
6044 is live in the ELSE branch. */
6045 && (! ce_info->else_bb
6046 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6047 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6048 REGNO (SET_DEST (set))))))
6051 else if (mode == QImode || mode == HImode || mode == SImode
6054 int changed_p = FALSE;
6056 /* Check for just loading up a constant */
6057 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6059 src = frv_ifcvt_load_value (src, insn);
6066 /* See if we need to fix up stores */
6067 if (GET_CODE (dest) == MEM)
6069 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6074 else if (new_mem != dest)
6081 /* See if we need to fix up loads */
6082 if (GET_CODE (src) == MEM)
6084 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6089 else if (new_mem != src)
6096 /* If either src or destination changed, redo SET. */
6098 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6101 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6102 rewriting the CC register to be the same as the paired CC/CR register
6104 else if (mode == CC_CCRmode && COMPARISON_P (src))
6106 int regno = REGNO (XEXP (src, 0));
6109 if (ce_info->pass > 1
6110 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6111 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6113 src = gen_rtx_fmt_ee (GET_CODE (src),
6115 frv_ifcvt.nested_cc_reg,
6119 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6120 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6123 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6124 else if (ce_info->pass > 1
6125 && GET_CODE (dest) == REG
6126 && CC_P (REGNO (dest))
6127 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6128 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6130 && GET_CODE (src) == COMPARE)
6132 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6133 COND_EXEC_CODE (pattern)
6134 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6138 if (TARGET_DEBUG_COND_EXEC)
6140 rtx orig_pattern = PATTERN (insn);
6142 PATTERN (insn) = pattern;
6144 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6148 PATTERN (insn) = orig_pattern;
6154 if (TARGET_DEBUG_COND_EXEC)
6156 rtx orig_pattern = PATTERN (insn);
6158 PATTERN (insn) = orig_ce_pattern;
6160 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6164 PATTERN (insn) = orig_pattern;
6171 /* A C expression to perform any final machine dependent modifications in
6172 converting code to conditional execution in the code described by the
6173 conditional if information CE_INFO. */
6176 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6180 rtx p = frv_ifcvt.added_insns_list;
6183 /* Loop inserting the check insns. The last check insn is the first test,
6184 and is the appropriate place to insert constants. */
6189 rtx check_and_insert_insns = XEXP (p, 0);
6192 check_insn = XEXP (check_and_insert_insns, 0);
6193 existing_insn = XEXP (check_and_insert_insns, 1);
6196 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6197 the existing insn, otherwise it is to be inserted AFTER. */
6198 if (check_and_insert_insns->jump)
6200 emit_insn_before (check_insn, existing_insn);
6201 check_and_insert_insns->jump = 0;
6204 emit_insn_after (check_insn, existing_insn);
6206 free_EXPR_LIST_node (check_and_insert_insns);
6207 free_EXPR_LIST_node (old_p);
6209 while (p != NULL_RTX);
6211 /* Load up any constants needed into temp gprs */
6212 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6214 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6215 if (! frv_ifcvt.scratch_insns_bitmap)
6216 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6217 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6218 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6221 frv_ifcvt.added_insns_list = NULL_RTX;
6222 frv_ifcvt.cur_scratch_regs = 0;
6226 /* A C expression to cancel any machine dependent modifications in converting
6227 code to conditional execution in the code described by the conditional if
6228 information CE_INFO. */
6231 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6234 rtx p = frv_ifcvt.added_insns_list;
6236 /* Loop freeing up the EXPR_LIST's allocated. */
6237 while (p != NULL_RTX)
6239 rtx check_and_jump = XEXP (p, 0);
6243 free_EXPR_LIST_node (check_and_jump);
6244 free_EXPR_LIST_node (old_p);
6247 /* Release any temporary gprs allocated. */
6248 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6249 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6251 frv_ifcvt.added_insns_list = NULL_RTX;
6252 frv_ifcvt.cur_scratch_regs = 0;
6256 /* A C expression for the size in bytes of the trampoline, as an integer.
6260 setlo #0, <static_chain>
6262 sethi #0, <static_chain>
6263 jmpl @(gr0,<jmp_reg>) */
6266 frv_trampoline_size (void)
6269 /* Allocate room for the function descriptor and the lddi
6272 return 5 /* instructions */ * 4 /* instruction size. */;
6276 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6277 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6278 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6279 should be passed to the function when it is called.
6284 setlo #0, <static_chain>
6286 sethi #0, <static_chain>
6287 jmpl @(gr0,<jmp_reg>) */
6290 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6292 rtx sc_reg = force_reg (Pmode, static_chain);
6294 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6297 GEN_INT (frv_trampoline_size ()), SImode,
6303 /* Many machines have some registers that cannot be copied directly to or from
6304 memory or even from other types of registers. An example is the `MQ'
6305 register, which on most machines, can only be copied to or from general
6306 registers, but not memory. Some machines allow copying all registers to and
6307 from memory, but require a scratch register for stores to some memory
6308 locations (e.g., those with symbolic address on the RT, and those with
6309 certain symbolic address on the SPARC when compiling PIC). In some cases,
6310 both an intermediate and a scratch register are required.
6312 You should define these macros to indicate to the reload phase that it may
6313 need to allocate at least one register for a reload in addition to the
6314 register to contain the data. Specifically, if copying X to a register
6315 RCLASS in MODE requires an intermediate register, you should define
6316 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6317 whose registers can be used as intermediate registers or scratch registers.
6319 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6320 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6321 largest register class required. If the requirements for input and output
6322 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6323 instead of defining both macros identically.
6325 The values returned by these macros are often `GENERAL_REGS'. Return
6326 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6327 to or from a register of RCLASS in MODE without requiring a scratch register.
6328 Do not define this macro if it would always return `NO_REGS'.
6330 If a scratch register is required (either with or without an intermediate
6331 register), you should define patterns for `reload_inM' or `reload_outM', as
6332 required.. These patterns, which will normally be implemented with a
6333 `define_expand', should be similar to the `movM' patterns, except that
6334 operand 2 is the scratch register.
6336 Define constraints for the reload register and scratch register that contain
6337 a single register class. If the original reload register (whose class is
6338 RCLASS) can meet the constraint given in the pattern, the value returned by
6339 these macros is used for the class of the scratch register. Otherwise, two
6340 additional reload registers are required. Their classes are obtained from
6341 the constraints in the insn pattern.
6343 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6344 either be in a hard register or in memory. Use `true_regnum' to find out;
6345 it will return -1 if the pseudo is in memory and the hard register number if
6346 it is in a register.
6348 These macros should not be used in the case where a particular class of
6349 registers can only be copied to memory and not to another class of
6350 registers. In that case, secondary reload registers are not needed and
6351 would not be helpful. Instead, a stack location must be used to perform the
6352 copy and the `movM' pattern should use memory as an intermediate storage.
6353 This case often occurs between floating-point and general registers. */
6356 frv_secondary_reload_class (enum reg_class rclass,
6357 enum machine_mode mode ATTRIBUTE_UNUSED,
6368 /* Accumulators/Accumulator guard registers need to go through floating
6374 if (x && GET_CODE (x) == REG)
6376 int regno = REGNO (x);
6378 if (ACC_P (regno) || ACCG_P (regno))
6383 /* Nonzero constants should be loaded into an FPR through a GPR. */
6387 if (x && CONSTANT_P (x) && !ZERO_P (x))
6393 /* All of these types need gpr registers. */
6405 /* The accumulators need fpr registers. */
6417 /* This hook exists to catch the case where secondary_reload_class() is
6418 called from init_reg_autoinc() in regclass.c - before the reload optabs
6419 have been initialised. */
6422 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6423 enum machine_mode reload_mode,
6424 secondary_reload_info * sri)
6426 enum reg_class rclass = NO_REGS;
6428 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6430 sri->icode = sri->prev_sri->t_icode;
6434 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6436 if (rclass != NO_REGS)
6438 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6439 : reload_out_optab[(int) reload_mode]);
6442 /* This happens when then the reload_[in|out]_optabs have
6443 not been initialised. */
6444 sri->t_icode = CODE_FOR_nothing;
6449 /* Fall back to the default secondary reload handler. */
6450 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6454 /* A C expression whose value is nonzero if pseudos that have been assigned to
6455 registers of class RCLASS would likely be spilled because registers of RCLASS
6456 are needed for spill registers.
6458 The default value of this macro returns 1 if RCLASS has exactly one register
6459 and zero otherwise. On most machines, this default should be used. Only
6460 define this macro to some other expression if pseudo allocated by
6461 `local-alloc.c' end up in memory because their hard registers were needed
6462 for spill registers. If this macro returns nonzero for those classes, those
6463 pseudos will only be allocated by `global.c', which knows how to reallocate
6464 the pseudo to another register. If there would not be another register
6465 available for reallocation, you should not change the definition of this
6466 macro since the only effect of such a definition would be to slow down
6467 register allocation. */
6470 frv_class_likely_spilled_p (enum reg_class rclass)
6480 case FDPIC_FPTR_REGS:
6502 /* An expression for the alignment of a structure field FIELD if the
6503 alignment computed in the usual way is COMPUTED. GCC uses this
6504 value instead of the value in `BIGGEST_ALIGNMENT' or
6505 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6507 /* The definition type of the bit field data is either char, short, long or
6508 long long. The maximum bit size is the number of bits of its own type.
6510 The bit field data is assigned to a storage unit that has an adequate size
6511 for bit field data retention and is located at the smallest address.
6513 Consecutive bit field data are packed at consecutive bits having the same
6514 storage unit, with regard to the type, beginning with the MSB and continuing
6517 If a field to be assigned lies over a bit field type boundary, its
6518 assignment is completed by aligning it with a boundary suitable for the
6521 When a bit field having a bit length of 0 is declared, it is forcibly
6522 assigned to the next storage unit.
6535 &x 00000000 00000000 00000000 00000000
6538 &x+4 00000000 00000000 00000000 00000000
6541 &x+8 00000000 00000000 00000000 00000000
6544 &x+12 00000000 00000000 00000000 00000000
6550 frv_adjust_field_align (tree field, int computed)
6552 /* Make sure that the bitfield is not wider than the type. */
6553 if (DECL_BIT_FIELD (field)
6554 && !DECL_ARTIFICIAL (field))
6556 tree parent = DECL_CONTEXT (field);
6557 tree prev = NULL_TREE;
6560 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6562 if (TREE_CODE (cur) != FIELD_DECL)
6570 /* If this isn't a :0 field and if the previous element is a bitfield
6571 also, see if the type is different, if so, we will need to align the
6572 bit-field to the next boundary. */
6574 && ! DECL_PACKED (field)
6575 && ! integer_zerop (DECL_SIZE (field))
6576 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6578 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6579 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6580 computed = (prev_align > cur_align) ? prev_align : cur_align;
6588 /* A C expression that is nonzero if it is permissible to store a value of mode
6589 MODE in hard register number REGNO (or in several registers starting with
6590 that one). For a machine where all registers are equivalent, a suitable
6593 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6595 It is not necessary for this macro to check for the numbers of fixed
6596 registers, because the allocation mechanism considers them to be always
6599 On some machines, double-precision values must be kept in even/odd register
6600 pairs. The way to implement that is to define this macro to reject odd
6601 register numbers for such modes.
6603 The minimum requirement for a mode to be OK in a register is that the
6604 `movMODE' instruction pattern support moves between the register and any
6605 other hard register for which the mode is OK; and that moving a value into
6606 the register and back out not alter it.
6608 Since the same instruction used to move `SImode' will work for all narrower
6609 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6610 to distinguish between these modes, provided you define patterns `movhi',
6611 etc., to take advantage of this. This is useful because of the interaction
6612 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6613 all integer modes to be tieable.
6615 Many machines have special registers for floating point arithmetic. Often
6616 people assume that floating point machine modes are allowed only in floating
6617 point registers. This is not true. Any registers that can hold integers
6618 can safely *hold* a floating point machine mode, whether or not floating
6619 arithmetic can be done on it in those registers. Integer move instructions
6620 can be used to move the values.
6622 On some machines, though, the converse is true: fixed-point machine modes
6623 may not go in floating registers. This is true if the floating registers
6624 normalize any value stored in them, because storing a non-floating value
6625 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6626 fixed-point machine modes in floating registers. But if the floating
6627 registers do not automatically normalize, if you can store any bit pattern
6628 in one and retrieve it unchanged without a trap, then any machine mode may
6629 go in a floating register, so you can define this macro to say so.
6631 The primary significance of special floating registers is rather that they
6632 are the registers acceptable in floating point arithmetic instructions.
6633 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6634 writing the proper constraints for those instructions.
6636 On some machines, the floating registers are especially slow to access, so
6637 that it is better to store a value in a stack frame than in such a register
6638 if floating point arithmetic is not being done. As long as the floating
6639 registers are not in class `GENERAL_REGS', they will not be used unless some
6640 pattern's constraint asks for one. */
6643 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6653 return ICC_P (regno) || GPR_P (regno);
6656 return CR_P (regno) || GPR_P (regno);
6659 return FCC_P (regno) || GPR_P (regno);
6665 /* Set BASE to the first register in REGNO's class. Set MASK to the
6666 bits that must be clear in (REGNO - BASE) for the register to be
6668 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6672 /* ACCGs store one byte. Two-byte quantities must start in
6673 even-numbered registers, four-byte ones in registers whose
6674 numbers are divisible by four, and so on. */
6676 mask = GET_MODE_SIZE (mode) - 1;
6680 /* The other registers store one word. */
6681 if (GPR_P (regno) || regno == AP_FIRST)
6684 else if (FPR_P (regno))
6687 else if (ACC_P (regno))
6690 else if (SPR_P (regno))
6691 return mode == SImode;
6693 /* Fill in the table. */
6697 /* Anything smaller than an SI is OK in any word-sized register. */
6698 if (GET_MODE_SIZE (mode) < 4)
6701 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6703 return (((regno - base) & mask) == 0);
6710 /* A C expression for the number of consecutive hard registers, starting at
6711 register number REGNO, required to hold a value of mode MODE.
6713 On a machine where all registers are exactly one word, a suitable definition
6716 #define HARD_REGNO_NREGS(REGNO, MODE) \
6717 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6718 / UNITS_PER_WORD)) */
6720 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6721 that we can build the appropriate instructions to properly reload the
6722 values. Also, make the byte-sized accumulator guards use one guard
6726 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6729 return GET_MODE_SIZE (mode);
6731 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6735 /* A C expression for the maximum number of consecutive registers of
6736 class RCLASS needed to hold a value of mode MODE.
6738 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6739 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6740 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6742 This macro helps control the handling of multiple-word values in
6745 This declaration is required. */
6748 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6750 if (rclass == ACCG_REGS)
6751 /* An N-byte value requires N accumulator guards. */
6752 return GET_MODE_SIZE (mode);
6754 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6758 /* A C expression that is nonzero if X is a legitimate constant for an
6759 immediate operand on the target machine. You can assume that X satisfies
6760 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6761 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6764 frv_legitimate_constant_p (rtx x)
6766 enum machine_mode mode = GET_MODE (x);
6768 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6769 means that the move expanders will be expected to deal with most
6770 kinds of constant, regardless of what we return here.
6772 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6773 a constant can be entered into reg_equiv_constant[]. If we return true,
6774 reload can create new instances of the constant whenever it likes.
6776 The idea is therefore to accept as many constants as possible (to give
6777 reload more freedom) while rejecting constants that can only be created
6778 at certain times. In particular, anything with a symbolic component will
6779 require use of the pseudo FDPIC register, which is only available before
6782 return LEGITIMATE_PIC_OPERAND_P (x);
6784 /* All of the integer constants are ok. */
6785 if (GET_CODE (x) != CONST_DOUBLE)
6788 /* double integer constants are ok. */
6789 if (mode == VOIDmode || mode == DImode)
6792 /* 0 is always ok. */
6793 if (x == CONST0_RTX (mode))
6796 /* If floating point is just emulated, allow any constant, since it will be
6797 constructed in the GPRs. */
6798 if (!TARGET_HAS_FPRS)
6801 if (mode == DFmode && !TARGET_DOUBLE)
6804 /* Otherwise store the constant away and do a load. */
6808 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6809 CC_NZ for comparisons against zero in which a single Z or N flag test
6810 is enough, CC_UNS for other unsigned comparisons, and CC for other
6811 signed comparisons. */
6814 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6816 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6825 return y == const0_rtx ? CC_NZmode : CCmode;
6831 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6838 /* A C expression for the cost of moving data from a register in class FROM to
6839 one in class TO. The classes are expressed using the enumeration values
6840 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6841 interpreted relative to that.
6843 It is not required that the cost always equal 2 when FROM is the same as TO;
6844 on some machines it is expensive to move between registers if they are not
6847 If reload sees an insn consisting of a single `set' between two hard
6848 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6849 value of 2, reload does not check to ensure that the constraints of the insn
6850 are met. Setting a cost of other than 2 will allow reload to verify that
6851 the constraints are met. You should do this if the `movM' pattern's
6852 constraints do not allow such copying. */
6854 #define HIGH_COST 40
6855 #define MEDIUM_COST 3
6859 frv_register_move_cost (enum reg_class from, enum reg_class to)
6943 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6944 use ".picptr" to generate safe relocations for PIC code. We also
6945 need a fixup entry for aligned (non-debugging) code. */
6948 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6950 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6952 if (GET_CODE (value) == CONST
6953 || GET_CODE (value) == SYMBOL_REF
6954 || GET_CODE (value) == LABEL_REF)
6956 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6957 && SYMBOL_REF_FUNCTION_P (value))
6959 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6960 output_addr_const (asm_out_file, value);
6961 fputs (")\n", asm_out_file);
6964 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6965 && frv_function_symbol_referenced_p (value))
6967 if (aligned_p && !TARGET_FDPIC)
6969 static int label_num = 0;
6973 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6974 p = (* targetm.strip_name_encoding) (buf);
6976 fprintf (asm_out_file, "%s:\n", p);
6977 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6978 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6979 fprintf (asm_out_file, "\t.previous\n");
6981 assemble_integer_with_op ("\t.picptr\t", value);
6986 /* We've set the unaligned SI op to NULL, so we always have to
6987 handle the unaligned case here. */
6988 assemble_integer_with_op ("\t.4byte\t", value);
6992 return default_assemble_integer (value, size, aligned_p);
6995 /* Function to set up the backend function structure. */
6997 static struct machine_function *
6998 frv_init_machine_status (void)
7000 return GGC_CNEW (struct machine_function);
7003 /* Implement TARGET_SCHED_ISSUE_RATE. */
7006 frv_issue_rate (void)
7011 switch (frv_cpu_type)
7015 case FRV_CPU_SIMPLE:
7023 case FRV_CPU_GENERIC:
7025 case FRV_CPU_TOMCAT:
7033 /* A for_each_rtx callback. If X refers to an accumulator, return
7034 ACC_GROUP_ODD if the bit 2 of the register number is set and
7035 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7039 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7043 if (ACC_P (REGNO (*x)))
7044 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7045 if (ACCG_P (REGNO (*x)))
7046 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7051 /* Return the value of INSN's acc_group attribute. */
7054 frv_acc_group (rtx insn)
7056 /* This distinction only applies to the FR550 packing constraints. */
7057 if (frv_cpu_type != FRV_CPU_FR550)
7058 return ACC_GROUP_NONE;
7059 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7062 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7063 INSN will try to claim first. Since this value depends only on the
7064 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7067 frv_insn_unit (rtx insn)
7069 enum attr_type type;
7071 type = get_attr_type (insn);
7072 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7074 /* We haven't seen this type of instruction before. */
7078 /* Issue the instruction on its own to see which unit it prefers. */
7079 state = alloca (state_size ());
7080 state_reset (state);
7081 state_transition (state, insn);
7083 /* Find out which unit was taken. */
7084 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7085 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7088 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7090 frv_type_to_unit[type] = unit;
7092 return frv_type_to_unit[type];
7095 /* Return true if INSN issues to a branch unit. */
7098 frv_issues_to_branch_unit_p (rtx insn)
7100 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7103 /* The current state of the packing pass, implemented by frv_pack_insns. */
7105 /* The state of the pipeline DFA. */
7108 /* Which hardware registers are set within the current packet,
7109 and the conditions under which they are set. */
7110 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7112 /* The memory locations that have been modified so far in this
7113 packet. MEM is the memref and COND is the regstate_t condition
7114 under which it is set. */
7120 /* The number of valid entries in MEMS. The value is larger than
7121 ARRAY_SIZE (mems) if there were too many mems to record. */
7122 unsigned int num_mems;
7124 /* The maximum number of instructions that can be packed together. */
7125 unsigned int issue_rate;
7127 /* The instructions in the packet, partitioned into groups. */
7128 struct frv_packet_group {
7129 /* How many instructions in the packet belong to this group. */
7130 unsigned int num_insns;
7132 /* A list of the instructions that belong to this group, in the order
7133 they appear in the rtl stream. */
7134 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7136 /* The contents of INSNS after they have been sorted into the correct
7137 assembly-language order. Element X issues to unit X. The list may
7138 contain extra nops. */
7139 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7141 /* The member of frv_nops[] to use in sorted[]. */
7143 } groups[NUM_GROUPS];
7145 /* The instructions that make up the current packet. */
7146 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7147 unsigned int num_insns;
7150 /* Return the regstate_t flags for the given COND_EXEC condition.
7151 Abort if the condition isn't in the right form. */
7154 frv_cond_flags (rtx cond)
7156 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7157 && GET_CODE (XEXP (cond, 0)) == REG
7158 && CR_P (REGNO (XEXP (cond, 0)))
7159 && XEXP (cond, 1) == const0_rtx);
7160 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7161 | (GET_CODE (cond) == NE
7163 : REGSTATE_IF_FALSE));
7167 /* Return true if something accessed under condition COND2 can
7168 conflict with something written under condition COND1. */
7171 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7173 /* If either reference was unconditional, we have a conflict. */
7174 if ((cond1 & REGSTATE_IF_EITHER) == 0
7175 || (cond2 & REGSTATE_IF_EITHER) == 0)
7178 /* The references might conflict if they were controlled by
7180 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7183 /* They definitely conflict if they are controlled by the
7185 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7192 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7193 the current packet. DATA points to a regstate_t that describes the
7194 condition under which *X might be set or used. */
7197 frv_registers_conflict_p_1 (rtx *x, void *data)
7199 unsigned int regno, i;
7202 cond = *(regstate_t *) data;
7204 if (GET_CODE (*x) == REG)
7205 FOR_EACH_REGNO (regno, *x)
7206 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7207 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7210 if (GET_CODE (*x) == MEM)
7212 /* If we ran out of memory slots, assume a conflict. */
7213 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7216 /* Check for output or true dependencies with earlier MEMs. */
7217 for (i = 0; i < frv_packet.num_mems; i++)
7218 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7220 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7224 if (output_dependence (frv_packet.mems[i].mem, *x))
7229 /* The return values of calls aren't significant: they describe
7230 the effect of the call as a whole, not of the insn itself. */
7231 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7233 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7238 /* Check subexpressions. */
7243 /* Return true if something in X might depend on an instruction
7244 in the current packet. */
7247 frv_registers_conflict_p (rtx x)
7252 if (GET_CODE (x) == COND_EXEC)
7254 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7257 flags |= frv_cond_flags (XEXP (x, 0));
7260 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7264 /* A note_stores callback. DATA points to the regstate_t condition
7265 under which X is modified. Update FRV_PACKET accordingly. */
7268 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7272 if (GET_CODE (x) == REG)
7273 FOR_EACH_REGNO (regno, x)
7274 frv_packet.regstate[regno] |= *(regstate_t *) data;
7276 if (GET_CODE (x) == MEM)
7278 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7280 frv_packet.mems[frv_packet.num_mems].mem = x;
7281 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7283 frv_packet.num_mems++;
7288 /* Update the register state information for an instruction whose
7292 frv_registers_update (rtx x)
7296 flags = REGSTATE_MODIFIED;
7297 if (GET_CODE (x) == COND_EXEC)
7299 flags |= frv_cond_flags (XEXP (x, 0));
7302 note_stores (x, frv_registers_update_1, &flags);
7306 /* Initialize frv_packet for the start of a new packet. */
7309 frv_start_packet (void)
7311 enum frv_insn_group group;
7313 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7314 frv_packet.num_mems = 0;
7315 frv_packet.num_insns = 0;
7316 for (group = 0; group < NUM_GROUPS; group++)
7317 frv_packet.groups[group].num_insns = 0;
7321 /* Likewise for the start of a new basic block. */
7324 frv_start_packet_block (void)
7326 state_reset (frv_packet.dfa_state);
7327 frv_start_packet ();
7331 /* Finish the current packet, if any, and start a new one. Call
7332 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7335 frv_finish_packet (void (*handle_packet) (void))
7337 if (frv_packet.num_insns > 0)
7340 state_transition (frv_packet.dfa_state, 0);
7341 frv_start_packet ();
7346 /* Return true if INSN can be added to the current packet. Update
7347 the DFA state on success. */
7350 frv_pack_insn_p (rtx insn)
7352 /* See if the packet is already as long as it can be. */
7353 if (frv_packet.num_insns == frv_packet.issue_rate)
7356 /* If the scheduler thought that an instruction should start a packet,
7357 it's usually a good idea to believe it. It knows much more about
7358 the latencies than we do.
7360 There are some exceptions though:
7362 - Conditional instructions are scheduled on the assumption that
7363 they will be executed. This is usually a good thing, since it
7364 tends to avoid unnecessary stalls in the conditional code.
7365 But we want to pack conditional instructions as tightly as
7366 possible, in order to optimize the case where they aren't
7369 - The scheduler will always put branches on their own, even
7370 if there's no real dependency.
7372 - There's no point putting a call in its own packet unless
7374 if (frv_packet.num_insns > 0
7375 && GET_CODE (insn) == INSN
7376 && GET_MODE (insn) == TImode
7377 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7380 /* Check for register conflicts. Don't do this for setlo since any
7381 conflict will be with the partnering sethi, with which it can
7383 if (get_attr_type (insn) != TYPE_SETLO)
7384 if (frv_registers_conflict_p (PATTERN (insn)))
7387 return state_transition (frv_packet.dfa_state, insn) < 0;
7391 /* Add instruction INSN to the current packet. */
7394 frv_add_insn_to_packet (rtx insn)
7396 struct frv_packet_group *packet_group;
7398 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7399 packet_group->insns[packet_group->num_insns++] = insn;
7400 frv_packet.insns[frv_packet.num_insns++] = insn;
7402 frv_registers_update (PATTERN (insn));
7406 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7407 packet ends in a branch or call, insert the nop before it, otherwise
7411 frv_insert_nop_in_packet (rtx insn)
7413 struct frv_packet_group *packet_group;
7416 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7417 last = frv_packet.insns[frv_packet.num_insns - 1];
7418 if (GET_CODE (last) != INSN)
7420 insn = emit_insn_before (PATTERN (insn), last);
7421 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7422 frv_packet.insns[frv_packet.num_insns++] = last;
7426 insn = emit_insn_after (PATTERN (insn), last);
7427 frv_packet.insns[frv_packet.num_insns++] = insn;
7429 packet_group->insns[packet_group->num_insns++] = insn;
7433 /* If packing is enabled, divide the instructions into packets and
7434 return true. Call HANDLE_PACKET for each complete packet. */
7437 frv_for_each_packet (void (*handle_packet) (void))
7439 rtx insn, next_insn;
7441 frv_packet.issue_rate = frv_issue_rate ();
7443 /* Early exit if we don't want to pack insns. */
7445 || !flag_schedule_insns_after_reload
7446 || !TARGET_VLIW_BRANCH
7447 || frv_packet.issue_rate == 1)
7450 /* Set up the initial packing state. */
7452 frv_packet.dfa_state = alloca (state_size ());
7454 frv_start_packet_block ();
7455 for (insn = get_insns (); insn != 0; insn = next_insn)
7460 code = GET_CODE (insn);
7461 next_insn = NEXT_INSN (insn);
7463 if (code == CODE_LABEL)
7465 frv_finish_packet (handle_packet);
7466 frv_start_packet_block ();
7470 switch (GET_CODE (PATTERN (insn)))
7479 /* Calls mustn't be packed on a TOMCAT. */
7480 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7481 frv_finish_packet (handle_packet);
7483 /* Since the last instruction in a packet determines the EH
7484 region, any exception-throwing instruction must come at
7485 the end of reordered packet. Insns that issue to a
7486 branch unit are bound to come last; for others it's
7487 too hard to predict. */
7488 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7489 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7490 frv_finish_packet (handle_packet);
7492 /* Finish the current packet if we can't add INSN to it.
7493 Simulate cycles until INSN is ready to issue. */
7494 if (!frv_pack_insn_p (insn))
7496 frv_finish_packet (handle_packet);
7497 while (!frv_pack_insn_p (insn))
7498 state_transition (frv_packet.dfa_state, 0);
7501 /* Add the instruction to the packet. */
7502 frv_add_insn_to_packet (insn);
7504 /* Calls and jumps end a packet, as do insns that throw
7506 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7507 frv_finish_packet (handle_packet);
7511 frv_finish_packet (handle_packet);
7516 /* Subroutine of frv_sort_insn_group. We are trying to sort
7517 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7518 language order. We have already picked a new position for
7519 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7520 These instructions will occupy elements [0, LOWER_SLOT) and
7521 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7522 the DFA state after issuing these instructions.
7524 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7525 of the unused instructions. Return true if one such permutation gives
7526 a valid ordering, leaving the successful permutation in sorted[].
7527 Do not modify sorted[] until a valid permutation is found. */
7530 frv_sort_insn_group_1 (enum frv_insn_group group,
7531 unsigned int lower_slot, unsigned int upper_slot,
7532 unsigned int issued, unsigned int num_insns,
7535 struct frv_packet_group *packet_group;
7541 /* Early success if we've filled all the slots. */
7542 if (lower_slot == upper_slot)
7545 packet_group = &frv_packet.groups[group];
7546 dfa_size = state_size ();
7547 test_state = alloca (dfa_size);
7549 /* Try issuing each unused instruction. */
7550 for (i = num_insns - 1; i + 1 != 0; i--)
7551 if (~issued & (1 << i))
7553 insn = packet_group->sorted[i];
7554 memcpy (test_state, state, dfa_size);
7555 if (state_transition (test_state, insn) < 0
7556 && cpu_unit_reservation_p (test_state,
7557 NTH_UNIT (group, upper_slot - 1))
7558 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7559 issued | (1 << i), num_insns,
7562 packet_group->sorted[upper_slot - 1] = insn;
7570 /* Compare two instructions by their frv_insn_unit. */
7573 frv_compare_insns (const void *first, const void *second)
7575 const rtx *const insn1 = (rtx const *) first,
7576 *const insn2 = (rtx const *) second;
7577 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7580 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7581 and sort it into assembly language order. See frv.md for a description of
7585 frv_sort_insn_group (enum frv_insn_group group)
7587 struct frv_packet_group *packet_group;
7588 unsigned int first, i, nop, max_unit, num_slots;
7589 state_t state, test_state;
7592 packet_group = &frv_packet.groups[group];
7594 /* Assume no nop is needed. */
7595 packet_group->nop = 0;
7597 if (packet_group->num_insns == 0)
7600 /* Copy insns[] to sorted[]. */
7601 memcpy (packet_group->sorted, packet_group->insns,
7602 sizeof (rtx) * packet_group->num_insns);
7604 /* Sort sorted[] by the unit that each insn tries to take first. */
7605 if (packet_group->num_insns > 1)
7606 qsort (packet_group->sorted, packet_group->num_insns,
7607 sizeof (rtx), frv_compare_insns);
7609 /* That's always enough for branch and control insns. */
7610 if (group == GROUP_B || group == GROUP_C)
7613 dfa_size = state_size ();
7614 state = alloca (dfa_size);
7615 test_state = alloca (dfa_size);
7617 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7618 consecutively and such that the DFA takes unit X when sorted[X]
7619 is added. Set STATE to the new DFA state. */
7620 state_reset (test_state);
7621 for (first = 0; first < packet_group->num_insns; first++)
7623 memcpy (state, test_state, dfa_size);
7624 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7625 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7629 /* If all the instructions issued in ascending order, we're done. */
7630 if (first == packet_group->num_insns)
7633 /* Add nops to the end of sorted[] and try each permutation until
7634 we find one that works. */
7635 for (nop = 0; nop < frv_num_nops; nop++)
7637 max_unit = frv_insn_unit (frv_nops[nop]);
7638 if (frv_unit_groups[max_unit] == group)
7640 packet_group->nop = frv_nops[nop];
7641 num_slots = UNIT_NUMBER (max_unit) + 1;
7642 for (i = packet_group->num_insns; i < num_slots; i++)
7643 packet_group->sorted[i] = frv_nops[nop];
7644 if (frv_sort_insn_group_1 (group, first, num_slots,
7645 (1 << first) - 1, num_slots, state))
7652 /* Sort the current packet into assembly-language order. Set packing
7653 flags as appropriate. */
7656 frv_reorder_packet (void)
7658 unsigned int cursor[NUM_GROUPS];
7659 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7660 unsigned int unit, to, from;
7661 enum frv_insn_group group;
7662 struct frv_packet_group *packet_group;
7664 /* First sort each group individually. */
7665 for (group = 0; group < NUM_GROUPS; group++)
7668 frv_sort_insn_group (group);
7671 /* Go through the unit template and try add an instruction from
7672 that unit's group. */
7674 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7676 group = frv_unit_groups[unit];
7677 packet_group = &frv_packet.groups[group];
7678 if (cursor[group] < packet_group->num_insns)
7680 /* frv_reorg should have added nops for us. */
7681 gcc_assert (packet_group->sorted[cursor[group]]
7682 != packet_group->nop);
7683 insns[to++] = packet_group->sorted[cursor[group]++];
7687 gcc_assert (to == frv_packet.num_insns);
7689 /* Clear the last instruction's packing flag, thus marking the end of
7690 a packet. Reorder the other instructions relative to it. */
7691 CLEAR_PACKING_FLAG (insns[to - 1]);
7692 for (from = 0; from < to - 1; from++)
7694 remove_insn (insns[from]);
7695 add_insn_before (insns[from], insns[to - 1], NULL);
7696 SET_PACKING_FLAG (insns[from]);
7701 /* Divide instructions into packets. Reorder the contents of each
7702 packet so that they are in the correct assembly-language order.
7704 Since this pass can change the raw meaning of the rtl stream, it must
7705 only be called at the last minute, just before the instructions are
7709 frv_pack_insns (void)
7711 if (frv_for_each_packet (frv_reorder_packet))
7712 frv_insn_packing_flag = 0;
7714 frv_insn_packing_flag = -1;
7717 /* See whether we need to add nops to group GROUP in order to
7718 make a valid packet. */
7721 frv_fill_unused_units (enum frv_insn_group group)
7723 unsigned int non_nops, nops, i;
7724 struct frv_packet_group *packet_group;
7726 packet_group = &frv_packet.groups[group];
7728 /* Sort the instructions into assembly-language order.
7729 Use nops to fill slots that are otherwise unused. */
7730 frv_sort_insn_group (group);
7732 /* See how many nops are needed before the final useful instruction. */
7734 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7735 while (packet_group->sorted[i++] == packet_group->nop)
7738 /* Insert that many nops into the instruction stream. */
7740 frv_insert_nop_in_packet (packet_group->nop);
7743 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7746 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7748 if (io1->const_address != 0 && io2->const_address != 0)
7749 return io1->const_address == io2->const_address;
7751 if (io1->var_address != 0 && io2->var_address != 0)
7752 return rtx_equal_p (io1->var_address, io2->var_address);
7757 /* Return true if operations IO1 and IO2 are guaranteed to complete
7761 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7763 /* The order of writes is always preserved. */
7764 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7767 /* The order of reads isn't preserved. */
7768 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7771 /* One operation is a write and the other is (or could be) a read.
7772 The order is only guaranteed if the accesses are to the same
7774 return frv_same_doubleword_p (io1, io2);
7777 /* Generalize I/O operation X so that it covers both X and Y. */
7780 frv_io_union (struct frv_io *x, const struct frv_io *y)
7782 if (x->type != y->type)
7783 x->type = FRV_IO_UNKNOWN;
7784 if (!frv_same_doubleword_p (x, y))
7786 x->const_address = 0;
7791 /* Fill IO with information about the load or store associated with
7792 membar instruction INSN. */
7795 frv_extract_membar (struct frv_io *io, rtx insn)
7797 extract_insn (insn);
7798 io->type = INTVAL (recog_data.operand[2]);
7799 io->const_address = INTVAL (recog_data.operand[1]);
7800 io->var_address = XEXP (recog_data.operand[0], 0);
7803 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7804 if X is a register and *DATA depends on X. */
7807 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7809 rtx *other = (rtx *) data;
7811 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7815 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7816 Remove every modified register from the set. */
7819 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7821 HARD_REG_SET *set = (HARD_REG_SET *) data;
7825 FOR_EACH_REGNO (regno, x)
7826 CLEAR_HARD_REG_BIT (*set, regno);
7829 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7830 Add every register in *X to the set. */
7833 frv_io_handle_use_1 (rtx *x, void *data)
7835 HARD_REG_SET *set = (HARD_REG_SET *) data;
7839 FOR_EACH_REGNO (regno, *x)
7840 SET_HARD_REG_BIT (*set, regno);
7845 /* A note_stores callback that applies frv_io_handle_use_1 to an
7846 entire rhs value. */
7849 frv_io_handle_use (rtx *x, void *data)
7851 for_each_rtx (x, frv_io_handle_use_1, data);
7854 /* Go through block BB looking for membars to remove. There are two
7855 cases where intra-block analysis is enough:
7857 - a membar is redundant if it occurs between two consecutive I/O
7858 operations and if those operations are guaranteed to complete
7861 - a membar for a __builtin_read is redundant if the result is
7862 used before the next I/O operation is issued.
7864 If the last membar in the block could not be removed, and there
7865 are guaranteed to be no I/O operations between that membar and
7866 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7869 Describe the block's first I/O operation in *NEXT_IO. Describe
7870 an unknown operation if the block doesn't do any I/O. */
7873 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7876 HARD_REG_SET used_regs;
7877 rtx next_membar, set, insn;
7880 /* NEXT_IO is the next I/O operation to be performed after the current
7881 instruction. It starts off as being an unknown operation. */
7882 memset (next_io, 0, sizeof (*next_io));
7884 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7885 next_is_end_p = true;
7887 /* If the current instruction is a __builtin_read or __builtin_write,
7888 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7889 is null if the membar has already been deleted.
7891 Note that the initialization here should only be needed to
7892 suppress warnings. */
7895 /* USED_REGS is the set of registers that are used before the
7896 next I/O instruction. */
7897 CLEAR_HARD_REG_SET (used_regs);
7899 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7900 if (GET_CODE (insn) == CALL_INSN)
7902 /* We can't predict what a call will do to volatile memory. */
7903 memset (next_io, 0, sizeof (struct frv_io));
7904 next_is_end_p = false;
7905 CLEAR_HARD_REG_SET (used_regs);
7907 else if (INSN_P (insn))
7908 switch (recog_memoized (insn))
7910 case CODE_FOR_optional_membar_qi:
7911 case CODE_FOR_optional_membar_hi:
7912 case CODE_FOR_optional_membar_si:
7913 case CODE_FOR_optional_membar_di:
7917 /* Local information isn't enough to decide whether this
7918 membar is needed. Stash it away for later. */
7919 *last_membar = insn;
7920 frv_extract_membar (next_io, insn);
7921 next_is_end_p = false;
7925 /* Check whether the I/O operation before INSN could be
7926 reordered with one described by NEXT_IO. If it can't,
7927 INSN will not be needed. */
7928 struct frv_io prev_io;
7930 frv_extract_membar (&prev_io, insn);
7931 if (frv_io_fixed_order_p (&prev_io, next_io))
7935 ";; [Local] Removing membar %d since order"
7936 " of accesses is guaranteed\n",
7937 INSN_UID (next_membar));
7939 insn = NEXT_INSN (insn);
7940 delete_insn (next_membar);
7948 /* Invalidate NEXT_IO's address if it depends on something that
7949 is clobbered by INSN. */
7950 if (next_io->var_address)
7951 note_stores (PATTERN (insn), frv_io_check_address,
7952 &next_io->var_address);
7954 /* If the next membar is associated with a __builtin_read,
7955 see if INSN reads from that address. If it does, and if
7956 the destination register is used before the next I/O access,
7957 there is no need for the membar. */
7958 set = PATTERN (insn);
7959 if (next_io->type == FRV_IO_READ
7960 && next_io->var_address != 0
7962 && GET_CODE (set) == SET
7963 && GET_CODE (SET_DEST (set)) == REG
7964 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7968 src = SET_SRC (set);
7969 if (GET_CODE (src) == ZERO_EXTEND)
7970 src = XEXP (src, 0);
7972 if (GET_CODE (src) == MEM
7973 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7977 ";; [Local] Removing membar %d since the target"
7978 " of %d is used before the I/O operation\n",
7979 INSN_UID (next_membar), INSN_UID (insn));
7981 if (next_membar == *last_membar)
7984 delete_insn (next_membar);
7989 /* If INSN has volatile references, forget about any registers
7990 that are used after it. Otherwise forget about uses that
7991 are (or might be) defined by INSN. */
7992 if (volatile_refs_p (PATTERN (insn)))
7993 CLEAR_HARD_REG_SET (used_regs);
7995 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
7997 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8002 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8003 FIRST_IO[X] describes the first operation performed by basic block X. */
8006 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8009 struct frv_io this_io, next_io;
8013 /* We need to keep the membar if there is an edge to the exit block. */
8014 FOR_EACH_EDGE (succ, ei, bb->succs)
8015 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8016 if (succ->dest == EXIT_BLOCK_PTR)
8019 /* Work out the union of all successor blocks. */
8020 ei = ei_start (bb->succs);
8021 ei_cond (ei, &succ);
8022 /* next_io = first_io[bb->succ->dest->index]; */
8023 next_io = first_io[succ->dest->index];
8024 ei = ei_start (bb->succs);
8025 if (ei_cond (ei, &succ))
8027 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8028 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8029 frv_io_union (&next_io, &first_io[succ->dest->index]);
8034 frv_extract_membar (&this_io, membar);
8035 if (frv_io_fixed_order_p (&this_io, &next_io))
8039 ";; [Global] Removing membar %d since order of accesses"
8040 " is guaranteed\n", INSN_UID (membar));
8042 delete_insn (membar);
8046 /* Remove redundant membars from the current function. */
8049 frv_optimize_membar (void)
8052 struct frv_io *first_io;
8055 compute_bb_for_insn ();
8056 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8057 last_membar = XCNEWVEC (rtx, last_basic_block);
8060 frv_optimize_membar_local (bb, &first_io[bb->index],
8061 &last_membar[bb->index]);
8064 if (last_membar[bb->index] != 0)
8065 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8071 /* Used by frv_reorg to keep track of the current packet's address. */
8072 static unsigned int frv_packet_address;
8074 /* If the current packet falls through to a label, try to pad the packet
8075 with nops in order to fit the label's alignment requirements. */
8078 frv_align_label (void)
8080 unsigned int alignment, target, nop;
8081 rtx x, last, barrier, label;
8083 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8084 maximum alignment of that packet, LABEL to the last label between
8085 the packets, and BARRIER to the last barrier. */
8086 last = frv_packet.insns[frv_packet.num_insns - 1];
8087 label = barrier = 0;
8089 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8093 unsigned int subalign = 1 << label_to_alignment (x);
8094 alignment = MAX (alignment, subalign);
8101 /* If -malign-labels, and the packet falls through to an unaligned
8102 label, try introducing a nop to align that label to 8 bytes. */
8103 if (TARGET_ALIGN_LABELS
8106 && frv_packet.num_insns < frv_packet.issue_rate)
8107 alignment = MAX (alignment, 8);
8109 /* Advance the address to the end of the current packet. */
8110 frv_packet_address += frv_packet.num_insns * 4;
8112 /* Work out the target address, after alignment. */
8113 target = (frv_packet_address + alignment - 1) & -alignment;
8115 /* If the packet falls through to the label, try to find an efficient
8116 padding sequence. */
8119 /* First try adding nops to the current packet. */
8120 for (nop = 0; nop < frv_num_nops; nop++)
8121 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8123 frv_insert_nop_in_packet (frv_nops[nop]);
8124 frv_packet_address += 4;
8127 /* If we still haven't reached the target, add some new packets that
8128 contain only nops. If there are two types of nop, insert an
8129 alternating sequence of frv_nops[0] and frv_nops[1], which will
8130 lead to packets like:
8137 etc. Just emit frv_nops[0] if that's the only nop we have. */
8138 last = frv_packet.insns[frv_packet.num_insns - 1];
8140 while (frv_packet_address < target)
8142 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8143 frv_packet_address += 4;
8144 if (frv_num_nops > 1)
8149 frv_packet_address = target;
8152 /* Subroutine of frv_reorg, called after each packet has been constructed
8156 frv_reorg_packet (void)
8158 frv_fill_unused_units (GROUP_I);
8159 frv_fill_unused_units (GROUP_FM);
8163 /* Add an instruction with pattern NOP to frv_nops[]. */
8166 frv_register_nop (rtx nop)
8168 nop = make_insn_raw (nop);
8169 NEXT_INSN (nop) = 0;
8170 PREV_INSN (nop) = 0;
8171 frv_nops[frv_num_nops++] = nop;
8174 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8175 into packets and check whether we need to insert nops in order to
8176 fulfill the processor's issue requirements. Also, if the user has
8177 requested a certain alignment for a label, try to meet that alignment
8178 by inserting nops in the previous packet. */
8183 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8184 frv_optimize_membar ();
8187 frv_register_nop (gen_nop ());
8189 frv_register_nop (gen_mnop ());
8190 if (TARGET_HARD_FLOAT)
8191 frv_register_nop (gen_fnop ());
8193 /* Estimate the length of each branch. Although this may change after
8194 we've inserted nops, it will only do so in big functions. */
8195 shorten_branches (get_insns ());
8197 frv_packet_address = 0;
8198 frv_for_each_packet (frv_reorg_packet);
8201 #define def_builtin(name, type, code) \
8202 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8204 struct builtin_description
8206 enum insn_code icode;
8208 enum frv_builtins code;
8209 enum rtx_code comparison;
8213 /* Media intrinsics that take a single, constant argument. */
8215 static struct builtin_description bdesc_set[] =
8217 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8220 /* Media intrinsics that take just one argument. */
8222 static struct builtin_description bdesc_1arg[] =
8224 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8225 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8226 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8227 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8228 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8229 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8232 /* Media intrinsics that take two arguments. */
8234 static struct builtin_description bdesc_2arg[] =
8236 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8237 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8238 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8239 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8240 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8241 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8242 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8243 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8244 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8245 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8246 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8247 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8248 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8249 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8250 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8251 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8252 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8253 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8254 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8255 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8256 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8257 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8258 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8259 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8260 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8261 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8262 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8265 /* Integer intrinsics that take two arguments and have no return value. */
8267 static struct builtin_description bdesc_int_void2arg[] =
8269 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8270 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8271 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8274 static struct builtin_description bdesc_prefetches[] =
8276 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8277 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8280 /* Media intrinsics that take two arguments, the first being an ACC number. */
8282 static struct builtin_description bdesc_cut[] =
8284 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8285 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8286 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8289 /* Two-argument media intrinsics with an immediate second argument. */
8291 static struct builtin_description bdesc_2argimm[] =
8293 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8294 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8295 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8296 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8297 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8298 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8299 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8300 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8301 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8302 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8303 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8304 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8305 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8306 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8307 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8308 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8309 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8312 /* Media intrinsics that take two arguments and return void, the first argument
8313 being a pointer to 4 words in memory. */
8315 static struct builtin_description bdesc_void2arg[] =
8317 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8318 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8321 /* Media intrinsics that take three arguments, the first being a const_int that
8322 denotes an accumulator, and that return void. */
8324 static struct builtin_description bdesc_void3arg[] =
8326 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8327 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8328 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8329 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8330 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8331 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8332 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8333 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8334 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8335 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8336 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8337 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8338 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8339 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8340 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8341 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8342 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8343 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8344 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8345 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8346 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8347 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8348 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8349 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8350 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8353 /* Media intrinsics that take two accumulator numbers as argument and
8356 static struct builtin_description bdesc_voidacc[] =
8358 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8359 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8360 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8361 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8362 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8363 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8366 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8367 a normal move and the ICODE is for the membar. */
8369 static struct builtin_description bdesc_loads[] =
8371 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8372 FRV_BUILTIN_READ8, 0, 0 },
8373 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8374 FRV_BUILTIN_READ16, 0, 0 },
8375 { CODE_FOR_optional_membar_si, "__builtin_read32",
8376 FRV_BUILTIN_READ32, 0, 0 },
8377 { CODE_FOR_optional_membar_di, "__builtin_read64",
8378 FRV_BUILTIN_READ64, 0, 0 }
8381 /* Likewise stores. */
8383 static struct builtin_description bdesc_stores[] =
8385 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8386 FRV_BUILTIN_WRITE8, 0, 0 },
8387 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8388 FRV_BUILTIN_WRITE16, 0, 0 },
8389 { CODE_FOR_optional_membar_si, "__builtin_write32",
8390 FRV_BUILTIN_WRITE32, 0, 0 },
8391 { CODE_FOR_optional_membar_di, "__builtin_write64",
8392 FRV_BUILTIN_WRITE64, 0, 0 },
8395 /* Initialize media builtins. */
8398 frv_init_builtins (void)
8400 tree endlink = void_list_node;
8401 tree accumulator = integer_type_node;
8402 tree integer = integer_type_node;
8403 tree voidt = void_type_node;
8404 tree uhalf = short_unsigned_type_node;
8405 tree sword1 = long_integer_type_node;
8406 tree uword1 = long_unsigned_type_node;
8407 tree sword2 = long_long_integer_type_node;
8408 tree uword2 = long_long_unsigned_type_node;
8409 tree uword4 = build_pointer_type (uword1);
8410 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8411 tree ubyte = unsigned_char_type_node;
8412 tree iacc = integer_type_node;
8414 #define UNARY(RET, T1) \
8415 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8417 #define BINARY(RET, T1, T2) \
8418 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8419 tree_cons (NULL_TREE, T2, endlink)))
8421 #define TRINARY(RET, T1, T2, T3) \
8422 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8423 tree_cons (NULL_TREE, T2, \
8424 tree_cons (NULL_TREE, T3, endlink))))
8426 #define QUAD(RET, T1, T2, T3, T4) \
8427 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8428 tree_cons (NULL_TREE, T2, \
8429 tree_cons (NULL_TREE, T3, \
8430 tree_cons (NULL_TREE, T4, endlink)))))
8432 tree void_ftype_void = build_function_type (voidt, endlink);
8434 tree void_ftype_acc = UNARY (voidt, accumulator);
8435 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8436 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8437 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8438 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8439 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8440 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8441 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8442 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8444 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8445 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8446 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8447 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8448 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8449 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8450 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8451 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8452 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8453 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8454 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8456 tree sw1_ftype_int = UNARY (sword1, integer);
8457 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8458 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8460 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8461 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8462 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8463 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8464 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8465 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8467 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8468 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8469 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8470 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8471 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8472 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8473 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8474 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8475 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8476 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8477 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8478 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8479 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8480 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8481 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8482 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8483 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8485 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8486 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8487 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8488 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8489 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8490 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8491 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8492 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8493 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8494 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8495 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8496 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8497 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8498 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8499 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8500 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8501 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8502 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8503 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8504 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8505 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8506 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8507 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8508 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8509 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8510 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8511 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8512 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8513 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8514 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8515 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8516 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8517 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8518 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8519 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8520 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8521 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8522 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8523 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8524 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8525 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8526 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8527 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8528 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8529 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8530 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8531 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8532 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8533 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8534 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8535 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8536 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8537 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8538 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8539 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8540 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8541 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8542 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8543 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8544 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8545 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8546 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8547 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8548 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8549 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8550 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8551 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8552 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8553 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8554 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8555 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8556 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8557 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8558 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8559 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8560 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8561 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8562 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8563 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8564 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8565 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8566 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8567 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8568 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8569 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8570 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8571 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8572 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8573 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8574 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8575 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8576 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8577 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8578 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8579 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8580 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8581 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8582 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8583 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8584 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8585 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8586 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8587 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8588 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8589 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8590 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8591 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8592 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8594 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8595 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8596 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8597 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8605 /* Set the names for various arithmetic operations according to the
8608 frv_init_libfuncs (void)
8610 set_optab_libfunc (smod_optab, SImode, "__modi");
8611 set_optab_libfunc (umod_optab, SImode, "__umodi");
8613 set_optab_libfunc (add_optab, DImode, "__addll");
8614 set_optab_libfunc (sub_optab, DImode, "__subll");
8615 set_optab_libfunc (smul_optab, DImode, "__mulll");
8616 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8617 set_optab_libfunc (smod_optab, DImode, "__modll");
8618 set_optab_libfunc (umod_optab, DImode, "__umodll");
8619 set_optab_libfunc (and_optab, DImode, "__andll");
8620 set_optab_libfunc (ior_optab, DImode, "__orll");
8621 set_optab_libfunc (xor_optab, DImode, "__xorll");
8622 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8624 set_optab_libfunc (add_optab, SFmode, "__addf");
8625 set_optab_libfunc (sub_optab, SFmode, "__subf");
8626 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8627 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8629 set_optab_libfunc (add_optab, DFmode, "__addd");
8630 set_optab_libfunc (sub_optab, DFmode, "__subd");
8631 set_optab_libfunc (smul_optab, DFmode, "__muld");
8632 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8634 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8635 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8637 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8638 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8639 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8640 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8642 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8643 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8644 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8645 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8647 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8648 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8649 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8650 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8653 /* Convert an integer constant to an accumulator register. ICODE is the
8654 code of the target instruction, OPNUM is the number of the
8655 accumulator operand and OPVAL is the constant integer. Try both
8656 ACC and ACCG registers; only report an error if neither fit the
8660 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8665 /* ACCs and ACCGs are implicit global registers if media intrinsics
8666 are being used. We set up this lazily to avoid creating lots of
8667 unnecessary call_insn rtl in non-media code. */
8668 for (i = 0; i <= ACC_MASK; i++)
8669 if ((i & ACC_MASK) == i)
8670 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8672 if (GET_CODE (opval) != CONST_INT)
8674 error ("accumulator is not a constant integer");
8677 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8679 error ("accumulator number is out of bounds");
8683 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8684 ACC_FIRST + INTVAL (opval));
8685 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8686 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8688 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8690 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8696 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8699 static enum machine_mode
8700 frv_matching_accg_mode (enum machine_mode mode)
8718 /* Given that a __builtin_read or __builtin_write function is accessing
8719 address ADDRESS, return the value that should be used as operand 1
8723 frv_io_address_cookie (rtx address)
8725 return (GET_CODE (address) == CONST_INT
8726 ? GEN_INT (INTVAL (address) / 8 * 8)
8730 /* Return the accumulator guard that should be paired with accumulator
8731 register ACC. The mode of the returned register is in the same
8732 class as ACC, but is four times smaller. */
8735 frv_matching_accg_for_acc (rtx acc)
8737 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8738 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8741 /* Read the requested argument from the call EXP given by INDEX.
8742 Return the value as an rtx. */
8745 frv_read_argument (tree exp, unsigned int index)
8747 return expand_expr (CALL_EXPR_ARG (exp, index),
8748 NULL_RTX, VOIDmode, 0);
8751 /* Like frv_read_argument, but interpret the argument as the number
8752 of an IACC register and return a (reg:MODE ...) rtx for it. */
8755 frv_read_iacc_argument (enum machine_mode mode, tree call,
8761 op = frv_read_argument (call, index);
8762 if (GET_CODE (op) != CONST_INT
8764 || INTVAL (op) > IACC_LAST - IACC_FIRST
8765 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8767 error ("invalid IACC argument");
8771 /* IACCs are implicit global registers. We set up this lazily to
8772 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8774 regno = INTVAL (op) + IACC_FIRST;
8775 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8776 global_regs[regno + i] = 1;
8778 return gen_rtx_REG (mode, regno);
8781 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8782 The instruction should require a constant operand of some sort. The
8783 function prints an error if OPVAL is not valid. */
8786 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8788 if (GET_CODE (opval) != CONST_INT)
8790 error ("%qs expects a constant argument", insn_data[icode].name);
8793 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8795 error ("constant argument out of range for %qs", insn_data[icode].name);
8801 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8802 if it's not null, has the right mode, and satisfies operand 0's
8806 frv_legitimize_target (enum insn_code icode, rtx target)
8808 enum machine_mode mode = insn_data[icode].operand[0].mode;
8811 || GET_MODE (target) != mode
8812 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8813 return gen_reg_rtx (mode);
8818 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8819 check whether ARG satisfies the operand's constraints. If it doesn't,
8820 copy ARG to a temporary register and return that. Otherwise return ARG
8824 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8826 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8828 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8831 return copy_to_mode_reg (mode, arg);
8834 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8837 frv_volatile_memref (enum machine_mode mode, rtx arg)
8841 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8842 MEM_VOLATILE_P (mem) = 1;
8846 /* Expand builtins that take a single, constant argument. At the moment,
8847 only MHDSETS falls into this category. */
8850 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8853 rtx op0 = frv_read_argument (call, 0);
8855 if (! frv_check_constant_argument (icode, 1, op0))
8858 target = frv_legitimize_target (icode, target);
8859 pat = GEN_FCN (icode) (target, op0);
8867 /* Expand builtins that take one operand. */
8870 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8873 rtx op0 = frv_read_argument (call, 0);
8875 target = frv_legitimize_target (icode, target);
8876 op0 = frv_legitimize_argument (icode, 1, op0);
8877 pat = GEN_FCN (icode) (target, op0);
8885 /* Expand builtins that take two operands. */
8888 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8891 rtx op0 = frv_read_argument (call, 0);
8892 rtx op1 = frv_read_argument (call, 1);
8894 target = frv_legitimize_target (icode, target);
8895 op0 = frv_legitimize_argument (icode, 1, op0);
8896 op1 = frv_legitimize_argument (icode, 2, op1);
8897 pat = GEN_FCN (icode) (target, op0, op1);
8905 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8909 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8912 rtx op0 = frv_read_argument (call, 0);
8913 rtx op1 = frv_read_argument (call, 1);
8916 target = frv_legitimize_target (icode, target);
8917 op0 = frv_int_to_acc (icode, 1, op0);
8921 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8923 if (! frv_check_constant_argument (icode, 2, op1))
8927 op1 = frv_legitimize_argument (icode, 2, op1);
8929 op2 = frv_matching_accg_for_acc (op0);
8930 pat = GEN_FCN (icode) (target, op0, op1, op2);
8938 /* Expand builtins that take two operands and the second is immediate. */
8941 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8944 rtx op0 = frv_read_argument (call, 0);
8945 rtx op1 = frv_read_argument (call, 1);
8947 if (! frv_check_constant_argument (icode, 2, op1))
8950 target = frv_legitimize_target (icode, target);
8951 op0 = frv_legitimize_argument (icode, 1, op0);
8952 pat = GEN_FCN (icode) (target, op0, op1);
8960 /* Expand builtins that take two operands, the first operand being a pointer to
8961 ints and return void. */
8964 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8967 rtx op0 = frv_read_argument (call, 0);
8968 rtx op1 = frv_read_argument (call, 1);
8969 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8972 if (GET_CODE (op0) != MEM)
8976 if (! offsettable_address_p (0, mode0, op0))
8978 reg = gen_reg_rtx (Pmode);
8979 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8982 op0 = gen_rtx_MEM (SImode, reg);
8985 addr = XEXP (op0, 0);
8986 if (! offsettable_address_p (0, mode0, addr))
8987 addr = copy_to_mode_reg (Pmode, op0);
8989 op0 = change_address (op0, V4SImode, addr);
8990 op1 = frv_legitimize_argument (icode, 1, op1);
8991 pat = GEN_FCN (icode) (op0, op1);
8999 /* Expand builtins that take two long operands and return void. */
9002 frv_expand_int_void2arg (enum insn_code icode, tree call)
9005 rtx op0 = frv_read_argument (call, 0);
9006 rtx op1 = frv_read_argument (call, 1);
9008 op0 = frv_legitimize_argument (icode, 1, op0);
9009 op1 = frv_legitimize_argument (icode, 1, op1);
9010 pat = GEN_FCN (icode) (op0, op1);
9018 /* Expand prefetch builtins. These take a single address as argument. */
9021 frv_expand_prefetches (enum insn_code icode, tree call)
9024 rtx op0 = frv_read_argument (call, 0);
9026 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9034 /* Expand builtins that take three operands and return void. The first
9035 argument must be a constant that describes a pair or quad accumulators. A
9036 fourth argument is created that is the accumulator guard register that
9037 corresponds to the accumulator. */
9040 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9043 rtx op0 = frv_read_argument (call, 0);
9044 rtx op1 = frv_read_argument (call, 1);
9045 rtx op2 = frv_read_argument (call, 2);
9048 op0 = frv_int_to_acc (icode, 0, op0);
9052 op1 = frv_legitimize_argument (icode, 1, op1);
9053 op2 = frv_legitimize_argument (icode, 2, op2);
9054 op3 = frv_matching_accg_for_acc (op0);
9055 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9063 /* Expand builtins that perform accumulator-to-accumulator operations.
9064 These builtins take two accumulator numbers as argument and return
9068 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9071 rtx op0 = frv_read_argument (call, 0);
9072 rtx op1 = frv_read_argument (call, 1);
9076 op0 = frv_int_to_acc (icode, 0, op0);
9080 op1 = frv_int_to_acc (icode, 1, op1);
9084 op2 = frv_matching_accg_for_acc (op0);
9085 op3 = frv_matching_accg_for_acc (op1);
9086 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9094 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9095 membar and TARGET_MODE is the mode that the loaded value should have. */
9098 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9099 tree call, rtx target)
9101 rtx op0 = frv_read_argument (call, 0);
9102 rtx cookie = frv_io_address_cookie (op0);
9104 if (target == 0 || !REG_P (target))
9105 target = gen_reg_rtx (target_mode);
9106 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9107 convert_move (target, op0, 1);
9108 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9109 cfun->machine->has_membar_p = 1;
9113 /* Likewise __builtin_write* functions. */
9116 frv_expand_store_builtin (enum insn_code icode, tree call)
9118 rtx op0 = frv_read_argument (call, 0);
9119 rtx op1 = frv_read_argument (call, 1);
9120 rtx cookie = frv_io_address_cookie (op0);
9122 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9123 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9124 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9125 cfun->machine->has_membar_p = 1;
9129 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9130 each argument forms one word of the two double-word input registers.
9131 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9132 to put the return value. */
9135 frv_expand_mdpackh_builtin (tree call, rtx target)
9137 enum insn_code icode = CODE_FOR_mdpackh;
9139 rtx arg1 = frv_read_argument (call, 0);
9140 rtx arg2 = frv_read_argument (call, 1);
9141 rtx arg3 = frv_read_argument (call, 2);
9142 rtx arg4 = frv_read_argument (call, 3);
9144 target = frv_legitimize_target (icode, target);
9145 op0 = gen_reg_rtx (DImode);
9146 op1 = gen_reg_rtx (DImode);
9148 /* The high half of each word is not explicitly initialized, so indicate
9149 that the input operands are not live before this point. */
9153 /* Move each argument into the low half of its associated input word. */
9154 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9155 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9156 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9157 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9159 pat = GEN_FCN (icode) (target, op0, op1);
9167 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9168 number as argument. */
9171 frv_expand_mclracc_builtin (tree call)
9173 enum insn_code icode = CODE_FOR_mclracc;
9175 rtx op0 = frv_read_argument (call, 0);
9177 op0 = frv_int_to_acc (icode, 0, op0);
9181 pat = GEN_FCN (icode) (op0);
9188 /* Expand builtins that take no arguments. */
9191 frv_expand_noargs_builtin (enum insn_code icode)
9193 rtx pat = GEN_FCN (icode) (const0_rtx);
9200 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9201 number or accumulator guard number as argument and return an SI integer. */
9204 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9207 rtx target = gen_reg_rtx (SImode);
9208 rtx op0 = frv_read_argument (call, 0);
9210 op0 = frv_int_to_acc (icode, 1, op0);
9214 pat = GEN_FCN (icode) (target, op0);
9222 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9223 accumulator guard as their first argument and an SImode value as their
9227 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9230 rtx op0 = frv_read_argument (call, 0);
9231 rtx op1 = frv_read_argument (call, 1);
9233 op0 = frv_int_to_acc (icode, 0, op0);
9237 op1 = frv_legitimize_argument (icode, 1, op1);
9238 pat = GEN_FCN (icode) (op0, op1);
9245 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9246 to move DImode values into and out of IACC0. */
9249 frv_split_iacc_move (rtx dest, rtx src)
9251 enum machine_mode inner;
9254 inner = GET_MODE (dest);
9255 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9256 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9257 simplify_gen_subreg (SImode, src, inner, i));
9260 /* Expand builtins. */
9263 frv_expand_builtin (tree exp,
9265 rtx subtarget ATTRIBUTE_UNUSED,
9266 enum machine_mode mode ATTRIBUTE_UNUSED,
9267 int ignore ATTRIBUTE_UNUSED)
9269 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9270 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9272 struct builtin_description *d;
9274 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9276 error ("media functions are not available unless -mmedia is used");
9282 case FRV_BUILTIN_MCOP1:
9283 case FRV_BUILTIN_MCOP2:
9284 case FRV_BUILTIN_MDUNPACKH:
9285 case FRV_BUILTIN_MBTOHE:
9286 if (! TARGET_MEDIA_REV1)
9288 error ("this media function is only available on the fr500");
9293 case FRV_BUILTIN_MQXMACHS:
9294 case FRV_BUILTIN_MQXMACXHS:
9295 case FRV_BUILTIN_MQMACXHS:
9296 case FRV_BUILTIN_MADDACCS:
9297 case FRV_BUILTIN_MSUBACCS:
9298 case FRV_BUILTIN_MASACCS:
9299 case FRV_BUILTIN_MDADDACCS:
9300 case FRV_BUILTIN_MDSUBACCS:
9301 case FRV_BUILTIN_MDASACCS:
9302 case FRV_BUILTIN_MABSHS:
9303 case FRV_BUILTIN_MDROTLI:
9304 case FRV_BUILTIN_MCPLHI:
9305 case FRV_BUILTIN_MCPLI:
9306 case FRV_BUILTIN_MDCUTSSI:
9307 case FRV_BUILTIN_MQSATHS:
9308 case FRV_BUILTIN_MHSETLOS:
9309 case FRV_BUILTIN_MHSETLOH:
9310 case FRV_BUILTIN_MHSETHIS:
9311 case FRV_BUILTIN_MHSETHIH:
9312 case FRV_BUILTIN_MHDSETS:
9313 case FRV_BUILTIN_MHDSETH:
9314 if (! TARGET_MEDIA_REV2)
9316 error ("this media function is only available on the fr400"
9322 case FRV_BUILTIN_SMASS:
9323 case FRV_BUILTIN_SMSSS:
9324 case FRV_BUILTIN_SMU:
9325 case FRV_BUILTIN_ADDSS:
9326 case FRV_BUILTIN_SUBSS:
9327 case FRV_BUILTIN_SLASS:
9328 case FRV_BUILTIN_SCUTSS:
9329 case FRV_BUILTIN_IACCreadll:
9330 case FRV_BUILTIN_IACCreadl:
9331 case FRV_BUILTIN_IACCsetll:
9332 case FRV_BUILTIN_IACCsetl:
9333 if (!TARGET_FR405_BUILTINS)
9335 error ("this builtin function is only available"
9336 " on the fr405 and fr450");
9341 case FRV_BUILTIN_PREFETCH:
9342 if (!TARGET_FR500_FR550_BUILTINS)
9344 error ("this builtin function is only available on the fr500"
9350 case FRV_BUILTIN_MQLCLRHS:
9351 case FRV_BUILTIN_MQLMTHS:
9352 case FRV_BUILTIN_MQSLLHI:
9353 case FRV_BUILTIN_MQSRAHI:
9354 if (!TARGET_MEDIA_FR450)
9356 error ("this builtin function is only available on the fr450");
9365 /* Expand unique builtins. */
9369 case FRV_BUILTIN_MTRAP:
9370 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9372 case FRV_BUILTIN_MCLRACC:
9373 return frv_expand_mclracc_builtin (exp);
9375 case FRV_BUILTIN_MCLRACCA:
9377 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9379 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9381 case FRV_BUILTIN_MRDACC:
9382 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9384 case FRV_BUILTIN_MRDACCG:
9385 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9387 case FRV_BUILTIN_MWTACC:
9388 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9390 case FRV_BUILTIN_MWTACCG:
9391 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9393 case FRV_BUILTIN_MDPACKH:
9394 return frv_expand_mdpackh_builtin (exp, target);
9396 case FRV_BUILTIN_IACCreadll:
9398 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9399 if (target == 0 || !REG_P (target))
9400 target = gen_reg_rtx (DImode);
9401 frv_split_iacc_move (target, src);
9405 case FRV_BUILTIN_IACCreadl:
9406 return frv_read_iacc_argument (SImode, exp, 0);
9408 case FRV_BUILTIN_IACCsetll:
9410 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9411 rtx src = frv_read_argument (exp, 1);
9412 frv_split_iacc_move (dest, force_reg (DImode, src));
9416 case FRV_BUILTIN_IACCsetl:
9418 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9419 rtx src = frv_read_argument (exp, 1);
9420 emit_move_insn (dest, force_reg (SImode, src));
9428 /* Expand groups of builtins. */
9430 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9431 if (d->code == fcode)
9432 return frv_expand_set_builtin (d->icode, exp, target);
9434 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9435 if (d->code == fcode)
9436 return frv_expand_unop_builtin (d->icode, exp, target);
9438 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9439 if (d->code == fcode)
9440 return frv_expand_binop_builtin (d->icode, exp, target);
9442 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9443 if (d->code == fcode)
9444 return frv_expand_cut_builtin (d->icode, exp, target);
9446 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9447 if (d->code == fcode)
9448 return frv_expand_binopimm_builtin (d->icode, exp, target);
9450 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9451 if (d->code == fcode)
9452 return frv_expand_voidbinop_builtin (d->icode, exp);
9454 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9455 if (d->code == fcode)
9456 return frv_expand_voidtriop_builtin (d->icode, exp);
9458 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9459 if (d->code == fcode)
9460 return frv_expand_voidaccop_builtin (d->icode, exp);
9462 for (i = 0, d = bdesc_int_void2arg;
9463 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9464 if (d->code == fcode)
9465 return frv_expand_int_void2arg (d->icode, exp);
9467 for (i = 0, d = bdesc_prefetches;
9468 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9469 if (d->code == fcode)
9470 return frv_expand_prefetches (d->icode, exp);
9472 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9473 if (d->code == fcode)
9474 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9477 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9478 if (d->code == fcode)
9479 return frv_expand_store_builtin (d->icode, exp);
9485 frv_in_small_data_p (const_tree decl)
9488 const_tree section_name;
9490 /* Don't apply the -G flag to internal compiler structures. We
9491 should leave such structures in the main data section, partly
9492 for efficiency and partly because the size of some of them
9493 (such as C++ typeinfos) is not known until later. */
9494 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9497 /* If we already know which section the decl should be in, see if
9498 it's a small data section. */
9499 section_name = DECL_SECTION_NAME (decl);
9502 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9503 if (frv_string_begins_with (section_name, ".sdata"))
9505 if (frv_string_begins_with (section_name, ".sbss"))
9510 size = int_size_in_bytes (TREE_TYPE (decl));
9511 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9518 frv_rtx_costs (rtx x,
9519 int code ATTRIBUTE_UNUSED,
9520 int outer_code ATTRIBUTE_UNUSED,
9522 bool speed ATTRIBUTE_UNUSED)
9524 if (outer_code == MEM)
9526 /* Don't differentiate between memory addresses. All the ones
9527 we accept have equal cost. */
9528 *total = COSTS_N_INSNS (0);
9535 /* Make 12-bit integers really cheap. */
9536 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9547 *total = COSTS_N_INSNS (2);
9561 if (GET_MODE (x) == SImode)
9562 *total = COSTS_N_INSNS (1);
9563 else if (GET_MODE (x) == DImode)
9564 *total = COSTS_N_INSNS (2);
9566 *total = COSTS_N_INSNS (3);
9570 if (GET_MODE (x) == SImode)
9571 *total = COSTS_N_INSNS (2);
9573 *total = COSTS_N_INSNS (6); /* guess */
9580 *total = COSTS_N_INSNS (18);
9584 *total = COSTS_N_INSNS (3);
9593 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9595 switch_to_section (ctors_section);
9596 assemble_align (POINTER_SIZE);
9599 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9604 assemble_integer_with_op ("\t.picptr\t", symbol);
9608 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9610 switch_to_section (dtors_section);
9611 assemble_align (POINTER_SIZE);
9614 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9619 assemble_integer_with_op ("\t.picptr\t", symbol);
9622 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9625 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9626 int incoming ATTRIBUTE_UNUSED)
9628 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9631 #define TLS_BIAS (2048 - 16)
9633 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9634 We need to emit DTP-relative relocations. */
9637 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9639 gcc_assert (size == 4);
9640 fputs ("\t.picptr\ttlsmoff(", file);
9641 /* We want the unbiased TLS offset, so add the bias to the
9642 expression, such that the implicit biasing cancels out. */
9643 output_addr_const (file, plus_constant (x, TLS_BIAS));