1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Define the information needed to generate branch and scc insns. This is
197 stored from the compare operation. */
201 /* Conditional execution support gathered together in one structure. */
204 /* Linked list of insns to add if the conditional execution conversion was
205 successful. Each link points to an EXPR_LIST which points to the pattern
206 of the insn to add, and the insn to be inserted before. */
207 rtx added_insns_list;
209 /* Identify which registers are safe to allocate for if conversions to
210 conditional execution. We keep the last allocated register in the
211 register classes between COND_EXEC statements. This will mean we allocate
212 different registers for each different COND_EXEC group if we can. This
213 might allow the scheduler to intermix two different COND_EXEC sections. */
214 frv_tmp_reg_t tmp_reg;
216 /* For nested IFs, identify which CC registers are used outside of setting
217 via a compare isnsn, and using via a check insn. This will allow us to
218 know if we can rewrite the register to use a different register that will
219 be paired with the CR register controlling the nested IF-THEN blocks. */
220 HARD_REG_SET nested_cc_ok_rewrite;
222 /* Temporary registers allocated to hold constants during conditional
224 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
226 /* Current number of temp registers available. */
227 int cur_scratch_regs;
229 /* Number of nested conditional execution blocks. */
230 int num_nested_cond_exec;
232 /* Map of insns that set up constants in scratch registers. */
233 bitmap scratch_insns_bitmap;
235 /* Conditional execution test register (CC0..CC7). */
238 /* Conditional execution compare register that is paired with cr_reg, so that
239 nested compares can be done. The csubcc and caddcc instructions don't
240 have enough bits to specify both a CC register to be set and a CR register
241 to do the test on, so the same bit number is used for both. Needless to
242 say, this is rather inconvenient for GCC. */
245 /* Extra CR registers used for &&, ||. */
249 /* Previous CR used in nested if, to make sure we are dealing with the same
250 nested if as the previous statement. */
251 rtx last_nested_if_cr;
255 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
257 /* Map register number to smallest register class. */
258 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
260 /* Map class letter into register class. */
261 enum reg_class reg_class_from_letter[256];
263 /* Cached value of frv_stack_info. */
264 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
267 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
269 /* Forward references */
271 static bool frv_handle_option (size_t, const char *, int);
272 static int frv_default_flags_for_cpu (void);
273 static int frv_string_begins_with (const_tree, const char *);
274 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
281 static rtx single_set_pattern (rtx);
282 static int frv_function_contains_far_jump (void);
283 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
287 static rtx frv_frame_offset_rtx (int);
288 static rtx frv_frame_mem (enum machine_mode, rtx, int);
289 static rtx frv_dwarf_store (rtx, int);
290 static void frv_frame_insn (rtx, rtx);
291 static void frv_frame_access (frv_frame_accessor_t*,
293 static void frv_frame_access_multi (frv_frame_accessor_t*,
295 static void frv_frame_access_standard_regs (enum frv_stack_op,
297 static struct machine_function *frv_init_machine_status (void);
298 static rtx frv_int_to_acc (enum insn_code, int, rtx);
299 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
300 static rtx frv_read_argument (tree, unsigned int);
301 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
302 static int frv_check_constant_argument (enum insn_code, int, rtx);
303 static rtx frv_legitimize_target (enum insn_code, rtx);
304 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
305 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static int frv_clear_registers_used (rtx *, void *);
323 static void frv_ifcvt_add_insn (rtx, rtx, int);
324 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
325 static rtx frv_ifcvt_load_value (rtx, rtx);
326 static int frv_acc_group_1 (rtx *, void *);
327 static unsigned int frv_insn_unit (rtx);
328 static bool frv_issues_to_branch_unit_p (rtx);
329 static int frv_cond_flags (rtx);
330 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
331 static int frv_registers_conflict_p_1 (rtx *, void *);
332 static bool frv_registers_conflict_p (rtx);
333 static void frv_registers_update_1 (rtx, const_rtx, void *);
334 static void frv_registers_update (rtx);
335 static void frv_start_packet (void);
336 static void frv_start_packet_block (void);
337 static void frv_finish_packet (void (*) (void));
338 static bool frv_pack_insn_p (rtx);
339 static void frv_add_insn_to_packet (rtx);
340 static void frv_insert_nop_in_packet (rtx);
341 static bool frv_for_each_packet (void (*) (void));
342 static bool frv_sort_insn_group_1 (enum frv_insn_group,
343 unsigned int, unsigned int,
344 unsigned int, unsigned int,
346 static int frv_compare_insns (const void *, const void *);
347 static void frv_sort_insn_group (enum frv_insn_group);
348 static void frv_reorder_packet (void);
349 static void frv_fill_unused_units (enum frv_insn_group);
350 static void frv_align_label (void);
351 static void frv_reorg_packet (void);
352 static void frv_register_nop (rtx);
353 static void frv_reorg (void);
354 static void frv_pack_insns (void);
355 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
356 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
357 static bool frv_assemble_integer (rtx, unsigned, int);
358 static void frv_init_builtins (void);
359 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
360 static void frv_init_libfuncs (void);
361 static bool frv_in_small_data_p (const_tree);
362 static void frv_asm_output_mi_thunk
363 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
364 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
367 static rtx frv_expand_builtin_saveregs (void);
368 static void frv_expand_builtin_va_start (tree, rtx);
369 static bool frv_rtx_costs (rtx, int, int, int*, bool);
370 static void frv_asm_out_constructor (rtx, int);
371 static void frv_asm_out_destructor (rtx, int);
372 static bool frv_function_symbol_referenced_p (rtx);
373 static bool frv_cannot_force_const_mem (rtx);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec *);
377 static bool frv_function_ok_for_sibcall (tree, tree);
378 static rtx frv_struct_value_rtx (tree, int);
379 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
380 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
382 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
384 static bool frv_secondary_reload (bool, rtx, enum reg_class,
386 secondary_reload_info *);
388 /* Allow us to easily change the default for -malloc-cc. */
389 #ifndef DEFAULT_NO_ALLOC_CC
390 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
392 #define MASK_DEFAULT_ALLOC_CC 0
395 /* Initialize the GCC target structure. */
396 #undef TARGET_ASM_FUNCTION_PROLOGUE
397 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
398 #undef TARGET_ASM_FUNCTION_EPILOGUE
399 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
400 #undef TARGET_ASM_INTEGER
401 #define TARGET_ASM_INTEGER frv_assemble_integer
402 #undef TARGET_DEFAULT_TARGET_FLAGS
403 #define TARGET_DEFAULT_TARGET_FLAGS \
404 (MASK_DEFAULT_ALLOC_CC \
411 #undef TARGET_HANDLE_OPTION
412 #define TARGET_HANDLE_OPTION frv_handle_option
413 #undef TARGET_INIT_BUILTINS
414 #define TARGET_INIT_BUILTINS frv_init_builtins
415 #undef TARGET_EXPAND_BUILTIN
416 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
417 #undef TARGET_INIT_LIBFUNCS
418 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
419 #undef TARGET_IN_SMALL_DATA_P
420 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
421 #undef TARGET_RTX_COSTS
422 #define TARGET_RTX_COSTS frv_rtx_costs
423 #undef TARGET_ASM_CONSTRUCTOR
424 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
425 #undef TARGET_ASM_DESTRUCTOR
426 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
428 #undef TARGET_ASM_OUTPUT_MI_THUNK
429 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
430 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
431 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
433 #undef TARGET_SCHED_ISSUE_RATE
434 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
436 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
437 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
438 #undef TARGET_CANNOT_FORCE_CONST_MEM
439 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
441 #undef TARGET_HAVE_TLS
442 #define TARGET_HAVE_TLS HAVE_AS_TLS
444 #undef TARGET_STRUCT_VALUE_RTX
445 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
446 #undef TARGET_MUST_PASS_IN_STACK
447 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
448 #undef TARGET_PASS_BY_REFERENCE
449 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
450 #undef TARGET_ARG_PARTIAL_BYTES
451 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
453 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
454 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
455 #undef TARGET_SETUP_INCOMING_VARARGS
456 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
457 #undef TARGET_MACHINE_DEPENDENT_REORG
458 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
460 #undef TARGET_EXPAND_BUILTIN_VA_START
461 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
464 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
465 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
468 #undef TARGET_SECONDARY_RELOAD
469 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
471 struct gcc_target targetm = TARGET_INITIALIZER;
473 #define FRV_SYMBOL_REF_TLS_P(RTX) \
474 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
477 /* Any function call that satisfies the machine-independent
478 requirements is eligible on FR-V. */
481 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
482 tree exp ATTRIBUTE_UNUSED)
487 /* Return true if SYMBOL is a small data symbol and relocation RELOC
488 can be used to access it directly in a load or store. */
490 static FRV_INLINE bool
491 frv_small_data_reloc_p (rtx symbol, int reloc)
493 return (GET_CODE (symbol) == SYMBOL_REF
494 && SYMBOL_REF_SMALL_P (symbol)
495 && (!TARGET_FDPIC || flag_pic == 1)
496 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
499 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
503 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
505 if (GET_CODE (x) == CONST)
509 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
511 unspec->offset += INTVAL (XEXP (x, 1));
514 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
516 unspec->symbol = XVECEXP (x, 0, 0);
517 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
519 if (unspec->offset == 0)
522 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
523 && unspec->offset > 0
524 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
531 /* Decide whether we can force certain constants to memory. If we
532 decide we can't, the caller should be able to cope with it in
535 We never allow constants to be forced into memory for TARGET_FDPIC.
536 This is necessary for several reasons:
538 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
539 target-independent code will try to force them into the constant
540 pool, thus leading to infinite recursion.
542 2. We can never introduce new constant pool references during reload.
543 Any such reference would require use of the pseudo FDPIC register.
545 3. We can't represent a constant added to a function pointer (which is
546 not the same as a pointer to a function+constant).
548 4. In many cases, it's more efficient to calculate the constant in-line. */
551 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
556 /* Implement TARGET_HANDLE_OPTION. */
559 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
564 if (strcmp (arg, "simple") == 0)
565 frv_cpu_type = FRV_CPU_SIMPLE;
566 else if (strcmp (arg, "tomcat") == 0)
567 frv_cpu_type = FRV_CPU_TOMCAT;
568 else if (strcmp (arg, "fr550") == 0)
569 frv_cpu_type = FRV_CPU_FR550;
570 else if (strcmp (arg, "fr500") == 0)
571 frv_cpu_type = FRV_CPU_FR500;
572 else if (strcmp (arg, "fr450") == 0)
573 frv_cpu_type = FRV_CPU_FR450;
574 else if (strcmp (arg, "fr405") == 0)
575 frv_cpu_type = FRV_CPU_FR405;
576 else if (strcmp (arg, "fr400") == 0)
577 frv_cpu_type = FRV_CPU_FR400;
578 else if (strcmp (arg, "fr300") == 0)
579 frv_cpu_type = FRV_CPU_FR300;
580 else if (strcmp (arg, "frv") == 0)
581 frv_cpu_type = FRV_CPU_GENERIC;
592 frv_default_flags_for_cpu (void)
594 switch (frv_cpu_type)
596 case FRV_CPU_GENERIC:
597 return MASK_DEFAULT_FRV;
600 return MASK_DEFAULT_FR550;
604 return MASK_DEFAULT_FR500;
607 return MASK_DEFAULT_FR450;
611 return MASK_DEFAULT_FR400;
615 return MASK_DEFAULT_SIMPLE;
622 /* Sometimes certain combinations of command options do not make
623 sense on a particular target machine. You can define a macro
624 `OVERRIDE_OPTIONS' to take account of this. This macro, if
625 defined, is executed once just after all the command options have
628 Don't use this macro to turn on various extra optimizations for
629 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
632 frv_override_options (void)
637 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
639 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
640 linker about linking pic and non-pic code. */
643 if (!flag_pic) /* -fPIC */
646 if (! g_switch_set) /* -G0 */
653 /* A C expression whose value is a register class containing hard
654 register REGNO. In general there is more than one such class;
655 choose a class which is "minimal", meaning that no smaller class
656 also contains the register. */
658 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
660 enum reg_class rclass;
664 int gpr_reg = regno - GPR_FIRST;
666 if (gpr_reg == GR8_REG)
669 else if (gpr_reg == GR9_REG)
672 else if (gpr_reg == GR14_REG)
673 rclass = FDPIC_FPTR_REGS;
675 else if (gpr_reg == FDPIC_REGNO)
678 else if ((gpr_reg & 3) == 0)
681 else if ((gpr_reg & 1) == 0)
688 else if (FPR_P (regno))
690 int fpr_reg = regno - GPR_FIRST;
691 if ((fpr_reg & 3) == 0)
692 rclass = QUAD_FPR_REGS;
694 else if ((fpr_reg & 1) == 0)
701 else if (regno == LR_REGNO)
704 else if (regno == LCR_REGNO)
707 else if (ICC_P (regno))
710 else if (FCC_P (regno))
713 else if (ICR_P (regno))
716 else if (FCR_P (regno))
719 else if (ACC_P (regno))
721 int r = regno - ACC_FIRST;
723 rclass = QUAD_ACC_REGS;
724 else if ((r & 1) == 0)
725 rclass = EVEN_ACC_REGS;
730 else if (ACCG_P (regno))
736 regno_reg_class[regno] = rclass;
739 /* Check for small data option */
741 g_switch_value = SDATA_DEFAULT_SIZE;
743 /* A C expression which defines the machine-dependent operand
744 constraint letters for register classes. If CHAR is such a
745 letter, the value should be the register class corresponding to
746 it. Otherwise, the value should be `NO_REGS'. The register
747 letter `r', corresponding to class `GENERAL_REGS', will not be
748 passed to this macro; you do not need to handle it.
750 The following letters are unavailable, due to being used as
755 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
756 'Q', 'R', 'S', 'T', 'U'
758 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
760 for (i = 0; i < 256; i++)
761 reg_class_from_letter[i] = NO_REGS;
763 reg_class_from_letter['a'] = ACC_REGS;
764 reg_class_from_letter['b'] = EVEN_ACC_REGS;
765 reg_class_from_letter['c'] = CC_REGS;
766 reg_class_from_letter['d'] = GPR_REGS;
767 reg_class_from_letter['e'] = EVEN_REGS;
768 reg_class_from_letter['f'] = FPR_REGS;
769 reg_class_from_letter['h'] = FEVEN_REGS;
770 reg_class_from_letter['l'] = LR_REG;
771 reg_class_from_letter['q'] = QUAD_REGS;
772 reg_class_from_letter['t'] = ICC_REGS;
773 reg_class_from_letter['u'] = FCC_REGS;
774 reg_class_from_letter['v'] = ICR_REGS;
775 reg_class_from_letter['w'] = FCR_REGS;
776 reg_class_from_letter['x'] = QUAD_FPR_REGS;
777 reg_class_from_letter['y'] = LCR_REG;
778 reg_class_from_letter['z'] = SPR_REGS;
779 reg_class_from_letter['A'] = QUAD_ACC_REGS;
780 reg_class_from_letter['B'] = ACCG_REGS;
781 reg_class_from_letter['C'] = CR_REGS;
782 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
783 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
785 /* There is no single unaligned SI op for PIC code. Sometimes we
786 need to use ".4byte" and sometimes we need to use ".picptr".
787 See frv_assemble_integer for details. */
788 if (flag_pic || TARGET_FDPIC)
789 targetm.asm_out.unaligned_op.si = 0;
791 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
792 target_flags |= MASK_LINKED_FP;
794 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
795 target_flags |= MASK_OPTIMIZE_MEMBAR;
797 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
798 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
800 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
801 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
803 init_machine_status = frv_init_machine_status;
807 /* Some machines may desire to change what optimizations are performed for
808 various optimization levels. This macro, if defined, is executed once just
809 after the optimization level is determined and before the remainder of the
810 command options have been parsed. Values set in this macro are used as the
811 default values for the other command line options.
813 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
814 `-O' is specified, and 0 if neither is specified.
816 SIZE is nonzero if `-Os' is specified, 0 otherwise.
818 You should not use this macro to change options that are not
819 machine-specific. These should uniformly selected by the same optimization
820 level on all supported machines. Use this macro to enable machine-specific
823 *Do not examine `write_symbols' in this macro!* The debugging options are
824 *not supposed to alter the generated code. */
826 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
827 scheduling pass at the current time. */
829 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
833 #ifdef DISABLE_SCHED2
834 flag_schedule_insns_after_reload = 0;
843 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
846 frv_string_begins_with (const_tree name, const char *prefix)
848 const int prefix_len = strlen (prefix);
850 /* Remember: NAME's length includes the null terminator. */
851 return (TREE_STRING_LENGTH (name) > prefix_len
852 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
855 /* Zero or more C statements that may conditionally modify two variables
856 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
857 been initialized from the two preceding macros.
859 This is necessary in case the fixed or call-clobbered registers depend on
862 You need not define this macro if it has no work to do.
864 If the usage of an entire class of registers depends on the target flags,
865 you may indicate this to GCC by using this macro to modify `fixed_regs' and
866 `call_used_regs' to 1 for each of the registers in the classes which should
867 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
868 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
870 (However, if this class is not included in `GENERAL_REGS' and all of the
871 insn patterns whose constraints permit this class are controlled by target
872 switches, then GCC will automatically avoid using these registers when the
873 target switches are opposed to them.) */
876 frv_conditional_register_usage (void)
880 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
881 fixed_regs[i] = call_used_regs[i] = 1;
883 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
884 fixed_regs[i] = call_used_regs[i] = 1;
886 /* Reserve the registers used for conditional execution. At present, we need
887 1 ICC and 1 ICR register. */
888 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
889 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
893 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
894 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
895 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
896 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
900 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
901 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
904 /* If -fpic, SDA_BASE_REG is the PIC register. */
905 if (g_switch_value == 0 && !flag_pic)
906 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
909 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
915 * Compute the stack frame layout
918 * +---------------+-----------------------+-----------------------+
919 * |Register |type |caller-save/callee-save|
920 * +---------------+-----------------------+-----------------------+
921 * |GR0 |Zero register | - |
922 * |GR1 |Stack pointer(SP) | - |
923 * |GR2 |Frame pointer(FP) | - |
924 * |GR3 |Hidden parameter | caller save |
925 * |GR4-GR7 | - | caller save |
926 * |GR8-GR13 |Argument register | caller save |
927 * |GR14-GR15 | - | caller save |
928 * |GR16-GR31 | - | callee save |
929 * |GR32-GR47 | - | caller save |
930 * |GR48-GR63 | - | callee save |
931 * |FR0-FR15 | - | caller save |
932 * |FR16-FR31 | - | callee save |
933 * |FR32-FR47 | - | caller save |
934 * |FR48-FR63 | - | callee save |
935 * +---------------+-----------------------+-----------------------+
939 * SP-> |-----------------------------------|
941 * |-----------------------------------|
942 * | Register save area |
943 * |-----------------------------------|
944 * | Local variable save area |
945 * FP-> |-----------------------------------|
947 * |-----------------------------------|
948 * | Hidden parameter save area |
949 * |-----------------------------------|
950 * | Return address(LR) storage area |
951 * |-----------------------------------|
952 * | Padding for alignment |
953 * |-----------------------------------|
954 * | Register argument area |
955 * OLD SP-> |-----------------------------------|
957 * |-----------------------------------|
960 * Argument area/Parameter area:
962 * When a function is called, this area is used for argument transfer. When
963 * the argument is set up by the caller function, this area is referred to as
964 * the argument area. When the argument is referenced by the callee function,
965 * this area is referred to as the parameter area. The area is allocated when
966 * all arguments cannot be placed on the argument register at the time of
969 * Register save area:
971 * This is a register save area that must be guaranteed for the caller
972 * function. This area is not secured when the register save operation is not
975 * Local variable save area:
977 * This is the area for local variables and temporary variables.
981 * This area stores the FP value of the caller function.
983 * Hidden parameter save area:
985 * This area stores the start address of the return value storage
986 * area for a struct/union return function.
987 * When a struct/union is used as the return value, the caller
988 * function stores the return value storage area start address in
989 * register GR3 and passes it to the caller function.
990 * The callee function interprets the address stored in the GR3
991 * as the return value storage area start address.
992 * When register GR3 needs to be saved into memory, the callee
993 * function saves it in the hidden parameter save area. This
994 * area is not secured when the save operation is not needed.
996 * Return address(LR) storage area:
998 * This area saves the LR. The LR stores the address of a return to the caller
999 * function for the purpose of function calling.
1001 * Argument register area:
1003 * This area saves the argument register. This area is not secured when the
1004 * save operation is not needed.
1008 * Arguments, the count of which equals the count of argument registers (6
1009 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1010 * function. When a struct/union return function is called, the return value
1011 * area address is stored in register GR3. Arguments not placed in the
1012 * argument registers will be stored in the stack argument area for transfer
1013 * purposes. When an 8-byte type argument is to be delivered using registers,
1014 * it is divided into two and placed in two registers for transfer. When
1015 * argument registers must be saved to memory, the callee function secures an
1016 * argument register save area in the stack. In this case, a continuous
1017 * argument register save area must be established in the parameter area. The
1018 * argument register save area must be allocated as needed to cover the size of
1019 * the argument register to be saved. If the function has a variable count of
1020 * arguments, it saves all argument registers in the argument register save
1023 * Argument Extension Format:
1025 * When an argument is to be stored in the stack, its type is converted to an
1026 * extended type in accordance with the individual argument type. The argument
1027 * is freed by the caller function after the return from the callee function is
1030 * +-----------------------+---------------+------------------------+
1031 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1032 * +-----------------------+---------------+------------------------+
1034 * |signed char |int | 4 |
1035 * |unsigned char |int | 4 |
1036 * |[signed] short int |int | 4 |
1037 * |unsigned short int |int | 4 |
1038 * |[signed] int |No extension | 4 |
1039 * |unsigned int |No extension | 4 |
1040 * |[signed] long int |No extension | 4 |
1041 * |unsigned long int |No extension | 4 |
1042 * |[signed] long long int |No extension | 8 |
1043 * |unsigned long long int |No extension | 8 |
1044 * |float |double | 8 |
1045 * |double |No extension | 8 |
1046 * |long double |No extension | 8 |
1047 * |pointer |No extension | 4 |
1048 * |struct/union |- | 4 (*1) |
1049 * +-----------------------+---------------+------------------------+
1051 * When a struct/union is to be delivered as an argument, the caller copies it
1052 * to the local variable area and delivers the address of that area.
1056 * +-------------------------------+----------------------+
1057 * |Return Value Type |Return Value Interface|
1058 * +-------------------------------+----------------------+
1060 * |[signed|unsigned] char |GR8 |
1061 * |[signed|unsigned] short int |GR8 |
1062 * |[signed|unsigned] int |GR8 |
1063 * |[signed|unsigned] long int |GR8 |
1065 * |[signed|unsigned] long long int|GR8 & GR9 |
1067 * |double |GR8 & GR9 |
1068 * |long double |GR8 & GR9 |
1069 * |struct/union |(*1) |
1070 * +-------------------------------+----------------------+
1072 * When a struct/union is used as the return value, the caller function stores
1073 * the start address of the return value storage area into GR3 and then passes
1074 * it to the callee function. The callee function interprets GR3 as the start
1075 * address of the return value storage area. When this address needs to be
1076 * saved in memory, the callee function secures the hidden parameter save area
1077 * and saves the address in that area.
1081 frv_stack_info (void)
1083 static frv_stack_t info, zero_info;
1084 frv_stack_t *info_ptr = &info;
1085 tree fndecl = current_function_decl;
1093 /* If we've already calculated the values and reload is complete,
1095 if (frv_stack_cache)
1096 return frv_stack_cache;
1098 /* Zero all fields. */
1101 /* Set up the register range information. */
1102 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1103 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1104 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1105 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1107 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1108 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1109 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1110 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1112 info_ptr->regs[STACK_REGS_LR].name = "lr";
1113 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1114 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1115 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1117 info_ptr->regs[STACK_REGS_CC].name = "cc";
1118 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1119 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1120 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1122 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1123 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1124 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1126 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1127 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1128 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1129 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1130 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1132 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1133 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1134 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1135 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1137 info_ptr->regs[STACK_REGS_FP].name = "fp";
1138 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1139 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1140 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1142 /* Determine if this is a stdarg function. If so, allocate space to store
1149 /* Find the last argument, and see if it is __builtin_va_alist. */
1150 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1152 next_arg = TREE_CHAIN (cur_arg);
1153 if (next_arg == (tree)0)
1155 if (DECL_NAME (cur_arg)
1156 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1164 /* Iterate over all of the register ranges. */
1165 for (range = 0; range < STACK_REGS_MAX; range++)
1167 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1168 int first = reg_ptr->first;
1169 int last = reg_ptr->last;
1171 int size_2words = 0;
1174 /* Calculate which registers need to be saved & save area size. */
1178 for (regno = first; regno <= last; regno++)
1180 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1181 || (crtl->calls_eh_return
1182 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1183 || (!TARGET_FDPIC && flag_pic
1184 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1186 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1187 size_1word += UNITS_PER_WORD;
1192 /* Calculate whether we need to create a frame after everything else
1193 has been processed. */
1198 if (df_regs_ever_live_p (LR_REGNO)
1200 /* This is set for __builtin_return_address, etc. */
1201 || cfun->machine->frame_needed
1202 || (TARGET_LINKED_FP && frame_pointer_needed)
1203 || (!TARGET_FDPIC && flag_pic
1204 && crtl->uses_pic_offset_table))
1206 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1207 size_1word += UNITS_PER_WORD;
1211 case STACK_REGS_STDARG:
1214 /* If this is a stdarg function with a non varardic
1215 argument split between registers and the stack,
1216 adjust the saved registers downward. */
1217 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1220 for (regno = first; regno <= last; regno++)
1222 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1223 size_1word += UNITS_PER_WORD;
1226 info_ptr->stdarg_size = size_1word;
1230 case STACK_REGS_STRUCT:
1231 if (cfun->returns_struct)
1233 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1234 size_1word += UNITS_PER_WORD;
1242 /* If this is a field, it only takes one word. */
1243 if (reg_ptr->field_p)
1244 size_1word = UNITS_PER_WORD;
1246 /* Determine which register pairs can be saved together. */
1247 else if (reg_ptr->dword_p && TARGET_DWORD)
1249 for (regno = first; regno < last; regno += 2)
1251 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1253 size_2words += 2 * UNITS_PER_WORD;
1254 size_1word -= 2 * UNITS_PER_WORD;
1255 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1256 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1261 reg_ptr->size_1word = size_1word;
1262 reg_ptr->size_2words = size_2words;
1264 if (! reg_ptr->special_p)
1266 info_ptr->regs_size_1word += size_1word;
1267 info_ptr->regs_size_2words += size_2words;
1272 /* Set up the sizes of each each field in the frame body, making the sizes
1273 of each be divisible by the size of a dword if dword operations might
1274 be used, or the size of a word otherwise. */
1275 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1277 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1278 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1279 + info_ptr->regs_size_1word,
1281 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1283 info_ptr->pretend_size = crtl->args.pretend_args_size;
1285 /* Work out the size of the frame, excluding the header. Both the frame
1286 body and register parameter area will be dword-aligned. */
1287 info_ptr->total_size
1288 = (ADDR_ALIGN (info_ptr->parameter_size
1289 + info_ptr->regs_size
1290 + info_ptr->vars_size,
1292 + ADDR_ALIGN (info_ptr->pretend_size
1293 + info_ptr->stdarg_size,
1294 2 * UNITS_PER_WORD));
1296 /* See if we need to create a frame at all, if so add header area. */
1297 if (info_ptr->total_size > 0
1298 || frame_pointer_needed
1299 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1300 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1302 offset = info_ptr->parameter_size;
1303 info_ptr->header_size = 4 * UNITS_PER_WORD;
1304 info_ptr->total_size += 4 * UNITS_PER_WORD;
1306 /* Calculate the offsets to save normal register pairs. */
1307 for (range = 0; range < STACK_REGS_MAX; range++)
1309 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1310 if (! reg_ptr->special_p)
1312 int first = reg_ptr->first;
1313 int last = reg_ptr->last;
1316 for (regno = first; regno <= last; regno++)
1317 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1318 && regno != FRAME_POINTER_REGNUM
1319 && (regno < FIRST_ARG_REGNUM
1320 || regno > LAST_ARG_REGNUM))
1322 info_ptr->reg_offset[regno] = offset;
1323 offset += 2 * UNITS_PER_WORD;
1328 /* Calculate the offsets to save normal single registers. */
1329 for (range = 0; range < STACK_REGS_MAX; range++)
1331 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1332 if (! reg_ptr->special_p)
1334 int first = reg_ptr->first;
1335 int last = reg_ptr->last;
1338 for (regno = first; regno <= last; regno++)
1339 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1340 && regno != FRAME_POINTER_REGNUM
1341 && (regno < FIRST_ARG_REGNUM
1342 || regno > LAST_ARG_REGNUM))
1344 info_ptr->reg_offset[regno] = offset;
1345 offset += UNITS_PER_WORD;
1350 /* Calculate the offset to save the local variables at. */
1351 offset = ADDR_ALIGN (offset, alignment);
1352 if (info_ptr->vars_size)
1354 info_ptr->vars_offset = offset;
1355 offset += info_ptr->vars_size;
1358 /* Align header to a dword-boundary. */
1359 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1361 /* Calculate the offsets in the fixed frame. */
1362 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1363 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1364 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1366 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1367 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1368 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1370 if (cfun->returns_struct)
1372 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1373 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1374 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1377 /* Calculate the offsets to store the arguments passed in registers
1378 for stdarg functions. The register pairs are first and the single
1379 register if any is last. The register save area starts on a
1381 if (info_ptr->stdarg_size)
1383 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1384 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1387 /* Skip the header. */
1388 offset += 4 * UNITS_PER_WORD;
1389 for (regno = first; regno <= last; regno++)
1391 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1393 info_ptr->reg_offset[regno] = offset;
1394 offset += 2 * UNITS_PER_WORD;
1396 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1398 info_ptr->reg_offset[regno] = offset;
1399 offset += UNITS_PER_WORD;
1405 if (reload_completed)
1406 frv_stack_cache = info_ptr;
1412 /* Print the information about the frv stack offsets, etc. when debugging. */
1415 frv_debug_stack (frv_stack_t *info)
1420 info = frv_stack_info ();
1422 fprintf (stderr, "\nStack information for function %s:\n",
1423 ((current_function_decl && DECL_NAME (current_function_decl))
1424 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1427 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1428 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1429 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1430 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1431 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1433 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1434 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1435 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1436 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1438 for (range = 0; range < STACK_REGS_MAX; range++)
1440 frv_stack_regs_t *regs = &(info->regs[range]);
1441 if ((regs->size_1word + regs->size_2words) > 0)
1443 int first = regs->first;
1444 int last = regs->last;
1447 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1448 regs->name, regs->size_1word + regs->size_2words,
1449 regs->size_1word, regs->size_2words);
1451 for (regno = first; regno <= last; regno++)
1453 if (info->save_p[regno] == REG_SAVE_1WORD)
1454 fprintf (stderr, " %s (%d)", reg_names[regno],
1455 info->reg_offset[regno]);
1457 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1458 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1459 reg_names[regno+1], info->reg_offset[regno]);
1462 fputc ('\n', stderr);
1472 /* Used during final to control the packing of insns. The value is
1473 1 if the current instruction should be packed with the next one,
1474 0 if it shouldn't or -1 if packing is disabled altogether. */
1476 static int frv_insn_packing_flag;
1478 /* True if the current function contains a far jump. */
1481 frv_function_contains_far_jump (void)
1483 rtx insn = get_insns ();
1485 && !(GET_CODE (insn) == JUMP_INSN
1486 /* Ignore tablejump patterns. */
1487 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1488 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1489 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1490 insn = NEXT_INSN (insn);
1491 return (insn != NULL);
1494 /* For the FRV, this function makes sure that a function with far jumps
1495 will return correctly. It also does the VLIW packing. */
1498 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1500 /* If no frame was created, check whether the function uses a call
1501 instruction to implement a far jump. If so, save the link in gr3 and
1502 replace all returns to LR with returns to GR3. GR3 is used because it
1503 is call-clobbered, because is not available to the register allocator,
1504 and because all functions that take a hidden argument pointer will have
1506 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1510 /* Just to check that the above comment is true. */
1511 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1513 /* Generate the instruction that saves the link register. */
1514 fprintf (file, "\tmovsg lr,gr3\n");
1516 /* Replace the LR with GR3 in *return_internal patterns. The insn
1517 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1518 simply emit a different assembly directive because bralr and jmpl
1519 execute in different units. */
1520 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1521 if (GET_CODE (insn) == JUMP_INSN)
1523 rtx pattern = PATTERN (insn);
1524 if (GET_CODE (pattern) == PARALLEL
1525 && XVECLEN (pattern, 0) >= 2
1526 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1527 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1529 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1530 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1531 SET_REGNO (address, GPR_FIRST + 3);
1538 /* Allow the garbage collector to free the nops created by frv_reorg. */
1539 memset (frv_nops, 0, sizeof (frv_nops));
1543 /* Return the next available temporary register in a given class. */
1546 frv_alloc_temp_reg (
1547 frv_tmp_reg_t *info, /* which registers are available */
1548 enum reg_class rclass, /* register class desired */
1549 enum machine_mode mode, /* mode to allocate register with */
1550 int mark_as_used, /* register not available after allocation */
1551 int no_abort) /* return NULL instead of aborting */
1553 int regno = info->next_reg[ (int)rclass ];
1554 int orig_regno = regno;
1555 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1560 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1561 && TEST_HARD_REG_BIT (info->regs, regno))
1564 if (++regno >= FIRST_PSEUDO_REGISTER)
1566 if (regno == orig_regno)
1568 gcc_assert (no_abort);
1573 nr = HARD_REGNO_NREGS (regno, mode);
1574 info->next_reg[ (int)rclass ] = regno + nr;
1577 for (i = 0; i < nr; i++)
1578 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1580 return gen_rtx_REG (mode, regno);
1584 /* Return an rtx with the value OFFSET, which will either be a register or a
1585 signed 12-bit integer. It can be used as the second operand in an "add"
1586 instruction, or as the index in a load or store.
1588 The function returns a constant rtx if OFFSET is small enough, otherwise
1589 it loads the constant into register OFFSET_REGNO and returns that. */
1591 frv_frame_offset_rtx (int offset)
1593 rtx offset_rtx = GEN_INT (offset);
1594 if (IN_RANGE_P (offset, -2048, 2047))
1598 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1599 if (IN_RANGE_P (offset, -32768, 32767))
1600 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1603 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1604 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1610 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1611 prologue and epilogue uses such expressions to access the stack. */
1613 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1615 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1617 frv_frame_offset_rtx (offset)));
1620 /* Generate a frame-related expression:
1622 (set REG (mem (plus (sp) (const_int OFFSET)))).
1624 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1625 instructions. Marking the expressions as frame-related is superfluous if
1626 the note contains just a single set. But if the note contains a PARALLEL
1627 or SEQUENCE that has several sets, each set must be individually marked
1628 as frame-related. */
1630 frv_dwarf_store (rtx reg, int offset)
1632 rtx set = gen_rtx_SET (VOIDmode,
1633 gen_rtx_MEM (GET_MODE (reg),
1634 plus_constant (stack_pointer_rtx,
1637 RTX_FRAME_RELATED_P (set) = 1;
1641 /* Emit a frame-related instruction whose pattern is PATTERN. The
1642 instruction is the last in a sequence that cumulatively performs the
1643 operation described by DWARF_PATTERN. The instruction is marked as
1644 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1647 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1649 rtx insn = emit_insn (pattern);
1650 RTX_FRAME_RELATED_P (insn) = 1;
1651 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1656 /* Emit instructions that transfer REG to or from the memory location (sp +
1657 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1658 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1659 function to store registers and only the epilogue uses it to load them.
1661 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1662 The generated instruction will use BASE as its base register. BASE may
1663 simply be the stack pointer, but if several accesses are being made to a
1664 region far away from the stack pointer, it may be more efficient to set
1665 up a temporary instead.
1667 Store instructions will be frame-related and will be annotated with the
1668 overall effect of the store. Load instructions will be followed by a
1669 (use) to prevent later optimizations from zapping them.
1671 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1672 as a temporary in such cases. */
1674 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1676 enum machine_mode mode = GET_MODE (reg);
1677 rtx mem = frv_frame_mem (mode,
1679 stack_offset - accessor->base_offset);
1681 if (accessor->op == FRV_LOAD)
1683 if (SPR_P (REGNO (reg)))
1685 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1686 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1687 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1691 /* We cannot use reg+reg addressing for DImode access. */
1693 && GET_CODE (XEXP (mem, 0)) == PLUS
1694 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1695 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1697 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1698 rtx insn = emit_move_insn (temp,
1699 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1700 XEXP (XEXP (mem, 0), 1)));
1701 mem = gen_rtx_MEM (DImode, temp);
1703 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1709 if (SPR_P (REGNO (reg)))
1711 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1712 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1713 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1714 frv_dwarf_store (reg, stack_offset));
1716 else if (mode == DImode)
1718 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1719 with a separate save for each register. */
1720 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1721 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1722 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1723 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1725 /* Also we cannot use reg+reg addressing. */
1726 if (GET_CODE (XEXP (mem, 0)) == PLUS
1727 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1728 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1730 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1731 rtx insn = emit_move_insn (temp,
1732 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1733 XEXP (XEXP (mem, 0), 1)));
1734 mem = gen_rtx_MEM (DImode, temp);
1737 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1738 gen_rtx_PARALLEL (VOIDmode,
1739 gen_rtvec (2, set1, set2)));
1742 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1743 frv_dwarf_store (reg, stack_offset));
1747 /* A function that uses frv_frame_access to transfer a group of registers to
1748 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1749 is the stack information generated by frv_stack_info, and REG_SET is the
1750 number of the register set to transfer. */
1752 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1756 frv_stack_regs_t *regs_info;
1759 regs_info = &info->regs[reg_set];
1760 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1761 if (info->save_p[regno])
1762 frv_frame_access (accessor,
1763 info->save_p[regno] == REG_SAVE_2WORDS
1764 ? gen_rtx_REG (DImode, regno)
1765 : gen_rtx_REG (SImode, regno),
1766 info->reg_offset[regno]);
1769 /* Save or restore callee-saved registers that are kept outside the frame
1770 header. The function saves the registers if OP is FRV_STORE and restores
1771 them if OP is FRV_LOAD. INFO is the stack information generated by
1774 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1776 frv_frame_accessor_t accessor;
1779 accessor.base = stack_pointer_rtx;
1780 accessor.base_offset = 0;
1781 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1782 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1783 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1787 /* Called after register allocation to add any instructions needed for the
1788 prologue. Using a prologue insn is favored compared to putting all of the
1789 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1790 it allows the scheduler to intermix instructions with the saves of
1791 the caller saved registers. In some cases, it might be necessary
1792 to emit a barrier instruction as the last insn to prevent such
1795 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1796 so that the debug info generation code can handle them properly. */
1798 frv_expand_prologue (void)
1800 frv_stack_t *info = frv_stack_info ();
1801 rtx sp = stack_pointer_rtx;
1802 rtx fp = frame_pointer_rtx;
1803 frv_frame_accessor_t accessor;
1805 if (TARGET_DEBUG_STACK)
1806 frv_debug_stack (info);
1808 if (info->total_size == 0)
1811 /* We're interested in three areas of the frame here:
1813 A: the register save area
1815 C: the header after B
1817 If the frame pointer isn't used, we'll have to set up A, B and C
1818 using the stack pointer. If the frame pointer is used, we'll access
1822 B: set up using sp or a temporary (see below)
1825 We set up B using the stack pointer if the frame is small enough.
1826 Otherwise, it's more efficient to copy the old stack pointer into a
1827 temporary and use that.
1829 Note that it's important to make sure the prologue and epilogue use the
1830 same registers to access A and C, since doing otherwise will confuse
1831 the aliasing code. */
1833 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1834 isn't used, the same method will serve for C. */
1835 accessor.op = FRV_STORE;
1836 if (frame_pointer_needed && info->total_size > 2048)
1840 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1841 accessor.base_offset = info->total_size;
1842 insn = emit_insn (gen_movsi (accessor.base, sp));
1846 accessor.base = stack_pointer_rtx;
1847 accessor.base_offset = 0;
1850 /* Allocate the stack space. */
1852 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1853 rtx dwarf_offset = GEN_INT (-info->total_size);
1855 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1858 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1861 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1862 and point the new one to that location. */
1863 if (frame_pointer_needed)
1865 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1867 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1868 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1870 rtx asm_src = plus_constant (accessor.base,
1871 fp_offset - accessor.base_offset);
1872 rtx dwarf_src = plus_constant (sp, fp_offset);
1874 /* Store the old frame pointer at (sp + FP_OFFSET). */
1875 frv_frame_access (&accessor, fp, fp_offset);
1877 /* Set up the new frame pointer. */
1878 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1879 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1881 /* Access region C from the frame pointer. */
1883 accessor.base_offset = fp_offset;
1886 /* Set up region C. */
1887 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1888 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1889 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1891 /* Set up region A. */
1892 frv_frame_access_standard_regs (FRV_STORE, info);
1894 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1895 scheduler from moving loads before the stores saving the registers. */
1896 if (info->stdarg_size > 0)
1897 emit_insn (gen_blockage ());
1899 /* Set up pic register/small data register for this function. */
1900 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1901 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1902 gen_rtx_REG (Pmode, LR_REGNO),
1903 gen_rtx_REG (SImode, OFFSET_REGNO)));
1907 /* Under frv, all of the work is done via frv_expand_epilogue, but
1908 this function provides a convenient place to do cleanup. */
1911 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1912 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1914 frv_stack_cache = (frv_stack_t *)0;
1916 /* Zap last used registers for conditional execution. */
1917 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1919 /* Release the bitmap of created insns. */
1920 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1924 /* Called after register allocation to add any instructions needed for the
1925 epilogue. Using an epilogue insn is favored compared to putting all of the
1926 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1927 it allows the scheduler to intermix instructions with the saves of
1928 the caller saved registers. In some cases, it might be necessary
1929 to emit a barrier instruction as the last insn to prevent such
1933 frv_expand_epilogue (bool emit_return)
1935 frv_stack_t *info = frv_stack_info ();
1936 rtx fp = frame_pointer_rtx;
1937 rtx sp = stack_pointer_rtx;
1941 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1943 /* Restore the stack pointer to its original value if alloca or the like
1945 if (! current_function_sp_is_unchanging)
1946 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1948 /* Restore the callee-saved registers that were used in this function. */
1949 frv_frame_access_standard_regs (FRV_LOAD, info);
1951 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1952 no return instruction should be emitted. */
1953 if (info->save_p[LR_REGNO])
1958 /* Use the same method to access the link register's slot as we did in
1959 the prologue. In other words, use the frame pointer if available,
1960 otherwise use the stack pointer.
1962 LR_OFFSET is the offset of the link register's slot from the start
1963 of the frame and MEM is a memory rtx for it. */
1964 lr_offset = info->reg_offset[LR_REGNO];
1965 if (frame_pointer_needed)
1966 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1968 mem = frv_frame_mem (Pmode, sp, lr_offset);
1970 /* Load the old link register into a GPR. */
1971 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1972 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1975 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1977 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1978 the load is preserved. */
1979 if (frame_pointer_needed)
1981 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1985 /* Deallocate the stack frame. */
1986 if (info->total_size != 0)
1988 rtx offset = frv_frame_offset_rtx (info->total_size);
1989 emit_insn (gen_stack_adjust (sp, sp, offset));
1992 /* If this function uses eh_return, add the final stack adjustment now. */
1993 if (crtl->calls_eh_return)
1994 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1997 emit_jump_insn (gen_epilogue_return (return_addr));
2000 rtx lr = return_addr;
2002 if (REGNO (return_addr) != LR_REGNO)
2004 lr = gen_rtx_REG (Pmode, LR_REGNO);
2005 emit_move_insn (lr, return_addr);
2013 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2016 frv_asm_output_mi_thunk (FILE *file,
2017 tree thunk_fndecl ATTRIBUTE_UNUSED,
2018 HOST_WIDE_INT delta,
2019 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2022 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2023 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2024 const char *name_jmp = reg_names[JUMP_REGNO];
2025 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2027 /* Do the add using an addi if possible. */
2028 if (IN_RANGE_P (delta, -2048, 2047))
2029 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2032 const char *const name_add = reg_names[TEMP_REGNO];
2033 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2034 parallel, delta, name_add);
2035 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2037 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2042 const char *name_pic = reg_names[FDPIC_REGNO];
2043 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2047 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2048 assemble_name (file, name_func);
2049 fprintf (file, "),%s\n", name_jmp);
2051 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2052 assemble_name (file, name_func);
2053 fprintf (file, "),%s\n", name_jmp);
2055 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2059 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2060 assemble_name (file, name_func);
2061 fprintf (file, "\t)), %s\n", name_jmp);
2066 fprintf (file, "\tsethi%s #hi(", parallel);
2067 assemble_name (file, name_func);
2068 fprintf (file, "),%s\n", name_jmp);
2070 fprintf (file, "\tsetlo #lo(");
2071 assemble_name (file, name_func);
2072 fprintf (file, "),%s\n", name_jmp);
2076 /* Use JUMP_REGNO as a temporary PIC register. */
2077 const char *name_lr = reg_names[LR_REGNO];
2078 const char *name_gppic = name_jmp;
2079 const char *name_tmp = reg_names[TEMP_REGNO];
2081 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2082 fprintf (file, "\tcall 1f\n");
2083 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2084 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2085 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2086 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2087 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2089 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2090 assemble_name (file, name_func);
2091 fprintf (file, "),%s\n", name_tmp);
2093 fprintf (file, "\tsetlo #gprello(");
2094 assemble_name (file, name_func);
2095 fprintf (file, "),%s\n", name_tmp);
2097 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2100 /* Jump to the function address. */
2101 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2105 /* A C expression which is nonzero if a function must have and use a frame
2106 pointer. This expression is evaluated in the reload pass. If its value is
2107 nonzero the function will have a frame pointer.
2109 The expression can in principle examine the current function and decide
2110 according to the facts, but on most machines the constant 0 or the constant
2111 1 suffices. Use 0 when the machine allows code to be generated with no
2112 frame pointer, and doing so saves some time or space. Use 1 when there is
2113 no possible advantage to avoiding a frame pointer.
2115 In certain cases, the compiler does not know how to produce valid code
2116 without a frame pointer. The compiler recognizes those cases and
2117 automatically gives the function a frame pointer regardless of what
2118 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2120 In a function that does not require a frame pointer, the frame pointer
2121 register can be allocated for ordinary usage, unless you mark it as a fixed
2122 register. See `FIXED_REGISTERS' for more information. */
2124 /* On frv, create a frame whenever we need to create stack. */
2127 frv_frame_pointer_required (void)
2129 /* If we forgoing the usual linkage requirements, we only need
2130 a frame pointer if the stack pointer might change. */
2131 if (!TARGET_LINKED_FP)
2132 return !current_function_sp_is_unchanging;
2134 if (! current_function_is_leaf)
2137 if (get_frame_size () != 0)
2143 if (!current_function_sp_is_unchanging)
2146 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2152 if (cfun->machine->frame_needed)
2159 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2160 initial difference between the specified pair of registers. This macro must
2161 be defined if `ELIMINABLE_REGS' is defined. */
2163 /* See frv_stack_info for more details on the frv stack frame. */
2166 frv_initial_elimination_offset (int from, int to)
2168 frv_stack_t *info = frv_stack_info ();
2171 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2172 ret = info->total_size - info->pretend_size;
2174 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2175 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2177 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2178 ret = (info->total_size
2179 - info->reg_offset[FRAME_POINTER_REGNUM]
2180 - info->pretend_size);
2185 if (TARGET_DEBUG_STACK)
2186 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2187 reg_names [from], reg_names[to], ret);
2193 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2196 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2197 enum machine_mode mode,
2198 tree type ATTRIBUTE_UNUSED,
2202 if (TARGET_DEBUG_ARG)
2204 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2205 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2209 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2212 frv_expand_builtin_saveregs (void)
2214 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2216 if (TARGET_DEBUG_ARG)
2217 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2220 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2224 /* Expand __builtin_va_start to do the va_start macro. */
2227 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2230 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2232 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2233 GEN_INT (UNITS_PER_WORD * num));
2235 if (TARGET_DEBUG_ARG)
2237 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2238 crtl->args.info, num);
2240 debug_rtx (nextarg);
2243 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2244 fold_convert (TREE_TYPE (valist),
2245 make_tree (sizetype, nextarg)));
2246 TREE_SIDE_EFFECTS (t) = 1;
2248 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2252 /* Expand a block move operation, and return 1 if successful. Return 0
2253 if we should let the compiler generate normal code.
2255 operands[0] is the destination
2256 operands[1] is the source
2257 operands[2] is the length
2258 operands[3] is the alignment */
2260 /* Maximum number of loads to do before doing the stores */
2261 #ifndef MAX_MOVE_REG
2262 #define MAX_MOVE_REG 4
2265 /* Maximum number of total loads to do. */
2266 #ifndef TOTAL_MOVE_REG
2267 #define TOTAL_MOVE_REG 8
2271 frv_expand_block_move (rtx operands[])
2273 rtx orig_dest = operands[0];
2274 rtx orig_src = operands[1];
2275 rtx bytes_rtx = operands[2];
2276 rtx align_rtx = operands[3];
2277 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2290 rtx stores[MAX_MOVE_REG];
2292 enum machine_mode mode;
2294 /* If this is not a fixed size move, just call memcpy. */
2298 /* This should be a fixed size alignment. */
2299 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2301 align = INTVAL (align_rtx);
2303 /* Anything to move? */
2304 bytes = INTVAL (bytes_rtx);
2308 /* Don't support real large moves. */
2309 if (bytes > TOTAL_MOVE_REG*align)
2312 /* Move the address into scratch registers. */
2313 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2314 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2316 num_reg = offset = 0;
2317 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2319 /* Calculate the correct offset for src/dest. */
2323 dest_addr = dest_reg;
2327 src_addr = plus_constant (src_reg, offset);
2328 dest_addr = plus_constant (dest_reg, offset);
2331 /* Generate the appropriate load and store, saving the stores
2333 if (bytes >= 4 && align >= 4)
2335 else if (bytes >= 2 && align >= 2)
2340 move_bytes = GET_MODE_SIZE (mode);
2341 tmp_reg = gen_reg_rtx (mode);
2342 src_mem = change_address (orig_src, mode, src_addr);
2343 dest_mem = change_address (orig_dest, mode, dest_addr);
2344 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2345 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2347 if (num_reg >= MAX_MOVE_REG)
2349 for (i = 0; i < num_reg; i++)
2350 emit_insn (stores[i]);
2355 for (i = 0; i < num_reg; i++)
2356 emit_insn (stores[i]);
2362 /* Expand a block clear operation, and return 1 if successful. Return 0
2363 if we should let the compiler generate normal code.
2365 operands[0] is the destination
2366 operands[1] is the length
2367 operands[3] is the alignment */
2370 frv_expand_block_clear (rtx operands[])
2372 rtx orig_dest = operands[0];
2373 rtx bytes_rtx = operands[1];
2374 rtx align_rtx = operands[3];
2375 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2384 enum machine_mode mode;
2386 /* If this is not a fixed size move, just call memcpy. */
2390 /* This should be a fixed size alignment. */
2391 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2393 align = INTVAL (align_rtx);
2395 /* Anything to move? */
2396 bytes = INTVAL (bytes_rtx);
2400 /* Don't support real large clears. */
2401 if (bytes > TOTAL_MOVE_REG*align)
2404 /* Move the address into a scratch register. */
2405 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2407 num_reg = offset = 0;
2408 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2410 /* Calculate the correct offset for src/dest. */
2411 dest_addr = ((offset == 0)
2413 : plus_constant (dest_reg, offset));
2415 /* Generate the appropriate store of gr0. */
2416 if (bytes >= 4 && align >= 4)
2418 else if (bytes >= 2 && align >= 2)
2423 clear_bytes = GET_MODE_SIZE (mode);
2424 dest_mem = change_address (orig_dest, mode, dest_addr);
2425 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2432 /* The following variable is used to output modifiers of assembler
2433 code of the current output insn. */
2435 static rtx *frv_insn_operands;
2437 /* The following function is used to add assembler insn code suffix .p
2438 if it is necessary. */
2441 frv_asm_output_opcode (FILE *f, const char *ptr)
2445 if (frv_insn_packing_flag <= 0)
2448 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2451 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2452 || (*ptr >= 'A' && *ptr <= 'Z')))
2454 int letter = *ptr++;
2457 frv_print_operand (f, frv_insn_operands [c], letter);
2458 while ((c = *ptr) >= '0' && c <= '9')
2470 /* Set up the packing bit for the current output insn. Note that this
2471 function is not called for asm insns. */
2474 frv_final_prescan_insn (rtx insn, rtx *opvec,
2475 int noperands ATTRIBUTE_UNUSED)
2479 if (frv_insn_packing_flag >= 0)
2481 frv_insn_operands = opvec;
2482 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2484 else if (recog_memoized (insn) >= 0
2485 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2486 /* Packing optimizations have been disabled, but INSN can only
2487 be issued in M1. Insert an mnop in M0. */
2488 fprintf (asm_out_file, "\tmnop.p\n");
2494 /* A C expression whose value is RTL representing the address in a stack frame
2495 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2496 an RTL expression for the address of the stack frame itself.
2498 If you don't define this macro, the default is to return the value of
2499 FRAMEADDR--that is, the stack frame address is also the address of the stack
2500 word that points to the previous frame. */
2502 /* The default is correct, but we need to make sure the frame gets created. */
2504 frv_dynamic_chain_address (rtx frame)
2506 cfun->machine->frame_needed = 1;
2511 /* A C expression whose value is RTL representing the value of the return
2512 address for the frame COUNT steps up from the current frame, after the
2513 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2514 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2517 The value of the expression must always be the correct address when COUNT is
2518 zero, but may be `NULL_RTX' if there is not way to determine the return
2519 address of other frames. */
2522 frv_return_addr_rtx (int count, rtx frame)
2526 cfun->machine->frame_needed = 1;
2527 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2530 /* Given a memory reference MEMREF, interpret the referenced memory as
2531 an array of MODE values, and return a reference to the element
2532 specified by INDEX. Assume that any pre-modification implicit in
2533 MEMREF has already happened.
2535 MEMREF must be a legitimate operand for modes larger than SImode.
2536 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2537 this function cannot handle. */
2539 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2541 rtx base = XEXP (memref, 0);
2542 if (GET_CODE (base) == PRE_MODIFY)
2543 base = XEXP (base, 0);
2544 return change_address (memref, mode,
2545 plus_constant (base, index * GET_MODE_SIZE (mode)));
2549 /* Print a memory address as an operand to reference that memory location. */
2551 frv_print_operand_address (FILE * stream, rtx x)
2553 if (GET_CODE (x) == MEM)
2556 switch (GET_CODE (x))
2559 fputs (reg_names [ REGNO (x)], stream);
2563 fprintf (stream, "%ld", (long) INTVAL (x));
2567 assemble_name (stream, XSTR (x, 0));
2572 output_addr_const (stream, x);
2576 /* Poorly constructed asm statements can trigger this alternative.
2577 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2578 frv_print_operand_memory_reference (stream, x, 0);
2585 fatal_insn ("bad insn to frv_print_operand_address:", x);
2590 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2592 int regno = true_regnum (x);
2594 fputs (reg_names[regno], stream);
2596 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2599 /* Print a memory reference suitable for the ld/st instructions. */
2602 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2604 struct frv_unspec unspec;
2608 switch (GET_CODE (x))
2615 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2617 x1 = XEXP (XEXP (x, 1), 1);
2627 if (GET_CODE (x0) == CONST_INT)
2635 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2644 else if (GET_CODE (x1) != CONST_INT)
2645 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2648 fputs ("@(", stream);
2650 fputs (reg_names[GPR_R0], stream);
2651 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2652 frv_print_operand_memory_reference_reg (stream, x0);
2654 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2656 fputs (",", stream);
2658 fputs (reg_names [GPR_R0], stream);
2662 switch (GET_CODE (x1))
2666 frv_print_operand_memory_reference_reg (stream, x1);
2670 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2674 if (!frv_const_unspec_p (x1, &unspec))
2675 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2676 frv_output_const_unspec (stream, &unspec);
2680 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2684 fputs (")", stream);
2688 /* Return 2 for likely branches and 0 for non-likely branches */
2690 #define FRV_JUMP_LIKELY 2
2691 #define FRV_JUMP_NOT_LIKELY 0
2694 frv_print_operand_jump_hint (rtx insn)
2699 HOST_WIDE_INT prob = -1;
2700 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2702 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2704 /* Assume any non-conditional jump is likely. */
2705 if (! any_condjump_p (insn))
2706 ret = FRV_JUMP_LIKELY;
2710 labelref = condjump_label (insn);
2713 rtx label = XEXP (labelref, 0);
2714 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2719 note = find_reg_note (insn, REG_BR_PROB, 0);
2721 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2725 prob = INTVAL (XEXP (note, 0));
2726 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2728 : FRV_JUMP_NOT_LIKELY);
2740 case UNKNOWN: direction = "unknown jump direction"; break;
2741 case BACKWARD: direction = "jump backward"; break;
2742 case FORWARD: direction = "jump forward"; break;
2746 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2747 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2748 (long)INSN_UID (insn), direction, (long)prob,
2749 (long)REG_BR_PROB_BASE, ret);
2757 /* Return the comparison operator to use for CODE given that the ICC
2761 comparison_string (enum rtx_code code, rtx op0)
2763 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2766 default: output_operand_lossage ("bad condition code");
2767 case EQ: return "eq";
2768 case NE: return "ne";
2769 case LT: return is_nz_p ? "n" : "lt";
2770 case LE: return "le";
2771 case GT: return "gt";
2772 case GE: return is_nz_p ? "p" : "ge";
2773 case LTU: return is_nz_p ? "no" : "c";
2774 case LEU: return is_nz_p ? "eq" : "ls";
2775 case GTU: return is_nz_p ? "ne" : "hi";
2776 case GEU: return is_nz_p ? "ra" : "nc";
2780 /* Print an operand to an assembler instruction.
2782 `%' followed by a letter and a digit says to output an operand in an
2783 alternate fashion. Four letters have standard, built-in meanings described
2784 below. The machine description macro `PRINT_OPERAND' can define additional
2785 letters with nonstandard meanings.
2787 `%cDIGIT' can be used to substitute an operand that is a constant value
2788 without the syntax that normally indicates an immediate operand.
2790 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2793 `%aDIGIT' can be used to substitute an operand as if it were a memory
2794 reference, with the actual operand treated as the address. This may be
2795 useful when outputting a "load address" instruction, because often the
2796 assembler syntax for such an instruction requires you to write the operand
2797 as if it were a memory reference.
2799 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2801 `%=' outputs a number which is unique to each instruction in the entire
2802 compilation. This is useful for making local labels to be referred to more
2803 than once in a single template that generates multiple assembler
2806 `%' followed by a punctuation character specifies a substitution that does
2807 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2808 assembler code. Other nonstandard cases can be defined in the
2809 `PRINT_OPERAND' macro. You must also define which punctuation characters
2810 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2813 frv_print_operand (FILE * file, rtx x, int code)
2815 struct frv_unspec unspec;
2816 HOST_WIDE_INT value;
2819 if (code != 0 && !ISALPHA (code))
2822 else if (GET_CODE (x) == CONST_INT)
2825 else if (GET_CODE (x) == CONST_DOUBLE)
2827 if (GET_MODE (x) == SFmode)
2832 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2833 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2837 else if (GET_MODE (x) == VOIDmode)
2838 value = CONST_DOUBLE_LOW (x);
2841 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2852 fputs (reg_names[GPR_R0], file);
2856 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2860 /* Output small data area base register (gr16). */
2861 fputs (reg_names[SDA_BASE_REG], file);
2865 /* Output pic register (gr17). */
2866 fputs (reg_names[PIC_REGNO], file);
2870 /* Output the temporary integer CCR register. */
2871 fputs (reg_names[ICR_TEMP], file);
2875 /* Output the temporary integer CC register. */
2876 fputs (reg_names[ICC_TEMP], file);
2879 /* case 'a': print an address. */
2882 /* Print appropriate test for integer branch false operation. */
2883 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2884 XEXP (x, 0)), file);
2888 /* Print appropriate test for integer branch true operation. */
2889 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2893 /* Print 1 for a NE and 0 for an EQ to give the final argument
2894 for a conditional instruction. */
2895 if (GET_CODE (x) == NE)
2898 else if (GET_CODE (x) == EQ)
2902 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2906 /* Print appropriate test for floating point branch false operation. */
2907 switch (GET_CODE (x))
2910 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2912 case EQ: fputs ("ne", file); break;
2913 case NE: fputs ("eq", file); break;
2914 case LT: fputs ("uge", file); break;
2915 case LE: fputs ("ug", file); break;
2916 case GT: fputs ("ule", file); break;
2917 case GE: fputs ("ul", file); break;
2922 /* Print appropriate test for floating point branch true operation. */
2923 switch (GET_CODE (x))
2926 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2928 case EQ: fputs ("eq", file); break;
2929 case NE: fputs ("ne", file); break;
2930 case LT: fputs ("lt", file); break;
2931 case LE: fputs ("le", file); break;
2932 case GT: fputs ("gt", file); break;
2933 case GE: fputs ("ge", file); break;
2938 /* Print appropriate GOT function. */
2939 if (GET_CODE (x) != CONST_INT)
2940 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2941 fputs (unspec_got_name (INTVAL (x)), file);
2945 /* Print 'i' if the operand is a constant, or is a memory reference that
2947 if (GET_CODE (x) == MEM)
2948 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2949 ? XEXP (XEXP (x, 0), 1)
2951 else if (GET_CODE (x) == PLUS)
2954 switch (GET_CODE (x))
2968 /* For jump instructions, print 'i' if the operand is a constant or
2969 is an expression that adds a constant. */
2970 if (GET_CODE (x) == CONST_INT)
2975 if (GET_CODE (x) == CONST_INT
2976 || (GET_CODE (x) == PLUS
2977 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2978 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2984 /* Print the lower register of a double word register pair */
2985 if (GET_CODE (x) == REG)
2986 fputs (reg_names[ REGNO (x)+1 ], file);
2988 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2991 /* case 'l': print a LABEL_REF. */
2995 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2996 for the second word of double memory operations. */
2997 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2998 switch (GET_CODE (x))
3001 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3004 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3012 frv_print_operand_memory_reference (file, x, offset);
3018 /* Print the opcode of a command. */
3019 switch (GET_CODE (x))
3022 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3024 case PLUS: fputs ("add", file); break;
3025 case MINUS: fputs ("sub", file); break;
3026 case AND: fputs ("and", file); break;
3027 case IOR: fputs ("or", file); break;
3028 case XOR: fputs ("xor", file); break;
3029 case ASHIFT: fputs ("sll", file); break;
3030 case ASHIFTRT: fputs ("sra", file); break;
3031 case LSHIFTRT: fputs ("srl", file); break;
3035 /* case 'n': negate and print a constant int. */
3038 /* Print PIC label using operand as the number. */
3039 if (GET_CODE (x) != CONST_INT)
3040 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3042 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3046 /* Print 'u' if the operand is a update load/store. */
3047 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3052 /* If value is 0, print gr0, otherwise it must be a register. */
3053 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3054 fputs (reg_names[GPR_R0], file);
3056 else if (GET_CODE (x) == REG)
3057 fputs (reg_names [REGNO (x)], file);
3060 fatal_insn ("bad insn in frv_print_operand, z case", x);
3064 /* Print constant in hex. */
3065 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3067 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3074 if (GET_CODE (x) == REG)
3075 fputs (reg_names [REGNO (x)], file);
3077 else if (GET_CODE (x) == CONST_INT
3078 || GET_CODE (x) == CONST_DOUBLE)
3079 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3081 else if (frv_const_unspec_p (x, &unspec))
3082 frv_output_const_unspec (file, &unspec);
3084 else if (GET_CODE (x) == MEM)
3085 frv_print_operand_address (file, XEXP (x, 0));
3087 else if (CONSTANT_ADDRESS_P (x))
3088 frv_print_operand_address (file, x);
3091 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3096 fatal_insn ("frv_print_operand: unknown code", x);
3104 /* A C statement (sans semicolon) for initializing the variable CUM for the
3105 state at the beginning of the argument list. The variable has type
3106 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3107 of the function which will receive the args, or 0 if the args are to a
3108 compiler support library function. The value of INDIRECT is nonzero when
3109 processing an indirect call, for example a call through a function pointer.
3110 The value of INDIRECT is zero for a call to an explicitly named function, a
3111 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3112 arguments for the function being compiled.
3114 When processing a call to a compiler support library function, LIBNAME
3115 identifies which one. It is a `symbol_ref' rtx which contains the name of
3116 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3117 being processed. Thus, each time this macro is called, either LIBNAME or
3118 FNTYPE is nonzero, but never both of them at once. */
3121 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3127 *cum = FIRST_ARG_REGNUM;
3129 if (TARGET_DEBUG_ARG)
3131 fprintf (stderr, "\ninit_cumulative_args:");
3132 if (!fndecl && fntype)
3133 fputs (" indirect", stderr);
3136 fputs (" incoming", stderr);
3140 tree ret_type = TREE_TYPE (fntype);
3141 fprintf (stderr, " return=%s,",
3142 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3145 if (libname && GET_CODE (libname) == SYMBOL_REF)
3146 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3148 if (cfun->returns_struct)
3149 fprintf (stderr, " return-struct");
3151 putc ('\n', stderr);
3156 /* Return true if we should pass an argument on the stack rather than
3160 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3162 if (mode == BLKmode)
3166 return AGGREGATE_TYPE_P (type);
3169 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3170 argument with the specified mode and type. If it is not defined,
3171 `PARM_BOUNDARY' is used for all arguments. */
3174 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3175 tree type ATTRIBUTE_UNUSED)
3177 return BITS_PER_WORD;
3181 frv_function_arg (CUMULATIVE_ARGS *cum,
3182 enum machine_mode mode,
3183 tree type ATTRIBUTE_UNUSED,
3185 int incoming ATTRIBUTE_UNUSED)
3187 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3192 /* Return a marker for use in the call instruction. */
3193 if (xmode == VOIDmode)
3199 else if (arg_num <= LAST_ARG_REGNUM)
3201 ret = gen_rtx_REG (xmode, arg_num);
3202 debstr = reg_names[arg_num];
3211 if (TARGET_DEBUG_ARG)
3213 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3214 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3220 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3221 advance past an argument in the argument list. The values MODE, TYPE and
3222 NAMED describe that argument. Once this is done, the variable CUM is
3223 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3225 This macro need not do anything if the argument in question was passed on
3226 the stack. The compiler knows how to track the amount of stack space used
3227 for arguments without any special help. */
3230 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3231 enum machine_mode mode,
3232 tree type ATTRIBUTE_UNUSED,
3235 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3236 int bytes = GET_MODE_SIZE (xmode);
3237 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3240 *cum = arg_num + words;
3242 if (TARGET_DEBUG_ARG)
3244 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3245 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3249 /* A C expression for the number of words, at the beginning of an argument,
3250 must be put in registers. The value must be zero for arguments that are
3251 passed entirely in registers or that are entirely pushed on the stack.
3253 On some machines, certain arguments must be passed partially in registers
3254 and partially in memory. On these machines, typically the first N words of
3255 arguments are passed in registers, and the rest on the stack. If a
3256 multi-word argument (a `double' or a structure) crosses that boundary, its
3257 first few words must be passed in registers and the rest must be pushed.
3258 This macro tells the compiler when this occurs, and how many of the words
3259 should go in registers.
3261 `FUNCTION_ARG' for these arguments should return the first register to be
3262 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3263 the called function. */
3266 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3267 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3269 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3270 int bytes = GET_MODE_SIZE (xmode);
3271 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3275 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3276 ? LAST_ARG_REGNUM - arg_num + 1
3278 ret *= UNITS_PER_WORD;
3280 if (TARGET_DEBUG_ARG && ret)
3281 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3287 /* Return true if a register is ok to use as a base or index register. */
3289 static FRV_INLINE int
3290 frv_regno_ok_for_base_p (int regno, int strict_p)
3296 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3298 if (regno == ARG_POINTER_REGNUM)
3301 return (regno >= FIRST_PSEUDO_REGISTER);
3305 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3306 RTX) is a legitimate memory address on the target machine for a memory
3307 operand of mode MODE.
3309 It usually pays to define several simpler macros to serve as subroutines for
3310 this one. Otherwise it may be too complicated to understand.
3312 This macro must exist in two variants: a strict variant and a non-strict
3313 one. The strict variant is used in the reload pass. It must be defined so
3314 that any pseudo-register that has not been allocated a hard register is
3315 considered a memory reference. In contexts where some kind of register is
3316 required, a pseudo-register with no hard register must be rejected.
3318 The non-strict variant is used in other passes. It must be defined to
3319 accept all pseudo-registers in every context where some kind of register is
3322 Compiler source files that want to use the strict variant of this macro
3323 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3324 conditional to define the strict variant in that case and the non-strict
3327 Subroutines to check for acceptable registers for various purposes (one for
3328 base registers, one for index registers, and so on) are typically among the
3329 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3330 subroutine macros need have two variants; the higher levels of macros may be
3331 the same whether strict or not.
3333 Normally, constant addresses which are the sum of a `symbol_ref' and an
3334 integer are stored inside a `const' RTX to mark them as constant.
3335 Therefore, there is no need to recognize such sums specifically as
3336 legitimate addresses. Normally you would simply recognize any `const' as
3339 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3340 are not marked with `const'. It assumes that a naked `plus' indicates
3341 indexing. If so, then you *must* reject such naked constant sums as
3342 illegitimate addresses, so that none of them will be given to
3343 `PRINT_OPERAND_ADDRESS'.
3345 On some machines, whether a symbolic address is legitimate depends on the
3346 section that the address refers to. On these machines, define the macro
3347 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3348 then check for it here. When you see a `const', you will have to look
3349 inside it to find the `symbol_ref' in order to determine the section.
3351 The best way to modify the name string is by adding text to the beginning,
3352 with suitable punctuation to prevent any ambiguity. Allocate the new name
3353 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3354 remove and decode the added text and output the name accordingly, and define
3355 `(* targetm.strip_name_encoding)' to access the original name string.
3357 You can check the information stored here into the `symbol_ref' in the
3358 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3359 `PRINT_OPERAND_ADDRESS'. */
3362 frv_legitimate_address_p (enum machine_mode mode,
3366 int allow_double_reg_p)
3370 HOST_WIDE_INT value;
3373 if (FRV_SYMBOL_REF_TLS_P (x))
3376 switch (GET_CODE (x))
3383 if (GET_CODE (x) != REG)
3389 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3395 if (GET_CODE (x0) != REG
3396 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3397 || GET_CODE (x1) != PLUS
3398 || ! rtx_equal_p (x0, XEXP (x1, 0))
3399 || GET_CODE (XEXP (x1, 1)) != REG
3400 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3407 /* 12-bit immediate */
3412 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3414 /* If we can't use load/store double operations, make sure we can
3415 address the second word. */
3416 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3417 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3426 if (GET_CODE (x0) == SUBREG)
3427 x0 = SUBREG_REG (x0);
3429 if (GET_CODE (x0) != REG)
3432 regno0 = REGNO (x0);
3433 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3436 switch (GET_CODE (x1))
3442 x1 = SUBREG_REG (x1);
3443 if (GET_CODE (x1) != REG)
3449 /* Do not allow reg+reg addressing for modes > 1 word if we
3450 can't depend on having move double instructions. */
3451 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3454 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3458 /* 12-bit immediate */
3463 value = INTVAL (x1);
3464 ret = IN_RANGE_P (value, -2048, 2047);
3466 /* If we can't use load/store double operations, make sure we can
3467 address the second word. */
3468 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3469 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3474 if (!condexec_p && got12_operand (x1, VOIDmode))
3482 if (TARGET_DEBUG_ADDR)
3484 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3485 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3486 (condexec_p) ? ", inside conditional code" : "");
3493 /* Given an ADDR, generate code to inline the PLT. */
3495 gen_inlined_tls_plt (rtx addr)
3498 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3501 dest = gen_reg_rtx (DImode);
3508 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3509 calll #gettlsoff(ADDR)@(gr8, gr0)
3511 emit_insn (gen_tls_lddi (dest, addr, picreg));
3518 sethi.p #gottlsdeschi(ADDR), gr8
3519 setlo #gottlsdesclo(ADDR), gr8
3520 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3521 calll #gettlsoff(ADDR)@(gr8, gr0)
3523 rtx reguse = gen_reg_rtx (Pmode);
3524 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3525 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3528 retval = gen_reg_rtx (Pmode);
3529 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3533 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3534 the destination address. */
3536 gen_tlsmoff (rtx addr, rtx reg)
3538 rtx dest = gen_reg_rtx (Pmode);
3542 /* sethi.p #tlsmoffhi(x), grA
3543 setlo #tlsmofflo(x), grA
3545 dest = gen_reg_rtx (Pmode);
3546 emit_insn (gen_tlsoff_hilo (dest, addr,
3547 GEN_INT (R_FRV_TLSMOFFHI)));
3548 dest = gen_rtx_PLUS (Pmode, dest, reg);
3552 /* addi grB, #tlsmoff12(x), grC
3554 ld/st @(grB, #tlsmoff12(x)), grC
3556 dest = gen_reg_rtx (Pmode);
3557 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3558 GEN_INT (R_FRV_TLSMOFF12)));
3563 /* Generate code for a TLS address. */
3565 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3567 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3568 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3572 case TLS_MODEL_INITIAL_EXEC:
3576 ldi @(gr15, #gottlsoff12(x)), gr5
3578 dest = gen_reg_rtx (Pmode);
3579 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3580 dest = gen_rtx_PLUS (Pmode, tp, dest);
3584 /* -fPIC or anything else.
3586 sethi.p #gottlsoffhi(x), gr14
3587 setlo #gottlsofflo(x), gr14
3588 ld #tlsoff(x)@(gr15, gr14), gr9
3590 rtx tmp = gen_reg_rtx (Pmode);
3591 dest = gen_reg_rtx (Pmode);
3592 emit_insn (gen_tlsoff_hilo (tmp, addr,
3593 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3595 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3596 dest = gen_rtx_PLUS (Pmode, tp, dest);
3599 case TLS_MODEL_LOCAL_DYNAMIC:
3603 if (TARGET_INLINE_PLT)
3604 retval = gen_inlined_tls_plt (GEN_INT (0));
3607 /* call #gettlsoff(0) */
3608 retval = gen_reg_rtx (Pmode);
3609 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3612 reg = gen_reg_rtx (Pmode);
3613 emit_insn (gen_rtx_SET (VOIDmode, reg,
3614 gen_rtx_PLUS (Pmode,
3617 dest = gen_tlsmoff (addr, reg);
3620 dest = gen_reg_rtx (Pmode);
3621 emit_insn (gen_tlsoff_hilo (dest, addr,
3622 GEN_INT (R_FRV_TLSMOFFHI)));
3623 dest = gen_rtx_PLUS (Pmode, dest, reg);
3627 case TLS_MODEL_LOCAL_EXEC:
3628 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3630 case TLS_MODEL_GLOBAL_DYNAMIC:
3634 if (TARGET_INLINE_PLT)
3635 retval = gen_inlined_tls_plt (addr);
3638 /* call #gettlsoff(x) */
3639 retval = gen_reg_rtx (Pmode);
3640 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3642 dest = gen_rtx_PLUS (Pmode, retval, tp);
3653 frv_legitimize_address (rtx x,
3654 rtx oldx ATTRIBUTE_UNUSED,
3655 enum machine_mode mode ATTRIBUTE_UNUSED)
3657 if (GET_CODE (x) == SYMBOL_REF)
3659 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3661 return frv_legitimize_tls_address (x, model);
3667 /* Test whether a local function descriptor is canonical, i.e.,
3668 whether we can use FUNCDESC_GOTOFF to compute the address of the
3672 frv_local_funcdesc_p (rtx fnx)
3675 enum symbol_visibility vis;
3678 if (! SYMBOL_REF_LOCAL_P (fnx))
3681 fn = SYMBOL_REF_DECL (fnx);
3686 vis = DECL_VISIBILITY (fn);
3688 if (vis == VISIBILITY_PROTECTED)
3689 /* Private function descriptors for protected functions are not
3690 canonical. Temporarily change the visibility to global. */
3691 vis = VISIBILITY_DEFAULT;
3692 else if (flag_shlib)
3693 /* If we're already compiling for a shared library (that, unlike
3694 executables, can't assume that the existence of a definition
3695 implies local binding), we can skip the re-testing. */
3698 ret = default_binds_local_p_1 (fn, flag_pic);
3700 DECL_VISIBILITY (fn) = vis;
3705 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3709 frv_gen_GPsym2reg (rtx dest, rtx src)
3711 tree gp = get_identifier ("_gp");
3712 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3714 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3718 unspec_got_name (int i)
3722 case R_FRV_GOT12: return "got12";
3723 case R_FRV_GOTHI: return "gothi";
3724 case R_FRV_GOTLO: return "gotlo";
3725 case R_FRV_FUNCDESC: return "funcdesc";
3726 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3727 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3728 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3729 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3730 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3731 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3732 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3733 case R_FRV_GOTOFF12: return "gotoff12";
3734 case R_FRV_GOTOFFHI: return "gotoffhi";
3735 case R_FRV_GOTOFFLO: return "gotofflo";
3736 case R_FRV_GPREL12: return "gprel12";
3737 case R_FRV_GPRELHI: return "gprelhi";
3738 case R_FRV_GPRELLO: return "gprello";
3739 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3740 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3741 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3742 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3743 case R_FRV_TLSMOFF12: return "tlsmoff12";
3744 case R_FRV_TLSDESCHI: return "tlsdeschi";
3745 case R_FRV_TLSDESCLO: return "tlsdesclo";
3746 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3747 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3748 default: gcc_unreachable ();
3752 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3753 is added inside the relocation operator. */
3756 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3758 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3759 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3760 fputs (")", stream);
3763 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3764 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3765 otherwise return ORIG_X. */
3768 frv_find_base_term (rtx x)
3770 struct frv_unspec unspec;
3772 if (frv_const_unspec_p (x, &unspec)
3773 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3774 return plus_constant (unspec.symbol, unspec.offset);
3779 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3780 the operand is used by a predicated instruction. */
3783 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3785 return ((GET_MODE (op) == mode || mode == VOIDmode)
3786 && GET_CODE (op) == MEM
3787 && frv_legitimate_address_p (mode, XEXP (op, 0),
3788 reload_completed, condexec_p, FALSE));
3792 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3794 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3795 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3801 rvrtx = operands[0];
3805 addr = XEXP (operands[0], 0);
3807 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3808 any calls that would involve a PLT, but can't tell, since we
3809 don't know whether an extern function is going to be provided by
3810 a separate translation unit or imported from a separate module.
3811 When compiling for shared libraries, if the function has default
3812 visibility, we assume it's overridable, so we inline the PLT, but
3813 for executables, we don't really have a way to make a good
3814 decision: a function is as likely to be imported from a shared
3815 library as it is to be defined in the executable itself. We
3816 assume executables will get global functions defined locally,
3817 whereas shared libraries will have them potentially overridden,
3818 so we only inline PLTs when compiling for shared libraries.
3820 In order to mark a function as local to a shared library, any
3821 non-default visibility attribute suffices. Unfortunately,
3822 there's no simple way to tag a function declaration as ``in a
3823 different module'', which we could then use to trigger PLT
3824 inlining on executables. There's -minline-plt, but it affects
3825 all external functions, so one would have to also mark function
3826 declarations available in the same module with non-default
3827 visibility, which is advantageous in itself. */
3828 if (GET_CODE (addr) == SYMBOL_REF
3829 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3833 dest = gen_reg_rtx (SImode);
3835 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3836 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3838 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3839 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3841 crtl->uses_pic_offset_table = TRUE;
3844 else if (GET_CODE (addr) == SYMBOL_REF)
3846 /* These are always either local, or handled through a local
3849 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3850 operands[2], picreg, lr);
3852 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3856 else if (! ldd_address_operand (addr, Pmode))
3857 addr = force_reg (Pmode, addr);
3859 picreg = gen_reg_rtx (DImode);
3860 emit_insn (gen_movdi_ldd (picreg, addr));
3862 if (sibcall && ret_value)
3863 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3865 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3867 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3869 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3873 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3874 process these separately from any offsets, such that we add any
3875 offsets to the function descriptor (the actual pointer), not to the
3876 function address. */
3879 frv_function_symbol_referenced_p (rtx x)
3885 if (GET_CODE (x) == SYMBOL_REF)
3886 return SYMBOL_REF_FUNCTION_P (x);
3888 length = GET_RTX_LENGTH (GET_CODE (x));
3889 format = GET_RTX_FORMAT (GET_CODE (x));
3891 for (j = 0; j < length; ++j)
3896 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3902 if (XVEC (x, j) != 0)
3905 for (k = 0; k < XVECLEN (x, j); ++k)
3906 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3912 /* Nothing to do. */
3920 /* Return true if the memory operand is one that can be conditionally
3924 condexec_memory_operand (rtx op, enum machine_mode mode)
3926 enum machine_mode op_mode = GET_MODE (op);
3929 if (mode != VOIDmode && op_mode != mode)
3944 if (GET_CODE (op) != MEM)
3947 addr = XEXP (op, 0);
3948 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
3951 /* Return true if the bare return instruction can be used outside of the
3952 epilog code. For frv, we only do it if there was no stack allocation. */
3955 direct_return_p (void)
3959 if (!reload_completed)
3962 info = frv_stack_info ();
3963 return (info->total_size == 0);
3968 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3970 if (GET_CODE (src) == SYMBOL_REF)
3972 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3974 src = frv_legitimize_tls_address (src, model);
3980 if (frv_emit_movsi (dest, src))
3989 if (!reload_in_progress
3990 && !reload_completed
3991 && !register_operand (dest, mode)
3992 && !reg_or_0_operand (src, mode))
3993 src = copy_to_mode_reg (mode, src);
4000 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4003 /* Emit code to handle a MOVSI, adding in the small data register or pic
4004 register if needed to load up addresses. Return TRUE if the appropriate
4005 instructions are emitted. */
4008 frv_emit_movsi (rtx dest, rtx src)
4010 int base_regno = -1;
4013 struct frv_unspec old_unspec;
4015 if (!reload_in_progress
4016 && !reload_completed
4017 && !register_operand (dest, SImode)
4018 && (!reg_or_0_operand (src, SImode)
4019 /* Virtual registers will almost always be replaced by an
4020 add instruction, so expose this to CSE by copying to
4021 an intermediate register. */
4022 || (GET_CODE (src) == REG
4023 && IN_RANGE_P (REGNO (src),
4024 FIRST_VIRTUAL_REGISTER,
4025 LAST_VIRTUAL_REGISTER))))
4027 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4031 /* Explicitly add in the PIC or small data register if needed. */
4032 switch (GET_CODE (src))
4041 /* Using GPREL12, we use a single GOT entry for all symbols
4042 in read-only sections, but trade sequences such as:
4044 sethi #gothi(label), gr#
4045 setlo #gotlo(label), gr#
4050 ld @(gr15,#got12(_gp)), gr#
4051 sethi #gprelhi(label), gr##
4052 setlo #gprello(label), gr##
4055 We may often be able to share gr# for multiple
4056 computations of GPREL addresses, and we may often fold
4057 the final add into the pair of registers of a load or
4058 store instruction, so it's often profitable. Even when
4059 optimizing for size, we're trading a GOT entry for an
4060 additional instruction, which trades GOT space
4061 (read-write) for code size (read-only, shareable), as
4062 long as the symbol is not used in more than two different
4065 With -fpie/-fpic, we'd be trading a single load for a
4066 sequence of 4 instructions, because the offset of the
4067 label can't be assumed to be addressable with 12 bits, so
4068 we don't do this. */
4069 if (TARGET_GPREL_RO)
4070 unspec = R_FRV_GPREL12;
4072 unspec = R_FRV_GOT12;
4075 base_regno = PIC_REGNO;
4080 if (frv_const_unspec_p (src, &old_unspec))
4083 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4086 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4087 emit_move_insn (dest, src);
4092 sym = XEXP (sym, 0);
4093 if (GET_CODE (sym) == PLUS
4094 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4095 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4096 sym = XEXP (sym, 0);
4097 if (GET_CODE (sym) == SYMBOL_REF)
4099 else if (GET_CODE (sym) == LABEL_REF)
4102 goto handle_whatever;
4110 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4114 src = frv_legitimize_tls_address (src, model);
4115 emit_move_insn (dest, src);
4119 if (SYMBOL_REF_FUNCTION_P (sym))
4121 if (frv_local_funcdesc_p (sym))
4122 unspec = R_FRV_FUNCDESC_GOTOFF12;
4124 unspec = R_FRV_FUNCDESC_GOT12;
4128 if (CONSTANT_POOL_ADDRESS_P (sym))
4129 switch (GET_CODE (get_pool_constant (sym)))
4136 unspec = R_FRV_GOTOFF12;
4141 if (TARGET_GPREL_RO)
4142 unspec = R_FRV_GPREL12;
4144 unspec = R_FRV_GOT12;
4147 else if (SYMBOL_REF_LOCAL_P (sym)
4148 && !SYMBOL_REF_EXTERNAL_P (sym)
4149 && SYMBOL_REF_DECL (sym)
4150 && (!DECL_P (SYMBOL_REF_DECL (sym))
4151 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4153 tree decl = SYMBOL_REF_DECL (sym);
4154 tree init = TREE_CODE (decl) == VAR_DECL
4155 ? DECL_INITIAL (decl)
4156 : TREE_CODE (decl) == CONSTRUCTOR
4159 bool named_section, readonly;
4161 if (init && init != error_mark_node)
4162 reloc = compute_reloc_for_constant (init);
4164 named_section = TREE_CODE (decl) == VAR_DECL
4165 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4166 readonly = decl_readonly_section (decl, reloc);
4169 unspec = R_FRV_GOT12;
4171 unspec = R_FRV_GOTOFF12;
4172 else if (readonly && TARGET_GPREL_RO)
4173 unspec = R_FRV_GPREL12;
4175 unspec = R_FRV_GOT12;
4178 unspec = R_FRV_GOT12;
4182 else if (SYMBOL_REF_SMALL_P (sym))
4183 base_regno = SDA_BASE_REG;
4186 base_regno = PIC_REGNO;
4191 if (base_regno >= 0)
4193 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4194 emit_insn (gen_symGOTOFF2reg (dest, src,
4195 gen_rtx_REG (Pmode, base_regno),
4196 GEN_INT (R_FRV_GPREL12)));
4198 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4199 gen_rtx_REG (Pmode, base_regno),
4200 GEN_INT (R_FRV_GPREL12)));
4201 if (base_regno == PIC_REGNO)
4202 crtl->uses_pic_offset_table = TRUE;
4210 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4211 new uses of it once reload has begun. */
4212 gcc_assert (!reload_in_progress && !reload_completed);
4216 case R_FRV_GOTOFF12:
4217 if (!frv_small_data_reloc_p (sym, unspec))
4218 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4221 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4224 if (!frv_small_data_reloc_p (sym, unspec))
4225 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4228 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4230 case R_FRV_FUNCDESC_GOTOFF12:
4232 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4235 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4239 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4242 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4246 crtl->uses_pic_offset_table = TRUE;
4255 /* Return a string to output a single word move. */
4258 output_move_single (rtx operands[], rtx insn)
4260 rtx dest = operands[0];
4261 rtx src = operands[1];
4263 if (GET_CODE (dest) == REG)
4265 int dest_regno = REGNO (dest);
4266 enum machine_mode mode = GET_MODE (dest);
4268 if (GPR_P (dest_regno))
4270 if (GET_CODE (src) == REG)
4272 /* gpr <- some sort of register */
4273 int src_regno = REGNO (src);
4275 if (GPR_P (src_regno))
4276 return "mov %1, %0";
4278 else if (FPR_P (src_regno))
4279 return "movfg %1, %0";
4281 else if (SPR_P (src_regno))
4282 return "movsg %1, %0";
4285 else if (GET_CODE (src) == MEM)
4294 return "ldsb%I1%U1 %M1,%0";
4297 return "ldsh%I1%U1 %M1,%0";
4301 return "ld%I1%U1 %M1, %0";
4305 else if (GET_CODE (src) == CONST_INT
4306 || GET_CODE (src) == CONST_DOUBLE)
4308 /* gpr <- integer/floating constant */
4309 HOST_WIDE_INT value;
4311 if (GET_CODE (src) == CONST_INT)
4312 value = INTVAL (src);
4314 else if (mode == SFmode)
4319 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4320 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4325 value = CONST_DOUBLE_LOW (src);
4327 if (IN_RANGE_P (value, -32768, 32767))
4328 return "setlos %1, %0";
4333 else if (GET_CODE (src) == SYMBOL_REF
4334 || GET_CODE (src) == LABEL_REF
4335 || GET_CODE (src) == CONST)
4341 else if (FPR_P (dest_regno))
4343 if (GET_CODE (src) == REG)
4345 /* fpr <- some sort of register */
4346 int src_regno = REGNO (src);
4348 if (GPR_P (src_regno))
4349 return "movgf %1, %0";
4351 else if (FPR_P (src_regno))
4353 if (TARGET_HARD_FLOAT)
4354 return "fmovs %1, %0";
4356 return "mor %1, %1, %0";
4360 else if (GET_CODE (src) == MEM)
4369 return "ldbf%I1%U1 %M1,%0";
4372 return "ldhf%I1%U1 %M1,%0";
4376 return "ldf%I1%U1 %M1, %0";
4380 else if (ZERO_P (src))
4381 return "movgf %., %0";
4384 else if (SPR_P (dest_regno))
4386 if (GET_CODE (src) == REG)
4388 /* spr <- some sort of register */
4389 int src_regno = REGNO (src);
4391 if (GPR_P (src_regno))
4392 return "movgs %1, %0";
4394 else if (ZERO_P (src))
4395 return "movgs %., %0";
4399 else if (GET_CODE (dest) == MEM)
4401 if (GET_CODE (src) == REG)
4403 int src_regno = REGNO (src);
4404 enum machine_mode mode = GET_MODE (dest);
4406 if (GPR_P (src_regno))
4414 return "stb%I0%U0 %1, %M0";
4417 return "sth%I0%U0 %1, %M0";
4421 return "st%I0%U0 %1, %M0";
4425 else if (FPR_P (src_regno))
4433 return "stbf%I0%U0 %1, %M0";
4436 return "sthf%I0%U0 %1, %M0";
4440 return "stf%I0%U0 %1, %M0";
4445 else if (ZERO_P (src))
4447 switch (GET_MODE (dest))
4453 return "stb%I0%U0 %., %M0";
4456 return "sth%I0%U0 %., %M0";
4460 return "st%I0%U0 %., %M0";
4465 fatal_insn ("bad output_move_single operand", insn);
4470 /* Return a string to output a double word move. */
4473 output_move_double (rtx operands[], rtx insn)
4475 rtx dest = operands[0];
4476 rtx src = operands[1];
4477 enum machine_mode mode = GET_MODE (dest);
4479 if (GET_CODE (dest) == REG)
4481 int dest_regno = REGNO (dest);
4483 if (GPR_P (dest_regno))
4485 if (GET_CODE (src) == REG)
4487 /* gpr <- some sort of register */
4488 int src_regno = REGNO (src);
4490 if (GPR_P (src_regno))
4493 else if (FPR_P (src_regno))
4495 if (((dest_regno - GPR_FIRST) & 1) == 0
4496 && ((src_regno - FPR_FIRST) & 1) == 0)
4497 return "movfgd %1, %0";
4503 else if (GET_CODE (src) == MEM)
4506 if (dbl_memory_one_insn_operand (src, mode))
4507 return "ldd%I1%U1 %M1, %0";
4512 else if (GET_CODE (src) == CONST_INT
4513 || GET_CODE (src) == CONST_DOUBLE)
4517 else if (FPR_P (dest_regno))
4519 if (GET_CODE (src) == REG)
4521 /* fpr <- some sort of register */
4522 int src_regno = REGNO (src);
4524 if (GPR_P (src_regno))
4526 if (((dest_regno - FPR_FIRST) & 1) == 0
4527 && ((src_regno - GPR_FIRST) & 1) == 0)
4528 return "movgfd %1, %0";
4533 else if (FPR_P (src_regno))
4536 && ((dest_regno - FPR_FIRST) & 1) == 0
4537 && ((src_regno - FPR_FIRST) & 1) == 0)
4538 return "fmovd %1, %0";
4544 else if (GET_CODE (src) == MEM)
4547 if (dbl_memory_one_insn_operand (src, mode))
4548 return "lddf%I1%U1 %M1, %0";
4553 else if (ZERO_P (src))
4558 else if (GET_CODE (dest) == MEM)
4560 if (GET_CODE (src) == REG)
4562 int src_regno = REGNO (src);
4564 if (GPR_P (src_regno))
4566 if (((src_regno - GPR_FIRST) & 1) == 0
4567 && dbl_memory_one_insn_operand (dest, mode))
4568 return "std%I0%U0 %1, %M0";
4573 if (FPR_P (src_regno))
4575 if (((src_regno - FPR_FIRST) & 1) == 0
4576 && dbl_memory_one_insn_operand (dest, mode))
4577 return "stdf%I0%U0 %1, %M0";
4583 else if (ZERO_P (src))
4585 if (dbl_memory_one_insn_operand (dest, mode))
4586 return "std%I0%U0 %., %M0";
4592 fatal_insn ("bad output_move_double operand", insn);
4597 /* Return a string to output a single word conditional move.
4598 Operand0 -- EQ/NE of ccr register and 0
4599 Operand1 -- CCR register
4600 Operand2 -- destination
4601 Operand3 -- source */
4604 output_condmove_single (rtx operands[], rtx insn)
4606 rtx dest = operands[2];
4607 rtx src = operands[3];
4609 if (GET_CODE (dest) == REG)
4611 int dest_regno = REGNO (dest);
4612 enum machine_mode mode = GET_MODE (dest);
4614 if (GPR_P (dest_regno))
4616 if (GET_CODE (src) == REG)
4618 /* gpr <- some sort of register */
4619 int src_regno = REGNO (src);
4621 if (GPR_P (src_regno))
4622 return "cmov %z3, %2, %1, %e0";
4624 else if (FPR_P (src_regno))
4625 return "cmovfg %3, %2, %1, %e0";
4628 else if (GET_CODE (src) == MEM)
4637 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4640 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4644 return "cld%I3%U3 %M3, %2, %1, %e0";
4648 else if (ZERO_P (src))
4649 return "cmov %., %2, %1, %e0";
4652 else if (FPR_P (dest_regno))
4654 if (GET_CODE (src) == REG)
4656 /* fpr <- some sort of register */
4657 int src_regno = REGNO (src);
4659 if (GPR_P (src_regno))
4660 return "cmovgf %3, %2, %1, %e0";
4662 else if (FPR_P (src_regno))
4664 if (TARGET_HARD_FLOAT)
4665 return "cfmovs %3,%2,%1,%e0";
4667 return "cmor %3, %3, %2, %1, %e0";
4671 else if (GET_CODE (src) == MEM)
4674 if (mode == SImode || mode == SFmode)
4675 return "cldf%I3%U3 %M3, %2, %1, %e0";
4678 else if (ZERO_P (src))
4679 return "cmovgf %., %2, %1, %e0";
4683 else if (GET_CODE (dest) == MEM)
4685 if (GET_CODE (src) == REG)
4687 int src_regno = REGNO (src);
4688 enum machine_mode mode = GET_MODE (dest);
4690 if (GPR_P (src_regno))
4698 return "cstb%I2%U2 %3, %M2, %1, %e0";
4701 return "csth%I2%U2 %3, %M2, %1, %e0";
4705 return "cst%I2%U2 %3, %M2, %1, %e0";
4709 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4710 return "cstf%I2%U2 %3, %M2, %1, %e0";
4713 else if (ZERO_P (src))
4715 enum machine_mode mode = GET_MODE (dest);
4722 return "cstb%I2%U2 %., %M2, %1, %e0";
4725 return "csth%I2%U2 %., %M2, %1, %e0";
4729 return "cst%I2%U2 %., %M2, %1, %e0";
4734 fatal_insn ("bad output_condmove_single operand", insn);
4739 /* Emit the appropriate code to do a comparison, returning the register the
4740 comparison was done it. */
4743 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4745 enum machine_mode cc_mode;
4748 /* Floating point doesn't have comparison against a constant. */
4749 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4750 op1 = force_reg (GET_MODE (op0), op1);
4752 /* Possibly disable using anything but a fixed register in order to work
4753 around cse moving comparisons past function calls. */
4754 cc_mode = SELECT_CC_MODE (test, op0, op1);
4755 cc_reg = ((TARGET_ALLOC_CC)
4756 ? gen_reg_rtx (cc_mode)
4757 : gen_rtx_REG (cc_mode,
4758 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4760 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4761 gen_rtx_COMPARE (cc_mode, op0, op1)));
4767 /* Emit code for a conditional branch. The comparison operands were previously
4768 stored in frv_compare_op0 and frv_compare_op1.
4770 XXX: I originally wanted to add a clobber of a CCR register to use in
4771 conditional execution, but that confuses the rest of the compiler. */
4774 frv_emit_cond_branch (enum rtx_code test, rtx label)
4779 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4780 enum machine_mode cc_mode = GET_MODE (cc_reg);
4782 /* Branches generate:
4784 (if_then_else (<test>, <cc_reg>, (const_int 0))
4785 (label_ref <branch_label>)
4787 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
4788 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4789 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4790 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4795 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
4796 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
4799 frv_emit_scc (enum rtx_code test, rtx target)
4805 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4807 /* SCC instructions generate:
4808 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4809 (clobber (<ccr_reg>))]) */
4810 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4811 set = gen_rtx_SET (VOIDmode, target, test_rtx);
4813 cr_reg = ((TARGET_ALLOC_CC)
4814 ? gen_reg_rtx (CC_CCRmode)
4815 : gen_rtx_REG (CC_CCRmode,
4816 ((GET_MODE (cc_reg) == CC_FPmode)
4820 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4821 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4826 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4827 the separate insns. */
4830 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4836 /* Set the appropriate CCR bit. */
4837 emit_insn (gen_rtx_SET (VOIDmode,
4839 gen_rtx_fmt_ee (GET_CODE (test),
4844 /* Move the value into the destination. */
4845 emit_move_insn (dest, GEN_INT (value));
4847 /* Move 0 into the destination if the test failed */
4848 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4849 gen_rtx_EQ (GET_MODE (cr_reg),
4852 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4854 /* Finish up, return sequence. */
4861 /* Emit the code for a conditional move, return TRUE if we could do the
4865 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4872 enum rtx_code test = GET_CODE (test_rtx);
4873 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4874 enum machine_mode cc_mode = GET_MODE (cc_reg);
4876 /* Conditional move instructions generate:
4877 (parallel [(set <target>
4878 (if_then_else (<test> <cc_reg> (const_int 0))
4881 (clobber (<ccr_reg>))]) */
4883 /* Handle various cases of conditional move involving two constants. */
4884 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4886 HOST_WIDE_INT value1 = INTVAL (src1);
4887 HOST_WIDE_INT value2 = INTVAL (src2);
4889 /* Having 0 as one of the constants can be done by loading the other
4890 constant, and optionally moving in gr0. */
4891 if (value1 == 0 || value2 == 0)
4894 /* If the first value is within an addi range and also the difference
4895 between the two fits in an addi's range, load up the difference, then
4896 conditionally move in 0, and then unconditionally add the first
4898 else if (IN_RANGE_P (value1, -2048, 2047)
4899 && IN_RANGE_P (value2 - value1, -2048, 2047))
4902 /* If neither condition holds, just force the constant into a
4906 src1 = force_reg (GET_MODE (dest), src1);
4907 src2 = force_reg (GET_MODE (dest), src2);
4911 /* If one value is a register, insure the other value is either 0 or a
4915 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4916 src1 = force_reg (GET_MODE (dest), src1);
4918 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4919 src2 = force_reg (GET_MODE (dest), src2);
4922 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4923 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4925 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4927 cr_reg = ((TARGET_ALLOC_CC)
4928 ? gen_reg_rtx (CC_CCRmode)
4929 : gen_rtx_REG (CC_CCRmode,
4930 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4932 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4933 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4938 /* Split a conditional move into constituent parts, returning a SEQUENCE
4939 containing all of the insns. */
4942 frv_split_cond_move (rtx operands[])
4944 rtx dest = operands[0];
4945 rtx test = operands[1];
4946 rtx cc_reg = operands[2];
4947 rtx src1 = operands[3];
4948 rtx src2 = operands[4];
4949 rtx cr_reg = operands[5];
4951 enum machine_mode cr_mode = GET_MODE (cr_reg);
4955 /* Set the appropriate CCR bit. */
4956 emit_insn (gen_rtx_SET (VOIDmode,
4958 gen_rtx_fmt_ee (GET_CODE (test),
4963 /* Handle various cases of conditional move involving two constants. */
4964 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4966 HOST_WIDE_INT value1 = INTVAL (src1);
4967 HOST_WIDE_INT value2 = INTVAL (src2);
4969 /* Having 0 as one of the constants can be done by loading the other
4970 constant, and optionally moving in gr0. */
4973 emit_move_insn (dest, src2);
4974 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4975 gen_rtx_NE (cr_mode, cr_reg,
4977 gen_rtx_SET (VOIDmode, dest, src1)));
4980 else if (value2 == 0)
4982 emit_move_insn (dest, src1);
4983 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4984 gen_rtx_EQ (cr_mode, cr_reg,
4986 gen_rtx_SET (VOIDmode, dest, src2)));
4989 /* If the first value is within an addi range and also the difference
4990 between the two fits in an addi's range, load up the difference, then
4991 conditionally move in 0, and then unconditionally add the first
4993 else if (IN_RANGE_P (value1, -2048, 2047)
4994 && IN_RANGE_P (value2 - value1, -2048, 2047))
4996 rtx dest_si = ((GET_MODE (dest) == SImode)
4998 : gen_rtx_SUBREG (SImode, dest, 0));
5000 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5001 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5002 gen_rtx_NE (cr_mode, cr_reg,
5004 gen_rtx_SET (VOIDmode, dest_si,
5006 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5014 /* Emit the conditional move for the test being true if needed. */
5015 if (! rtx_equal_p (dest, src1))
5016 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5017 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5018 gen_rtx_SET (VOIDmode, dest, src1)));
5020 /* Emit the conditional move for the test being false if needed. */
5021 if (! rtx_equal_p (dest, src2))
5022 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5023 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5024 gen_rtx_SET (VOIDmode, dest, src2)));
5027 /* Finish up, return sequence. */
5034 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5035 memory location that is not known to be dword-aligned. */
5037 frv_split_double_load (rtx dest, rtx source)
5039 int regno = REGNO (dest);
5040 rtx dest1 = gen_highpart (SImode, dest);
5041 rtx dest2 = gen_lowpart (SImode, dest);
5042 rtx address = XEXP (source, 0);
5044 /* If the address is pre-modified, load the lower-numbered register
5045 first, then load the other register using an integer offset from
5046 the modified base register. This order should always be safe,
5047 since the pre-modification cannot affect the same registers as the
5050 The situation for other loads is more complicated. Loading one
5051 of the registers could affect the value of ADDRESS, so we must
5052 be careful which order we do them in. */
5053 if (GET_CODE (address) == PRE_MODIFY
5054 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5056 /* It is safe to load the lower-numbered register first. */
5057 emit_move_insn (dest1, change_address (source, SImode, NULL));
5058 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5062 /* ADDRESS is not pre-modified and the address depends on the
5063 lower-numbered register. Load the higher-numbered register
5065 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5066 emit_move_insn (dest1, change_address (source, SImode, NULL));
5070 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5071 and SOURCE is either a double register or the constant zero. */
5073 frv_split_double_store (rtx dest, rtx source)
5075 rtx dest1 = change_address (dest, SImode, NULL);
5076 rtx dest2 = frv_index_memory (dest, SImode, 1);
5077 if (ZERO_P (source))
5079 emit_move_insn (dest1, CONST0_RTX (SImode));
5080 emit_move_insn (dest2, CONST0_RTX (SImode));
5084 emit_move_insn (dest1, gen_highpart (SImode, source));
5085 emit_move_insn (dest2, gen_lowpart (SImode, source));
5090 /* Split a min/max operation returning a SEQUENCE containing all of the
5094 frv_split_minmax (rtx operands[])
5096 rtx dest = operands[0];
5097 rtx minmax = operands[1];
5098 rtx src1 = operands[2];
5099 rtx src2 = operands[3];
5100 rtx cc_reg = operands[4];
5101 rtx cr_reg = operands[5];
5103 enum rtx_code test_code;
5104 enum machine_mode cr_mode = GET_MODE (cr_reg);
5108 /* Figure out which test to use. */
5109 switch (GET_CODE (minmax))
5114 case SMIN: test_code = LT; break;
5115 case SMAX: test_code = GT; break;
5116 case UMIN: test_code = LTU; break;
5117 case UMAX: test_code = GTU; break;
5120 /* Issue the compare instruction. */
5121 emit_insn (gen_rtx_SET (VOIDmode,
5123 gen_rtx_COMPARE (GET_MODE (cc_reg),
5126 /* Set the appropriate CCR bit. */
5127 emit_insn (gen_rtx_SET (VOIDmode,
5129 gen_rtx_fmt_ee (test_code,
5134 /* If are taking the min/max of a nonzero constant, load that first, and
5135 then do a conditional move of the other value. */
5136 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5138 gcc_assert (!rtx_equal_p (dest, src1));
5140 emit_move_insn (dest, src2);
5141 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5142 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5143 gen_rtx_SET (VOIDmode, dest, src1)));
5146 /* Otherwise, do each half of the move. */
5149 /* Emit the conditional move for the test being true if needed. */
5150 if (! rtx_equal_p (dest, src1))
5151 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5152 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5153 gen_rtx_SET (VOIDmode, dest, src1)));
5155 /* Emit the conditional move for the test being false if needed. */
5156 if (! rtx_equal_p (dest, src2))
5157 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5158 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5159 gen_rtx_SET (VOIDmode, dest, src2)));
5162 /* Finish up, return sequence. */
5169 /* Split an integer abs operation returning a SEQUENCE containing all of the
5173 frv_split_abs (rtx operands[])
5175 rtx dest = operands[0];
5176 rtx src = operands[1];
5177 rtx cc_reg = operands[2];
5178 rtx cr_reg = operands[3];
5183 /* Issue the compare < 0 instruction. */
5184 emit_insn (gen_rtx_SET (VOIDmode,
5186 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5188 /* Set the appropriate CCR bit. */
5189 emit_insn (gen_rtx_SET (VOIDmode,
5191 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5193 /* Emit the conditional negate if the value is negative. */
5194 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5195 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5196 gen_negsi2 (dest, src)));
5198 /* Emit the conditional move for the test being false if needed. */
5199 if (! rtx_equal_p (dest, src))
5200 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5201 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5202 gen_rtx_SET (VOIDmode, dest, src)));
5204 /* Finish up, return sequence. */
5211 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5212 register used in an insn. */
5215 frv_clear_registers_used (rtx *ptr, void *data)
5217 if (GET_CODE (*ptr) == REG)
5219 int regno = REGNO (*ptr);
5220 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5222 if (regno < FIRST_PSEUDO_REGISTER)
5224 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5226 while (regno < reg_max)
5228 CLEAR_HARD_REG_BIT (*p_regs, regno);
5238 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5240 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5241 initialize the static storage. */
5243 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5245 frv_ifcvt.added_insns_list = NULL_RTX;
5246 frv_ifcvt.cur_scratch_regs = 0;
5247 frv_ifcvt.num_nested_cond_exec = 0;
5248 frv_ifcvt.cr_reg = NULL_RTX;
5249 frv_ifcvt.nested_cc_reg = NULL_RTX;
5250 frv_ifcvt.extra_int_cr = NULL_RTX;
5251 frv_ifcvt.extra_fp_cr = NULL_RTX;
5252 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5256 /* Internal function to add a potential insn to the list of insns to be inserted
5257 if the conditional execution conversion is successful. */
5260 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5262 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5264 link->jump = before_p; /* Mark to add this before or after insn. */
5265 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5266 frv_ifcvt.added_insns_list);
5268 if (TARGET_DEBUG_COND_EXEC)
5271 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5272 (before_p) ? "before" : "after",
5273 (int)INSN_UID (insn));
5275 debug_rtx (pattern);
5280 /* A C expression to modify the code described by the conditional if
5281 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5282 FALSE_EXPR for converting if-then and if-then-else code to conditional
5283 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5284 tests cannot be converted. */
5287 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5289 basic_block test_bb = ce_info->test_bb; /* test basic block */
5290 basic_block then_bb = ce_info->then_bb; /* THEN */
5291 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5292 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5293 rtx true_expr = *p_true;
5297 enum machine_mode mode = GET_MODE (true_expr);
5301 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5303 rtx sub_cond_exec_reg;
5305 enum rtx_code code_true;
5306 enum rtx_code code_false;
5307 enum reg_class cc_class;
5308 enum reg_class cr_class;
5311 reg_set_iterator rsi;
5313 /* Make sure we are only dealing with hard registers. Also honor the
5314 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5316 if (!reload_completed || !TARGET_COND_EXEC
5317 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5320 /* Figure out which registers we can allocate for our own purposes. Only
5321 consider registers that are not preserved across function calls and are
5322 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5323 if we did not need to use them in reloading other registers. */
5324 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5325 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5326 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5327 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5328 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5330 /* If this is a nested IF, we need to discover whether the CC registers that
5331 are set/used inside of the block are used anywhere else. If not, we can
5332 change them to be the CC register that is paired with the CR register that
5333 controls the outermost IF block. */
5334 if (ce_info->pass > 1)
5336 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5337 for (j = CC_FIRST; j <= CC_LAST; j++)
5338 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5340 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5344 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5348 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5351 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5355 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5356 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5358 frv_ifcvt.added_insns_list = NULL_RTX;
5359 frv_ifcvt.cur_scratch_regs = 0;
5361 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5362 * sizeof (basic_block));
5368 /* Remove anything live at the beginning of the join block from being
5369 available for allocation. */
5370 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5372 if (regno < FIRST_PSEUDO_REGISTER)
5373 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5377 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5379 if (ce_info->num_multiple_test_blocks)
5381 basic_block multiple_test_bb = ce_info->last_test_bb;
5383 while (multiple_test_bb != test_bb)
5385 bb[num_bb++] = multiple_test_bb;
5386 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5390 /* Add in the THEN and ELSE blocks to be scanned. */
5391 bb[num_bb++] = then_bb;
5393 bb[num_bb++] = else_bb;
5395 sub_cond_exec_reg = NULL_RTX;
5396 frv_ifcvt.num_nested_cond_exec = 0;
5398 /* Scan all of the blocks for registers that must not be allocated. */
5399 for (j = 0; j < num_bb; j++)
5401 rtx last_insn = BB_END (bb[j]);
5402 rtx insn = BB_HEAD (bb[j]);
5406 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5407 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5409 (int) INSN_UID (BB_HEAD (bb[j])),
5410 (int) INSN_UID (BB_END (bb[j])));
5412 /* Anything live at the beginning of the block is obviously unavailable
5414 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5416 if (regno < FIRST_PSEUDO_REGISTER)
5417 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5420 /* Loop through the insns in the block. */
5423 /* Mark any new registers that are created as being unavailable for
5424 allocation. Also see if the CC register used in nested IFs can be
5430 int skip_nested_if = FALSE;
5432 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5433 (void *)&tmp_reg->regs);
5435 pattern = PATTERN (insn);
5436 if (GET_CODE (pattern) == COND_EXEC)
5438 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5440 if (reg != sub_cond_exec_reg)
5442 sub_cond_exec_reg = reg;
5443 frv_ifcvt.num_nested_cond_exec++;
5447 set = single_set_pattern (pattern);
5450 rtx dest = SET_DEST (set);
5451 rtx src = SET_SRC (set);
5453 if (GET_CODE (dest) == REG)
5455 int regno = REGNO (dest);
5456 enum rtx_code src_code = GET_CODE (src);
5458 if (CC_P (regno) && src_code == COMPARE)
5459 skip_nested_if = TRUE;
5461 else if (CR_P (regno)
5462 && (src_code == IF_THEN_ELSE
5463 || COMPARISON_P (src)))
5464 skip_nested_if = TRUE;
5468 if (! skip_nested_if)
5469 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5470 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5473 if (insn == last_insn)
5476 insn = NEXT_INSN (insn);
5480 /* If this is a nested if, rewrite the CC registers that are available to
5481 include the ones that can be rewritten, to increase the chance of being
5482 able to allocate a paired CC/CR register combination. */
5483 if (ce_info->pass > 1)
5485 for (j = CC_FIRST; j <= CC_LAST; j++)
5486 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5487 SET_HARD_REG_BIT (tmp_reg->regs, j);
5489 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5495 fprintf (dump_file, "Available GPRs: ");
5497 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5498 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5500 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5501 if (++num_gprs > GPR_TEMP_NUM+2)
5505 fprintf (dump_file, "%s\nAvailable CRs: ",
5506 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5508 for (j = CR_FIRST; j <= CR_LAST; j++)
5509 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5510 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5512 fputs ("\n", dump_file);
5514 if (ce_info->pass > 1)
5516 fprintf (dump_file, "Modifiable CCs: ");
5517 for (j = CC_FIRST; j <= CC_LAST; j++)
5518 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5519 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5521 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5522 frv_ifcvt.num_nested_cond_exec);
5526 /* Allocate the appropriate temporary condition code register. Try to
5527 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5528 that conditional cmp's can be done. */
5529 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5531 cr_class = ICR_REGS;
5532 cc_class = ICC_REGS;
5533 cc_first = ICC_FIRST;
5536 else if (mode == CC_FPmode)
5538 cr_class = FCR_REGS;
5539 cc_class = FCC_REGS;
5540 cc_first = FCC_FIRST;
5545 cc_first = cc_last = 0;
5546 cr_class = cc_class = NO_REGS;
5549 cc = XEXP (true_expr, 0);
5550 nested_cc = cr = NULL_RTX;
5551 if (cc_class != NO_REGS)
5553 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5554 so we can execute a csubcc/caddcc/cfcmps instruction. */
5557 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5559 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5561 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5562 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5564 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5565 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5568 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5569 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5579 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5586 "Will use %s for conditional execution, %s for nested comparisons\n",
5587 reg_names[ REGNO (cr)],
5588 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5590 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5591 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5592 bit being true. We don't do this for floating point, because of NaNs. */
5593 code = GET_CODE (true_expr);
5594 if (GET_MODE (cc) != CC_FPmode)
5596 code = reverse_condition (code);
5606 check_insn = gen_rtx_SET (VOIDmode, cr,
5607 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5609 /* Record the check insn to be inserted later. */
5610 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5612 /* Update the tests. */
5613 frv_ifcvt.cr_reg = cr;
5614 frv_ifcvt.nested_cc_reg = nested_cc;
5615 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5616 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5619 /* Fail, don't do this conditional execution. */
5622 *p_false = NULL_RTX;
5624 fprintf (dump_file, "Disabling this conditional execution.\n");
5630 /* A C expression to modify the code described by the conditional if
5631 information CE_INFO, for the basic block BB, possibly updating the tests in
5632 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5633 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5634 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5636 /* p_true and p_false are given expressions of the form:
5638 (and (eq:CC_CCR (reg:CC_CCR)
5644 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5649 rtx old_true = XEXP (*p_true, 0);
5650 rtx old_false = XEXP (*p_false, 0);
5651 rtx true_expr = XEXP (*p_true, 1);
5652 rtx false_expr = XEXP (*p_false, 1);
5655 rtx cr = XEXP (old_true, 0);
5657 rtx new_cr = NULL_RTX;
5658 rtx *p_new_cr = (rtx *)0;
5662 enum reg_class cr_class;
5663 enum machine_mode mode = GET_MODE (true_expr);
5664 rtx (*logical_func)(rtx, rtx, rtx);
5666 if (TARGET_DEBUG_COND_EXEC)
5669 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5670 ce_info->and_and_p ? "&&" : "||");
5672 debug_rtx (*p_true);
5674 fputs ("\nfalse insn:\n", stderr);
5675 debug_rtx (*p_false);
5678 if (!TARGET_MULTI_CE)
5681 if (GET_CODE (cr) != REG)
5684 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5686 cr_class = ICR_REGS;
5687 p_new_cr = &frv_ifcvt.extra_int_cr;
5689 else if (mode == CC_FPmode)
5691 cr_class = FCR_REGS;
5692 p_new_cr = &frv_ifcvt.extra_fp_cr;
5697 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5698 more &&/|| tests. */
5702 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5703 CC_CCRmode, TRUE, TRUE);
5708 if (ce_info->and_and_p)
5710 old_test = old_false;
5711 test_expr = true_expr;
5712 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5713 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5714 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5718 old_test = old_false;
5719 test_expr = false_expr;
5720 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5721 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5722 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5725 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5726 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5728 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5730 /* Now add the conditional check insn. */
5731 cc = XEXP (test_expr, 0);
5732 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5733 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5735 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5737 /* Add the new check insn to the list of check insns that need to be
5739 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5741 if (TARGET_DEBUG_COND_EXEC)
5743 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5746 debug_rtx (*p_true);
5748 fputs ("\nfalse insn:\n", stderr);
5749 debug_rtx (*p_false);
5755 *p_true = *p_false = NULL_RTX;
5757 /* If we allocated a CR register, release it. */
5760 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5761 *p_new_cr = NULL_RTX;
5764 if (TARGET_DEBUG_COND_EXEC)
5765 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5771 /* Return a register which will be loaded with a value if an IF block is
5772 converted to conditional execution. This is used to rewrite instructions
5773 that use constants to ones that just use registers. */
5776 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5778 int num_alloc = frv_ifcvt.cur_scratch_regs;
5782 /* We know gr0 == 0, so replace any errant uses. */
5783 if (value == const0_rtx)
5784 return gen_rtx_REG (SImode, GPR_FIRST);
5786 /* First search all registers currently loaded to see if we have an
5787 applicable constant. */
5788 if (CONSTANT_P (value)
5789 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5791 for (i = 0; i < num_alloc; i++)
5793 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5794 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5798 /* Have we exhausted the number of registers available? */
5799 if (num_alloc >= GPR_TEMP_NUM)
5802 fprintf (dump_file, "Too many temporary registers allocated\n");
5807 /* Allocate the new register. */
5808 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5812 fputs ("Could not find a scratch register\n", dump_file);
5817 frv_ifcvt.cur_scratch_regs++;
5818 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5822 if (GET_CODE (value) == CONST_INT)
5823 fprintf (dump_file, "Register %s will hold %ld\n",
5824 reg_names[ REGNO (reg)], (long)INTVAL (value));
5826 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5827 fprintf (dump_file, "Register %s will hold LR\n",
5828 reg_names[ REGNO (reg)]);
5831 fprintf (dump_file, "Register %s will hold a saved value\n",
5832 reg_names[ REGNO (reg)]);
5839 /* Update a MEM used in conditional code that might contain an offset to put
5840 the offset into a scratch register, so that the conditional load/store
5841 operations can be used. This function returns the original pointer if the
5842 MEM is valid to use in conditional code, NULL if we can't load up the offset
5843 into a temporary register, or the new MEM if we were successful. */
5846 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5848 rtx addr = XEXP (mem, 0);
5850 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
5852 if (GET_CODE (addr) == PLUS)
5854 rtx addr_op0 = XEXP (addr, 0);
5855 rtx addr_op1 = XEXP (addr, 1);
5857 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5859 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5863 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5870 else if (CONSTANT_P (addr))
5871 addr = frv_ifcvt_load_value (addr, insn);
5876 if (addr == NULL_RTX)
5879 else if (XEXP (mem, 0) != addr)
5880 return change_address (mem, mode, addr);
5887 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5888 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5891 single_set_pattern (rtx pattern)
5896 if (GET_CODE (pattern) == COND_EXEC)
5897 pattern = COND_EXEC_CODE (pattern);
5899 if (GET_CODE (pattern) == SET)
5902 else if (GET_CODE (pattern) == PARALLEL)
5904 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5906 rtx sub = XVECEXP (pattern, 0, i);
5908 switch (GET_CODE (sub))
5932 /* A C expression to modify the code described by the conditional if
5933 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5934 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5935 insn cannot be converted to be executed conditionally. */
5938 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5942 rtx orig_ce_pattern = pattern;
5948 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5950 test = COND_EXEC_TEST (pattern);
5951 if (GET_CODE (test) == AND)
5953 rtx cr = frv_ifcvt.cr_reg;
5956 op0 = XEXP (test, 0);
5957 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5960 op1 = XEXP (test, 1);
5961 test_reg = XEXP (op1, 0);
5962 if (GET_CODE (test_reg) != REG)
5965 /* Is this the first nested if block in this sequence? If so, generate
5966 an andcr or andncr. */
5967 if (! frv_ifcvt.last_nested_if_cr)
5971 frv_ifcvt.last_nested_if_cr = test_reg;
5972 if (GET_CODE (op0) == NE)
5973 and_op = gen_andcr (test_reg, cr, test_reg);
5975 and_op = gen_andncr (test_reg, cr, test_reg);
5977 frv_ifcvt_add_insn (and_op, insn, TRUE);
5980 /* If this isn't the first statement in the nested if sequence, see if we
5981 are dealing with the same register. */
5982 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5985 COND_EXEC_TEST (pattern) = test = op1;
5988 /* If this isn't a nested if, reset state variables. */
5991 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5994 set = single_set_pattern (pattern);
5997 rtx dest = SET_DEST (set);
5998 rtx src = SET_SRC (set);
5999 enum machine_mode mode = GET_MODE (dest);
6001 /* Check for normal binary operators. */
6002 if (mode == SImode && ARITHMETIC_P (src))
6004 op0 = XEXP (src, 0);
6005 op1 = XEXP (src, 1);
6007 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6009 op1 = frv_ifcvt_load_value (op1, insn);
6011 COND_EXEC_CODE (pattern)
6012 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6020 /* For multiply by a constant, we need to handle the sign extending
6021 correctly. Add a USE of the value after the multiply to prevent flow
6022 from cratering because only one register out of the two were used. */
6023 else if (mode == DImode && GET_CODE (src) == MULT)
6025 op0 = XEXP (src, 0);
6026 op1 = XEXP (src, 1);
6027 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6029 op1 = frv_ifcvt_load_value (op1, insn);
6032 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6033 COND_EXEC_CODE (pattern)
6034 = gen_rtx_SET (VOIDmode, dest,
6035 gen_rtx_MULT (DImode, op0, op1));
6041 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6044 /* If we are just loading a constant created for a nested conditional
6045 execution statement, just load the constant without any conditional
6046 execution, since we know that the constant will not interfere with any
6048 else if (frv_ifcvt.scratch_insns_bitmap
6049 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6051 && REG_P (SET_DEST (set))
6052 /* We must not unconditionally set a scratch reg chosen
6053 for a nested if-converted block if its incoming
6054 value from the TEST block (or the result of the THEN
6055 branch) could/should propagate to the JOIN block.
6056 It suffices to test whether the register is live at
6057 the JOIN point: if it's live there, we can infer
6058 that we set it in the former JOIN block of the
6059 nested if-converted block (otherwise it wouldn't
6060 have been available as a scratch register), and it
6061 is either propagated through or set in the other
6062 conditional block. It's probably not worth trying
6063 to catch the latter case, and it could actually
6064 limit scheduling of the combined block quite
6067 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6068 REGNO (SET_DEST (set))))
6069 /* Similarly, we must not unconditionally set a reg
6070 used as scratch in the THEN branch if the same reg
6071 is live in the ELSE branch. */
6072 && (! ce_info->else_bb
6073 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6074 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6075 REGNO (SET_DEST (set))))))
6078 else if (mode == QImode || mode == HImode || mode == SImode
6081 int changed_p = FALSE;
6083 /* Check for just loading up a constant */
6084 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6086 src = frv_ifcvt_load_value (src, insn);
6093 /* See if we need to fix up stores */
6094 if (GET_CODE (dest) == MEM)
6096 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6101 else if (new_mem != dest)
6108 /* See if we need to fix up loads */
6109 if (GET_CODE (src) == MEM)
6111 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6116 else if (new_mem != src)
6123 /* If either src or destination changed, redo SET. */
6125 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6128 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6129 rewriting the CC register to be the same as the paired CC/CR register
6131 else if (mode == CC_CCRmode && COMPARISON_P (src))
6133 int regno = REGNO (XEXP (src, 0));
6136 if (ce_info->pass > 1
6137 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6138 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6140 src = gen_rtx_fmt_ee (GET_CODE (src),
6142 frv_ifcvt.nested_cc_reg,
6146 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6147 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6150 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6151 else if (ce_info->pass > 1
6152 && GET_CODE (dest) == REG
6153 && CC_P (REGNO (dest))
6154 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6155 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6157 && GET_CODE (src) == COMPARE)
6159 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6160 COND_EXEC_CODE (pattern)
6161 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6165 if (TARGET_DEBUG_COND_EXEC)
6167 rtx orig_pattern = PATTERN (insn);
6169 PATTERN (insn) = pattern;
6171 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6175 PATTERN (insn) = orig_pattern;
6181 if (TARGET_DEBUG_COND_EXEC)
6183 rtx orig_pattern = PATTERN (insn);
6185 PATTERN (insn) = orig_ce_pattern;
6187 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6191 PATTERN (insn) = orig_pattern;
6198 /* A C expression to perform any final machine dependent modifications in
6199 converting code to conditional execution in the code described by the
6200 conditional if information CE_INFO. */
6203 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6207 rtx p = frv_ifcvt.added_insns_list;
6210 /* Loop inserting the check insns. The last check insn is the first test,
6211 and is the appropriate place to insert constants. */
6216 rtx check_and_insert_insns = XEXP (p, 0);
6219 check_insn = XEXP (check_and_insert_insns, 0);
6220 existing_insn = XEXP (check_and_insert_insns, 1);
6223 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6224 the existing insn, otherwise it is to be inserted AFTER. */
6225 if (check_and_insert_insns->jump)
6227 emit_insn_before (check_insn, existing_insn);
6228 check_and_insert_insns->jump = 0;
6231 emit_insn_after (check_insn, existing_insn);
6233 free_EXPR_LIST_node (check_and_insert_insns);
6234 free_EXPR_LIST_node (old_p);
6236 while (p != NULL_RTX);
6238 /* Load up any constants needed into temp gprs */
6239 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6241 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6242 if (! frv_ifcvt.scratch_insns_bitmap)
6243 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6244 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6245 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6248 frv_ifcvt.added_insns_list = NULL_RTX;
6249 frv_ifcvt.cur_scratch_regs = 0;
6253 /* A C expression to cancel any machine dependent modifications in converting
6254 code to conditional execution in the code described by the conditional if
6255 information CE_INFO. */
6258 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6261 rtx p = frv_ifcvt.added_insns_list;
6263 /* Loop freeing up the EXPR_LIST's allocated. */
6264 while (p != NULL_RTX)
6266 rtx check_and_jump = XEXP (p, 0);
6270 free_EXPR_LIST_node (check_and_jump);
6271 free_EXPR_LIST_node (old_p);
6274 /* Release any temporary gprs allocated. */
6275 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6276 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6278 frv_ifcvt.added_insns_list = NULL_RTX;
6279 frv_ifcvt.cur_scratch_regs = 0;
6283 /* A C expression for the size in bytes of the trampoline, as an integer.
6287 setlo #0, <static_chain>
6289 sethi #0, <static_chain>
6290 jmpl @(gr0,<jmp_reg>) */
6293 frv_trampoline_size (void)
6296 /* Allocate room for the function descriptor and the lddi
6299 return 5 /* instructions */ * 4 /* instruction size. */;
6303 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6304 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6305 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6306 should be passed to the function when it is called.
6311 setlo #0, <static_chain>
6313 sethi #0, <static_chain>
6314 jmpl @(gr0,<jmp_reg>) */
6317 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6319 rtx sc_reg = force_reg (Pmode, static_chain);
6321 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6324 GEN_INT (frv_trampoline_size ()), SImode,
6330 /* Many machines have some registers that cannot be copied directly to or from
6331 memory or even from other types of registers. An example is the `MQ'
6332 register, which on most machines, can only be copied to or from general
6333 registers, but not memory. Some machines allow copying all registers to and
6334 from memory, but require a scratch register for stores to some memory
6335 locations (e.g., those with symbolic address on the RT, and those with
6336 certain symbolic address on the SPARC when compiling PIC). In some cases,
6337 both an intermediate and a scratch register are required.
6339 You should define these macros to indicate to the reload phase that it may
6340 need to allocate at least one register for a reload in addition to the
6341 register to contain the data. Specifically, if copying X to a register
6342 RCLASS in MODE requires an intermediate register, you should define
6343 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6344 whose registers can be used as intermediate registers or scratch registers.
6346 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6347 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6348 largest register class required. If the requirements for input and output
6349 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6350 instead of defining both macros identically.
6352 The values returned by these macros are often `GENERAL_REGS'. Return
6353 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6354 to or from a register of RCLASS in MODE without requiring a scratch register.
6355 Do not define this macro if it would always return `NO_REGS'.
6357 If a scratch register is required (either with or without an intermediate
6358 register), you should define patterns for `reload_inM' or `reload_outM', as
6359 required.. These patterns, which will normally be implemented with a
6360 `define_expand', should be similar to the `movM' patterns, except that
6361 operand 2 is the scratch register.
6363 Define constraints for the reload register and scratch register that contain
6364 a single register class. If the original reload register (whose class is
6365 RCLASS) can meet the constraint given in the pattern, the value returned by
6366 these macros is used for the class of the scratch register. Otherwise, two
6367 additional reload registers are required. Their classes are obtained from
6368 the constraints in the insn pattern.
6370 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6371 either be in a hard register or in memory. Use `true_regnum' to find out;
6372 it will return -1 if the pseudo is in memory and the hard register number if
6373 it is in a register.
6375 These macros should not be used in the case where a particular class of
6376 registers can only be copied to memory and not to another class of
6377 registers. In that case, secondary reload registers are not needed and
6378 would not be helpful. Instead, a stack location must be used to perform the
6379 copy and the `movM' pattern should use memory as an intermediate storage.
6380 This case often occurs between floating-point and general registers. */
6383 frv_secondary_reload_class (enum reg_class rclass,
6384 enum machine_mode mode ATTRIBUTE_UNUSED,
6395 /* Accumulators/Accumulator guard registers need to go through floating
6401 if (x && GET_CODE (x) == REG)
6403 int regno = REGNO (x);
6405 if (ACC_P (regno) || ACCG_P (regno))
6410 /* Nonzero constants should be loaded into an FPR through a GPR. */
6414 if (x && CONSTANT_P (x) && !ZERO_P (x))
6420 /* All of these types need gpr registers. */
6432 /* The accumulators need fpr registers. */
6444 /* This hook exists to catch the case where secondary_reload_class() is
6445 called from init_reg_autoinc() in regclass.c - before the reload optabs
6446 have been initialised. */
6449 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6450 enum machine_mode reload_mode,
6451 secondary_reload_info * sri)
6453 enum reg_class rclass = NO_REGS;
6455 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6457 sri->icode = sri->prev_sri->t_icode;
6461 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6463 if (rclass != NO_REGS)
6465 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6466 : reload_out_optab[(int) reload_mode]);
6469 /* This happens when then the reload_[in|out]_optabs have
6470 not been initialised. */
6471 sri->t_icode = CODE_FOR_nothing;
6476 /* Fall back to the default secondary reload handler. */
6477 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6481 /* A C expression whose value is nonzero if pseudos that have been assigned to
6482 registers of class RCLASS would likely be spilled because registers of RCLASS
6483 are needed for spill registers.
6485 The default value of this macro returns 1 if RCLASS has exactly one register
6486 and zero otherwise. On most machines, this default should be used. Only
6487 define this macro to some other expression if pseudo allocated by
6488 `local-alloc.c' end up in memory because their hard registers were needed
6489 for spill registers. If this macro returns nonzero for those classes, those
6490 pseudos will only be allocated by `global.c', which knows how to reallocate
6491 the pseudo to another register. If there would not be another register
6492 available for reallocation, you should not change the definition of this
6493 macro since the only effect of such a definition would be to slow down
6494 register allocation. */
6497 frv_class_likely_spilled_p (enum reg_class rclass)
6507 case FDPIC_FPTR_REGS:
6529 /* An expression for the alignment of a structure field FIELD if the
6530 alignment computed in the usual way is COMPUTED. GCC uses this
6531 value instead of the value in `BIGGEST_ALIGNMENT' or
6532 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6534 /* The definition type of the bit field data is either char, short, long or
6535 long long. The maximum bit size is the number of bits of its own type.
6537 The bit field data is assigned to a storage unit that has an adequate size
6538 for bit field data retention and is located at the smallest address.
6540 Consecutive bit field data are packed at consecutive bits having the same
6541 storage unit, with regard to the type, beginning with the MSB and continuing
6544 If a field to be assigned lies over a bit field type boundary, its
6545 assignment is completed by aligning it with a boundary suitable for the
6548 When a bit field having a bit length of 0 is declared, it is forcibly
6549 assigned to the next storage unit.
6562 &x 00000000 00000000 00000000 00000000
6565 &x+4 00000000 00000000 00000000 00000000
6568 &x+8 00000000 00000000 00000000 00000000
6571 &x+12 00000000 00000000 00000000 00000000
6577 frv_adjust_field_align (tree field, int computed)
6579 /* Make sure that the bitfield is not wider than the type. */
6580 if (DECL_BIT_FIELD (field)
6581 && !DECL_ARTIFICIAL (field))
6583 tree parent = DECL_CONTEXT (field);
6584 tree prev = NULL_TREE;
6587 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6589 if (TREE_CODE (cur) != FIELD_DECL)
6597 /* If this isn't a :0 field and if the previous element is a bitfield
6598 also, see if the type is different, if so, we will need to align the
6599 bit-field to the next boundary. */
6601 && ! DECL_PACKED (field)
6602 && ! integer_zerop (DECL_SIZE (field))
6603 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6605 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6606 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6607 computed = (prev_align > cur_align) ? prev_align : cur_align;
6615 /* A C expression that is nonzero if it is permissible to store a value of mode
6616 MODE in hard register number REGNO (or in several registers starting with
6617 that one). For a machine where all registers are equivalent, a suitable
6620 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6622 It is not necessary for this macro to check for the numbers of fixed
6623 registers, because the allocation mechanism considers them to be always
6626 On some machines, double-precision values must be kept in even/odd register
6627 pairs. The way to implement that is to define this macro to reject odd
6628 register numbers for such modes.
6630 The minimum requirement for a mode to be OK in a register is that the
6631 `movMODE' instruction pattern support moves between the register and any
6632 other hard register for which the mode is OK; and that moving a value into
6633 the register and back out not alter it.
6635 Since the same instruction used to move `SImode' will work for all narrower
6636 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6637 to distinguish between these modes, provided you define patterns `movhi',
6638 etc., to take advantage of this. This is useful because of the interaction
6639 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6640 all integer modes to be tieable.
6642 Many machines have special registers for floating point arithmetic. Often
6643 people assume that floating point machine modes are allowed only in floating
6644 point registers. This is not true. Any registers that can hold integers
6645 can safely *hold* a floating point machine mode, whether or not floating
6646 arithmetic can be done on it in those registers. Integer move instructions
6647 can be used to move the values.
6649 On some machines, though, the converse is true: fixed-point machine modes
6650 may not go in floating registers. This is true if the floating registers
6651 normalize any value stored in them, because storing a non-floating value
6652 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6653 fixed-point machine modes in floating registers. But if the floating
6654 registers do not automatically normalize, if you can store any bit pattern
6655 in one and retrieve it unchanged without a trap, then any machine mode may
6656 go in a floating register, so you can define this macro to say so.
6658 The primary significance of special floating registers is rather that they
6659 are the registers acceptable in floating point arithmetic instructions.
6660 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6661 writing the proper constraints for those instructions.
6663 On some machines, the floating registers are especially slow to access, so
6664 that it is better to store a value in a stack frame than in such a register
6665 if floating point arithmetic is not being done. As long as the floating
6666 registers are not in class `GENERAL_REGS', they will not be used unless some
6667 pattern's constraint asks for one. */
6670 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6680 return ICC_P (regno) || GPR_P (regno);
6683 return CR_P (regno) || GPR_P (regno);
6686 return FCC_P (regno) || GPR_P (regno);
6692 /* Set BASE to the first register in REGNO's class. Set MASK to the
6693 bits that must be clear in (REGNO - BASE) for the register to be
6695 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6699 /* ACCGs store one byte. Two-byte quantities must start in
6700 even-numbered registers, four-byte ones in registers whose
6701 numbers are divisible by four, and so on. */
6703 mask = GET_MODE_SIZE (mode) - 1;
6707 /* The other registers store one word. */
6708 if (GPR_P (regno) || regno == AP_FIRST)
6711 else if (FPR_P (regno))
6714 else if (ACC_P (regno))
6717 else if (SPR_P (regno))
6718 return mode == SImode;
6720 /* Fill in the table. */
6724 /* Anything smaller than an SI is OK in any word-sized register. */
6725 if (GET_MODE_SIZE (mode) < 4)
6728 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6730 return (((regno - base) & mask) == 0);
6737 /* A C expression for the number of consecutive hard registers, starting at
6738 register number REGNO, required to hold a value of mode MODE.
6740 On a machine where all registers are exactly one word, a suitable definition
6743 #define HARD_REGNO_NREGS(REGNO, MODE) \
6744 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6745 / UNITS_PER_WORD)) */
6747 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6748 that we can build the appropriate instructions to properly reload the
6749 values. Also, make the byte-sized accumulator guards use one guard
6753 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6756 return GET_MODE_SIZE (mode);
6758 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6762 /* A C expression for the maximum number of consecutive registers of
6763 class RCLASS needed to hold a value of mode MODE.
6765 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6766 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6767 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6769 This macro helps control the handling of multiple-word values in
6772 This declaration is required. */
6775 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6777 if (rclass == ACCG_REGS)
6778 /* An N-byte value requires N accumulator guards. */
6779 return GET_MODE_SIZE (mode);
6781 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6785 /* A C expression that is nonzero if X is a legitimate constant for an
6786 immediate operand on the target machine. You can assume that X satisfies
6787 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6788 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6791 frv_legitimate_constant_p (rtx x)
6793 enum machine_mode mode = GET_MODE (x);
6795 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6796 means that the move expanders will be expected to deal with most
6797 kinds of constant, regardless of what we return here.
6799 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6800 a constant can be entered into reg_equiv_constant[]. If we return true,
6801 reload can create new instances of the constant whenever it likes.
6803 The idea is therefore to accept as many constants as possible (to give
6804 reload more freedom) while rejecting constants that can only be created
6805 at certain times. In particular, anything with a symbolic component will
6806 require use of the pseudo FDPIC register, which is only available before
6809 return LEGITIMATE_PIC_OPERAND_P (x);
6811 /* All of the integer constants are ok. */
6812 if (GET_CODE (x) != CONST_DOUBLE)
6815 /* double integer constants are ok. */
6816 if (mode == VOIDmode || mode == DImode)
6819 /* 0 is always ok. */
6820 if (x == CONST0_RTX (mode))
6823 /* If floating point is just emulated, allow any constant, since it will be
6824 constructed in the GPRs. */
6825 if (!TARGET_HAS_FPRS)
6828 if (mode == DFmode && !TARGET_DOUBLE)
6831 /* Otherwise store the constant away and do a load. */
6835 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6836 CC_NZ for comparisons against zero in which a single Z or N flag test
6837 is enough, CC_UNS for other unsigned comparisons, and CC for other
6838 signed comparisons. */
6841 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6843 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6852 return y == const0_rtx ? CC_NZmode : CCmode;
6858 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6865 /* A C expression for the cost of moving data from a register in class FROM to
6866 one in class TO. The classes are expressed using the enumeration values
6867 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6868 interpreted relative to that.
6870 It is not required that the cost always equal 2 when FROM is the same as TO;
6871 on some machines it is expensive to move between registers if they are not
6874 If reload sees an insn consisting of a single `set' between two hard
6875 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6876 value of 2, reload does not check to ensure that the constraints of the insn
6877 are met. Setting a cost of other than 2 will allow reload to verify that
6878 the constraints are met. You should do this if the `movM' pattern's
6879 constraints do not allow such copying. */
6881 #define HIGH_COST 40
6882 #define MEDIUM_COST 3
6886 frv_register_move_cost (enum reg_class from, enum reg_class to)
6970 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6971 use ".picptr" to generate safe relocations for PIC code. We also
6972 need a fixup entry for aligned (non-debugging) code. */
6975 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6977 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6979 if (GET_CODE (value) == CONST
6980 || GET_CODE (value) == SYMBOL_REF
6981 || GET_CODE (value) == LABEL_REF)
6983 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6984 && SYMBOL_REF_FUNCTION_P (value))
6986 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6987 output_addr_const (asm_out_file, value);
6988 fputs (")\n", asm_out_file);
6991 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6992 && frv_function_symbol_referenced_p (value))
6994 if (aligned_p && !TARGET_FDPIC)
6996 static int label_num = 0;
7000 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7001 p = (* targetm.strip_name_encoding) (buf);
7003 fprintf (asm_out_file, "%s:\n", p);
7004 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7005 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7006 fprintf (asm_out_file, "\t.previous\n");
7008 assemble_integer_with_op ("\t.picptr\t", value);
7013 /* We've set the unaligned SI op to NULL, so we always have to
7014 handle the unaligned case here. */
7015 assemble_integer_with_op ("\t.4byte\t", value);
7019 return default_assemble_integer (value, size, aligned_p);
7022 /* Function to set up the backend function structure. */
7024 static struct machine_function *
7025 frv_init_machine_status (void)
7027 return GGC_CNEW (struct machine_function);
7030 /* Implement TARGET_SCHED_ISSUE_RATE. */
7033 frv_issue_rate (void)
7038 switch (frv_cpu_type)
7042 case FRV_CPU_SIMPLE:
7050 case FRV_CPU_GENERIC:
7052 case FRV_CPU_TOMCAT:
7060 /* A for_each_rtx callback. If X refers to an accumulator, return
7061 ACC_GROUP_ODD if the bit 2 of the register number is set and
7062 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7066 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7070 if (ACC_P (REGNO (*x)))
7071 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7072 if (ACCG_P (REGNO (*x)))
7073 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7078 /* Return the value of INSN's acc_group attribute. */
7081 frv_acc_group (rtx insn)
7083 /* This distinction only applies to the FR550 packing constraints. */
7084 if (frv_cpu_type != FRV_CPU_FR550)
7085 return ACC_GROUP_NONE;
7086 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7089 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7090 INSN will try to claim first. Since this value depends only on the
7091 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7094 frv_insn_unit (rtx insn)
7096 enum attr_type type;
7098 type = get_attr_type (insn);
7099 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7101 /* We haven't seen this type of instruction before. */
7105 /* Issue the instruction on its own to see which unit it prefers. */
7106 state = alloca (state_size ());
7107 state_reset (state);
7108 state_transition (state, insn);
7110 /* Find out which unit was taken. */
7111 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7112 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7115 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7117 frv_type_to_unit[type] = unit;
7119 return frv_type_to_unit[type];
7122 /* Return true if INSN issues to a branch unit. */
7125 frv_issues_to_branch_unit_p (rtx insn)
7127 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7130 /* The current state of the packing pass, implemented by frv_pack_insns. */
7132 /* The state of the pipeline DFA. */
7135 /* Which hardware registers are set within the current packet,
7136 and the conditions under which they are set. */
7137 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7139 /* The memory locations that have been modified so far in this
7140 packet. MEM is the memref and COND is the regstate_t condition
7141 under which it is set. */
7147 /* The number of valid entries in MEMS. The value is larger than
7148 ARRAY_SIZE (mems) if there were too many mems to record. */
7149 unsigned int num_mems;
7151 /* The maximum number of instructions that can be packed together. */
7152 unsigned int issue_rate;
7154 /* The instructions in the packet, partitioned into groups. */
7155 struct frv_packet_group {
7156 /* How many instructions in the packet belong to this group. */
7157 unsigned int num_insns;
7159 /* A list of the instructions that belong to this group, in the order
7160 they appear in the rtl stream. */
7161 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7163 /* The contents of INSNS after they have been sorted into the correct
7164 assembly-language order. Element X issues to unit X. The list may
7165 contain extra nops. */
7166 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7168 /* The member of frv_nops[] to use in sorted[]. */
7170 } groups[NUM_GROUPS];
7172 /* The instructions that make up the current packet. */
7173 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7174 unsigned int num_insns;
7177 /* Return the regstate_t flags for the given COND_EXEC condition.
7178 Abort if the condition isn't in the right form. */
7181 frv_cond_flags (rtx cond)
7183 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7184 && GET_CODE (XEXP (cond, 0)) == REG
7185 && CR_P (REGNO (XEXP (cond, 0)))
7186 && XEXP (cond, 1) == const0_rtx);
7187 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7188 | (GET_CODE (cond) == NE
7190 : REGSTATE_IF_FALSE));
7194 /* Return true if something accessed under condition COND2 can
7195 conflict with something written under condition COND1. */
7198 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7200 /* If either reference was unconditional, we have a conflict. */
7201 if ((cond1 & REGSTATE_IF_EITHER) == 0
7202 || (cond2 & REGSTATE_IF_EITHER) == 0)
7205 /* The references might conflict if they were controlled by
7207 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7210 /* They definitely conflict if they are controlled by the
7212 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7219 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7220 the current packet. DATA points to a regstate_t that describes the
7221 condition under which *X might be set or used. */
7224 frv_registers_conflict_p_1 (rtx *x, void *data)
7226 unsigned int regno, i;
7229 cond = *(regstate_t *) data;
7231 if (GET_CODE (*x) == REG)
7232 FOR_EACH_REGNO (regno, *x)
7233 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7234 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7237 if (GET_CODE (*x) == MEM)
7239 /* If we ran out of memory slots, assume a conflict. */
7240 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7243 /* Check for output or true dependencies with earlier MEMs. */
7244 for (i = 0; i < frv_packet.num_mems; i++)
7245 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7247 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7251 if (output_dependence (frv_packet.mems[i].mem, *x))
7256 /* The return values of calls aren't significant: they describe
7257 the effect of the call as a whole, not of the insn itself. */
7258 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7260 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7265 /* Check subexpressions. */
7270 /* Return true if something in X might depend on an instruction
7271 in the current packet. */
7274 frv_registers_conflict_p (rtx x)
7279 if (GET_CODE (x) == COND_EXEC)
7281 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7284 flags |= frv_cond_flags (XEXP (x, 0));
7287 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7291 /* A note_stores callback. DATA points to the regstate_t condition
7292 under which X is modified. Update FRV_PACKET accordingly. */
7295 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7299 if (GET_CODE (x) == REG)
7300 FOR_EACH_REGNO (regno, x)
7301 frv_packet.regstate[regno] |= *(regstate_t *) data;
7303 if (GET_CODE (x) == MEM)
7305 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7307 frv_packet.mems[frv_packet.num_mems].mem = x;
7308 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7310 frv_packet.num_mems++;
7315 /* Update the register state information for an instruction whose
7319 frv_registers_update (rtx x)
7323 flags = REGSTATE_MODIFIED;
7324 if (GET_CODE (x) == COND_EXEC)
7326 flags |= frv_cond_flags (XEXP (x, 0));
7329 note_stores (x, frv_registers_update_1, &flags);
7333 /* Initialize frv_packet for the start of a new packet. */
7336 frv_start_packet (void)
7338 enum frv_insn_group group;
7340 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7341 frv_packet.num_mems = 0;
7342 frv_packet.num_insns = 0;
7343 for (group = 0; group < NUM_GROUPS; group++)
7344 frv_packet.groups[group].num_insns = 0;
7348 /* Likewise for the start of a new basic block. */
7351 frv_start_packet_block (void)
7353 state_reset (frv_packet.dfa_state);
7354 frv_start_packet ();
7358 /* Finish the current packet, if any, and start a new one. Call
7359 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7362 frv_finish_packet (void (*handle_packet) (void))
7364 if (frv_packet.num_insns > 0)
7367 state_transition (frv_packet.dfa_state, 0);
7368 frv_start_packet ();
7373 /* Return true if INSN can be added to the current packet. Update
7374 the DFA state on success. */
7377 frv_pack_insn_p (rtx insn)
7379 /* See if the packet is already as long as it can be. */
7380 if (frv_packet.num_insns == frv_packet.issue_rate)
7383 /* If the scheduler thought that an instruction should start a packet,
7384 it's usually a good idea to believe it. It knows much more about
7385 the latencies than we do.
7387 There are some exceptions though:
7389 - Conditional instructions are scheduled on the assumption that
7390 they will be executed. This is usually a good thing, since it
7391 tends to avoid unnecessary stalls in the conditional code.
7392 But we want to pack conditional instructions as tightly as
7393 possible, in order to optimize the case where they aren't
7396 - The scheduler will always put branches on their own, even
7397 if there's no real dependency.
7399 - There's no point putting a call in its own packet unless
7401 if (frv_packet.num_insns > 0
7402 && GET_CODE (insn) == INSN
7403 && GET_MODE (insn) == TImode
7404 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7407 /* Check for register conflicts. Don't do this for setlo since any
7408 conflict will be with the partnering sethi, with which it can
7410 if (get_attr_type (insn) != TYPE_SETLO)
7411 if (frv_registers_conflict_p (PATTERN (insn)))
7414 return state_transition (frv_packet.dfa_state, insn) < 0;
7418 /* Add instruction INSN to the current packet. */
7421 frv_add_insn_to_packet (rtx insn)
7423 struct frv_packet_group *packet_group;
7425 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7426 packet_group->insns[packet_group->num_insns++] = insn;
7427 frv_packet.insns[frv_packet.num_insns++] = insn;
7429 frv_registers_update (PATTERN (insn));
7433 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7434 packet ends in a branch or call, insert the nop before it, otherwise
7438 frv_insert_nop_in_packet (rtx insn)
7440 struct frv_packet_group *packet_group;
7443 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7444 last = frv_packet.insns[frv_packet.num_insns - 1];
7445 if (GET_CODE (last) != INSN)
7447 insn = emit_insn_before (PATTERN (insn), last);
7448 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7449 frv_packet.insns[frv_packet.num_insns++] = last;
7453 insn = emit_insn_after (PATTERN (insn), last);
7454 frv_packet.insns[frv_packet.num_insns++] = insn;
7456 packet_group->insns[packet_group->num_insns++] = insn;
7460 /* If packing is enabled, divide the instructions into packets and
7461 return true. Call HANDLE_PACKET for each complete packet. */
7464 frv_for_each_packet (void (*handle_packet) (void))
7466 rtx insn, next_insn;
7468 frv_packet.issue_rate = frv_issue_rate ();
7470 /* Early exit if we don't want to pack insns. */
7472 || !flag_schedule_insns_after_reload
7473 || !TARGET_VLIW_BRANCH
7474 || frv_packet.issue_rate == 1)
7477 /* Set up the initial packing state. */
7479 frv_packet.dfa_state = alloca (state_size ());
7481 frv_start_packet_block ();
7482 for (insn = get_insns (); insn != 0; insn = next_insn)
7487 code = GET_CODE (insn);
7488 next_insn = NEXT_INSN (insn);
7490 if (code == CODE_LABEL)
7492 frv_finish_packet (handle_packet);
7493 frv_start_packet_block ();
7497 switch (GET_CODE (PATTERN (insn)))
7506 /* Calls mustn't be packed on a TOMCAT. */
7507 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7508 frv_finish_packet (handle_packet);
7510 /* Since the last instruction in a packet determines the EH
7511 region, any exception-throwing instruction must come at
7512 the end of reordered packet. Insns that issue to a
7513 branch unit are bound to come last; for others it's
7514 too hard to predict. */
7515 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7516 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7517 frv_finish_packet (handle_packet);
7519 /* Finish the current packet if we can't add INSN to it.
7520 Simulate cycles until INSN is ready to issue. */
7521 if (!frv_pack_insn_p (insn))
7523 frv_finish_packet (handle_packet);
7524 while (!frv_pack_insn_p (insn))
7525 state_transition (frv_packet.dfa_state, 0);
7528 /* Add the instruction to the packet. */
7529 frv_add_insn_to_packet (insn);
7531 /* Calls and jumps end a packet, as do insns that throw
7533 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7534 frv_finish_packet (handle_packet);
7538 frv_finish_packet (handle_packet);
7543 /* Subroutine of frv_sort_insn_group. We are trying to sort
7544 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7545 language order. We have already picked a new position for
7546 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7547 These instructions will occupy elements [0, LOWER_SLOT) and
7548 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7549 the DFA state after issuing these instructions.
7551 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7552 of the unused instructions. Return true if one such permutation gives
7553 a valid ordering, leaving the successful permutation in sorted[].
7554 Do not modify sorted[] until a valid permutation is found. */
7557 frv_sort_insn_group_1 (enum frv_insn_group group,
7558 unsigned int lower_slot, unsigned int upper_slot,
7559 unsigned int issued, unsigned int num_insns,
7562 struct frv_packet_group *packet_group;
7568 /* Early success if we've filled all the slots. */
7569 if (lower_slot == upper_slot)
7572 packet_group = &frv_packet.groups[group];
7573 dfa_size = state_size ();
7574 test_state = alloca (dfa_size);
7576 /* Try issuing each unused instruction. */
7577 for (i = num_insns - 1; i + 1 != 0; i--)
7578 if (~issued & (1 << i))
7580 insn = packet_group->sorted[i];
7581 memcpy (test_state, state, dfa_size);
7582 if (state_transition (test_state, insn) < 0
7583 && cpu_unit_reservation_p (test_state,
7584 NTH_UNIT (group, upper_slot - 1))
7585 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7586 issued | (1 << i), num_insns,
7589 packet_group->sorted[upper_slot - 1] = insn;
7597 /* Compare two instructions by their frv_insn_unit. */
7600 frv_compare_insns (const void *first, const void *second)
7602 const rtx *const insn1 = (rtx const *) first,
7603 *const insn2 = (rtx const *) second;
7604 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7607 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7608 and sort it into assembly language order. See frv.md for a description of
7612 frv_sort_insn_group (enum frv_insn_group group)
7614 struct frv_packet_group *packet_group;
7615 unsigned int first, i, nop, max_unit, num_slots;
7616 state_t state, test_state;
7619 packet_group = &frv_packet.groups[group];
7621 /* Assume no nop is needed. */
7622 packet_group->nop = 0;
7624 if (packet_group->num_insns == 0)
7627 /* Copy insns[] to sorted[]. */
7628 memcpy (packet_group->sorted, packet_group->insns,
7629 sizeof (rtx) * packet_group->num_insns);
7631 /* Sort sorted[] by the unit that each insn tries to take first. */
7632 if (packet_group->num_insns > 1)
7633 qsort (packet_group->sorted, packet_group->num_insns,
7634 sizeof (rtx), frv_compare_insns);
7636 /* That's always enough for branch and control insns. */
7637 if (group == GROUP_B || group == GROUP_C)
7640 dfa_size = state_size ();
7641 state = alloca (dfa_size);
7642 test_state = alloca (dfa_size);
7644 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7645 consecutively and such that the DFA takes unit X when sorted[X]
7646 is added. Set STATE to the new DFA state. */
7647 state_reset (test_state);
7648 for (first = 0; first < packet_group->num_insns; first++)
7650 memcpy (state, test_state, dfa_size);
7651 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7652 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7656 /* If all the instructions issued in ascending order, we're done. */
7657 if (first == packet_group->num_insns)
7660 /* Add nops to the end of sorted[] and try each permutation until
7661 we find one that works. */
7662 for (nop = 0; nop < frv_num_nops; nop++)
7664 max_unit = frv_insn_unit (frv_nops[nop]);
7665 if (frv_unit_groups[max_unit] == group)
7667 packet_group->nop = frv_nops[nop];
7668 num_slots = UNIT_NUMBER (max_unit) + 1;
7669 for (i = packet_group->num_insns; i < num_slots; i++)
7670 packet_group->sorted[i] = frv_nops[nop];
7671 if (frv_sort_insn_group_1 (group, first, num_slots,
7672 (1 << first) - 1, num_slots, state))
7679 /* Sort the current packet into assembly-language order. Set packing
7680 flags as appropriate. */
7683 frv_reorder_packet (void)
7685 unsigned int cursor[NUM_GROUPS];
7686 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7687 unsigned int unit, to, from;
7688 enum frv_insn_group group;
7689 struct frv_packet_group *packet_group;
7691 /* First sort each group individually. */
7692 for (group = 0; group < NUM_GROUPS; group++)
7695 frv_sort_insn_group (group);
7698 /* Go through the unit template and try add an instruction from
7699 that unit's group. */
7701 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7703 group = frv_unit_groups[unit];
7704 packet_group = &frv_packet.groups[group];
7705 if (cursor[group] < packet_group->num_insns)
7707 /* frv_reorg should have added nops for us. */
7708 gcc_assert (packet_group->sorted[cursor[group]]
7709 != packet_group->nop);
7710 insns[to++] = packet_group->sorted[cursor[group]++];
7714 gcc_assert (to == frv_packet.num_insns);
7716 /* Clear the last instruction's packing flag, thus marking the end of
7717 a packet. Reorder the other instructions relative to it. */
7718 CLEAR_PACKING_FLAG (insns[to - 1]);
7719 for (from = 0; from < to - 1; from++)
7721 remove_insn (insns[from]);
7722 add_insn_before (insns[from], insns[to - 1], NULL);
7723 SET_PACKING_FLAG (insns[from]);
7728 /* Divide instructions into packets. Reorder the contents of each
7729 packet so that they are in the correct assembly-language order.
7731 Since this pass can change the raw meaning of the rtl stream, it must
7732 only be called at the last minute, just before the instructions are
7736 frv_pack_insns (void)
7738 if (frv_for_each_packet (frv_reorder_packet))
7739 frv_insn_packing_flag = 0;
7741 frv_insn_packing_flag = -1;
7744 /* See whether we need to add nops to group GROUP in order to
7745 make a valid packet. */
7748 frv_fill_unused_units (enum frv_insn_group group)
7750 unsigned int non_nops, nops, i;
7751 struct frv_packet_group *packet_group;
7753 packet_group = &frv_packet.groups[group];
7755 /* Sort the instructions into assembly-language order.
7756 Use nops to fill slots that are otherwise unused. */
7757 frv_sort_insn_group (group);
7759 /* See how many nops are needed before the final useful instruction. */
7761 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7762 while (packet_group->sorted[i++] == packet_group->nop)
7765 /* Insert that many nops into the instruction stream. */
7767 frv_insert_nop_in_packet (packet_group->nop);
7770 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7773 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7775 if (io1->const_address != 0 && io2->const_address != 0)
7776 return io1->const_address == io2->const_address;
7778 if (io1->var_address != 0 && io2->var_address != 0)
7779 return rtx_equal_p (io1->var_address, io2->var_address);
7784 /* Return true if operations IO1 and IO2 are guaranteed to complete
7788 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7790 /* The order of writes is always preserved. */
7791 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7794 /* The order of reads isn't preserved. */
7795 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7798 /* One operation is a write and the other is (or could be) a read.
7799 The order is only guaranteed if the accesses are to the same
7801 return frv_same_doubleword_p (io1, io2);
7804 /* Generalize I/O operation X so that it covers both X and Y. */
7807 frv_io_union (struct frv_io *x, const struct frv_io *y)
7809 if (x->type != y->type)
7810 x->type = FRV_IO_UNKNOWN;
7811 if (!frv_same_doubleword_p (x, y))
7813 x->const_address = 0;
7818 /* Fill IO with information about the load or store associated with
7819 membar instruction INSN. */
7822 frv_extract_membar (struct frv_io *io, rtx insn)
7824 extract_insn (insn);
7825 io->type = INTVAL (recog_data.operand[2]);
7826 io->const_address = INTVAL (recog_data.operand[1]);
7827 io->var_address = XEXP (recog_data.operand[0], 0);
7830 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7831 if X is a register and *DATA depends on X. */
7834 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7836 rtx *other = (rtx *) data;
7838 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7842 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7843 Remove every modified register from the set. */
7846 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7848 HARD_REG_SET *set = (HARD_REG_SET *) data;
7852 FOR_EACH_REGNO (regno, x)
7853 CLEAR_HARD_REG_BIT (*set, regno);
7856 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7857 Add every register in *X to the set. */
7860 frv_io_handle_use_1 (rtx *x, void *data)
7862 HARD_REG_SET *set = (HARD_REG_SET *) data;
7866 FOR_EACH_REGNO (regno, *x)
7867 SET_HARD_REG_BIT (*set, regno);
7872 /* A note_stores callback that applies frv_io_handle_use_1 to an
7873 entire rhs value. */
7876 frv_io_handle_use (rtx *x, void *data)
7878 for_each_rtx (x, frv_io_handle_use_1, data);
7881 /* Go through block BB looking for membars to remove. There are two
7882 cases where intra-block analysis is enough:
7884 - a membar is redundant if it occurs between two consecutive I/O
7885 operations and if those operations are guaranteed to complete
7888 - a membar for a __builtin_read is redundant if the result is
7889 used before the next I/O operation is issued.
7891 If the last membar in the block could not be removed, and there
7892 are guaranteed to be no I/O operations between that membar and
7893 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7896 Describe the block's first I/O operation in *NEXT_IO. Describe
7897 an unknown operation if the block doesn't do any I/O. */
7900 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7903 HARD_REG_SET used_regs;
7904 rtx next_membar, set, insn;
7907 /* NEXT_IO is the next I/O operation to be performed after the current
7908 instruction. It starts off as being an unknown operation. */
7909 memset (next_io, 0, sizeof (*next_io));
7911 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7912 next_is_end_p = true;
7914 /* If the current instruction is a __builtin_read or __builtin_write,
7915 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7916 is null if the membar has already been deleted.
7918 Note that the initialization here should only be needed to
7919 suppress warnings. */
7922 /* USED_REGS is the set of registers that are used before the
7923 next I/O instruction. */
7924 CLEAR_HARD_REG_SET (used_regs);
7926 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7927 if (GET_CODE (insn) == CALL_INSN)
7929 /* We can't predict what a call will do to volatile memory. */
7930 memset (next_io, 0, sizeof (struct frv_io));
7931 next_is_end_p = false;
7932 CLEAR_HARD_REG_SET (used_regs);
7934 else if (INSN_P (insn))
7935 switch (recog_memoized (insn))
7937 case CODE_FOR_optional_membar_qi:
7938 case CODE_FOR_optional_membar_hi:
7939 case CODE_FOR_optional_membar_si:
7940 case CODE_FOR_optional_membar_di:
7944 /* Local information isn't enough to decide whether this
7945 membar is needed. Stash it away for later. */
7946 *last_membar = insn;
7947 frv_extract_membar (next_io, insn);
7948 next_is_end_p = false;
7952 /* Check whether the I/O operation before INSN could be
7953 reordered with one described by NEXT_IO. If it can't,
7954 INSN will not be needed. */
7955 struct frv_io prev_io;
7957 frv_extract_membar (&prev_io, insn);
7958 if (frv_io_fixed_order_p (&prev_io, next_io))
7962 ";; [Local] Removing membar %d since order"
7963 " of accesses is guaranteed\n",
7964 INSN_UID (next_membar));
7966 insn = NEXT_INSN (insn);
7967 delete_insn (next_membar);
7975 /* Invalidate NEXT_IO's address if it depends on something that
7976 is clobbered by INSN. */
7977 if (next_io->var_address)
7978 note_stores (PATTERN (insn), frv_io_check_address,
7979 &next_io->var_address);
7981 /* If the next membar is associated with a __builtin_read,
7982 see if INSN reads from that address. If it does, and if
7983 the destination register is used before the next I/O access,
7984 there is no need for the membar. */
7985 set = PATTERN (insn);
7986 if (next_io->type == FRV_IO_READ
7987 && next_io->var_address != 0
7989 && GET_CODE (set) == SET
7990 && GET_CODE (SET_DEST (set)) == REG
7991 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7995 src = SET_SRC (set);
7996 if (GET_CODE (src) == ZERO_EXTEND)
7997 src = XEXP (src, 0);
7999 if (GET_CODE (src) == MEM
8000 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8004 ";; [Local] Removing membar %d since the target"
8005 " of %d is used before the I/O operation\n",
8006 INSN_UID (next_membar), INSN_UID (insn));
8008 if (next_membar == *last_membar)
8011 delete_insn (next_membar);
8016 /* If INSN has volatile references, forget about any registers
8017 that are used after it. Otherwise forget about uses that
8018 are (or might be) defined by INSN. */
8019 if (volatile_refs_p (PATTERN (insn)))
8020 CLEAR_HARD_REG_SET (used_regs);
8022 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8024 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8029 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8030 FIRST_IO[X] describes the first operation performed by basic block X. */
8033 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8036 struct frv_io this_io, next_io;
8040 /* We need to keep the membar if there is an edge to the exit block. */
8041 FOR_EACH_EDGE (succ, ei, bb->succs)
8042 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8043 if (succ->dest == EXIT_BLOCK_PTR)
8046 /* Work out the union of all successor blocks. */
8047 ei = ei_start (bb->succs);
8048 ei_cond (ei, &succ);
8049 /* next_io = first_io[bb->succ->dest->index]; */
8050 next_io = first_io[succ->dest->index];
8051 ei = ei_start (bb->succs);
8052 if (ei_cond (ei, &succ))
8054 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8055 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8056 frv_io_union (&next_io, &first_io[succ->dest->index]);
8061 frv_extract_membar (&this_io, membar);
8062 if (frv_io_fixed_order_p (&this_io, &next_io))
8066 ";; [Global] Removing membar %d since order of accesses"
8067 " is guaranteed\n", INSN_UID (membar));
8069 delete_insn (membar);
8073 /* Remove redundant membars from the current function. */
8076 frv_optimize_membar (void)
8079 struct frv_io *first_io;
8082 compute_bb_for_insn ();
8083 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8084 last_membar = XCNEWVEC (rtx, last_basic_block);
8087 frv_optimize_membar_local (bb, &first_io[bb->index],
8088 &last_membar[bb->index]);
8091 if (last_membar[bb->index] != 0)
8092 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8098 /* Used by frv_reorg to keep track of the current packet's address. */
8099 static unsigned int frv_packet_address;
8101 /* If the current packet falls through to a label, try to pad the packet
8102 with nops in order to fit the label's alignment requirements. */
8105 frv_align_label (void)
8107 unsigned int alignment, target, nop;
8108 rtx x, last, barrier, label;
8110 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8111 maximum alignment of that packet, LABEL to the last label between
8112 the packets, and BARRIER to the last barrier. */
8113 last = frv_packet.insns[frv_packet.num_insns - 1];
8114 label = barrier = 0;
8116 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8120 unsigned int subalign = 1 << label_to_alignment (x);
8121 alignment = MAX (alignment, subalign);
8128 /* If -malign-labels, and the packet falls through to an unaligned
8129 label, try introducing a nop to align that label to 8 bytes. */
8130 if (TARGET_ALIGN_LABELS
8133 && frv_packet.num_insns < frv_packet.issue_rate)
8134 alignment = MAX (alignment, 8);
8136 /* Advance the address to the end of the current packet. */
8137 frv_packet_address += frv_packet.num_insns * 4;
8139 /* Work out the target address, after alignment. */
8140 target = (frv_packet_address + alignment - 1) & -alignment;
8142 /* If the packet falls through to the label, try to find an efficient
8143 padding sequence. */
8146 /* First try adding nops to the current packet. */
8147 for (nop = 0; nop < frv_num_nops; nop++)
8148 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8150 frv_insert_nop_in_packet (frv_nops[nop]);
8151 frv_packet_address += 4;
8154 /* If we still haven't reached the target, add some new packets that
8155 contain only nops. If there are two types of nop, insert an
8156 alternating sequence of frv_nops[0] and frv_nops[1], which will
8157 lead to packets like:
8164 etc. Just emit frv_nops[0] if that's the only nop we have. */
8165 last = frv_packet.insns[frv_packet.num_insns - 1];
8167 while (frv_packet_address < target)
8169 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8170 frv_packet_address += 4;
8171 if (frv_num_nops > 1)
8176 frv_packet_address = target;
8179 /* Subroutine of frv_reorg, called after each packet has been constructed
8183 frv_reorg_packet (void)
8185 frv_fill_unused_units (GROUP_I);
8186 frv_fill_unused_units (GROUP_FM);
8190 /* Add an instruction with pattern NOP to frv_nops[]. */
8193 frv_register_nop (rtx nop)
8195 nop = make_insn_raw (nop);
8196 NEXT_INSN (nop) = 0;
8197 PREV_INSN (nop) = 0;
8198 frv_nops[frv_num_nops++] = nop;
8201 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8202 into packets and check whether we need to insert nops in order to
8203 fulfill the processor's issue requirements. Also, if the user has
8204 requested a certain alignment for a label, try to meet that alignment
8205 by inserting nops in the previous packet. */
8210 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8211 frv_optimize_membar ();
8214 frv_register_nop (gen_nop ());
8216 frv_register_nop (gen_mnop ());
8217 if (TARGET_HARD_FLOAT)
8218 frv_register_nop (gen_fnop ());
8220 /* Estimate the length of each branch. Although this may change after
8221 we've inserted nops, it will only do so in big functions. */
8222 shorten_branches (get_insns ());
8224 frv_packet_address = 0;
8225 frv_for_each_packet (frv_reorg_packet);
8228 #define def_builtin(name, type, code) \
8229 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8231 struct builtin_description
8233 enum insn_code icode;
8235 enum frv_builtins code;
8236 enum rtx_code comparison;
8240 /* Media intrinsics that take a single, constant argument. */
8242 static struct builtin_description bdesc_set[] =
8244 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8247 /* Media intrinsics that take just one argument. */
8249 static struct builtin_description bdesc_1arg[] =
8251 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8252 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8253 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8254 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8255 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8256 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8259 /* Media intrinsics that take two arguments. */
8261 static struct builtin_description bdesc_2arg[] =
8263 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8264 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8265 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8266 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8267 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8268 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8269 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8270 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8271 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8272 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8273 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8274 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8275 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8276 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8277 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8278 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8279 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8280 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8281 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8282 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8283 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8284 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8285 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8286 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8287 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8288 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8289 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8292 /* Integer intrinsics that take two arguments and have no return value. */
8294 static struct builtin_description bdesc_int_void2arg[] =
8296 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8297 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8298 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8301 static struct builtin_description bdesc_prefetches[] =
8303 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8304 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8307 /* Media intrinsics that take two arguments, the first being an ACC number. */
8309 static struct builtin_description bdesc_cut[] =
8311 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8312 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8313 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8316 /* Two-argument media intrinsics with an immediate second argument. */
8318 static struct builtin_description bdesc_2argimm[] =
8320 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8321 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8322 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8323 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8324 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8325 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8326 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8327 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8328 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8329 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8330 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8331 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8332 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8333 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8334 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8335 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8336 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8339 /* Media intrinsics that take two arguments and return void, the first argument
8340 being a pointer to 4 words in memory. */
8342 static struct builtin_description bdesc_void2arg[] =
8344 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8345 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8348 /* Media intrinsics that take three arguments, the first being a const_int that
8349 denotes an accumulator, and that return void. */
8351 static struct builtin_description bdesc_void3arg[] =
8353 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8354 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8355 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8356 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8357 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8358 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8359 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8360 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8361 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8362 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8363 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8364 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8365 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8366 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8367 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8368 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8369 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8370 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8371 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8372 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8373 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8374 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8375 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8376 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8377 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8380 /* Media intrinsics that take two accumulator numbers as argument and
8383 static struct builtin_description bdesc_voidacc[] =
8385 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8386 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8387 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8388 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8389 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8390 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8393 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8394 a normal move and the ICODE is for the membar. */
8396 static struct builtin_description bdesc_loads[] =
8398 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8399 FRV_BUILTIN_READ8, 0, 0 },
8400 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8401 FRV_BUILTIN_READ16, 0, 0 },
8402 { CODE_FOR_optional_membar_si, "__builtin_read32",
8403 FRV_BUILTIN_READ32, 0, 0 },
8404 { CODE_FOR_optional_membar_di, "__builtin_read64",
8405 FRV_BUILTIN_READ64, 0, 0 }
8408 /* Likewise stores. */
8410 static struct builtin_description bdesc_stores[] =
8412 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8413 FRV_BUILTIN_WRITE8, 0, 0 },
8414 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8415 FRV_BUILTIN_WRITE16, 0, 0 },
8416 { CODE_FOR_optional_membar_si, "__builtin_write32",
8417 FRV_BUILTIN_WRITE32, 0, 0 },
8418 { CODE_FOR_optional_membar_di, "__builtin_write64",
8419 FRV_BUILTIN_WRITE64, 0, 0 },
8422 /* Initialize media builtins. */
8425 frv_init_builtins (void)
8427 tree endlink = void_list_node;
8428 tree accumulator = integer_type_node;
8429 tree integer = integer_type_node;
8430 tree voidt = void_type_node;
8431 tree uhalf = short_unsigned_type_node;
8432 tree sword1 = long_integer_type_node;
8433 tree uword1 = long_unsigned_type_node;
8434 tree sword2 = long_long_integer_type_node;
8435 tree uword2 = long_long_unsigned_type_node;
8436 tree uword4 = build_pointer_type (uword1);
8437 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8438 tree ubyte = unsigned_char_type_node;
8439 tree iacc = integer_type_node;
8441 #define UNARY(RET, T1) \
8442 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8444 #define BINARY(RET, T1, T2) \
8445 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8446 tree_cons (NULL_TREE, T2, endlink)))
8448 #define TRINARY(RET, T1, T2, T3) \
8449 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8450 tree_cons (NULL_TREE, T2, \
8451 tree_cons (NULL_TREE, T3, endlink))))
8453 #define QUAD(RET, T1, T2, T3, T4) \
8454 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8455 tree_cons (NULL_TREE, T2, \
8456 tree_cons (NULL_TREE, T3, \
8457 tree_cons (NULL_TREE, T4, endlink)))))
8459 tree void_ftype_void = build_function_type (voidt, endlink);
8461 tree void_ftype_acc = UNARY (voidt, accumulator);
8462 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8463 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8464 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8465 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8466 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8467 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8468 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8469 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8471 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8472 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8473 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8474 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8475 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8476 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8477 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8478 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8479 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8480 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8481 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8483 tree sw1_ftype_int = UNARY (sword1, integer);
8484 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8485 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8487 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8488 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8489 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8490 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8491 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8492 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8494 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8495 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8496 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8497 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8498 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8499 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8500 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8501 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8502 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8503 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8504 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8505 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8506 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8507 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8508 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8509 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8510 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8512 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8513 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8514 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8515 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8516 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8517 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8518 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8519 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8520 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8521 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8522 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8523 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8524 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8525 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8526 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8527 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8528 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8529 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8530 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8531 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8532 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8533 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8534 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8535 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8536 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8537 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8538 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8539 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8540 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8541 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8542 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8543 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8544 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8545 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8546 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8547 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8548 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8549 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8550 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8551 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8552 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8553 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8554 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8555 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8556 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8557 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8558 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8559 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8560 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8561 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8562 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8563 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8564 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8565 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8566 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8567 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8568 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8569 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8570 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8571 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8572 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8573 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8574 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8575 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8576 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8577 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8578 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8579 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8580 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8581 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8582 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8583 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8584 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8585 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8586 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8587 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8588 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8589 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8590 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8591 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8592 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8593 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8594 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8595 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8596 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8597 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8598 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8599 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8600 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8601 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8602 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8603 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8604 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8605 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8606 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8607 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8608 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8609 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8610 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8611 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8612 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8613 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8614 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8615 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8616 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8617 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8618 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8619 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8621 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8622 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8623 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8624 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8632 /* Set the names for various arithmetic operations according to the
8635 frv_init_libfuncs (void)
8637 set_optab_libfunc (smod_optab, SImode, "__modi");
8638 set_optab_libfunc (umod_optab, SImode, "__umodi");
8640 set_optab_libfunc (add_optab, DImode, "__addll");
8641 set_optab_libfunc (sub_optab, DImode, "__subll");
8642 set_optab_libfunc (smul_optab, DImode, "__mulll");
8643 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8644 set_optab_libfunc (smod_optab, DImode, "__modll");
8645 set_optab_libfunc (umod_optab, DImode, "__umodll");
8646 set_optab_libfunc (and_optab, DImode, "__andll");
8647 set_optab_libfunc (ior_optab, DImode, "__orll");
8648 set_optab_libfunc (xor_optab, DImode, "__xorll");
8649 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8651 set_optab_libfunc (add_optab, SFmode, "__addf");
8652 set_optab_libfunc (sub_optab, SFmode, "__subf");
8653 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8654 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8656 set_optab_libfunc (add_optab, DFmode, "__addd");
8657 set_optab_libfunc (sub_optab, DFmode, "__subd");
8658 set_optab_libfunc (smul_optab, DFmode, "__muld");
8659 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8661 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8662 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8664 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8665 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8666 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8667 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8669 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8670 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8671 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8672 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8674 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8675 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8676 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8677 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8680 /* Convert an integer constant to an accumulator register. ICODE is the
8681 code of the target instruction, OPNUM is the number of the
8682 accumulator operand and OPVAL is the constant integer. Try both
8683 ACC and ACCG registers; only report an error if neither fit the
8687 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8692 /* ACCs and ACCGs are implicit global registers if media intrinsics
8693 are being used. We set up this lazily to avoid creating lots of
8694 unnecessary call_insn rtl in non-media code. */
8695 for (i = 0; i <= ACC_MASK; i++)
8696 if ((i & ACC_MASK) == i)
8697 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8699 if (GET_CODE (opval) != CONST_INT)
8701 error ("accumulator is not a constant integer");
8704 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8706 error ("accumulator number is out of bounds");
8710 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8711 ACC_FIRST + INTVAL (opval));
8712 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8713 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8715 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8717 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8723 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8726 static enum machine_mode
8727 frv_matching_accg_mode (enum machine_mode mode)
8745 /* Given that a __builtin_read or __builtin_write function is accessing
8746 address ADDRESS, return the value that should be used as operand 1
8750 frv_io_address_cookie (rtx address)
8752 return (GET_CODE (address) == CONST_INT
8753 ? GEN_INT (INTVAL (address) / 8 * 8)
8757 /* Return the accumulator guard that should be paired with accumulator
8758 register ACC. The mode of the returned register is in the same
8759 class as ACC, but is four times smaller. */
8762 frv_matching_accg_for_acc (rtx acc)
8764 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8765 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8768 /* Read the requested argument from the call EXP given by INDEX.
8769 Return the value as an rtx. */
8772 frv_read_argument (tree exp, unsigned int index)
8774 return expand_expr (CALL_EXPR_ARG (exp, index),
8775 NULL_RTX, VOIDmode, 0);
8778 /* Like frv_read_argument, but interpret the argument as the number
8779 of an IACC register and return a (reg:MODE ...) rtx for it. */
8782 frv_read_iacc_argument (enum machine_mode mode, tree call,
8788 op = frv_read_argument (call, index);
8789 if (GET_CODE (op) != CONST_INT
8791 || INTVAL (op) > IACC_LAST - IACC_FIRST
8792 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8794 error ("invalid IACC argument");
8798 /* IACCs are implicit global registers. We set up this lazily to
8799 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8801 regno = INTVAL (op) + IACC_FIRST;
8802 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8803 global_regs[regno + i] = 1;
8805 return gen_rtx_REG (mode, regno);
8808 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8809 The instruction should require a constant operand of some sort. The
8810 function prints an error if OPVAL is not valid. */
8813 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8815 if (GET_CODE (opval) != CONST_INT)
8817 error ("%qs expects a constant argument", insn_data[icode].name);
8820 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8822 error ("constant argument out of range for %qs", insn_data[icode].name);
8828 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8829 if it's not null, has the right mode, and satisfies operand 0's
8833 frv_legitimize_target (enum insn_code icode, rtx target)
8835 enum machine_mode mode = insn_data[icode].operand[0].mode;
8838 || GET_MODE (target) != mode
8839 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8840 return gen_reg_rtx (mode);
8845 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8846 check whether ARG satisfies the operand's constraints. If it doesn't,
8847 copy ARG to a temporary register and return that. Otherwise return ARG
8851 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8853 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8855 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8858 return copy_to_mode_reg (mode, arg);
8861 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8864 frv_volatile_memref (enum machine_mode mode, rtx arg)
8868 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8869 MEM_VOLATILE_P (mem) = 1;
8873 /* Expand builtins that take a single, constant argument. At the moment,
8874 only MHDSETS falls into this category. */
8877 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8880 rtx op0 = frv_read_argument (call, 0);
8882 if (! frv_check_constant_argument (icode, 1, op0))
8885 target = frv_legitimize_target (icode, target);
8886 pat = GEN_FCN (icode) (target, op0);
8894 /* Expand builtins that take one operand. */
8897 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8900 rtx op0 = frv_read_argument (call, 0);
8902 target = frv_legitimize_target (icode, target);
8903 op0 = frv_legitimize_argument (icode, 1, op0);
8904 pat = GEN_FCN (icode) (target, op0);
8912 /* Expand builtins that take two operands. */
8915 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8918 rtx op0 = frv_read_argument (call, 0);
8919 rtx op1 = frv_read_argument (call, 1);
8921 target = frv_legitimize_target (icode, target);
8922 op0 = frv_legitimize_argument (icode, 1, op0);
8923 op1 = frv_legitimize_argument (icode, 2, op1);
8924 pat = GEN_FCN (icode) (target, op0, op1);
8932 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8936 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8939 rtx op0 = frv_read_argument (call, 0);
8940 rtx op1 = frv_read_argument (call, 1);
8943 target = frv_legitimize_target (icode, target);
8944 op0 = frv_int_to_acc (icode, 1, op0);
8948 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8950 if (! frv_check_constant_argument (icode, 2, op1))
8954 op1 = frv_legitimize_argument (icode, 2, op1);
8956 op2 = frv_matching_accg_for_acc (op0);
8957 pat = GEN_FCN (icode) (target, op0, op1, op2);
8965 /* Expand builtins that take two operands and the second is immediate. */
8968 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8971 rtx op0 = frv_read_argument (call, 0);
8972 rtx op1 = frv_read_argument (call, 1);
8974 if (! frv_check_constant_argument (icode, 2, op1))
8977 target = frv_legitimize_target (icode, target);
8978 op0 = frv_legitimize_argument (icode, 1, op0);
8979 pat = GEN_FCN (icode) (target, op0, op1);
8987 /* Expand builtins that take two operands, the first operand being a pointer to
8988 ints and return void. */
8991 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8994 rtx op0 = frv_read_argument (call, 0);
8995 rtx op1 = frv_read_argument (call, 1);
8996 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8999 if (GET_CODE (op0) != MEM)
9003 if (! offsettable_address_p (0, mode0, op0))
9005 reg = gen_reg_rtx (Pmode);
9006 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9009 op0 = gen_rtx_MEM (SImode, reg);
9012 addr = XEXP (op0, 0);
9013 if (! offsettable_address_p (0, mode0, addr))
9014 addr = copy_to_mode_reg (Pmode, op0);
9016 op0 = change_address (op0, V4SImode, addr);
9017 op1 = frv_legitimize_argument (icode, 1, op1);
9018 pat = GEN_FCN (icode) (op0, op1);
9026 /* Expand builtins that take two long operands and return void. */
9029 frv_expand_int_void2arg (enum insn_code icode, tree call)
9032 rtx op0 = frv_read_argument (call, 0);
9033 rtx op1 = frv_read_argument (call, 1);
9035 op0 = frv_legitimize_argument (icode, 1, op0);
9036 op1 = frv_legitimize_argument (icode, 1, op1);
9037 pat = GEN_FCN (icode) (op0, op1);
9045 /* Expand prefetch builtins. These take a single address as argument. */
9048 frv_expand_prefetches (enum insn_code icode, tree call)
9051 rtx op0 = frv_read_argument (call, 0);
9053 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9061 /* Expand builtins that take three operands and return void. The first
9062 argument must be a constant that describes a pair or quad accumulators. A
9063 fourth argument is created that is the accumulator guard register that
9064 corresponds to the accumulator. */
9067 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9070 rtx op0 = frv_read_argument (call, 0);
9071 rtx op1 = frv_read_argument (call, 1);
9072 rtx op2 = frv_read_argument (call, 2);
9075 op0 = frv_int_to_acc (icode, 0, op0);
9079 op1 = frv_legitimize_argument (icode, 1, op1);
9080 op2 = frv_legitimize_argument (icode, 2, op2);
9081 op3 = frv_matching_accg_for_acc (op0);
9082 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9090 /* Expand builtins that perform accumulator-to-accumulator operations.
9091 These builtins take two accumulator numbers as argument and return
9095 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9098 rtx op0 = frv_read_argument (call, 0);
9099 rtx op1 = frv_read_argument (call, 1);
9103 op0 = frv_int_to_acc (icode, 0, op0);
9107 op1 = frv_int_to_acc (icode, 1, op1);
9111 op2 = frv_matching_accg_for_acc (op0);
9112 op3 = frv_matching_accg_for_acc (op1);
9113 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9121 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9122 membar and TARGET_MODE is the mode that the loaded value should have. */
9125 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9126 tree call, rtx target)
9128 rtx op0 = frv_read_argument (call, 0);
9129 rtx cookie = frv_io_address_cookie (op0);
9131 if (target == 0 || !REG_P (target))
9132 target = gen_reg_rtx (target_mode);
9133 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9134 convert_move (target, op0, 1);
9135 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9136 cfun->machine->has_membar_p = 1;
9140 /* Likewise __builtin_write* functions. */
9143 frv_expand_store_builtin (enum insn_code icode, tree call)
9145 rtx op0 = frv_read_argument (call, 0);
9146 rtx op1 = frv_read_argument (call, 1);
9147 rtx cookie = frv_io_address_cookie (op0);
9149 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9150 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9151 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9152 cfun->machine->has_membar_p = 1;
9156 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9157 each argument forms one word of the two double-word input registers.
9158 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9159 to put the return value. */
9162 frv_expand_mdpackh_builtin (tree call, rtx target)
9164 enum insn_code icode = CODE_FOR_mdpackh;
9166 rtx arg1 = frv_read_argument (call, 0);
9167 rtx arg2 = frv_read_argument (call, 1);
9168 rtx arg3 = frv_read_argument (call, 2);
9169 rtx arg4 = frv_read_argument (call, 3);
9171 target = frv_legitimize_target (icode, target);
9172 op0 = gen_reg_rtx (DImode);
9173 op1 = gen_reg_rtx (DImode);
9175 /* The high half of each word is not explicitly initialized, so indicate
9176 that the input operands are not live before this point. */
9180 /* Move each argument into the low half of its associated input word. */
9181 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9182 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9183 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9184 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9186 pat = GEN_FCN (icode) (target, op0, op1);
9194 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9195 number as argument. */
9198 frv_expand_mclracc_builtin (tree call)
9200 enum insn_code icode = CODE_FOR_mclracc;
9202 rtx op0 = frv_read_argument (call, 0);
9204 op0 = frv_int_to_acc (icode, 0, op0);
9208 pat = GEN_FCN (icode) (op0);
9215 /* Expand builtins that take no arguments. */
9218 frv_expand_noargs_builtin (enum insn_code icode)
9220 rtx pat = GEN_FCN (icode) (const0_rtx);
9227 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9228 number or accumulator guard number as argument and return an SI integer. */
9231 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9234 rtx target = gen_reg_rtx (SImode);
9235 rtx op0 = frv_read_argument (call, 0);
9237 op0 = frv_int_to_acc (icode, 1, op0);
9241 pat = GEN_FCN (icode) (target, op0);
9249 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9250 accumulator guard as their first argument and an SImode value as their
9254 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9257 rtx op0 = frv_read_argument (call, 0);
9258 rtx op1 = frv_read_argument (call, 1);
9260 op0 = frv_int_to_acc (icode, 0, op0);
9264 op1 = frv_legitimize_argument (icode, 1, op1);
9265 pat = GEN_FCN (icode) (op0, op1);
9272 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9273 to move DImode values into and out of IACC0. */
9276 frv_split_iacc_move (rtx dest, rtx src)
9278 enum machine_mode inner;
9281 inner = GET_MODE (dest);
9282 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9283 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9284 simplify_gen_subreg (SImode, src, inner, i));
9287 /* Expand builtins. */
9290 frv_expand_builtin (tree exp,
9292 rtx subtarget ATTRIBUTE_UNUSED,
9293 enum machine_mode mode ATTRIBUTE_UNUSED,
9294 int ignore ATTRIBUTE_UNUSED)
9296 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9297 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9299 struct builtin_description *d;
9301 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9303 error ("media functions are not available unless -mmedia is used");
9309 case FRV_BUILTIN_MCOP1:
9310 case FRV_BUILTIN_MCOP2:
9311 case FRV_BUILTIN_MDUNPACKH:
9312 case FRV_BUILTIN_MBTOHE:
9313 if (! TARGET_MEDIA_REV1)
9315 error ("this media function is only available on the fr500");
9320 case FRV_BUILTIN_MQXMACHS:
9321 case FRV_BUILTIN_MQXMACXHS:
9322 case FRV_BUILTIN_MQMACXHS:
9323 case FRV_BUILTIN_MADDACCS:
9324 case FRV_BUILTIN_MSUBACCS:
9325 case FRV_BUILTIN_MASACCS:
9326 case FRV_BUILTIN_MDADDACCS:
9327 case FRV_BUILTIN_MDSUBACCS:
9328 case FRV_BUILTIN_MDASACCS:
9329 case FRV_BUILTIN_MABSHS:
9330 case FRV_BUILTIN_MDROTLI:
9331 case FRV_BUILTIN_MCPLHI:
9332 case FRV_BUILTIN_MCPLI:
9333 case FRV_BUILTIN_MDCUTSSI:
9334 case FRV_BUILTIN_MQSATHS:
9335 case FRV_BUILTIN_MHSETLOS:
9336 case FRV_BUILTIN_MHSETLOH:
9337 case FRV_BUILTIN_MHSETHIS:
9338 case FRV_BUILTIN_MHSETHIH:
9339 case FRV_BUILTIN_MHDSETS:
9340 case FRV_BUILTIN_MHDSETH:
9341 if (! TARGET_MEDIA_REV2)
9343 error ("this media function is only available on the fr400"
9349 case FRV_BUILTIN_SMASS:
9350 case FRV_BUILTIN_SMSSS:
9351 case FRV_BUILTIN_SMU:
9352 case FRV_BUILTIN_ADDSS:
9353 case FRV_BUILTIN_SUBSS:
9354 case FRV_BUILTIN_SLASS:
9355 case FRV_BUILTIN_SCUTSS:
9356 case FRV_BUILTIN_IACCreadll:
9357 case FRV_BUILTIN_IACCreadl:
9358 case FRV_BUILTIN_IACCsetll:
9359 case FRV_BUILTIN_IACCsetl:
9360 if (!TARGET_FR405_BUILTINS)
9362 error ("this builtin function is only available"
9363 " on the fr405 and fr450");
9368 case FRV_BUILTIN_PREFETCH:
9369 if (!TARGET_FR500_FR550_BUILTINS)
9371 error ("this builtin function is only available on the fr500"
9377 case FRV_BUILTIN_MQLCLRHS:
9378 case FRV_BUILTIN_MQLMTHS:
9379 case FRV_BUILTIN_MQSLLHI:
9380 case FRV_BUILTIN_MQSRAHI:
9381 if (!TARGET_MEDIA_FR450)
9383 error ("this builtin function is only available on the fr450");
9392 /* Expand unique builtins. */
9396 case FRV_BUILTIN_MTRAP:
9397 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9399 case FRV_BUILTIN_MCLRACC:
9400 return frv_expand_mclracc_builtin (exp);
9402 case FRV_BUILTIN_MCLRACCA:
9404 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9406 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9408 case FRV_BUILTIN_MRDACC:
9409 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9411 case FRV_BUILTIN_MRDACCG:
9412 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9414 case FRV_BUILTIN_MWTACC:
9415 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9417 case FRV_BUILTIN_MWTACCG:
9418 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9420 case FRV_BUILTIN_MDPACKH:
9421 return frv_expand_mdpackh_builtin (exp, target);
9423 case FRV_BUILTIN_IACCreadll:
9425 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9426 if (target == 0 || !REG_P (target))
9427 target = gen_reg_rtx (DImode);
9428 frv_split_iacc_move (target, src);
9432 case FRV_BUILTIN_IACCreadl:
9433 return frv_read_iacc_argument (SImode, exp, 0);
9435 case FRV_BUILTIN_IACCsetll:
9437 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9438 rtx src = frv_read_argument (exp, 1);
9439 frv_split_iacc_move (dest, force_reg (DImode, src));
9443 case FRV_BUILTIN_IACCsetl:
9445 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9446 rtx src = frv_read_argument (exp, 1);
9447 emit_move_insn (dest, force_reg (SImode, src));
9455 /* Expand groups of builtins. */
9457 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9458 if (d->code == fcode)
9459 return frv_expand_set_builtin (d->icode, exp, target);
9461 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9462 if (d->code == fcode)
9463 return frv_expand_unop_builtin (d->icode, exp, target);
9465 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9466 if (d->code == fcode)
9467 return frv_expand_binop_builtin (d->icode, exp, target);
9469 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9470 if (d->code == fcode)
9471 return frv_expand_cut_builtin (d->icode, exp, target);
9473 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9474 if (d->code == fcode)
9475 return frv_expand_binopimm_builtin (d->icode, exp, target);
9477 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9478 if (d->code == fcode)
9479 return frv_expand_voidbinop_builtin (d->icode, exp);
9481 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9482 if (d->code == fcode)
9483 return frv_expand_voidtriop_builtin (d->icode, exp);
9485 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9486 if (d->code == fcode)
9487 return frv_expand_voidaccop_builtin (d->icode, exp);
9489 for (i = 0, d = bdesc_int_void2arg;
9490 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9491 if (d->code == fcode)
9492 return frv_expand_int_void2arg (d->icode, exp);
9494 for (i = 0, d = bdesc_prefetches;
9495 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9496 if (d->code == fcode)
9497 return frv_expand_prefetches (d->icode, exp);
9499 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9500 if (d->code == fcode)
9501 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9504 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9505 if (d->code == fcode)
9506 return frv_expand_store_builtin (d->icode, exp);
9512 frv_in_small_data_p (const_tree decl)
9515 const_tree section_name;
9517 /* Don't apply the -G flag to internal compiler structures. We
9518 should leave such structures in the main data section, partly
9519 for efficiency and partly because the size of some of them
9520 (such as C++ typeinfos) is not known until later. */
9521 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9524 /* If we already know which section the decl should be in, see if
9525 it's a small data section. */
9526 section_name = DECL_SECTION_NAME (decl);
9529 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9530 if (frv_string_begins_with (section_name, ".sdata"))
9532 if (frv_string_begins_with (section_name, ".sbss"))
9537 size = int_size_in_bytes (TREE_TYPE (decl));
9538 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9545 frv_rtx_costs (rtx x,
9546 int code ATTRIBUTE_UNUSED,
9547 int outer_code ATTRIBUTE_UNUSED,
9549 bool speed ATTRIBUTE_UNUSED)
9551 if (outer_code == MEM)
9553 /* Don't differentiate between memory addresses. All the ones
9554 we accept have equal cost. */
9555 *total = COSTS_N_INSNS (0);
9562 /* Make 12-bit integers really cheap. */
9563 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9574 *total = COSTS_N_INSNS (2);
9588 if (GET_MODE (x) == SImode)
9589 *total = COSTS_N_INSNS (1);
9590 else if (GET_MODE (x) == DImode)
9591 *total = COSTS_N_INSNS (2);
9593 *total = COSTS_N_INSNS (3);
9597 if (GET_MODE (x) == SImode)
9598 *total = COSTS_N_INSNS (2);
9600 *total = COSTS_N_INSNS (6); /* guess */
9607 *total = COSTS_N_INSNS (18);
9611 *total = COSTS_N_INSNS (3);
9620 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9622 switch_to_section (ctors_section);
9623 assemble_align (POINTER_SIZE);
9626 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9631 assemble_integer_with_op ("\t.picptr\t", symbol);
9635 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9637 switch_to_section (dtors_section);
9638 assemble_align (POINTER_SIZE);
9641 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9646 assemble_integer_with_op ("\t.picptr\t", symbol);
9649 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9652 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9653 int incoming ATTRIBUTE_UNUSED)
9655 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9658 #define TLS_BIAS (2048 - 16)
9660 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9661 We need to emit DTP-relative relocations. */
9664 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9666 gcc_assert (size == 4);
9667 fputs ("\t.picptr\ttlsmoff(", file);
9668 /* We want the unbiased TLS offset, so add the bias to the
9669 expression, such that the implicit biasing cancels out. */
9670 output_addr_const (file, plus_constant (x, TLS_BIAS));