1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
46 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
47 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
49 static void d30v_add_gc_roots PARAMS ((void));
50 static void d30v_init_machine_status PARAMS ((struct function *));
51 static void d30v_mark_machine_status PARAMS ((struct function *));
52 static void d30v_free_machine_status PARAMS ((struct function *));
53 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
54 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
55 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
56 static int d30v_issue_rate PARAMS ((void));
58 /* Define the information needed to generate branch and scc insns. This is
59 stored from the compare operation. */
61 struct rtx_def *d30v_compare_op0;
62 struct rtx_def *d30v_compare_op1;
64 /* Cached value of d30v_stack_info */
65 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
67 /* Values of the -mbranch-cost=n string. */
68 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
69 const char *d30v_branch_cost_string = (const char *)0;
71 /* Values of the -mcond-exec=n string. */
72 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
73 const char *d30v_cond_exec_string = (const char *)0;
75 /* Whether or not a hard register can accept a register */
76 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
78 /* Whether to try and avoid moves between two different modes */
79 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
81 /* Map register number to smallest register class. */
82 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
84 /* Map class letter into register class */
85 enum reg_class reg_class_from_letter[256];
87 /* Initialize the GCC target structure. */
88 #undef TARGET_ASM_FUNCTION_PROLOGUE
89 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
90 #undef TARGET_ASM_FUNCTION_EPILOGUE
91 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
92 #undef TARGET_SCHED_ADJUST_COST
93 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
94 #undef TARGET_SCHED_ISSUE_RATE
95 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
97 struct gcc_target targetm = TARGET_INITIALIZER;
99 /* Sometimes certain combinations of command options do not make
100 sense on a particular target machine. You can define a macro
101 `OVERRIDE_OPTIONS' to take account of this. This macro, if
102 defined, is executed once just after all the command options have
105 Don't use this macro to turn on various extra optimizations for
106 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
112 enum machine_mode mode1, mode2;
114 /* Set up the branch cost information */
115 if (d30v_branch_cost_string)
116 d30v_branch_cost = atoi (d30v_branch_cost_string);
118 /* Set up max # instructions to use with conditional execution */
119 if (d30v_cond_exec_string)
120 d30v_cond_exec = atoi (d30v_cond_exec_string);
122 /* Setup hard_regno_mode_ok/modes_tieable_p */
123 for (mode1 = VOIDmode;
124 (int)mode1 < NUM_MACHINE_MODES;
125 mode1 = (enum machine_mode)((int)mode1 + 1))
127 int size = GET_MODE_SIZE (mode1);
128 int large_p = size > UNITS_PER_WORD;
129 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
131 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
133 if (mode1 == VOIDmode)
136 else if (GPR_P (regno))
141 ok_p = (((regno - GPR_FIRST) & 1) == 0);
144 else if (FLAG_P (regno))
145 ok_p = (mode1 == CCmode);
147 else if (CR_P (regno))
148 ok_p = int_p && !large_p;
150 else if (ACCUM_P (regno))
151 ok_p = (mode1 == DImode);
153 else if (SPECIAL_REG_P (regno))
154 ok_p = (mode1 == SImode);
159 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
162 /* A C expression that is nonzero if it is desirable to choose
163 register allocation so as to avoid move instructions between a
164 value of mode MODE1 and a value of mode MODE2.
166 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
167 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
168 MODE2)' must be zero. */
169 for (mode2 = VOIDmode;
170 (int)mode2 <= NUM_MACHINE_MODES;
171 mode2 = (enum machine_mode)((int)mode2 + 1))
177 else if (GET_MODE_CLASS (mode1) == MODE_INT
178 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
179 && GET_MODE_CLASS (mode2) == MODE_INT
180 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
187 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
192 for (mode1 = VOIDmode;
193 (int)mode1 < NUM_MACHINE_MODES;
194 mode1 = (enum machine_mode)((int)mode1 + 1))
196 for (mode2 = VOIDmode;
197 (int)mode2 <= NUM_MACHINE_MODES;
198 mode2 = (enum machine_mode)((int)mode2 + 1))
200 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
202 && (hard_regno_mode_ok[(int)mode1][regno]
203 != hard_regno_mode_ok[(int)mode2][regno]))
204 error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
205 reg_names[regno], GET_MODE_NAME (mode1),
206 GET_MODE_NAME (mode2));
211 /* A C expression whose value is a register class containing hard
212 register REGNO. In general there is more than one such class;
213 choose a class which is "minimal", meaning that no smaller class
214 also contains the register. */
215 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
217 enum reg_class class;
220 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
221 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
223 else if (regno == FLAG_F0)
226 else if (regno == FLAG_F1)
229 else if (FLAG_P (regno))
230 class = OTHER_FLAG_REGS;
232 else if (ACCUM_P (regno))
235 else if (regno == CR_RPT_C)
238 else if (CR_P (regno))
241 else if (SPECIAL_REG_P (regno))
247 regno_reg_class[regno] = class;
251 static const char *const names[] = REG_CLASS_NAMES;
252 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
253 for (mode1 = VOIDmode;
254 (int)mode1 < NUM_MACHINE_MODES;
255 mode1 = (enum machine_mode)((int)mode1 + 1))
257 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
258 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
260 fprintf (stderr, "\n");
265 /* A C expression which defines the machine-dependent operand
266 constraint letters for register classes. If CHAR is such a
267 letter, the value should be the register class corresponding to
268 it. Otherwise, the value should be `NO_REGS'. The register
269 letter `r', corresponding to class `GENERAL_REGS', will not be
270 passed to this macro; you do not need to handle it.
272 The following letters are unavailable, due to being used as
277 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
278 'Q', 'R', 'S', 'T', 'U'
280 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
282 for (i = 0; i < 256; i++)
283 reg_class_from_letter[i] = NO_REGS;
285 reg_class_from_letter['a'] = ACCUM_REGS;
286 reg_class_from_letter['b'] = BR_FLAG_REGS;
287 reg_class_from_letter['c'] = CR_REGS;
288 reg_class_from_letter['d'] = GPR_REGS;
289 reg_class_from_letter['e'] = EVEN_REGS;
290 reg_class_from_letter['f'] = FLAG_REGS;
291 reg_class_from_letter['l'] = REPEAT_REGS;
292 reg_class_from_letter['x'] = F0_REGS;
293 reg_class_from_letter['y'] = F1_REGS;
294 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
296 d30v_add_gc_roots ();
300 /* Return true if a memory operand is a short memory operand. */
303 short_memory_operand (op, mode)
305 enum machine_mode mode;
307 if (GET_CODE (op) != MEM)
310 if (GET_MODE (op) != mode && mode != VOIDmode)
313 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
317 /* Return true if a memory operand is a long operand. */
320 long_memory_operand (op, mode)
322 enum machine_mode mode;
324 if (GET_CODE (op) != MEM)
327 if (GET_MODE (op) != mode && mode != VOIDmode)
330 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
334 /* Return true if a memory operand is valid for the D30V. */
337 d30v_memory_operand (op, mode)
339 enum machine_mode mode;
341 if (GET_CODE (op) != MEM)
344 if (GET_MODE (op) != mode && mode != VOIDmode)
347 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
351 /* Return true if a memory operand uses a single register for the
355 single_reg_memory_operand (op, mode)
357 enum machine_mode mode;
361 if (GET_CODE (op) != MEM)
364 if (GET_MODE (op) != mode && mode != VOIDmode)
368 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
371 if (GET_CODE (addr) == SUBREG)
372 addr = SUBREG_REG (addr);
374 return (GET_CODE (addr) == REG);
377 /* Return true if a memory operand uses a constant address. */
380 const_addr_memory_operand (op, mode)
382 enum machine_mode mode;
384 if (GET_CODE (op) != MEM)
387 if (GET_MODE (op) != mode && mode != VOIDmode)
390 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
393 switch (GET_CODE (XEXP (op, 0)))
408 /* Return true if operand is a memory reference suitable for a call. */
411 call_operand (op, mode)
413 enum machine_mode mode;
415 if (GET_CODE (op) != MEM)
418 if (GET_MODE (op) != mode && mode != VOIDmode)
421 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
424 switch (GET_CODE (XEXP (op, 0)))
430 op = SUBREG_REG (op);
431 if (GET_CODE (op) != REG)
437 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
449 /* Return true if operand is a GPR register. */
452 gpr_operand (op, mode)
454 enum machine_mode mode;
456 if (GET_MODE (op) != mode && mode != VOIDmode)
459 if (GET_CODE (op) == SUBREG)
461 if (GET_CODE (SUBREG_REG (op)) != REG)
462 return register_operand (op, mode);
464 op = SUBREG_REG (op);
467 if (GET_CODE (op) != REG)
470 return GPR_OR_PSEUDO_P (REGNO (op));
473 /* Return true if operand is an accumulator register. */
476 accum_operand (op, mode)
478 enum machine_mode mode;
480 if (GET_MODE (op) != mode && mode != VOIDmode)
483 if (GET_CODE (op) == SUBREG)
485 if (GET_CODE (SUBREG_REG (op)) != REG)
486 return register_operand (op, mode);
488 op = SUBREG_REG (op);
491 if (GET_CODE (op) != REG)
494 return ACCUM_OR_PSEUDO_P (REGNO (op));
497 /* Return true if operand is a GPR or an accumulator register. */
500 gpr_or_accum_operand (op, mode)
502 enum machine_mode mode;
504 if (GET_MODE (op) != mode && mode != VOIDmode)
507 if (GET_CODE (op) == SUBREG)
509 if (GET_CODE (SUBREG_REG (op)) != REG)
510 return register_operand (op, mode);
512 op = SUBREG_REG (op);
515 if (GET_CODE (op) != REG)
518 if (ACCUM_P (REGNO (op)))
521 return GPR_OR_PSEUDO_P (REGNO (op));
524 /* Return true if operand is a CR register. */
527 cr_operand (op, mode)
529 enum machine_mode mode;
531 if (GET_MODE (op) != mode && mode != VOIDmode)
534 if (GET_CODE (op) == SUBREG)
536 if (GET_CODE (SUBREG_REG (op)) != REG)
537 return register_operand (op, mode);
539 op = SUBREG_REG (op);
542 if (GET_CODE (op) != REG)
545 return CR_OR_PSEUDO_P (REGNO (op));
548 /* Return true if operand is the repeat count register. */
551 repeat_operand (op, mode)
553 enum machine_mode mode;
555 if (GET_MODE (op) != mode && mode != VOIDmode)
558 if (GET_CODE (op) == SUBREG)
560 if (GET_CODE (SUBREG_REG (op)) != REG)
561 return register_operand (op, mode);
563 op = SUBREG_REG (op);
566 if (GET_CODE (op) != REG)
569 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
572 /* Return true if operand is a FLAG register. */
575 flag_operand (op, mode)
577 enum machine_mode mode;
579 if (GET_MODE (op) != mode && mode != VOIDmode)
582 if (GET_CODE (op) == SUBREG)
584 if (GET_CODE (SUBREG_REG (op)) != REG)
585 return register_operand (op, mode);
587 op = SUBREG_REG (op);
590 if (GET_CODE (op) != REG)
593 return FLAG_OR_PSEUDO_P (REGNO (op));
596 /* Return true if operand is either F0 or F1. */
599 br_flag_operand (op, mode)
601 enum machine_mode mode;
603 if (GET_MODE (op) != mode && mode != VOIDmode)
606 if (GET_CODE (op) == SUBREG)
608 if (GET_CODE (SUBREG_REG (op)) != REG)
609 return register_operand (op, mode);
611 op = SUBREG_REG (op);
614 if (GET_CODE (op) != REG)
617 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
620 /* Return true if operand is either F0/F1 or the constants 0/1. */
623 br_flag_or_constant_operand (op, mode)
625 enum machine_mode mode;
627 if (GET_MODE (op) != mode && mode != VOIDmode)
630 if (GET_CODE (op) == SUBREG)
632 if (GET_CODE (SUBREG_REG (op)) != REG)
633 return register_operand (op, mode);
635 op = SUBREG_REG (op);
638 if (GET_CODE (op) == CONST_INT)
639 return (INTVAL (op) == 0 || INTVAL (op) == 1);
641 if (GET_CODE (op) != REG)
644 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
647 /* Return true if operand is either F0 or F1, or a GPR register. */
650 gpr_or_br_flag_operand (op, mode)
652 enum machine_mode mode;
654 if (GET_MODE (op) != mode && mode != VOIDmode)
657 if (GET_CODE (op) == SUBREG)
659 if (GET_CODE (SUBREG_REG (op)) != REG)
660 return register_operand (op, mode);
662 op = SUBREG_REG (op);
665 if (GET_CODE (op) != REG)
668 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
671 /* Return true if operand is the F0 register. */
674 f0_operand (op, mode)
676 enum machine_mode mode;
678 if (GET_MODE (op) != mode && mode != VOIDmode)
681 if (GET_CODE (op) == SUBREG)
683 if (GET_CODE (SUBREG_REG (op)) != REG)
684 return register_operand (op, mode);
686 op = SUBREG_REG (op);
689 if (GET_CODE (op) != REG)
692 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
695 /* Return true if operand is the F1 register. */
698 f1_operand (op, mode)
700 enum machine_mode mode;
702 if (GET_MODE (op) != mode && mode != VOIDmode)
705 if (GET_CODE (op) == SUBREG)
707 if (GET_CODE (SUBREG_REG (op)) != REG)
708 return register_operand (op, mode);
710 op = SUBREG_REG (op);
713 if (GET_CODE (op) != REG)
716 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
719 /* Return true if operand is the F1 register. */
722 carry_operand (op, mode)
724 enum machine_mode mode;
726 if (GET_MODE (op) != mode && mode != VOIDmode)
729 if (GET_CODE (op) == SUBREG)
731 if (GET_CODE (SUBREG_REG (op)) != REG)
732 return register_operand (op, mode);
734 op = SUBREG_REG (op);
737 if (GET_CODE (op) != REG)
740 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
743 /* Return true if operand is a register of any flavor or a 0 of the
747 reg_or_0_operand (op, mode)
749 enum machine_mode mode;
751 switch (GET_CODE (op))
758 if (GET_MODE (op) != mode && mode != VOIDmode)
761 return register_operand (op, mode);
764 return INTVAL (op) == 0;
767 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
773 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
776 gpr_or_signed6_operand (op, mode)
778 enum machine_mode mode;
780 if (GET_CODE (op) == SUBREG)
782 if (GET_CODE (SUBREG_REG (op)) != REG)
783 return register_operand (op, mode);
785 op = SUBREG_REG (op);
788 if (GET_CODE (op) == CONST_INT)
789 return IN_RANGE_P (INTVAL (op), -32, 31);
791 if (GET_CODE (op) != REG)
794 if (GET_MODE (op) != mode && mode != VOIDmode)
797 return GPR_OR_PSEUDO_P (REGNO (op));
800 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
803 gpr_or_unsigned5_operand (op, mode)
805 enum machine_mode mode;
807 if (GET_CODE (op) == SUBREG)
809 if (GET_CODE (SUBREG_REG (op)) != REG)
810 return register_operand (op, mode);
812 op = SUBREG_REG (op);
815 if (GET_CODE (op) == CONST_INT)
816 return IN_RANGE_P (INTVAL (op), 0, 31);
818 if (GET_CODE (op) != REG)
821 if (GET_MODE (op) != mode && mode != VOIDmode)
824 return GPR_OR_PSEUDO_P (REGNO (op));
827 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
830 gpr_or_unsigned6_operand (op, mode)
832 enum machine_mode mode;
834 if (GET_CODE (op) == SUBREG)
836 if (GET_CODE (SUBREG_REG (op)) != REG)
837 return register_operand (op, mode);
839 op = SUBREG_REG (op);
842 if (GET_CODE (op) == CONST_INT)
843 return IN_RANGE_P (INTVAL (op), 0, 63);
845 if (GET_CODE (op) != REG)
848 if (GET_MODE (op) != mode && mode != VOIDmode)
851 return GPR_OR_PSEUDO_P (REGNO (op));
854 /* Return true if operand is a GPR register or a constant of some form. */
857 gpr_or_constant_operand (op, mode)
859 enum machine_mode mode;
861 switch (GET_CODE (op))
873 if (GET_CODE (SUBREG_REG (op)) != REG)
874 return register_operand (op, mode);
876 op = SUBREG_REG (op);
880 if (GET_MODE (op) != mode && mode != VOIDmode)
883 return GPR_OR_PSEUDO_P (REGNO (op));
889 /* Return true if operand is a GPR register or a constant of some form,
890 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
893 gpr_or_dbl_const_operand (op, mode)
895 enum machine_mode mode;
897 switch (GET_CODE (op))
910 if (GET_CODE (SUBREG_REG (op)) != REG)
911 return register_operand (op, mode);
913 op = SUBREG_REG (op);
917 if (GET_MODE (op) != mode && mode != VOIDmode)
920 return GPR_OR_PSEUDO_P (REGNO (op));
926 /* Return true if operand is a gpr register or a valid memory operation. */
929 gpr_or_memory_operand (op, mode)
931 enum machine_mode mode;
933 switch (GET_CODE (op))
939 if (GET_CODE (SUBREG_REG (op)) != REG)
940 return register_operand (op, mode);
942 op = SUBREG_REG (op);
946 if (GET_MODE (op) != mode && mode != VOIDmode)
949 return GPR_OR_PSEUDO_P (REGNO (op));
952 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
958 /* Return true if operand is something that can be an input for a move
962 move_input_operand (op, mode)
964 enum machine_mode mode;
969 switch (GET_CODE (op))
982 if (GET_MODE (op) != mode && mode != VOIDmode)
985 subreg = SUBREG_REG (op);
986 code = GET_CODE (subreg);
988 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
991 return (code == REG);
994 if (GET_MODE (op) != mode && mode != VOIDmode)
1000 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1002 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1009 /* Return true if operand is something that can be an output for a move
1013 move_output_operand (op, mode)
1015 enum machine_mode mode;
1020 switch (GET_CODE (op))
1026 if (GET_MODE (op) != mode && mode != VOIDmode)
1029 subreg = SUBREG_REG (op);
1030 code = GET_CODE (subreg);
1032 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1035 return (code == REG);
1038 if (GET_MODE (op) != mode && mode != VOIDmode)
1044 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1046 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1053 /* Return true if operand is a signed 6 bit immediate. */
1056 signed6_operand (op, mode)
1058 enum machine_mode mode ATTRIBUTE_UNUSED;
1060 if (GET_CODE (op) == CONST_INT)
1061 return IN_RANGE_P (INTVAL (op), -32, 31);
1066 /* Return true if operand is an unsigned 5 bit immediate. */
1069 unsigned5_operand (op, mode)
1071 enum machine_mode mode ATTRIBUTE_UNUSED;
1073 if (GET_CODE (op) == CONST_INT)
1074 return IN_RANGE_P (INTVAL (op), 0, 31);
1079 /* Return true if operand is an unsigned 6 bit immediate. */
1082 unsigned6_operand (op, mode)
1084 enum machine_mode mode ATTRIBUTE_UNUSED;
1086 if (GET_CODE (op) == CONST_INT)
1087 return IN_RANGE_P (INTVAL (op), 0, 63);
1092 /* Return true if operand is a constant with a single bit set. */
1095 bitset_operand (op, mode)
1097 enum machine_mode mode ATTRIBUTE_UNUSED;
1099 if (GET_CODE (op) == CONST_INT)
1100 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1105 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1106 used in conditional execution. */
1109 condexec_test_operator (op, mode)
1111 enum machine_mode mode;
1115 if (GET_MODE (op) != mode && mode != VOIDmode)
1118 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1122 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1126 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1132 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1133 register that can be used in a branch instruction. */
1136 condexec_branch_operator (op, mode)
1138 enum machine_mode mode;
1142 if (GET_MODE (op) != mode && mode != VOIDmode)
1145 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1149 if (GET_CODE (x0) == REG)
1151 int regno = REGNO (x0);
1152 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1155 /* Allow the optimizer to generate things like:
1156 (if_then_else (ne (const_int 1) (const_int 0))) */
1157 else if (GET_CODE (x0) != CONST_INT)
1161 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1167 /* Return true if the unary operator can be executed with conditional
1171 condexec_unary_operator (op, mode)
1173 enum machine_mode mode ATTRIBUTE_UNUSED;
1177 /* Only do this after register allocation, so that we can look at the register # */
1178 if (!reload_completed)
1181 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1185 if (GET_CODE (op0) == SUBREG)
1186 op0 = SUBREG_REG (op0);
1188 switch (GET_CODE (op))
1195 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1204 /* Return true if the add or subtraction can be executed with conditional
1208 condexec_addsub_operator (op, mode)
1210 enum machine_mode mode ATTRIBUTE_UNUSED;
1214 /* Only do this after register allocation, so that we can look at the register # */
1215 if (!reload_completed)
1218 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1224 if (GET_CODE (op0) == SUBREG)
1225 op0 = SUBREG_REG (op0);
1227 if (GET_CODE (op1) == SUBREG)
1228 op1 = SUBREG_REG (op1);
1230 if (GET_CODE (op0) != REG)
1233 switch (GET_CODE (op))
1240 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1241 && gpr_or_constant_operand (op1, SImode));
1247 /* Return true if the binary operator can be executed with conditional
1248 execution. We don't include add/sub here, since they have extra
1249 clobbers for the flags registers. */
1252 condexec_binary_operator (op, mode)
1254 enum machine_mode mode ATTRIBUTE_UNUSED;
1258 /* Only do this after register allocation, so that we can look at the register # */
1259 if (!reload_completed)
1262 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1268 if (GET_CODE (op0) == SUBREG)
1269 op0 = SUBREG_REG (op0);
1271 if (GET_CODE (op1) == SUBREG)
1272 op1 = SUBREG_REG (op1);
1274 if (GET_CODE (op0) != REG)
1277 /* MULT is not included here, because it is an IU only instruction. */
1278 switch (GET_CODE (op))
1289 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1290 && gpr_or_constant_operand (op1, SImode));
1294 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1295 && GET_CODE (op1) == CONST_INT);
1301 /* Return true if the shift/rotate left operator can be executed with
1302 conditional execution. */
1305 condexec_shiftl_operator (op, mode)
1307 enum machine_mode mode ATTRIBUTE_UNUSED;
1311 /* Only do this after register allocation, so that we can look at the register # */
1312 if (!reload_completed)
1315 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1321 if (GET_CODE (op0) == SUBREG)
1322 op0 = SUBREG_REG (op0);
1324 if (GET_CODE (op1) == SUBREG)
1325 op1 = SUBREG_REG (op1);
1327 if (GET_CODE (op0) != REG)
1330 switch (GET_CODE (op))
1337 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1338 && GET_CODE (op1) == NEG
1339 && GET_CODE (XEXP (op1, 0)) == REG
1340 && GPR_P (REGNO (XEXP (op1, 0))));
1346 /* Return true if the {sign,zero} extend operator from memory can be
1347 conditionally executed. */
1350 condexec_extend_operator (op, mode)
1352 enum machine_mode mode ATTRIBUTE_UNUSED;
1354 /* Only do this after register allocation, so that we can look at the register # */
1355 if (!reload_completed)
1358 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1361 switch (GET_CODE (op))
1368 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1369 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1370 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1379 /* Return true for comparisons against 0 that can be turned into a
1380 bratnz/bratzr instruction. */
1383 branch_zero_operator (op, mode)
1385 enum machine_mode mode;
1389 if (GET_MODE (op) != mode && mode != VOIDmode)
1392 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1396 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1400 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1406 /* Return true if an operand is simple, suitable for use as the destination of
1407 a conditional move */
1410 cond_move_dest_operand (op, mode)
1412 enum machine_mode mode ATTRIBUTE_UNUSED;
1416 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1419 switch (GET_CODE (op))
1426 return gpr_operand (op, mode);
1428 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1430 addr = XEXP (op, 0);
1431 return (GET_CODE (addr) != POST_DEC
1432 && GET_CODE (addr) != POST_INC
1433 && d30v_legitimate_address_p (mode, addr, reload_completed));
1439 /* Return true if an operand is simple, suitable for use in a conditional move */
1442 cond_move_operand (op, mode)
1444 enum machine_mode mode ATTRIBUTE_UNUSED;
1448 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1451 switch (GET_CODE (op))
1458 return gpr_operand (op, mode);
1461 return GET_MODE (op) == SFmode;
1469 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1471 addr = XEXP (op, 0);
1472 return (GET_CODE (addr) != POST_DEC
1473 && GET_CODE (addr) != POST_INC
1474 && d30v_legitimate_address_p (mode, addr, reload_completed));
1480 /* Return true if an operand is simple, suitable for use in conditional execution.
1481 Unlike cond_move, we can allow auto inc/dec. */
1484 cond_exec_operand (op, mode)
1486 enum machine_mode mode;
1488 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1491 switch (GET_CODE (op))
1498 return gpr_operand (op, mode);
1501 return GET_MODE (op) == SFmode;
1510 return memory_operand (op, mode);
1516 /* Return true if operand is a SI mode signed relational test. */
1519 srelational_si_operator (op, mode)
1521 enum machine_mode mode;
1525 if (GET_MODE (op) != mode && mode != VOIDmode)
1528 switch (GET_CODE (op))
1543 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1546 if (GET_MODE (x0) != SImode)
1550 switch (GET_CODE (x1))
1567 /* Return true if operand is a SI mode unsigned relational test. */
1570 urelational_si_operator (op, mode)
1572 enum machine_mode mode;
1576 if (GET_MODE (op) != mode && mode != VOIDmode)
1579 switch (GET_CODE (op))
1592 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1595 if (GET_MODE (x0) != SImode)
1599 switch (GET_CODE (x1))
1616 /* Return true if operand is a DI mode relational test. */
1619 relational_di_operator (op, mode)
1621 enum machine_mode mode;
1625 if (GET_MODE (op) != mode && mode != VOIDmode)
1628 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1632 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1635 if (GET_MODE (x0) != DImode)
1639 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1640 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1647 /* Calculate the stack information for the current function.
1649 D30V stack frames look like:
1652 +-------------------------------+
1653 | Argument word #19 |
1654 +-------------------------------+
1655 | Argument word #18 |
1656 +-------------------------------+
1657 | Argument word #17 |
1658 +-------------------------------+
1659 | Argument word #16 |
1660 Prev sp +-------------------------------+
1662 | Save for arguments 1..16 if |
1663 | the func. uses stdarg/varargs |
1665 +-------------------------------+
1667 | Save area for GPR registers |
1669 +-------------------------------+
1671 | Save area for accumulators |
1673 +-------------------------------+
1677 +-------------------------------+
1679 | alloca space if used |
1681 +-------------------------------+
1683 | Space for outgoing arguments |
1685 low SP----> +-------------------------------+
1691 static d30v_stack_t info, zero_info;
1692 d30v_stack_t *info_ptr = &info;
1693 tree fndecl = current_function_decl;
1694 tree fntype = TREE_TYPE (fndecl);
1702 unsigned char save_gpr_p[GPR_LAST];
1705 /* If we've already calculated the values and reload is complete, just return now */
1706 if (d30v_stack_cache)
1707 return d30v_stack_cache;
1709 /* Zero all fields */
1713 regs_ever_live[GPR_LINK] = 1;
1715 /* Determine if this is a stdarg function */
1716 if (TYPE_ARG_TYPES (fntype) != 0
1717 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1721 /* Find the last argument, and see if it is __builtin_va_alist. */
1722 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1724 next_arg = TREE_CHAIN (cur_arg);
1725 if (next_arg == (tree)0)
1727 if (DECL_NAME (cur_arg)
1728 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1736 /* Calculate which registers need to be saved & save area size */
1740 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1742 if (regs_ever_live[i] && !call_used_regs[i])
1744 info_ptr->save_p[i] = 2;
1751 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1753 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1762 /* Determine which register pairs can be saved together with ld2w/st2w */
1763 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1765 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1768 info_ptr->save_p[i++] = 2;
1770 else if (save_gpr_p[i])
1773 info_ptr->save_p[i] = 1;
1777 /* Determine various sizes */
1778 info_ptr->varargs_p = varargs_p;
1779 info_ptr->varargs_size = ((varargs_p)
1780 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1783 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1784 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1785 2 * UNITS_PER_WORD);
1786 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1787 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1788 2 * UNITS_PER_WORD);
1790 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1791 + info_ptr->accum_size
1792 + info_ptr->vars_size
1793 + info_ptr->parm_size
1794 + info_ptr->varargs_size
1795 + current_function_pretend_args_size),
1796 (STACK_BOUNDARY / BITS_PER_UNIT));
1798 info_ptr->save_offset = (info_ptr->total_size
1799 - (current_function_pretend_args_size
1800 + info_ptr->varargs_size
1801 + info_ptr->gpr_size
1802 + info_ptr->accum_size));
1804 /* The link register is the last GPR saved, but there might be some padding
1805 bytes after it, so account for that. */
1806 info_ptr->link_offset = (info_ptr->total_size
1807 - (current_function_pretend_args_size
1808 + info_ptr->varargs_size
1809 + (info_ptr->gpr_size
1810 - UNITS_PER_WORD * saved_gprs)
1813 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1814 info_ptr->memrefs_2words = memrefs_2words;
1815 info_ptr->memrefs_1word = memrefs_1word;
1817 if (reload_completed)
1818 d30v_stack_cache = info_ptr;
1824 /* Internal function to print all of the information about the stack */
1827 debug_stack_info (info)
1833 info = d30v_stack_info ();
1835 fprintf (stderr, "\nStack information for function %s:\n",
1836 ((current_function_decl && DECL_NAME (current_function_decl))
1837 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1840 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1841 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1842 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1843 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1844 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1845 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1846 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1847 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1848 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1849 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1850 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1851 fprintf (stderr, "\tsaved registers =");
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 if (info->save_p[i] == 2)
1857 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1860 else if (info->save_p[i])
1861 fprintf (stderr, " %s", reg_names[i]);
1864 putc ('\n', stderr);
1869 /* Return non-zero if this function is known to have a null or 1 instruction epilogue. */
1874 if (reload_completed)
1876 d30v_stack_t *info = d30v_stack_info ();
1878 /* If no epilogue code is needed, can use just a simple jump */
1879 if (info->total_size == 0)
1883 /* If just a small amount of local stack was allocated and no registers
1884 saved, skip forward branch */
1885 if (info->total_size == info->vars_size
1886 && IN_RANGE_P (info->total_size, 1, 31))
1895 /* A C statement (sans semicolon) for initializing the variable CUM for the
1896 state at the beginning of the argument list. The variable has type
1897 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1898 of the function which will receive the args, or 0 if the args are to a
1899 compiler support library function. The value of INDIRECT is nonzero when
1900 processing an indirect call, for example a call through a function pointer.
1901 The value of INDIRECT is zero for a call to an explicitly named function, a
1902 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1903 arguments for the function being compiled.
1905 When processing a call to a compiler support library function, LIBNAME
1906 identifies which one. It is a `symbol_ref' rtx which contains the name of
1907 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1908 being processed. Thus, each time this macro is called, either LIBNAME or
1909 FNTYPE is nonzero, but never both of them at once. */
1912 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1913 CUMULATIVE_ARGS *cum;
1919 *cum = GPR_ARG_FIRST;
1921 if (TARGET_DEBUG_ARG)
1923 fprintf (stderr, "\ninit_cumulative_args:");
1925 fputs (" indirect", stderr);
1928 fputs (" incoming", stderr);
1932 tree ret_type = TREE_TYPE (fntype);
1933 fprintf (stderr, " return=%s,",
1934 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1937 if (libname && GET_CODE (libname) == SYMBOL_REF)
1938 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1940 putc ('\n', stderr);
1945 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1946 argument with the specified mode and type. If it is not defined,
1947 `PARM_BOUNDARY' is used for all arguments. */
1950 d30v_function_arg_boundary (mode, type)
1951 enum machine_mode mode;
1954 int size = ((mode == BLKmode && type)
1955 ? int_size_in_bytes (type)
1956 : (int) GET_MODE_SIZE (mode));
1958 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1962 /* A C expression that controls whether a function argument is passed in a
1963 register, and which register.
1965 The arguments are CUM, which summarizes all the previous arguments; MODE,
1966 the machine mode of the argument; TYPE, the data type of the argument as a
1967 tree node or 0 if that is not known (which happens for C support library
1968 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1969 nameless arguments that correspond to `...' in the called function's
1972 The value of the expression should either be a `reg' RTX for the hard
1973 register in which to pass the argument, or zero to pass the argument on the
1976 For machines like the VAX and 68000, where normally all arguments are
1977 pushed, zero suffices as a definition.
1979 The usual way to make the ANSI library `stdarg.h' work on a machine where
1980 some arguments are usually passed in registers, is to cause nameless
1981 arguments to be passed on the stack instead. This is done by making
1982 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1984 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1985 this macro to determine if this argument is of a type that must be passed in
1986 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1987 returns non-zero for such an argument, the compiler will abort. If
1988 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1989 stack and then loaded into a register. */
1992 d30v_function_arg (cum, mode, type, named, incoming)
1993 CUMULATIVE_ARGS *cum;
1994 enum machine_mode mode;
1997 int incoming ATTRIBUTE_UNUSED;
1999 int size = ((mode == BLKmode && type)
2000 ? int_size_in_bytes (type)
2001 : (int) GET_MODE_SIZE (mode));
2002 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2005 /* Return a marker for use in the call instruction. */
2006 if (mode == VOIDmode)
2009 else if (*cum + adjust <= GPR_ARG_LAST)
2010 ret = gen_rtx (REG, mode, *cum + adjust);
2015 if (TARGET_DEBUG_ARG)
2017 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2018 *cum, GET_MODE_NAME (mode), named, size, adjust,
2019 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2025 /* A C expression for the number of words, at the beginning of an argument,
2026 must be put in registers. The value must be zero for arguments that are
2027 passed entirely in registers or that are entirely pushed on the stack.
2029 On some machines, certain arguments must be passed partially in registers
2030 and partially in memory. On these machines, typically the first N words of
2031 arguments are passed in registers, and the rest on the stack. If a
2032 multi-word argument (a `double' or a structure) crosses that boundary, its
2033 first few words must be passed in registers and the rest must be pushed.
2034 This macro tells the compiler when this occurs, and how many of the words
2035 should go in registers.
2037 `FUNCTION_ARG' for these arguments should return the first register to be
2038 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2039 the called function. */
2042 d30v_function_arg_partial_nregs (cum, mode, type, named)
2043 CUMULATIVE_ARGS *cum;
2044 enum machine_mode mode;
2046 int named ATTRIBUTE_UNUSED;
2048 int bytes = ((mode == BLKmode)
2049 ? int_size_in_bytes (type)
2050 : (int) GET_MODE_SIZE (mode));
2051 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2052 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2053 int arg_num = *cum + adjust;
2056 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2057 ? GPR_ARG_LAST - arg_num + 1
2060 if (TARGET_DEBUG_ARG && ret)
2061 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2067 /* A C expression that indicates when an argument must be passed by reference.
2068 If nonzero for an argument, a copy of that argument is made in memory and a
2069 pointer to the argument is passed instead of the argument itself. The
2070 pointer is passed in whatever way is appropriate for passing a pointer to
2073 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2074 definition of this macro might be
2075 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2076 (CUM, MODE, TYPE, NAMED) \
2077 MUST_PASS_IN_STACK (MODE, TYPE) */
2080 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2081 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2082 enum machine_mode mode;
2084 int named ATTRIBUTE_UNUSED;
2086 int ret = MUST_PASS_IN_STACK (mode, type);
2088 if (TARGET_DEBUG_ARG && ret)
2089 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2095 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2096 advance past an argument in the argument list. The values MODE, TYPE and
2097 NAMED describe that argument. Once this is done, the variable CUM is
2098 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2100 This macro need not do anything if the argument in question was passed on
2101 the stack. The compiler knows how to track the amount of stack space used
2102 for arguments without any special help. */
2105 d30v_function_arg_advance (cum, mode, type, named)
2106 CUMULATIVE_ARGS *cum;
2107 enum machine_mode mode;
2111 int bytes = ((mode == BLKmode)
2112 ? int_size_in_bytes (type)
2113 : (int) GET_MODE_SIZE (mode));
2114 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2115 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2117 *cum += words + adjust;
2119 if (TARGET_DEBUG_ARG)
2121 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2122 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2126 /* If defined, is a C expression that produces the machine-specific code for a
2127 call to `__builtin_saveregs'. This code will be moved to the very beginning
2128 of the function, before any parameter access are made. The return value of
2129 this function should be an RTX that contains the value to use as the return
2130 of `__builtin_saveregs'.
2132 If this macro is not defined, the compiler will output an ordinary call to
2133 the library function `__builtin_saveregs'. */
2136 d30v_expand_builtin_saveregs ()
2138 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2140 if (TARGET_DEBUG_ARG)
2141 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2144 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2148 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2149 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2150 arguments into the stack so that all the arguments appear to have been
2151 passed consecutively on the stack. Once this is done, you can use the
2152 standard implementation of varargs that works for machines that pass all
2153 their arguments on the stack.
2155 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2156 the values that obtain after processing of the named arguments. The
2157 arguments MODE and TYPE describe the last named argument--its machine mode
2158 and its data type as a tree node.
2160 The macro implementation should do two things: first, push onto the stack
2161 all the argument registers *not* used for the named arguments, and second,
2162 store the size of the data thus pushed into the `int'-valued variable whose
2163 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2164 store here will serve as additional offset for setting up the stack frame.
2166 Because you must generate code to push the anonymous arguments at compile
2167 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2168 useful on machines that have just a single category of argument register and
2169 use it uniformly for all data types.
2171 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2172 function are being analyzed for the second time. This happens for an inline
2173 function, which is not actually compiled until the end of the source file.
2174 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2178 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2179 CUMULATIVE_ARGS *cum;
2180 enum machine_mode mode;
2181 tree type ATTRIBUTE_UNUSED;
2182 int *pretend_size ATTRIBUTE_UNUSED;
2185 if (TARGET_DEBUG_ARG)
2187 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2188 *cum, GET_MODE_NAME (mode), second_time);
2192 /* Create the va_list data type. */
2195 d30v_build_va_list ()
2197 tree f_arg_ptr, f_arg_num, record, type_decl;
2200 record = make_lang_type (RECORD_TYPE);
2201 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2202 int_type_node = make_signed_type (INT_TYPE_SIZE);
2204 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2206 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2209 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2210 DECL_FIELD_CONTEXT (f_arg_num) = record;
2212 TREE_CHAIN (record) = type_decl;
2213 TYPE_NAME (record) = type_decl;
2214 TYPE_FIELDS (record) = f_arg_ptr;
2215 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2217 layout_type (record);
2219 /* The correct type is an array type of one element. */
2220 return build_array_type (record, build_index_type (size_zero_node));
2224 /* Expand __builtin_va_start to do the va_start macro. */
2227 d30v_expand_builtin_va_start (stdarg_p, valist, nextarg)
2228 int stdarg_p ATTRIBUTE_UNUSED;
2230 rtx nextarg ATTRIBUTE_UNUSED;
2232 HOST_WIDE_INT words;
2233 tree f_arg_ptr, f_arg_num;
2234 tree arg_ptr, arg_num, saveregs, t;
2236 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2237 f_arg_num = TREE_CHAIN (f_arg_ptr);
2239 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2240 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2241 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2243 words = current_function_args_info; /* __builtin_args_info (0) */
2245 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2246 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2247 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2248 TREE_SIDE_EFFECTS (t) = 1;
2249 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2251 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2252 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2253 build_int_2 (-GPR_ARG_FIRST, 0));
2254 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2255 TREE_SIDE_EFFECTS (t) = 1;
2256 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2260 /* Expand __builtin_va_arg to do the va_arg macro. */
2263 d30v_expand_builtin_va_arg(valist, type)
2267 tree f_arg_ptr, f_arg_num;
2268 tree arg_ptr, arg_num, t, ptr;
2270 rtx lab_false, ptr_rtx, r;
2272 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2273 f_arg_num = TREE_CHAIN (f_arg_ptr);
2275 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2276 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2277 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2279 size = int_size_in_bytes (type);
2281 lab_false = gen_label_rtx ();
2282 ptr_rtx = gen_reg_rtx (Pmode);
2284 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2285 (AP)->__va_arg_num++; */
2287 if (size > UNITS_PER_WORD)
2289 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2290 build_int_2 (1, 0));
2292 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2293 GEN_INT (0), EQ, const1_rtx, QImode, 1,
2296 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2297 build_int_2 (1, 0));
2298 TREE_SIDE_EFFECTS (t) = 1;
2299 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2301 emit_label (lab_false);
2305 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2306 + (AP)->__va_arg_num))); */
2308 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2309 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2311 /* if (sizeof (TYPE) < 4)
2312 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2314 if (size < UNITS_PER_WORD)
2315 t = build (PLUS_EXPR, ptr_type_node, t,
2316 build_int_2 (UNITS_PER_WORD - size, 0));
2318 TREE_SIDE_EFFECTS (t) = 1;
2320 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2321 t = build (MODIFY_EXPR, type, ptr, t);
2323 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2325 emit_move_insn (ptr_rtx, r);
2328 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2329 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2330 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2331 build_int_2 (num, 0));
2332 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2337 /* Generate the assembly code for function entry. FILE is a stdio
2338 stream to output the code to. SIZE is an int: how many units of
2339 temporary storage to allocate.
2341 Refer to the array `regs_ever_live' to determine which registers to
2342 save; `regs_ever_live[I]' is nonzero if register number I is ever
2343 used in the function. This function is responsible for knowing
2344 which registers should not be saved even if used. */
2347 d30v_output_function_prologue (stream, size)
2348 FILE *stream ATTRIBUTE_UNUSED;
2349 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2351 /* For the d30v, move all of the prologue processing into separate
2356 /* Called after register allocation to add any instructions needed for
2357 the prologue. Using a prologue insn is favored compared to putting
2358 all of the instructions in output_function_prologue (), since it
2359 allows the scheduler to intermix instructions with the saves of the
2360 caller saved registers. In some cases, it might be necessary to
2361 emit a barrier instruction as the last insn to prevent such
2365 d30v_expand_prologue ()
2367 rtx sp = stack_pointer_rtx;
2368 d30v_stack_t *info = d30v_stack_info ();
2370 rtx mem_di = NULL_RTX;
2371 rtx mem_si = NULL_RTX;
2372 int num_memrefs = (info->memrefs_2words
2373 + info->memrefs_1word
2374 + info->memrefs_varargs);
2376 if (TARGET_DEBUG_STACK)
2377 debug_stack_info (info);
2379 /* Grow the stack. */
2380 if (info->total_size)
2381 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2383 /* If there is more than one save, use post-increment addressing which will
2384 result in smaller code, than would the normal references. If there is
2385 only one save, just do the store as normal. */
2387 if (num_memrefs > 1)
2389 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2390 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2391 mem_di = gen_rtx (MEM, DImode, post_inc);
2392 mem_si = gen_rtx (MEM, SImode, post_inc);
2393 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2395 else if (num_memrefs == 1)
2397 rtx addr = plus_constant (sp, info->save_offset);
2398 mem_di = gen_rtx (MEM, DImode, addr);
2399 mem_si = gen_rtx (MEM, SImode, addr);
2402 /* Save the accumulators. */
2403 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2404 if (info->save_p[i])
2406 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2407 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2408 emit_insn (gen_movdi (mem_di, acc_tmp));
2411 /* Save the GPR registers that are adjacent to each other with st2w. */
2412 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2413 if (info->save_p[i] == 2)
2414 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2416 /* Save the GPR registers that need to be saved with a single word store. */
2417 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2418 if (info->save_p[i] == 1)
2419 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2421 /* Save the argument registers if this function accepts variable args. */
2422 if (info->varargs_p)
2424 /* Realign r22 if an odd # of GPRs were saved. */
2425 if ((info->memrefs_1word & 1) != 0)
2427 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2428 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2431 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2432 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2435 /* Update the frame pointer. */
2436 if (frame_pointer_needed)
2437 emit_move_insn (frame_pointer_rtx, sp);
2439 /* Hack for now, to prevent scheduler from being too cleaver */
2440 emit_insn (gen_blockage ());
2444 /* This function generates the assembly code for function exit.
2445 Args are as for output_function_prologue ().
2447 The function epilogue should not depend on the current stack
2448 pointer! It should use the frame pointer only. This is mandatory
2449 because of alloca; we also take advantage of it to omit stack
2450 adjustments before returning. */
2453 d30v_output_function_epilogue (stream, size)
2454 FILE *stream ATTRIBUTE_UNUSED;
2455 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2457 /* For the d30v, move all processing to be as insns, but do any
2458 cleanup here, since it is done after handling all of the insns. */
2459 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2464 /* Called after register allocation to add any instructions needed for
2465 the epilogue. Using an epilogue insn is favored compared to putting
2466 all of the instructions in output_function_prologue(), since it
2467 allows the scheduler to intermix instructions with the saves of the
2468 caller saved registers. In some cases, it might be necessary to
2469 emit a barrier instruction as the last insn to prevent such
2473 d30v_expand_epilogue ()
2475 rtx sp = stack_pointer_rtx;
2476 d30v_stack_t *info = d30v_stack_info ();
2478 rtx mem_di = NULL_RTX;
2479 rtx mem_si = NULL_RTX;
2483 /* Hack for now, to prevent scheduler from being too cleaver */
2484 emit_insn (gen_blockage ());
2486 /* Restore sp from fp. */
2487 if (frame_pointer_needed)
2488 emit_move_insn (sp, frame_pointer_rtx);
2490 /* For the epilogue, use post-increment addressing all of the time. First
2491 adjust the sp, to eliminate all of the stack, except for the save area. */
2493 if (info->save_offset)
2494 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2496 post_inc = gen_rtx (POST_INC, Pmode, sp);
2497 mem_di = gen_rtx (MEM, DImode, post_inc);
2498 mem_si = gen_rtx (MEM, SImode, post_inc);
2500 /* Restore the accumulators. */
2501 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2502 if (info->save_p[i])
2504 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2505 emit_insn (gen_movdi (acc_tmp, mem_di));
2506 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2509 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2510 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2511 if (info->save_p[i] == 2)
2512 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2514 /* Save the GPR registers that need to be saved with a single word store. */
2516 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2517 if (info->save_p[i] == 1)
2519 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2525 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2528 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2532 /* Release any remaining stack that was allocated for saving the
2533 varargs registers or because an odd # of registers were stored. */
2534 if ((info->memrefs_1word & 1) != 0)
2535 extra_stack += UNITS_PER_WORD;
2536 extra_stack += current_function_pretend_args_size + info->varargs_size;
2540 if (cfun->machine->eh_epilogue_sp_ofs)
2541 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2542 cfun->machine->eh_epilogue_sp_ofs,
2543 GEN_INT (extra_stack)));
2545 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2547 if (cfun->machine->eh_epilogue_sp_ofs)
2548 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2550 /* Now emit the return instruction. */
2551 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2555 /* A C statement or compound statement to output to FILE some assembler code to
2556 call the profiling subroutine `mcount'. Before calling, the assembler code
2557 must load the address of a counter variable into a register where `mcount'
2558 expects to find the address. The name of this variable is `LP' followed by
2559 the number LABELNO, so you would generate the name using `LP%d' in a
2562 The details of how the address should be passed to `mcount' are determined
2563 by your operating system environment, not by GNU CC. To figure them out,
2564 compile a small program for profiling using the system's installed C
2565 compiler and look at the assembler code that results. */
2568 d30v_function_profiler (stream, labelno)
2570 int labelno ATTRIBUTE_UNUSED;
2572 fprintf (stream, "# profile\n");
2576 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2577 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2578 the wrong part for floating point in cross compilers, and split_double does
2579 not handle registers. Also abort if the register is not a general purpose
2583 d30v_split_double (value, p_high, p_low)
2591 if (!reload_completed)
2594 switch (GET_CODE (value))
2597 if (GET_CODE (SUBREG_REG (value)) != REG)
2599 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2600 GET_MODE (SUBREG_REG (value)),
2601 SUBREG_BYTE (value),
2603 value = SUBREG_REG (value);
2608 regno = REGNO (value) + offset;
2612 *p_high = gen_rtx (REG, SImode, regno);
2613 *p_low = gen_rtx (REG, SImode, regno+1);
2618 split_double (value, p_high, p_low);
2627 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2628 for an instruction operand that is a memory reference whose address is X. X
2629 is an RTL expression.
2631 On some machines, the syntax for a symbolic address depends on the section
2632 that the address refers to. On these machines, define the macro
2633 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
2634 then check for it here. *Note Assembler Format::. */
2637 d30v_print_operand_address (stream, x)
2641 if (GET_CODE (x) == MEM)
2644 switch (GET_CODE (x))
2650 fputs (reg_names[ REGNO (x) ], stream);
2654 fprintf (stream, "%ld", (long) INTVAL (x));
2657 /* We wrap simple symbol refs inside a parenthesis, so that a name
2658 like `r2' is not taken for a register name. */
2660 fputs ("(", stream);
2661 assemble_name (stream, XSTR (x, 0));
2662 fputs (")", stream);
2667 output_addr_const (stream, x);
2671 fatal_insn ("bad insn to d30v_print_operand_address:", x);
2675 /* Print a memory reference suitable for the ld/st instructions. */
2678 d30v_print_operand_memory_reference (stream, x)
2685 switch (GET_CODE (x))
2688 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2708 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2709 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2717 fputs ("@(", stream);
2719 fputs (reg_names[GPR_R0], stream);
2723 const char *suffix = "";
2726 if (GET_CODE (x0) == SUBREG)
2728 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2729 GET_MODE (SUBREG_REG (x0)),
2732 x0 = SUBREG_REG (x0);
2735 if (GET_CODE (x0) == POST_INC)
2740 else if (GET_CODE (x0) == POST_DEC)
2746 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2747 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2749 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2752 fputs (",", stream);
2755 fputs (reg_names[GPR_R0], stream);
2761 switch (GET_CODE (x1))
2764 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2765 GET_MODE (SUBREG_REG (x1)),
2768 x1 = SUBREG_REG (x1);
2769 if (GET_CODE (x1) != REG)
2770 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2774 fputs (reg_names[REGNO (x1) + offset1], stream);
2778 fprintf (stream, "%ld", (long) INTVAL (x1));
2784 d30v_print_operand_address (stream, x1);
2788 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2792 fputs (")", stream);
2796 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2797 for an instruction operand X. X is an RTL expression.
2799 LETTER is a value that can be used to specify one of several ways of
2800 printing the operand. It is used when identical operands must be printed
2801 differently depending on the context. LETTER comes from the `%'
2802 specification that was used to request printing of the operand. If the
2803 specification was just `%DIGIT' then LETTER is 0; if the specification was
2804 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2806 If X is a register, this macro should print the register's name. The names
2807 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2808 is initialized from `REGISTER_NAMES'.
2810 When the machine description has a specification `%PUNCT' (a `%' followed by
2811 a punctuation character), this macro is called with a null pointer for X and
2812 the punctuation character for LETTER.
2814 Standard operand flags that are handled elsewhere:
2815 `=' Output a number unique to each instruction in the compilation.
2816 `a' Substitute an operand as if it were a memory reference.
2817 `c' Omit the syntax that indicates an immediate operand.
2818 `l' Substitute a LABEL_REF into a jump instruction.
2819 `n' Like %cDIGIT, except negate the value before printing.
2821 The d30v specific operand flags are:
2823 `f' Print a SF constant as an int.
2824 `s' Subtract 32 and negate.
2825 `A' Print accumulator number without an `a' in front of it.
2826 `B' Print bit offset for BSET, etc. instructions.
2827 `E' Print u if this is zero extend, nothing if this is sign extend.
2828 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2829 `L' Print the lower half of a 64 bit item.
2830 `M' Print a memory reference for ld/st instructions.
2831 `R' Return appropriate cmp instruction for relational test.
2833 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2834 `U' Print the upper half of a 64 bit item. */
2837 d30v_print_operand (stream, x, letter)
2842 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2843 rtx split_values[2];
2850 case '.': /* Output r0 */
2851 fputs (reg_names[GPR_R0], stream);
2854 case 'f': /* Print a SF floating constant as an int */
2855 if (GET_CODE (x) != CONST_DOUBLE)
2856 fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x);
2858 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2859 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2860 fprintf (stream, "%ld", num);
2863 case 'A': /* Print accumulator number without an `a' in front of it. */
2864 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2865 fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x);
2867 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2870 case 'M': /* Print a memory reference for ld/st */
2871 if (GET_CODE (x) != MEM)
2872 fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x);
2874 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2877 case 'L': /* print lower part of 64 bit item. */
2878 case 'U': /* print upper part of 64 bit item. */
2879 d30v_split_double (x, &split_values[0], &split_values[1]);
2880 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2883 case ':': /* Output the condition for the current insn. */
2884 x = current_insn_predicate;
2890 case 'F': /* Print an appropriate suffix for a false comparision. */
2891 case 'T': /* Print an appropriate suffix for a true comparision. */
2892 /* Note that the sense of appropriate suffix is for conditional execution
2893 and opposite of what branches want. Branches just use the inverse
2895 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2896 && GET_MODE (x) == CCmode
2897 && GET_CODE (XEXP (x, 0)) == REG
2898 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2899 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2901 int true_false = (letter == 'T');
2903 if (GET_CODE (x) == EQ)
2904 true_false = !true_false;
2906 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2907 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2909 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2910 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2913 fputs ((true_false) ? "tnz" : "tzr", stream);
2916 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2917 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2919 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2920 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2922 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2923 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2926 fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x);
2929 case 'B': /* emit offset single bit to change */
2930 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2931 fprintf (stream, "%d", 31 - log);
2933 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2934 fprintf (stream, "%d", 31 - log);
2937 fatal_insn ("bad insn to print_operand, 'B' modifier:", x);
2940 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2941 if (GET_CODE (x) == ZERO_EXTEND)
2943 else if (GET_CODE (x) != SIGN_EXTEND)
2944 fatal_insn ("bad insn to print_operand, 'E' modifier:", x);
2947 case 'R': /* Return appropriate cmp instruction for relational test. */
2948 switch (GET_CODE (x))
2950 case EQ: fputs ("cmpeq", stream); break;
2951 case NE: fputs ("cmpne", stream); break;
2952 case LT: fputs ("cmplt", stream); break;
2953 case LE: fputs ("cmple", stream); break;
2954 case GT: fputs ("cmpgt", stream); break;
2955 case GE: fputs ("cmpge", stream); break;
2956 case LTU: fputs ("cmpult", stream); break;
2957 case LEU: fputs ("cmpule", stream); break;
2958 case GTU: fputs ("cmpugt", stream); break;
2959 case GEU: fputs ("cmpuge", stream); break;
2962 fatal_insn ("bad insn to print_operand, 'R' modifier:", x);
2966 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2967 if (GET_CODE (x) == CONST_INT)
2968 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2971 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2974 case 'S': /* Subtract 32. */
2975 if (GET_CODE (x) == CONST_INT)
2976 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2979 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2983 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2984 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2985 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2986 && CONST_DOUBLE_HIGH (x) == 0))
2988 fputs (reg_names[GPR_FIRST], stream);
2996 fputs (reg_names[ REGNO (x) ], stream);
2998 else if (code == CONST_INT)
2999 fprintf (stream, "%d", (int)INTVAL (x));
3001 else if (code == MEM)
3002 d30v_print_operand_address (stream, XEXP (x, 0));
3004 else if (CONSTANT_ADDRESS_P (x))
3005 d30v_print_operand_address (stream, x);
3008 fatal_insn ("bad insn in d30v_print_operand, 0 case", x);
3016 sprintf (buf, "invalid asm template character '%%%c'", letter);
3017 fatal_insn (buf, x);
3023 /* A C expression for the size in bytes of the trampoline, as an integer. */
3026 d30v_trampoline_size ()
3032 /* Create a long instruction for building up a trampoline. */
3035 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3036 HOST_WIDE_INT high_bits;
3037 HOST_WIDE_INT low_bits;
3041 rtx reg = gen_reg_rtx (DImode);
3042 rtx high_word = gen_highpart (SImode, reg);
3043 rtx low_word = gen_lowpart (SImode, reg);
3044 rtx tmp1 = gen_reg_rtx (SImode);
3045 rtx tmp2 = gen_reg_rtx (SImode);
3046 rtx tmp3 = gen_reg_rtx (SImode);
3047 rtx tmp4 = gen_reg_rtx (SImode);
3048 rtx tmp5 = gen_reg_rtx (SImode);
3049 rtx tmp6 = gen_reg_rtx (SImode);
3051 imm = force_reg (SImode, imm);
3053 /* Stuff top 6 bits of immediate value into high word */
3054 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3055 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3056 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3058 /* Now get the next 8 bits for building the low word */
3059 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3060 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3062 /* And the bottom 18 bits */
3063 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3064 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3065 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3067 /* Store the instruction */
3068 emit_insn (gen_movdi (mem, reg));
3072 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3073 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3074 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3075 should be passed to the function when it is called. */
3078 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3083 /* The instruction space can only be accessed by ld2w/st2w.
3084 Generate on the fly:
3085 or r18,r0,<static-chain>
3087 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3088 0x80000000, static_chain,
3089 gen_rtx (MEM, DImode, addr));
3091 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3092 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3096 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3097 RTX) is a legitimate memory address on the target machine for a memory
3098 operand of mode MODE.
3100 It usually pays to define several simpler macros to serve as subroutines for
3101 this one. Otherwise it may be too complicated to understand.
3103 This macro must exist in two variants: a strict variant and a non-strict
3104 one. The strict variant is used in the reload pass. It must be defined so
3105 that any pseudo-register that has not been allocated a hard register is
3106 considered a memory reference. In contexts where some kind of register is
3107 required, a pseudo-register with no hard register must be rejected.
3109 The non-strict variant is used in other passes. It must be defined to
3110 accept all pseudo-registers in every context where some kind of register is
3113 Compiler source files that want to use the strict variant of this macro
3114 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3115 conditional to define the strict variant in that case and the non-strict
3118 Subroutines to check for acceptable registers for various purposes (one for
3119 base registers, one for index registers, and so on) are typically among the
3120 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3121 subroutine macros need have two variants; the higher levels of macros may be
3122 the same whether strict or not.
3124 Normally, constant addresses which are the sum of a `symbol_ref' and an
3125 integer are stored inside a `const' RTX to mark them as constant.
3126 Therefore, there is no need to recognize such sums specifically as
3127 legitimate addresses. Normally you would simply recognize any `const' as
3130 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3131 are not marked with `const'. It assumes that a naked `plus' indicates
3132 indexing. If so, then you *must* reject such naked constant sums as
3133 illegitimate addresses, so that none of them will be given to
3134 `PRINT_OPERAND_ADDRESS'.
3136 On some machines, whether a symbolic address is legitimate depends on the
3137 section that the address refers to. On these machines, define the macro
3138 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3139 then check for it here. When you see a `const', you will have to look
3140 inside it to find the `symbol_ref' in order to determine the section. *Note
3143 The best way to modify the name string is by adding text to the beginning,
3144 with suitable punctuation to prevent any ambiguity. Allocate the new name
3145 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3146 remove and decode the added text and output the name accordingly, and define
3147 `STRIP_NAME_ENCODING' to access the original name string.
3149 You can check the information stored here into the `symbol_ref' in the
3150 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3151 `PRINT_OPERAND_ADDRESS'.
3153 Return 0 if the address is not legitimate, 1 if the address would fit
3154 in a short instruction, or 2 if the address would fit in a long
3157 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3159 ? REGNO_OK_FOR_BASE_P (REGNO) \
3160 : GPR_OR_PSEUDO_P (REGNO))
3163 d30v_legitimate_address_p (mode, x, strict_p)
3164 enum machine_mode mode;
3171 switch (GET_CODE (x))
3178 if (GET_CODE (x) != REG)
3184 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3191 if (GET_CODE (x0) == SUBREG)
3192 x0 = SUBREG_REG (x0);
3194 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3197 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3200 switch (GET_CODE (x1))
3206 x1 = SUBREG_REG (x1);
3207 if (GET_CODE (x1) != REG)
3213 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3217 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3229 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3241 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3246 if (TARGET_DEBUG_ADDR)
3248 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3249 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3257 /* A C compound statement that attempts to replace X with a valid memory
3258 address for an operand of mode MODE. WIN will be a C statement label
3259 elsewhere in the code; the macro definition may use
3261 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3263 to avoid further processing if the address has become legitimate.
3265 X will always be the result of a call to `break_out_memory_refs', and OLDX
3266 will be the operand that was given to that function to produce X.
3268 The code generated by this macro should not alter the substructure of X. If
3269 it transforms X into a more legitimate form, it should assign X (which will
3270 always be a C variable) a new value.
3272 It is not necessary for this macro to come up with a legitimate address.
3273 The compiler has standard ways of doing so in all cases. In fact, it is
3274 safe for this macro to do nothing. But often a machine-dependent strategy
3275 can generate better code. */
3278 d30v_legitimize_address (x, oldx, mode, strict_p)
3280 rtx oldx ATTRIBUTE_UNUSED;
3281 enum machine_mode mode ATTRIBUTE_UNUSED;
3282 int strict_p ATTRIBUTE_UNUSED;
3286 if (TARGET_DEBUG_ADDR)
3290 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3292 fprintf (stderr, "\ninto:\n");
3297 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3306 /* A C statement or compound statement with a conditional `goto LABEL;'
3307 executed if memory address X (an RTX) can have different meanings depending
3308 on the machine mode of the memory reference it is used for or if the address
3309 is valid for some modes but not others.
3311 Autoincrement and autodecrement addresses typically have mode-dependent
3312 effects because the amount of the increment or decrement is the size of the
3313 operand being addressed. Some machines have other mode-dependent addresses.
3314 Many RISC machines have no mode-dependent addresses.
3316 You may assume that ADDR is a valid address for the machine. */
3319 d30v_mode_dependent_address_p (addr)
3322 switch (GET_CODE (addr))
3336 /* Generate the appropriate comparison code for a test. */
3339 d30v_emit_comparison (test_int, result, arg1, arg2)
3345 enum rtx_code test = (enum rtx_code) test_int;
3346 enum machine_mode mode = GET_MODE (arg1);
3347 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3350 || (mode == DImode && (test == EQ || test == NE))
3351 || (mode == DImode && (test == LT || test == GE)
3352 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3355 else if (mode == DImode)
3356 return gen_rtx (PARALLEL, VOIDmode,
3359 gen_rtx (CLOBBER, VOIDmode,
3360 gen_reg_rtx (CCmode))));
3363 fatal_insn ("d30v_emit_comparison", rtx_test);
3367 /* Return appropriate code to move 2 words. Since DImode registers must start
3368 on even register numbers, there is no possibility of overlap. */
3371 d30v_move_2words (operands, insn)
3375 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3377 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3378 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3380 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3381 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3383 else if (GET_CODE (operands[1]) == MEM)
3384 return "ld2w %0,%M1";
3386 else if (GET_CODE (operands[1]) == CONST_INT
3387 || GET_CODE (operands[1]) == CONST_DOUBLE)
3388 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3391 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3393 if (GET_CODE (operands[1]) == REG
3394 && GPR_P (REGNO (operands[1])))
3395 return "mvtacc %0,%U1,%L1";
3397 if (GET_CODE (operands[1]) == CONST_INT
3398 && INTVAL (operands[1]) == 0)
3399 return "mvtacc %0,%.,%.";
3402 else if (GET_CODE (operands[0]) == MEM
3403 && GET_CODE (operands[1]) == REG
3404 && GPR_P (REGNO (operands[1])))
3405 return "st2w %1,%M0";
3407 fatal_insn ("bad call to d30v_move_2words", insn);
3411 /* Emit the code to do a conditional move instruction. Return FALSE
3412 if the conditional move could not be executed. */
3415 d30v_emit_cond_move (dest, test, true_value, false_value)
3422 enum machine_mode mode = GET_MODE (dest);
3423 int two_mem_moves_p = FALSE;
3425 if (GET_CODE (dest) == MEM)
3427 if (!reg_or_0_operand (true_value, mode))
3430 if (rtx_equal_p (dest, false_value))
3431 two_mem_moves_p = TRUE;
3433 else if (!reg_or_0_operand (false_value, mode))
3437 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3438 to be slower than just doing the conditional execution. */
3440 br_reg = gen_reg_rtx (CCmode);
3441 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3442 d30v_compare_op0, d30v_compare_op1));
3444 if (!two_mem_moves_p)
3445 emit_insn (gen_rtx_SET (VOIDmode,
3447 gen_rtx_IF_THEN_ELSE (mode,
3448 gen_rtx_NE (CCmode, br_reg,
3454 /* Emit conditional stores as two separate stores. This avoids a problem
3455 where you have a conditional store, and one of the arms of the
3456 conditional store is spilled to memory. */
3457 emit_insn (gen_rtx_SET (VOIDmode,
3459 gen_rtx_IF_THEN_ELSE (mode,
3460 gen_rtx_NE (CCmode, br_reg,
3465 emit_insn (gen_rtx_SET (VOIDmode,
3467 gen_rtx_IF_THEN_ELSE (mode,
3468 gen_rtx_EQ (CCmode, br_reg,
3479 /* In rare cases, correct code generation requires extra machine dependent
3480 processing between the second jump optimization pass and delayed branch
3481 scheduling. On those machines, define this macro as a C statement to act on
3482 the code starting at INSN. */
3485 d30v_machine_dependent_reorg (insn)
3486 rtx insn ATTRIBUTE_UNUSED;
3491 /* A C statement (sans semicolon) to update the integer variable COST based on
3492 the relationship between INSN that is dependent on DEP_INSN through the
3493 dependence LINK. The default is to make no adjustment to COST. This can be
3494 used for example to specify to the scheduler that an output- or
3495 anti-dependence does not incur the same cost as a data-dependence. */
3497 /* For the d30v, try to insure that the source operands for a load/store are
3498 set 2 cycles before the memory reference. */
3501 d30v_adjust_cost (insn, link, dep_insn, cost)
3503 rtx link ATTRIBUTE_UNUSED;
3507 rtx set_dep = single_set (dep_insn);
3508 rtx set_insn = single_set (insn);
3510 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3511 && GET_CODE (SET_DEST (set_dep)) == REG)
3513 rtx reg = SET_DEST (set_dep);
3516 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3517 && reg_mentioned_p (reg, XEXP (mem, 0)))
3518 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3519 && reg_mentioned_p (reg, XEXP (mem, 0))))
3528 /* Function which returns the number of insns that can be
3529 scheduled in the same machine cycle. This must be constant
3530 over an entire compilation. The default is 1. */
3538 /* Routine to allocate, mark and free a per-function,
3539 machine specific structure. */
3542 d30v_init_machine_status (p)
3546 (machine_function *) xcalloc (1, sizeof (machine_function));
3550 d30v_mark_machine_status (p)
3551 struct function * p;
3553 if (p->machine == NULL)
3556 ggc_mark_rtx (p->machine->eh_epilogue_sp_ofs);
3560 d30v_free_machine_status (p)
3563 struct machine_function *machine = p->machine;
3565 if (machine == NULL)
3572 /* Do anything needed before RTL is emitted for each function. */
3575 d30v_init_expanders ()
3577 /* Arrange to save and restore machine status around nested functions. */
3578 init_machine_status = d30v_init_machine_status;
3579 mark_machine_status = d30v_mark_machine_status;
3580 free_machine_status = d30v_free_machine_status;
3583 /* Find the current function's return address.
3585 ??? It would be better to arrange things such that if we would ordinarily
3586 have been a leaf function and we didn't spill the hard reg that we
3587 wouldn't have to save the register in the prolog. But it's not clear
3588 how to get the right information at the right time. */
3593 return get_hard_reg_initial_val (Pmode, GPR_LINK);
3596 /* Called to register all of our global variables with the garbage
3600 d30v_add_gc_roots ()
3602 ggc_add_rtx_root (&d30v_compare_op0, 1);
3603 ggc_add_rtx_root (&d30v_compare_op1, 1);