1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
43 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
49 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
50 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
52 static struct machine_function * d30v_init_machine_status PARAMS ((void));
53 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
54 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
55 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
56 static int d30v_issue_rate PARAMS ((void));
58 /* Define the information needed to generate branch and scc insns. This is
59 stored from the compare operation. */
61 struct rtx_def *d30v_compare_op0;
62 struct rtx_def *d30v_compare_op1;
64 /* Cached value of d30v_stack_info */
65 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
67 /* Values of the -mbranch-cost=n string. */
68 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
69 const char *d30v_branch_cost_string = (const char *)0;
71 /* Values of the -mcond-exec=n string. */
72 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
73 const char *d30v_cond_exec_string = (const char *)0;
75 /* Whether or not a hard register can accept a register */
76 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
78 /* Whether to try and avoid moves between two different modes */
79 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
81 /* Map register number to smallest register class. */
82 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
84 /* Map class letter into register class */
85 enum reg_class reg_class_from_letter[256];
87 /* Initialize the GCC target structure. */
88 #undef TARGET_ASM_ALIGNED_HI_OP
89 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
90 #undef TARGET_ASM_ALIGNED_SI_OP
91 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
93 #undef TARGET_ASM_FUNCTION_PROLOGUE
94 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
95 #undef TARGET_ASM_FUNCTION_EPILOGUE
96 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
97 #undef TARGET_SCHED_ADJUST_COST
98 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
99 #undef TARGET_SCHED_ISSUE_RATE
100 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
102 struct gcc_target targetm = TARGET_INITIALIZER;
104 /* Sometimes certain combinations of command options do not make
105 sense on a particular target machine. You can define a macro
106 `OVERRIDE_OPTIONS' to take account of this. This macro, if
107 defined, is executed once just after all the command options have
110 Don't use this macro to turn on various extra optimizations for
111 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
117 enum machine_mode mode1, mode2;
119 /* Set up the branch cost information */
120 if (d30v_branch_cost_string)
121 d30v_branch_cost = atoi (d30v_branch_cost_string);
123 /* Set up max # instructions to use with conditional execution */
124 if (d30v_cond_exec_string)
125 d30v_cond_exec = atoi (d30v_cond_exec_string);
127 /* Setup hard_regno_mode_ok/modes_tieable_p */
128 for (mode1 = VOIDmode;
129 (int)mode1 < NUM_MACHINE_MODES;
130 mode1 = (enum machine_mode)((int)mode1 + 1))
132 int size = GET_MODE_SIZE (mode1);
133 int large_p = size > UNITS_PER_WORD;
134 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
136 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
138 if (mode1 == VOIDmode)
141 else if (GPR_P (regno))
146 ok_p = (((regno - GPR_FIRST) & 1) == 0);
149 else if (FLAG_P (regno))
150 ok_p = (mode1 == CCmode);
152 else if (CR_P (regno))
153 ok_p = int_p && !large_p;
155 else if (ACCUM_P (regno))
156 ok_p = (mode1 == DImode);
158 else if (SPECIAL_REG_P (regno))
159 ok_p = (mode1 == SImode);
164 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
167 /* A C expression that is nonzero if it is desirable to choose
168 register allocation so as to avoid move instructions between a
169 value of mode MODE1 and a value of mode MODE2.
171 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
172 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
173 MODE2)' must be zero. */
174 for (mode2 = VOIDmode;
175 (int)mode2 <= NUM_MACHINE_MODES;
176 mode2 = (enum machine_mode)((int)mode2 + 1))
182 else if (GET_MODE_CLASS (mode1) == MODE_INT
183 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
184 && GET_MODE_CLASS (mode2) == MODE_INT
185 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
192 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
197 for (mode1 = VOIDmode;
198 (int)mode1 < NUM_MACHINE_MODES;
199 mode1 = (enum machine_mode)((int)mode1 + 1))
201 for (mode2 = VOIDmode;
202 (int)mode2 <= NUM_MACHINE_MODES;
203 mode2 = (enum machine_mode)((int)mode2 + 1))
205 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
207 && (hard_regno_mode_ok[(int)mode1][regno]
208 != hard_regno_mode_ok[(int)mode2][regno]))
209 error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
210 reg_names[regno], GET_MODE_NAME (mode1),
211 GET_MODE_NAME (mode2));
216 /* A C expression whose value is a register class containing hard
217 register REGNO. In general there is more than one such class;
218 choose a class which is "minimal", meaning that no smaller class
219 also contains the register. */
220 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
222 enum reg_class class;
225 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
226 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
228 else if (regno == FLAG_F0)
231 else if (regno == FLAG_F1)
234 else if (FLAG_P (regno))
235 class = OTHER_FLAG_REGS;
237 else if (ACCUM_P (regno))
240 else if (regno == CR_RPT_C)
243 else if (CR_P (regno))
246 else if (SPECIAL_REG_P (regno))
252 regno_reg_class[regno] = class;
256 static const char *const names[] = REG_CLASS_NAMES;
257 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
258 for (mode1 = VOIDmode;
259 (int)mode1 < NUM_MACHINE_MODES;
260 mode1 = (enum machine_mode)((int)mode1 + 1))
262 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
263 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
265 fprintf (stderr, "\n");
270 /* A C expression which defines the machine-dependent operand
271 constraint letters for register classes. If CHAR is such a
272 letter, the value should be the register class corresponding to
273 it. Otherwise, the value should be `NO_REGS'. The register
274 letter `r', corresponding to class `GENERAL_REGS', will not be
275 passed to this macro; you do not need to handle it.
277 The following letters are unavailable, due to being used as
282 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
283 'Q', 'R', 'S', 'T', 'U'
285 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
287 for (i = 0; i < 256; i++)
288 reg_class_from_letter[i] = NO_REGS;
290 reg_class_from_letter['a'] = ACCUM_REGS;
291 reg_class_from_letter['b'] = BR_FLAG_REGS;
292 reg_class_from_letter['c'] = CR_REGS;
293 reg_class_from_letter['d'] = GPR_REGS;
294 reg_class_from_letter['e'] = EVEN_REGS;
295 reg_class_from_letter['f'] = FLAG_REGS;
296 reg_class_from_letter['l'] = REPEAT_REGS;
297 reg_class_from_letter['x'] = F0_REGS;
298 reg_class_from_letter['y'] = F1_REGS;
299 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
303 /* Return true if a memory operand is a short memory operand. */
306 short_memory_operand (op, mode)
308 enum machine_mode mode;
310 if (GET_CODE (op) != MEM)
313 if (GET_MODE (op) != mode && mode != VOIDmode)
316 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
320 /* Return true if a memory operand is a long operand. */
323 long_memory_operand (op, mode)
325 enum machine_mode mode;
327 if (GET_CODE (op) != MEM)
330 if (GET_MODE (op) != mode && mode != VOIDmode)
333 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
337 /* Return true if a memory operand is valid for the D30V. */
340 d30v_memory_operand (op, mode)
342 enum machine_mode mode;
344 if (GET_CODE (op) != MEM)
347 if (GET_MODE (op) != mode && mode != VOIDmode)
350 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
354 /* Return true if a memory operand uses a single register for the
358 single_reg_memory_operand (op, mode)
360 enum machine_mode mode;
364 if (GET_CODE (op) != MEM)
367 if (GET_MODE (op) != mode && mode != VOIDmode)
371 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
374 if (GET_CODE (addr) == SUBREG)
375 addr = SUBREG_REG (addr);
377 return (GET_CODE (addr) == REG);
380 /* Return true if a memory operand uses a constant address. */
383 const_addr_memory_operand (op, mode)
385 enum machine_mode mode;
387 if (GET_CODE (op) != MEM)
390 if (GET_MODE (op) != mode && mode != VOIDmode)
393 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
396 switch (GET_CODE (XEXP (op, 0)))
411 /* Return true if operand is a memory reference suitable for a call. */
414 call_operand (op, mode)
416 enum machine_mode mode;
418 if (GET_CODE (op) != MEM)
421 if (GET_MODE (op) != mode && mode != VOIDmode)
424 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
427 switch (GET_CODE (XEXP (op, 0)))
433 op = SUBREG_REG (op);
434 if (GET_CODE (op) != REG)
440 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
452 /* Return true if operand is a GPR register. */
455 gpr_operand (op, mode)
457 enum machine_mode mode;
459 if (GET_MODE (op) != mode && mode != VOIDmode)
462 if (GET_CODE (op) == SUBREG)
464 if (GET_CODE (SUBREG_REG (op)) != REG)
465 return register_operand (op, mode);
467 op = SUBREG_REG (op);
470 if (GET_CODE (op) != REG)
473 return GPR_OR_PSEUDO_P (REGNO (op));
476 /* Return true if operand is an accumulator register. */
479 accum_operand (op, mode)
481 enum machine_mode mode;
483 if (GET_MODE (op) != mode && mode != VOIDmode)
486 if (GET_CODE (op) == SUBREG)
488 if (GET_CODE (SUBREG_REG (op)) != REG)
489 return register_operand (op, mode);
491 op = SUBREG_REG (op);
494 if (GET_CODE (op) != REG)
497 return ACCUM_OR_PSEUDO_P (REGNO (op));
500 /* Return true if operand is a GPR or an accumulator register. */
503 gpr_or_accum_operand (op, mode)
505 enum machine_mode mode;
507 if (GET_MODE (op) != mode && mode != VOIDmode)
510 if (GET_CODE (op) == SUBREG)
512 if (GET_CODE (SUBREG_REG (op)) != REG)
513 return register_operand (op, mode);
515 op = SUBREG_REG (op);
518 if (GET_CODE (op) != REG)
521 if (ACCUM_P (REGNO (op)))
524 return GPR_OR_PSEUDO_P (REGNO (op));
527 /* Return true if operand is a CR register. */
530 cr_operand (op, mode)
532 enum machine_mode mode;
534 if (GET_MODE (op) != mode && mode != VOIDmode)
537 if (GET_CODE (op) == SUBREG)
539 if (GET_CODE (SUBREG_REG (op)) != REG)
540 return register_operand (op, mode);
542 op = SUBREG_REG (op);
545 if (GET_CODE (op) != REG)
548 return CR_OR_PSEUDO_P (REGNO (op));
551 /* Return true if operand is the repeat count register. */
554 repeat_operand (op, mode)
556 enum machine_mode mode;
558 if (GET_MODE (op) != mode && mode != VOIDmode)
561 if (GET_CODE (op) == SUBREG)
563 if (GET_CODE (SUBREG_REG (op)) != REG)
564 return register_operand (op, mode);
566 op = SUBREG_REG (op);
569 if (GET_CODE (op) != REG)
572 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
575 /* Return true if operand is a FLAG register. */
578 flag_operand (op, mode)
580 enum machine_mode mode;
582 if (GET_MODE (op) != mode && mode != VOIDmode)
585 if (GET_CODE (op) == SUBREG)
587 if (GET_CODE (SUBREG_REG (op)) != REG)
588 return register_operand (op, mode);
590 op = SUBREG_REG (op);
593 if (GET_CODE (op) != REG)
596 return FLAG_OR_PSEUDO_P (REGNO (op));
599 /* Return true if operand is either F0 or F1. */
602 br_flag_operand (op, mode)
604 enum machine_mode mode;
606 if (GET_MODE (op) != mode && mode != VOIDmode)
609 if (GET_CODE (op) == SUBREG)
611 if (GET_CODE (SUBREG_REG (op)) != REG)
612 return register_operand (op, mode);
614 op = SUBREG_REG (op);
617 if (GET_CODE (op) != REG)
620 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
623 /* Return true if operand is either F0/F1 or the constants 0/1. */
626 br_flag_or_constant_operand (op, mode)
628 enum machine_mode mode;
630 if (GET_MODE (op) != mode && mode != VOIDmode)
633 if (GET_CODE (op) == SUBREG)
635 if (GET_CODE (SUBREG_REG (op)) != REG)
636 return register_operand (op, mode);
638 op = SUBREG_REG (op);
641 if (GET_CODE (op) == CONST_INT)
642 return (INTVAL (op) == 0 || INTVAL (op) == 1);
644 if (GET_CODE (op) != REG)
647 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
650 /* Return true if operand is either F0 or F1, or a GPR register. */
653 gpr_or_br_flag_operand (op, mode)
655 enum machine_mode mode;
657 if (GET_MODE (op) != mode && mode != VOIDmode)
660 if (GET_CODE (op) == SUBREG)
662 if (GET_CODE (SUBREG_REG (op)) != REG)
663 return register_operand (op, mode);
665 op = SUBREG_REG (op);
668 if (GET_CODE (op) != REG)
671 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
674 /* Return true if operand is the F0 register. */
677 f0_operand (op, mode)
679 enum machine_mode mode;
681 if (GET_MODE (op) != mode && mode != VOIDmode)
684 if (GET_CODE (op) == SUBREG)
686 if (GET_CODE (SUBREG_REG (op)) != REG)
687 return register_operand (op, mode);
689 op = SUBREG_REG (op);
692 if (GET_CODE (op) != REG)
695 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
698 /* Return true if operand is the F1 register. */
701 f1_operand (op, mode)
703 enum machine_mode mode;
705 if (GET_MODE (op) != mode && mode != VOIDmode)
708 if (GET_CODE (op) == SUBREG)
710 if (GET_CODE (SUBREG_REG (op)) != REG)
711 return register_operand (op, mode);
713 op = SUBREG_REG (op);
716 if (GET_CODE (op) != REG)
719 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
722 /* Return true if operand is the F1 register. */
725 carry_operand (op, mode)
727 enum machine_mode mode;
729 if (GET_MODE (op) != mode && mode != VOIDmode)
732 if (GET_CODE (op) == SUBREG)
734 if (GET_CODE (SUBREG_REG (op)) != REG)
735 return register_operand (op, mode);
737 op = SUBREG_REG (op);
740 if (GET_CODE (op) != REG)
743 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
746 /* Return true if operand is a register of any flavor or a 0 of the
750 reg_or_0_operand (op, mode)
752 enum machine_mode mode;
754 switch (GET_CODE (op))
761 if (GET_MODE (op) != mode && mode != VOIDmode)
764 return register_operand (op, mode);
767 return INTVAL (op) == 0;
770 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
776 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
779 gpr_or_signed6_operand (op, mode)
781 enum machine_mode mode;
783 if (GET_CODE (op) == SUBREG)
785 if (GET_CODE (SUBREG_REG (op)) != REG)
786 return register_operand (op, mode);
788 op = SUBREG_REG (op);
791 if (GET_CODE (op) == CONST_INT)
792 return IN_RANGE_P (INTVAL (op), -32, 31);
794 if (GET_CODE (op) != REG)
797 if (GET_MODE (op) != mode && mode != VOIDmode)
800 return GPR_OR_PSEUDO_P (REGNO (op));
803 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
806 gpr_or_unsigned5_operand (op, mode)
808 enum machine_mode mode;
810 if (GET_CODE (op) == SUBREG)
812 if (GET_CODE (SUBREG_REG (op)) != REG)
813 return register_operand (op, mode);
815 op = SUBREG_REG (op);
818 if (GET_CODE (op) == CONST_INT)
819 return IN_RANGE_P (INTVAL (op), 0, 31);
821 if (GET_CODE (op) != REG)
824 if (GET_MODE (op) != mode && mode != VOIDmode)
827 return GPR_OR_PSEUDO_P (REGNO (op));
830 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
833 gpr_or_unsigned6_operand (op, mode)
835 enum machine_mode mode;
837 if (GET_CODE (op) == SUBREG)
839 if (GET_CODE (SUBREG_REG (op)) != REG)
840 return register_operand (op, mode);
842 op = SUBREG_REG (op);
845 if (GET_CODE (op) == CONST_INT)
846 return IN_RANGE_P (INTVAL (op), 0, 63);
848 if (GET_CODE (op) != REG)
851 if (GET_MODE (op) != mode && mode != VOIDmode)
854 return GPR_OR_PSEUDO_P (REGNO (op));
857 /* Return true if operand is a GPR register or a constant of some form. */
860 gpr_or_constant_operand (op, mode)
862 enum machine_mode mode;
864 switch (GET_CODE (op))
876 if (GET_CODE (SUBREG_REG (op)) != REG)
877 return register_operand (op, mode);
879 op = SUBREG_REG (op);
883 if (GET_MODE (op) != mode && mode != VOIDmode)
886 return GPR_OR_PSEUDO_P (REGNO (op));
892 /* Return true if operand is a GPR register or a constant of some form,
893 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
896 gpr_or_dbl_const_operand (op, mode)
898 enum machine_mode mode;
900 switch (GET_CODE (op))
913 if (GET_CODE (SUBREG_REG (op)) != REG)
914 return register_operand (op, mode);
916 op = SUBREG_REG (op);
920 if (GET_MODE (op) != mode && mode != VOIDmode)
923 return GPR_OR_PSEUDO_P (REGNO (op));
929 /* Return true if operand is a gpr register or a valid memory operation. */
932 gpr_or_memory_operand (op, mode)
934 enum machine_mode mode;
936 switch (GET_CODE (op))
942 if (GET_CODE (SUBREG_REG (op)) != REG)
943 return register_operand (op, mode);
945 op = SUBREG_REG (op);
949 if (GET_MODE (op) != mode && mode != VOIDmode)
952 return GPR_OR_PSEUDO_P (REGNO (op));
955 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
961 /* Return true if operand is something that can be an input for a move
965 move_input_operand (op, mode)
967 enum machine_mode mode;
972 switch (GET_CODE (op))
985 if (GET_MODE (op) != mode && mode != VOIDmode)
988 subreg = SUBREG_REG (op);
989 code = GET_CODE (subreg);
991 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
994 return (code == REG);
997 if (GET_MODE (op) != mode && mode != VOIDmode)
1003 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1005 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1012 /* Return true if operand is something that can be an output for a move
1016 move_output_operand (op, mode)
1018 enum machine_mode mode;
1023 switch (GET_CODE (op))
1029 if (GET_MODE (op) != mode && mode != VOIDmode)
1032 subreg = SUBREG_REG (op);
1033 code = GET_CODE (subreg);
1035 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1038 return (code == REG);
1041 if (GET_MODE (op) != mode && mode != VOIDmode)
1047 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1049 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1056 /* Return true if operand is a signed 6 bit immediate. */
1059 signed6_operand (op, mode)
1061 enum machine_mode mode ATTRIBUTE_UNUSED;
1063 if (GET_CODE (op) == CONST_INT)
1064 return IN_RANGE_P (INTVAL (op), -32, 31);
1069 /* Return true if operand is an unsigned 5 bit immediate. */
1072 unsigned5_operand (op, mode)
1074 enum machine_mode mode ATTRIBUTE_UNUSED;
1076 if (GET_CODE (op) == CONST_INT)
1077 return IN_RANGE_P (INTVAL (op), 0, 31);
1082 /* Return true if operand is an unsigned 6 bit immediate. */
1085 unsigned6_operand (op, mode)
1087 enum machine_mode mode ATTRIBUTE_UNUSED;
1089 if (GET_CODE (op) == CONST_INT)
1090 return IN_RANGE_P (INTVAL (op), 0, 63);
1095 /* Return true if operand is a constant with a single bit set. */
1098 bitset_operand (op, mode)
1100 enum machine_mode mode ATTRIBUTE_UNUSED;
1102 if (GET_CODE (op) == CONST_INT)
1103 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1108 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1109 used in conditional execution. */
1112 condexec_test_operator (op, mode)
1114 enum machine_mode mode;
1118 if (GET_MODE (op) != mode && mode != VOIDmode)
1121 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1125 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1129 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1135 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1136 register that can be used in a branch instruction. */
1139 condexec_branch_operator (op, mode)
1141 enum machine_mode mode;
1145 if (GET_MODE (op) != mode && mode != VOIDmode)
1148 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1152 if (GET_CODE (x0) == REG)
1154 int regno = REGNO (x0);
1155 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1158 /* Allow the optimizer to generate things like:
1159 (if_then_else (ne (const_int 1) (const_int 0))) */
1160 else if (GET_CODE (x0) != CONST_INT)
1164 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1170 /* Return true if the unary operator can be executed with conditional
1174 condexec_unary_operator (op, mode)
1176 enum machine_mode mode ATTRIBUTE_UNUSED;
1180 /* Only do this after register allocation, so that we can look at the register # */
1181 if (!reload_completed)
1184 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1188 if (GET_CODE (op0) == SUBREG)
1189 op0 = SUBREG_REG (op0);
1191 switch (GET_CODE (op))
1198 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1207 /* Return true if the add or subtraction can be executed with conditional
1211 condexec_addsub_operator (op, mode)
1213 enum machine_mode mode ATTRIBUTE_UNUSED;
1217 /* Only do this after register allocation, so that we can look at the register # */
1218 if (!reload_completed)
1221 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1227 if (GET_CODE (op0) == SUBREG)
1228 op0 = SUBREG_REG (op0);
1230 if (GET_CODE (op1) == SUBREG)
1231 op1 = SUBREG_REG (op1);
1233 if (GET_CODE (op0) != REG)
1236 switch (GET_CODE (op))
1243 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1244 && gpr_or_constant_operand (op1, SImode));
1250 /* Return true if the binary operator can be executed with conditional
1251 execution. We don't include add/sub here, since they have extra
1252 clobbers for the flags registers. */
1255 condexec_binary_operator (op, mode)
1257 enum machine_mode mode ATTRIBUTE_UNUSED;
1261 /* Only do this after register allocation, so that we can look at the register # */
1262 if (!reload_completed)
1265 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1271 if (GET_CODE (op0) == SUBREG)
1272 op0 = SUBREG_REG (op0);
1274 if (GET_CODE (op1) == SUBREG)
1275 op1 = SUBREG_REG (op1);
1277 if (GET_CODE (op0) != REG)
1280 /* MULT is not included here, because it is an IU only instruction. */
1281 switch (GET_CODE (op))
1292 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1293 && gpr_or_constant_operand (op1, SImode));
1297 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1298 && GET_CODE (op1) == CONST_INT);
1304 /* Return true if the shift/rotate left operator can be executed with
1305 conditional execution. */
1308 condexec_shiftl_operator (op, mode)
1310 enum machine_mode mode ATTRIBUTE_UNUSED;
1314 /* Only do this after register allocation, so that we can look at the register # */
1315 if (!reload_completed)
1318 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1324 if (GET_CODE (op0) == SUBREG)
1325 op0 = SUBREG_REG (op0);
1327 if (GET_CODE (op1) == SUBREG)
1328 op1 = SUBREG_REG (op1);
1330 if (GET_CODE (op0) != REG)
1333 switch (GET_CODE (op))
1340 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1341 && GET_CODE (op1) == NEG
1342 && GET_CODE (XEXP (op1, 0)) == REG
1343 && GPR_P (REGNO (XEXP (op1, 0))));
1349 /* Return true if the {sign,zero} extend operator from memory can be
1350 conditionally executed. */
1353 condexec_extend_operator (op, mode)
1355 enum machine_mode mode ATTRIBUTE_UNUSED;
1357 /* Only do this after register allocation, so that we can look at the register # */
1358 if (!reload_completed)
1361 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1364 switch (GET_CODE (op))
1371 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1372 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1373 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1382 /* Return true for comparisons against 0 that can be turned into a
1383 bratnz/bratzr instruction. */
1386 branch_zero_operator (op, mode)
1388 enum machine_mode mode;
1392 if (GET_MODE (op) != mode && mode != VOIDmode)
1395 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1399 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1403 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1409 /* Return true if an operand is simple, suitable for use as the destination of
1410 a conditional move */
1413 cond_move_dest_operand (op, mode)
1415 enum machine_mode mode ATTRIBUTE_UNUSED;
1419 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1422 switch (GET_CODE (op))
1429 return gpr_operand (op, mode);
1431 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1433 addr = XEXP (op, 0);
1434 return (GET_CODE (addr) != POST_DEC
1435 && GET_CODE (addr) != POST_INC
1436 && d30v_legitimate_address_p (mode, addr, reload_completed));
1442 /* Return true if an operand is simple, suitable for use in a conditional move */
1445 cond_move_operand (op, mode)
1447 enum machine_mode mode ATTRIBUTE_UNUSED;
1451 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1454 switch (GET_CODE (op))
1461 return gpr_operand (op, mode);
1464 return GET_MODE (op) == SFmode;
1472 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1474 addr = XEXP (op, 0);
1475 return (GET_CODE (addr) != POST_DEC
1476 && GET_CODE (addr) != POST_INC
1477 && d30v_legitimate_address_p (mode, addr, reload_completed));
1483 /* Return true if an operand is simple, suitable for use in conditional execution.
1484 Unlike cond_move, we can allow auto inc/dec. */
1487 cond_exec_operand (op, mode)
1489 enum machine_mode mode;
1491 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1494 switch (GET_CODE (op))
1501 return gpr_operand (op, mode);
1504 return GET_MODE (op) == SFmode;
1513 return memory_operand (op, mode);
1519 /* Return true if operand is a SI mode signed relational test. */
1522 srelational_si_operator (op, mode)
1524 enum machine_mode mode;
1528 if (GET_MODE (op) != mode && mode != VOIDmode)
1531 switch (GET_CODE (op))
1546 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1549 if (GET_MODE (x0) != SImode)
1553 switch (GET_CODE (x1))
1570 /* Return true if operand is a SI mode unsigned relational test. */
1573 urelational_si_operator (op, mode)
1575 enum machine_mode mode;
1579 if (GET_MODE (op) != mode && mode != VOIDmode)
1582 switch (GET_CODE (op))
1595 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1598 if (GET_MODE (x0) != SImode)
1602 switch (GET_CODE (x1))
1619 /* Return true if operand is a DI mode relational test. */
1622 relational_di_operator (op, mode)
1624 enum machine_mode mode;
1628 if (GET_MODE (op) != mode && mode != VOIDmode)
1631 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1635 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1638 if (GET_MODE (x0) != DImode)
1642 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1643 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1650 /* Calculate the stack information for the current function.
1652 D30V stack frames look like:
1655 +-------------------------------+
1656 | Argument word #19 |
1657 +-------------------------------+
1658 | Argument word #18 |
1659 +-------------------------------+
1660 | Argument word #17 |
1661 +-------------------------------+
1662 | Argument word #16 |
1663 Prev sp +-------------------------------+
1665 | Save for arguments 1..16 if |
1666 | the func. uses stdarg/varargs |
1668 +-------------------------------+
1670 | Save area for GPR registers |
1672 +-------------------------------+
1674 | Save area for accumulators |
1676 +-------------------------------+
1680 +-------------------------------+
1682 | alloca space if used |
1684 +-------------------------------+
1686 | Space for outgoing arguments |
1688 low SP----> +-------------------------------+
1694 static d30v_stack_t info, zero_info;
1695 d30v_stack_t *info_ptr = &info;
1696 tree fndecl = current_function_decl;
1697 tree fntype = TREE_TYPE (fndecl);
1705 unsigned char save_gpr_p[GPR_LAST];
1708 /* If we've already calculated the values and reload is complete, just return now */
1709 if (d30v_stack_cache)
1710 return d30v_stack_cache;
1712 /* Zero all fields */
1715 if (current_function_profile)
1716 regs_ever_live[GPR_LINK] = 1;
1718 /* Determine if this is a stdarg function */
1719 if (TYPE_ARG_TYPES (fntype) != 0
1720 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1724 /* Find the last argument, and see if it is __builtin_va_alist. */
1725 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1727 next_arg = TREE_CHAIN (cur_arg);
1728 if (next_arg == (tree)0)
1730 if (DECL_NAME (cur_arg)
1731 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1739 /* Calculate which registers need to be saved & save area size */
1743 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1745 if (regs_ever_live[i] && !call_used_regs[i])
1747 info_ptr->save_p[i] = 2;
1754 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1756 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1765 /* Determine which register pairs can be saved together with ld2w/st2w */
1766 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1768 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1771 info_ptr->save_p[i++] = 2;
1773 else if (save_gpr_p[i])
1776 info_ptr->save_p[i] = 1;
1780 /* Determine various sizes */
1781 info_ptr->varargs_p = varargs_p;
1782 info_ptr->varargs_size = ((varargs_p)
1783 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1786 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1787 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1788 2 * UNITS_PER_WORD);
1789 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1790 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1791 2 * UNITS_PER_WORD);
1793 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1794 + info_ptr->accum_size
1795 + info_ptr->vars_size
1796 + info_ptr->parm_size
1797 + info_ptr->varargs_size
1798 + current_function_pretend_args_size),
1799 (STACK_BOUNDARY / BITS_PER_UNIT));
1801 info_ptr->save_offset = (info_ptr->total_size
1802 - (current_function_pretend_args_size
1803 + info_ptr->varargs_size
1804 + info_ptr->gpr_size
1805 + info_ptr->accum_size));
1807 /* The link register is the last GPR saved, but there might be some padding
1808 bytes after it, so account for that. */
1809 info_ptr->link_offset = (info_ptr->total_size
1810 - (current_function_pretend_args_size
1811 + info_ptr->varargs_size
1812 + (info_ptr->gpr_size
1813 - UNITS_PER_WORD * saved_gprs)
1816 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1817 info_ptr->memrefs_2words = memrefs_2words;
1818 info_ptr->memrefs_1word = memrefs_1word;
1820 if (reload_completed)
1821 d30v_stack_cache = info_ptr;
1827 /* Internal function to print all of the information about the stack */
1830 debug_stack_info (info)
1836 info = d30v_stack_info ();
1838 fprintf (stderr, "\nStack information for function %s:\n",
1839 ((current_function_decl && DECL_NAME (current_function_decl))
1840 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1843 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1844 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1845 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1846 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1847 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1848 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1849 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1850 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1851 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1852 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1853 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1854 fprintf (stderr, "\tsaved registers =");
1856 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1858 if (info->save_p[i] == 2)
1860 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1863 else if (info->save_p[i])
1864 fprintf (stderr, " %s", reg_names[i]);
1867 putc ('\n', stderr);
1872 /* Return nonzero if this function is known to have a null or 1 instruction epilogue. */
1877 if (reload_completed)
1879 d30v_stack_t *info = d30v_stack_info ();
1881 /* If no epilogue code is needed, can use just a simple jump */
1882 if (info->total_size == 0)
1886 /* If just a small amount of local stack was allocated and no registers
1887 saved, skip forward branch */
1888 if (info->total_size == info->vars_size
1889 && IN_RANGE_P (info->total_size, 1, 31))
1898 /* A C statement (sans semicolon) for initializing the variable CUM for the
1899 state at the beginning of the argument list. The variable has type
1900 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1901 of the function which will receive the args, or 0 if the args are to a
1902 compiler support library function. The value of INDIRECT is nonzero when
1903 processing an indirect call, for example a call through a function pointer.
1904 The value of INDIRECT is zero for a call to an explicitly named function, a
1905 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1906 arguments for the function being compiled.
1908 When processing a call to a compiler support library function, LIBNAME
1909 identifies which one. It is a `symbol_ref' rtx which contains the name of
1910 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1911 being processed. Thus, each time this macro is called, either LIBNAME or
1912 FNTYPE is nonzero, but never both of them at once. */
1915 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1916 CUMULATIVE_ARGS *cum;
1922 *cum = GPR_ARG_FIRST;
1924 if (TARGET_DEBUG_ARG)
1926 fprintf (stderr, "\ninit_cumulative_args:");
1928 fputs (" indirect", stderr);
1931 fputs (" incoming", stderr);
1935 tree ret_type = TREE_TYPE (fntype);
1936 fprintf (stderr, " return=%s,",
1937 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1940 if (libname && GET_CODE (libname) == SYMBOL_REF)
1941 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1943 putc ('\n', stderr);
1948 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1949 argument with the specified mode and type. If it is not defined,
1950 `PARM_BOUNDARY' is used for all arguments. */
1953 d30v_function_arg_boundary (mode, type)
1954 enum machine_mode mode;
1957 int size = ((mode == BLKmode && type)
1958 ? int_size_in_bytes (type)
1959 : (int) GET_MODE_SIZE (mode));
1961 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1965 /* A C expression that controls whether a function argument is passed in a
1966 register, and which register.
1968 The arguments are CUM, which summarizes all the previous arguments; MODE,
1969 the machine mode of the argument; TYPE, the data type of the argument as a
1970 tree node or 0 if that is not known (which happens for C support library
1971 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1972 nameless arguments that correspond to `...' in the called function's
1975 The value of the expression should either be a `reg' RTX for the hard
1976 register in which to pass the argument, or zero to pass the argument on the
1979 For machines like the VAX and 68000, where normally all arguments are
1980 pushed, zero suffices as a definition.
1982 The usual way to make the ANSI library `stdarg.h' work on a machine where
1983 some arguments are usually passed in registers, is to cause nameless
1984 arguments to be passed on the stack instead. This is done by making
1985 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1987 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1988 this macro to determine if this argument is of a type that must be passed in
1989 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1990 returns nonzero for such an argument, the compiler will abort. If
1991 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1992 stack and then loaded into a register. */
1995 d30v_function_arg (cum, mode, type, named, incoming)
1996 CUMULATIVE_ARGS *cum;
1997 enum machine_mode mode;
2000 int incoming ATTRIBUTE_UNUSED;
2002 int size = ((mode == BLKmode && type)
2003 ? int_size_in_bytes (type)
2004 : (int) GET_MODE_SIZE (mode));
2005 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2008 /* Return a marker for use in the call instruction. */
2009 if (mode == VOIDmode)
2012 else if (*cum + adjust <= GPR_ARG_LAST)
2013 ret = gen_rtx (REG, mode, *cum + adjust);
2018 if (TARGET_DEBUG_ARG)
2020 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2021 *cum, GET_MODE_NAME (mode), named, size, adjust,
2022 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2028 /* A C expression for the number of words, at the beginning of an argument,
2029 must be put in registers. The value must be zero for arguments that are
2030 passed entirely in registers or that are entirely pushed on the stack.
2032 On some machines, certain arguments must be passed partially in registers
2033 and partially in memory. On these machines, typically the first N words of
2034 arguments are passed in registers, and the rest on the stack. If a
2035 multi-word argument (a `double' or a structure) crosses that boundary, its
2036 first few words must be passed in registers and the rest must be pushed.
2037 This macro tells the compiler when this occurs, and how many of the words
2038 should go in registers.
2040 `FUNCTION_ARG' for these arguments should return the first register to be
2041 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2042 the called function. */
2045 d30v_function_arg_partial_nregs (cum, mode, type, named)
2046 CUMULATIVE_ARGS *cum;
2047 enum machine_mode mode;
2049 int named ATTRIBUTE_UNUSED;
2051 int bytes = ((mode == BLKmode)
2052 ? int_size_in_bytes (type)
2053 : (int) GET_MODE_SIZE (mode));
2054 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2055 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2056 int arg_num = *cum + adjust;
2059 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2060 ? GPR_ARG_LAST - arg_num + 1
2063 if (TARGET_DEBUG_ARG && ret)
2064 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2070 /* A C expression that indicates when an argument must be passed by reference.
2071 If nonzero for an argument, a copy of that argument is made in memory and a
2072 pointer to the argument is passed instead of the argument itself. The
2073 pointer is passed in whatever way is appropriate for passing a pointer to
2076 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2077 definition of this macro might be
2078 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2079 (CUM, MODE, TYPE, NAMED) \
2080 MUST_PASS_IN_STACK (MODE, TYPE) */
2083 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2084 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2085 enum machine_mode mode;
2087 int named ATTRIBUTE_UNUSED;
2089 int ret = MUST_PASS_IN_STACK (mode, type);
2091 if (TARGET_DEBUG_ARG && ret)
2092 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2098 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2099 advance past an argument in the argument list. The values MODE, TYPE and
2100 NAMED describe that argument. Once this is done, the variable CUM is
2101 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2103 This macro need not do anything if the argument in question was passed on
2104 the stack. The compiler knows how to track the amount of stack space used
2105 for arguments without any special help. */
2108 d30v_function_arg_advance (cum, mode, type, named)
2109 CUMULATIVE_ARGS *cum;
2110 enum machine_mode mode;
2114 int bytes = ((mode == BLKmode)
2115 ? int_size_in_bytes (type)
2116 : (int) GET_MODE_SIZE (mode));
2117 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2118 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2120 *cum += words + adjust;
2122 if (TARGET_DEBUG_ARG)
2124 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2125 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2129 /* If defined, is a C expression that produces the machine-specific code for a
2130 call to `__builtin_saveregs'. This code will be moved to the very beginning
2131 of the function, before any parameter access are made. The return value of
2132 this function should be an RTX that contains the value to use as the return
2133 of `__builtin_saveregs'.
2135 If this macro is not defined, the compiler will output an ordinary call to
2136 the library function `__builtin_saveregs'. */
2139 d30v_expand_builtin_saveregs ()
2141 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2143 if (TARGET_DEBUG_ARG)
2144 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2147 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2151 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2152 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2153 arguments into the stack so that all the arguments appear to have been
2154 passed consecutively on the stack. Once this is done, you can use the
2155 standard implementation of varargs that works for machines that pass all
2156 their arguments on the stack.
2158 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2159 the values that obtain after processing of the named arguments. The
2160 arguments MODE and TYPE describe the last named argument--its machine mode
2161 and its data type as a tree node.
2163 The macro implementation should do two things: first, push onto the stack
2164 all the argument registers *not* used for the named arguments, and second,
2165 store the size of the data thus pushed into the `int'-valued variable whose
2166 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2167 store here will serve as additional offset for setting up the stack frame.
2169 Because you must generate code to push the anonymous arguments at compile
2170 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2171 useful on machines that have just a single category of argument register and
2172 use it uniformly for all data types.
2174 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2175 function are being analyzed for the second time. This happens for an inline
2176 function, which is not actually compiled until the end of the source file.
2177 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2181 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2182 CUMULATIVE_ARGS *cum;
2183 enum machine_mode mode;
2184 tree type ATTRIBUTE_UNUSED;
2185 int *pretend_size ATTRIBUTE_UNUSED;
2188 if (TARGET_DEBUG_ARG)
2190 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2191 *cum, GET_MODE_NAME (mode), second_time);
2195 /* Create the va_list data type. */
2198 d30v_build_va_list ()
2200 tree f_arg_ptr, f_arg_num, record, type_decl;
2203 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2204 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2205 int_type_node = make_signed_type (INT_TYPE_SIZE);
2207 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2209 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2212 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2213 DECL_FIELD_CONTEXT (f_arg_num) = record;
2215 TREE_CHAIN (record) = type_decl;
2216 TYPE_NAME (record) = type_decl;
2217 TYPE_FIELDS (record) = f_arg_ptr;
2218 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2220 layout_type (record);
2222 /* The correct type is an array type of one element. */
2223 return build_array_type (record, build_index_type (size_zero_node));
2227 /* Expand __builtin_va_start to do the va_start macro. */
2230 d30v_expand_builtin_va_start (valist, nextarg)
2232 rtx nextarg ATTRIBUTE_UNUSED;
2234 HOST_WIDE_INT words;
2235 tree f_arg_ptr, f_arg_num;
2236 tree arg_ptr, arg_num, saveregs, t;
2238 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2239 f_arg_num = TREE_CHAIN (f_arg_ptr);
2241 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2242 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2243 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2245 words = current_function_args_info; /* __builtin_args_info (0) */
2247 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2248 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2249 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2250 TREE_SIDE_EFFECTS (t) = 1;
2251 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2253 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2254 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2255 build_int_2 (-GPR_ARG_FIRST, 0));
2256 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2257 TREE_SIDE_EFFECTS (t) = 1;
2258 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2262 /* Expand __builtin_va_arg to do the va_arg macro. */
2265 d30v_expand_builtin_va_arg(valist, type)
2269 tree f_arg_ptr, f_arg_num;
2270 tree arg_ptr, arg_num, t, ptr;
2272 rtx lab_false, ptr_rtx, r;
2274 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2275 f_arg_num = TREE_CHAIN (f_arg_ptr);
2277 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2278 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2279 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2281 size = int_size_in_bytes (type);
2283 lab_false = gen_label_rtx ();
2284 ptr_rtx = gen_reg_rtx (Pmode);
2286 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2287 (AP)->__va_arg_num++; */
2289 if (size > UNITS_PER_WORD)
2291 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2292 build_int_2 (1, 0));
2294 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2295 GEN_INT (0), EQ, const1_rtx, QImode, 1,
2298 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2299 build_int_2 (1, 0));
2300 TREE_SIDE_EFFECTS (t) = 1;
2301 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2303 emit_label (lab_false);
2307 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2308 + (AP)->__va_arg_num))); */
2310 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2311 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2313 /* if (sizeof (TYPE) < 4)
2314 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2316 if (size < UNITS_PER_WORD)
2317 t = build (PLUS_EXPR, ptr_type_node, t,
2318 build_int_2 (UNITS_PER_WORD - size, 0));
2320 TREE_SIDE_EFFECTS (t) = 1;
2322 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2323 t = build (MODIFY_EXPR, type, ptr, t);
2325 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2327 emit_move_insn (ptr_rtx, r);
2330 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2331 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2332 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2333 build_int_2 (num, 0));
2334 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2339 /* Generate the assembly code for function entry. FILE is a stdio
2340 stream to output the code to. SIZE is an int: how many units of
2341 temporary storage to allocate.
2343 Refer to the array `regs_ever_live' to determine which registers to
2344 save; `regs_ever_live[I]' is nonzero if register number I is ever
2345 used in the function. This function is responsible for knowing
2346 which registers should not be saved even if used. */
2349 d30v_output_function_prologue (stream, size)
2350 FILE *stream ATTRIBUTE_UNUSED;
2351 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2353 /* For the d30v, move all of the prologue processing into separate
2358 /* Called after register allocation to add any instructions needed for
2359 the prologue. Using a prologue insn is favored compared to putting
2360 all of the instructions in output_function_prologue (), since it
2361 allows the scheduler to intermix instructions with the saves of the
2362 caller saved registers. In some cases, it might be necessary to
2363 emit a barrier instruction as the last insn to prevent such
2367 d30v_expand_prologue ()
2369 rtx sp = stack_pointer_rtx;
2370 d30v_stack_t *info = d30v_stack_info ();
2372 rtx mem_di = NULL_RTX;
2373 rtx mem_si = NULL_RTX;
2374 int num_memrefs = (info->memrefs_2words
2375 + info->memrefs_1word
2376 + info->memrefs_varargs);
2378 if (TARGET_DEBUG_STACK)
2379 debug_stack_info (info);
2381 /* Grow the stack. */
2382 if (info->total_size)
2383 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2385 /* If there is more than one save, use post-increment addressing which will
2386 result in smaller code, than would the normal references. If there is
2387 only one save, just do the store as normal. */
2389 if (num_memrefs > 1)
2391 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2392 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2393 mem_di = gen_rtx (MEM, DImode, post_inc);
2394 mem_si = gen_rtx (MEM, SImode, post_inc);
2395 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2397 else if (num_memrefs == 1)
2399 rtx addr = plus_constant (sp, info->save_offset);
2400 mem_di = gen_rtx (MEM, DImode, addr);
2401 mem_si = gen_rtx (MEM, SImode, addr);
2404 /* Save the accumulators. */
2405 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2406 if (info->save_p[i])
2408 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2409 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2410 emit_insn (gen_movdi (mem_di, acc_tmp));
2413 /* Save the GPR registers that are adjacent to each other with st2w. */
2414 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2415 if (info->save_p[i] == 2)
2416 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2418 /* Save the GPR registers that need to be saved with a single word store. */
2419 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2420 if (info->save_p[i] == 1)
2421 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2423 /* Save the argument registers if this function accepts variable args. */
2424 if (info->varargs_p)
2426 /* Realign r22 if an odd # of GPRs were saved. */
2427 if ((info->memrefs_1word & 1) != 0)
2429 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2430 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2433 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2434 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2437 /* Update the frame pointer. */
2438 if (frame_pointer_needed)
2439 emit_move_insn (frame_pointer_rtx, sp);
2441 /* Hack for now, to prevent scheduler from being too cleaver */
2442 emit_insn (gen_blockage ());
2446 /* This function generates the assembly code for function exit.
2447 Args are as for output_function_prologue ().
2449 The function epilogue should not depend on the current stack
2450 pointer! It should use the frame pointer only. This is mandatory
2451 because of alloca; we also take advantage of it to omit stack
2452 adjustments before returning. */
2455 d30v_output_function_epilogue (stream, size)
2456 FILE *stream ATTRIBUTE_UNUSED;
2457 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2459 /* For the d30v, move all processing to be as insns, but do any
2460 cleanup here, since it is done after handling all of the insns. */
2461 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2466 /* Called after register allocation to add any instructions needed for
2467 the epilogue. Using an epilogue insn is favored compared to putting
2468 all of the instructions in output_function_prologue(), since it
2469 allows the scheduler to intermix instructions with the saves of the
2470 caller saved registers. In some cases, it might be necessary to
2471 emit a barrier instruction as the last insn to prevent such
2475 d30v_expand_epilogue ()
2477 rtx sp = stack_pointer_rtx;
2478 d30v_stack_t *info = d30v_stack_info ();
2480 rtx mem_di = NULL_RTX;
2481 rtx mem_si = NULL_RTX;
2485 /* Hack for now, to prevent scheduler from being too cleaver */
2486 emit_insn (gen_blockage ());
2488 /* Restore sp from fp. */
2489 if (frame_pointer_needed)
2490 emit_move_insn (sp, frame_pointer_rtx);
2492 /* For the epilogue, use post-increment addressing all of the time. First
2493 adjust the sp, to eliminate all of the stack, except for the save area. */
2495 if (info->save_offset)
2496 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2498 post_inc = gen_rtx (POST_INC, Pmode, sp);
2499 mem_di = gen_rtx (MEM, DImode, post_inc);
2500 mem_si = gen_rtx (MEM, SImode, post_inc);
2502 /* Restore the accumulators. */
2503 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2504 if (info->save_p[i])
2506 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2507 emit_insn (gen_movdi (acc_tmp, mem_di));
2508 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2511 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2512 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2513 if (info->save_p[i] == 2)
2514 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2516 /* Save the GPR registers that need to be saved with a single word store. */
2518 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2519 if (info->save_p[i] == 1)
2521 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2527 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2530 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2534 /* Release any remaining stack that was allocated for saving the
2535 varargs registers or because an odd # of registers were stored. */
2536 if ((info->memrefs_1word & 1) != 0)
2537 extra_stack += UNITS_PER_WORD;
2538 extra_stack += current_function_pretend_args_size + info->varargs_size;
2542 if (cfun->machine->eh_epilogue_sp_ofs)
2543 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2544 cfun->machine->eh_epilogue_sp_ofs,
2545 GEN_INT (extra_stack)));
2547 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2549 if (cfun->machine->eh_epilogue_sp_ofs)
2550 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2552 /* Now emit the return instruction. */
2553 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2557 /* A C statement or compound statement to output to FILE some assembler code to
2558 call the profiling subroutine `mcount'. Before calling, the assembler code
2559 must load the address of a counter variable into a register where `mcount'
2560 expects to find the address. The name of this variable is `LP' followed by
2561 the number LABELNO, so you would generate the name using `LP%d' in a
2564 The details of how the address should be passed to `mcount' are determined
2565 by your operating system environment, not by GNU CC. To figure them out,
2566 compile a small program for profiling using the system's installed C
2567 compiler and look at the assembler code that results. */
2570 d30v_function_profiler (stream, labelno)
2572 int labelno ATTRIBUTE_UNUSED;
2574 fprintf (stream, "# profile\n");
2578 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2579 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2580 the wrong part for floating point in cross compilers, and split_double does
2581 not handle registers. Also abort if the register is not a general purpose
2585 d30v_split_double (value, p_high, p_low)
2593 if (!reload_completed)
2596 switch (GET_CODE (value))
2599 if (GET_CODE (SUBREG_REG (value)) != REG)
2601 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2602 GET_MODE (SUBREG_REG (value)),
2603 SUBREG_BYTE (value),
2605 value = SUBREG_REG (value);
2610 regno = REGNO (value) + offset;
2614 *p_high = gen_rtx (REG, SImode, regno);
2615 *p_low = gen_rtx (REG, SImode, regno+1);
2620 split_double (value, p_high, p_low);
2629 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2630 for an instruction operand that is a memory reference whose address is X. X
2631 is an RTL expression. */
2634 d30v_print_operand_address (stream, x)
2638 if (GET_CODE (x) == MEM)
2641 switch (GET_CODE (x))
2647 fputs (reg_names[ REGNO (x) ], stream);
2651 fprintf (stream, "%ld", (long) INTVAL (x));
2654 /* We wrap simple symbol refs inside a parenthesis, so that a name
2655 like `r2' is not taken for a register name. */
2657 fputs ("(", stream);
2658 assemble_name (stream, XSTR (x, 0));
2659 fputs (")", stream);
2664 output_addr_const (stream, x);
2668 fatal_insn ("bad insn to d30v_print_operand_address:", x);
2672 /* Print a memory reference suitable for the ld/st instructions. */
2675 d30v_print_operand_memory_reference (stream, x)
2682 switch (GET_CODE (x))
2685 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2705 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2706 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2714 fputs ("@(", stream);
2716 fputs (reg_names[GPR_R0], stream);
2720 const char *suffix = "";
2723 if (GET_CODE (x0) == SUBREG)
2725 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2726 GET_MODE (SUBREG_REG (x0)),
2729 x0 = SUBREG_REG (x0);
2732 if (GET_CODE (x0) == POST_INC)
2737 else if (GET_CODE (x0) == POST_DEC)
2743 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2744 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2746 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2749 fputs (",", stream);
2752 fputs (reg_names[GPR_R0], stream);
2758 switch (GET_CODE (x1))
2761 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2762 GET_MODE (SUBREG_REG (x1)),
2765 x1 = SUBREG_REG (x1);
2766 if (GET_CODE (x1) != REG)
2767 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2771 fputs (reg_names[REGNO (x1) + offset1], stream);
2775 fprintf (stream, "%ld", (long) INTVAL (x1));
2781 d30v_print_operand_address (stream, x1);
2785 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2789 fputs (")", stream);
2793 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2794 for an instruction operand X. X is an RTL expression.
2796 LETTER is a value that can be used to specify one of several ways of
2797 printing the operand. It is used when identical operands must be printed
2798 differently depending on the context. LETTER comes from the `%'
2799 specification that was used to request printing of the operand. If the
2800 specification was just `%DIGIT' then LETTER is 0; if the specification was
2801 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2803 If X is a register, this macro should print the register's name. The names
2804 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2805 is initialized from `REGISTER_NAMES'.
2807 When the machine description has a specification `%PUNCT' (a `%' followed by
2808 a punctuation character), this macro is called with a null pointer for X and
2809 the punctuation character for LETTER.
2811 Standard operand flags that are handled elsewhere:
2812 `=' Output a number unique to each instruction in the compilation.
2813 `a' Substitute an operand as if it were a memory reference.
2814 `c' Omit the syntax that indicates an immediate operand.
2815 `l' Substitute a LABEL_REF into a jump instruction.
2816 `n' Like %cDIGIT, except negate the value before printing.
2818 The d30v specific operand flags are:
2820 `f' Print a SF constant as an int.
2821 `s' Subtract 32 and negate.
2822 `A' Print accumulator number without an `a' in front of it.
2823 `B' Print bit offset for BSET, etc. instructions.
2824 `E' Print u if this is zero extend, nothing if this is sign extend.
2825 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2826 `L' Print the lower half of a 64 bit item.
2827 `M' Print a memory reference for ld/st instructions.
2828 `R' Return appropriate cmp instruction for relational test.
2830 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2831 `U' Print the upper half of a 64 bit item. */
2834 d30v_print_operand (stream, x, letter)
2839 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2840 rtx split_values[2];
2847 case '.': /* Output r0 */
2848 fputs (reg_names[GPR_R0], stream);
2851 case 'f': /* Print a SF floating constant as an int */
2852 if (GET_CODE (x) != CONST_DOUBLE)
2853 fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x);
2855 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2856 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2857 fprintf (stream, "%ld", num);
2860 case 'A': /* Print accumulator number without an `a' in front of it. */
2861 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2862 fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x);
2864 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2867 case 'M': /* Print a memory reference for ld/st */
2868 if (GET_CODE (x) != MEM)
2869 fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x);
2871 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2874 case 'L': /* print lower part of 64 bit item. */
2875 case 'U': /* print upper part of 64 bit item. */
2876 d30v_split_double (x, &split_values[0], &split_values[1]);
2877 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2880 case ':': /* Output the condition for the current insn. */
2881 x = current_insn_predicate;
2887 case 'F': /* Print an appropriate suffix for a false comparision. */
2888 case 'T': /* Print an appropriate suffix for a true comparision. */
2889 /* Note that the sense of appropriate suffix is for conditional execution
2890 and opposite of what branches want. Branches just use the inverse
2892 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2893 && GET_MODE (x) == CCmode
2894 && GET_CODE (XEXP (x, 0)) == REG
2895 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2896 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2898 int true_false = (letter == 'T');
2900 if (GET_CODE (x) == EQ)
2901 true_false = !true_false;
2903 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2904 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2906 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2907 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2910 fputs ((true_false) ? "tnz" : "tzr", stream);
2913 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2914 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2916 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2917 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2919 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2920 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2923 fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x);
2926 case 'B': /* emit offset single bit to change */
2927 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2928 fprintf (stream, "%d", 31 - log);
2930 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2931 fprintf (stream, "%d", 31 - log);
2934 fatal_insn ("bad insn to print_operand, 'B' modifier:", x);
2937 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2938 if (GET_CODE (x) == ZERO_EXTEND)
2940 else if (GET_CODE (x) != SIGN_EXTEND)
2941 fatal_insn ("bad insn to print_operand, 'E' modifier:", x);
2944 case 'R': /* Return appropriate cmp instruction for relational test. */
2945 switch (GET_CODE (x))
2947 case EQ: fputs ("cmpeq", stream); break;
2948 case NE: fputs ("cmpne", stream); break;
2949 case LT: fputs ("cmplt", stream); break;
2950 case LE: fputs ("cmple", stream); break;
2951 case GT: fputs ("cmpgt", stream); break;
2952 case GE: fputs ("cmpge", stream); break;
2953 case LTU: fputs ("cmpult", stream); break;
2954 case LEU: fputs ("cmpule", stream); break;
2955 case GTU: fputs ("cmpugt", stream); break;
2956 case GEU: fputs ("cmpuge", stream); break;
2959 fatal_insn ("bad insn to print_operand, 'R' modifier:", x);
2963 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2964 if (GET_CODE (x) == CONST_INT)
2965 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2968 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2971 case 'S': /* Subtract 32. */
2972 if (GET_CODE (x) == CONST_INT)
2973 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2976 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2980 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2981 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2982 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2983 && CONST_DOUBLE_HIGH (x) == 0))
2985 fputs (reg_names[GPR_FIRST], stream);
2993 fputs (reg_names[ REGNO (x) ], stream);
2995 else if (code == CONST_INT)
2996 fprintf (stream, "%d", (int)INTVAL (x));
2998 else if (code == MEM)
2999 d30v_print_operand_address (stream, XEXP (x, 0));
3001 else if (CONSTANT_ADDRESS_P (x))
3002 d30v_print_operand_address (stream, x);
3005 fatal_insn ("bad insn in d30v_print_operand, 0 case", x);
3013 sprintf (buf, "invalid asm template character '%%%c'", letter);
3014 fatal_insn (buf, x);
3020 /* A C expression for the size in bytes of the trampoline, as an integer. */
3023 d30v_trampoline_size ()
3029 /* Create a long instruction for building up a trampoline. */
3032 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3033 HOST_WIDE_INT high_bits;
3034 HOST_WIDE_INT low_bits;
3038 rtx reg = gen_reg_rtx (DImode);
3039 rtx high_word = gen_highpart (SImode, reg);
3040 rtx low_word = gen_lowpart (SImode, reg);
3041 rtx tmp1 = gen_reg_rtx (SImode);
3042 rtx tmp2 = gen_reg_rtx (SImode);
3043 rtx tmp3 = gen_reg_rtx (SImode);
3044 rtx tmp4 = gen_reg_rtx (SImode);
3045 rtx tmp5 = gen_reg_rtx (SImode);
3046 rtx tmp6 = gen_reg_rtx (SImode);
3048 imm = force_reg (SImode, imm);
3050 /* Stuff top 6 bits of immediate value into high word */
3051 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3052 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3053 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3055 /* Now get the next 8 bits for building the low word */
3056 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3057 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3059 /* And the bottom 18 bits */
3060 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3061 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3062 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3064 /* Store the instruction */
3065 emit_insn (gen_movdi (mem, reg));
3069 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3070 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3071 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3072 should be passed to the function when it is called. */
3075 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3080 /* The instruction space can only be accessed by ld2w/st2w.
3081 Generate on the fly:
3082 or r18,r0,<static-chain>
3084 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3085 0x80000000, static_chain,
3086 gen_rtx (MEM, DImode, addr));
3088 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3089 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3093 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3094 RTX) is a legitimate memory address on the target machine for a memory
3095 operand of mode MODE. */
3097 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3099 ? REGNO_OK_FOR_BASE_P (REGNO) \
3100 : GPR_OR_PSEUDO_P (REGNO))
3103 d30v_legitimate_address_p (mode, x, strict_p)
3104 enum machine_mode mode;
3111 switch (GET_CODE (x))
3118 if (GET_CODE (x) != REG)
3124 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3131 if (GET_CODE (x0) == SUBREG)
3132 x0 = SUBREG_REG (x0);
3134 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3137 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3140 switch (GET_CODE (x1))
3146 x1 = SUBREG_REG (x1);
3147 if (GET_CODE (x1) != REG)
3153 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3157 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3169 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3181 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3186 if (TARGET_DEBUG_ADDR)
3188 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3189 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3197 /* A C compound statement that attempts to replace X with a valid memory
3198 address for an operand of mode MODE. WIN will be a C statement label
3199 elsewhere in the code; the macro definition may use
3201 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3203 to avoid further processing if the address has become legitimate.
3205 X will always be the result of a call to `break_out_memory_refs', and OLDX
3206 will be the operand that was given to that function to produce X.
3208 The code generated by this macro should not alter the substructure of X. If
3209 it transforms X into a more legitimate form, it should assign X (which will
3210 always be a C variable) a new value.
3212 It is not necessary for this macro to come up with a legitimate address.
3213 The compiler has standard ways of doing so in all cases. In fact, it is
3214 safe for this macro to do nothing. But often a machine-dependent strategy
3215 can generate better code. */
3218 d30v_legitimize_address (x, oldx, mode, strict_p)
3220 rtx oldx ATTRIBUTE_UNUSED;
3221 enum machine_mode mode ATTRIBUTE_UNUSED;
3222 int strict_p ATTRIBUTE_UNUSED;
3226 if (TARGET_DEBUG_ADDR)
3230 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3232 fprintf (stderr, "\ninto:\n");
3237 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3246 /* A C statement or compound statement with a conditional `goto LABEL;'
3247 executed if memory address X (an RTX) can have different meanings depending
3248 on the machine mode of the memory reference it is used for or if the address
3249 is valid for some modes but not others.
3251 Autoincrement and autodecrement addresses typically have mode-dependent
3252 effects because the amount of the increment or decrement is the size of the
3253 operand being addressed. Some machines have other mode-dependent addresses.
3254 Many RISC machines have no mode-dependent addresses.
3256 You may assume that ADDR is a valid address for the machine. */
3259 d30v_mode_dependent_address_p (addr)
3262 switch (GET_CODE (addr))
3276 /* Generate the appropriate comparison code for a test. */
3279 d30v_emit_comparison (test_int, result, arg1, arg2)
3285 enum rtx_code test = (enum rtx_code) test_int;
3286 enum machine_mode mode = GET_MODE (arg1);
3287 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3290 || (mode == DImode && (test == EQ || test == NE))
3291 || (mode == DImode && (test == LT || test == GE)
3292 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3295 else if (mode == DImode)
3296 return gen_rtx (PARALLEL, VOIDmode,
3299 gen_rtx (CLOBBER, VOIDmode,
3300 gen_reg_rtx (CCmode))));
3303 fatal_insn ("d30v_emit_comparison", rtx_test);
3307 /* Return appropriate code to move 2 words. Since DImode registers must start
3308 on even register numbers, there is no possibility of overlap. */
3311 d30v_move_2words (operands, insn)
3315 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3317 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3318 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3320 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3321 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3323 else if (GET_CODE (operands[1]) == MEM)
3324 return "ld2w %0,%M1";
3326 else if (GET_CODE (operands[1]) == CONST_INT
3327 || GET_CODE (operands[1]) == CONST_DOUBLE)
3328 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3331 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3333 if (GET_CODE (operands[1]) == REG
3334 && GPR_P (REGNO (operands[1])))
3335 return "mvtacc %0,%U1,%L1";
3337 if (GET_CODE (operands[1]) == CONST_INT
3338 && INTVAL (operands[1]) == 0)
3339 return "mvtacc %0,%.,%.";
3342 else if (GET_CODE (operands[0]) == MEM
3343 && GET_CODE (operands[1]) == REG
3344 && GPR_P (REGNO (operands[1])))
3345 return "st2w %1,%M0";
3347 fatal_insn ("bad call to d30v_move_2words", insn);
3351 /* Emit the code to do a conditional move instruction. Return FALSE
3352 if the conditional move could not be executed. */
3355 d30v_emit_cond_move (dest, test, true_value, false_value)
3362 enum machine_mode mode = GET_MODE (dest);
3363 int two_mem_moves_p = FALSE;
3365 if (GET_CODE (dest) == MEM)
3367 if (!reg_or_0_operand (true_value, mode))
3370 if (rtx_equal_p (dest, false_value))
3371 two_mem_moves_p = TRUE;
3373 else if (!reg_or_0_operand (false_value, mode))
3377 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3378 to be slower than just doing the conditional execution. */
3380 br_reg = gen_reg_rtx (CCmode);
3381 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3382 d30v_compare_op0, d30v_compare_op1));
3384 if (!two_mem_moves_p)
3385 emit_insn (gen_rtx_SET (VOIDmode,
3387 gen_rtx_IF_THEN_ELSE (mode,
3388 gen_rtx_NE (CCmode, br_reg,
3394 /* Emit conditional stores as two separate stores. This avoids a problem
3395 where you have a conditional store, and one of the arms of the
3396 conditional store is spilled to memory. */
3397 emit_insn (gen_rtx_SET (VOIDmode,
3399 gen_rtx_IF_THEN_ELSE (mode,
3400 gen_rtx_NE (CCmode, br_reg,
3405 emit_insn (gen_rtx_SET (VOIDmode,
3407 gen_rtx_IF_THEN_ELSE (mode,
3408 gen_rtx_EQ (CCmode, br_reg,
3419 /* In rare cases, correct code generation requires extra machine dependent
3420 processing between the second jump optimization pass and delayed branch
3421 scheduling. On those machines, define this macro as a C statement to act on
3422 the code starting at INSN. */
3425 d30v_machine_dependent_reorg (insn)
3426 rtx insn ATTRIBUTE_UNUSED;
3431 /* A C statement (sans semicolon) to update the integer variable COST based on
3432 the relationship between INSN that is dependent on DEP_INSN through the
3433 dependence LINK. The default is to make no adjustment to COST. This can be
3434 used for example to specify to the scheduler that an output- or
3435 anti-dependence does not incur the same cost as a data-dependence. */
3437 /* For the d30v, try to insure that the source operands for a load/store are
3438 set 2 cycles before the memory reference. */
3441 d30v_adjust_cost (insn, link, dep_insn, cost)
3443 rtx link ATTRIBUTE_UNUSED;
3447 rtx set_dep = single_set (dep_insn);
3448 rtx set_insn = single_set (insn);
3450 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3451 && GET_CODE (SET_DEST (set_dep)) == REG)
3453 rtx reg = SET_DEST (set_dep);
3456 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3457 && reg_mentioned_p (reg, XEXP (mem, 0)))
3458 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3459 && reg_mentioned_p (reg, XEXP (mem, 0))))
3468 /* Function which returns the number of insns that can be
3469 scheduled in the same machine cycle. This must be constant
3470 over an entire compilation. The default is 1. */
3478 /* Routine to allocate, mark and free a per-function,
3479 machine specific structure. */
3481 static struct machine_function *
3482 d30v_init_machine_status ()
3484 return ggc_alloc_cleared (sizeof (machine_function));
3487 /* Do anything needed before RTL is emitted for each function. */
3490 d30v_init_expanders ()
3492 /* Arrange to save and restore machine status around nested functions. */
3493 init_machine_status = d30v_init_machine_status;
3496 /* Find the current function's return address.
3498 ??? It would be better to arrange things such that if we would ordinarily
3499 have been a leaf function and we didn't spill the hard reg that we
3500 wouldn't have to save the register in the prolog. But it's not clear
3501 how to get the right information at the right time. */
3506 return get_hard_reg_initial_val (Pmode, GPR_LINK);