1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
45 #include "langhooks.h"
47 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
48 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
50 static struct machine_function * d30v_init_machine_status PARAMS ((void));
51 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
52 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
53 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
54 static int d30v_issue_rate PARAMS ((void));
56 /* Define the information needed to generate branch and scc insns. This is
57 stored from the compare operation. */
59 struct rtx_def *d30v_compare_op0;
60 struct rtx_def *d30v_compare_op1;
62 /* Cached value of d30v_stack_info */
63 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
65 /* Values of the -mbranch-cost=n string. */
66 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
67 const char *d30v_branch_cost_string = (const char *)0;
69 /* Values of the -mcond-exec=n string. */
70 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
71 const char *d30v_cond_exec_string = (const char *)0;
73 /* Whether or not a hard register can accept a register */
74 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
76 /* Whether to try and avoid moves between two different modes */
77 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
79 /* Map register number to smallest register class. */
80 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
82 /* Map class letter into register class */
83 enum reg_class reg_class_from_letter[256];
85 /* Initialize the GCC target structure. */
86 #undef TARGET_ASM_ALIGNED_HI_OP
87 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
88 #undef TARGET_ASM_ALIGNED_SI_OP
89 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
91 #undef TARGET_ASM_FUNCTION_PROLOGUE
92 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
93 #undef TARGET_ASM_FUNCTION_EPILOGUE
94 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
95 #undef TARGET_SCHED_ADJUST_COST
96 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
97 #undef TARGET_SCHED_ISSUE_RATE
98 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
100 struct gcc_target targetm = TARGET_INITIALIZER;
102 /* Sometimes certain combinations of command options do not make
103 sense on a particular target machine. You can define a macro
104 `OVERRIDE_OPTIONS' to take account of this. This macro, if
105 defined, is executed once just after all the command options have
108 Don't use this macro to turn on various extra optimizations for
109 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
115 enum machine_mode mode1, mode2;
117 /* Set up the branch cost information */
118 if (d30v_branch_cost_string)
119 d30v_branch_cost = atoi (d30v_branch_cost_string);
121 /* Set up max # instructions to use with conditional execution */
122 if (d30v_cond_exec_string)
123 d30v_cond_exec = atoi (d30v_cond_exec_string);
125 /* Setup hard_regno_mode_ok/modes_tieable_p */
126 for (mode1 = VOIDmode;
127 (int)mode1 < NUM_MACHINE_MODES;
128 mode1 = (enum machine_mode)((int)mode1 + 1))
130 int size = GET_MODE_SIZE (mode1);
131 int large_p = size > UNITS_PER_WORD;
132 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
134 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
136 if (mode1 == VOIDmode)
139 else if (GPR_P (regno))
144 ok_p = (((regno - GPR_FIRST) & 1) == 0);
147 else if (FLAG_P (regno))
148 ok_p = (mode1 == CCmode);
150 else if (CR_P (regno))
151 ok_p = int_p && !large_p;
153 else if (ACCUM_P (regno))
154 ok_p = (mode1 == DImode);
156 else if (SPECIAL_REG_P (regno))
157 ok_p = (mode1 == SImode);
162 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
165 /* A C expression that is nonzero if it is desirable to choose
166 register allocation so as to avoid move instructions between a
167 value of mode MODE1 and a value of mode MODE2.
169 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
170 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
171 MODE2)' must be zero. */
172 for (mode2 = VOIDmode;
173 (int)mode2 <= NUM_MACHINE_MODES;
174 mode2 = (enum machine_mode)((int)mode2 + 1))
180 else if (GET_MODE_CLASS (mode1) == MODE_INT
181 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
182 && GET_MODE_CLASS (mode2) == MODE_INT
183 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
190 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
195 for (mode1 = VOIDmode;
196 (int)mode1 < NUM_MACHINE_MODES;
197 mode1 = (enum machine_mode)((int)mode1 + 1))
199 for (mode2 = VOIDmode;
200 (int)mode2 <= NUM_MACHINE_MODES;
201 mode2 = (enum machine_mode)((int)mode2 + 1))
203 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
205 && (hard_regno_mode_ok[(int)mode1][regno]
206 != hard_regno_mode_ok[(int)mode2][regno]))
207 error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
208 reg_names[regno], GET_MODE_NAME (mode1),
209 GET_MODE_NAME (mode2));
214 /* A C expression whose value is a register class containing hard
215 register REGNO. In general there is more than one such class;
216 choose a class which is "minimal", meaning that no smaller class
217 also contains the register. */
218 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
220 enum reg_class class;
223 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
224 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
226 else if (regno == FLAG_F0)
229 else if (regno == FLAG_F1)
232 else if (FLAG_P (regno))
233 class = OTHER_FLAG_REGS;
235 else if (ACCUM_P (regno))
238 else if (regno == CR_RPT_C)
241 else if (CR_P (regno))
244 else if (SPECIAL_REG_P (regno))
250 regno_reg_class[regno] = class;
254 static const char *const names[] = REG_CLASS_NAMES;
255 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
256 for (mode1 = VOIDmode;
257 (int)mode1 < NUM_MACHINE_MODES;
258 mode1 = (enum machine_mode)((int)mode1 + 1))
260 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
261 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
263 fprintf (stderr, "\n");
268 /* A C expression which defines the machine-dependent operand
269 constraint letters for register classes. If CHAR is such a
270 letter, the value should be the register class corresponding to
271 it. Otherwise, the value should be `NO_REGS'. The register
272 letter `r', corresponding to class `GENERAL_REGS', will not be
273 passed to this macro; you do not need to handle it.
275 The following letters are unavailable, due to being used as
280 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
281 'Q', 'R', 'S', 'T', 'U'
283 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
285 for (i = 0; i < 256; i++)
286 reg_class_from_letter[i] = NO_REGS;
288 reg_class_from_letter['a'] = ACCUM_REGS;
289 reg_class_from_letter['b'] = BR_FLAG_REGS;
290 reg_class_from_letter['c'] = CR_REGS;
291 reg_class_from_letter['d'] = GPR_REGS;
292 reg_class_from_letter['e'] = EVEN_REGS;
293 reg_class_from_letter['f'] = FLAG_REGS;
294 reg_class_from_letter['l'] = REPEAT_REGS;
295 reg_class_from_letter['x'] = F0_REGS;
296 reg_class_from_letter['y'] = F1_REGS;
297 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
301 /* Return true if a memory operand is a short memory operand. */
304 short_memory_operand (op, mode)
306 enum machine_mode mode;
308 if (GET_CODE (op) != MEM)
311 if (GET_MODE (op) != mode && mode != VOIDmode)
314 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
318 /* Return true if a memory operand is a long operand. */
321 long_memory_operand (op, mode)
323 enum machine_mode mode;
325 if (GET_CODE (op) != MEM)
328 if (GET_MODE (op) != mode && mode != VOIDmode)
331 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
335 /* Return true if a memory operand is valid for the D30V. */
338 d30v_memory_operand (op, mode)
340 enum machine_mode mode;
342 if (GET_CODE (op) != MEM)
345 if (GET_MODE (op) != mode && mode != VOIDmode)
348 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
352 /* Return true if a memory operand uses a single register for the
356 single_reg_memory_operand (op, mode)
358 enum machine_mode mode;
362 if (GET_CODE (op) != MEM)
365 if (GET_MODE (op) != mode && mode != VOIDmode)
369 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
372 if (GET_CODE (addr) == SUBREG)
373 addr = SUBREG_REG (addr);
375 return (GET_CODE (addr) == REG);
378 /* Return true if a memory operand uses a constant address. */
381 const_addr_memory_operand (op, mode)
383 enum machine_mode mode;
385 if (GET_CODE (op) != MEM)
388 if (GET_MODE (op) != mode && mode != VOIDmode)
391 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
394 switch (GET_CODE (XEXP (op, 0)))
409 /* Return true if operand is a memory reference suitable for a call. */
412 call_operand (op, mode)
414 enum machine_mode mode;
416 if (GET_CODE (op) != MEM)
419 if (GET_MODE (op) != mode && mode != VOIDmode)
422 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
425 switch (GET_CODE (XEXP (op, 0)))
431 op = SUBREG_REG (op);
432 if (GET_CODE (op) != REG)
438 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
450 /* Return true if operand is a GPR register. */
453 gpr_operand (op, mode)
455 enum machine_mode mode;
457 if (GET_MODE (op) != mode && mode != VOIDmode)
460 if (GET_CODE (op) == SUBREG)
462 if (GET_CODE (SUBREG_REG (op)) != REG)
463 return register_operand (op, mode);
465 op = SUBREG_REG (op);
468 if (GET_CODE (op) != REG)
471 return GPR_OR_PSEUDO_P (REGNO (op));
474 /* Return true if operand is an accumulator register. */
477 accum_operand (op, mode)
479 enum machine_mode mode;
481 if (GET_MODE (op) != mode && mode != VOIDmode)
484 if (GET_CODE (op) == SUBREG)
486 if (GET_CODE (SUBREG_REG (op)) != REG)
487 return register_operand (op, mode);
489 op = SUBREG_REG (op);
492 if (GET_CODE (op) != REG)
495 return ACCUM_OR_PSEUDO_P (REGNO (op));
498 /* Return true if operand is a GPR or an accumulator register. */
501 gpr_or_accum_operand (op, mode)
503 enum machine_mode mode;
505 if (GET_MODE (op) != mode && mode != VOIDmode)
508 if (GET_CODE (op) == SUBREG)
510 if (GET_CODE (SUBREG_REG (op)) != REG)
511 return register_operand (op, mode);
513 op = SUBREG_REG (op);
516 if (GET_CODE (op) != REG)
519 if (ACCUM_P (REGNO (op)))
522 return GPR_OR_PSEUDO_P (REGNO (op));
525 /* Return true if operand is a CR register. */
528 cr_operand (op, mode)
530 enum machine_mode mode;
532 if (GET_MODE (op) != mode && mode != VOIDmode)
535 if (GET_CODE (op) == SUBREG)
537 if (GET_CODE (SUBREG_REG (op)) != REG)
538 return register_operand (op, mode);
540 op = SUBREG_REG (op);
543 if (GET_CODE (op) != REG)
546 return CR_OR_PSEUDO_P (REGNO (op));
549 /* Return true if operand is the repeat count register. */
552 repeat_operand (op, mode)
554 enum machine_mode mode;
556 if (GET_MODE (op) != mode && mode != VOIDmode)
559 if (GET_CODE (op) == SUBREG)
561 if (GET_CODE (SUBREG_REG (op)) != REG)
562 return register_operand (op, mode);
564 op = SUBREG_REG (op);
567 if (GET_CODE (op) != REG)
570 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
573 /* Return true if operand is a FLAG register. */
576 flag_operand (op, mode)
578 enum machine_mode mode;
580 if (GET_MODE (op) != mode && mode != VOIDmode)
583 if (GET_CODE (op) == SUBREG)
585 if (GET_CODE (SUBREG_REG (op)) != REG)
586 return register_operand (op, mode);
588 op = SUBREG_REG (op);
591 if (GET_CODE (op) != REG)
594 return FLAG_OR_PSEUDO_P (REGNO (op));
597 /* Return true if operand is either F0 or F1. */
600 br_flag_operand (op, mode)
602 enum machine_mode mode;
604 if (GET_MODE (op) != mode && mode != VOIDmode)
607 if (GET_CODE (op) == SUBREG)
609 if (GET_CODE (SUBREG_REG (op)) != REG)
610 return register_operand (op, mode);
612 op = SUBREG_REG (op);
615 if (GET_CODE (op) != REG)
618 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
621 /* Return true if operand is either F0/F1 or the constants 0/1. */
624 br_flag_or_constant_operand (op, mode)
626 enum machine_mode mode;
628 if (GET_MODE (op) != mode && mode != VOIDmode)
631 if (GET_CODE (op) == SUBREG)
633 if (GET_CODE (SUBREG_REG (op)) != REG)
634 return register_operand (op, mode);
636 op = SUBREG_REG (op);
639 if (GET_CODE (op) == CONST_INT)
640 return (INTVAL (op) == 0 || INTVAL (op) == 1);
642 if (GET_CODE (op) != REG)
645 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
648 /* Return true if operand is either F0 or F1, or a GPR register. */
651 gpr_or_br_flag_operand (op, mode)
653 enum machine_mode mode;
655 if (GET_MODE (op) != mode && mode != VOIDmode)
658 if (GET_CODE (op) == SUBREG)
660 if (GET_CODE (SUBREG_REG (op)) != REG)
661 return register_operand (op, mode);
663 op = SUBREG_REG (op);
666 if (GET_CODE (op) != REG)
669 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
672 /* Return true if operand is the F0 register. */
675 f0_operand (op, mode)
677 enum machine_mode mode;
679 if (GET_MODE (op) != mode && mode != VOIDmode)
682 if (GET_CODE (op) == SUBREG)
684 if (GET_CODE (SUBREG_REG (op)) != REG)
685 return register_operand (op, mode);
687 op = SUBREG_REG (op);
690 if (GET_CODE (op) != REG)
693 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
696 /* Return true if operand is the F1 register. */
699 f1_operand (op, mode)
701 enum machine_mode mode;
703 if (GET_MODE (op) != mode && mode != VOIDmode)
706 if (GET_CODE (op) == SUBREG)
708 if (GET_CODE (SUBREG_REG (op)) != REG)
709 return register_operand (op, mode);
711 op = SUBREG_REG (op);
714 if (GET_CODE (op) != REG)
717 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
720 /* Return true if operand is the F1 register. */
723 carry_operand (op, mode)
725 enum machine_mode mode;
727 if (GET_MODE (op) != mode && mode != VOIDmode)
730 if (GET_CODE (op) == SUBREG)
732 if (GET_CODE (SUBREG_REG (op)) != REG)
733 return register_operand (op, mode);
735 op = SUBREG_REG (op);
738 if (GET_CODE (op) != REG)
741 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
744 /* Return true if operand is a register of any flavor or a 0 of the
748 reg_or_0_operand (op, mode)
750 enum machine_mode mode;
752 switch (GET_CODE (op))
759 if (GET_MODE (op) != mode && mode != VOIDmode)
762 return register_operand (op, mode);
765 return INTVAL (op) == 0;
768 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
774 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
777 gpr_or_signed6_operand (op, mode)
779 enum machine_mode mode;
781 if (GET_CODE (op) == SUBREG)
783 if (GET_CODE (SUBREG_REG (op)) != REG)
784 return register_operand (op, mode);
786 op = SUBREG_REG (op);
789 if (GET_CODE (op) == CONST_INT)
790 return IN_RANGE_P (INTVAL (op), -32, 31);
792 if (GET_CODE (op) != REG)
795 if (GET_MODE (op) != mode && mode != VOIDmode)
798 return GPR_OR_PSEUDO_P (REGNO (op));
801 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
804 gpr_or_unsigned5_operand (op, mode)
806 enum machine_mode mode;
808 if (GET_CODE (op) == SUBREG)
810 if (GET_CODE (SUBREG_REG (op)) != REG)
811 return register_operand (op, mode);
813 op = SUBREG_REG (op);
816 if (GET_CODE (op) == CONST_INT)
817 return IN_RANGE_P (INTVAL (op), 0, 31);
819 if (GET_CODE (op) != REG)
822 if (GET_MODE (op) != mode && mode != VOIDmode)
825 return GPR_OR_PSEUDO_P (REGNO (op));
828 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
831 gpr_or_unsigned6_operand (op, mode)
833 enum machine_mode mode;
835 if (GET_CODE (op) == SUBREG)
837 if (GET_CODE (SUBREG_REG (op)) != REG)
838 return register_operand (op, mode);
840 op = SUBREG_REG (op);
843 if (GET_CODE (op) == CONST_INT)
844 return IN_RANGE_P (INTVAL (op), 0, 63);
846 if (GET_CODE (op) != REG)
849 if (GET_MODE (op) != mode && mode != VOIDmode)
852 return GPR_OR_PSEUDO_P (REGNO (op));
855 /* Return true if operand is a GPR register or a constant of some form. */
858 gpr_or_constant_operand (op, mode)
860 enum machine_mode mode;
862 switch (GET_CODE (op))
874 if (GET_CODE (SUBREG_REG (op)) != REG)
875 return register_operand (op, mode);
877 op = SUBREG_REG (op);
881 if (GET_MODE (op) != mode && mode != VOIDmode)
884 return GPR_OR_PSEUDO_P (REGNO (op));
890 /* Return true if operand is a GPR register or a constant of some form,
891 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
894 gpr_or_dbl_const_operand (op, mode)
896 enum machine_mode mode;
898 switch (GET_CODE (op))
911 if (GET_CODE (SUBREG_REG (op)) != REG)
912 return register_operand (op, mode);
914 op = SUBREG_REG (op);
918 if (GET_MODE (op) != mode && mode != VOIDmode)
921 return GPR_OR_PSEUDO_P (REGNO (op));
927 /* Return true if operand is a gpr register or a valid memory operation. */
930 gpr_or_memory_operand (op, mode)
932 enum machine_mode mode;
934 switch (GET_CODE (op))
940 if (GET_CODE (SUBREG_REG (op)) != REG)
941 return register_operand (op, mode);
943 op = SUBREG_REG (op);
947 if (GET_MODE (op) != mode && mode != VOIDmode)
950 return GPR_OR_PSEUDO_P (REGNO (op));
953 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
959 /* Return true if operand is something that can be an input for a move
963 move_input_operand (op, mode)
965 enum machine_mode mode;
970 switch (GET_CODE (op))
983 if (GET_MODE (op) != mode && mode != VOIDmode)
986 subreg = SUBREG_REG (op);
987 code = GET_CODE (subreg);
989 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
992 return (code == REG);
995 if (GET_MODE (op) != mode && mode != VOIDmode)
1001 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1003 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1010 /* Return true if operand is something that can be an output for a move
1014 move_output_operand (op, mode)
1016 enum machine_mode mode;
1021 switch (GET_CODE (op))
1027 if (GET_MODE (op) != mode && mode != VOIDmode)
1030 subreg = SUBREG_REG (op);
1031 code = GET_CODE (subreg);
1033 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1036 return (code == REG);
1039 if (GET_MODE (op) != mode && mode != VOIDmode)
1045 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1047 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1054 /* Return true if operand is a signed 6 bit immediate. */
1057 signed6_operand (op, mode)
1059 enum machine_mode mode ATTRIBUTE_UNUSED;
1061 if (GET_CODE (op) == CONST_INT)
1062 return IN_RANGE_P (INTVAL (op), -32, 31);
1067 /* Return true if operand is an unsigned 5 bit immediate. */
1070 unsigned5_operand (op, mode)
1072 enum machine_mode mode ATTRIBUTE_UNUSED;
1074 if (GET_CODE (op) == CONST_INT)
1075 return IN_RANGE_P (INTVAL (op), 0, 31);
1080 /* Return true if operand is an unsigned 6 bit immediate. */
1083 unsigned6_operand (op, mode)
1085 enum machine_mode mode ATTRIBUTE_UNUSED;
1087 if (GET_CODE (op) == CONST_INT)
1088 return IN_RANGE_P (INTVAL (op), 0, 63);
1093 /* Return true if operand is a constant with a single bit set. */
1096 bitset_operand (op, mode)
1098 enum machine_mode mode ATTRIBUTE_UNUSED;
1100 if (GET_CODE (op) == CONST_INT)
1101 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1106 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1107 used in conditional execution. */
1110 condexec_test_operator (op, mode)
1112 enum machine_mode mode;
1116 if (GET_MODE (op) != mode && mode != VOIDmode)
1119 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1123 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1127 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1133 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1134 register that can be used in a branch instruction. */
1137 condexec_branch_operator (op, mode)
1139 enum machine_mode mode;
1143 if (GET_MODE (op) != mode && mode != VOIDmode)
1146 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1150 if (GET_CODE (x0) == REG)
1152 int regno = REGNO (x0);
1153 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1156 /* Allow the optimizer to generate things like:
1157 (if_then_else (ne (const_int 1) (const_int 0))) */
1158 else if (GET_CODE (x0) != CONST_INT)
1162 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1168 /* Return true if the unary operator can be executed with conditional
1172 condexec_unary_operator (op, mode)
1174 enum machine_mode mode ATTRIBUTE_UNUSED;
1178 /* Only do this after register allocation, so that we can look at the register # */
1179 if (!reload_completed)
1182 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1186 if (GET_CODE (op0) == SUBREG)
1187 op0 = SUBREG_REG (op0);
1189 switch (GET_CODE (op))
1196 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1205 /* Return true if the add or subtraction can be executed with conditional
1209 condexec_addsub_operator (op, mode)
1211 enum machine_mode mode ATTRIBUTE_UNUSED;
1215 /* Only do this after register allocation, so that we can look at the register # */
1216 if (!reload_completed)
1219 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1225 if (GET_CODE (op0) == SUBREG)
1226 op0 = SUBREG_REG (op0);
1228 if (GET_CODE (op1) == SUBREG)
1229 op1 = SUBREG_REG (op1);
1231 if (GET_CODE (op0) != REG)
1234 switch (GET_CODE (op))
1241 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1242 && gpr_or_constant_operand (op1, SImode));
1248 /* Return true if the binary operator can be executed with conditional
1249 execution. We don't include add/sub here, since they have extra
1250 clobbers for the flags registers. */
1253 condexec_binary_operator (op, mode)
1255 enum machine_mode mode ATTRIBUTE_UNUSED;
1259 /* Only do this after register allocation, so that we can look at the register # */
1260 if (!reload_completed)
1263 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1269 if (GET_CODE (op0) == SUBREG)
1270 op0 = SUBREG_REG (op0);
1272 if (GET_CODE (op1) == SUBREG)
1273 op1 = SUBREG_REG (op1);
1275 if (GET_CODE (op0) != REG)
1278 /* MULT is not included here, because it is an IU only instruction. */
1279 switch (GET_CODE (op))
1290 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1291 && gpr_or_constant_operand (op1, SImode));
1295 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1296 && GET_CODE (op1) == CONST_INT);
1302 /* Return true if the shift/rotate left operator can be executed with
1303 conditional execution. */
1306 condexec_shiftl_operator (op, mode)
1308 enum machine_mode mode ATTRIBUTE_UNUSED;
1312 /* Only do this after register allocation, so that we can look at the register # */
1313 if (!reload_completed)
1316 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1322 if (GET_CODE (op0) == SUBREG)
1323 op0 = SUBREG_REG (op0);
1325 if (GET_CODE (op1) == SUBREG)
1326 op1 = SUBREG_REG (op1);
1328 if (GET_CODE (op0) != REG)
1331 switch (GET_CODE (op))
1338 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1339 && GET_CODE (op1) == NEG
1340 && GET_CODE (XEXP (op1, 0)) == REG
1341 && GPR_P (REGNO (XEXP (op1, 0))));
1347 /* Return true if the {sign,zero} extend operator from memory can be
1348 conditionally executed. */
1351 condexec_extend_operator (op, mode)
1353 enum machine_mode mode ATTRIBUTE_UNUSED;
1355 /* Only do this after register allocation, so that we can look at the register # */
1356 if (!reload_completed)
1359 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1362 switch (GET_CODE (op))
1369 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1370 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1371 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1380 /* Return true for comparisons against 0 that can be turned into a
1381 bratnz/bratzr instruction. */
1384 branch_zero_operator (op, mode)
1386 enum machine_mode mode;
1390 if (GET_MODE (op) != mode && mode != VOIDmode)
1393 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1397 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1401 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1407 /* Return true if an operand is simple, suitable for use as the destination of
1408 a conditional move */
1411 cond_move_dest_operand (op, mode)
1413 enum machine_mode mode ATTRIBUTE_UNUSED;
1417 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1420 switch (GET_CODE (op))
1427 return gpr_operand (op, mode);
1429 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1431 addr = XEXP (op, 0);
1432 return (GET_CODE (addr) != POST_DEC
1433 && GET_CODE (addr) != POST_INC
1434 && d30v_legitimate_address_p (mode, addr, reload_completed));
1440 /* Return true if an operand is simple, suitable for use in a conditional move */
1443 cond_move_operand (op, mode)
1445 enum machine_mode mode ATTRIBUTE_UNUSED;
1449 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1452 switch (GET_CODE (op))
1459 return gpr_operand (op, mode);
1462 return GET_MODE (op) == SFmode;
1470 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1472 addr = XEXP (op, 0);
1473 return (GET_CODE (addr) != POST_DEC
1474 && GET_CODE (addr) != POST_INC
1475 && d30v_legitimate_address_p (mode, addr, reload_completed));
1481 /* Return true if an operand is simple, suitable for use in conditional execution.
1482 Unlike cond_move, we can allow auto inc/dec. */
1485 cond_exec_operand (op, mode)
1487 enum machine_mode mode;
1489 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1492 switch (GET_CODE (op))
1499 return gpr_operand (op, mode);
1502 return GET_MODE (op) == SFmode;
1511 return memory_operand (op, mode);
1517 /* Return true if operand is a SI mode signed relational test. */
1520 srelational_si_operator (op, mode)
1522 enum machine_mode mode;
1526 if (GET_MODE (op) != mode && mode != VOIDmode)
1529 switch (GET_CODE (op))
1544 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1547 if (GET_MODE (x0) != SImode)
1551 switch (GET_CODE (x1))
1568 /* Return true if operand is a SI mode unsigned relational test. */
1571 urelational_si_operator (op, mode)
1573 enum machine_mode mode;
1577 if (GET_MODE (op) != mode && mode != VOIDmode)
1580 switch (GET_CODE (op))
1593 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1596 if (GET_MODE (x0) != SImode)
1600 switch (GET_CODE (x1))
1617 /* Return true if operand is a DI mode relational test. */
1620 relational_di_operator (op, mode)
1622 enum machine_mode mode;
1626 if (GET_MODE (op) != mode && mode != VOIDmode)
1629 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1633 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1636 if (GET_MODE (x0) != DImode)
1640 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1641 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1648 /* Calculate the stack information for the current function.
1650 D30V stack frames look like:
1653 +-------------------------------+
1654 | Argument word #19 |
1655 +-------------------------------+
1656 | Argument word #18 |
1657 +-------------------------------+
1658 | Argument word #17 |
1659 +-------------------------------+
1660 | Argument word #16 |
1661 Prev sp +-------------------------------+
1663 | Save for arguments 1..16 if |
1664 | the func. uses stdarg/varargs |
1666 +-------------------------------+
1668 | Save area for GPR registers |
1670 +-------------------------------+
1672 | Save area for accumulators |
1674 +-------------------------------+
1678 +-------------------------------+
1680 | alloca space if used |
1682 +-------------------------------+
1684 | Space for outgoing arguments |
1686 low SP----> +-------------------------------+
1692 static d30v_stack_t info, zero_info;
1693 d30v_stack_t *info_ptr = &info;
1694 tree fndecl = current_function_decl;
1695 tree fntype = TREE_TYPE (fndecl);
1703 unsigned char save_gpr_p[GPR_LAST];
1706 /* If we've already calculated the values and reload is complete, just return now */
1707 if (d30v_stack_cache)
1708 return d30v_stack_cache;
1710 /* Zero all fields */
1713 if (current_function_profile)
1714 regs_ever_live[GPR_LINK] = 1;
1716 /* Determine if this is a stdarg function */
1717 if (TYPE_ARG_TYPES (fntype) != 0
1718 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1722 /* Find the last argument, and see if it is __builtin_va_alist. */
1723 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1725 next_arg = TREE_CHAIN (cur_arg);
1726 if (next_arg == (tree)0)
1728 if (DECL_NAME (cur_arg)
1729 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1737 /* Calculate which registers need to be saved & save area size */
1741 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1743 if (regs_ever_live[i] && !call_used_regs[i])
1745 info_ptr->save_p[i] = 2;
1752 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1754 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1763 /* Determine which register pairs can be saved together with ld2w/st2w */
1764 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1766 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1769 info_ptr->save_p[i++] = 2;
1771 else if (save_gpr_p[i])
1774 info_ptr->save_p[i] = 1;
1778 /* Determine various sizes */
1779 info_ptr->varargs_p = varargs_p;
1780 info_ptr->varargs_size = ((varargs_p)
1781 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1784 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1785 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1786 2 * UNITS_PER_WORD);
1787 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1788 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1789 2 * UNITS_PER_WORD);
1791 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1792 + info_ptr->accum_size
1793 + info_ptr->vars_size
1794 + info_ptr->parm_size
1795 + info_ptr->varargs_size
1796 + current_function_pretend_args_size),
1797 (STACK_BOUNDARY / BITS_PER_UNIT));
1799 info_ptr->save_offset = (info_ptr->total_size
1800 - (current_function_pretend_args_size
1801 + info_ptr->varargs_size
1802 + info_ptr->gpr_size
1803 + info_ptr->accum_size));
1805 /* The link register is the last GPR saved, but there might be some padding
1806 bytes after it, so account for that. */
1807 info_ptr->link_offset = (info_ptr->total_size
1808 - (current_function_pretend_args_size
1809 + info_ptr->varargs_size
1810 + (info_ptr->gpr_size
1811 - UNITS_PER_WORD * saved_gprs)
1814 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1815 info_ptr->memrefs_2words = memrefs_2words;
1816 info_ptr->memrefs_1word = memrefs_1word;
1818 if (reload_completed)
1819 d30v_stack_cache = info_ptr;
1825 /* Internal function to print all of the information about the stack */
1828 debug_stack_info (info)
1834 info = d30v_stack_info ();
1836 fprintf (stderr, "\nStack information for function %s:\n",
1837 ((current_function_decl && DECL_NAME (current_function_decl))
1838 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1841 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1842 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1843 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1844 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1845 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1846 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1847 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1848 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1849 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1850 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1851 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1852 fprintf (stderr, "\tsaved registers =");
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 if (info->save_p[i] == 2)
1858 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1861 else if (info->save_p[i])
1862 fprintf (stderr, " %s", reg_names[i]);
1865 putc ('\n', stderr);
1870 /* Return non-zero if this function is known to have a null or 1 instruction epilogue. */
1875 if (reload_completed)
1877 d30v_stack_t *info = d30v_stack_info ();
1879 /* If no epilogue code is needed, can use just a simple jump */
1880 if (info->total_size == 0)
1884 /* If just a small amount of local stack was allocated and no registers
1885 saved, skip forward branch */
1886 if (info->total_size == info->vars_size
1887 && IN_RANGE_P (info->total_size, 1, 31))
1896 /* A C statement (sans semicolon) for initializing the variable CUM for the
1897 state at the beginning of the argument list. The variable has type
1898 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1899 of the function which will receive the args, or 0 if the args are to a
1900 compiler support library function. The value of INDIRECT is nonzero when
1901 processing an indirect call, for example a call through a function pointer.
1902 The value of INDIRECT is zero for a call to an explicitly named function, a
1903 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1904 arguments for the function being compiled.
1906 When processing a call to a compiler support library function, LIBNAME
1907 identifies which one. It is a `symbol_ref' rtx which contains the name of
1908 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1909 being processed. Thus, each time this macro is called, either LIBNAME or
1910 FNTYPE is nonzero, but never both of them at once. */
1913 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1914 CUMULATIVE_ARGS *cum;
1920 *cum = GPR_ARG_FIRST;
1922 if (TARGET_DEBUG_ARG)
1924 fprintf (stderr, "\ninit_cumulative_args:");
1926 fputs (" indirect", stderr);
1929 fputs (" incoming", stderr);
1933 tree ret_type = TREE_TYPE (fntype);
1934 fprintf (stderr, " return=%s,",
1935 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1938 if (libname && GET_CODE (libname) == SYMBOL_REF)
1939 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1941 putc ('\n', stderr);
1946 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1947 argument with the specified mode and type. If it is not defined,
1948 `PARM_BOUNDARY' is used for all arguments. */
1951 d30v_function_arg_boundary (mode, type)
1952 enum machine_mode mode;
1955 int size = ((mode == BLKmode && type)
1956 ? int_size_in_bytes (type)
1957 : (int) GET_MODE_SIZE (mode));
1959 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1963 /* A C expression that controls whether a function argument is passed in a
1964 register, and which register.
1966 The arguments are CUM, which summarizes all the previous arguments; MODE,
1967 the machine mode of the argument; TYPE, the data type of the argument as a
1968 tree node or 0 if that is not known (which happens for C support library
1969 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1970 nameless arguments that correspond to `...' in the called function's
1973 The value of the expression should either be a `reg' RTX for the hard
1974 register in which to pass the argument, or zero to pass the argument on the
1977 For machines like the VAX and 68000, where normally all arguments are
1978 pushed, zero suffices as a definition.
1980 The usual way to make the ANSI library `stdarg.h' work on a machine where
1981 some arguments are usually passed in registers, is to cause nameless
1982 arguments to be passed on the stack instead. This is done by making
1983 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1985 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1986 this macro to determine if this argument is of a type that must be passed in
1987 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1988 returns non-zero for such an argument, the compiler will abort. If
1989 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1990 stack and then loaded into a register. */
1993 d30v_function_arg (cum, mode, type, named, incoming)
1994 CUMULATIVE_ARGS *cum;
1995 enum machine_mode mode;
1998 int incoming ATTRIBUTE_UNUSED;
2000 int size = ((mode == BLKmode && type)
2001 ? int_size_in_bytes (type)
2002 : (int) GET_MODE_SIZE (mode));
2003 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2006 /* Return a marker for use in the call instruction. */
2007 if (mode == VOIDmode)
2010 else if (*cum + adjust <= GPR_ARG_LAST)
2011 ret = gen_rtx (REG, mode, *cum + adjust);
2016 if (TARGET_DEBUG_ARG)
2018 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2019 *cum, GET_MODE_NAME (mode), named, size, adjust,
2020 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2026 /* A C expression for the number of words, at the beginning of an argument,
2027 must be put in registers. The value must be zero for arguments that are
2028 passed entirely in registers or that are entirely pushed on the stack.
2030 On some machines, certain arguments must be passed partially in registers
2031 and partially in memory. On these machines, typically the first N words of
2032 arguments are passed in registers, and the rest on the stack. If a
2033 multi-word argument (a `double' or a structure) crosses that boundary, its
2034 first few words must be passed in registers and the rest must be pushed.
2035 This macro tells the compiler when this occurs, and how many of the words
2036 should go in registers.
2038 `FUNCTION_ARG' for these arguments should return the first register to be
2039 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2040 the called function. */
2043 d30v_function_arg_partial_nregs (cum, mode, type, named)
2044 CUMULATIVE_ARGS *cum;
2045 enum machine_mode mode;
2047 int named ATTRIBUTE_UNUSED;
2049 int bytes = ((mode == BLKmode)
2050 ? int_size_in_bytes (type)
2051 : (int) GET_MODE_SIZE (mode));
2052 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2053 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2054 int arg_num = *cum + adjust;
2057 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2058 ? GPR_ARG_LAST - arg_num + 1
2061 if (TARGET_DEBUG_ARG && ret)
2062 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2068 /* A C expression that indicates when an argument must be passed by reference.
2069 If nonzero for an argument, a copy of that argument is made in memory and a
2070 pointer to the argument is passed instead of the argument itself. The
2071 pointer is passed in whatever way is appropriate for passing a pointer to
2074 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2075 definition of this macro might be
2076 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2077 (CUM, MODE, TYPE, NAMED) \
2078 MUST_PASS_IN_STACK (MODE, TYPE) */
2081 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2082 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2083 enum machine_mode mode;
2085 int named ATTRIBUTE_UNUSED;
2087 int ret = MUST_PASS_IN_STACK (mode, type);
2089 if (TARGET_DEBUG_ARG && ret)
2090 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2096 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2097 advance past an argument in the argument list. The values MODE, TYPE and
2098 NAMED describe that argument. Once this is done, the variable CUM is
2099 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2101 This macro need not do anything if the argument in question was passed on
2102 the stack. The compiler knows how to track the amount of stack space used
2103 for arguments without any special help. */
2106 d30v_function_arg_advance (cum, mode, type, named)
2107 CUMULATIVE_ARGS *cum;
2108 enum machine_mode mode;
2112 int bytes = ((mode == BLKmode)
2113 ? int_size_in_bytes (type)
2114 : (int) GET_MODE_SIZE (mode));
2115 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2116 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2118 *cum += words + adjust;
2120 if (TARGET_DEBUG_ARG)
2122 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2123 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2127 /* If defined, is a C expression that produces the machine-specific code for a
2128 call to `__builtin_saveregs'. This code will be moved to the very beginning
2129 of the function, before any parameter access are made. The return value of
2130 this function should be an RTX that contains the value to use as the return
2131 of `__builtin_saveregs'.
2133 If this macro is not defined, the compiler will output an ordinary call to
2134 the library function `__builtin_saveregs'. */
2137 d30v_expand_builtin_saveregs ()
2139 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2141 if (TARGET_DEBUG_ARG)
2142 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2145 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2149 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2150 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2151 arguments into the stack so that all the arguments appear to have been
2152 passed consecutively on the stack. Once this is done, you can use the
2153 standard implementation of varargs that works for machines that pass all
2154 their arguments on the stack.
2156 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2157 the values that obtain after processing of the named arguments. The
2158 arguments MODE and TYPE describe the last named argument--its machine mode
2159 and its data type as a tree node.
2161 The macro implementation should do two things: first, push onto the stack
2162 all the argument registers *not* used for the named arguments, and second,
2163 store the size of the data thus pushed into the `int'-valued variable whose
2164 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2165 store here will serve as additional offset for setting up the stack frame.
2167 Because you must generate code to push the anonymous arguments at compile
2168 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2169 useful on machines that have just a single category of argument register and
2170 use it uniformly for all data types.
2172 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2173 function are being analyzed for the second time. This happens for an inline
2174 function, which is not actually compiled until the end of the source file.
2175 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2179 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2180 CUMULATIVE_ARGS *cum;
2181 enum machine_mode mode;
2182 tree type ATTRIBUTE_UNUSED;
2183 int *pretend_size ATTRIBUTE_UNUSED;
2186 if (TARGET_DEBUG_ARG)
2188 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2189 *cum, GET_MODE_NAME (mode), second_time);
2193 /* Create the va_list data type. */
2196 d30v_build_va_list ()
2198 tree f_arg_ptr, f_arg_num, record, type_decl;
2201 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2202 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2203 int_type_node = make_signed_type (INT_TYPE_SIZE);
2205 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2207 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2210 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2211 DECL_FIELD_CONTEXT (f_arg_num) = record;
2213 TREE_CHAIN (record) = type_decl;
2214 TYPE_NAME (record) = type_decl;
2215 TYPE_FIELDS (record) = f_arg_ptr;
2216 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2218 layout_type (record);
2220 /* The correct type is an array type of one element. */
2221 return build_array_type (record, build_index_type (size_zero_node));
2225 /* Expand __builtin_va_start to do the va_start macro. */
2228 d30v_expand_builtin_va_start (stdarg_p, valist, nextarg)
2229 int stdarg_p ATTRIBUTE_UNUSED;
2231 rtx nextarg ATTRIBUTE_UNUSED;
2233 HOST_WIDE_INT words;
2234 tree f_arg_ptr, f_arg_num;
2235 tree arg_ptr, arg_num, saveregs, t;
2237 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2238 f_arg_num = TREE_CHAIN (f_arg_ptr);
2240 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2241 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2242 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2244 words = current_function_args_info; /* __builtin_args_info (0) */
2246 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2247 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2248 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2249 TREE_SIDE_EFFECTS (t) = 1;
2250 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2252 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2253 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2254 build_int_2 (-GPR_ARG_FIRST, 0));
2255 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2256 TREE_SIDE_EFFECTS (t) = 1;
2257 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2261 /* Expand __builtin_va_arg to do the va_arg macro. */
2264 d30v_expand_builtin_va_arg(valist, type)
2268 tree f_arg_ptr, f_arg_num;
2269 tree arg_ptr, arg_num, t, ptr;
2271 rtx lab_false, ptr_rtx, r;
2273 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2274 f_arg_num = TREE_CHAIN (f_arg_ptr);
2276 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2277 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2278 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2280 size = int_size_in_bytes (type);
2282 lab_false = gen_label_rtx ();
2283 ptr_rtx = gen_reg_rtx (Pmode);
2285 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2286 (AP)->__va_arg_num++; */
2288 if (size > UNITS_PER_WORD)
2290 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2291 build_int_2 (1, 0));
2293 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2294 GEN_INT (0), EQ, const1_rtx, QImode, 1,
2297 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2298 build_int_2 (1, 0));
2299 TREE_SIDE_EFFECTS (t) = 1;
2300 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2302 emit_label (lab_false);
2306 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2307 + (AP)->__va_arg_num))); */
2309 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2310 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2312 /* if (sizeof (TYPE) < 4)
2313 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2315 if (size < UNITS_PER_WORD)
2316 t = build (PLUS_EXPR, ptr_type_node, t,
2317 build_int_2 (UNITS_PER_WORD - size, 0));
2319 TREE_SIDE_EFFECTS (t) = 1;
2321 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2322 t = build (MODIFY_EXPR, type, ptr, t);
2324 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2326 emit_move_insn (ptr_rtx, r);
2329 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2330 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2331 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2332 build_int_2 (num, 0));
2333 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2338 /* Generate the assembly code for function entry. FILE is a stdio
2339 stream to output the code to. SIZE is an int: how many units of
2340 temporary storage to allocate.
2342 Refer to the array `regs_ever_live' to determine which registers to
2343 save; `regs_ever_live[I]' is nonzero if register number I is ever
2344 used in the function. This function is responsible for knowing
2345 which registers should not be saved even if used. */
2348 d30v_output_function_prologue (stream, size)
2349 FILE *stream ATTRIBUTE_UNUSED;
2350 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2352 /* For the d30v, move all of the prologue processing into separate
2357 /* Called after register allocation to add any instructions needed for
2358 the prologue. Using a prologue insn is favored compared to putting
2359 all of the instructions in output_function_prologue (), since it
2360 allows the scheduler to intermix instructions with the saves of the
2361 caller saved registers. In some cases, it might be necessary to
2362 emit a barrier instruction as the last insn to prevent such
2366 d30v_expand_prologue ()
2368 rtx sp = stack_pointer_rtx;
2369 d30v_stack_t *info = d30v_stack_info ();
2371 rtx mem_di = NULL_RTX;
2372 rtx mem_si = NULL_RTX;
2373 int num_memrefs = (info->memrefs_2words
2374 + info->memrefs_1word
2375 + info->memrefs_varargs);
2377 if (TARGET_DEBUG_STACK)
2378 debug_stack_info (info);
2380 /* Grow the stack. */
2381 if (info->total_size)
2382 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2384 /* If there is more than one save, use post-increment addressing which will
2385 result in smaller code, than would the normal references. If there is
2386 only one save, just do the store as normal. */
2388 if (num_memrefs > 1)
2390 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2391 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2392 mem_di = gen_rtx (MEM, DImode, post_inc);
2393 mem_si = gen_rtx (MEM, SImode, post_inc);
2394 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2396 else if (num_memrefs == 1)
2398 rtx addr = plus_constant (sp, info->save_offset);
2399 mem_di = gen_rtx (MEM, DImode, addr);
2400 mem_si = gen_rtx (MEM, SImode, addr);
2403 /* Save the accumulators. */
2404 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2405 if (info->save_p[i])
2407 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2408 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2409 emit_insn (gen_movdi (mem_di, acc_tmp));
2412 /* Save the GPR registers that are adjacent to each other with st2w. */
2413 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2414 if (info->save_p[i] == 2)
2415 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2417 /* Save the GPR registers that need to be saved with a single word store. */
2418 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2419 if (info->save_p[i] == 1)
2420 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2422 /* Save the argument registers if this function accepts variable args. */
2423 if (info->varargs_p)
2425 /* Realign r22 if an odd # of GPRs were saved. */
2426 if ((info->memrefs_1word & 1) != 0)
2428 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2429 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2432 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2433 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2436 /* Update the frame pointer. */
2437 if (frame_pointer_needed)
2438 emit_move_insn (frame_pointer_rtx, sp);
2440 /* Hack for now, to prevent scheduler from being too cleaver */
2441 emit_insn (gen_blockage ());
2445 /* This function generates the assembly code for function exit.
2446 Args are as for output_function_prologue ().
2448 The function epilogue should not depend on the current stack
2449 pointer! It should use the frame pointer only. This is mandatory
2450 because of alloca; we also take advantage of it to omit stack
2451 adjustments before returning. */
2454 d30v_output_function_epilogue (stream, size)
2455 FILE *stream ATTRIBUTE_UNUSED;
2456 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2458 /* For the d30v, move all processing to be as insns, but do any
2459 cleanup here, since it is done after handling all of the insns. */
2460 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2465 /* Called after register allocation to add any instructions needed for
2466 the epilogue. Using an epilogue insn is favored compared to putting
2467 all of the instructions in output_function_prologue(), since it
2468 allows the scheduler to intermix instructions with the saves of the
2469 caller saved registers. In some cases, it might be necessary to
2470 emit a barrier instruction as the last insn to prevent such
2474 d30v_expand_epilogue ()
2476 rtx sp = stack_pointer_rtx;
2477 d30v_stack_t *info = d30v_stack_info ();
2479 rtx mem_di = NULL_RTX;
2480 rtx mem_si = NULL_RTX;
2484 /* Hack for now, to prevent scheduler from being too cleaver */
2485 emit_insn (gen_blockage ());
2487 /* Restore sp from fp. */
2488 if (frame_pointer_needed)
2489 emit_move_insn (sp, frame_pointer_rtx);
2491 /* For the epilogue, use post-increment addressing all of the time. First
2492 adjust the sp, to eliminate all of the stack, except for the save area. */
2494 if (info->save_offset)
2495 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2497 post_inc = gen_rtx (POST_INC, Pmode, sp);
2498 mem_di = gen_rtx (MEM, DImode, post_inc);
2499 mem_si = gen_rtx (MEM, SImode, post_inc);
2501 /* Restore the accumulators. */
2502 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2503 if (info->save_p[i])
2505 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2506 emit_insn (gen_movdi (acc_tmp, mem_di));
2507 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2510 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2511 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2512 if (info->save_p[i] == 2)
2513 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2515 /* Save the GPR registers that need to be saved with a single word store. */
2517 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2518 if (info->save_p[i] == 1)
2520 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2526 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2529 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2533 /* Release any remaining stack that was allocated for saving the
2534 varargs registers or because an odd # of registers were stored. */
2535 if ((info->memrefs_1word & 1) != 0)
2536 extra_stack += UNITS_PER_WORD;
2537 extra_stack += current_function_pretend_args_size + info->varargs_size;
2541 if (cfun->machine->eh_epilogue_sp_ofs)
2542 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2543 cfun->machine->eh_epilogue_sp_ofs,
2544 GEN_INT (extra_stack)));
2546 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2548 if (cfun->machine->eh_epilogue_sp_ofs)
2549 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2551 /* Now emit the return instruction. */
2552 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2556 /* A C statement or compound statement to output to FILE some assembler code to
2557 call the profiling subroutine `mcount'. Before calling, the assembler code
2558 must load the address of a counter variable into a register where `mcount'
2559 expects to find the address. The name of this variable is `LP' followed by
2560 the number LABELNO, so you would generate the name using `LP%d' in a
2563 The details of how the address should be passed to `mcount' are determined
2564 by your operating system environment, not by GNU CC. To figure them out,
2565 compile a small program for profiling using the system's installed C
2566 compiler and look at the assembler code that results. */
2569 d30v_function_profiler (stream, labelno)
2571 int labelno ATTRIBUTE_UNUSED;
2573 fprintf (stream, "# profile\n");
2577 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2578 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2579 the wrong part for floating point in cross compilers, and split_double does
2580 not handle registers. Also abort if the register is not a general purpose
2584 d30v_split_double (value, p_high, p_low)
2592 if (!reload_completed)
2595 switch (GET_CODE (value))
2598 if (GET_CODE (SUBREG_REG (value)) != REG)
2600 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2601 GET_MODE (SUBREG_REG (value)),
2602 SUBREG_BYTE (value),
2604 value = SUBREG_REG (value);
2609 regno = REGNO (value) + offset;
2613 *p_high = gen_rtx (REG, SImode, regno);
2614 *p_low = gen_rtx (REG, SImode, regno+1);
2619 split_double (value, p_high, p_low);
2628 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2629 for an instruction operand that is a memory reference whose address is X. X
2630 is an RTL expression. */
2633 d30v_print_operand_address (stream, x)
2637 if (GET_CODE (x) == MEM)
2640 switch (GET_CODE (x))
2646 fputs (reg_names[ REGNO (x) ], stream);
2650 fprintf (stream, "%ld", (long) INTVAL (x));
2653 /* We wrap simple symbol refs inside a parenthesis, so that a name
2654 like `r2' is not taken for a register name. */
2656 fputs ("(", stream);
2657 assemble_name (stream, XSTR (x, 0));
2658 fputs (")", stream);
2663 output_addr_const (stream, x);
2667 fatal_insn ("bad insn to d30v_print_operand_address:", x);
2671 /* Print a memory reference suitable for the ld/st instructions. */
2674 d30v_print_operand_memory_reference (stream, x)
2681 switch (GET_CODE (x))
2684 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2704 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2705 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2713 fputs ("@(", stream);
2715 fputs (reg_names[GPR_R0], stream);
2719 const char *suffix = "";
2722 if (GET_CODE (x0) == SUBREG)
2724 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2725 GET_MODE (SUBREG_REG (x0)),
2728 x0 = SUBREG_REG (x0);
2731 if (GET_CODE (x0) == POST_INC)
2736 else if (GET_CODE (x0) == POST_DEC)
2742 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2743 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2745 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2748 fputs (",", stream);
2751 fputs (reg_names[GPR_R0], stream);
2757 switch (GET_CODE (x1))
2760 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2761 GET_MODE (SUBREG_REG (x1)),
2764 x1 = SUBREG_REG (x1);
2765 if (GET_CODE (x1) != REG)
2766 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2770 fputs (reg_names[REGNO (x1) + offset1], stream);
2774 fprintf (stream, "%ld", (long) INTVAL (x1));
2780 d30v_print_operand_address (stream, x1);
2784 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2788 fputs (")", stream);
2792 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2793 for an instruction operand X. X is an RTL expression.
2795 LETTER is a value that can be used to specify one of several ways of
2796 printing the operand. It is used when identical operands must be printed
2797 differently depending on the context. LETTER comes from the `%'
2798 specification that was used to request printing of the operand. If the
2799 specification was just `%DIGIT' then LETTER is 0; if the specification was
2800 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2802 If X is a register, this macro should print the register's name. The names
2803 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2804 is initialized from `REGISTER_NAMES'.
2806 When the machine description has a specification `%PUNCT' (a `%' followed by
2807 a punctuation character), this macro is called with a null pointer for X and
2808 the punctuation character for LETTER.
2810 Standard operand flags that are handled elsewhere:
2811 `=' Output a number unique to each instruction in the compilation.
2812 `a' Substitute an operand as if it were a memory reference.
2813 `c' Omit the syntax that indicates an immediate operand.
2814 `l' Substitute a LABEL_REF into a jump instruction.
2815 `n' Like %cDIGIT, except negate the value before printing.
2817 The d30v specific operand flags are:
2819 `f' Print a SF constant as an int.
2820 `s' Subtract 32 and negate.
2821 `A' Print accumulator number without an `a' in front of it.
2822 `B' Print bit offset for BSET, etc. instructions.
2823 `E' Print u if this is zero extend, nothing if this is sign extend.
2824 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2825 `L' Print the lower half of a 64 bit item.
2826 `M' Print a memory reference for ld/st instructions.
2827 `R' Return appropriate cmp instruction for relational test.
2829 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2830 `U' Print the upper half of a 64 bit item. */
2833 d30v_print_operand (stream, x, letter)
2838 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2839 rtx split_values[2];
2846 case '.': /* Output r0 */
2847 fputs (reg_names[GPR_R0], stream);
2850 case 'f': /* Print a SF floating constant as an int */
2851 if (GET_CODE (x) != CONST_DOUBLE)
2852 fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x);
2854 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2855 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2856 fprintf (stream, "%ld", num);
2859 case 'A': /* Print accumulator number without an `a' in front of it. */
2860 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2861 fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x);
2863 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2866 case 'M': /* Print a memory reference for ld/st */
2867 if (GET_CODE (x) != MEM)
2868 fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x);
2870 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2873 case 'L': /* print lower part of 64 bit item. */
2874 case 'U': /* print upper part of 64 bit item. */
2875 d30v_split_double (x, &split_values[0], &split_values[1]);
2876 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2879 case ':': /* Output the condition for the current insn. */
2880 x = current_insn_predicate;
2886 case 'F': /* Print an appropriate suffix for a false comparision. */
2887 case 'T': /* Print an appropriate suffix for a true comparision. */
2888 /* Note that the sense of appropriate suffix is for conditional execution
2889 and opposite of what branches want. Branches just use the inverse
2891 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2892 && GET_MODE (x) == CCmode
2893 && GET_CODE (XEXP (x, 0)) == REG
2894 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2895 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2897 int true_false = (letter == 'T');
2899 if (GET_CODE (x) == EQ)
2900 true_false = !true_false;
2902 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2903 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2905 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2906 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2909 fputs ((true_false) ? "tnz" : "tzr", stream);
2912 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2913 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2915 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2916 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2918 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2919 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2922 fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x);
2925 case 'B': /* emit offset single bit to change */
2926 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2927 fprintf (stream, "%d", 31 - log);
2929 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2930 fprintf (stream, "%d", 31 - log);
2933 fatal_insn ("bad insn to print_operand, 'B' modifier:", x);
2936 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2937 if (GET_CODE (x) == ZERO_EXTEND)
2939 else if (GET_CODE (x) != SIGN_EXTEND)
2940 fatal_insn ("bad insn to print_operand, 'E' modifier:", x);
2943 case 'R': /* Return appropriate cmp instruction for relational test. */
2944 switch (GET_CODE (x))
2946 case EQ: fputs ("cmpeq", stream); break;
2947 case NE: fputs ("cmpne", stream); break;
2948 case LT: fputs ("cmplt", stream); break;
2949 case LE: fputs ("cmple", stream); break;
2950 case GT: fputs ("cmpgt", stream); break;
2951 case GE: fputs ("cmpge", stream); break;
2952 case LTU: fputs ("cmpult", stream); break;
2953 case LEU: fputs ("cmpule", stream); break;
2954 case GTU: fputs ("cmpugt", stream); break;
2955 case GEU: fputs ("cmpuge", stream); break;
2958 fatal_insn ("bad insn to print_operand, 'R' modifier:", x);
2962 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2963 if (GET_CODE (x) == CONST_INT)
2964 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2967 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2970 case 'S': /* Subtract 32. */
2971 if (GET_CODE (x) == CONST_INT)
2972 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2975 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2979 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2980 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2981 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2982 && CONST_DOUBLE_HIGH (x) == 0))
2984 fputs (reg_names[GPR_FIRST], stream);
2992 fputs (reg_names[ REGNO (x) ], stream);
2994 else if (code == CONST_INT)
2995 fprintf (stream, "%d", (int)INTVAL (x));
2997 else if (code == MEM)
2998 d30v_print_operand_address (stream, XEXP (x, 0));
3000 else if (CONSTANT_ADDRESS_P (x))
3001 d30v_print_operand_address (stream, x);
3004 fatal_insn ("bad insn in d30v_print_operand, 0 case", x);
3012 sprintf (buf, "invalid asm template character '%%%c'", letter);
3013 fatal_insn (buf, x);
3019 /* A C expression for the size in bytes of the trampoline, as an integer. */
3022 d30v_trampoline_size ()
3028 /* Create a long instruction for building up a trampoline. */
3031 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3032 HOST_WIDE_INT high_bits;
3033 HOST_WIDE_INT low_bits;
3037 rtx reg = gen_reg_rtx (DImode);
3038 rtx high_word = gen_highpart (SImode, reg);
3039 rtx low_word = gen_lowpart (SImode, reg);
3040 rtx tmp1 = gen_reg_rtx (SImode);
3041 rtx tmp2 = gen_reg_rtx (SImode);
3042 rtx tmp3 = gen_reg_rtx (SImode);
3043 rtx tmp4 = gen_reg_rtx (SImode);
3044 rtx tmp5 = gen_reg_rtx (SImode);
3045 rtx tmp6 = gen_reg_rtx (SImode);
3047 imm = force_reg (SImode, imm);
3049 /* Stuff top 6 bits of immediate value into high word */
3050 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3051 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3052 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3054 /* Now get the next 8 bits for building the low word */
3055 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3056 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3058 /* And the bottom 18 bits */
3059 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3060 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3061 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3063 /* Store the instruction */
3064 emit_insn (gen_movdi (mem, reg));
3068 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3069 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3070 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3071 should be passed to the function when it is called. */
3074 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3079 /* The instruction space can only be accessed by ld2w/st2w.
3080 Generate on the fly:
3081 or r18,r0,<static-chain>
3083 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3084 0x80000000, static_chain,
3085 gen_rtx (MEM, DImode, addr));
3087 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3088 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3092 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3093 RTX) is a legitimate memory address on the target machine for a memory
3094 operand of mode MODE. */
3096 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3098 ? REGNO_OK_FOR_BASE_P (REGNO) \
3099 : GPR_OR_PSEUDO_P (REGNO))
3102 d30v_legitimate_address_p (mode, x, strict_p)
3103 enum machine_mode mode;
3110 switch (GET_CODE (x))
3117 if (GET_CODE (x) != REG)
3123 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3130 if (GET_CODE (x0) == SUBREG)
3131 x0 = SUBREG_REG (x0);
3133 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3136 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3139 switch (GET_CODE (x1))
3145 x1 = SUBREG_REG (x1);
3146 if (GET_CODE (x1) != REG)
3152 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3156 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3168 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3180 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3185 if (TARGET_DEBUG_ADDR)
3187 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3188 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3196 /* A C compound statement that attempts to replace X with a valid memory
3197 address for an operand of mode MODE. WIN will be a C statement label
3198 elsewhere in the code; the macro definition may use
3200 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3202 to avoid further processing if the address has become legitimate.
3204 X will always be the result of a call to `break_out_memory_refs', and OLDX
3205 will be the operand that was given to that function to produce X.
3207 The code generated by this macro should not alter the substructure of X. If
3208 it transforms X into a more legitimate form, it should assign X (which will
3209 always be a C variable) a new value.
3211 It is not necessary for this macro to come up with a legitimate address.
3212 The compiler has standard ways of doing so in all cases. In fact, it is
3213 safe for this macro to do nothing. But often a machine-dependent strategy
3214 can generate better code. */
3217 d30v_legitimize_address (x, oldx, mode, strict_p)
3219 rtx oldx ATTRIBUTE_UNUSED;
3220 enum machine_mode mode ATTRIBUTE_UNUSED;
3221 int strict_p ATTRIBUTE_UNUSED;
3225 if (TARGET_DEBUG_ADDR)
3229 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3231 fprintf (stderr, "\ninto:\n");
3236 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3245 /* A C statement or compound statement with a conditional `goto LABEL;'
3246 executed if memory address X (an RTX) can have different meanings depending
3247 on the machine mode of the memory reference it is used for or if the address
3248 is valid for some modes but not others.
3250 Autoincrement and autodecrement addresses typically have mode-dependent
3251 effects because the amount of the increment or decrement is the size of the
3252 operand being addressed. Some machines have other mode-dependent addresses.
3253 Many RISC machines have no mode-dependent addresses.
3255 You may assume that ADDR is a valid address for the machine. */
3258 d30v_mode_dependent_address_p (addr)
3261 switch (GET_CODE (addr))
3275 /* Generate the appropriate comparison code for a test. */
3278 d30v_emit_comparison (test_int, result, arg1, arg2)
3284 enum rtx_code test = (enum rtx_code) test_int;
3285 enum machine_mode mode = GET_MODE (arg1);
3286 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3289 || (mode == DImode && (test == EQ || test == NE))
3290 || (mode == DImode && (test == LT || test == GE)
3291 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3294 else if (mode == DImode)
3295 return gen_rtx (PARALLEL, VOIDmode,
3298 gen_rtx (CLOBBER, VOIDmode,
3299 gen_reg_rtx (CCmode))));
3302 fatal_insn ("d30v_emit_comparison", rtx_test);
3306 /* Return appropriate code to move 2 words. Since DImode registers must start
3307 on even register numbers, there is no possibility of overlap. */
3310 d30v_move_2words (operands, insn)
3314 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3316 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3317 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3319 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3320 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3322 else if (GET_CODE (operands[1]) == MEM)
3323 return "ld2w %0,%M1";
3325 else if (GET_CODE (operands[1]) == CONST_INT
3326 || GET_CODE (operands[1]) == CONST_DOUBLE)
3327 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3330 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3332 if (GET_CODE (operands[1]) == REG
3333 && GPR_P (REGNO (operands[1])))
3334 return "mvtacc %0,%U1,%L1";
3336 if (GET_CODE (operands[1]) == CONST_INT
3337 && INTVAL (operands[1]) == 0)
3338 return "mvtacc %0,%.,%.";
3341 else if (GET_CODE (operands[0]) == MEM
3342 && GET_CODE (operands[1]) == REG
3343 && GPR_P (REGNO (operands[1])))
3344 return "st2w %1,%M0";
3346 fatal_insn ("bad call to d30v_move_2words", insn);
3350 /* Emit the code to do a conditional move instruction. Return FALSE
3351 if the conditional move could not be executed. */
3354 d30v_emit_cond_move (dest, test, true_value, false_value)
3361 enum machine_mode mode = GET_MODE (dest);
3362 int two_mem_moves_p = FALSE;
3364 if (GET_CODE (dest) == MEM)
3366 if (!reg_or_0_operand (true_value, mode))
3369 if (rtx_equal_p (dest, false_value))
3370 two_mem_moves_p = TRUE;
3372 else if (!reg_or_0_operand (false_value, mode))
3376 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3377 to be slower than just doing the conditional execution. */
3379 br_reg = gen_reg_rtx (CCmode);
3380 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3381 d30v_compare_op0, d30v_compare_op1));
3383 if (!two_mem_moves_p)
3384 emit_insn (gen_rtx_SET (VOIDmode,
3386 gen_rtx_IF_THEN_ELSE (mode,
3387 gen_rtx_NE (CCmode, br_reg,
3393 /* Emit conditional stores as two separate stores. This avoids a problem
3394 where you have a conditional store, and one of the arms of the
3395 conditional store is spilled to memory. */
3396 emit_insn (gen_rtx_SET (VOIDmode,
3398 gen_rtx_IF_THEN_ELSE (mode,
3399 gen_rtx_NE (CCmode, br_reg,
3404 emit_insn (gen_rtx_SET (VOIDmode,
3406 gen_rtx_IF_THEN_ELSE (mode,
3407 gen_rtx_EQ (CCmode, br_reg,
3418 /* In rare cases, correct code generation requires extra machine dependent
3419 processing between the second jump optimization pass and delayed branch
3420 scheduling. On those machines, define this macro as a C statement to act on
3421 the code starting at INSN. */
3424 d30v_machine_dependent_reorg (insn)
3425 rtx insn ATTRIBUTE_UNUSED;
3430 /* A C statement (sans semicolon) to update the integer variable COST based on
3431 the relationship between INSN that is dependent on DEP_INSN through the
3432 dependence LINK. The default is to make no adjustment to COST. This can be
3433 used for example to specify to the scheduler that an output- or
3434 anti-dependence does not incur the same cost as a data-dependence. */
3436 /* For the d30v, try to insure that the source operands for a load/store are
3437 set 2 cycles before the memory reference. */
3440 d30v_adjust_cost (insn, link, dep_insn, cost)
3442 rtx link ATTRIBUTE_UNUSED;
3446 rtx set_dep = single_set (dep_insn);
3447 rtx set_insn = single_set (insn);
3449 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3450 && GET_CODE (SET_DEST (set_dep)) == REG)
3452 rtx reg = SET_DEST (set_dep);
3455 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3456 && reg_mentioned_p (reg, XEXP (mem, 0)))
3457 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3458 && reg_mentioned_p (reg, XEXP (mem, 0))))
3467 /* Function which returns the number of insns that can be
3468 scheduled in the same machine cycle. This must be constant
3469 over an entire compilation. The default is 1. */
3477 /* Routine to allocate, mark and free a per-function,
3478 machine specific structure. */
3480 static struct machine_function *
3481 d30v_init_machine_status ()
3483 return ggc_alloc_cleared (sizeof (machine_function));
3486 /* Do anything needed before RTL is emitted for each function. */
3489 d30v_init_expanders ()
3491 /* Arrange to save and restore machine status around nested functions. */
3492 init_machine_status = d30v_init_machine_status;
3495 /* Find the current function's return address.
3497 ??? It would be better to arrange things such that if we would ordinarily
3498 have been a leaf function and we didn't spill the hard reg that we
3499 wouldn't have to save the register in the prolog. But it's not clear
3500 how to get the right information at the right time. */
3505 return get_hard_reg_initial_val (Pmode, GPR_LINK);