1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
43 #include "target-def.h"
45 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
46 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
48 static void d30v_add_gc_roots PARAMS ((void));
49 static void d30v_init_machine_status PARAMS ((struct function *));
50 static void d30v_mark_machine_status PARAMS ((struct function *));
51 static void d30v_free_machine_status PARAMS ((struct function *));
52 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
53 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
54 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
55 static int d30v_issue_rate PARAMS ((void));
57 /* Define the information needed to generate branch and scc insns. This is
58 stored from the compare operation. */
60 struct rtx_def *d30v_compare_op0;
61 struct rtx_def *d30v_compare_op1;
63 /* Cached value of d30v_stack_info */
64 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
66 /* Values of the -mbranch-cost=n string. */
67 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
68 const char *d30v_branch_cost_string = (const char *)0;
70 /* Values of the -mcond-exec=n string. */
71 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
72 const char *d30v_cond_exec_string = (const char *)0;
74 /* Whether or not a hard register can accept a register */
75 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
77 /* Whether to try and avoid moves between two different modes */
78 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
80 /* Map register number to smallest register class. */
81 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
83 /* Map class letter into register class */
84 enum reg_class reg_class_from_letter[256];
86 /* Initialize the GCC target structure. */
87 #undef TARGET_ASM_FUNCTION_PROLOGUE
88 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
89 #undef TARGET_ASM_FUNCTION_EPILOGUE
90 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
91 #undef TARGET_SCHED_ADJUST_COST
92 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
93 #undef TARGET_SCHED_ISSUE_RATE
94 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
96 struct gcc_target targetm = TARGET_INITIALIZER;
98 /* Sometimes certain combinations of command options do not make
99 sense on a particular target machine. You can define a macro
100 `OVERRIDE_OPTIONS' to take account of this. This macro, if
101 defined, is executed once just after all the command options have
104 Don't use this macro to turn on various extra optimizations for
105 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
111 enum machine_mode mode1, mode2;
113 /* Set up the branch cost information */
114 if (d30v_branch_cost_string)
115 d30v_branch_cost = atoi (d30v_branch_cost_string);
117 /* Set up max # instructions to use with conditional execution */
118 if (d30v_cond_exec_string)
119 d30v_cond_exec = atoi (d30v_cond_exec_string);
121 /* Setup hard_regno_mode_ok/modes_tieable_p */
122 for (mode1 = VOIDmode;
123 (int)mode1 < NUM_MACHINE_MODES;
124 mode1 = (enum machine_mode)((int)mode1 + 1))
126 int size = GET_MODE_SIZE (mode1);
127 int large_p = size > UNITS_PER_WORD;
128 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
130 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
132 if (mode1 == VOIDmode)
135 else if (GPR_P (regno))
140 ok_p = (((regno - GPR_FIRST) & 1) == 0);
143 else if (FLAG_P (regno))
144 ok_p = (mode1 == CCmode);
146 else if (CR_P (regno))
147 ok_p = int_p && !large_p;
149 else if (ACCUM_P (regno))
150 ok_p = (mode1 == DImode);
152 else if (SPECIAL_REG_P (regno))
153 ok_p = (mode1 == SImode);
158 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
161 /* A C expression that is nonzero if it is desirable to choose
162 register allocation so as to avoid move instructions between a
163 value of mode MODE1 and a value of mode MODE2.
165 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
166 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
167 MODE2)' must be zero. */
168 for (mode2 = VOIDmode;
169 (int)mode2 <= NUM_MACHINE_MODES;
170 mode2 = (enum machine_mode)((int)mode2 + 1))
176 else if (GET_MODE_CLASS (mode1) == MODE_INT
177 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
178 && GET_MODE_CLASS (mode2) == MODE_INT
179 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
186 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
191 for (mode1 = VOIDmode;
192 (int)mode1 < NUM_MACHINE_MODES;
193 mode1 = (enum machine_mode)((int)mode1 + 1))
195 for (mode2 = VOIDmode;
196 (int)mode2 <= NUM_MACHINE_MODES;
197 mode2 = (enum machine_mode)((int)mode2 + 1))
199 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
201 && (hard_regno_mode_ok[(int)mode1][regno]
202 != hard_regno_mode_ok[(int)mode2][regno]))
203 error ("Bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
204 reg_names[regno], GET_MODE_NAME (mode1),
205 GET_MODE_NAME (mode2));
210 /* A C expression whose value is a register class containing hard
211 register REGNO. In general there is more than one such class;
212 choose a class which is "minimal", meaning that no smaller class
213 also contains the register. */
214 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
216 enum reg_class class;
219 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
220 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
222 else if (regno == FLAG_F0)
225 else if (regno == FLAG_F1)
228 else if (FLAG_P (regno))
229 class = OTHER_FLAG_REGS;
231 else if (ACCUM_P (regno))
234 else if (regno == CR_RPT_C)
237 else if (CR_P (regno))
240 else if (SPECIAL_REG_P (regno))
246 regno_reg_class[regno] = class;
250 static char *names[] = REG_CLASS_NAMES;
251 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
252 for (mode1 = VOIDmode;
253 (int)mode1 < NUM_MACHINE_MODES;
254 mode1 = (enum machine_mode)((int)mode1 + 1))
256 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
257 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
259 fprintf (stderr, "\n");
264 /* A C expression which defines the machine-dependent operand
265 constraint letters for register classes. If CHAR is such a
266 letter, the value should be the register class corresponding to
267 it. Otherwise, the value should be `NO_REGS'. The register
268 letter `r', corresponding to class `GENERAL_REGS', will not be
269 passed to this macro; you do not need to handle it.
271 The following letters are unavailable, due to being used as
276 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
277 'Q', 'R', 'S', 'T', 'U'
279 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
281 for (i = 0; i < 256; i++)
282 reg_class_from_letter[i] = NO_REGS;
284 reg_class_from_letter['a'] = ACCUM_REGS;
285 reg_class_from_letter['b'] = BR_FLAG_REGS;
286 reg_class_from_letter['c'] = CR_REGS;
287 reg_class_from_letter['d'] = GPR_REGS;
288 reg_class_from_letter['e'] = EVEN_REGS;
289 reg_class_from_letter['f'] = FLAG_REGS;
290 reg_class_from_letter['l'] = REPEAT_REGS;
291 reg_class_from_letter['x'] = F0_REGS;
292 reg_class_from_letter['y'] = F1_REGS;
293 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
295 d30v_add_gc_roots ();
299 /* Return true if a memory operand is a short memory operand. */
302 short_memory_operand (op, mode)
304 enum machine_mode mode;
306 if (GET_CODE (op) != MEM)
309 if (GET_MODE (op) != mode && mode != VOIDmode)
312 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
316 /* Return true if a memory operand is a long operand. */
319 long_memory_operand (op, mode)
321 enum machine_mode mode;
323 if (GET_CODE (op) != MEM)
326 if (GET_MODE (op) != mode && mode != VOIDmode)
329 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
333 /* Return true if a memory operand is valid for the D30V. */
336 d30v_memory_operand (op, mode)
338 enum machine_mode mode;
340 if (GET_CODE (op) != MEM)
343 if (GET_MODE (op) != mode && mode != VOIDmode)
346 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
350 /* Return true if a memory operand uses a single register for the
354 single_reg_memory_operand (op, mode)
356 enum machine_mode mode;
360 if (GET_CODE (op) != MEM)
363 if (GET_MODE (op) != mode && mode != VOIDmode)
367 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
370 if (GET_CODE (addr) == SUBREG)
371 addr = SUBREG_REG (addr);
373 return (GET_CODE (addr) == REG);
376 /* Return true if a memory operand uses a constant address. */
379 const_addr_memory_operand (op, mode)
381 enum machine_mode mode;
383 if (GET_CODE (op) != MEM)
386 if (GET_MODE (op) != mode && mode != VOIDmode)
389 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
392 switch (GET_CODE (XEXP (op, 0)))
407 /* Return true if operand is a memory reference suitable for a call. */
410 call_operand (op, mode)
412 enum machine_mode mode;
414 if (GET_CODE (op) != MEM)
417 if (GET_MODE (op) != mode && mode != VOIDmode)
420 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
423 switch (GET_CODE (XEXP (op, 0)))
429 op = SUBREG_REG (op);
430 if (GET_CODE (op) != REG)
436 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
448 /* Return true if operand is a GPR register. */
451 gpr_operand (op, mode)
453 enum machine_mode mode;
455 if (GET_MODE (op) != mode && mode != VOIDmode)
458 if (GET_CODE (op) == SUBREG)
460 if (GET_CODE (SUBREG_REG (op)) != REG)
461 return register_operand (op, mode);
463 op = SUBREG_REG (op);
466 if (GET_CODE (op) != REG)
469 return GPR_OR_PSEUDO_P (REGNO (op));
472 /* Return true if operand is an accumulator register. */
475 accum_operand (op, mode)
477 enum machine_mode mode;
479 if (GET_MODE (op) != mode && mode != VOIDmode)
482 if (GET_CODE (op) == SUBREG)
484 if (GET_CODE (SUBREG_REG (op)) != REG)
485 return register_operand (op, mode);
487 op = SUBREG_REG (op);
490 if (GET_CODE (op) != REG)
493 return ACCUM_OR_PSEUDO_P (REGNO (op));
496 /* Return true if operand is a GPR or an accumulator register. */
499 gpr_or_accum_operand (op, mode)
501 enum machine_mode mode;
503 if (GET_MODE (op) != mode && mode != VOIDmode)
506 if (GET_CODE (op) == SUBREG)
508 if (GET_CODE (SUBREG_REG (op)) != REG)
509 return register_operand (op, mode);
511 op = SUBREG_REG (op);
514 if (GET_CODE (op) != REG)
517 if (ACCUM_P (REGNO (op)))
520 return GPR_OR_PSEUDO_P (REGNO (op));
523 /* Return true if operand is a CR register. */
526 cr_operand (op, mode)
528 enum machine_mode mode;
530 if (GET_MODE (op) != mode && mode != VOIDmode)
533 if (GET_CODE (op) == SUBREG)
535 if (GET_CODE (SUBREG_REG (op)) != REG)
536 return register_operand (op, mode);
538 op = SUBREG_REG (op);
541 if (GET_CODE (op) != REG)
544 return CR_OR_PSEUDO_P (REGNO (op));
547 /* Return true if operand is the repeat count register. */
550 repeat_operand (op, mode)
552 enum machine_mode mode;
554 if (GET_MODE (op) != mode && mode != VOIDmode)
557 if (GET_CODE (op) == SUBREG)
559 if (GET_CODE (SUBREG_REG (op)) != REG)
560 return register_operand (op, mode);
562 op = SUBREG_REG (op);
565 if (GET_CODE (op) != REG)
568 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
571 /* Return true if operand is a FLAG register. */
574 flag_operand (op, mode)
576 enum machine_mode mode;
578 if (GET_MODE (op) != mode && mode != VOIDmode)
581 if (GET_CODE (op) == SUBREG)
583 if (GET_CODE (SUBREG_REG (op)) != REG)
584 return register_operand (op, mode);
586 op = SUBREG_REG (op);
589 if (GET_CODE (op) != REG)
592 return FLAG_OR_PSEUDO_P (REGNO (op));
595 /* Return true if operand is either F0 or F1. */
598 br_flag_operand (op, mode)
600 enum machine_mode mode;
602 if (GET_MODE (op) != mode && mode != VOIDmode)
605 if (GET_CODE (op) == SUBREG)
607 if (GET_CODE (SUBREG_REG (op)) != REG)
608 return register_operand (op, mode);
610 op = SUBREG_REG (op);
613 if (GET_CODE (op) != REG)
616 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
619 /* Return true if operand is either F0/F1 or the constants 0/1. */
622 br_flag_or_constant_operand (op, mode)
624 enum machine_mode mode;
626 if (GET_MODE (op) != mode && mode != VOIDmode)
629 if (GET_CODE (op) == SUBREG)
631 if (GET_CODE (SUBREG_REG (op)) != REG)
632 return register_operand (op, mode);
634 op = SUBREG_REG (op);
637 if (GET_CODE (op) == CONST_INT)
638 return (INTVAL (op) == 0 || INTVAL (op) == 1);
640 if (GET_CODE (op) != REG)
643 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
646 /* Return true if operand is either F0 or F1, or a GPR register. */
649 gpr_or_br_flag_operand (op, mode)
651 enum machine_mode mode;
653 if (GET_MODE (op) != mode && mode != VOIDmode)
656 if (GET_CODE (op) == SUBREG)
658 if (GET_CODE (SUBREG_REG (op)) != REG)
659 return register_operand (op, mode);
661 op = SUBREG_REG (op);
664 if (GET_CODE (op) != REG)
667 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
670 /* Return true if operand is the F0 register. */
673 f0_operand (op, mode)
675 enum machine_mode mode;
677 if (GET_MODE (op) != mode && mode != VOIDmode)
680 if (GET_CODE (op) == SUBREG)
682 if (GET_CODE (SUBREG_REG (op)) != REG)
683 return register_operand (op, mode);
685 op = SUBREG_REG (op);
688 if (GET_CODE (op) != REG)
691 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
694 /* Return true if operand is the F1 register. */
697 f1_operand (op, mode)
699 enum machine_mode mode;
701 if (GET_MODE (op) != mode && mode != VOIDmode)
704 if (GET_CODE (op) == SUBREG)
706 if (GET_CODE (SUBREG_REG (op)) != REG)
707 return register_operand (op, mode);
709 op = SUBREG_REG (op);
712 if (GET_CODE (op) != REG)
715 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
718 /* Return true if operand is the F1 register. */
721 carry_operand (op, mode)
723 enum machine_mode mode;
725 if (GET_MODE (op) != mode && mode != VOIDmode)
728 if (GET_CODE (op) == SUBREG)
730 if (GET_CODE (SUBREG_REG (op)) != REG)
731 return register_operand (op, mode);
733 op = SUBREG_REG (op);
736 if (GET_CODE (op) != REG)
739 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
742 /* Return true if operand is a register of any flavor or a 0 of the
746 reg_or_0_operand (op, mode)
748 enum machine_mode mode;
750 switch (GET_CODE (op))
757 if (GET_MODE (op) != mode && mode != VOIDmode)
760 return register_operand (op, mode);
763 return INTVAL (op) == 0;
766 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
772 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
775 gpr_or_signed6_operand (op, mode)
777 enum machine_mode mode;
779 if (GET_CODE (op) == SUBREG)
781 if (GET_CODE (SUBREG_REG (op)) != REG)
782 return register_operand (op, mode);
784 op = SUBREG_REG (op);
787 if (GET_CODE (op) == CONST_INT)
788 return IN_RANGE_P (INTVAL (op), -32, 31);
790 if (GET_CODE (op) != REG)
793 if (GET_MODE (op) != mode && mode != VOIDmode)
796 return GPR_OR_PSEUDO_P (REGNO (op));
799 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
802 gpr_or_unsigned5_operand (op, mode)
804 enum machine_mode mode;
806 if (GET_CODE (op) == SUBREG)
808 if (GET_CODE (SUBREG_REG (op)) != REG)
809 return register_operand (op, mode);
811 op = SUBREG_REG (op);
814 if (GET_CODE (op) == CONST_INT)
815 return IN_RANGE_P (INTVAL (op), 0, 31);
817 if (GET_CODE (op) != REG)
820 if (GET_MODE (op) != mode && mode != VOIDmode)
823 return GPR_OR_PSEUDO_P (REGNO (op));
826 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
829 gpr_or_unsigned6_operand (op, mode)
831 enum machine_mode mode;
833 if (GET_CODE (op) == SUBREG)
835 if (GET_CODE (SUBREG_REG (op)) != REG)
836 return register_operand (op, mode);
838 op = SUBREG_REG (op);
841 if (GET_CODE (op) == CONST_INT)
842 return IN_RANGE_P (INTVAL (op), 0, 63);
844 if (GET_CODE (op) != REG)
847 if (GET_MODE (op) != mode && mode != VOIDmode)
850 return GPR_OR_PSEUDO_P (REGNO (op));
853 /* Return true if operand is a GPR register or a constant of some form. */
856 gpr_or_constant_operand (op, mode)
858 enum machine_mode mode;
860 switch (GET_CODE (op))
872 if (GET_CODE (SUBREG_REG (op)) != REG)
873 return register_operand (op, mode);
875 op = SUBREG_REG (op);
879 if (GET_MODE (op) != mode && mode != VOIDmode)
882 return GPR_OR_PSEUDO_P (REGNO (op));
888 /* Return true if operand is a GPR register or a constant of some form,
889 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
892 gpr_or_dbl_const_operand (op, mode)
894 enum machine_mode mode;
896 switch (GET_CODE (op))
909 if (GET_CODE (SUBREG_REG (op)) != REG)
910 return register_operand (op, mode);
912 op = SUBREG_REG (op);
916 if (GET_MODE (op) != mode && mode != VOIDmode)
919 return GPR_OR_PSEUDO_P (REGNO (op));
925 /* Return true if operand is a gpr register or a valid memory operation. */
928 gpr_or_memory_operand (op, mode)
930 enum machine_mode mode;
932 switch (GET_CODE (op))
938 if (GET_CODE (SUBREG_REG (op)) != REG)
939 return register_operand (op, mode);
941 op = SUBREG_REG (op);
945 if (GET_MODE (op) != mode && mode != VOIDmode)
948 return GPR_OR_PSEUDO_P (REGNO (op));
951 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
957 /* Return true if operand is something that can be an input for a move
961 move_input_operand (op, mode)
963 enum machine_mode mode;
968 switch (GET_CODE (op))
981 if (GET_MODE (op) != mode && mode != VOIDmode)
984 subreg = SUBREG_REG (op);
985 code = GET_CODE (subreg);
987 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
990 return (code == REG);
993 if (GET_MODE (op) != mode && mode != VOIDmode)
999 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1001 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1008 /* Return true if operand is something that can be an output for a move
1012 move_output_operand (op, mode)
1014 enum machine_mode mode;
1019 switch (GET_CODE (op))
1025 if (GET_MODE (op) != mode && mode != VOIDmode)
1028 subreg = SUBREG_REG (op);
1029 code = GET_CODE (subreg);
1031 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1034 return (code == REG);
1037 if (GET_MODE (op) != mode && mode != VOIDmode)
1043 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1045 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1052 /* Return true if operand is a signed 6 bit immediate. */
1055 signed6_operand (op, mode)
1057 enum machine_mode mode ATTRIBUTE_UNUSED;
1059 if (GET_CODE (op) == CONST_INT)
1060 return IN_RANGE_P (INTVAL (op), -32, 31);
1065 /* Return true if operand is an unsigned 5 bit immediate. */
1068 unsigned5_operand (op, mode)
1070 enum machine_mode mode ATTRIBUTE_UNUSED;
1072 if (GET_CODE (op) == CONST_INT)
1073 return IN_RANGE_P (INTVAL (op), 0, 31);
1078 /* Return true if operand is an unsigned 6 bit immediate. */
1081 unsigned6_operand (op, mode)
1083 enum machine_mode mode ATTRIBUTE_UNUSED;
1085 if (GET_CODE (op) == CONST_INT)
1086 return IN_RANGE_P (INTVAL (op), 0, 63);
1091 /* Return true if operand is a constant with a single bit set. */
1094 bitset_operand (op, mode)
1096 enum machine_mode mode ATTRIBUTE_UNUSED;
1098 if (GET_CODE (op) == CONST_INT)
1099 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1104 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1105 used in conditional execution. */
1108 condexec_test_operator (op, mode)
1110 enum machine_mode mode;
1114 if (GET_MODE (op) != mode && mode != VOIDmode)
1117 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1121 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1125 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1131 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1132 register that can be used in a branch instruction. */
1135 condexec_branch_operator (op, mode)
1137 enum machine_mode mode;
1141 if (GET_MODE (op) != mode && mode != VOIDmode)
1144 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1148 if (GET_CODE (x0) == REG)
1150 int regno = REGNO (x0);
1151 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1154 /* Allow the optimizer to generate things like:
1155 (if_then_else (ne (const_int 1) (const_int 0))) */
1156 else if (GET_CODE (x0) != CONST_INT)
1160 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1166 /* Return true if the unary operator can be executed with conditional
1170 condexec_unary_operator (op, mode)
1172 enum machine_mode mode ATTRIBUTE_UNUSED;
1176 /* Only do this after register allocation, so that we can look at the register # */
1177 if (!reload_completed)
1180 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1184 if (GET_CODE (op0) == SUBREG)
1185 op0 = SUBREG_REG (op0);
1187 switch (GET_CODE (op))
1194 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1203 /* Return true if the add or subtraction can be executed with conditional
1207 condexec_addsub_operator (op, mode)
1209 enum machine_mode mode ATTRIBUTE_UNUSED;
1213 /* Only do this after register allocation, so that we can look at the register # */
1214 if (!reload_completed)
1217 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1223 if (GET_CODE (op0) == SUBREG)
1224 op0 = SUBREG_REG (op0);
1226 if (GET_CODE (op1) == SUBREG)
1227 op1 = SUBREG_REG (op1);
1229 if (GET_CODE (op0) != REG)
1232 switch (GET_CODE (op))
1239 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1240 && gpr_or_constant_operand (op1, SImode));
1246 /* Return true if the binary operator can be executed with conditional
1247 execution. We don't include add/sub here, since they have extra
1248 clobbers for the flags registers. */
1251 condexec_binary_operator (op, mode)
1253 enum machine_mode mode ATTRIBUTE_UNUSED;
1257 /* Only do this after register allocation, so that we can look at the register # */
1258 if (!reload_completed)
1261 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1267 if (GET_CODE (op0) == SUBREG)
1268 op0 = SUBREG_REG (op0);
1270 if (GET_CODE (op1) == SUBREG)
1271 op1 = SUBREG_REG (op1);
1273 if (GET_CODE (op0) != REG)
1276 /* MULT is not included here, because it is an IU only instruction. */
1277 switch (GET_CODE (op))
1288 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1289 && gpr_or_constant_operand (op1, SImode));
1293 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1294 && GET_CODE (op1) == CONST_INT);
1300 /* Return true if the shift/rotate left operator can be executed with
1301 conditional execution. */
1304 condexec_shiftl_operator (op, mode)
1306 enum machine_mode mode ATTRIBUTE_UNUSED;
1310 /* Only do this after register allocation, so that we can look at the register # */
1311 if (!reload_completed)
1314 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1320 if (GET_CODE (op0) == SUBREG)
1321 op0 = SUBREG_REG (op0);
1323 if (GET_CODE (op1) == SUBREG)
1324 op1 = SUBREG_REG (op1);
1326 if (GET_CODE (op0) != REG)
1329 switch (GET_CODE (op))
1336 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1337 && GET_CODE (op1) == NEG
1338 && GET_CODE (XEXP (op1, 0)) == REG
1339 && GPR_P (REGNO (XEXP (op1, 0))));
1345 /* Return true if the {sign,zero} extend operator from memory can be
1346 conditionally executed. */
1349 condexec_extend_operator (op, mode)
1351 enum machine_mode mode ATTRIBUTE_UNUSED;
1353 /* Only do this after register allocation, so that we can look at the register # */
1354 if (!reload_completed)
1357 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1360 switch (GET_CODE (op))
1367 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1368 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1369 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1378 /* Return true for comparisons against 0 that can be turned into a
1379 bratnz/bratzr instruction. */
1382 branch_zero_operator (op, mode)
1384 enum machine_mode mode;
1388 if (GET_MODE (op) != mode && mode != VOIDmode)
1391 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1395 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1399 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1405 /* Return true if an operand is simple, suitable for use as the destination of
1406 a conditional move */
1409 cond_move_dest_operand (op, mode)
1411 enum machine_mode mode ATTRIBUTE_UNUSED;
1415 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1418 switch (GET_CODE (op))
1425 return gpr_operand (op, mode);
1427 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1429 addr = XEXP (op, 0);
1430 return (GET_CODE (addr) != POST_DEC
1431 && GET_CODE (addr) != POST_INC
1432 && d30v_legitimate_address_p (mode, addr, reload_completed));
1438 /* Return true if an operand is simple, suitable for use in a conditional move */
1441 cond_move_operand (op, mode)
1443 enum machine_mode mode ATTRIBUTE_UNUSED;
1447 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1450 switch (GET_CODE (op))
1457 return gpr_operand (op, mode);
1460 return GET_MODE (op) == SFmode;
1468 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1470 addr = XEXP (op, 0);
1471 return (GET_CODE (addr) != POST_DEC
1472 && GET_CODE (addr) != POST_INC
1473 && d30v_legitimate_address_p (mode, addr, reload_completed));
1479 /* Return true if an operand is simple, suitable for use in conditional execution.
1480 Unlike cond_move, we can allow auto inc/dec. */
1483 cond_exec_operand (op, mode)
1485 enum machine_mode mode;
1487 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1490 switch (GET_CODE (op))
1497 return gpr_operand (op, mode);
1500 return GET_MODE (op) == SFmode;
1509 return memory_operand (op, mode);
1515 /* Return true if operand is a SI mode signed relational test. */
1518 srelational_si_operator (op, mode)
1520 enum machine_mode mode;
1524 if (GET_MODE (op) != mode && mode != VOIDmode)
1527 switch (GET_CODE (op))
1542 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1545 if (GET_MODE (x0) != SImode)
1549 switch (GET_CODE (x1))
1566 /* Return true if operand is a SI mode unsigned relational test. */
1569 urelational_si_operator (op, mode)
1571 enum machine_mode mode;
1575 if (GET_MODE (op) != mode && mode != VOIDmode)
1578 switch (GET_CODE (op))
1591 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1594 if (GET_MODE (x0) != SImode)
1598 switch (GET_CODE (x1))
1615 /* Return true if operand is a DI mode relational test. */
1618 relational_di_operator (op, mode)
1620 enum machine_mode mode;
1624 if (GET_MODE (op) != mode && mode != VOIDmode)
1627 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1631 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1634 if (GET_MODE (x0) != DImode)
1638 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1639 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1646 /* Calculate the stack information for the current function.
1648 D30V stack frames look like:
1651 +-------------------------------+
1652 | Argument word #19 |
1653 +-------------------------------+
1654 | Argument word #18 |
1655 +-------------------------------+
1656 | Argument word #17 |
1657 +-------------------------------+
1658 | Argument word #16 |
1659 Prev sp +-------------------------------+
1661 | Save for arguments 1..16 if |
1662 | the func. uses stdarg/varargs |
1664 +-------------------------------+
1666 | Save area for GPR registers |
1668 +-------------------------------+
1670 | Save area for accumulators |
1672 +-------------------------------+
1676 +-------------------------------+
1678 | alloca space if used |
1680 +-------------------------------+
1682 | Space for outgoing arguments |
1684 low SP----> +-------------------------------+
1690 static d30v_stack_t info, zero_info;
1691 d30v_stack_t *info_ptr = &info;
1692 tree fndecl = current_function_decl;
1693 tree fntype = TREE_TYPE (fndecl);
1701 unsigned char save_gpr_p[GPR_LAST];
1704 /* If we've already calculated the values and reload is complete, just return now */
1705 if (d30v_stack_cache)
1706 return d30v_stack_cache;
1708 /* Zero all fields */
1712 regs_ever_live[GPR_LINK] = 1;
1714 /* Determine if this is a stdarg function */
1715 if (TYPE_ARG_TYPES (fntype) != 0
1716 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1720 /* Find the last argument, and see if it is __builtin_va_alist. */
1721 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1723 next_arg = TREE_CHAIN (cur_arg);
1724 if (next_arg == (tree)0)
1726 if (DECL_NAME (cur_arg)
1727 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1735 /* Calculate which registers need to be saved & save area size */
1739 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1741 if (regs_ever_live[i] && !call_used_regs[i])
1743 info_ptr->save_p[i] = 2;
1750 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1752 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1761 /* Determine which register pairs can be saved together with ld2w/st2w */
1762 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1764 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1767 info_ptr->save_p[i++] = 2;
1769 else if (save_gpr_p[i])
1772 info_ptr->save_p[i] = 1;
1776 /* Determine various sizes */
1777 info_ptr->varargs_p = varargs_p;
1778 info_ptr->varargs_size = ((varargs_p)
1779 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1782 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1783 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1784 2 * UNITS_PER_WORD);
1785 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1786 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1787 2 * UNITS_PER_WORD);
1789 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1790 + info_ptr->accum_size
1791 + info_ptr->vars_size
1792 + info_ptr->parm_size
1793 + info_ptr->varargs_size
1794 + current_function_pretend_args_size),
1795 (STACK_BOUNDARY / BITS_PER_UNIT));
1797 info_ptr->save_offset = (info_ptr->total_size
1798 - (current_function_pretend_args_size
1799 + info_ptr->varargs_size
1800 + info_ptr->gpr_size
1801 + info_ptr->accum_size));
1803 /* The link register is the last GPR saved, but there might be some padding
1804 bytes after it, so account for that. */
1805 info_ptr->link_offset = (info_ptr->total_size
1806 - (current_function_pretend_args_size
1807 + info_ptr->varargs_size
1808 + (info_ptr->gpr_size
1809 - UNITS_PER_WORD * saved_gprs)
1812 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1813 info_ptr->memrefs_2words = memrefs_2words;
1814 info_ptr->memrefs_1word = memrefs_1word;
1816 if (reload_completed)
1817 d30v_stack_cache = info_ptr;
1823 /* Internal function to print all of the information about the stack */
1826 debug_stack_info (info)
1832 info = d30v_stack_info ();
1834 fprintf (stderr, "\nStack information for function %s:\n",
1835 ((current_function_decl && DECL_NAME (current_function_decl))
1836 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1839 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1840 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1841 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1842 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1843 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1844 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1845 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1846 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1847 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1848 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1849 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1850 fprintf (stderr, "\tsaved registers =");
1852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1854 if (info->save_p[i] == 2)
1856 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1859 else if (info->save_p[i])
1860 fprintf (stderr, " %s", reg_names[i]);
1863 putc ('\n', stderr);
1868 /* Return non-zero if this function is known to have a null or 1 instruction epilogue. */
1873 if (reload_completed)
1875 d30v_stack_t *info = d30v_stack_info ();
1877 /* If no epilogue code is needed, can use just a simple jump */
1878 if (info->total_size == 0)
1882 /* If just a small amount of local stack was allocated and no registers
1883 saved, skip forward branch */
1884 if (info->total_size == info->vars_size
1885 && IN_RANGE_P (info->total_size, 1, 31))
1894 /* A C statement (sans semicolon) for initializing the variable CUM for the
1895 state at the beginning of the argument list. The variable has type
1896 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1897 of the function which will receive the args, or 0 if the args are to a
1898 compiler support library function. The value of INDIRECT is nonzero when
1899 processing an indirect call, for example a call through a function pointer.
1900 The value of INDIRECT is zero for a call to an explicitly named function, a
1901 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1902 arguments for the function being compiled.
1904 When processing a call to a compiler support library function, LIBNAME
1905 identifies which one. It is a `symbol_ref' rtx which contains the name of
1906 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1907 being processed. Thus, each time this macro is called, either LIBNAME or
1908 FNTYPE is nonzero, but never both of them at once. */
1911 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1912 CUMULATIVE_ARGS *cum;
1918 *cum = GPR_ARG_FIRST;
1920 if (TARGET_DEBUG_ARG)
1922 fprintf (stderr, "\ninit_cumulative_args:");
1924 fputs (" indirect", stderr);
1927 fputs (" incoming", stderr);
1931 tree ret_type = TREE_TYPE (fntype);
1932 fprintf (stderr, " return=%s,",
1933 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1936 if (libname && GET_CODE (libname) == SYMBOL_REF)
1937 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1939 putc ('\n', stderr);
1944 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1945 argument with the specified mode and type. If it is not defined,
1946 `PARM_BOUNDARY' is used for all arguments. */
1949 d30v_function_arg_boundary (mode, type)
1950 enum machine_mode mode;
1953 int size = ((mode == BLKmode && type)
1954 ? int_size_in_bytes (type)
1955 : GET_MODE_SIZE (mode));
1957 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1961 /* A C expression that controls whether a function argument is passed in a
1962 register, and which register.
1964 The arguments are CUM, which summarizes all the previous arguments; MODE,
1965 the machine mode of the argument; TYPE, the data type of the argument as a
1966 tree node or 0 if that is not known (which happens for C support library
1967 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1968 nameless arguments that correspond to `...' in the called function's
1971 The value of the expression should either be a `reg' RTX for the hard
1972 register in which to pass the argument, or zero to pass the argument on the
1975 For machines like the VAX and 68000, where normally all arguments are
1976 pushed, zero suffices as a definition.
1978 The usual way to make the ANSI library `stdarg.h' work on a machine where
1979 some arguments are usually passed in registers, is to cause nameless
1980 arguments to be passed on the stack instead. This is done by making
1981 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1983 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1984 this macro to determine if this argument is of a type that must be passed in
1985 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1986 returns non-zero for such an argument, the compiler will abort. If
1987 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1988 stack and then loaded into a register. */
1991 d30v_function_arg (cum, mode, type, named, incoming)
1992 CUMULATIVE_ARGS *cum;
1993 enum machine_mode mode;
1996 int incoming ATTRIBUTE_UNUSED;
1998 int size = ((mode == BLKmode && type)
1999 ? int_size_in_bytes (type)
2000 : GET_MODE_SIZE (mode));
2001 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2004 /* Return a marker for use in the call instruction. */
2005 if (mode == VOIDmode)
2008 else if (*cum + adjust <= GPR_ARG_LAST)
2009 ret = gen_rtx (REG, mode, *cum + adjust);
2014 if (TARGET_DEBUG_ARG)
2016 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2017 *cum, GET_MODE_NAME (mode), named, size, adjust,
2018 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2024 /* A C expression for the number of words, at the beginning of an argument,
2025 must be put in registers. The value must be zero for arguments that are
2026 passed entirely in registers or that are entirely pushed on the stack.
2028 On some machines, certain arguments must be passed partially in registers
2029 and partially in memory. On these machines, typically the first N words of
2030 arguments are passed in registers, and the rest on the stack. If a
2031 multi-word argument (a `double' or a structure) crosses that boundary, its
2032 first few words must be passed in registers and the rest must be pushed.
2033 This macro tells the compiler when this occurs, and how many of the words
2034 should go in registers.
2036 `FUNCTION_ARG' for these arguments should return the first register to be
2037 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2038 the called function. */
2041 d30v_function_arg_partial_nregs (cum, mode, type, named)
2042 CUMULATIVE_ARGS *cum;
2043 enum machine_mode mode;
2045 int named ATTRIBUTE_UNUSED;
2047 int bytes = ((mode == BLKmode)
2048 ? int_size_in_bytes (type)
2049 : GET_MODE_SIZE (mode));
2050 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2051 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2052 int arg_num = *cum + adjust;
2055 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2056 ? GPR_ARG_LAST - arg_num + 1
2059 if (TARGET_DEBUG_ARG && ret)
2060 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2066 /* A C expression that indicates when an argument must be passed by reference.
2067 If nonzero for an argument, a copy of that argument is made in memory and a
2068 pointer to the argument is passed instead of the argument itself. The
2069 pointer is passed in whatever way is appropriate for passing a pointer to
2072 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2073 definition of this macro might be
2074 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2075 (CUM, MODE, TYPE, NAMED) \
2076 MUST_PASS_IN_STACK (MODE, TYPE) */
2079 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2080 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2081 enum machine_mode mode;
2083 int named ATTRIBUTE_UNUSED;
2085 int ret = MUST_PASS_IN_STACK (mode, type);
2087 if (TARGET_DEBUG_ARG && ret)
2088 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2094 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2095 advance past an argument in the argument list. The values MODE, TYPE and
2096 NAMED describe that argument. Once this is done, the variable CUM is
2097 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2099 This macro need not do anything if the argument in question was passed on
2100 the stack. The compiler knows how to track the amount of stack space used
2101 for arguments without any special help. */
2104 d30v_function_arg_advance (cum, mode, type, named)
2105 CUMULATIVE_ARGS *cum;
2106 enum machine_mode mode;
2110 int bytes = ((mode == BLKmode)
2111 ? int_size_in_bytes (type)
2112 : GET_MODE_SIZE (mode));
2113 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2114 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2116 *cum += words + adjust;
2118 if (TARGET_DEBUG_ARG)
2120 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2121 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2125 /* If defined, is a C expression that produces the machine-specific code for a
2126 call to `__builtin_saveregs'. This code will be moved to the very beginning
2127 of the function, before any parameter access are made. The return value of
2128 this function should be an RTX that contains the value to use as the return
2129 of `__builtin_saveregs'.
2131 If this macro is not defined, the compiler will output an ordinary call to
2132 the library function `__builtin_saveregs'. */
2135 d30v_expand_builtin_saveregs ()
2137 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2139 if (TARGET_DEBUG_ARG)
2140 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2143 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2147 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2148 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2149 arguments into the stack so that all the arguments appear to have been
2150 passed consecutively on the stack. Once this is done, you can use the
2151 standard implementation of varargs that works for machines that pass all
2152 their arguments on the stack.
2154 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2155 the values that obtain after processing of the named arguments. The
2156 arguments MODE and TYPE describe the last named argument--its machine mode
2157 and its data type as a tree node.
2159 The macro implementation should do two things: first, push onto the stack
2160 all the argument registers *not* used for the named arguments, and second,
2161 store the size of the data thus pushed into the `int'-valued variable whose
2162 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2163 store here will serve as additional offset for setting up the stack frame.
2165 Because you must generate code to push the anonymous arguments at compile
2166 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2167 useful on machines that have just a single category of argument register and
2168 use it uniformly for all data types.
2170 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2171 function are being analyzed for the second time. This happens for an inline
2172 function, which is not actually compiled until the end of the source file.
2173 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2177 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2178 CUMULATIVE_ARGS *cum;
2179 enum machine_mode mode;
2180 tree type ATTRIBUTE_UNUSED;
2181 int *pretend_size ATTRIBUTE_UNUSED;
2184 if (TARGET_DEBUG_ARG)
2186 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2187 *cum, GET_MODE_NAME (mode), second_time);
2191 /* Create the va_list data type. */
2194 d30v_build_va_list ()
2196 tree f_arg_ptr, f_arg_num, record, type_decl;
2199 record = make_lang_type (RECORD_TYPE);
2200 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2201 int_type_node = make_signed_type (INT_TYPE_SIZE);
2203 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2205 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2208 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2209 DECL_FIELD_CONTEXT (f_arg_num) = record;
2211 TREE_CHAIN (record) = type_decl;
2212 TYPE_NAME (record) = type_decl;
2213 TYPE_FIELDS (record) = f_arg_ptr;
2214 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2216 layout_type (record);
2218 /* The correct type is an array type of one element. */
2219 return build_array_type (record, build_index_type (size_zero_node));
2223 /* Expand __builtin_va_start to do the va_start macro. */
2226 d30v_expand_builtin_va_start (stdarg_p, valist, nextarg)
2227 int stdarg_p ATTRIBUTE_UNUSED;
2229 rtx nextarg ATTRIBUTE_UNUSED;
2231 HOST_WIDE_INT words;
2232 tree f_arg_ptr, f_arg_num;
2233 tree arg_ptr, arg_num, saveregs, t;
2235 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2236 f_arg_num = TREE_CHAIN (f_arg_ptr);
2238 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2239 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2240 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2242 words = current_function_args_info; /* __builtin_args_info (0) */
2244 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2245 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2246 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2247 TREE_SIDE_EFFECTS (t) = 1;
2248 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2250 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2251 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2252 build_int_2 (-GPR_ARG_FIRST, 0));
2253 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2254 TREE_SIDE_EFFECTS (t) = 1;
2255 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2259 /* Expand __builtin_va_arg to do the va_arg macro. */
2262 d30v_expand_builtin_va_arg(valist, type)
2266 tree f_arg_ptr, f_arg_num;
2267 tree arg_ptr, arg_num, t, ptr;
2269 rtx lab_false, ptr_rtx, r;
2271 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2272 f_arg_num = TREE_CHAIN (f_arg_ptr);
2274 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2275 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2276 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2278 size = int_size_in_bytes (type);
2280 lab_false = gen_label_rtx ();
2281 ptr_rtx = gen_reg_rtx (Pmode);
2283 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2284 (AP)->__va_arg_num++; */
2286 if (size > UNITS_PER_WORD)
2288 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2289 build_int_2 (1, 0));
2291 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2292 GEN_INT (0), EQ, const1_rtx, QImode, 1, 1,
2295 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2296 build_int_2 (1, 0));
2297 TREE_SIDE_EFFECTS (t) = 1;
2298 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2300 emit_label (lab_false);
2304 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2305 + (AP)->__va_arg_num))); */
2307 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2308 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2310 /* if (sizeof (TYPE) < 4)
2311 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2313 if (size < UNITS_PER_WORD)
2314 t = build (PLUS_EXPR, ptr_type_node, t,
2315 build_int_2 (UNITS_PER_WORD - size, 0));
2317 TREE_SIDE_EFFECTS (t) = 1;
2319 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2320 t = build (MODIFY_EXPR, type, ptr, t);
2322 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2324 emit_move_insn (ptr_rtx, r);
2327 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2328 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2329 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2330 build_int_2 (num, 0));
2331 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2336 /* Generate the assembly code for function entry. FILE is a stdio
2337 stream to output the code to. SIZE is an int: how many units of
2338 temporary storage to allocate.
2340 Refer to the array `regs_ever_live' to determine which registers to
2341 save; `regs_ever_live[I]' is nonzero if register number I is ever
2342 used in the function. This function is responsible for knowing
2343 which registers should not be saved even if used. */
2346 d30v_output_function_prologue (stream, size)
2347 FILE *stream ATTRIBUTE_UNUSED;
2348 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2350 /* For the d30v, move all of the prologue processing into separate
2355 /* Called after register allocation to add any instructions needed for
2356 the prologue. Using a prologue insn is favored compared to putting
2357 all of the instructions in output_function_prologue (), since it
2358 allows the scheduler to intermix instructions with the saves of the
2359 caller saved registers. In some cases, it might be necessary to
2360 emit a barrier instruction as the last insn to prevent such
2364 d30v_expand_prologue ()
2366 rtx sp = stack_pointer_rtx;
2367 d30v_stack_t *info = d30v_stack_info ();
2369 rtx mem_di = NULL_RTX;
2370 rtx mem_si = NULL_RTX;
2371 int num_memrefs = (info->memrefs_2words
2372 + info->memrefs_1word
2373 + info->memrefs_varargs);
2375 if (TARGET_DEBUG_STACK)
2376 debug_stack_info (info);
2378 /* Grow the stack. */
2379 if (info->total_size)
2380 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2382 /* If there is more than one save, use post-increment addressing which will
2383 result in smaller code, than would the normal references. If there is
2384 only one save, just do the store as normal. */
2386 if (num_memrefs > 1)
2388 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2389 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2390 mem_di = gen_rtx (MEM, DImode, post_inc);
2391 mem_si = gen_rtx (MEM, SImode, post_inc);
2392 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2394 else if (num_memrefs == 1)
2396 rtx addr = plus_constant (sp, info->save_offset);
2397 mem_di = gen_rtx (MEM, DImode, addr);
2398 mem_si = gen_rtx (MEM, SImode, addr);
2401 /* Save the accumulators. */
2402 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2403 if (info->save_p[i])
2405 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2406 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2407 emit_insn (gen_movdi (mem_di, acc_tmp));
2410 /* Save the GPR registers that are adjacent to each other with st2w. */
2411 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2412 if (info->save_p[i] == 2)
2413 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2415 /* Save the GPR registers that need to be saved with a single word store. */
2416 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2417 if (info->save_p[i] == 1)
2418 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2420 /* Save the argument registers if this function accepts variable args. */
2421 if (info->varargs_p)
2423 /* Realign r22 if an odd # of GPRs were saved. */
2424 if ((info->memrefs_1word & 1) != 0)
2426 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2427 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2430 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2431 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2434 /* Update the frame pointer. */
2435 if (frame_pointer_needed)
2436 emit_move_insn (frame_pointer_rtx, sp);
2438 /* Hack for now, to prevent scheduler from being too cleaver */
2439 emit_insn (gen_blockage ());
2443 /* This function generates the assembly code for function exit.
2444 Args are as for output_function_prologue ().
2446 The function epilogue should not depend on the current stack
2447 pointer! It should use the frame pointer only. This is mandatory
2448 because of alloca; we also take advantage of it to omit stack
2449 adjustments before returning. */
2452 d30v_output_function_epilogue (stream, size)
2453 FILE *stream ATTRIBUTE_UNUSED;
2454 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2456 /* For the d30v, move all processing to be as insns, but do any
2457 cleanup here, since it is done after handling all of the insns. */
2458 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2463 /* Called after register allocation to add any instructions needed for
2464 the epilogue. Using a epilogue insn is favored compared to putting
2465 all of the instructions in output_function_prologue(), since it
2466 allows the scheduler to intermix instructions with the saves of the
2467 caller saved registers. In some cases, it might be necessary to
2468 emit a barrier instruction as the last insn to prevent such
2472 d30v_expand_epilogue ()
2474 rtx sp = stack_pointer_rtx;
2475 d30v_stack_t *info = d30v_stack_info ();
2477 rtx mem_di = NULL_RTX;
2478 rtx mem_si = NULL_RTX;
2482 /* Hack for now, to prevent scheduler from being too cleaver */
2483 emit_insn (gen_blockage ());
2485 /* Restore sp from fp. */
2486 if (frame_pointer_needed)
2487 emit_move_insn (sp, frame_pointer_rtx);
2489 /* For the epilogue, use post-increment addressing all of the time. First
2490 adjust the sp, to eliminate all of the stack, except for the save area. */
2492 if (info->save_offset)
2493 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2495 post_inc = gen_rtx (POST_INC, Pmode, sp);
2496 mem_di = gen_rtx (MEM, DImode, post_inc);
2497 mem_si = gen_rtx (MEM, SImode, post_inc);
2499 /* Restore the accumulators. */
2500 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2501 if (info->save_p[i])
2503 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2504 emit_insn (gen_movdi (acc_tmp, mem_di));
2505 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2508 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2509 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2510 if (info->save_p[i] == 2)
2511 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2513 /* Save the GPR registers that need to be saved with a single word store. */
2515 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2516 if (info->save_p[i] == 1)
2518 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2524 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2527 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2531 /* Release any remaining stack that was allocated for saving the
2532 varargs registers or because an odd # of registers were stored. */
2533 if ((info->memrefs_1word & 1) != 0)
2534 extra_stack += UNITS_PER_WORD;
2535 extra_stack += current_function_pretend_args_size + info->varargs_size;
2539 if (cfun->machine->eh_epilogue_sp_ofs)
2540 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2541 cfun->machine->eh_epilogue_sp_ofs,
2542 GEN_INT (extra_stack)));
2544 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2546 if (cfun->machine->eh_epilogue_sp_ofs)
2547 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2549 /* Now emit the return instruction. */
2550 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2554 /* A C statement or compound statement to output to FILE some assembler code to
2555 call the profiling subroutine `mcount'. Before calling, the assembler code
2556 must load the address of a counter variable into a register where `mcount'
2557 expects to find the address. The name of this variable is `LP' followed by
2558 the number LABELNO, so you would generate the name using `LP%d' in a
2561 The details of how the address should be passed to `mcount' are determined
2562 by your operating system environment, not by GNU CC. To figure them out,
2563 compile a small program for profiling using the system's installed C
2564 compiler and look at the assembler code that results. */
2567 d30v_function_profiler (stream, labelno)
2569 int labelno ATTRIBUTE_UNUSED;
2571 fprintf (stream, "# profile\n");
2575 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2576 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2577 the wrong part for floating point in cross compilers, and split_double does
2578 not handle registers. Also abort if the register is not a general purpose
2582 d30v_split_double (value, p_high, p_low)
2590 if (!reload_completed)
2593 switch (GET_CODE (value))
2596 if (GET_CODE (SUBREG_REG (value)) != REG)
2598 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2599 GET_MODE (SUBREG_REG (value)),
2600 SUBREG_BYTE (value),
2602 value = SUBREG_REG (value);
2607 regno = REGNO (value) + offset;
2611 *p_high = gen_rtx (REG, SImode, regno);
2612 *p_low = gen_rtx (REG, SImode, regno+1);
2617 split_double (value, p_high, p_low);
2626 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2627 for an instruction operand that is a memory reference whose address is X. X
2628 is an RTL expression.
2630 On some machines, the syntax for a symbolic address depends on the section
2631 that the address refers to. On these machines, define the macro
2632 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
2633 then check for it here. *Note Assembler Format::. */
2636 d30v_print_operand_address (stream, x)
2640 if (GET_CODE (x) == MEM)
2643 switch (GET_CODE (x))
2649 fputs (reg_names[ REGNO (x) ], stream);
2653 fprintf (stream, "%ld", (long) INTVAL (x));
2656 /* We wrap simple symbol refs inside a parenthesis, so that a name
2657 like `r2' is not taken for a register name. */
2659 fputs ("(", stream);
2660 assemble_name (stream, XSTR (x, 0));
2661 fputs (")", stream);
2666 output_addr_const (stream, x);
2670 fatal_insn ("Bad insn to d30v_print_operand_address:", x);
2674 /* Print a memory reference suitable for the ld/st instructions. */
2677 d30v_print_operand_memory_reference (stream, x)
2684 switch (GET_CODE (x))
2687 fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
2707 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2708 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2716 fputs ("@(", stream);
2718 fputs (reg_names[GPR_R0], stream);
2725 if (GET_CODE (x0) == SUBREG)
2727 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2728 GET_MODE (SUBREG_REG (x0)),
2731 x0 = SUBREG_REG (x0);
2734 if (GET_CODE (x0) == POST_INC)
2739 else if (GET_CODE (x0) == POST_DEC)
2745 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2746 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2748 fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
2751 fputs (",", stream);
2754 fputs (reg_names[GPR_R0], stream);
2760 switch (GET_CODE (x1))
2763 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2764 GET_MODE (SUBREG_REG (x1)),
2767 x1 = SUBREG_REG (x1);
2768 if (GET_CODE (x1) != REG)
2769 fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
2773 fputs (reg_names[REGNO (x1) + offset1], stream);
2777 fprintf (stream, "%ld", (long) INTVAL (x1));
2783 d30v_print_operand_address (stream, x1);
2787 fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
2791 fputs (")", stream);
2795 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2796 for an instruction operand X. X is an RTL expression.
2798 LETTER is a value that can be used to specify one of several ways of
2799 printing the operand. It is used when identical operands must be printed
2800 differently depending on the context. LETTER comes from the `%'
2801 specification that was used to request printing of the operand. If the
2802 specification was just `%DIGIT' then LETTER is 0; if the specification was
2803 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2805 If X is a register, this macro should print the register's name. The names
2806 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2807 is initialized from `REGISTER_NAMES'.
2809 When the machine description has a specification `%PUNCT' (a `%' followed by
2810 a punctuation character), this macro is called with a null pointer for X and
2811 the punctuation character for LETTER.
2813 Standard operand flags that are handled elsewhere:
2814 `=' Output a number unique to each instruction in the compilation.
2815 `a' Substitute an operand as if it were a memory reference.
2816 `c' Omit the syntax that indicates an immediate operand.
2817 `l' Substitute a LABEL_REF into a jump instruction.
2818 `n' Like %cDIGIT, except negate the value before printing.
2820 The d30v specific operand flags are:
2822 `f' Print a SF constant as an int.
2823 `s' Subtract 32 and negate.
2824 `A' Print accumulator number without an `a' in front of it.
2825 `B' Print bit offset for BSET, etc. instructions.
2826 `E' Print u if this is zero extend, nothing if this is sign extend.
2827 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2828 `L' Print the lower half of a 64 bit item.
2829 `M' Print a memory reference for ld/st instructions.
2830 `R' Return appropriate cmp instruction for relational test.
2832 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2833 `U' Print the upper half of a 64 bit item. */
2836 d30v_print_operand (stream, x, letter)
2841 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2842 rtx split_values[2];
2849 case '.': /* Output r0 */
2850 fputs (reg_names[GPR_R0], stream);
2853 case 'f': /* Print a SF floating constant as an int */
2854 if (GET_CODE (x) != CONST_DOUBLE)
2855 fatal_insn ("Bad insn to d30v_print_operand, 'f' modifier:", x);
2857 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2858 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2859 fprintf (stream, "%ld", num);
2862 case 'A': /* Print accumulator number without an `a' in front of it. */
2863 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2864 fatal_insn ("Bad insn to d30v_print_operand, 'A' modifier:", x);
2866 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2869 case 'M': /* Print a memory reference for ld/st */
2870 if (GET_CODE (x) != MEM)
2871 fatal_insn ("Bad insn to d30v_print_operand, 'M' modifier:", x);
2873 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2876 case 'L': /* print lower part of 64 bit item. */
2877 case 'U': /* print upper part of 64 bit item. */
2878 d30v_split_double (x, &split_values[0], &split_values[1]);
2879 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2882 case ':': /* Output the condition for the current insn. */
2883 x = current_insn_predicate;
2889 case 'F': /* Print an appropriate suffix for a false comparision. */
2890 case 'T': /* Print an appropriate suffix for a true comparision. */
2891 /* Note that the sense of appropriate suffix is for conditional execution
2892 and opposite of what branches want. Branches just use the inverse
2894 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2895 && GET_MODE (x) == CCmode
2896 && GET_CODE (XEXP (x, 0)) == REG
2897 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2898 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2900 int true_false = (letter == 'T');
2902 if (GET_CODE (x) == EQ)
2903 true_false = !true_false;
2905 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2906 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2908 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2909 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2912 fputs ((true_false) ? "tnz" : "tzr", stream);
2915 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2916 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2918 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2919 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2921 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2922 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2925 fatal_insn ("Bad insn to print_operand, 'F' or 'T' modifier:", x);
2928 case 'B': /* emit offset single bit to change */
2929 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2930 fprintf (stream, "%d", 31 - log);
2932 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2933 fprintf (stream, "%d", 31 - log);
2936 fatal_insn ("Bad insn to print_operand, 'B' modifier:", x);
2939 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2940 if (GET_CODE (x) == ZERO_EXTEND)
2942 else if (GET_CODE (x) != SIGN_EXTEND)
2943 fatal_insn ("Bad insn to print_operand, 'E' modifier:", x);
2946 case 'R': /* Return appropriate cmp instruction for relational test. */
2947 switch (GET_CODE (x))
2949 case EQ: fputs ("cmpeq", stream); break;
2950 case NE: fputs ("cmpne", stream); break;
2951 case LT: fputs ("cmplt", stream); break;
2952 case LE: fputs ("cmple", stream); break;
2953 case GT: fputs ("cmpgt", stream); break;
2954 case GE: fputs ("cmpge", stream); break;
2955 case LTU: fputs ("cmpult", stream); break;
2956 case LEU: fputs ("cmpule", stream); break;
2957 case GTU: fputs ("cmpugt", stream); break;
2958 case GEU: fputs ("cmpuge", stream); break;
2961 fatal_insn ("Bad insn to print_operand, 'R' modifier:", x);
2965 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2966 if (GET_CODE (x) == CONST_INT)
2967 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2970 fatal_insn ("Bad insn to print_operand, 's' modifier:", x);
2973 case 'S': /* Subtract 32. */
2974 if (GET_CODE (x) == CONST_INT)
2975 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2978 fatal_insn ("Bad insn to print_operand, 's' modifier:", x);
2982 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2983 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2984 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2985 && CONST_DOUBLE_HIGH (x) == 0))
2987 fputs (reg_names[GPR_FIRST], stream);
2995 fputs (reg_names[ REGNO (x) ], stream);
2997 else if (code == CONST_INT)
2998 fprintf (stream, "%d", (int)INTVAL (x));
3000 else if (code == MEM)
3001 d30v_print_operand_address (stream, XEXP (x, 0));
3003 else if (CONSTANT_ADDRESS_P (x))
3004 d30v_print_operand_address (stream, x);
3007 fatal_insn ("Bad insn in d30v_print_operand, 0 case", x);
3015 sprintf (buf, "Invalid asm template character '%%%c'", letter);
3016 fatal_insn (buf, x);
3022 /* A C expression for the size in bytes of the trampoline, as an integer. */
3025 d30v_trampoline_size ()
3031 /* Create a long instruction for building up a trampoline. */
3034 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3035 HOST_WIDE_INT high_bits;
3036 HOST_WIDE_INT low_bits;
3040 rtx reg = gen_reg_rtx (DImode);
3041 rtx high_word = gen_highpart (SImode, reg);
3042 rtx low_word = gen_lowpart (SImode, reg);
3043 rtx tmp1 = gen_reg_rtx (SImode);
3044 rtx tmp2 = gen_reg_rtx (SImode);
3045 rtx tmp3 = gen_reg_rtx (SImode);
3046 rtx tmp4 = gen_reg_rtx (SImode);
3047 rtx tmp5 = gen_reg_rtx (SImode);
3048 rtx tmp6 = gen_reg_rtx (SImode);
3050 imm = force_reg (SImode, imm);
3052 /* Stuff top 6 bits of immediate value into high word */
3053 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3054 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3055 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3057 /* Now get the next 8 bits for building the low word */
3058 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3059 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3061 /* And the bottom 18 bits */
3062 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3063 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3064 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3066 /* Store the instruction */
3067 emit_insn (gen_movdi (mem, reg));
3071 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3072 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3073 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3074 should be passed to the function when it is called. */
3077 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3082 /* The instruction space can only be accessed by ld2w/st2w.
3083 Generate on the fly:
3084 or r18,r0,<static-chain>
3086 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3087 0x80000000, static_chain,
3088 gen_rtx (MEM, DImode, addr));
3090 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3091 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3095 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3096 RTX) is a legitimate memory address on the target machine for a memory
3097 operand of mode MODE.
3099 It usually pays to define several simpler macros to serve as subroutines for
3100 this one. Otherwise it may be too complicated to understand.
3102 This macro must exist in two variants: a strict variant and a non-strict
3103 one. The strict variant is used in the reload pass. It must be defined so
3104 that any pseudo-register that has not been allocated a hard register is
3105 considered a memory reference. In contexts where some kind of register is
3106 required, a pseudo-register with no hard register must be rejected.
3108 The non-strict variant is used in other passes. It must be defined to
3109 accept all pseudo-registers in every context where some kind of register is
3112 Compiler source files that want to use the strict variant of this macro
3113 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3114 conditional to define the strict variant in that case and the non-strict
3117 Subroutines to check for acceptable registers for various purposes (one for
3118 base registers, one for index registers, and so on) are typically among the
3119 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3120 subroutine macros need have two variants; the higher levels of macros may be
3121 the same whether strict or not.
3123 Normally, constant addresses which are the sum of a `symbol_ref' and an
3124 integer are stored inside a `const' RTX to mark them as constant.
3125 Therefore, there is no need to recognize such sums specifically as
3126 legitimate addresses. Normally you would simply recognize any `const' as
3129 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3130 are not marked with `const'. It assumes that a naked `plus' indicates
3131 indexing. If so, then you *must* reject such naked constant sums as
3132 illegitimate addresses, so that none of them will be given to
3133 `PRINT_OPERAND_ADDRESS'.
3135 On some machines, whether a symbolic address is legitimate depends on the
3136 section that the address refers to. On these machines, define the macro
3137 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3138 then check for it here. When you see a `const', you will have to look
3139 inside it to find the `symbol_ref' in order to determine the section. *Note
3142 The best way to modify the name string is by adding text to the beginning,
3143 with suitable punctuation to prevent any ambiguity. Allocate the new name
3144 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3145 remove and decode the added text and output the name accordingly, and define
3146 `STRIP_NAME_ENCODING' to access the original name string.
3148 You can check the information stored here into the `symbol_ref' in the
3149 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3150 `PRINT_OPERAND_ADDRESS'.
3152 Return 0 if the address is not legitimate, 1 if the address would fit
3153 in a short instruction, or 2 if the address would fit in a long
3156 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3158 ? REGNO_OK_FOR_BASE_P (REGNO) \
3159 : GPR_OR_PSEUDO_P (REGNO))
3162 d30v_legitimate_address_p (mode, x, strict_p)
3163 enum machine_mode mode;
3170 switch (GET_CODE (x))
3177 if (GET_CODE (x) != REG)
3183 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3190 if (GET_CODE (x0) == SUBREG)
3191 x0 = SUBREG_REG (x0);
3193 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3196 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3199 switch (GET_CODE (x1))
3205 x1 = SUBREG_REG (x1);
3206 if (GET_CODE (x1) != REG)
3212 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3216 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3228 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3240 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3245 if (TARGET_DEBUG_ADDR)
3247 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3248 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3256 /* A C compound statement that attempts to replace X with a valid memory
3257 address for an operand of mode MODE. WIN will be a C statement label
3258 elsewhere in the code; the macro definition may use
3260 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3262 to avoid further processing if the address has become legitimate.
3264 X will always be the result of a call to `break_out_memory_refs', and OLDX
3265 will be the operand that was given to that function to produce X.
3267 The code generated by this macro should not alter the substructure of X. If
3268 it transforms X into a more legitimate form, it should assign X (which will
3269 always be a C variable) a new value.
3271 It is not necessary for this macro to come up with a legitimate address.
3272 The compiler has standard ways of doing so in all cases. In fact, it is
3273 safe for this macro to do nothing. But often a machine-dependent strategy
3274 can generate better code. */
3277 d30v_legitimize_address (x, oldx, mode, strict_p)
3279 rtx oldx ATTRIBUTE_UNUSED;
3280 enum machine_mode mode ATTRIBUTE_UNUSED;
3281 int strict_p ATTRIBUTE_UNUSED;
3285 if (TARGET_DEBUG_ADDR)
3289 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3291 fprintf (stderr, "\ninto:\n");
3296 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3305 /* A C statement or compound statement with a conditional `goto LABEL;'
3306 executed if memory address X (an RTX) can have different meanings depending
3307 on the machine mode of the memory reference it is used for or if the address
3308 is valid for some modes but not others.
3310 Autoincrement and autodecrement addresses typically have mode-dependent
3311 effects because the amount of the increment or decrement is the size of the
3312 operand being addressed. Some machines have other mode-dependent addresses.
3313 Many RISC machines have no mode-dependent addresses.
3315 You may assume that ADDR is a valid address for the machine. */
3318 d30v_mode_dependent_address_p (addr)
3321 switch (GET_CODE (addr))
3335 /* Generate the appropriate comparison code for a test. */
3338 d30v_emit_comparison (test_int, result, arg1, arg2)
3344 enum rtx_code test = (enum rtx_code) test_int;
3345 enum machine_mode mode = GET_MODE (arg1);
3346 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3349 || (mode == DImode && (test == EQ || test == NE))
3350 || (mode == DImode && (test == LT || test == GE)
3351 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3354 else if (mode == DImode)
3355 return gen_rtx (PARALLEL, VOIDmode,
3358 gen_rtx (CLOBBER, VOIDmode,
3359 gen_reg_rtx (CCmode))));
3362 fatal_insn ("d30v_emit_comparison", rtx_test);
3366 /* Return appropriate code to move 2 words. Since DImode registers must start
3367 on even register numbers, there is no possibility of overlap. */
3370 d30v_move_2words (operands, insn)
3374 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3376 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3377 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3379 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3380 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3382 else if (GET_CODE (operands[1]) == MEM)
3383 return "ld2w %0,%M1";
3385 else if (GET_CODE (operands[1]) == CONST_INT
3386 || GET_CODE (operands[1]) == CONST_DOUBLE)
3387 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3390 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3392 if (GET_CODE (operands[1]) == REG
3393 && GPR_P (REGNO (operands[1])))
3394 return "mvtacc %0,%U1,%L1";
3396 if (GET_CODE (operands[1]) == CONST_INT
3397 && INTVAL (operands[1]) == 0)
3398 return "mvtacc %0,%.,%.";
3401 else if (GET_CODE (operands[0]) == MEM
3402 && GET_CODE (operands[1]) == REG
3403 && GPR_P (REGNO (operands[1])))
3404 return "st2w %1,%M0";
3406 fatal_insn ("Bad call to d30v_move_2words", insn);
3410 /* Emit the code to do a conditional move instruction. Return FALSE
3411 if the conditional move could not be executed. */
3414 d30v_emit_cond_move (dest, test, true_value, false_value)
3421 enum machine_mode mode = GET_MODE (dest);
3422 int two_mem_moves_p = FALSE;
3424 if (GET_CODE (dest) == MEM)
3426 if (!reg_or_0_operand (true_value, mode))
3429 if (rtx_equal_p (dest, false_value))
3430 two_mem_moves_p = TRUE;
3432 else if (!reg_or_0_operand (false_value, mode))
3436 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3437 to be slower than just doing the conditional execution. */
3439 br_reg = gen_reg_rtx (CCmode);
3440 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3441 d30v_compare_op0, d30v_compare_op1));
3443 if (!two_mem_moves_p)
3444 emit_insn (gen_rtx_SET (VOIDmode,
3446 gen_rtx_IF_THEN_ELSE (mode,
3447 gen_rtx_NE (CCmode, br_reg,
3453 /* Emit conditional stores as two separate stores. This avoids a problem
3454 where you have a conditional store, and one of the arms of the
3455 conditional store is spilled to memory. */
3456 emit_insn (gen_rtx_SET (VOIDmode,
3458 gen_rtx_IF_THEN_ELSE (mode,
3459 gen_rtx_NE (CCmode, br_reg,
3464 emit_insn (gen_rtx_SET (VOIDmode,
3466 gen_rtx_IF_THEN_ELSE (mode,
3467 gen_rtx_EQ (CCmode, br_reg,
3478 /* In rare cases, correct code generation requires extra machine dependent
3479 processing between the second jump optimization pass and delayed branch
3480 scheduling. On those machines, define this macro as a C statement to act on
3481 the code starting at INSN. */
3484 d30v_machine_dependent_reorg (insn)
3485 rtx insn ATTRIBUTE_UNUSED;
3490 /* A C statement (sans semicolon) to update the integer variable COST based on
3491 the relationship between INSN that is dependent on DEP_INSN through the
3492 dependence LINK. The default is to make no adjustment to COST. This can be
3493 used for example to specify to the scheduler that an output- or
3494 anti-dependence does not incur the same cost as a data-dependence. */
3496 /* For the d30v, try to insure that the source operands for a load/store are
3497 set 2 cycles before the memory reference. */
3500 d30v_adjust_cost (insn, link, dep_insn, cost)
3502 rtx link ATTRIBUTE_UNUSED;
3506 rtx set_dep = single_set (dep_insn);
3507 rtx set_insn = single_set (insn);
3509 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3510 && GET_CODE (SET_DEST (set_dep)) == REG)
3512 rtx reg = SET_DEST (set_dep);
3515 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3516 && reg_mentioned_p (reg, XEXP (mem, 0)))
3517 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3518 && reg_mentioned_p (reg, XEXP (mem, 0))))
3527 /* Function which returns the number of insns that can be
3528 scheduled in the same machine cycle. This must be constant
3529 over an entire compilation. The default is 1. */
3537 /* Routine to allocate, mark and free a per-function,
3538 machine specific structure. */
3541 d30v_init_machine_status (p)
3545 (machine_function *) xcalloc (1, sizeof (machine_function));
3549 d30v_mark_machine_status (p)
3550 struct function * p;
3552 if (p->machine == NULL)
3555 ggc_mark_rtx (p->machine->eh_epilogue_sp_ofs);
3559 d30v_free_machine_status (p)
3562 struct machine_function *machine = p->machine;
3564 if (machine == NULL)
3571 /* Do anything needed before RTL is emitted for each function. */
3574 d30v_init_expanders ()
3576 /* Arrange to save and restore machine status around nested functions. */
3577 init_machine_status = d30v_init_machine_status;
3578 mark_machine_status = d30v_mark_machine_status;
3579 free_machine_status = d30v_free_machine_status;
3582 /* Find the current function's return address.
3584 ??? It would be better to arrange things such that if we would ordinarily
3585 have been a leaf function and we didn't spill the hard reg that we
3586 wouldn't have to save the register in the prolog. But it's not clear
3587 how to get the right information at the right time. */
3592 return get_hard_reg_initial_val (Pmode, GPR_LINK);
3595 /* Called to register all of our global variables with the garbage
3599 d30v_add_gc_roots ()
3601 ggc_add_rtx_root (&d30v_compare_op0, 1);
3602 ggc_add_rtx_root (&d30v_compare_op1, 1);