1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
29 ;; The function cris_notice_update_cc in cris.c handles condition code
30 ;; updates for most instructions, helped by the "cc" attribute.
32 ;; There are several instructions that are orthogonal in size, and seems
33 ;; they could be matched by a single pattern without a specified size
34 ;; for the operand that is orthogonal. However, this did not work on
35 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
36 ;; constant is substituted into an operand, the actual mode must be
37 ;; deduced from the pattern. There is reasonable hope that that has been
38 ;; fixed, so FIXME: try again.
40 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
41 ;; are marked with a "!" constraint modifier to avoid being reloaded
42 ;; into. This is because gcc would otherwise prefer to use the constant
43 ;; pool and its offsettable address instead of reloading to an
44 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
45 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
47 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
48 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
49 ;; pointer). Thus the instructions that get into trouble have specific
50 ;; checks against matching frame_pointer_rtx.
51 ;; ??? But it should be re-checked for gcc > 2.7.2
52 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
54 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
55 ;; [rX=gotless_symbol].
56 ;; The movsi for a gotless symbol could be split (post reload).
59 ;; 0 PLT reference from call expansion: operand 0 is the address,
60 ;; the mode is VOIDmode. Always wrapped in CONST.
62 ;; We need an attribute to define whether an instruction can be put in
63 ;; a branch-delay slot or not, and whether it has a delay slot.
65 ;; Branches and return instructions have a delay slot, and cannot
66 ;; themselves be put in a delay slot. This has changed *for short
67 ;; branches only* between architecture variants, but the possible win
68 ;; is presumed negligible compared to the added complexity of the machine
69 ;; description: one would have to add always-correct infrastructure to
70 ;; distinguish short branches.
72 ;; Whether an instruction can be put in a delay slot depends on the
73 ;; instruction (all short instructions except jumps and branches)
74 ;; and the addressing mode (must not be prefixed or referring to pc).
75 ;; In short, any "slottable" instruction must be 16 bit and not refer
76 ;; to pc, or alter it.
78 ;; The possible values are "yes", "no" and "has_slot". Yes/no means if
79 ;; the insn is slottable or not. Has_slot means that the insn is a
80 ;; return insn or branch insn (which are not considered slottable since
81 ;; that is generally true). Having the seemingly illogical value
82 ;; "has_slot" means we do not have to add another attribute just to say
83 ;; that an insn has a delay-slot, since it also infers that it is not
84 ;; slottable. Better names for the attribute were found to be longer and
85 ;; not add readability to the machine description.
87 ;; The default that is defined here for this attribute is "no", not
88 ;; slottable, not having a delay-slot, so there's no need to worry about
89 ;; it being wrong for non-branch and return instructions.
90 ;; The default could depend on the kind of insn and the addressing
91 ;; mode, but that would need more attributes and hairier, more error
94 ;; There is an extra constraint, 'Q', which recognizes indirect reg,
95 ;; except when the reg is pc. The constraints 'Q' and '>' together match
96 ;; all possible memory operands that are slottable.
97 ;; For other operands, you need to check if it has a valid "slottable"
98 ;; quick-immediate operand, where the particular signedness-variation
99 ;; may match the constraints 'I' or 'J'.), and include it in the
100 ;; constraint pattern for the slottable pattern. An alternative using
101 ;; only "r" constraints is most often slottable.
103 (define_attr "slottable" "no,yes,has_slot" (const_string "no"))
105 ;; We also need attributes to sanely determine the condition code
106 ;; state. See cris_notice_update_cc for how this is used.
108 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
110 ;; A branch or return has one delay-slot. The instruction in the
111 ;; delay-slot is always executed, independent of whether the branch is
112 ;; taken or not. Note that besides setting "slottable" to "has_slot",
113 ;; there also has to be a "%#" at the end of a "delayed" instruction
114 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
115 ;; catch it and print a "nop" if necessary. This method was stolen from
118 (define_delay (eq_attr "slottable" "has_slot")
119 [(eq_attr "slottable" "yes") (nil) (nil)])
125 ;; Allow register and offsettable mem operands only; post-increment is
126 ;; not worth the trouble.
130 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
132 "test.d %M0\;ax\;test.d %H0")
134 ;; No test insns with side-effect on the mem addressing.
136 ;; See note on cmp-insns with side-effects (or lack of them)
138 ;; Normal named test patterns from SI on.
139 ;; FIXME: Seems they should change to be in order smallest..largest.
143 (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))]
146 [(set_attr "slottable" "yes,yes,no")])
150 (match_operand:HI 0 "nonimmediate_operand" "r,Q>,m"))]
153 [(set_attr "slottable" "yes,yes,no")])
157 (match_operand:QI 0 "nonimmediate_operand" "r,Q>,m"))]
160 [(set_attr "slottable" "yes,yes,no")])
162 ;; It seems that the position of the sign-bit and the fact that 0.0 is
163 ;; all 0-bits would make "tstsf" a straight-forward implementation;
164 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
167 ;; FIXME: Do that some time; check next_cc0_user to determine if
168 ;; zero or negative is tested for.
172 ;; We could optimize the sizes of the immediate operands for various
173 ;; cases, but that is not worth it because of the very little usage of
174 ;; DImode for anything else but a structure/block-mode. Just do the
175 ;; obvious stuff for the straight-forward constraint letters.
179 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
180 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
183 cmpq %1,%M0\;ax\;cmpq 0,%H0
184 cmpq %1,%M0\;ax\;cmpq -1,%H0
185 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
186 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
187 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
188 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
189 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
191 ;; Note that compare insns with side effect addressing mode (e.g.):
193 ;; cmp.S [rx=ry+i],rz;
194 ;; cmp.S [%3=%1+%2],%0
196 ;; are *not* usable for gcc since the reloader *does not accept*
197 ;; cc0-changing insns with side-effects other than setting the condition
198 ;; codes. The reason is that the reload stage *may* cause another insn to
199 ;; be output after the main instruction, in turn invalidating cc0 for the
200 ;; insn using the test. (This does not apply to the CRIS case, since a
201 ;; reload for output -- move to memory -- does not change the condition
202 ;; code. Unfortunately we have no way to describe that at the moment. I
203 ;; think code would improve being in the order of one percent faster.
205 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
206 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
207 ;; constants, but sometimes gcc will find its way to use it for other
208 ;; (memory) operands. Avoid side-effect patterns, though (see above).
210 ;; FIXME: These could have an anonymous mode for operand 1.
214 (define_insn "*cmp_extsi"
217 (match_operand:SI 0 "register_operand" "r,r")
218 (match_operator:SI 2 "cris_extend_operator"
219 [(match_operand:QI 1 "memory_operand" "Q>,m")])))]
222 [(set_attr "slottable" "yes,no")])
225 (define_insn "*cmp_exthi"
228 (match_operand:SI 0 "register_operand" "r,r")
229 (match_operator:SI 2 "cris_extend_operator"
230 [(match_operand:HI 1 "memory_operand" "Q>,m")])))]
233 [(set_attr "slottable" "yes,no")])
235 ;; Swap operands; it seems the canonical look (if any) is not enforced.
237 ;; FIXME: Investigate that.
238 ;; FIXME: These could have an anonymous mode for operand 1.
242 (define_insn "*cmp_swapextqi"
245 (match_operator:SI 2 "cris_extend_operator"
246 [(match_operand:QI 0 "memory_operand" "Q>,m")])
247 (match_operand:SI 1 "register_operand" "r,r")))]
249 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
250 ; swapped operands to compares.
251 [(set_attr "slottable" "yes,no")])
255 (define_insn "*cmp_swapexthi"
258 (match_operator:SI 2 "cris_extend_operator"
259 [(match_operand:HI 0 "memory_operand" "Q>,m")])
260 (match_operand:SI 1 "register_operand" "r,r")))]
262 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
263 ; swapped operands to compares.
264 [(set_attr "slottable" "yes,no")])
266 ;; The "normal" compare patterns, from SI on.
271 (match_operand:SI 0 "nonimmediate_operand" "r,r,r,r,Q>,Q>,r,r,m,m")
272 (match_operand:SI 1 "general_operand" "I,r,Q>,M,M,r,P,g,M,r")))]
285 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])
289 (compare (match_operand:HI 0 "nonimmediate_operand" "r,r,Q>,Q>,r,m,m")
290 (match_operand:HI 1 "general_operand" "r,Q>,M,r,g,M,r")))]
300 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
305 (match_operand:QI 0 "nonimmediate_operand" "r,r,r,Q>,Q>,r,m,m")
306 (match_operand:QI 1 "general_operand" "r,Q>,M,M,r,g,M,r")))]
317 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
319 ;; Pattern matching the BTST insn.
320 ;; It is useful for "if (i & val)" constructs, where val is an exact
321 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
322 ;; of zeros starting at bit 0).
324 ;; SImode. This mode is the only one needed, since gcc automatically
325 ;; extends subregs for lower-size modes. FIXME: Add testcase.
329 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
330 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
331 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
332 ;; Either it is a single bit, or consecutive ones starting at 0.
333 "GET_CODE (operands[1]) == CONST_INT
334 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
335 && (REG_S_P (operands[0])
336 || (operands[1] == const1_rtx
337 && REG_S_P (operands[2])
338 && GET_CODE (operands[0]) == CONST_INT
339 && exact_log2 (INTVAL (operands[0])) >= 0))"
341 ;; The last "&&" condition above should be caught by some kind of
342 ;; canonicalization in gcc, but we can easily help with it here.
343 ;; It results from expressions of the type
344 ;; "power_of_2_value & (1 << y)".
346 ;; Since there may be codes with tests in on bits (in constant position)
347 ;; beyond the size of a word, handle that by assuming those bits are 0.
348 ;; GCC should handle that, but it's a matter of easily-added belts while
349 ;; having suspenders.
359 [(set_attr "slottable" "yes")])
363 ;; The whole mandatory movdi family is here; expander, "anonymous"
364 ;; recognizer and splitter. We're forced to have a movdi pattern,
365 ;; although GCC should be able to split it up itself. Normally it can,
366 ;; but if other insns have DI operands (as is the case here), reload
367 ;; must be able to generate or match a movdi. many testcases fail at
368 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
369 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
370 ;; However, a patch from Richard Kenner (similar to the cause of
371 ;; discussion at the URL above), indicates otherwise. See
372 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
373 ;; The truth has IMO is not been decided yet, so check from time to
374 ;; time by disabling the movdi patterns.
376 (define_expand "movdi"
377 [(set (match_operand:DI 0 "nonimmediate_operand" "")
378 (match_operand:DI 1 "general_operand" ""))]
382 if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
383 operands[1] = copy_to_mode_reg (DImode, operands[1]);
385 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
386 prefer to split up constants early, like this. The testcase in
387 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
388 resulting subreg sets when using the construct from mcore (as of FSF
389 CVS, version -r 1.5), and it believes that the high part (the last one
390 emitted) is the final value. This construct from romp seems more
391 robust, especially considering the head comments from
392 emit_no_conflict_block. */
393 if ((GET_CODE (operands[1]) == CONST_INT
394 || GET_CODE (operands[1]) == CONST_DOUBLE)
395 && ! reload_completed
396 && ! reload_in_progress)
399 rtx op0 = operands[0];
400 rtx op1 = operands[1];
403 emit_move_insn (operand_subword (op0, 0, 1, DImode),
404 operand_subword (op1, 0, 1, DImode));
405 emit_move_insn (operand_subword (op0, 1, 1, DImode),
406 operand_subword (op1, 1, 1, DImode));
407 insns = get_insns ();
410 emit_no_conflict_block (insns, op0, op1, 0, op1);
415 (define_insn "*movdi_insn"
416 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
417 (match_operand:DI 1 "general_operand" "r,g,rM"))]
418 "register_operand (operands[0], DImode)
419 || register_operand (operands[1], DImode)
420 || operands[1] == const0_rtx"
424 [(set (match_operand:DI 0 "nonimmediate_operand" "")
425 (match_operand:DI 1 "general_operand" ""))]
428 "operands[2] = cris_split_movdx (operands);")
430 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
431 ;; and move.S1 [rx=ry+i],rz
432 ;; Then movs.S1 and movu.S1 for both modes.
434 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
435 ;; FIXME: These could have anonymous mode for operand 0.
439 (define_insn "*mov_sideqi_biap"
440 [(set (match_operand:QI 0 "register_operand" "=r,r")
442 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
443 (match_operand:SI 2 "const_int_operand" "n,n"))
444 (match_operand:SI 3 "register_operand" "r,r"))))
445 (set (match_operand:SI 4 "register_operand" "=*3,r")
446 (plus:SI (mult:SI (match_dup 1)
449 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
452 move.%s0 [%4=%3+%1%T2],%0")
456 (define_insn "*mov_sidehi_biap"
457 [(set (match_operand:HI 0 "register_operand" "=r,r")
459 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
460 (match_operand:SI 2 "const_int_operand" "n,n"))
461 (match_operand:SI 3 "register_operand" "r,r"))))
462 (set (match_operand:SI 4 "register_operand" "=*3,r")
463 (plus:SI (mult:SI (match_dup 1)
466 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
469 move.%s0 [%4=%3+%1%T2],%0")
473 (define_insn "*mov_sidesisf_biap"
474 [(set (match_operand 0 "register_operand" "=r,r")
476 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
477 (match_operand:SI 2 "const_int_operand" "n,n"))
478 (match_operand:SI 3 "register_operand" "r,r"))))
479 (set (match_operand:SI 4 "register_operand" "=*3,r")
480 (plus:SI (mult:SI (match_dup 1)
483 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
484 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
487 move.%s0 [%4=%3+%1%T2],%0")
489 ;; move.S1 [rx=ry+i],rz
490 ;; avoiding move.S1 [ry=ry+i],rz
491 ;; and move.S1 [rz=ry+i],rz
492 ;; Note that "i" is allowed to be a register.
493 ;; FIXME: These could have anonymous mode for operand 0.
497 (define_insn "*mov_sideqi"
498 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
500 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
501 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
502 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
503 (plus:SI (match_dup 1)
505 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
508 if (which_alternative == 0
509 && (GET_CODE (operands[2]) != CONST_INT
510 || INTVAL (operands[2]) > 127
511 || INTVAL (operands[2]) < -128
512 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
513 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
515 return \"move.%s0 [%3=%1%S2],%0\";
520 (define_insn "*mov_sidehi"
521 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
523 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
524 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
525 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
526 (plus:SI (match_dup 1)
528 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
531 if (which_alternative == 0
532 && (GET_CODE (operands[2]) != CONST_INT
533 || INTVAL (operands[2]) > 127
534 || INTVAL (operands[2]) < -128
535 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
536 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
538 return \"move.%s0 [%3=%1%S2],%0\";
543 (define_insn "*mov_sidesisf"
544 [(set (match_operand 0 "register_operand" "=r,r,r")
546 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
547 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
548 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
549 (plus:SI (match_dup 1)
551 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
552 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
555 if (which_alternative == 0
556 && (GET_CODE (operands[2]) != CONST_INT
557 || INTVAL (operands[2]) > 127
558 || INTVAL (operands[2]) < -128
559 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
560 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
562 return \"move.%s0 [%3=%1%S2],%0\";
565 ;; Other way around; move to memory.
567 ;; Note that the condition (which for side-effect patterns is usually a
568 ;; call to cris_side_effect_mode_ok), isn't consulted for register
569 ;; allocation preferences -- constraints is the method for that. The
570 ;; drawback is that we can't exclude register allocation to cause
571 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
572 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
573 ;; Instead of that, we recognize and split the cases where dangerous
574 ;; register combinations are spotted: where a register is set in the
575 ;; side-effect, and used in the main insn. We don't handle the case where
576 ;; the set in the main insn overlaps the set in the side-effect; that case
577 ;; must be handled in gcc. We handle just the case where the set in the
578 ;; side-effect overlaps the input operand of the main insn (i.e. just
582 ;; move.s rz,[ry=rx+rw.S]
583 ;; FIXME: These could have anonymous mode for operand 3.
587 (define_insn "*mov_sideqi_biap_mem"
588 [(set (mem:QI (plus:SI
589 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
590 (match_operand:SI 1 "const_int_operand" "n,n,n"))
591 (match_operand:SI 2 "register_operand" "r,r,r")))
592 (match_operand:QI 3 "register_operand" "r,r,r"))
593 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
594 (plus:SI (mult:SI (match_dup 0)
597 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
601 move.%s3 %3,[%4=%2+%0%T1]")
605 (define_insn "*mov_sidehi_biap_mem"
606 [(set (mem:HI (plus:SI
607 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
608 (match_operand:SI 1 "const_int_operand" "n,n,n"))
609 (match_operand:SI 2 "register_operand" "r,r,r")))
610 (match_operand:HI 3 "register_operand" "r,r,r"))
611 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
612 (plus:SI (mult:SI (match_dup 0)
615 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
619 move.%s3 %3,[%4=%2+%0%T1]")
623 (define_insn "*mov_sidesisf_biap_mem"
625 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
626 (match_operand:SI 1 "const_int_operand" "n,n,n"))
627 (match_operand:SI 2 "register_operand" "r,r,r")))
628 (match_operand 3 "register_operand" "r,r,r"))
629 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
630 (plus:SI (mult:SI (match_dup 0)
633 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
634 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
638 move.%s3 %3,[%4=%2+%0%T1]")
640 ;; Split for the case above where we're out of luck with register
641 ;; allocation (again, the condition isn't checked for that), and we end up
642 ;; with the set in the side-effect getting the same register as the input
647 [(set (match_operator
650 (mult:SI (match_operand:SI 0 "register_operand" "")
651 (match_operand:SI 1 "const_int_operand" ""))
652 (match_operand:SI 2 "register_operand" ""))])
653 (match_operand 3 "register_operand" ""))
654 (set (match_operand:SI 4 "register_operand" "")
655 (plus:SI (mult:SI (match_dup 0)
658 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
659 [(set (match_dup 5) (match_dup 3))
660 (set (match_dup 4) (match_dup 2))
662 (plus:SI (mult:SI (match_dup 0)
666 = replace_equiv_address (operands[6],
667 gen_rtx_PLUS (SImode,
668 gen_rtx_MULT (SImode,
673 ;; move.s rx,[ry=rz+i]
674 ;; FIXME: These could have anonymous mode for operand 2.
678 (define_insn "*mov_sideqi_mem"
680 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
681 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
682 (match_operand:QI 2 "register_operand" "r,r,r,r"))
683 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
684 (plus:SI (match_dup 0)
686 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
689 if (which_alternative == 0
690 && (GET_CODE (operands[1]) != CONST_INT
691 || INTVAL (operands[1]) > 127
692 || INTVAL (operands[1]) < -128
693 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
694 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
696 if (which_alternative == 1)
698 return \"move.%s2 %2,[%3=%0%S1]\";
703 (define_insn "*mov_sidehi_mem"
705 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
706 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
707 (match_operand:HI 2 "register_operand" "r,r,r,r"))
708 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
709 (plus:SI (match_dup 0)
711 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
714 if (which_alternative == 0
715 && (GET_CODE (operands[1]) != CONST_INT
716 || INTVAL (operands[1]) > 127
717 || INTVAL (operands[1]) < -128
718 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
719 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
721 if (which_alternative == 1)
723 return \"move.%s2 %2,[%3=%0%S1]\";
728 (define_insn "*mov_sidesisf_mem"
730 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
731 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
732 (match_operand 2 "register_operand" "r,r,r,r"))
733 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
734 (plus:SI (match_dup 0)
736 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
737 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
740 if (which_alternative == 0
741 && (GET_CODE (operands[1]) != CONST_INT
742 || INTVAL (operands[1]) > 127
743 || INTVAL (operands[1]) < -128
744 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
745 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
747 if (which_alternative == 1)
749 return \"move.%s2 %2,[%3=%0%S1]\";
752 ;; Like the biap case, a split where the set in the side-effect gets the
753 ;; same register as the input register to the main insn, since the
754 ;; condition isn't checked at register allocation.
758 [(set (match_operator
761 (match_operand:SI 0 "cris_bdap_operand" "")
762 (match_operand:SI 1 "cris_bdap_operand" ""))])
763 (match_operand 2 "register_operand" ""))
764 (set (match_operand:SI 3 "register_operand" "")
765 (plus:SI (match_dup 0) (match_dup 1)))])]
766 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
767 [(set (match_dup 4) (match_dup 2))
768 (set (match_dup 3) (match_dup 0))
769 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
772 ;; Clear memory side-effect patterns. It is hard to get to the mode if
773 ;; the MEM was anonymous, so there will be one for each mode.
775 ;; clear.d [ry=rx+rw.s2]
777 (define_insn "*clear_sidesi_biap"
778 [(set (mem:SI (plus:SI
779 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
780 (match_operand:SI 1 "const_int_operand" "n,n"))
781 (match_operand:SI 2 "register_operand" "r,r")))
783 (set (match_operand:SI 3 "register_operand" "=*2,r")
784 (plus:SI (mult:SI (match_dup 0)
787 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
790 clear.d [%3=%2+%0%T1]")
794 (define_insn "*clear_sidesi"
796 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
797 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
799 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
800 (plus:SI (match_dup 0)
802 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
805 if (which_alternative == 0
806 && (GET_CODE (operands[1]) != CONST_INT
807 || INTVAL (operands[1]) > 127
808 || INTVAL (operands[1]) < -128
809 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
810 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
812 return \"clear.d [%2=%0%S1]\";
815 ;; clear.w [ry=rx+rw.s2]
817 (define_insn "*clear_sidehi_biap"
818 [(set (mem:HI (plus:SI
819 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
820 (match_operand:SI 1 "const_int_operand" "n,n"))
821 (match_operand:SI 2 "register_operand" "r,r")))
823 (set (match_operand:SI 3 "register_operand" "=*2,r")
824 (plus:SI (mult:SI (match_dup 0)
827 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
830 clear.w [%3=%2+%0%T1]")
834 (define_insn "*clear_sidehi"
836 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
837 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
839 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
840 (plus:SI (match_dup 0)
842 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
845 if (which_alternative == 0
846 && (GET_CODE (operands[1]) != CONST_INT
847 || INTVAL (operands[1]) > 127
848 || INTVAL (operands[1]) < -128
849 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
850 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
852 return \"clear.w [%2=%0%S1]\";
855 ;; clear.b [ry=rx+rw.s2]
857 (define_insn "*clear_sideqi_biap"
858 [(set (mem:QI (plus:SI
859 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
860 (match_operand:SI 1 "const_int_operand" "n,n"))
861 (match_operand:SI 2 "register_operand" "r,r")))
863 (set (match_operand:SI 3 "register_operand" "=*2,r")
864 (plus:SI (mult:SI (match_dup 0)
867 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
870 clear.b [%3=%2+%0%T1]")
874 (define_insn "*clear_sideqi"
876 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
877 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
879 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
880 (plus:SI (match_dup 0)
882 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
885 if (which_alternative == 0
886 && (GET_CODE (operands[1]) != CONST_INT
887 || INTVAL (operands[1]) > 127
888 || INTVAL (operands[1]) < -128
889 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
890 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
892 return \"clear.b [%2=%0%S1]\";
895 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
896 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
897 ;; A cmpdi RTX needs reloading (global):
898 ;; (insn 185 326 186 (set (cc0)
899 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
900 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
902 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
903 ;; out of the instruction (into a register), since one of the operands
904 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
905 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
906 ;; wrt. overlap). The bad things happen with the synthesis in
907 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
908 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
909 ;; 22 is recognized to have an equivalent in memory which is substituted
910 ;; straight in, and we end up with an unrecognizable insn:
911 ;; (insn 325 324 326 (set (reg:SI 9 r9)
912 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
913 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
915 ;; which is the first part of the reloaded synthesized "movdi".
916 ;; The right thing would be to add equivalent replacement locations for
917 ;; insn with pseudos that need more reloading. The question is where.
919 ;; Normal move patterns from SI on.
921 (define_expand "movsi"
923 (match_operand:SI 0 "nonimmediate_operand" "")
924 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
928 /* If the output goes to a MEM, make sure we have zero or a register as
930 if (GET_CODE (operands[0]) == MEM
931 && ! REG_S_P (operands[1])
932 && operands[1] != const0_rtx
934 operands[1] = force_reg (SImode, operands[1]);
936 /* If we're generating PIC and have an incoming symbol, validize it to a
937 general operand or something that will match a special pattern.
939 FIXME: Do we *have* to recognize anything that would normally be a
940 valid symbol? Can we exclude global PIC addresses with an added
943 && CONSTANT_ADDRESS_P (operands[1])
944 && cris_symbol (operands[1]))
946 /* We must have a register as destination for what we're about to
947 do, and for the patterns we generate. */
948 if (! REG_S_P (operands[0]))
952 operands[1] = force_reg (SImode, operands[1]);
956 /* Mark a needed PIC setup for a LABEL_REF:s coming in here:
957 they are so rare not-being-branch-targets that we don't mark
958 a function as needing PIC setup just because we have
959 inspected LABEL_REF:s as operands. It is only in
960 __builtin_setjmp and such that we can get a LABEL_REF
961 assigned to a register. */
962 if (GET_CODE (operands[1]) == LABEL_REF)
963 current_function_uses_pic_offset_table = 1;
965 /* We don't have to do anything for global PIC operands; they
966 look just like ``[rPIC+sym]''. */
967 if (! cris_got_symbol (operands[1])
968 /* We don't do anything for local PIC operands; we match
969 that with a special alternative. */
970 && ! cris_gotless_symbol (operands[1]))
972 /* We get here when we have to change something that would
973 be recognizable if it wasn't PIC. A ``sym'' is ok for
974 PIC symbols both with and without a GOT entry. And ``sym
975 + offset'' is ok for local symbols, so the only thing it
976 could be, is a global symbol with an offset. Check and
978 rtx sym = get_related_value (operands[1]);
979 HOST_WIDE_INT offs = get_integer_term (operands[1]);
981 if (sym == NULL_RTX || offs == 0)
983 emit_move_insn (operands[0], sym);
984 if (expand_binop (SImode, add_optab, operands[0],
985 GEN_INT (offs), operands[0], 0,
986 OPTAB_LIB_WIDEN) != operands[0])
994 (define_insn "*movsi_internal"
996 (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,g,r,r,r,g")
998 ;; FIXME: We want to put S last, but apparently g matches S.
999 ;; It's a bug: an S is not a general_operand and shouldn't match g.
1000 "cris_general_operand_or_gotless_symbol" "r,Q>,M,M,I,r,M,n,!S,g,r"))]
1004 /* Better to have c-switch here; it is worth it to optimize the size of
1005 move insns. The alternative would be to try to find more constraint
1006 letters. FIXME: Check again. It seems this could shrink a bit. */
1007 switch (which_alternative)
1014 return \"move.d %1,%0\";
1019 return \"clear.d %0\";
1021 /* Constants -32..31 except 0. */
1023 return \"moveq %1,%0\";
1025 /* We can win a little on constants -32768..-33, 32..65535. */
1027 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1029 if (INTVAL (operands[1]) < 256)
1030 return \"movu.b %1,%0\";
1031 return \"movu.w %1,%0\";
1033 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1035 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1036 return \"movs.b %1,%0\";
1037 return \"movs.w %1,%0\";
1039 return \"move.d %1,%0\";
1042 /* FIXME: Try and split this into pieces GCC makes better code of,
1043 than this multi-insn pattern. Synopsis: wrap the GOT-relative
1044 symbol into an unspec, and when PIC, recognize the unspec
1045 everywhere a symbol is normally recognized. (The PIC register
1046 should be recognized by GCC as pic_offset_table_rtx when needed
1047 and similar for PC.) Each component can then be optimized with
1048 the rest of the code; it should be possible to have a constant
1049 term added on an unspec. Don't forget to add a REG_EQUAL (or
1050 is it REG_EQUIV) note to the destination. It might not be
1053 Note that the 'v' modifier makes PLT references be output as
1054 sym:PLT rather than [rPIC+sym:GOTPLT]. */
1055 return \"move.d %v1,%0\;add.d %P1,%0\";
1058 return \"BOGUS: %1 to %0\";
1061 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no")])
1063 ;; Extend operations with side-effect from mem to register, using
1064 ;; MOVS/MOVU. These are from mem to register only.
1070 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1071 ;; HImode by itself? Perhaps use only anonymous modes?
1073 (define_insn "*ext_sideqihi_biap"
1074 [(set (match_operand:HI 0 "register_operand" "=r,r")
1076 5 "cris_extend_operator"
1078 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1079 (match_operand:SI 2 "const_int_operand" "n,n"))
1080 (match_operand:SI 3 "register_operand" "r,r")))]))
1081 (set (match_operand:SI 4 "register_operand" "=*3,r")
1082 (plus:SI (mult:SI (match_dup 1)
1085 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1088 mov%e5.%m5 [%4=%3+%1%T2],%0")
1092 (define_insn "*ext_sideqisi_biap"
1093 [(set (match_operand:SI 0 "register_operand" "=r,r")
1095 5 "cris_extend_operator"
1097 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1098 (match_operand:SI 2 "const_int_operand" "n,n"))
1099 (match_operand:SI 3 "register_operand" "r,r")))]))
1100 (set (match_operand:SI 4 "register_operand" "=*3,r")
1101 (plus:SI (mult:SI (match_dup 1)
1104 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1107 mov%e5.%m5 [%4=%3+%1%T2],%0")
1111 (define_insn "*ext_sidehisi_biap"
1112 [(set (match_operand:SI 0 "register_operand" "=r,r")
1114 5 "cris_extend_operator"
1116 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1117 (match_operand:SI 2 "const_int_operand" "n,n"))
1118 (match_operand:SI 3 "register_operand" "r,r")))]))
1119 (set (match_operand:SI 4 "register_operand" "=*3,r")
1120 (plus:SI (mult:SI (match_dup 1)
1123 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1126 mov%e5.%m5 [%4=%3+%1%T2],%0")
1128 ;; Same but [rx=ry+i]
1132 (define_insn "*ext_sideqihi"
1133 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1135 4 "cris_extend_operator"
1137 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1138 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1139 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1140 (plus:SI (match_dup 1)
1142 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1145 if (which_alternative == 0
1146 && (GET_CODE (operands[2]) != CONST_INT
1147 || INTVAL (operands[2]) > 127
1148 || INTVAL (operands[2]) < -128
1149 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1150 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1152 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1157 (define_insn "*ext_sideqisi"
1158 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1160 4 "cris_extend_operator"
1162 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1163 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1164 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1165 (plus:SI (match_dup 1)
1167 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1170 if (which_alternative == 0
1171 && (GET_CODE (operands[2]) != CONST_INT
1172 || INTVAL (operands[2]) > 127
1173 || INTVAL (operands[2]) < -128
1174 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1175 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1177 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1182 (define_insn "*ext_sidehisi"
1183 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1185 4 "cris_extend_operator"
1187 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1188 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1189 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1190 (plus:SI (match_dup 1)
1192 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1195 if (which_alternative == 0
1196 && (GET_CODE (operands[2]) != CONST_INT
1197 || INTVAL (operands[2]) > 127
1198 || INTVAL (operands[2]) < -128
1199 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1200 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1202 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1205 ;; FIXME: See movsi.
1207 (define_insn "movhi"
1209 (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,r,r,r,g,g,r")
1210 (match_operand:HI 1 "general_operand" "r,Q>,M,M,I,r,L,O,n,M,r,g"))]
1214 switch (which_alternative)
1221 return \"move.w %1,%0\";
1225 return \"clear.w %0\";
1227 return \"moveq %1,%0\";
1230 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1232 if (INTVAL (operands[1]) > 0)
1233 return \"movu.b %1,%0\";
1234 return \"movs.b %1,%0\";
1236 return \"move.w %1,%0\";
1238 return \"movEq %b1,%0\";
1240 return \"BOGUS: %1 to %0\";
1243 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no")
1245 (if_then_else (eq_attr "alternative" "7")
1246 (const_string "clobber")
1247 (const_string "normal")))])
1249 (define_insn "movstricthi"
1252 (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g"))
1253 (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))]
1264 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1266 (define_insn "movqi"
1267 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r")
1268 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))]
1281 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no")
1283 (if_then_else (eq_attr "alternative" "8")
1284 (const_string "clobber")
1285 (const_string "normal")))])
1287 (define_insn "movstrictqi"
1288 [(set (strict_low_part
1289 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r"))
1290 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))]
1301 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1303 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1304 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1305 ;; all ones); the worthwhile one is "0.0".
1306 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1308 (define_insn "movsf"
1309 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r")
1310 (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))]
1321 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1324 ;; Sign- and zero-extend insns with standard names.
1325 ;; Those for integer source operand are ordered with the widest source
1330 (define_insn "extendsidi2"
1331 [(set (match_operand:DI 0 "register_operand" "=r")
1332 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1334 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1336 (define_insn "extendhidi2"
1337 [(set (match_operand:DI 0 "register_operand" "=r")
1338 (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
1340 "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0")
1342 (define_insn "extendhisi2"
1343 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1344 (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))]
1347 [(set_attr "slottable" "yes,yes,no")])
1349 (define_insn "extendqidi2"
1350 [(set (match_operand:DI 0 "register_operand" "=r")
1351 (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
1353 "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0")
1355 (define_insn "extendqisi2"
1356 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1357 (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1360 [(set_attr "slottable" "yes,yes,no")])
1362 ;; To do a byte->word extension, extend to dword, exept that the top half
1363 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1365 (define_insn "extendqihi2"
1366 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1367 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1370 [(set_attr "slottable" "yes,yes,no")])
1373 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1374 ;; specify them here.
1376 (define_insn "zero_extendhisi2"
1377 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1379 (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))]
1382 [(set_attr "slottable" "yes,yes,no")])
1384 (define_insn "zero_extendqisi2"
1385 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1387 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1390 [(set_attr "slottable" "yes,yes,no")])
1392 ;; Same comment as sign-extend QImode to HImode above applies.
1394 (define_insn "zero_extendqihi2"
1395 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1397 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1400 [(set_attr "slottable" "yes,yes,no")])
1402 ;; All kinds of arithmetic and logical instructions.
1404 ;; First, anonymous patterns to match addressing modes with
1407 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1410 ;; FIXME: These could have anonymous mode for operand 0.
1414 (define_insn "*op_sideqi_biap"
1415 [(set (match_operand:QI 0 "register_operand" "=r,r")
1417 6 "cris_orthogonal_operator"
1418 [(match_operand:QI 1 "register_operand" "0,0")
1420 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1421 (match_operand:SI 3 "const_int_operand" "n,n"))
1422 (match_operand:SI 4 "register_operand" "r,r")))]))
1423 (set (match_operand:SI 5 "register_operand" "=*4,r")
1424 (plus:SI (mult:SI (match_dup 2)
1427 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1430 %x6.%s0 [%5=%4+%2%T3],%0")
1434 (define_insn "*op_sidehi_biap"
1435 [(set (match_operand:HI 0 "register_operand" "=r,r")
1437 6 "cris_orthogonal_operator"
1438 [(match_operand:HI 1 "register_operand" "0,0")
1440 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1441 (match_operand:SI 3 "const_int_operand" "n,n"))
1442 (match_operand:SI 4 "register_operand" "r,r")))]))
1443 (set (match_operand:SI 5 "register_operand" "=*4,r")
1444 (plus:SI (mult:SI (match_dup 2)
1447 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1450 %x6.%s0 [%5=%4+%2%T3],%0")
1454 (define_insn "*op_sidesi_biap"
1455 [(set (match_operand:SI 0 "register_operand" "=r,r")
1457 6 "cris_orthogonal_operator"
1458 [(match_operand:SI 1 "register_operand" "0,0")
1460 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1461 (match_operand:SI 3 "const_int_operand" "n,n"))
1462 (match_operand:SI 4 "register_operand" "r,r")))]))
1463 (set (match_operand:SI 5 "register_operand" "=*4,r")
1464 (plus:SI (mult:SI (match_dup 2)
1467 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1470 %x6.%s0 [%5=%4+%2%T3],%0")
1472 ;; [rx=ry+i] ([%4=%2+%3])
1473 ;; FIXME: These could have anonymous mode for operand 0.
1477 (define_insn "*op_sideqi"
1478 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1480 5 "cris_orthogonal_operator"
1481 [(match_operand:QI 1 "register_operand" "0,0,0")
1483 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1484 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1485 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1486 (plus:SI (match_dup 2)
1488 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1491 if (which_alternative == 0
1492 && (GET_CODE (operands[3]) != CONST_INT
1493 || INTVAL (operands[3]) > 127
1494 || INTVAL (operands[3]) < -128
1495 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1496 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1498 return \"%x5.%s0 [%4=%2%S3],%0\";
1503 (define_insn "*op_sidehi"
1504 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1506 5 "cris_orthogonal_operator"
1507 [(match_operand:HI 1 "register_operand" "0,0,0")
1509 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1510 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1511 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1512 (plus:SI (match_dup 2)
1514 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1517 if (which_alternative == 0
1518 && (GET_CODE (operands[3]) != CONST_INT
1519 || INTVAL (operands[3]) > 127
1520 || INTVAL (operands[3]) < -128
1521 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1522 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1524 return \"%x5.%s0 [%4=%2%S3],%0\";
1529 (define_insn "*op_sidesi"
1530 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1532 5 "cris_orthogonal_operator"
1533 [(match_operand:SI 1 "register_operand" "0,0,0")
1535 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1536 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1537 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1538 (plus:SI (match_dup 2)
1540 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1543 if (which_alternative == 0
1544 && (GET_CODE (operands[3]) != CONST_INT
1545 || INTVAL (operands[3]) > 127
1546 || INTVAL (operands[3]) < -128
1547 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1548 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1550 return \"%x5.%s0 [%4=%2%S3],%0\";
1553 ;; To match all cases for commutative operations we may have to have the
1554 ;; following pattern for add, or & and. I do not know really, but it does
1555 ;; not break anything.
1557 ;; FIXME: This really ought to be checked.
1559 ;; op.S [rx=ry+I],rz;
1562 ;; FIXME: These could have anonymous mode for operand 0.
1566 (define_insn "*op_swap_sideqi_biap"
1567 [(set (match_operand:QI 0 "register_operand" "=r,r")
1569 6 "cris_commutative_orth_op"
1571 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1572 (match_operand:SI 3 "const_int_operand" "n,n"))
1573 (match_operand:SI 4 "register_operand" "r,r")))
1574 (match_operand:QI 1 "register_operand" "0,0")]))
1575 (set (match_operand:SI 5 "register_operand" "=*4,r")
1576 (plus:SI (mult:SI (match_dup 2)
1579 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1582 %x6.%s0 [%5=%4+%2%T3],%0")
1586 (define_insn "*op_swap_sidehi_biap"
1587 [(set (match_operand:HI 0 "register_operand" "=r,r")
1589 6 "cris_commutative_orth_op"
1591 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1592 (match_operand:SI 3 "const_int_operand" "n,n"))
1593 (match_operand:SI 4 "register_operand" "r,r")))
1594 (match_operand:HI 1 "register_operand" "0,0")]))
1595 (set (match_operand:SI 5 "register_operand" "=*4,r")
1596 (plus:SI (mult:SI (match_dup 2)
1599 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1602 %x6.%s0 [%5=%4+%2%T3],%0")
1606 (define_insn "*op_swap_sidesi_biap"
1607 [(set (match_operand:SI 0 "register_operand" "=r,r")
1609 6 "cris_commutative_orth_op"
1611 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1612 (match_operand:SI 3 "const_int_operand" "n,n"))
1613 (match_operand:SI 4 "register_operand" "r,r")))
1614 (match_operand:SI 1 "register_operand" "0,0")]))
1615 (set (match_operand:SI 5 "register_operand" "=*4,r")
1616 (plus:SI (mult:SI (match_dup 2)
1619 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1622 %x6.%s0 [%5=%4+%2%T3],%0")
1624 ;; [rx=ry+i] ([%4=%2+%3])
1625 ;; FIXME: These could have anonymous mode for operand 0.
1629 (define_insn "*op_swap_sideqi"
1630 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1632 5 "cris_commutative_orth_op"
1634 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1635 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1636 (match_operand:QI 1 "register_operand" "0,0,0")]))
1637 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1638 (plus:SI (match_dup 2)
1640 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1643 if (which_alternative == 0
1644 && (GET_CODE (operands[3]) != CONST_INT
1645 || INTVAL (operands[3]) > 127
1646 || INTVAL (operands[3]) < -128
1647 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1648 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1650 return \"%x5.%s0 [%4=%2%S3],%0\";
1655 (define_insn "*op_swap_sidehi"
1656 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1658 5 "cris_commutative_orth_op"
1660 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1661 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1662 (match_operand:HI 1 "register_operand" "0,0,0")]))
1663 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1664 (plus:SI (match_dup 2)
1666 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1669 if (which_alternative == 0
1670 && (GET_CODE (operands[3]) != CONST_INT
1671 || INTVAL (operands[3]) > 127
1672 || INTVAL (operands[3]) < -128
1673 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1674 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1676 return \"%x5.%s0 [%4=%2%S3],%0\";
1681 (define_insn "*op_swap_sidesi"
1682 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1684 5 "cris_commutative_orth_op"
1686 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1687 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1688 (match_operand:SI 1 "register_operand" "0,0,0")]))
1689 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1690 (plus:SI (match_dup 2)
1692 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1695 if (which_alternative == 0
1696 && (GET_CODE (operands[3]) != CONST_INT
1697 || INTVAL (operands[3]) > 127
1698 || INTVAL (operands[3]) < -128
1699 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1700 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1702 return \"%x5.%s0 [%4=%2%S3],%0\";
1705 ;; Add operations, standard names.
1707 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1708 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1710 (define_insn "adddi3"
1711 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1712 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1713 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1716 addq %2,%M0\;ax\;addq 0,%H0
1717 subq %n2,%M0\;ax\;subq 0,%H0
1718 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1719 add.d %M2,%M0\;ax\;add.d %H2,%H0
1720 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1722 (define_insn "addsi3"
1723 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1725 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r")
1726 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
1728 ;; The last constraint is due to that after reload, the '%' is not
1729 ;; honored, and canonicalization doesn't care about keeping the same
1730 ;; register as in destination. This will happen after insn splitting.
1731 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1736 switch (which_alternative)
1740 return \"add.d %2,%0\";
1742 return \"addq %2,%0\";
1744 return \"subq %n2,%0\";
1746 /* 'Known value', but not in -63..63.
1747 Check if addu/subu may be used. */
1748 if (INTVAL (operands[2]) > 0)
1750 if (INTVAL (operands[2]) < 256)
1751 return \"addu.b %2,%0\";
1752 if (INTVAL (operands[2]) < 65536)
1753 return \"addu.w %2,%0\";
1757 if (INTVAL (operands[2]) >= -255)
1758 return \"subu.b %n2,%0\";
1759 if (INTVAL (operands[2]) >= -65535)
1760 return \"subu.w %n2,%0\";
1762 return \"add.d %2,%0\";
1764 return \"add.d %2,%1,%0\";
1766 return \"add.d %2,%0\";
1768 return \"add.d %1,%0\";
1770 return \"BOGUS addsi %2+%1 to %0\";
1773 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
1775 (define_insn "addhi3"
1776 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1777 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
1778 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1787 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1788 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1790 (define_insn "addqi3"
1791 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r")
1792 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r")
1793 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1803 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1804 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1808 ;; Note that because of insn canonicalization these will *seldom* but
1809 ;; rarely be used with a known constant as an operand.
1811 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1812 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1814 (define_insn "subdi3"
1815 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1816 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1817 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1820 subq %2,%M0\;ax\;subq 0,%H0
1821 addq %n2,%M0\;ax\;addq 0,%H0
1822 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1823 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1824 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1826 (define_insn "subsi3"
1827 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1829 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r")
1830 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1833 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1834 ;; But then again, %2 should not be negative.
1845 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1847 (define_insn "subhi3"
1848 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1849 (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r")
1850 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1859 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1860 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1862 (define_insn "subqi3"
1863 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1864 (minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r")
1865 (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1874 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1875 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1877 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
1878 ;; Although these perform sign/zero-extension to SImode, they are
1879 ;; equally applicable for the HImode case.
1880 ;; FIXME: Check; GCC should handle the widening.
1881 ;; Note that these must be located after the normal add/sub patterns,
1882 ;; so not to get constants into any less specific operands.
1884 ;; Extend with add/sub and side-effect.
1886 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
1888 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
1889 ;; FIXME: These could have anonymous mode for operand 0.
1892 ;; FIXME: GCC should widen.
1894 (define_insn "*extopqihi_side_biap"
1895 [(set (match_operand:HI 0 "register_operand" "=r,r")
1897 6 "cris_additive_operand_extend_operator"
1898 [(match_operand:HI 1 "register_operand" "0,0")
1900 7 "cris_extend_operator"
1902 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1903 (match_operand:SI 3 "const_int_operand" "n,n"))
1904 (match_operand:SI 4 "register_operand" "r,r")))])]))
1905 (set (match_operand:SI 5 "register_operand" "=*4,r")
1906 (plus:SI (mult:SI (match_dup 2)
1909 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1912 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1916 (define_insn "*extopqisi_side_biap"
1917 [(set (match_operand:SI 0 "register_operand" "=r,r")
1919 6 "cris_operand_extend_operator"
1920 [(match_operand:SI 1 "register_operand" "0,0")
1922 7 "cris_extend_operator"
1924 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1925 (match_operand:SI 3 "const_int_operand" "n,n"))
1926 (match_operand:SI 4 "register_operand" "r,r")))])]))
1927 (set (match_operand:SI 5 "register_operand" "=*4,r")
1928 (plus:SI (mult:SI (match_dup 2)
1931 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1932 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1935 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1939 (define_insn "*extophisi_side_biap"
1940 [(set (match_operand:SI 0 "register_operand" "=r,r")
1942 6 "cris_operand_extend_operator"
1943 [(match_operand:SI 1 "register_operand" "0,0")
1945 7 "cris_extend_operator"
1947 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1948 (match_operand:SI 3 "const_int_operand" "n,n"))
1949 (match_operand:SI 4 "register_operand" "r,r")))])]))
1950 (set (match_operand:SI 5 "register_operand" "=*4,r")
1951 (plus:SI (mult:SI (match_dup 2)
1954 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1955 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1958 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1962 ;; FIXME: These could have anonymous mode for operand 0.
1966 (define_insn "*extopqihi_side"
1967 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1969 5 "cris_additive_operand_extend_operator"
1970 [(match_operand:HI 1 "register_operand" "0,0,0")
1972 6 "cris_extend_operator"
1974 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1975 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
1977 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1978 (plus:SI (match_dup 2)
1980 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1983 if (which_alternative == 0
1984 && (GET_CODE (operands[3]) != CONST_INT
1985 || INTVAL (operands[3]) > 127
1986 || INTVAL (operands[3]) < -128
1987 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1988 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1990 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
1995 (define_insn "*extopqisi_side"
1996 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1998 5 "cris_operand_extend_operator"
1999 [(match_operand:SI 1 "register_operand" "0,0,0")
2001 6 "cris_extend_operator"
2003 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2004 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
2006 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2007 (plus:SI (match_dup 2)
2010 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2011 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2014 if (which_alternative == 0
2015 && (GET_CODE (operands[3]) != CONST_INT
2016 || INTVAL (operands[3]) > 127
2017 || INTVAL (operands[3]) < -128
2018 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2019 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2021 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2026 (define_insn "*extophisi_side"
2027 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2029 5 "cris_operand_extend_operator"
2030 [(match_operand:SI 1 "register_operand" "0,0,0")
2032 6 "cris_extend_operator"
2034 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2035 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
2037 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2038 (plus:SI (match_dup 2)
2040 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2041 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2044 if (which_alternative == 0
2045 && (GET_CODE (operands[3]) != CONST_INT
2046 || INTVAL (operands[3]) > 127
2047 || INTVAL (operands[3]) < -128
2048 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2049 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2051 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2055 ;; As with op.S we may have to add special pattern to match commuted
2056 ;; operands to adds/addu and bound
2058 ;; adds/addu/bound [rx=ry+rz.S]
2061 ;; FIXME: GCC should widen.
2063 (define_insn "*extopqihi_swap_side_biap"
2064 [(set (match_operand:HI 0 "register_operand" "=r,r")
2067 6 "cris_extend_operator"
2069 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2070 (match_operand:SI 3 "const_int_operand" "n,n"))
2071 (match_operand:SI 4 "register_operand" "r,r")))])
2072 (match_operand:HI 1 "register_operand" "0,0")))
2073 (set (match_operand:SI 5 "register_operand" "=*4,r")
2074 (plus:SI (mult:SI (match_dup 2)
2077 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2080 add%e6.b [%5=%4+%2%T3],%0")
2084 (define_insn "*extopqisi_swap_side_biap"
2085 [(set (match_operand:SI 0 "register_operand" "=r,r")
2087 7 "cris_plus_or_bound_operator"
2089 6 "cris_extend_operator"
2091 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2092 (match_operand:SI 3 "const_int_operand" "n,n"))
2093 (match_operand:SI 4 "register_operand" "r,r")))])
2094 (match_operand:SI 1 "register_operand" "0,0")]))
2095 (set (match_operand:SI 5 "register_operand" "=*4,r")
2096 (plus:SI (mult:SI (match_dup 2)
2099 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2100 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2103 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2106 (define_insn "*extophisi_swap_side_biap"
2107 [(set (match_operand:SI 0 "register_operand" "=r,r")
2109 7 "cris_plus_or_bound_operator"
2111 6 "cris_extend_operator"
2113 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2114 (match_operand:SI 3 "const_int_operand" "n,n"))
2115 (match_operand:SI 4 "register_operand" "r,r")))])
2116 (match_operand:SI 1 "register_operand" "0,0")]))
2117 (set (match_operand:SI 5 "register_operand" "=*4,r")
2118 (plus:SI (mult:SI (match_dup 2)
2121 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2122 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2125 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2128 ;; FIXME: These could have anonymous mode for operand 0.
2129 ;; FIXME: GCC should widen.
2133 (define_insn "*extopqihi_swap_side"
2134 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2137 5 "cris_extend_operator"
2139 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2140 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2141 (match_operand:HI 1 "register_operand" "0,0,0")))
2142 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2143 (plus:SI (match_dup 2)
2145 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2148 if (which_alternative == 0
2149 && (GET_CODE (operands[3]) != CONST_INT
2150 || INTVAL (operands[3]) > 127
2151 || INTVAL (operands[3]) < -128
2152 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2153 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2155 return \"add%e5.b [%4=%2%S3],%0\";
2160 (define_insn "*extopqisi_swap_side"
2161 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2163 6 "cris_plus_or_bound_operator"
2165 5 "cris_extend_operator"
2167 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2168 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2169 (match_operand:SI 1 "register_operand" "0,0,0")]))
2170 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2171 (plus:SI (match_dup 2)
2173 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2174 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2177 if (which_alternative == 0
2178 && (GET_CODE (operands[3]) != CONST_INT
2179 || INTVAL (operands[3]) > 127
2180 || INTVAL (operands[3]) < -128
2181 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2182 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2184 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2189 (define_insn "*extophisi_swap_side"
2190 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2192 6 "cris_plus_or_bound_operator"
2194 5 "cris_extend_operator"
2196 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2197 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
2198 (match_operand:SI 1 "register_operand" "0,0,0")]))
2199 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2200 (plus:SI (match_dup 2)
2202 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2203 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2206 if (which_alternative == 0
2207 && (GET_CODE (operands[3]) != CONST_INT
2208 || INTVAL (operands[3]) > 127
2209 || INTVAL (operands[3]) < -128
2210 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2211 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2213 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2216 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2217 ;; FIXME: These could have anonymous mode for operand 0.
2220 ;; FIXME: GCC should widen.
2222 (define_insn "*extopqihi"
2223 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2225 3 "cris_additive_operand_extend_operator"
2226 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2228 4 "cris_extend_operator"
2229 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2230 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2231 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2236 %x3%e4.%m4 %2,%1,%0"
2237 [(set_attr "slottable" "yes,yes,no,no")
2238 (set_attr "cc" "clobber")])
2242 (define_insn "*extopqisi"
2243 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2245 3 "cris_operand_extend_operator"
2246 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2248 4 "cris_extend_operator"
2249 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2250 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2251 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2252 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2257 %x3%e4.%m4 %2,%1,%0"
2258 [(set_attr "slottable" "yes,yes,no,no")])
2262 (define_insn "*extophisi"
2263 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2265 3 "cris_operand_extend_operator"
2266 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2268 4 "cris_extend_operator"
2269 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2270 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2271 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2272 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2277 %x3%e4.%m4 %2,%1,%0"
2278 [(set_attr "slottable" "yes,yes,no,no")])
2281 ;; As with the side-effect patterns, may have to have swapped operands for add.
2282 ;; FIXME: *should* be redundant to gcc.
2286 (define_insn "*extopqihi_swap"
2287 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2290 3 "cris_extend_operator"
2291 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2292 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2293 "operands[1] != frame_pointer_rtx"
2299 [(set_attr "slottable" "yes,yes,no,no")
2300 (set_attr "cc" "clobber")])
2304 (define_insn "*extopqisi_swap"
2305 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2307 4 "cris_plus_or_bound_operator"
2309 3 "cris_extend_operator"
2310 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2311 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2312 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2313 && operands[1] != frame_pointer_rtx"
2318 %x4%e3.%m3 %2,%1,%0"
2319 [(set_attr "slottable" "yes,yes,no,no")])
2323 (define_insn "*extophisi_swap"
2324 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2326 4 "cris_plus_or_bound_operator"
2328 3 "cris_extend_operator"
2329 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2330 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2331 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2332 && operands[1] != frame_pointer_rtx"
2337 %x4%e3.%m3 %2,%1,%0"
2338 [(set_attr "slottable" "yes,yes,no,no")])
2340 ;; This is the special case when we use what corresponds to the
2341 ;; instruction above in "casesi". Do *not* change it to use the generic
2342 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2343 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2344 ;; or replacing this pattern with something simpler, other variant
2345 ;; patterns were recognized or combined, including some prefix variants
2346 ;; where the value in pc is not that of the next instruction (which means
2347 ;; this instruction actually *is* special and *should* be marked as such).
2348 ;; When switching from the "generic pattern match" approach to this simpler
2349 ;; approach, there were insignificant differences in gcc, ipps and
2350 ;; product code, somehow due to scratching reload behind the ear or
2351 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2352 ;; product code became .001% smaller but "looked better". The testcase
2353 ;; "ipps" was just different at register allocation).
2355 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2356 ;; pattern with the default-label as the else, with the "if" being
2357 ;; index-is-less-than the max number of cases plus one. The default-label
2358 ;; is attached to the end of the case-table at time of output.
2360 (define_insn "*casesi_adds_w"
2363 (ltu (match_operand:SI 0 "register_operand" "r")
2364 (match_operand:SI 1 "const_int_operand" "n"))
2365 (plus:SI (sign_extend:SI
2367 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2370 (label_ref (match_operand 2 "" ""))))
2371 (use (label_ref (match_operand 3 "" "")))]
2373 "operands[0] != frame_pointer_rtx"
2375 "adds.w [$pc+%0.w],$pc"
2376 [(set_attr "cc" "clobber")])
2378 ;; Multiply instructions.
2380 ;; Sometimes powers of 2 (which are normally canonicalized to a
2381 ;; left-shift) appear here, as a result of address reloading.
2382 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2384 ;; FIXME: This may be unnecessary now.
2385 ;; Explicitly named for convenience of having a gen_... function.
2387 (define_insn "addi_mul"
2388 [(set (match_operand:SI 0 "register_operand" "=r")
2390 (match_operand:SI 1 "register_operand" "%0")
2391 (match_operand:SI 2 "const_int_operand" "n")))]
2392 "operands[0] != frame_pointer_rtx
2393 && operands[1] != frame_pointer_rtx
2394 && GET_CODE (operands[2]) == CONST_INT
2395 && (INTVAL (operands[2]) == 2
2396 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2397 || INTVAL (operands[2]) == 5)"
2400 if (INTVAL (operands[2]) == 2)
2401 return \"lslq 1,%0\";
2402 else if (INTVAL (operands[2]) == 4)
2403 return \"lslq 2,%0\";
2404 else if (INTVAL (operands[2]) == 3)
2405 return \"addi %0.w,%0\";
2406 else if (INTVAL (operands[2]) == 5)
2407 return \"addi %0.d,%0\";
2408 return \"BAD: adr_mulsi: %0=%1*%2\";
2410 [(set_attr "slottable" "yes")
2411 ;; No flags are changed if this insn is "addi", but it does not seem
2412 ;; worth the trouble to distinguish that to the lslq cases.
2413 (set_attr "cc" "clobber")])
2415 ;; The addi insn as it is normally used.
2417 (define_insn "*addi"
2418 [(set (match_operand:SI 0 "register_operand" "=r")
2420 (mult:SI (match_operand:SI 2 "register_operand" "r")
2421 (match_operand:SI 3 "const_int_operand" "n"))
2422 (match_operand:SI 1 "register_operand" "0")))]
2423 "operands[0] != frame_pointer_rtx
2424 && operands[1] != frame_pointer_rtx
2425 && GET_CODE (operands[3]) == CONST_INT
2426 && (INTVAL (operands[3]) == 1
2427 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2429 [(set_attr "slottable" "yes")
2430 (set_attr "cc" "none")])
2432 ;; The mstep instruction. Probably not useful by itself; it's to
2433 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2436 (define_insn "mstep_shift"
2437 [(set (match_operand:SI 0 "register_operand" "=r")
2439 (lt:SI (cc0) (const_int 0))
2440 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2442 (match_operand:SI 2 "register_operand" "r"))
2443 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2447 [(set_attr "slottable" "yes")])
2449 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2450 ;; to canonicalize the multiplications.
2452 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2454 (define_insn "mstep_mul"
2455 [(set (match_operand:SI 0 "register_operand" "=r")
2457 (lt:SI (cc0) (const_int 0))
2458 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2460 (match_operand:SI 2 "register_operand" "r"))
2461 (mult:SI (match_operand:SI 3 "register_operand" "0")
2463 "operands[0] != frame_pointer_rtx
2464 && operands[1] != frame_pointer_rtx
2465 && operands[2] != frame_pointer_rtx
2466 && operands[3] != frame_pointer_rtx"
2468 [(set_attr "slottable" "yes")])
2470 (define_insn "umulhisi3"
2471 [(set (match_operand:SI 0 "register_operand" "=r")
2473 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2474 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2475 "TARGET_HAS_MUL_INSNS"
2477 [(set (attr "slottable")
2478 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2480 (const_string "yes")))
2481 ;; Just N unusable here, but let's be safe.
2482 (set_attr "cc" "clobber")])
2484 (define_insn "umulqihi3"
2485 [(set (match_operand:HI 0 "register_operand" "=r")
2487 (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2488 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2489 "TARGET_HAS_MUL_INSNS"
2491 [(set (attr "slottable")
2492 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2494 (const_string "yes")))
2495 ;; Not exactly sure, but let's be safe.
2496 (set_attr "cc" "clobber")])
2498 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2499 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2500 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2501 ;; Inspection of optab code shows that there must be only one widening
2502 ;; multiplication per mode widened to.
2504 (define_insn "mulsi3"
2505 [(set (match_operand:SI 0 "register_operand" "=r")
2506 (mult:SI (match_operand:SI 1 "register_operand" "0")
2507 (match_operand:SI 2 "register_operand" "r")))]
2508 "TARGET_HAS_MUL_INSNS"
2510 [(set (attr "slottable")
2511 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2513 (const_string "yes")))
2514 ;; Just N unusable here, but let's be safe.
2515 (set_attr "cc" "clobber")])
2517 ;; A few multiply variations.
2519 ;; This really extends to SImode, so cc should be considered clobbered.
2521 (define_insn "mulqihi3"
2522 [(set (match_operand:HI 0 "register_operand" "=r")
2524 (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))
2525 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2526 "TARGET_HAS_MUL_INSNS"
2528 [(set (attr "slottable")
2529 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2531 (const_string "yes")))
2532 (set_attr "cc" "clobber")])
2534 (define_insn "mulhisi3"
2535 [(set (match_operand:SI 0 "register_operand" "=r")
2537 (sign_extend:SI (match_operand:HI 1 "register_operand" "0"))
2538 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2539 "TARGET_HAS_MUL_INSNS"
2541 [(set (attr "slottable")
2542 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2544 (const_string "yes")))
2545 ;; Just N unusable here, but let's be safe.
2546 (set_attr "cc" "clobber")])
2548 ;; When needed, we can get the high 32 bits from the overflow
2549 ;; register. We don't care to split and optimize these.
2551 ;; Note that cc0 is still valid after the move-from-overflow-register
2552 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2554 (define_insn "mulsidi3"
2555 [(set (match_operand:DI 0 "register_operand" "=r")
2557 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
2558 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2559 "TARGET_HAS_MUL_INSNS"
2560 "%!muls.d %2,%M0\;move $mof,%H0")
2562 (define_insn "umulsidi3"
2563 [(set (match_operand:DI 0 "register_operand" "=r")
2565 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
2566 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2567 "TARGET_HAS_MUL_INSNS"
2568 "%!mulu.d %2,%M0\;move $mof,%H0")
2570 ;; This pattern would probably not be needed if we add "mof" in its own
2571 ;; register class (and open a can of worms about /not/ pairing it with a
2572 ;; "normal" register). Having multiple register classes here, and
2573 ;; applicable to the v10 variant only, seems worse than having these two
2574 ;; patterns with multi-insn contents for now (may change; having a free
2575 ;; call-clobbered register is worth some trouble).
2577 (define_insn "smulsi3_highpart"
2578 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2582 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2583 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2585 (clobber (match_scratch:SI 3 "=X,1,1"))]
2586 "TARGET_HAS_MUL_INSNS"
2587 "%!muls.d %2,%1\;move $mof,%0"
2588 [(set_attr "cc" "clobber")])
2590 (define_insn "umulsi3_highpart"
2591 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2595 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2596 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2598 (clobber (match_scratch:SI 3 "=X,1,1"))]
2599 "TARGET_HAS_MUL_INSNS"
2600 "%!mulu.d %2,%1\;move $mof,%0"
2601 [(set_attr "cc" "clobber")])
2603 ;; Divide and modulus instructions. CRIS only has a step instruction.
2605 (define_insn "dstep_shift"
2606 [(set (match_operand:SI 0 "register_operand" "=r")
2608 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2610 (match_operand:SI 2 "register_operand" "r"))
2611 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2613 (match_operand:SI 4 "register_operand" "2"))
2614 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2618 [(set_attr "slottable" "yes")])
2620 ;; Here's a variant with mult instead of ashift.
2622 ;; FIXME: This should be investigated. Which one matches through combination?
2624 (define_insn "dstep_mul"
2625 [(set (match_operand:SI 0 "register_operand" "=r")
2627 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2629 (match_operand:SI 2 "register_operand" "r"))
2630 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2632 (match_operand:SI 4 "register_operand" "2"))
2633 (mult:SI (match_operand:SI 5 "register_operand" "0")
2635 "operands[0] != frame_pointer_rtx
2636 && operands[1] != frame_pointer_rtx
2637 && operands[2] != frame_pointer_rtx
2638 && operands[3] != frame_pointer_rtx"
2640 [(set_attr "slottable" "yes")])
2642 ;; Logical operators.
2646 ;; There is no use in defining "anddi3", because gcc can expand this by
2647 ;; itself, and make reasonable code without interference.
2649 ;; If the first operand is memory or a register and is the same as the
2650 ;; second operand, and the third operand is -256 or -65536, we can use
2651 ;; CLEAR instead. Or, if the first operand is a register, and the third
2652 ;; operand is 255 or 65535, we can zero_extend.
2653 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2654 ;; to be common enough to be worthwhile.
2655 ;; FIXME: This should be made obsolete.
2657 (define_expand "andsi3"
2658 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2659 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2660 (match_operand:SI 2 "general_operand" "")))]
2664 if (! (GET_CODE (operands[2]) == CONST_INT
2665 && (((INTVAL (operands[2]) == -256
2666 || INTVAL (operands[2]) == -65536)
2667 && rtx_equal_p (operands[1], operands[0]))
2668 || ((INTVAL (operands[2]) == 255
2669 || INTVAL (operands[2]) == 65535)
2670 && REG_P (operands[0])))))
2672 /* Make intermediate steps if operand0 is not a register or
2673 operand1 is not a register, and hope that the reload pass will
2674 make something useful out of it. Note that the operands are
2675 *not* canonicalized. For the moment, I chicken out on this,
2676 because all or most ports do not describe 'and' with
2677 canonicalized operands, and I seem to remember magic in reload,
2678 checking that operand1 has constraint '%0', in which case
2679 operand0 and operand1 must have similar predicates.
2680 FIXME: Investigate. */
2681 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2682 rtx reg1 = operands[1];
2686 emit_move_insn (reg0, reg1);
2690 emit_insn (gen_rtx_SET (SImode, reg0,
2691 gen_rtx_AND (SImode, reg1, operands[2])));
2693 /* Make sure we get the right *final* destination. */
2694 if (! REG_P (operands[0]))
2695 emit_move_insn (operands[0], reg0);
2701 ;; Some special cases of andsi3.
2703 (define_insn "*andsi_movu"
2704 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2705 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2706 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2707 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2708 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
2710 [(set_attr "slottable" "yes,yes,no")])
2712 (define_insn "*andsi_clear"
2713 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2714 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2715 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2716 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2717 && (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0]))"
2725 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2726 (set_attr "cc" "none")])
2728 ;; This is a catch-all pattern, taking care of everything that was not
2729 ;; matched in the insns above.
2731 ;; Sidenote: the tightening from "nonimmediate_operand" to
2732 ;; "register_operand" for operand 1 actually increased the register
2733 ;; pressure (worse code). That will hopefully change with an
2734 ;; improved reload pass.
2736 (define_insn "*expanded_andsi"
2737 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2738 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,r")
2739 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2747 [(set_attr "slottable" "yes,yes,yes,no,no")])
2749 ;; For both QI and HI we may use the quick patterns. This results in
2750 ;; useless condition codes, but that is used rarely enough for it to
2751 ;; normally be a win (could check ahead for use of cc0, but seems to be
2752 ;; more pain than win).
2754 ;; FIXME: See note for andsi3
2756 (define_expand "andhi3"
2757 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2758 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2759 (match_operand:HI 2 "general_operand" "")))]
2763 if (! (GET_CODE (operands[2]) == CONST_INT
2764 && (((INTVAL (operands[2]) == -256
2765 || INTVAL (operands[2]) == 65280)
2766 && rtx_equal_p (operands[1], operands[0]))
2767 || (INTVAL (operands[2]) == 255
2768 && REG_P (operands[0])))))
2770 /* See comment for andsi3. */
2771 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2772 rtx reg1 = operands[1];
2776 emit_move_insn (reg0, reg1);
2780 emit_insn (gen_rtx_SET (HImode, reg0,
2781 gen_rtx_AND (HImode, reg1, operands[2])));
2783 /* Make sure we get the right destination. */
2784 if (! REG_P (operands[0]))
2785 emit_move_insn (operands[0], reg0);
2791 ;; Some fast andhi3 special cases.
2793 (define_insn "*andhi_movu"
2794 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2795 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2797 "GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1])"
2799 [(set_attr "slottable" "yes,yes,no")])
2801 (define_insn "*andhi_clear"
2802 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2803 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2805 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
2807 [(set_attr "slottable" "yes,yes,no")
2808 (set_attr "cc" "none")])
2810 ;; Catch-all andhi3 pattern.
2812 (define_insn "*expanded_andhi"
2813 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2814 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2815 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2817 ;; Sidenote: the tightening from "general_operand" to
2818 ;; "register_operand" for operand 1 actually increased the register
2819 ;; pressure (worse code). That will hopefully change with an
2820 ;; improved reload pass.
2831 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2832 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2834 ;; A strict_low_part pattern.
2836 (define_insn "*andhi_lowpart"
2837 [(set (strict_low_part
2838 (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r"))
2839 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
2840 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2849 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2850 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2852 (define_insn "andqi3"
2853 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2854 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2855 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2864 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2865 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2867 (define_insn "*andqi_lowpart"
2868 [(set (strict_low_part
2869 (match_operand:QI 0 "register_operand" "=r,r,r,r,r"))
2870 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,r")
2871 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2879 [(set_attr "slottable" "yes,yes,yes,no,no")
2880 (set_attr "cc" "normal,normal,clobber,normal,normal")])
2884 ;; Same comment as anddi3 applies here - no need for such a pattern.
2886 ;; It seems there's no need to jump through hoops to get good code such as
2889 (define_insn "iorsi3"
2890 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
2891 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,r")
2892 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g,!To")))]
2901 [(set_attr "slottable" "yes,yes,yes,no,no,no")
2902 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2904 (define_insn "iorhi3"
2905 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2906 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2907 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2917 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2918 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2920 (define_insn "iorqi3"
2921 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2922 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2923 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2932 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2933 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2937 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
2939 (define_insn "xorsi3"
2940 [(set (match_operand:SI 0 "register_operand" "=r")
2941 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2942 (match_operand:SI 2 "register_operand" "r")))]
2945 [(set_attr "slottable" "yes")])
2947 (define_insn "xorhi3"
2948 [(set (match_operand:HI 0 "register_operand" "=r")
2949 (xor:HI (match_operand:HI 1 "register_operand" "%0")
2950 (match_operand:HI 2 "register_operand" "r")))]
2953 [(set_attr "slottable" "yes")
2954 (set_attr "cc" "clobber")])
2956 (define_insn "xorqi3"
2957 [(set (match_operand:QI 0 "register_operand" "=r")
2958 (xor:QI (match_operand:QI 1 "register_operand" "%0")
2959 (match_operand:QI 2 "register_operand" "r")))]
2962 [(set_attr "slottable" "yes")
2963 (set_attr "cc" "clobber")])
2967 ;; Questionable use, here mostly as a (slightly usable) define_expand
2970 (define_expand "negsf2"
2973 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
2974 (neg:SF (match_operand:SF 1
2975 "register_operand" "0")))
2976 (use (match_dup 2))])]
2980 operands[2] = gen_reg_rtx (SImode);
2981 operands[3] = GEN_INT (1 << 31);
2984 (define_insn "*expanded_negsf2"
2985 [(set (match_operand:SF 0 "register_operand" "=r")
2986 (neg:SF (match_operand:SF 1 "register_operand" "0")))
2987 (use (match_operand:SI 2 "register_operand" "r"))]
2990 [(set_attr "slottable" "yes")])
2992 ;; No "negdi2" although we could make one up that may be faster than
2993 ;; the one in libgcc.
2995 (define_insn "negsi2"
2996 [(set (match_operand:SI 0 "register_operand" "=r")
2997 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
3000 [(set_attr "slottable" "yes")])
3002 (define_insn "neghi2"
3003 [(set (match_operand:HI 0 "register_operand" "=r")
3004 (neg:HI (match_operand:HI 1 "register_operand" "r")))]
3007 [(set_attr "slottable" "yes")])
3009 (define_insn "negqi2"
3010 [(set (match_operand:QI 0 "register_operand" "=r")
3011 (neg:QI (match_operand:QI 1 "register_operand" "r")))]
3014 [(set_attr "slottable" "yes")])
3018 ;; See comment on anddi3 - no need for a DImode pattern.
3020 (define_insn "one_cmplsi2"
3021 [(set (match_operand:SI 0 "register_operand" "=r")
3022 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3025 [(set_attr "slottable" "yes")])
3027 (define_insn "one_cmplhi2"
3028 [(set (match_operand:HI 0 "register_operand" "=r")
3029 (not:HI (match_operand:HI 1 "register_operand" "0")))]
3032 [(set_attr "slottable" "yes")
3033 (set_attr "cc" "clobber")])
3035 (define_insn "one_cmplqi2"
3036 [(set (match_operand:QI 0 "register_operand" "=r")
3037 (not:QI (match_operand:QI 1 "register_operand" "0")))]
3040 [(set_attr "slottable" "yes")
3041 (set_attr "cc" "clobber")])
3043 ;; Arithmetic shift right.
3045 (define_insn "ashrsi3"
3046 [(set (match_operand:SI 0 "register_operand" "=r")
3047 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
3048 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3052 if (REG_S_P (operands[2]))
3053 return \"asr.d %2,%0\";
3055 return \"asrq %2,%0\";
3057 [(set_attr "slottable" "yes")])
3059 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3060 ;; the destination) when it changes shifts of lower modes into SImode,
3061 ;; it is better to make these expands an anonymous patterns instead of
3062 ;; the more correct define_insns. This occurs when gcc thinks that is
3063 ;; is better to widen to SImode and use immediate shift count.
3065 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3067 (define_expand "ashrhi3"
3069 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))
3071 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm")))
3072 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3073 (set (match_operand:HI 0 "general_operand" "=g")
3074 (subreg:HI (match_dup 5) 0))]
3080 for (i = 3; i < 6; i++)
3081 operands[i] = gen_reg_rtx (SImode);
3084 (define_insn "*expanded_ashrhi"
3085 [(set (match_operand:HI 0 "register_operand" "=r")
3086 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
3087 (match_operand:HI 2 "register_operand" "r")))]
3090 [(set_attr "slottable" "yes")])
3092 (define_insn "*ashrhi_lowpart"
3093 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3094 (ashiftrt:HI (match_dup 0)
3095 (match_operand:HI 1 "register_operand" "r")))]
3098 [(set_attr "slottable" "yes")])
3100 ;; Same comment goes as for "ashrhi3".
3102 (define_expand "ashrqi3"
3104 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3106 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3107 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3108 (set (match_operand:QI 0 "general_operand" "=g")
3109 (subreg:QI (match_dup 5) 0))]
3115 for (i = 3; i < 6; i++)
3116 operands[i] = gen_reg_rtx (SImode);
3119 (define_insn "*expanded_ashrqi"
3120 [(set (match_operand:QI 0 "register_operand" "=r")
3121 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
3122 (match_operand:QI 2 "register_operand" "r")))]
3125 [(set_attr "slottable" "yes")])
3127 ;; A strict_low_part matcher.
3129 (define_insn "*ashrqi_lowpart"
3130 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3131 (ashiftrt:QI (match_dup 0)
3132 (match_operand:QI 1 "register_operand" "r")))]
3135 [(set_attr "slottable" "yes")])
3137 ;; Logical shift right.
3139 (define_insn "lshrsi3"
3140 [(set (match_operand:SI 0 "register_operand" "=r")
3141 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3142 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3146 if (REG_S_P (operands[2]))
3147 return \"lsr.d %2,%0\";
3149 return \"lsrq %2,%0\";
3151 [(set_attr "slottable" "yes")])
3153 ;; Same comments as for ashrhi3.
3155 (define_expand "lshrhi3"
3157 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
3159 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "g")))
3160 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3161 (set (match_operand:HI 0 "general_operand" "=g")
3162 (subreg:HI (match_dup 5) 0))]
3168 for (i = 3; i < 6; i++)
3169 operands[i] = gen_reg_rtx (SImode);
3172 (define_insn "*expanded_lshrhi"
3173 [(set (match_operand:HI 0 "register_operand" "=r")
3174 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
3175 (match_operand:HI 2 "register_operand" "r")))]
3178 [(set_attr "slottable" "yes")])
3180 ;; A strict_low_part matcher.
3182 (define_insn "*lshrhi_lowpart"
3183 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3184 (lshiftrt:HI (match_dup 0)
3185 (match_operand:HI 1 "register_operand" "r")))]
3188 [(set_attr "slottable" "yes")])
3190 ;; Same comments as for ashrhi3.
3192 (define_expand "lshrqi3"
3194 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3196 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3197 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3198 (set (match_operand:QI 0 "general_operand" "=g")
3199 (subreg:QI (match_dup 5) 0))]
3205 for (i = 3; i < 6; i++)
3206 operands[i] = gen_reg_rtx (SImode);
3209 (define_insn "*expanded_lshrqi"
3210 [(set (match_operand:QI 0 "register_operand" "=r")
3211 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
3212 (match_operand:QI 2 "register_operand" "r")))]
3215 [(set_attr "slottable" "yes")])
3217 ;; A strict_low_part matcher.
3219 (define_insn "*lshrqi_lowpart"
3220 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3221 (lshiftrt:QI (match_dup 0)
3222 (match_operand:QI 1 "register_operand" "r")))]
3225 [(set_attr "slottable" "yes")])
3227 ;; Arithmetic/logical shift left.
3229 (define_insn "ashlsi3"
3230 [(set (match_operand:SI 0 "register_operand" "=r")
3231 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3232 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3236 if (REG_S_P (operands[2]))
3237 return \"lsl.d %2,%0\";
3239 return \"lslq %2,%0\";
3241 [(set_attr "slottable" "yes")])
3243 ;; For narrower modes than SI, we can use lslq although it makes cc
3244 ;; unusable. The win is that we do not have to reload the shift-count
3247 (define_insn "ashlhi3"
3248 [(set (match_operand:HI 0 "register_operand" "=r,r")
3249 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
3250 (match_operand:HI 2 "nonmemory_operand" "r,K")))]
3255 (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 15)
3257 : (CONSTANT_P (operands[2])
3258 ? \"lslq %2,%0\" : \"lsl.w %2,%0\");
3260 [(set_attr "slottable" "yes")
3261 (set_attr "cc" "normal,clobber")])
3263 ;; A strict_low_part matcher.
3265 (define_insn "*ashlhi_lowpart"
3266 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3267 (ashift:HI (match_dup 0)
3268 (match_operand:HI 1 "register_operand" "r")))]
3271 [(set_attr "slottable" "yes")])
3273 (define_insn "ashlqi3"
3274 [(set (match_operand:QI 0 "register_operand" "=r,r")
3275 (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
3276 (match_operand:QI 2 "nonmemory_operand" "r,K")))]
3281 (GET_CODE (operands[2]) == CONST_INT
3282 && INTVAL (operands[2]) > 7)
3284 : (CONSTANT_P (operands[2])
3285 ? \"lslq %2,%0\" : \"lsl.b %2,%0\");
3287 [(set_attr "slottable" "yes")
3288 (set_attr "cc" "normal,clobber")])
3290 ;; A strict_low_part matcher.
3292 (define_insn "*ashlqi_lowpart"
3293 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3294 (ashift:QI (match_dup 0)
3295 (match_operand:QI 1 "register_operand" "r")))]
3298 [(set_attr "slottable" "yes")])
3300 ;; Various strange insns that gcc likes.
3302 ;; Fortunately, it is simple to construct an abssf (although it may not
3303 ;; be very much used in practice).
3305 (define_insn "abssf2"
3306 [(set (match_operand:SF 0 "register_operand" "=r")
3307 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3309 "lslq 1,%0\;lsrq 1,%0")
3311 (define_insn "abssi2"
3312 [(set (match_operand:SI 0 "register_operand" "=r")
3313 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3316 [(set_attr "slottable" "yes")])
3318 ;; FIXME: GCC should be able to do these expansions itself.
3320 (define_expand "abshi2"
3322 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))
3323 (set (match_dup 3) (abs:SI (match_dup 2)))
3324 (set (match_operand:HI 0 "register_operand" "=r")
3325 (subreg:HI (match_dup 3) 0))]
3327 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3329 (define_expand "absqi2"
3331 (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))
3332 (set (match_dup 3) (abs:SI (match_dup 2)))
3333 (set (match_operand:QI 0 "register_operand" "=r")
3334 (subreg:QI (match_dup 3) 0))]
3336 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3338 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3339 ;; operation supported by gcc. Used in casesi, but used now and then in
3342 (define_insn "uminsi3"
3343 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3344 (umin:SI (match_operand:SI 1 "register_operand" "%0,0,0,r")
3345 (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
3349 if (GET_CODE (operands[2]) == CONST_INT)
3351 if (INTVAL (operands[2]) < 256)
3352 return \"bound.b %2,%0\";
3354 if (INTVAL (operands[2]) < 65536)
3355 return \"bound.w %2,%0\";
3357 else if (which_alternative == 3)
3358 return \"bound.d %2,%1,%0\";
3360 return \"bound.d %2,%0\";
3362 [(set_attr "slottable" "yes,yes,no,no")])
3364 ;; Jump and branch insns.
3368 (label_ref (match_operand 0 "" "")))]
3371 [(set_attr "slottable" "has_slot")])
3373 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3374 ;; here, since the insn is not recognized as an indirect jump by
3375 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3376 ;; change from general_operand to nonimmediate_operand (at least the docs
3377 ;; should be changed), but then again the pattern is called indirect_jump.
3378 (define_insn "indirect_jump"
3379 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3383 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3384 ;; a single ret or jump [sp+] or a contiguous sequence of movem:able saved
3385 ;; registers. No allocated stack space is allowed.
3386 ;; Note that for this pattern, although named, it is ok to check the
3387 ;; context of the insn in the test, not only compiler switches.
3389 (define_insn "return"
3391 "cris_simple_epilogue ()"
3396 /* Just needs to hold a 'movem [sp+],rN'. */
3397 char rd[sizeof (\"movem [$sp+],$r99\")];
3399 /* Try to avoid reorg.c surprises; avoid emitting invalid code, prefer
3400 crashing. This test would have avoided invalid code for target/7042. */
3401 if (current_function_epilogue_delay_list != NULL)
3406 /* Start from the last call-saved register. We know that we have a
3407 simple epilogue, so we just have to find the last register in the
3409 for (i = 8; i >= 0; i--)
3410 if (regs_ever_live[i]
3411 || (i == PIC_OFFSET_TABLE_REGNUM
3412 && current_function_uses_pic_offset_table))
3416 sprintf (rd, \"movem [$sp+],$%s\", reg_names [i]);
3418 if (regs_ever_live[CRIS_SRP_REGNUM]
3419 || cris_return_address_on_stack ())
3422 output_asm_insn (rd, operands);
3423 return \"jump [$sp+]\";
3428 output_asm_insn (\"reT\", operands);
3429 output_asm_insn (rd, operands);
3435 [(set (attr "slottable")
3438 "(regs_ever_live[CRIS_SRP_REGNUM]
3439 || cris_return_address_on_stack ())")
3441 (const_string "no") ; If jump then not slottable.
3445 || (flag_pic != 0 && regs_ever_live[1])
3446 || (PIC_OFFSET_TABLE_REGNUM == 0
3447 && cris_cfun_uses_pic_table ()))")
3449 (const_string "no") ; ret+movem [sp+],rx: slot already filled.
3450 (const_string "has_slot")))) ; If ret then need to fill a slot.
3451 (set_attr "cc" "none")])
3453 ;; Conditional branches.
3455 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3456 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3461 (if_then_else (eq (cc0)
3463 (label_ref (match_operand 0 "" ""))
3467 [(set_attr "slottable" "has_slot")])
3471 (if_then_else (ne (cc0)
3473 (label_ref (match_operand 0 "" ""))
3477 [(set_attr "slottable" "has_slot")])
3481 (if_then_else (gt (cc0)
3483 (label_ref (match_operand 0 "" ""))
3489 (cc_prev_status.flags & CC_NO_OVERFLOW)
3490 ? 0 : \"bgt %l0%#\";
3492 [(set_attr "slottable" "has_slot")])
3496 (if_then_else (gtu (cc0)
3498 (label_ref (match_operand 0 "" ""))
3502 [(set_attr "slottable" "has_slot")])
3506 (if_then_else (lt (cc0)
3508 (label_ref (match_operand 0 "" ""))
3514 (cc_prev_status.flags & CC_NO_OVERFLOW)
3515 ? \"bmi %l0%#\" : \"blt %l0%#\";
3517 [(set_attr "slottable" "has_slot")])
3521 (if_then_else (ltu (cc0)
3523 (label_ref (match_operand 0 "" ""))
3527 [(set_attr "slottable" "has_slot")])
3531 (if_then_else (ge (cc0)
3533 (label_ref (match_operand 0 "" ""))
3539 (cc_prev_status.flags & CC_NO_OVERFLOW)
3540 ? \"bpl %l0%#\" : \"bge %l0%#\";
3542 [(set_attr "slottable" "has_slot")])
3546 (if_then_else (geu (cc0)
3548 (label_ref (match_operand 0 "" ""))
3552 [(set_attr "slottable" "has_slot")])
3556 (if_then_else (le (cc0)
3558 (label_ref (match_operand 0 "" ""))
3564 (cc_prev_status.flags & CC_NO_OVERFLOW)
3565 ? 0 : \"ble %l0%#\";
3567 [(set_attr "slottable" "has_slot")])
3571 (if_then_else (leu (cc0)
3573 (label_ref (match_operand 0 "" ""))
3577 [(set_attr "slottable" "has_slot")])
3579 ;; Reversed anonymous patterns to the ones above, as mandated.
3581 (define_insn "*beq_reversed"
3583 (if_then_else (eq (cc0)
3586 (label_ref (match_operand 0 "" ""))))]
3589 [(set_attr "slottable" "has_slot")])
3591 (define_insn "*bne_reversed"
3593 (if_then_else (ne (cc0)
3596 (label_ref (match_operand 0 "" ""))))]
3599 [(set_attr "slottable" "has_slot")])
3601 (define_insn "*bgt_reversed"
3603 (if_then_else (gt (cc0)
3606 (label_ref (match_operand 0 "" ""))))]
3611 (cc_prev_status.flags & CC_NO_OVERFLOW)
3612 ? 0 : \"ble %l0%#\";
3614 [(set_attr "slottable" "has_slot")])
3616 (define_insn "*bgtu_reversed"
3618 (if_then_else (gtu (cc0)
3621 (label_ref (match_operand 0 "" ""))))]
3624 [(set_attr "slottable" "has_slot")])
3626 (define_insn "*blt_reversed"
3628 (if_then_else (lt (cc0)
3631 (label_ref (match_operand 0 "" ""))))]
3636 (cc_prev_status.flags & CC_NO_OVERFLOW)
3637 ? \"bpl %l0%#\" : \"bge %l0%#\";
3639 [(set_attr "slottable" "has_slot")])
3641 (define_insn "*bltu_reversed"
3643 (if_then_else (ltu (cc0)
3646 (label_ref (match_operand 0 "" ""))))]
3649 [(set_attr "slottable" "has_slot")])
3651 (define_insn "*bge_reversed"
3653 (if_then_else (ge (cc0)
3656 (label_ref (match_operand 0 "" ""))))]
3661 (cc_prev_status.flags & CC_NO_OVERFLOW)
3662 ? \"bmi %l0%#\" : \"blt %l0%#\";
3664 [(set_attr "slottable" "has_slot")])
3666 (define_insn "*bgeu_reversed"
3668 (if_then_else (geu (cc0)
3671 (label_ref (match_operand 0 "" ""))))]
3674 [(set_attr "slottable" "has_slot")])
3676 (define_insn "*ble_reversed"
3678 (if_then_else (le (cc0)
3681 (label_ref (match_operand 0 "" ""))))]
3686 (cc_prev_status.flags & CC_NO_OVERFLOW)
3687 ? 0 : \"bgt %l0%#\";
3689 [(set_attr "slottable" "has_slot")])
3691 (define_insn "*bleu_reversed"
3693 (if_then_else (leu (cc0)
3696 (label_ref (match_operand 0 "" ""))))]
3699 [(set_attr "slottable" "has_slot")])
3701 ;; Set on condition: sCC.
3703 ;; Like bCC, we have to check the overflow bit for
3704 ;; signed conditions.
3707 [(set (match_operand:SI 0 "register_operand" "=r")
3708 (geu:SI (cc0) (const_int 0)))]
3711 [(set_attr "slottable" "yes")
3712 (set_attr "cc" "none")])
3715 [(set (match_operand:SI 0 "register_operand" "=r")
3716 (ltu:SI (cc0) (const_int 0)))]
3719 [(set_attr "slottable" "yes")
3720 (set_attr "cc" "none")])
3723 [(set (match_operand:SI 0 "register_operand" "=r")
3724 (eq:SI (cc0) (const_int 0)))]
3727 [(set_attr "slottable" "yes")
3728 (set_attr "cc" "none")])
3731 [(set (match_operand:SI 0 "register_operand" "=r")
3732 (ge:SI (cc0) (const_int 0)))]
3737 (cc_prev_status.flags & CC_NO_OVERFLOW)
3738 ? \"spl %0\" : \"sge %0\";
3740 [(set_attr "slottable" "yes")
3741 (set_attr "cc" "none")])
3744 [(set (match_operand:SI 0 "register_operand" "=r")
3745 (gt:SI (cc0) (const_int 0)))]
3750 (cc_prev_status.flags & CC_NO_OVERFLOW)
3753 [(set_attr "slottable" "yes")
3754 (set_attr "cc" "none")])
3757 [(set (match_operand:SI 0 "register_operand" "=r")
3758 (gtu:SI (cc0) (const_int 0)))]
3761 [(set_attr "slottable" "yes")
3762 (set_attr "cc" "none")])
3765 [(set (match_operand:SI 0 "register_operand" "=r")
3766 (le:SI (cc0) (const_int 0)))]
3771 (cc_prev_status.flags & CC_NO_OVERFLOW)
3774 [(set_attr "slottable" "yes")
3775 (set_attr "cc" "none")])
3778 [(set (match_operand:SI 0 "register_operand" "=r")
3779 (leu:SI (cc0) (const_int 0)))]
3782 [(set_attr "slottable" "yes")
3783 (set_attr "cc" "none")])
3786 [(set (match_operand:SI 0 "register_operand" "=r")
3787 (lt:SI (cc0) (const_int 0)))]
3792 (cc_prev_status.flags & CC_NO_OVERFLOW)
3793 ? \"smi %0\" : \"slt %0\";
3795 [(set_attr "slottable" "yes")
3796 (set_attr "cc" "none")])
3799 [(set (match_operand:SI 0 "register_operand" "=r")
3800 (ne:SI (cc0) (const_int 0)))]
3803 [(set_attr "slottable" "yes")
3804 (set_attr "cc" "none")])
3808 ;; We need to make these patterns "expand", since the real operand is
3809 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3810 ;; and cannot be checked if it were a "normal" pattern.
3811 ;; Note that "call" and "call_value" are *always* called with a
3812 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3813 ;; instructions is a different issue.
3815 (define_expand "call"
3816 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3817 (match_operand 1 "general_operand" ""))
3818 ;; 16 is the srp (can't use the symbolic name here)
3819 (clobber (reg:SI 16))])]
3825 if (GET_CODE (operands[0]) != MEM)
3830 op0 = XEXP (operands[0], 0);
3832 /* It might be that code can be generated that jumps to 0 (or to a
3833 specific address). Don't abort on that. At least there's a
3835 if (CONSTANT_ADDRESS_P (op0) && GET_CODE (op0) != CONST_INT)
3840 /* For local symbols (non-PLT), get the plain symbol reference
3841 into a register. For symbols that can be PLT, make them PLT. */
3842 if (cris_gotless_symbol (op0) || GET_CODE (op0) != SYMBOL_REF)
3843 op0 = force_reg (Pmode, op0);
3844 else if (cris_symbol (op0))
3845 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3846 for the symbol cause bad recombinatorial effects? */
3847 op0 = force_reg (Pmode,
3850 gen_rtx_UNSPEC (VOIDmode,
3851 gen_rtvec (1, op0), 0)));
3855 operands[0] = replace_equiv_address (operands[0], op0);
3860 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3861 ;; order of preference (Q includes r, but r is shorter, faster)
3863 (define_insn "*expanded_call"
3864 [(call (mem:QI (match_operand:SI
3865 0 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3866 (match_operand 1 "" ""))
3867 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3868 "! TARGET_AVOID_GOTPLT"
3871 ;; Same as above, since can't afford wasting a constraint letter to mean
3872 ;; "S unless TARGET_AVOID_GOTPLT".
3873 (define_insn "*expanded_call_no_gotplt"
3874 [(call (mem:QI (match_operand:SI
3875 0 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3876 (match_operand 1 "" ""))
3877 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3878 "TARGET_AVOID_GOTPLT"
3881 (define_expand "call_value"
3882 [(parallel [(set (match_operand 0 "" "")
3883 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3884 (match_operand 2 "" "")))
3885 ;; 16 is the srp (can't use symbolic name)
3886 (clobber (reg:SI 16))])]
3892 if (GET_CODE (operands[1]) != MEM)
3897 op1 = XEXP (operands[1], 0);
3899 /* It might be that code can be generated that jumps to 0 (or to a
3900 specific address). Don't abort on that. At least there's a
3902 if (CONSTANT_ADDRESS_P (op1) && GET_CODE (op1) != CONST_INT)
3907 if (cris_gotless_symbol (op1))
3908 op1 = force_reg (Pmode, op1);
3909 else if (cris_symbol (op1))
3910 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3911 for the symbol cause bad recombinatorial effects? */
3912 op1 = force_reg (Pmode,
3915 gen_rtx_UNSPEC (VOIDmode,
3916 gen_rtvec (1, op1), 0)));
3920 operands[1] = replace_equiv_address (operands[1], op1);
3925 ;; Accept *anything* as operand 2. The validity other than "general" of
3926 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3927 ;; order of preference (Q includes r, but r is shorter, faster).
3928 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3929 ;; than requiring getting rPIC + sym:PLT into a register.
3931 (define_insn "*expanded_call_value"
3932 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3933 (call (mem:QI (match_operand:SI
3934 1 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3935 (match_operand 2 "" "")))
3936 (clobber (reg:SI 16))]
3937 "! TARGET_AVOID_GOTPLT"
3939 [(set_attr "cc" "clobber")])
3941 ;; Same as above, since can't afford wasting a constraint letter to mean
3942 ;; "S unless TARGET_AVOID_GOTPLT".
3943 (define_insn "*expanded_call_value_no_gotplt"
3944 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3945 (call (mem:QI (match_operand:SI
3946 1 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3947 (match_operand 2 "" "")))
3948 (clobber (reg:SI 16))]
3949 "TARGET_AVOID_GOTPLT"
3951 [(set_attr "cc" "clobber")])
3953 ;; Used in debugging. No use for the direct pattern; unfilled
3954 ;; delayed-branches are taken care of by other means.
3960 [(set_attr "cc" "none")])
3962 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3963 ;; a table to pc" (adds.w [pc+%0.w],pc).
3965 ;; Note: if you change the "parallel" (or add anything after it) in
3966 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3967 ;; accordingly, to add the default case at the end of the jump-table.
3969 (define_expand "casesi"
3970 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3972 (minus:SI (match_dup 5)
3973 (match_operand:SI 1 "const_int_operand" "n")))
3975 (umin:SI (match_dup 6)
3976 (match_operand:SI 2 "const_int_operand" "n")))
3980 (ltu (match_dup 7) (match_dup 2))
3981 (plus:SI (sign_extend:SI
3983 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3986 (label_ref (match_operand 4 "" ""))))
3987 (use (label_ref (match_operand 3 "" "")))])]
3991 operands[2] = plus_constant (operands[2], 1);
3992 operands[5] = gen_reg_rtx (SImode);
3993 operands[6] = gen_reg_rtx (SImode);
3994 operands[7] = gen_reg_rtx (SImode);
3997 ;; Split-patterns. Some of them have modes unspecified. This
3998 ;; should always be ok; if for no other reason sparc.md has it as
4001 ;; When register_operand is specified for an operand, we can get a
4002 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
4003 ;; for a register_operand and that REGNO can be used as is. It is best to
4004 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
4006 ;; op [rx + 0],ry,rz
4007 ;; The index to rx is optimized into zero, and gone.
4009 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
4010 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
4014 ;; Lose if rz=ry or rx=rz.
4015 ;; Call this op-extend-split
4018 [(set (match_operand 0 "register_operand" "")
4020 4 "cris_operand_extend_operator"
4021 [(match_operand 1 "register_operand" "")
4023 3 "cris_extend_operator"
4024 [(match_operand 2 "memory_operand" "")])]))]
4025 "REG_P (operands[0])
4026 && REG_P (operands[1])
4027 && REGNO (operands[1]) != REGNO (operands[0])
4028 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4029 && REG_P (XEXP (operands[2], 0))
4030 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4036 (match_op_dup 3 [(match_dup 2)])]))]
4039 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
4042 ;; Do this for plus or bound only, being commutative operations, since we
4043 ;; have swapped the operands.
4044 ;; Call this op-extend-split-rx=rz
4047 [(set (match_operand 0 "register_operand" "")
4049 4 "cris_plus_or_bound_operator"
4050 [(match_operand 1 "register_operand" "")
4052 3 "cris_extend_operator"
4053 [(match_operand 2 "memory_operand" "")])]))]
4054 "REG_P (operands[0])
4055 && REG_P (operands[1])
4056 && REGNO (operands[1]) != REGNO (operands[0])
4057 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4058 && REG_P (XEXP (operands[2], 0))
4059 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4061 (match_op_dup 3 [(match_dup 2)]))
4068 ;; As the op-extend-split, but swapped operands, and only for
4069 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4070 ;; this needed? Is it?
4071 ;; Call this op-extend-split-swapped
4074 [(set (match_operand 0 "register_operand" "")
4076 4 "cris_plus_or_bound_operator"
4078 3 "cris_extend_operator"
4079 [(match_operand 2 "memory_operand" "")])
4080 (match_operand 1 "register_operand" "")]))]
4081 "REG_P (operands[0])
4082 && REG_P (operands[1])
4083 && REGNO (operands[1]) != REGNO (operands[0])
4084 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4085 && REG_P (XEXP (operands[2], 0))
4086 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4092 (match_op_dup 3 [(match_dup 2)])]))]
4095 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4096 ;; bound. Call this op-extend-split-swapped-rx=rz.
4099 [(set (match_operand 0 "register_operand" "")
4101 4 "cris_plus_or_bound_operator"
4103 3 "cris_extend_operator"
4104 [(match_operand 2 "memory_operand" "")])
4105 (match_operand 1 "register_operand" "")]))]
4106 "REG_P (operands[0])
4107 && REG_P (operands[1])
4108 && REGNO (operands[1]) != REGNO (operands[0])
4109 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4110 && REG_P (XEXP (operands[2], 0))
4111 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4113 (match_op_dup 3 [(match_dup 2)]))
4120 ;; As op-extend-split, but the mem operand is not extended.
4122 ;; op [rx],ry,rz changed into
4125 ;; lose if ry=rz or rx=rz
4126 ;; Call this op-extend.
4129 [(set (match_operand 0 "register_operand" "")
4131 3 "cris_orthogonal_operator"
4132 [(match_operand 1 "register_operand" "")
4133 (match_operand 2 "memory_operand" "")]))]
4134 "REG_P (operands[0])
4135 && REG_P (operands[1])
4136 && REGNO (operands[1]) != REGNO (operands[0])
4137 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4138 && REG_P (XEXP (operands[2], 0))
4139 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4148 ;; As op-extend-split-rx=rz, non-extended.
4149 ;; Call this op-split-rx=rz
4152 [(set (match_operand 0 "register_operand" "")
4154 3 "cris_commutative_orth_op"
4155 [(match_operand 2 "memory_operand" "")
4156 (match_operand 1 "register_operand" "")]))]
4157 "REG_P (operands[0])
4158 && REG_P (operands[1])
4159 && REGNO (operands[1]) != REGNO (operands[0])
4160 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4161 && REG_P (XEXP (operands[2], 0))
4162 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4171 ;; As op-extend-split-swapped, nonextended.
4172 ;; Call this op-split-swapped.
4175 [(set (match_operand 0 "register_operand" "")
4177 3 "cris_commutative_orth_op"
4178 [(match_operand 1 "register_operand" "")
4179 (match_operand 2 "memory_operand" "")]))]
4180 "REG_P (operands[0]) && REG_P (operands[1])
4181 && REGNO (operands[1]) != REGNO (operands[0])
4182 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4183 && REG_P (XEXP (operands[2], 0))
4184 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4193 ;; As op-extend-split-swapped-rx=rz, non-extended.
4194 ;; Call this op-split-swapped-rx=rz.
4197 [(set (match_operand 0 "register_operand" "")
4199 3 "cris_orthogonal_operator"
4200 [(match_operand 2 "memory_operand" "")
4201 (match_operand 1 "register_operand" "")]))]
4202 "REG_P (operands[0]) && REG_P (operands[1])
4203 && REGNO (operands[1]) != REGNO (operands[0])
4204 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4205 && REG_P (XEXP (operands[2], 0))
4206 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4215 ;; Splits for all cases in side-effect insns where (possibly after reload
4216 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4218 ;; move.S1 [rx=rx+rz.S2],ry
4222 [(set (match_operand 0 "register_operand" "")
4226 (mult:SI (match_operand:SI 1 "register_operand" "")
4227 (match_operand:SI 2 "const_int_operand" ""))
4228 (match_operand:SI 3 "register_operand" ""))]))
4229 (set (match_operand:SI 4 "register_operand" "")
4230 (plus:SI (mult:SI (match_dup 1)
4233 "REG_P (operands[3]) && REG_P (operands[4])
4234 && REGNO (operands[3]) == REGNO (operands[4])"
4235 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4237 (set (match_dup 0) (match_dup 5))]
4238 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4240 ;; move.S1 [rx=rx+i],ry
4244 [(set (match_operand 0 "register_operand" "")
4247 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4248 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4249 (set (match_operand:SI 3 "register_operand" "")
4250 (plus:SI (match_dup 1)
4252 "(rtx_equal_p (operands[3], operands[1])
4253 || rtx_equal_p (operands[3], operands[2]))"
4254 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4255 (set (match_dup 0) (match_dup 4))]
4256 "operands[4] = replace_equiv_address (operands[5], operands[3]);")
4258 ;; move.S1 ry,[rx=rx+rz.S2]
4262 [(set (match_operator
4265 (mult:SI (match_operand:SI 0 "register_operand" "")
4266 (match_operand:SI 1 "const_int_operand" ""))
4267 (match_operand:SI 2 "register_operand" ""))])
4268 (match_operand 3 "register_operand" ""))
4269 (set (match_operand:SI 4 "register_operand" "")
4270 (plus:SI (mult:SI (match_dup 0)
4273 "REG_P (operands[2]) && REG_P (operands[4])
4274 && REGNO (operands[4]) == REGNO (operands[2])"
4275 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4277 (set (match_dup 5) (match_dup 3))]
4278 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4280 ;; move.S1 ry,[rx=rx+i]
4284 [(set (match_operator
4286 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4287 (match_operand:SI 1 "cris_bdap_operand" ""))])
4288 (match_operand 2 "register_operand" ""))
4289 (set (match_operand:SI 3 "register_operand" "")
4290 (plus:SI (match_dup 0)
4292 "(rtx_equal_p (operands[3], operands[0])
4293 || rtx_equal_p (operands[3], operands[1]))"
4294 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4295 (set (match_dup 5) (match_dup 2))]
4296 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4298 ;; clear.d [rx=rx+rz.S2]
4302 [(set (mem:SI (plus:SI
4303 (mult:SI (match_operand:SI 0 "register_operand" "")
4304 (match_operand:SI 1 "const_int_operand" ""))
4305 (match_operand:SI 2 "register_operand" "")))
4307 (set (match_operand:SI 3 "register_operand" "")
4308 (plus:SI (mult:SI (match_dup 0)
4311 "REG_P (operands[2]) && REG_P (operands[3])
4312 && REGNO (operands[3]) == REGNO (operands[2])"
4313 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4315 (set (mem:SI (match_dup 3)) (const_int 0))]
4318 ;; clear.w [rx=rx+rz.S2]
4322 [(set (mem:HI (plus:SI
4323 (mult:SI (match_operand:SI 0 "register_operand" "")
4324 (match_operand:SI 1 "const_int_operand" ""))
4325 (match_operand:SI 2 "register_operand" "")))
4327 (set (match_operand:SI 3 "register_operand" "")
4328 (plus:SI (mult:SI (match_dup 0)
4331 "REG_P (operands[2]) && REG_P (operands[3])
4332 && REGNO (operands[3]) == REGNO (operands[2])"
4333 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4335 (set (mem:HI (match_dup 3)) (const_int 0))]
4338 ;; clear.b [rx=rx+rz.S2]
4342 [(set (mem:QI (plus:SI
4343 (mult:SI (match_operand:SI 0 "register_operand" "")
4344 (match_operand:SI 1 "const_int_operand" ""))
4345 (match_operand:SI 2 "register_operand" "")))
4347 (set (match_operand:SI 3 "register_operand" "")
4348 (plus:SI (mult:SI (match_dup 0)
4351 "REG_P (operands[2]) && REG_P (operands[3])
4352 && REGNO (operands[3]) == REGNO (operands[2])"
4353 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4355 (set (mem:QI (match_dup 3)) (const_int 0))]
4358 ;; clear.d [rx=rx+i]
4363 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4364 (match_operand:SI 1 "cris_bdap_operand" "")))
4366 (set (match_operand:SI 2 "register_operand" "")
4367 (plus:SI (match_dup 0)
4369 "(rtx_equal_p (operands[0], operands[2])
4370 || rtx_equal_p (operands[2], operands[1]))"
4371 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4372 (set (mem:SI (match_dup 2)) (const_int 0))]
4375 ;; clear.w [rx=rx+i]
4380 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4381 (match_operand:SI 1 "cris_bdap_operand" "")))
4383 (set (match_operand:SI 2 "register_operand" "")
4384 (plus:SI (match_dup 0)
4386 "(rtx_equal_p (operands[0], operands[2])
4387 || rtx_equal_p (operands[2], operands[1]))"
4388 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4389 (set (mem:HI (match_dup 2)) (const_int 0))]
4392 ;; clear.b [rx=rx+i]
4397 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4398 (match_operand:SI 1 "cris_bdap_operand" "")))
4400 (set (match_operand:SI 2 "register_operand" "")
4401 (plus:SI (match_dup 0)
4403 "(rtx_equal_p (operands[0], operands[2])
4404 || rtx_equal_p (operands[2], operands[1]))"
4405 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4406 (set (mem:QI (match_dup 2)) (const_int 0))]
4409 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4413 [(set (match_operand 0 "register_operand" "")
4415 5 "cris_extend_operator"
4417 (mult:SI (match_operand:SI 1 "register_operand" "")
4418 (match_operand:SI 2 "const_int_operand" ""))
4419 (match_operand:SI 3 "register_operand" "")))]))
4420 (set (match_operand:SI 4 "register_operand" "")
4421 (plus:SI (mult:SI (match_dup 1)
4424 "REG_P (operands[3])
4425 && REG_P (operands[4])
4426 && REGNO (operands[3]) == REGNO (operands[4])"
4427 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4429 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4430 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4432 ;; mov(s|u).S1 [rx=rx+i],ry
4436 [(set (match_operand 0 "register_operand" "")
4438 4 "cris_extend_operator"
4440 (match_operand:SI 1 "cris_bdap_operand" "")
4441 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4442 (set (match_operand:SI 3 "register_operand" "")
4443 (plus:SI (match_dup 1)
4445 "(rtx_equal_p (operands[1], operands[3])
4446 || rtx_equal_p (operands[2], operands[3]))"
4447 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4448 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4449 "operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);")
4451 ;; op.S1 [rx=rx+i],ry
4455 [(set (match_operand 0 "register_operand" "")
4457 5 "cris_orthogonal_operator"
4458 [(match_operand 1 "register_operand" "")
4460 (match_operand:SI 2 "cris_bdap_operand" "")
4461 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4462 (set (match_operand:SI 4 "register_operand" "")
4463 (plus:SI (match_dup 2)
4465 "(rtx_equal_p (operands[4], operands[2])
4466 || rtx_equal_p (operands[4], operands[3]))"
4467 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4468 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4469 "operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);")
4471 ;; op.S1 [rx=rx+rz.S2],ry
4475 [(set (match_operand 0 "register_operand" "")
4477 6 "cris_orthogonal_operator"
4478 [(match_operand 1 "register_operand" "")
4480 (mult:SI (match_operand:SI 2 "register_operand" "")
4481 (match_operand:SI 3 "const_int_operand" ""))
4482 (match_operand:SI 4 "register_operand" "")))]))
4483 (set (match_operand:SI 5 "register_operand" "")
4484 (plus:SI (mult:SI (match_dup 2)
4487 "REG_P (operands[4])
4488 && REG_P (operands[5])
4489 && REGNO (operands[5]) == REGNO (operands[4])"
4490 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4492 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4493 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4495 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4499 [(set (match_operand 0 "register_operand" "")
4501 6 "cris_commutative_orth_op"
4503 (mult:SI (match_operand:SI 2 "register_operand" "")
4504 (match_operand:SI 3 "const_int_operand" ""))
4505 (match_operand:SI 4 "register_operand" "")))
4506 (match_operand 1 "register_operand" "")]))
4507 (set (match_operand:SI 5 "register_operand" "")
4508 (plus:SI (mult:SI (match_dup 2)
4511 "REG_P (operands[4])
4512 && REG_P (operands[5])
4513 && REGNO (operands[5]) == REGNO (operands[4])"
4514 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4516 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4517 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4519 ;; op.S1 [rx=rx+i],ry (swapped)
4523 [(set (match_operand 0 "register_operand" "")
4525 5 "cris_commutative_orth_op"
4527 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4528 (match_operand:SI 3 "cris_bdap_operand" "")))
4529 (match_operand 1 "register_operand" "")]))
4530 (set (match_operand:SI 4 "register_operand" "")
4531 (plus:SI (match_dup 2)
4533 "(rtx_equal_p (operands[4], operands[2])
4534 || rtx_equal_p (operands[4], operands[3]))"
4535 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4536 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4537 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4539 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4543 [(set (match_operand 0 "register_operand" "")
4545 6 "cris_operand_extend_operator"
4546 [(match_operand 1 "register_operand" "")
4548 7 "cris_extend_operator"
4550 (mult:SI (match_operand:SI 2 "register_operand" "")
4551 (match_operand:SI 3 "const_int_operand" ""))
4552 (match_operand:SI 4 "register_operand" "")))])]))
4553 (set (match_operand:SI 5 "register_operand" "")
4554 (plus:SI (mult:SI (match_dup 2)
4557 "REG_P (operands[4])
4558 && REG_P (operands[5])
4559 && REGNO (operands[5]) == REGNO (operands[4])"
4560 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4562 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4563 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4564 replace_equiv_address (XEXP (operands[7], 0),
4567 ;; op(s|u).S1 [rx=rx+i],ry
4571 [(set (match_operand 0 "register_operand" "")
4573 5 "cris_operand_extend_operator"
4574 [(match_operand 1 "register_operand" "")
4576 6 "cris_extend_operator"
4578 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4579 (match_operand:SI 3 "cris_bdap_operand" "")
4581 (set (match_operand:SI 4 "register_operand" "")
4582 (plus:SI (match_dup 2)
4584 "(rtx_equal_p (operands[4], operands[2])
4585 || rtx_equal_p (operands[4], operands[3]))"
4586 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4587 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4588 "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4589 replace_equiv_address (XEXP (operands[6], 0),
4592 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4596 [(set (match_operand 0 "register_operand" "")
4598 7 "cris_plus_or_bound_operator"
4600 6 "cris_extend_operator"
4602 (mult:SI (match_operand:SI 2 "register_operand" "")
4603 (match_operand:SI 3 "const_int_operand" ""))
4604 (match_operand:SI 4 "register_operand" "")))])
4605 (match_operand 1 "register_operand" "")]))
4606 (set (match_operand:SI 5 "register_operand" "")
4607 (plus:SI (mult:SI (match_dup 2)
4610 "REG_P (operands[4]) && REG_P (operands[5])
4611 && REGNO (operands[5]) == REGNO (operands[4])"
4612 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4614 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4615 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4616 replace_equiv_address (XEXP (operands[6], 0),
4619 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4623 [(set (match_operand 0 "register_operand" "")
4625 6 "cris_plus_or_bound_operator"
4627 5 "cris_extend_operator"
4629 (match_operand:SI 2 "cris_bdap_operand" "")
4630 (match_operand:SI 3 "cris_bdap_operand" "")))])
4631 (match_operand 1 "register_operand" "")]))
4632 (set (match_operand:SI 4 "register_operand" "")
4633 (plus:SI (match_dup 2)
4635 "(rtx_equal_p (operands[4], operands[2])
4636 || rtx_equal_p (operands[4], operands[3]))"
4637 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4638 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4639 "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4640 replace_equiv_address (XEXP (operands[5], 0),
4643 ;; Splits for addressing prefixes that have no side-effects, so we can
4644 ;; fill a delay slot. Never split if we lose something, though.
4647 ;; move [indirect_ref],rx
4648 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4649 ;; move indirect_ref,rx
4651 ;; Take care not to allow indirect_ref = register.
4653 ;; We're not allowed to generate copies of registers with different mode
4654 ;; until after reload; copying pseudos upsets reload. CVS as of
4655 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4656 ;; cselib_invalidate_regno.
4659 [(set (match_operand 0 "register_operand" "")
4660 (match_operand 1 "indirect_operand" ""))]
4662 && REG_P (operands[0])
4663 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4664 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4665 || CONSTANT_P (XEXP (operands[1], 0)))"
4666 [(set (match_dup 2) (match_dup 4))
4667 (set (match_dup 0) (match_dup 3))]
4668 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4669 operands[3] = replace_equiv_address (operands[1], operands[2]);
4670 operands[4] = XEXP (operands[1], 0);")
4672 ;; As the above, but MOVS and MOVU.
4675 [(set (match_operand 0 "register_operand" "")
4677 4 "cris_extend_operator"
4678 [(match_operand 1 "indirect_operand" "")]))]
4680 && REG_P (operands[0])
4681 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4682 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4683 || CONSTANT_P (XEXP (operands[1], 0)))"
4684 [(set (match_dup 2) (match_dup 5))
4685 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4686 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4687 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4688 operands[5] = XEXP (operands[1], 0);")
4690 ;; Various peephole optimizations.
4692 ;; Watch out: when you exchange one set of instructions for another, the
4693 ;; condition codes setting must be the same, or you have to CC_INIT or
4694 ;; whatever is appropriate, in the pattern before you emit the
4695 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4696 ;; to keep changes local to their cause.
4698 ;; Do not add patterns that you do not know will be matched.
4699 ;; Please also add a self-contained testcase.
4701 ;; We have trouble with and:s and shifts. Maybe something is broken in
4702 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4703 ;; suboptimal when not having extzv insns.
4704 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4706 (define_peephole2 ; asrandb (peephole casesi+31)
4707 [(set (match_operand:SI 0 "register_operand" "")
4708 (ashiftrt:SI (match_dup 0)
4709 (match_operand:SI 1 "const_int_operand" "")))
4711 (and:SI (match_dup 0)
4712 (match_operand 2 "const_int_operand" "")))]
4713 "INTVAL (operands[2]) > 31
4714 && INTVAL (operands[2]) < 255
4715 && INTVAL (operands[1]) > 23
4716 /* Check that the and-operation enables us to use logical-shift. */
4717 && (INTVAL (operands[2])
4718 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4719 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4720 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4721 ;; FIXME: CC0 is valid except for the M bit.
4723 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4724 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4727 (define_peephole2 ; asrandw (peephole casesi+32)
4728 [(set (match_operand:SI 0 "register_operand" "")
4729 (ashiftrt:SI (match_dup 0)
4730 (match_operand:SI 1 "const_int_operand" "")))
4732 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4733 "INTVAL (operands[2]) > 31
4734 && INTVAL (operands[2]) < 65535
4735 && INTVAL (operands[2]) != 255
4736 && INTVAL (operands[1]) > 15
4737 /* Check that the and-operation enables us to use logical-shift. */
4738 && (INTVAL (operands[2])
4739 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4740 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4741 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4742 ;; FIXME: CC0 is valid except for the M bit.
4744 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4745 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4748 (define_peephole2 ; lsrandb (peephole casesi+33)
4749 [(set (match_operand:SI 0 "register_operand" "")
4750 (lshiftrt:SI (match_dup 0)
4751 (match_operand:SI 1 "const_int_operand" "")))
4753 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4754 "INTVAL (operands[2]) > 31
4755 && INTVAL (operands[2]) < 255
4756 && INTVAL (operands[1]) > 23"
4757 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4758 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4759 ;; FIXME: CC0 is valid except for the M bit.
4761 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4762 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4765 (define_peephole2 ; lsrandw (peephole casesi+34)
4766 [(set (match_operand:SI 0 "register_operand" "")
4767 (lshiftrt:SI (match_dup 0)
4768 (match_operand:SI 1 "const_int_operand" "")))
4770 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4771 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4772 && INTVAL (operands[2]) != 255
4773 && INTVAL (operands[1]) > 15"
4774 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4775 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4776 ;; FIXME: CC0 is valid except for the M bit.
4778 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4779 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4787 ;; move [rx=rx+n],ry
4788 ;; when -128 <= n <= 127.
4789 ;; This will reduce the size of the assembler code for n = [-128..127],
4790 ;; and speed up accordingly. Don't match if the previous insn is
4791 ;; (set rx rz) because that combination is matched by another peephole.
4792 ;; No stable test-case.
4794 (define_peephole2 ; moversideqi (peephole casesi+35)
4795 [(set (match_operand:SI 0 "register_operand" "")
4796 (plus:SI (match_operand:SI 1 "register_operand" "")
4797 (match_operand:SI 2 "const_int_operand" "")))
4798 (set (match_operand 3 "register_operand" "")
4799 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4800 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4801 && REGNO (operands[3]) != REGNO (operands[0])
4802 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4803 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4804 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4805 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4807 [(set (match_dup 3) (match_dup 5))
4808 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4809 ;; Checking the previous insn is a bit too awkward for the condition.
4811 rtx prev = prev_nonnote_insn (curr_insn);
4812 if (prev != NULL_RTX)
4814 rtx set = single_set (prev);
4816 && REG_S_P (SET_DEST (set))
4817 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4818 && REG_S_P (SET_SRC (set)))
4822 = replace_equiv_address (operands[4],
4823 gen_rtx_PLUS (SImode,
4824 operands[1], operands[2]));
4827 ;; Vice versa: move ry,[rx=rx+n]
4829 (define_peephole2 ; movemsideqi (peephole casesi+36)
4830 [(set (match_operand:SI 0 "register_operand" "")
4831 (plus:SI (match_operand:SI 1 "register_operand" "")
4832 (match_operand:SI 2 "const_int_operand" "")))
4833 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4834 (match_operand 4 "register_operand" ""))]
4835 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4836 && REGNO (operands[4]) != REGNO (operands[0])
4837 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4838 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4839 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4840 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4842 [(set (match_dup 5) (match_dup 4))
4843 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4845 = replace_equiv_address (operands[3],
4846 gen_rtx_PLUS (SImode,
4847 operands[1], operands[2]));")
4849 ;; As above, change:
4853 ;; op.d [rx=rx+n],ry
4854 ;; Saves when n = [-128..127].
4856 ;; Splitting and joining combinations for side-effect modes are slightly
4857 ;; out of hand. They probably will not save the time they take typing in,
4858 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4859 ;; the splits and peepholes as possible.
4860 ;; No stable test-case.
4862 (define_peephole2 ; mover2side (peephole casesi+37)
4863 [(set (match_operand:SI 0 "register_operand" "")
4864 (plus:SI (match_operand:SI 1 "register_operand" "")
4865 (match_operand:SI 2 "const_int_operand" "")))
4866 (set (match_operand 3 "register_operand" "")
4867 (match_operator 4 "cris_orthogonal_operator"
4870 5 "cris_mem_op" [(match_dup 0)])]))]
4871 "GET_MODE (operands[3]) != DImode
4872 && REGNO (operands[0]) != REGNO (operands[3])
4873 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4874 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4875 && INTVAL (operands[2]) >= -128
4876 && INTVAL (operands[2]) <= 127"
4878 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4879 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4881 = replace_equiv_address (operands[5],
4882 gen_rtx_PLUS (SImode,
4883 operands[1], operands[2]));")
4885 ;; Sometimes, for some reason the pattern
4889 ;; will occur. Solve this, and likewise for to-memory.
4890 ;; No stable test-case.
4892 (define_peephole2 ; moverside (peephole casesi+38)
4893 [(set (match_operand:SI 0 "register_operand" "")
4894 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4896 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4897 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4898 (set (match_operand 4 "register_operand" "")
4899 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4900 "(rtx_equal_p (operands[2], operands[0])
4901 || rtx_equal_p (operands[3], operands[0]))
4902 && cris_side_effect_mode_ok (PLUS, operands, 0,
4903 (REG_S_P (operands[1])
4905 : (rtx_equal_p (operands[2], operands[0])
4907 (! REG_S_P (operands[1])
4909 : (rtx_equal_p (operands[2], operands[0])
4913 [(set (match_dup 4) (match_dup 6))
4914 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4917 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4919 /* Make sure we have canonical RTX so we match the insn pattern -
4920 not a constant in the first operand. We also require the order
4921 (plus reg mem) to match the final pattern. */
4922 if (CONSTANT_P (otherop) || MEM_P (otherop))
4924 operands[7] = operands[1];
4925 operands[8] = otherop;
4929 operands[7] = otherop;
4930 operands[8] = operands[1];
4933 = replace_equiv_address (operands[5],
4934 gen_rtx_PLUS (SImode,
4935 operands[7], operands[8]));
4938 ;; As above but to memory.
4939 ;; FIXME: Split movemside and moverside into variants and prune
4940 ;; the ones that don't trig.
4941 ;; No stable test-case.
4943 (define_peephole2 ; movemside (peephole casesi+39)
4944 [(set (match_operand:SI 0 "register_operand" "")
4945 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4947 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4948 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4949 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4950 (match_operand 5 "register_operand" ""))]
4951 "(rtx_equal_p (operands[2], operands[0])
4952 || rtx_equal_p (operands[3], operands[0]))
4953 && cris_side_effect_mode_ok (PLUS, operands, 0,
4954 (REG_S_P (operands[1])
4956 : (rtx_equal_p (operands[2], operands[0])
4958 (! REG_S_P (operands[1])
4960 : (rtx_equal_p (operands[2], operands[0])
4964 [(set (match_dup 6) (match_dup 5))
4965 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4968 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4970 /* Make sure we have canonical RTX so we match the insn pattern -
4971 not a constant in the first operand. We also require the order
4972 (plus reg mem) to match the final pattern. */
4973 if (CONSTANT_P (otherop) || MEM_P (otherop))
4975 operands[7] = operands[1];
4976 operands[8] = otherop;
4980 operands[7] = otherop;
4981 operands[8] = operands[1];
4984 = replace_equiv_address (operands[4],
4985 gen_rtx_PLUS (SImode,
4986 operands[7], operands[8]));
4989 ;; Another spotted bad code:
4992 ;; No stable test-case.
4994 (define_peephole2 ; movei (peephole casesi+42)
4995 [(set (match_operand:SI 0 "register_operand" "")
4996 (match_operand:SI 1 "register_operand" ""))
4997 (set (match_operand 2 "register_operand" "")
4998 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4999 "REGNO (operands[0]) == REGNO (operands[2])
5000 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
5001 [(set (match_dup 2) (match_dup 4))]
5002 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
5004 ;; move.d [r10+16],r9
5007 ;; and.d [r10+16],r12,r9
5008 ;; With generalization of the operation, the size and the addressing mode.
5009 ;; This seems to be the result of a quirk in register allocation
5010 ;; missing the three-operand cases when having different predicates.
5011 ;; Maybe that it matters that it is a commutative operation.
5012 ;; This pattern helps that situation, but there's still the increased
5013 ;; register pressure.
5014 ;; Note that adding the noncommutative variant did not show any matches
5015 ;; in ipps and cc1, so it's not here.
5016 ;; No stable test-case.
5018 (define_peephole2 ; op3 (peephole casesi+44)
5019 [(set (match_operand 0 "register_operand" "")
5023 (match_operand:SI 1 "cris_bdap_biap_operand" "")
5024 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
5027 5 "cris_commutative_orth_op"
5028 [(match_operand 3 "register_operand" "")
5029 (match_operand 4 "register_operand" "")]))]
5030 "(rtx_equal_p (operands[3], operands[0])
5031 || rtx_equal_p (operands[4], operands[0]))
5032 && ! rtx_equal_p (operands[3], operands[4])
5033 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
5034 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
5035 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
5037 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
5039 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
5041 ;; and.b some_byte,const,reg_32
5042 ;; where reg_32 is the destination of the "three-address" code optimally.
5044 ;; movu.b some_byte,reg_32
5045 ;; and.b const,reg_32
5046 ;; but is turns into:
5047 ;; move.b some_byte,reg_32
5048 ;; and.d const,reg_32
5050 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
5052 (define_peephole2 ; andu (casesi+45)
5053 [(set (match_operand:SI 0 "register_operand" "")
5054 (match_operand:SI 1 "nonimmediate_operand" ""))
5055 (set (match_operand:SI 2 "register_operand" "")
5056 (and:SI (match_dup 0)
5057 (match_operand:SI 3 "const_int_operand" "")))]
5058 ;; Since the size of the memory access could be made different here,
5059 ;; don't do this for a mem-volatile access.
5060 "REGNO (operands[2]) == REGNO (operands[0])
5061 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
5062 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
5063 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
5064 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
5065 [(set (match_dup 0) (match_dup 4))
5066 (set (match_dup 5) (match_dup 6))]
5068 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
5069 enum machine_mode amode
5070 = CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
5072 = (REG_S_P (operands[1])
5073 ? gen_rtx_REG (zmode, REGNO (operands[1]))
5074 : adjust_address (operands[1], zmode, 0));
5076 = gen_rtx_ZERO_EXTEND (SImode, op1);
5077 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
5079 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
5080 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
5082 ? QImode : amode)));
5087 ;; comment-start: ";; "
5088 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5089 ;; eval: (modify-syntax-entry ?[ "(]")
5090 ;; eval: (modify-syntax-entry ?] ")[")
5091 ;; eval: (modify-syntax-entry ?{ "(}")
5092 ;; eval: (modify-syntax-entry ?} "){")
5093 ;; eval: (setq indent-tabs-mode t)