1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Axis Communications.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and problably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed in egcs post 1.1.1, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
58 ;; 0 PLT reference from call expansion: operand 0 is the address,
59 ;; the mode is VOIDmode. Always wrapped in CONST.
61 ;; We need an attribute to define whether an instruction can be put in
62 ;; a branch-delay slot or not, and whether it has a delay slot.
64 ;; Branches and return instructions have a delay slot, and cannot
65 ;; themselves be put in a delay slot. This has changed *for short
66 ;; branches only* between architecture variants, but the possible win
67 ;; is presumed negligible compared to the added complexity of the machine
68 ;; description: one would have to add always-correct infrastructure to
69 ;; distinguish short branches.
71 ;; Whether an instruction can be put in a delay slot depends on the
72 ;; instruction (all short instructions except jumps and branches)
73 ;; and the addressing mode (must not be prefixed or referring to pc).
74 ;; In short, any "slottable" instruction must be 16 bit and not refer
75 ;; to pc, or alter it.
77 ;; The possible values are "yes", "no" and "has_slot". Yes/no means if
78 ;; the insn is slottable or not. Has_slot means that the insn is a
79 ;; return insn or branch insn (which are not considered slottable since
80 ;; that is generally true). Having the semmingly illogical value
81 ;; "has_slot" means we do not have to add another attribute just to say
82 ;; that an insn has a delay-slot, since it also infers that it is not
83 ;; slottable. Better names for the attribute were found to be longer and
84 ;; not add readability to the machine description.
86 ;; The default that is defined here for this attribute is "no", not
87 ;; slottable, not having a delay-slot, so there's no need to worry about
88 ;; it being wrong for non-branch and return instructions.
89 ;; The default could depend on the kind of insn and the addressing
90 ;; mode, but that would need more attributes and hairier, more error
93 ;; There is an extra constraint, 'Q', which recognizes indirect reg,
94 ;; except when the reg is pc. The constraints 'Q' and '>' together match
95 ;; all possible memory operands that are slottable.
96 ;; For other operands, you need to check if it has a valid "slottable"
97 ;; quick-immediate operand, where the particular signedness-variation
98 ;; may match the constraints 'I' or 'J'.), and include it in the
99 ;; constraint pattern for the slottable pattern. An alternative using
100 ;; only "r" constraints is most often slottable.
102 (define_attr "slottable" "no,yes,has_slot" (const_string "no"))
104 ;; We also need attributes to sanely determine the condition code
105 ;; state. See cris_notice_update_cc for how this is used.
107 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
109 ;; A branch or return has one delay-slot. The instruction in the
110 ;; delay-slot is always executed, independent of whether the branch is
111 ;; taken or not. Note that besides setting "slottable" to "has_slot",
112 ;; there also has to be a "%#" at the end of a "delayed" instruction
113 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
114 ;; catch it and print a "nop" if necessary. This method was stolen from
117 (define_delay (eq_attr "slottable" "has_slot")
118 [(eq_attr "slottable" "yes") (nil) (nil)])
124 ;; Allow register and offsettable mem operands only; post-increment is
125 ;; not worth the trouble.
129 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
131 "test.d %M0\;ax\;test.d %H0")
133 ;; No test insns with side-effect on the mem addressing.
135 ;; See note on cmp-insns with side-effects (or lack of them)
137 ;; Normal named test patterns from SI on.
138 ;; FIXME: Seems they should change to be in order smallest..largest.
142 (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))]
145 [(set_attr "slottable" "yes,yes,no")])
149 (match_operand:HI 0 "nonimmediate_operand" "r,Q>,m"))]
152 [(set_attr "slottable" "yes,yes,no")])
156 (match_operand:QI 0 "nonimmediate_operand" "r,Q>,m"))]
159 [(set_attr "slottable" "yes,yes,no")])
161 ;; It seems that the position of the sign-bit and the fact that 0.0 is
162 ;; all 0-bits would make "tstsf" a straight-forward implementation;
163 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
166 ;; FIXME: Do that some time; check next_cc0_user to determine if
167 ;; zero or negative is tested for.
171 ;; We could optimize the sizes of the immediate operands for various
172 ;; cases, but that is not worth it because of the very little usage of
173 ;; DImode for anything else but a structure/block-mode. Just do the
174 ;; obvious stuff for the straight-forward constraint letters.
178 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
179 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
182 cmpq %1,%M0\;ax\;cmpq 0,%H0
183 cmpq %1,%M0\;ax\;cmpq -1,%H0
184 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
185 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
186 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
187 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
188 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
190 ;; Note that compare insns with side effect addressing mode (e.g.):
192 ;; cmp.S [rx=ry+i],rz;
193 ;; cmp.S [%3=%1+%2],%0
195 ;; are *not* usable for gcc since the reloader *does not accept*
196 ;; cc0-changing insns with side-effects other than setting the condition
197 ;; codes. The reason is that the reload stage *may* cause another insn to
198 ;; be output after the main instruction, in turn invalidating cc0 for the
199 ;; insn using the test. (This does not apply to the CRIS case, since a
200 ;; reload for output -- move to memory -- does not change the condition
201 ;; code. Unfortunately we have no way to describe that at the moment. I
202 ;; think code would improve being in the order of one percent faster.
204 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
205 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
206 ;; constants, but sometimes gcc will find its way to use it for other
207 ;; (memory) operands. Avoid side-effect patterns, though (see above).
209 ;; FIXME: These could have an anonymous mode for operand 1.
213 (define_insn "*cmp_extsi"
216 (match_operand:SI 0 "register_operand" "r,r")
217 (match_operator:SI 2 "cris_extend_operator"
218 [(match_operand:QI 1 "memory_operand" "Q>,m")])))]
221 [(set_attr "slottable" "yes,no")])
224 (define_insn "*cmp_exthi"
227 (match_operand:SI 0 "register_operand" "r,r")
228 (match_operator:SI 2 "cris_extend_operator"
229 [(match_operand:HI 1 "memory_operand" "Q>,m")])))]
232 [(set_attr "slottable" "yes,no")])
234 ;; Swap operands; it seems the canonical look (if any) is not enforced.
236 ;; FIXME: Investigate that.
237 ;; FIXME: These could have an anonymous mode for operand 1.
241 (define_insn "*cmp_swapextqi"
244 (match_operator:SI 2 "cris_extend_operator"
245 [(match_operand:QI 0 "memory_operand" "Q>,m")])
246 (match_operand:SI 1 "register_operand" "r,r")))]
248 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
249 ; swapped operands to compares.
250 [(set_attr "slottable" "yes,no")])
254 (define_insn "*cmp_swapexthi"
257 (match_operator:SI 2 "cris_extend_operator"
258 [(match_operand:HI 0 "memory_operand" "Q>,m")])
259 (match_operand:SI 1 "register_operand" "r,r")))]
261 "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about
262 ; swapped operands to compares.
263 [(set_attr "slottable" "yes,no")])
265 ;; The "normal" compare patterns, from SI on.
270 (match_operand:SI 0 "nonimmediate_operand" "r,r,r,r,Q>,Q>,r,r,m,m")
271 (match_operand:SI 1 "general_operand" "I,r,Q>,M,M,r,P,g,M,r")))]
284 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])
288 (compare (match_operand:HI 0 "nonimmediate_operand" "r,r,Q>,Q>,r,m,m")
289 (match_operand:HI 1 "general_operand" "r,Q>,M,r,g,M,r")))]
299 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
304 (match_operand:QI 0 "nonimmediate_operand" "r,r,r,Q>,Q>,r,m,m")
305 (match_operand:QI 1 "general_operand" "r,Q>,M,M,r,g,M,r")))]
316 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
318 ;; Pattern matching the BTST insn.
319 ;; It is useful for "if (i & val)" constructs, where val is an exact
320 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
321 ;; of zeros starting at bit 0).
323 ;; SImode. This mode is the only one needed, since gcc automatically
324 ;; extends subregs for lower-size modes. FIXME: Add test-case.
328 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
329 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
330 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
331 ;; Either it is a single bit, or consecutive ones starting at 0.
332 "GET_CODE (operands[1]) == CONST_INT
333 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
334 && (REG_S_P (operands[0])
335 || (operands[1] == const1_rtx
336 && REG_S_P (operands[2])
337 && GET_CODE (operands[0]) == CONST_INT
338 && exact_log2 (INTVAL (operands[0])) >= 0))"
340 ;; The last "&&" condition above should be caught by some kind of
341 ;; canonicalization in gcc, but we can easily help with it here.
342 ;; It results from expressions of the type
343 ;; "power_of_2_value & (1 << y)".
345 ;; Since there may be codes with tests in on bits (in constant position)
346 ;; beyond the size of a word, handle that by assuming those bits are 0.
347 ;; GCC should handle that, but it's a matter of easily-added belts while
348 ;; having suspenders.
358 [(set_attr "slottable" "yes")])
362 ;; The whole mandatory movdi family is here; expander, "anonymous"
363 ;; recognizer and splitter. We're forced to have a movdi pattern,
364 ;; although GCC should be able to split it up itself. Normally it can,
365 ;; but if other insns have DI operands (as is the case here), reload
366 ;; must be able to generate or match a movdi. many testcases fail at
367 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
368 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
369 ;; However, a patch from Richard Kenner (similar to the cause of
370 ;; discussion at the URL above), indicates otherwise. See
371 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
372 ;; The truth has IMO is not been decided yet, so check from time to
373 ;; time by disabling the movdi patterns.
375 (define_expand "movdi"
376 [(set (match_operand:DI 0 "nonimmediate_operand" "")
377 (match_operand:DI 1 "general_operand" ""))]
381 if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
382 operands[1] = copy_to_mode_reg (DImode, operands[1]);
384 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
385 prefer to split up constants early, like this. The testcase in
386 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
387 resulting subreg sets when using the construct from mcore (as of FSF
388 CVS, version -r 1.5), and it believes that the high part (the last one
389 emitted) is the final value. This construct from romp seems more
390 robust, especially considering the head comments from
391 emit_no_conflict_block. */
392 if ((GET_CODE (operands[1]) == CONST_INT
393 || GET_CODE (operands[1]) == CONST_DOUBLE)
394 && ! reload_completed
395 && ! reload_in_progress)
398 rtx op0 = operands[0];
399 rtx op1 = operands[1];
402 emit_move_insn (operand_subword (op0, 0, 1, DImode),
403 operand_subword (op1, 0, 1, DImode));
404 emit_move_insn (operand_subword (op0, 1, 1, DImode),
405 operand_subword (op1, 1, 1, DImode));
406 insns = get_insns ();
409 emit_no_conflict_block (insns, op0, op1, 0, op1);
414 (define_insn "*movdi_insn"
415 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
416 (match_operand:DI 1 "general_operand" "r,g,rM"))]
417 "register_operand (operands[0], DImode)
418 || register_operand (operands[1], DImode)
419 || operands[1] == const0_rtx"
423 [(set (match_operand:DI 0 "nonimmediate_operand" "")
424 (match_operand:DI 1 "general_operand" ""))]
427 "operands[2] = cris_split_movdx (operands);")
429 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
430 ;; and move.S1 [rx=ry+i],rz
431 ;; Then movs.S1 and movu.S1 for both modes.
433 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
434 ;; FIXME: These could have anonymous mode for operand 0.
438 (define_insn "*mov_sideqi_biap"
439 [(set (match_operand:QI 0 "register_operand" "=r,r")
441 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
442 (match_operand:SI 2 "const_int_operand" "n,n"))
443 (match_operand:SI 3 "register_operand" "r,r"))))
444 (set (match_operand:SI 4 "register_operand" "=*3,r")
445 (plus:SI (mult:SI (match_dup 1)
448 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
451 move.%s0 [%4=%3+%1%T2],%0")
455 (define_insn "*mov_sidehi_biap"
456 [(set (match_operand:HI 0 "register_operand" "=r,r")
458 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
459 (match_operand:SI 2 "const_int_operand" "n,n"))
460 (match_operand:SI 3 "register_operand" "r,r"))))
461 (set (match_operand:SI 4 "register_operand" "=*3,r")
462 (plus:SI (mult:SI (match_dup 1)
465 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
468 move.%s0 [%4=%3+%1%T2],%0")
472 (define_insn "*mov_sidesi_biap"
473 [(set (match_operand:SI 0 "register_operand" "=r,r")
475 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
476 (match_operand:SI 2 "const_int_operand" "n,n"))
477 (match_operand:SI 3 "register_operand" "r,r"))))
478 (set (match_operand:SI 4 "register_operand" "=*3,r")
479 (plus:SI (mult:SI (match_dup 1)
482 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
485 move.%s0 [%4=%3+%1%T2],%0")
487 ;; move.S1 [rx=ry+i],rz
488 ;; avoiding move.S1 [ry=ry+i],rz
489 ;; and move.S1 [rz=ry+i],rz
490 ;; Note that "i" is allowed to be a register.
491 ;; FIXME: These could have anonymous mode for operand 0.
495 (define_insn "*mov_sideqi"
496 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
498 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
499 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri"))))
500 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
501 (plus:SI (match_dup 1)
503 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
506 if (which_alternative == 0
507 && (GET_CODE (operands[2]) != CONST_INT
508 || INTVAL (operands[2]) > 127
509 || INTVAL (operands[2]) < -128
510 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
511 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
513 return \"move.%s0 [%3=%1%S2],%0\";
518 (define_insn "*mov_sidehi"
519 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
521 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
522 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri"))))
523 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
524 (plus:SI (match_dup 1)
526 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
529 if (which_alternative == 0
530 && (GET_CODE (operands[2]) != CONST_INT
531 || INTVAL (operands[2]) > 127
532 || INTVAL (operands[2]) < -128
533 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
534 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
536 return \"move.%s0 [%3=%1%S2],%0\";
541 (define_insn "*mov_sidesi"
542 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
544 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
545 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri"))))
546 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
547 (plus:SI (match_dup 1)
549 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
552 if (which_alternative == 0
553 && (GET_CODE (operands[2]) != CONST_INT
554 || INTVAL (operands[2]) > 127
555 || INTVAL (operands[2]) < -128
556 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
557 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
559 return \"move.%s0 [%3=%1%S2],%0\";
562 ;; Other way around; move to memory.
564 ;; Note that the condition (which for side-effect patterns is usually a
565 ;; call to cris_side_effect_mode_ok), isn't consulted for register
566 ;; allocation preferences -- constraints is the method for that. The
567 ;; drawback is that we can't exclude register allocation to cause
568 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
569 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
570 ;; Instead of that, we recognize and split the cases where dangerous
571 ;; register combinations are spotted: where a register is set in the
572 ;; side-effect, and used in the main insn. We don't handle the case where
573 ;; the set in the main insn overlaps the set in the side-effect; that case
574 ;; must be handled in gcc. We handle just the case where the set in the
575 ;; side-effect overlaps the input operand of the main insn (i.e. just
579 ;; move.s rz,[ry=rx+rw.S]
580 ;; FIXME: These could have anonymous mode for operand 3.
584 (define_insn "*mov_sideqi_biap_mem"
585 [(set (mem:QI (plus:SI
586 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
587 (match_operand:SI 1 "const_int_operand" "n,n,n"))
588 (match_operand:SI 2 "register_operand" "r,r,r")))
589 (match_operand:QI 3 "register_operand" "r,r,r"))
590 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
591 (plus:SI (mult:SI (match_dup 0)
594 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
598 move.%s3 %3,[%4=%2+%0%T1]")
602 (define_insn "*mov_sidehi_biap_mem"
603 [(set (mem:HI (plus:SI
604 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
605 (match_operand:SI 1 "const_int_operand" "n,n,n"))
606 (match_operand:SI 2 "register_operand" "r,r,r")))
607 (match_operand:HI 3 "register_operand" "r,r,r"))
608 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
609 (plus:SI (mult:SI (match_dup 0)
612 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
616 move.%s3 %3,[%4=%2+%0%T1]")
620 (define_insn "*mov_sidesi_biap_mem"
621 [(set (mem:SI (plus:SI
622 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
623 (match_operand:SI 1 "const_int_operand" "n,n,n"))
624 (match_operand:SI 2 "register_operand" "r,r,r")))
625 (match_operand:SI 3 "register_operand" "r,r,r"))
626 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
627 (plus:SI (mult:SI (match_dup 0)
630 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
634 move.%s3 %3,[%4=%2+%0%T1]")
636 ;; Split for the case above where we're out of luck with register
637 ;; allocation (again, the condition isn't checked for that), and we end up
638 ;; with the set in the side-effect getting the same register as the input
644 (mult:SI (match_operand:SI 0 "register_operand" "")
645 (match_operand:SI 1 "const_int_operand" ""))
646 (match_operand:SI 2 "register_operand" "")))
647 (match_operand 3 "register_operand" ""))
648 (set (match_operand:SI 4 "register_operand" "")
649 (plus:SI (mult:SI (match_dup 0)
652 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
653 [(set (match_dup 5) (match_dup 3))
654 (set (match_dup 4) (match_dup 2))
656 (plus:SI (mult:SI (match_dup 0)
660 = gen_rtx_MEM (GET_MODE (operands[3]),
661 gen_rtx_PLUS (SImode,
662 gen_rtx_MULT (SImode,
663 operands[0], operands[1]),
666 ;; move.s rx,[ry=rz+i]
667 ;; FIXME: These could have anonymous mode for operand 2.
671 (define_insn "*mov_sideqi_mem"
673 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
674 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r>Ri,r,>Ri")))
675 (match_operand:QI 2 "register_operand" "r,r,r,r"))
676 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
677 (plus:SI (match_dup 0)
679 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
682 if (which_alternative == 0
683 && (GET_CODE (operands[1]) != CONST_INT
684 || INTVAL (operands[1]) > 127
685 || INTVAL (operands[1]) < -128
686 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
687 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
689 if (which_alternative == 1)
691 return \"move.%s2 %2,[%3=%0%S1]\";
696 (define_insn "*mov_sidehi_mem"
698 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
699 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r>Ri,r,>Ri")))
700 (match_operand:HI 2 "register_operand" "r,r,r,r"))
701 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
702 (plus:SI (match_dup 0)
704 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
707 if (which_alternative == 0
708 && (GET_CODE (operands[1]) != CONST_INT
709 || INTVAL (operands[1]) > 127
710 || INTVAL (operands[1]) < -128
711 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
712 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
714 if (which_alternative == 1)
716 return \"move.%s2 %2,[%3=%0%S1]\";
721 (define_insn "*mov_sidesi_mem"
723 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
724 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r>Ri,r,>Ri")))
725 (match_operand:SI 2 "register_operand" "r,r,r,r"))
726 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
727 (plus:SI (match_dup 0)
729 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
732 if (which_alternative == 0
733 && (GET_CODE (operands[1]) != CONST_INT
734 || INTVAL (operands[1]) > 127
735 || INTVAL (operands[1]) < -128
736 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
737 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
739 if (which_alternative == 1)
741 return \"move.%s2 %2,[%3=%0%S1]\";
744 ;; Like the biap case, a split where the set in the side-effect gets the
745 ;; same register as the input register to the main insn, since the
746 ;; condition isn't checked at register allocation.
751 (match_operand:SI 0 "cris_bdap_operand" "")
752 (match_operand:SI 1 "cris_bdap_operand" "")))
753 (match_operand 2 "register_operand" ""))
754 (set (match_operand:SI 3 "register_operand" "")
755 (plus:SI (match_dup 0) (match_dup 1)))])]
756 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
757 [(set (match_dup 4) (match_dup 2))
758 (set (match_dup 3) (match_dup 0))
759 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
761 = gen_rtx_MEM (GET_MODE (operands[2]),
762 gen_rtx_PLUS (SImode, operands[0], operands[1]));")
764 ;; Clear memory side-effect patterns. It is hard to get to the mode if
765 ;; the MEM was anonymous, so there will be one for each mode.
767 ;; clear.d [ry=rx+rw.s2]
769 (define_insn "*clear_sidesi_biap"
770 [(set (mem:SI (plus:SI
771 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
772 (match_operand:SI 1 "const_int_operand" "n,n"))
773 (match_operand:SI 2 "register_operand" "r,r")))
775 (set (match_operand:SI 3 "register_operand" "=*2,r")
776 (plus:SI (mult:SI (match_dup 0)
779 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
782 clear.d [%3=%2+%0%T1]")
786 (define_insn "*clear_sidesi"
788 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
789 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r,>Ri")))
791 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
792 (plus:SI (match_dup 0)
794 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
797 if (which_alternative == 0
798 && (GET_CODE (operands[1]) != CONST_INT
799 || INTVAL (operands[1]) > 127
800 || INTVAL (operands[1]) < -128
801 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
802 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
804 return \"clear.d [%2=%0%S1]\";
807 ;; clear.w [ry=rx+rw.s2]
809 (define_insn "*clear_sidehi_biap"
810 [(set (mem:HI (plus:SI
811 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
812 (match_operand:SI 1 "const_int_operand" "n,n"))
813 (match_operand:SI 2 "register_operand" "r,r")))
815 (set (match_operand:SI 3 "register_operand" "=*2,r")
816 (plus:SI (mult:SI (match_dup 0)
819 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
822 clear.w [%3=%2+%0%T1]")
826 (define_insn "*clear_sidehi"
828 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
829 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r,>Ri")))
831 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
832 (plus:SI (match_dup 0)
834 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
837 if (which_alternative == 0
838 && (GET_CODE (operands[1]) != CONST_INT
839 || INTVAL (operands[1]) > 127
840 || INTVAL (operands[1]) < -128
841 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
842 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
844 return \"clear.w [%2=%0%S1]\";
847 ;; clear.b [ry=rx+rw.s2]
849 (define_insn "*clear_sideqi_biap"
850 [(set (mem:QI (plus:SI
851 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
852 (match_operand:SI 1 "const_int_operand" "n,n"))
853 (match_operand:SI 2 "register_operand" "r,r")))
855 (set (match_operand:SI 3 "register_operand" "=*2,r")
856 (plus:SI (mult:SI (match_dup 0)
859 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
862 clear.b [%3=%2+%0%T1]")
866 (define_insn "*clear_sideqi"
868 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
869 (match_operand:SI 1 "cris_bdap_operand" "r>Ri,r,>Ri")))
871 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
872 (plus:SI (match_dup 0)
874 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
877 if (which_alternative == 0
878 && (GET_CODE (operands[1]) != CONST_INT
879 || INTVAL (operands[1]) > 127
880 || INTVAL (operands[1]) < -128
881 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
882 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
884 return \"clear.b [%2=%0%S1]\";
887 ;; To appease test-case gcc.c-torture/execute/920501-2.c (and others) at
888 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
889 ;; A cmpdi RTX needs reloading (global):
890 ;; (insn 185 326 186 (set (cc0)
891 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
892 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
894 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
895 ;; out of the instruction (into a register), since one of the operands
896 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
897 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
898 ;; wrt. overlap). The bad things happen with the synthesis in
899 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
900 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
901 ;; 22 is recognized to have an equivalent in memory which is substituted
902 ;; straight in, and we end up with an unrecognizable insn:
903 ;; (insn 325 324 326 (set (reg:SI 9 r9)
904 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
905 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
907 ;; which is the first part of the reloaded synthesized "movdi".
908 ;; The right thing would be to add equivalent replacement locations for
909 ;; insn with pseudos that need more reloading. The question is where.
911 ;; Normal move patterns from SI on.
913 (define_expand "movsi"
915 (match_operand:SI 0 "nonimmediate_operand" "")
916 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
920 /* If the output goes to a MEM, make sure we have zero or a register as
922 if (GET_CODE (operands[0]) == MEM
923 && ! REG_S_P (operands[1])
924 && operands[1] != const0_rtx
926 operands[1] = force_reg (SImode, operands[1]);
928 /* If we're generating PIC and have an incoming symbol, validize it to a
929 general operand or something that will match a special pattern.
931 FIXME: Do we *have* to recognize anything that would normally be a
932 valid symbol? Can we exclude global PIC addresses with an added
935 && CONSTANT_ADDRESS_P (operands[1])
936 && cris_symbol (operands[1]))
938 /* We must have a register as destination for what we're about to
939 do, and for the patterns we generate. */
940 if (! REG_S_P (operands[0]))
944 operands[1] = force_reg (SImode, operands[1]);
948 /* Mark a needed PIC setup for a LABEL_REF:s coming in here:
949 they are so rare not-being-branch-targets that we don't mark
950 a function as needing PIC setup just because we have
951 inspected LABEL_REF:s as operands. It is only in
952 __builtin_setjmp and such that we can get a LABEL_REF
953 assigned to a register. */
954 if (GET_CODE (operands[1]) == LABEL_REF)
955 current_function_uses_pic_offset_table = 1;
957 /* We don't have to do anything for global PIC operands; they
958 look just like ``[rPIC+sym]''. */
959 if (! cris_got_symbol (operands[1])
960 /* We don't do anything for local PIC operands; we match
961 that with a special alternative. */
962 && ! cris_gotless_symbol (operands[1]))
964 /* We get here when we have to change something that would
965 be recognizable if it wasn't PIC. A ``sym'' is ok for
966 PIC symbols both with and without a GOT entry. And ``sym
967 + offset'' is ok for local symbols, so the only thing it
968 could be, is a global symbol with an offset. Check and
970 rtx sym = get_related_value (operands[1]);
971 HOST_WIDE_INT offs = get_integer_term (operands[1]);
973 if (sym == NULL_RTX || offs == 0)
975 emit_move_insn (operands[0], sym);
976 if (expand_binop (SImode, add_optab, operands[0],
977 GEN_INT (offs), operands[0], 0,
978 OPTAB_LIB_WIDEN) != operands[0])
986 (define_insn "*movsi_internal"
988 (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,g,r,r,r,g")
990 ;; FIXME: We want to put S last, but apparently g matches S.
991 ;; It's a bug: an S is not a general_operand and shouldn't match g.
992 "cris_general_operand_or_gotless_symbol" "r,Q>,M,M,I,r,M,n,!S,g,r"))]
996 /* Better to have c-switch here; it is worth it to optimize the size of
997 move insns. The alternative would be to try to find more constraint
998 letters. FIXME: Check again. It seems this could shrink a bit. */
999 switch (which_alternative)
1006 return \"move.d %1,%0\";
1011 return \"clear.d %0\";
1013 /* Constants -32..31 except 0. */
1015 return \"moveq %1,%0\";
1017 /* We can win a little on constants -32768..-33, 32..65535. */
1019 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1021 if (INTVAL (operands[1]) < 256)
1022 return \"movu.b %1,%0\";
1023 return \"movu.w %1,%0\";
1025 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1027 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1028 return \"movs.b %1,%0\";
1029 return \"movs.w %1,%0\";
1031 return \"move.d %1,%0\";
1034 /* FIXME: Try and split this into pieces GCC makes better code of,
1035 than this multi-insn pattern. Synopsis: wrap the GOT-relative
1036 symbol into an unspec, and when PIC, recognize the unspec
1037 everywhere a symbol is normally recognized. (The PIC register
1038 should be recognized by GCC as pic_offset_table_rtx when needed
1039 and similar for PC.) Each component can then be optimized with
1040 the rest of the code; it should be possible to have a constant
1041 term added on an unspec. Don't forget to add a REG_EQUAL (or
1042 is it REG_EQUIV) note to the destination. It might not be
1045 Note that the 'v' modifier makes PLT references be output as
1046 sym:PLT rather than [rPIC+sym:GOTPLT]. */
1047 return \"move.d %v1,%0\;add.d %P1,%0\";
1050 return \"BOGUS: %1 to %0\";
1053 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no")])
1055 ;; Extend operations with side-effect from mem to register, using
1056 ;; MOVS/MOVU. These are from mem to register only.
1062 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1063 ;; HImode by itself? Perhaps use only anonymous modes?
1065 (define_insn "*ext_sideqihi_biap"
1066 [(set (match_operand:HI 0 "register_operand" "=r,r")
1068 5 "cris_extend_operator"
1070 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1071 (match_operand:SI 2 "const_int_operand" "n,n"))
1072 (match_operand:SI 3 "register_operand" "r,r")))]))
1073 (set (match_operand:SI 4 "register_operand" "=*3,r")
1074 (plus:SI (mult:SI (match_dup 1)
1077 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1080 mov%e5.%m5 [%4=%3+%1%T2],%0")
1084 (define_insn "*ext_sideqisi_biap"
1085 [(set (match_operand:SI 0 "register_operand" "=r,r")
1087 5 "cris_extend_operator"
1089 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1090 (match_operand:SI 2 "const_int_operand" "n,n"))
1091 (match_operand:SI 3 "register_operand" "r,r")))]))
1092 (set (match_operand:SI 4 "register_operand" "=*3,r")
1093 (plus:SI (mult:SI (match_dup 1)
1096 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1099 mov%e5.%m5 [%4=%3+%1%T2],%0")
1103 (define_insn "*ext_sidehisi_biap"
1104 [(set (match_operand:SI 0 "register_operand" "=r,r")
1106 5 "cris_extend_operator"
1108 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1109 (match_operand:SI 2 "const_int_operand" "n,n"))
1110 (match_operand:SI 3 "register_operand" "r,r")))]))
1111 (set (match_operand:SI 4 "register_operand" "=*3,r")
1112 (plus:SI (mult:SI (match_dup 1)
1115 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1118 mov%e5.%m5 [%4=%3+%1%T2],%0")
1120 ;; Same but [rx=ry+i]
1124 (define_insn "*ext_sideqihi"
1125 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1127 4 "cris_extend_operator"
1129 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1130 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1131 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1132 (plus:SI (match_dup 1)
1134 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1137 if (which_alternative == 0
1138 && (GET_CODE (operands[2]) != CONST_INT
1139 || INTVAL (operands[2]) > 127
1140 || INTVAL (operands[2]) < -128
1141 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1142 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1144 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1149 (define_insn "*ext_sideqisi"
1150 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1152 4 "cris_extend_operator"
1154 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1155 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1156 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1157 (plus:SI (match_dup 1)
1159 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1162 if (which_alternative == 0
1163 && (GET_CODE (operands[2]) != CONST_INT
1164 || INTVAL (operands[2]) > 127
1165 || INTVAL (operands[2]) < -128
1166 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1167 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1169 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1174 (define_insn "*ext_sidehisi"
1175 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1177 4 "cris_extend_operator"
1179 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
1180 (match_operand:SI 2 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1181 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
1182 (plus:SI (match_dup 1)
1184 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1187 if (which_alternative == 0
1188 && (GET_CODE (operands[2]) != CONST_INT
1189 || INTVAL (operands[2]) > 127
1190 || INTVAL (operands[2]) < -128
1191 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1192 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1194 return \"mov%e4.%m4 [%3=%1%S2],%0\";
1197 ;; FIXME: See movsi.
1199 (define_insn "movhi"
1201 (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,r,r,r,g,g,r")
1202 (match_operand:HI 1 "general_operand" "r,Q>,M,M,I,r,L,O,n,M,r,g"))]
1206 switch (which_alternative)
1213 return \"move.w %1,%0\";
1217 return \"clear.w %0\";
1219 return \"moveq %1,%0\";
1222 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1224 if (INTVAL (operands[1]) > 0)
1225 return \"movu.b %1,%0\";
1226 return \"movs.b %1,%0\";
1228 return \"move.w %1,%0\";
1230 return \"movEq %b1,%0\";
1232 return \"BOGUS: %1 to %0\";
1235 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no")
1237 (if_then_else (eq_attr "alternative" "7")
1238 (const_string "clobber")
1239 (const_string "normal")))])
1241 (define_insn "movstricthi"
1244 (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g"))
1245 (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))]
1256 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1258 (define_insn "movqi"
1259 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r")
1260 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))]
1273 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no")
1275 (if_then_else (eq_attr "alternative" "8")
1276 (const_string "clobber")
1277 (const_string "normal")))])
1279 (define_insn "movstrictqi"
1280 [(set (strict_low_part
1281 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r"))
1282 (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))]
1293 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1295 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1296 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1297 ;; all ones); the worthwhile one is "0.0".
1298 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1300 (define_insn "movsf"
1301 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r")
1302 (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))]
1313 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1316 ;; Sign- and zero-extend insns with standard names.
1317 ;; Those for integer source operand are ordered with the widest source
1322 (define_insn "extendsidi2"
1323 [(set (match_operand:DI 0 "register_operand" "=r")
1324 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1326 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1328 (define_insn "extendhidi2"
1329 [(set (match_operand:DI 0 "register_operand" "=r")
1330 (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
1332 "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0")
1334 (define_insn "extendhisi2"
1335 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1336 (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))]
1339 [(set_attr "slottable" "yes,yes,no")])
1341 (define_insn "extendqidi2"
1342 [(set (match_operand:DI 0 "register_operand" "=r")
1343 (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
1345 "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0")
1347 (define_insn "extendqisi2"
1348 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1349 (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1352 [(set_attr "slottable" "yes,yes,no")])
1354 ;; To do a byte->word exension, extend to dword, exept that the top half
1355 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1357 (define_insn "extendqihi2"
1358 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1359 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1362 [(set_attr "slottable" "yes,yes,no")])
1365 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1366 ;; specify them here.
1368 (define_insn "zero_extendhisi2"
1369 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1371 (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))]
1374 [(set_attr "slottable" "yes,yes,no")])
1376 (define_insn "zero_extendqisi2"
1377 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1379 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1382 [(set_attr "slottable" "yes,yes,no")])
1384 ;; Same comment as sign-extend QImode to HImode above applies.
1386 (define_insn "zero_extendqihi2"
1387 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1389 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1392 [(set_attr "slottable" "yes,yes,no")])
1394 ;; All kinds of arithmetic and logical instructions.
1396 ;; First, anonymous patterns to match addressing modes with
1399 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1402 ;; FIXME: These could have anonymous mode for operand 0.
1406 (define_insn "*op_sideqi_biap"
1407 [(set (match_operand:QI 0 "register_operand" "=r,r")
1409 6 "cris_orthogonal_operator"
1410 [(match_operand:QI 1 "register_operand" "0,0")
1412 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1413 (match_operand:SI 3 "const_int_operand" "n,n"))
1414 (match_operand:SI 4 "register_operand" "r,r")))]))
1415 (set (match_operand:SI 5 "register_operand" "=*4,r")
1416 (plus:SI (mult:SI (match_dup 2)
1419 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1422 %x6.%s0 [%5=%4+%2%T3],%0")
1426 (define_insn "*op_sidehi_biap"
1427 [(set (match_operand:HI 0 "register_operand" "=r,r")
1429 6 "cris_orthogonal_operator"
1430 [(match_operand:HI 1 "register_operand" "0,0")
1432 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1433 (match_operand:SI 3 "const_int_operand" "n,n"))
1434 (match_operand:SI 4 "register_operand" "r,r")))]))
1435 (set (match_operand:SI 5 "register_operand" "=*4,r")
1436 (plus:SI (mult:SI (match_dup 2)
1439 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1442 %x6.%s0 [%5=%4+%2%T3],%0")
1446 (define_insn "*op_sidesi_biap"
1447 [(set (match_operand:SI 0 "register_operand" "=r,r")
1449 6 "cris_orthogonal_operator"
1450 [(match_operand:SI 1 "register_operand" "0,0")
1452 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1453 (match_operand:SI 3 "const_int_operand" "n,n"))
1454 (match_operand:SI 4 "register_operand" "r,r")))]))
1455 (set (match_operand:SI 5 "register_operand" "=*4,r")
1456 (plus:SI (mult:SI (match_dup 2)
1459 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1462 %x6.%s0 [%5=%4+%2%T3],%0")
1464 ;; [rx=ry+i] ([%4=%2+%3])
1465 ;; FIXME: These could have anonymous mode for operand 0.
1469 (define_insn "*op_sideqi"
1470 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1472 5 "cris_orthogonal_operator"
1473 [(match_operand:QI 1 "register_operand" "0,0,0")
1475 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1476 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1477 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1478 (plus:SI (match_dup 2)
1480 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1483 if (which_alternative == 0
1484 && (GET_CODE (operands[3]) != CONST_INT
1485 || INTVAL (operands[3]) > 127
1486 || INTVAL (operands[3]) < -128
1487 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1488 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1490 return \"%x5.%s0 [%4=%2%S3],%0\";
1495 (define_insn "*op_sidehi"
1496 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1498 5 "cris_orthogonal_operator"
1499 [(match_operand:HI 1 "register_operand" "0,0,0")
1501 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1502 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1503 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1504 (plus:SI (match_dup 2)
1506 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1509 if (which_alternative == 0
1510 && (GET_CODE (operands[3]) != CONST_INT
1511 || INTVAL (operands[3]) > 127
1512 || INTVAL (operands[3]) < -128
1513 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1514 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1516 return \"%x5.%s0 [%4=%2%S3],%0\";
1521 (define_insn "*op_sidesi"
1522 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1524 5 "cris_orthogonal_operator"
1525 [(match_operand:SI 1 "register_operand" "0,0,0")
1527 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1528 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))]))
1529 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1530 (plus:SI (match_dup 2)
1532 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1535 if (which_alternative == 0
1536 && (GET_CODE (operands[3]) != CONST_INT
1537 || INTVAL (operands[3]) > 127
1538 || INTVAL (operands[3]) < -128
1539 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1540 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1542 return \"%x5.%s0 [%4=%2%S3],%0\";
1545 ;; To match all cases for commutative operations we may have to have the
1546 ;; following pattern for add, or & and. I do not know really, but it does
1547 ;; not break anything.
1549 ;; FIXME: This really ought to be checked.
1551 ;; op.S [rx=ry+I],rz;
1554 ;; FIXME: These could have anonymous mode for operand 0.
1558 (define_insn "*op_swap_sideqi_biap"
1559 [(set (match_operand:QI 0 "register_operand" "=r,r")
1561 6 "cris_commutative_orth_op"
1563 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1564 (match_operand:SI 3 "const_int_operand" "n,n"))
1565 (match_operand:SI 4 "register_operand" "r,r")))
1566 (match_operand:QI 1 "register_operand" "0,0")]))
1567 (set (match_operand:SI 5 "register_operand" "=*4,r")
1568 (plus:SI (mult:SI (match_dup 2)
1571 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1574 %x6.%s0 [%5=%4+%2%T3],%0")
1578 (define_insn "*op_swap_sidehi_biap"
1579 [(set (match_operand:HI 0 "register_operand" "=r,r")
1581 6 "cris_commutative_orth_op"
1583 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1584 (match_operand:SI 3 "const_int_operand" "n,n"))
1585 (match_operand:SI 4 "register_operand" "r,r")))
1586 (match_operand:HI 1 "register_operand" "0,0")]))
1587 (set (match_operand:SI 5 "register_operand" "=*4,r")
1588 (plus:SI (mult:SI (match_dup 2)
1591 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1594 %x6.%s0 [%5=%4+%2%T3],%0")
1598 (define_insn "*op_swap_sidesi_biap"
1599 [(set (match_operand:SI 0 "register_operand" "=r,r")
1601 6 "cris_commutative_orth_op"
1603 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1604 (match_operand:SI 3 "const_int_operand" "n,n"))
1605 (match_operand:SI 4 "register_operand" "r,r")))
1606 (match_operand:SI 1 "register_operand" "0,0")]))
1607 (set (match_operand:SI 5 "register_operand" "=*4,r")
1608 (plus:SI (mult:SI (match_dup 2)
1611 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1614 %x6.%s0 [%5=%4+%2%T3],%0")
1616 ;; [rx=ry+i] ([%4=%2+%3])
1617 ;; FIXME: These could have anonymous mode for operand 0.
1621 (define_insn "*op_swap_sideqi"
1622 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
1624 5 "cris_commutative_orth_op"
1626 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1627 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))
1628 (match_operand:QI 1 "register_operand" "0,0,0")]))
1629 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1630 (plus:SI (match_dup 2)
1632 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1635 if (which_alternative == 0
1636 && (GET_CODE (operands[3]) != CONST_INT
1637 || INTVAL (operands[3]) > 127
1638 || INTVAL (operands[3]) < -128
1639 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1640 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1642 return \"%x5.%s0 [%4=%2%S3],%0\";
1647 (define_insn "*op_swap_sidehi"
1648 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1650 5 "cris_commutative_orth_op"
1652 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1653 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))
1654 (match_operand:HI 1 "register_operand" "0,0,0")]))
1655 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1656 (plus:SI (match_dup 2)
1658 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1661 if (which_alternative == 0
1662 && (GET_CODE (operands[3]) != CONST_INT
1663 || INTVAL (operands[3]) > 127
1664 || INTVAL (operands[3]) < -128
1665 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1666 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1668 return \"%x5.%s0 [%4=%2%S3],%0\";
1673 (define_insn "*op_swap_sidesi"
1674 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1676 5 "cris_commutative_orth_op"
1678 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1679 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))
1680 (match_operand:SI 1 "register_operand" "0,0,0")]))
1681 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1682 (plus:SI (match_dup 2)
1684 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1687 if (which_alternative == 0
1688 && (GET_CODE (operands[3]) != CONST_INT
1689 || INTVAL (operands[3]) > 127
1690 || INTVAL (operands[3]) < -128
1691 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1692 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1694 return \"%x5.%s0 [%4=%2%S3],%0\";
1697 ;; Add operations, standard names.
1699 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1700 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1702 (define_insn "adddi3"
1703 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1704 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1705 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1708 addq %2,%M0\;ax\;addq 0,%H0
1709 subq %n2,%M0\;ax\;subq 0,%H0
1710 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1711 add.d %M2,%M0\;ax\;add.d %H2,%H0
1712 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1714 (define_insn "addsi3"
1715 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1717 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r")
1718 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
1720 ;; The last constraint is due to that after reload, the '%' is not
1721 ;; honored, and canonicalization doesn't care about keeping the same
1722 ;; register as in destination. This will happen after insn splitting.
1723 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1728 switch (which_alternative)
1732 return \"add.d %2,%0\";
1734 return \"addq %2,%0\";
1736 return \"subq %n2,%0\";
1738 /* 'Known value', but not in -63..63.
1739 Check if addu/subu may be used. */
1740 if (INTVAL (operands[2]) > 0)
1742 if (INTVAL (operands[2]) < 256)
1743 return \"addu.b %2,%0\";
1744 if (INTVAL (operands[2]) < 65536)
1745 return \"addu.w %2,%0\";
1749 if (INTVAL (operands[2]) >= -255)
1750 return \"subu.b %n2,%0\";
1751 if (INTVAL (operands[2]) >= -65535)
1752 return \"subu.w %n2,%0\";
1754 return \"add.d %2,%0\";
1756 return \"add.d %2,%1,%0\";
1758 return \"add.d %2,%0\";
1760 return \"add.d %1,%0\";
1762 return \"BOGUS addsi %2+%1 to %0\";
1765 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
1767 (define_insn "addhi3"
1768 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1769 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
1770 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1779 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1780 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1782 (define_insn "addqi3"
1783 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r")
1784 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r")
1785 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1795 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1796 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1800 ;; Note that because of insn canonicalization these will *seldom* but
1801 ;; rarely be used with a known constant as an operand.
1803 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1804 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1806 (define_insn "subdi3"
1807 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1808 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1809 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1812 subq %2,%M0\;ax\;subq 0,%H0
1813 addq %n2,%M0\;ax\;addq 0,%H0
1814 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1815 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1816 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1818 (define_insn "subsi3"
1819 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1821 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r")
1822 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1825 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1826 ;; But then again, %2 should not be negative.
1837 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1839 (define_insn "subhi3"
1840 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1841 (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r")
1842 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1851 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1852 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1854 (define_insn "subqi3"
1855 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1856 (minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r")
1857 (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1866 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1867 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1869 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
1870 ;; Although these perform sign/zero-extension to SImode, they are
1871 ;; equally applicable for the HImode case.
1872 ;; FIXME: Check; GCC should handle the widening.
1873 ;; Note that these must be located after the normal add/sub patterns,
1874 ;; so not to get constants into any less specific operands.
1876 ;; Extend with add/sub and side-effect.
1878 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
1880 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
1881 ;; FIXME: These could have anonymous mode for operand 0.
1884 ;; FIXME: GCC should widen.
1886 (define_insn "*extopqihi_side_biap"
1887 [(set (match_operand:HI 0 "register_operand" "=r,r")
1889 6 "cris_operand_extend_operator"
1890 [(match_operand:HI 1 "register_operand" "0,0")
1892 7 "cris_extend_operator"
1894 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1895 (match_operand:SI 3 "const_int_operand" "n,n"))
1896 (match_operand:SI 4 "register_operand" "r,r")))])]))
1897 (set (match_operand:SI 5 "register_operand" "=*4,r")
1898 (plus:SI (mult:SI (match_dup 2)
1901 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1902 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1905 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1909 (define_insn "*extopqisi_side_biap"
1910 [(set (match_operand:SI 0 "register_operand" "=r,r")
1912 6 "cris_operand_extend_operator"
1913 [(match_operand:SI 1 "register_operand" "0,0")
1915 7 "cris_extend_operator"
1917 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1918 (match_operand:SI 3 "const_int_operand" "n,n"))
1919 (match_operand:SI 4 "register_operand" "r,r")))])]))
1920 (set (match_operand:SI 5 "register_operand" "=*4,r")
1921 (plus:SI (mult:SI (match_dup 2)
1924 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1925 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1928 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1932 (define_insn "*extophisi_side_biap"
1933 [(set (match_operand:SI 0 "register_operand" "=r,r")
1935 6 "cris_operand_extend_operator"
1936 [(match_operand:SI 1 "register_operand" "0,0")
1938 7 "cris_extend_operator"
1940 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1941 (match_operand:SI 3 "const_int_operand" "n,n"))
1942 (match_operand:SI 4 "register_operand" "r,r")))])]))
1943 (set (match_operand:SI 5 "register_operand" "=*4,r")
1944 (plus:SI (mult:SI (match_dup 2)
1947 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1948 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1951 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1955 ;; FIXME: These could have anonymous mode for operand 0.
1959 (define_insn "*extopqihi_side"
1960 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1962 5 "cris_operand_extend_operator"
1963 [(match_operand:HI 1 "register_operand" "0,0,0")
1965 6 "cris_extend_operator"
1967 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1968 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")
1970 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1971 (plus:SI (match_dup 2)
1973 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
1974 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1977 if (which_alternative == 0
1978 && (GET_CODE (operands[3]) != CONST_INT
1979 || INTVAL (operands[3]) > 127
1980 || INTVAL (operands[3]) < -128
1981 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1982 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1984 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
1989 (define_insn "*extopqisi_side"
1990 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1992 5 "cris_operand_extend_operator"
1993 [(match_operand:SI 1 "register_operand" "0,0,0")
1995 6 "cris_extend_operator"
1997 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1998 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")
2000 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2001 (plus:SI (match_dup 2)
2004 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2005 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2008 if (which_alternative == 0
2009 && (GET_CODE (operands[3]) != CONST_INT
2010 || INTVAL (operands[3]) > 127
2011 || INTVAL (operands[3]) < -128
2012 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2013 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2015 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2020 (define_insn "*extophisi_side"
2021 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2023 5 "cris_operand_extend_operator"
2024 [(match_operand:SI 1 "register_operand" "0,0,0")
2026 6 "cris_extend_operator"
2028 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2029 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")
2031 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2032 (plus:SI (match_dup 2)
2034 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2035 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2038 if (which_alternative == 0
2039 && (GET_CODE (operands[3]) != CONST_INT
2040 || INTVAL (operands[3]) > 127
2041 || INTVAL (operands[3]) < -128
2042 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2043 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2045 return \"%x5%e6.%m6 [%4=%2%S3],%0\";
2049 ;; As with op.S we may have to add special pattern to match commuted
2050 ;; operands to adds/addu and bound
2052 ;; adds/addu/bound [rx=ry+rz.S]
2055 ;; FIXME: GCC should widen.
2056 ;; FIXME: These could have anonymous mode for operand 0.
2058 (define_insn "*extopqihi_swap_side_biap"
2059 [(set (match_operand:HI 0 "register_operand" "=r,r")
2061 7 "cris_plus_or_bound_operator"
2063 6 "cris_extend_operator"
2065 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2066 (match_operand:SI 3 "const_int_operand" "n,n"))
2067 (match_operand:SI 4 "register_operand" "r,r")))])
2068 (match_operand:HI 1 "register_operand" "0,0")]))
2069 (set (match_operand:SI 5 "register_operand" "=*4,r")
2070 (plus:SI (mult:SI (match_dup 2)
2073 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2074 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2077 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2081 (define_insn "*extopqisi_swap_side_biap"
2082 [(set (match_operand:SI 0 "register_operand" "=r,r")
2084 7 "cris_plus_or_bound_operator"
2086 6 "cris_extend_operator"
2088 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2089 (match_operand:SI 3 "const_int_operand" "n,n"))
2090 (match_operand:SI 4 "register_operand" "r,r")))])
2091 (match_operand:SI 1 "register_operand" "0,0")]))
2092 (set (match_operand:SI 5 "register_operand" "=*4,r")
2093 (plus:SI (mult:SI (match_dup 2)
2096 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2097 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2100 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2103 (define_insn "*extophisi_swap_side_biap"
2104 [(set (match_operand:SI 0 "register_operand" "=r,r")
2106 7 "cris_plus_or_bound_operator"
2108 6 "cris_extend_operator"
2110 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2111 (match_operand:SI 3 "const_int_operand" "n,n"))
2112 (match_operand:SI 4 "register_operand" "r,r")))])
2113 (match_operand:SI 1 "register_operand" "0,0")]))
2114 (set (match_operand:SI 5 "register_operand" "=*4,r")
2115 (plus:SI (mult:SI (match_dup 2)
2118 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2119 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2122 %x7%e6.%m6 [%5=%4+%2%T3],%0")
2125 ;; FIXME: These could have anonymous mode for operand 0.
2126 ;; FIXME: GCC should widen.
2130 (define_insn "*extopqihi_swap_side"
2131 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2133 6 "cris_plus_or_bound_operator"
2135 5 "cris_extend_operator"
2137 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2138 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))])
2139 (match_operand:HI 1 "register_operand" "0,0,0")]))
2140 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2141 (plus:SI (match_dup 2)
2143 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2144 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2147 if (which_alternative == 0
2148 && (GET_CODE (operands[3]) != CONST_INT
2149 || INTVAL (operands[3]) > 127
2150 || INTVAL (operands[3]) < -128
2151 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2152 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2154 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2159 (define_insn "*extopqisi_swap_side"
2160 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2162 6 "cris_plus_or_bound_operator"
2164 5 "cris_extend_operator"
2166 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2167 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))])
2168 (match_operand:SI 1 "register_operand" "0,0,0")]))
2169 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2170 (plus:SI (match_dup 2)
2172 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2173 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2176 if (which_alternative == 0
2177 && (GET_CODE (operands[3]) != CONST_INT
2178 || INTVAL (operands[3]) > 127
2179 || INTVAL (operands[3]) < -128
2180 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2181 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2183 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2188 (define_insn "*extophisi_swap_side"
2189 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2191 6 "cris_plus_or_bound_operator"
2193 5 "cris_extend_operator"
2195 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
2196 (match_operand:SI 3 "cris_bdap_operand" "r>Ri,r,>Ri")))])
2197 (match_operand:SI 1 "register_operand" "0,0,0")]))
2198 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
2199 (plus:SI (match_dup 2)
2201 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2202 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2205 if (which_alternative == 0
2206 && (GET_CODE (operands[3]) != CONST_INT
2207 || INTVAL (operands[3]) > 127
2208 || INTVAL (operands[3]) < -128
2209 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2210 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2212 return \"%x6%e5.%m5 [%4=%2%S3],%0\";
2215 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2216 ;; FIXME: These could have anonymous mode for operand 0.
2219 ;; FIXME: GCC should widen.
2221 (define_insn "*extopqihi"
2222 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2224 3 "cris_operand_extend_operator"
2225 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2227 4 "cris_extend_operator"
2228 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2229 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2230 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2231 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2236 %x3%e4.%m4 %2,%1,%0"
2237 [(set_attr "slottable" "yes,yes,no,no")
2238 (set_attr "cc" "clobber")])
2242 (define_insn "*extopqisi"
2243 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2245 3 "cris_operand_extend_operator"
2246 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2248 4 "cris_extend_operator"
2249 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2250 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2251 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2252 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2257 %x3%e4.%m4 %2,%1,%0"
2258 [(set_attr "slottable" "yes,yes,no,no")])
2262 (define_insn "*extophisi"
2263 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2265 3 "cris_operand_extend_operator"
2266 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2268 4 "cris_extend_operator"
2269 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2270 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2271 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2272 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2277 %x3%e4.%m4 %2,%1,%0"
2278 [(set_attr "slottable" "yes,yes,no,no")])
2281 ;; As with the side-effect patterns, may have to have swapped operands for add.
2282 ;; FIXME: *should* be redundant to gcc.
2286 (define_insn "*extopqihi_swap"
2287 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2289 4 "cris_plus_or_bound_operator"
2291 3 "cris_extend_operator"
2292 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2293 (match_operand:HI 1 "register_operand" "0,0,0,r")]))]
2294 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2295 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2296 && operands[1] != frame_pointer_rtx"
2301 %x4%e3.%m3 %2,%1,%0"
2302 [(set_attr "slottable" "yes,yes,no,no")
2303 (set_attr "cc" "clobber")])
2307 (define_insn "*extopqisi_swap"
2308 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2310 4 "cris_plus_or_bound_operator"
2312 3 "cris_extend_operator"
2313 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2314 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2315 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2316 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2317 && operands[1] != frame_pointer_rtx"
2322 %x4%e3.%m3 %2,%1,%0"
2323 [(set_attr "slottable" "yes,yes,no,no")])
2327 (define_insn "*extophisi_swap"
2328 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2330 4 "cris_plus_or_bound_operator"
2332 3 "cris_extend_operator"
2333 [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2334 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2335 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2336 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2337 && operands[1] != frame_pointer_rtx"
2342 %x4%e3.%m3 %2,%1,%0"
2343 [(set_attr "slottable" "yes,yes,no,no")])
2345 ;; This is the special case when we use what corresponds to the
2346 ;; instruction above in "casesi". Do *not* change it to use the generic
2347 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2348 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2349 ;; or replacing this pattern with something simpler, other variant
2350 ;; patterns were recognized or combined, including some prefix variants
2351 ;; where the value in pc is not that of the next instruction (which means
2352 ;; this instruction actually *is* special and *should* be marked as such).
2353 ;; When switching from the "generic pattern match" approach to this simpler
2354 ;; approach, there were insignificant differences in gcc, ipps and
2355 ;; product code, somehow due to scratching reload behind the ear or
2356 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2357 ;; product code became .001% smaller but "looked better". The testcase
2358 ;; "ipps" was just different at register allocation).
2360 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2361 ;; pattern with the default-label as the else, with the "if" being
2362 ;; index-is-less-than the max number of cases plus one. The default-label
2363 ;; is attached to the end of the case-table at time of output.
2365 (define_insn "*casesi_adds_w"
2368 (ltu (match_operand:SI 0 "register_operand" "r")
2369 (match_operand:SI 1 "const_int_operand" "n"))
2370 (plus:SI (sign_extend:SI
2372 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2375 (label_ref (match_operand 2 "" ""))))
2376 (use (label_ref (match_operand 3 "" "")))]
2378 "operands[0] != frame_pointer_rtx"
2380 "adds.w [$pc+%0.w],$pc"
2381 [(set_attr "cc" "clobber")])
2383 ;; Multiply instructions.
2385 ;; Sometimes powers of 2 (which are normally canonicalized to a
2386 ;; left-shift) appear here, as a result of address reloading.
2387 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2389 ;; FIXME: This may be unnecessary now.
2390 ;; Explicitly named for convenience of having a gen_... function.
2392 (define_insn "addi_mul"
2393 [(set (match_operand:SI 0 "register_operand" "=r")
2395 (match_operand:SI 1 "register_operand" "%0")
2396 (match_operand:SI 2 "const_int_operand" "n")))]
2397 "operands[0] != frame_pointer_rtx
2398 && operands[1] != frame_pointer_rtx
2399 && GET_CODE (operands[2]) == CONST_INT
2400 && (INTVAL (operands[2]) == 2
2401 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2402 || INTVAL (operands[2]) == 5)"
2405 if (INTVAL (operands[2]) == 2)
2406 return \"lslq 1,%0\";
2407 else if (INTVAL (operands[2]) == 4)
2408 return \"lslq 2,%0\";
2409 else if (INTVAL (operands[2]) == 3)
2410 return \"addi %0.w,%0\";
2411 else if (INTVAL (operands[2]) == 5)
2412 return \"addi %0.d,%0\";
2413 return \"BAD: adr_mulsi: %0=%1*%2\";
2415 [(set_attr "slottable" "yes")
2416 ;; No flags are changed if this insn is "addi", but it does not seem
2417 ;; worth the trouble to distinguish that to the lslq cases.
2418 (set_attr "cc" "clobber")])
2420 ;; The addi insn as it is normally used.
2422 (define_insn "*addi"
2423 [(set (match_operand:SI 0 "register_operand" "=r")
2425 (mult:SI (match_operand:SI 2 "register_operand" "r")
2426 (match_operand:SI 3 "const_int_operand" "n"))
2427 (match_operand:SI 1 "register_operand" "0")))]
2428 "operands[0] != frame_pointer_rtx
2429 && operands[1] != frame_pointer_rtx
2430 && GET_CODE (operands[3]) == CONST_INT
2431 && (INTVAL (operands[3]) == 1
2432 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2434 [(set_attr "slottable" "yes")
2435 (set_attr "cc" "none")])
2437 ;; The mstep instruction. Probably not useful by itself; it's to
2438 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2441 (define_insn "mstep_shift"
2442 [(set (match_operand:SI 0 "register_operand" "=r")
2444 (lt:SI (cc0) (const_int 0))
2445 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2447 (match_operand:SI 2 "register_operand" "r"))
2448 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2452 [(set_attr "slottable" "yes")])
2454 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2455 ;; to canonicalize the multiplications.
2457 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2459 (define_insn "mstep_mul"
2460 [(set (match_operand:SI 0 "register_operand" "=r")
2462 (lt:SI (cc0) (const_int 0))
2463 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2465 (match_operand:SI 2 "register_operand" "r"))
2466 (mult:SI (match_operand:SI 3 "register_operand" "0")
2468 "operands[0] != frame_pointer_rtx
2469 && operands[1] != frame_pointer_rtx
2470 && operands[2] != frame_pointer_rtx
2471 && operands[3] != frame_pointer_rtx"
2473 [(set_attr "slottable" "yes")])
2475 (define_insn "umulhisi3"
2476 [(set (match_operand:SI 0 "register_operand" "=r")
2478 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2479 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2480 "TARGET_HAS_MUL_INSNS"
2482 [(set_attr "slottable" "yes")
2483 ;; Just N unusable here, but let's be safe.
2484 (set_attr "cc" "clobber")])
2486 (define_insn "umulqihi3"
2487 [(set (match_operand:HI 0 "register_operand" "=r")
2489 (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2490 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2491 "TARGET_HAS_MUL_INSNS"
2493 [(set_attr "slottable" "yes")
2494 ;; Not exactly sure, but let's be safe.
2495 (set_attr "cc" "clobber")])
2497 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2498 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2499 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2500 ;; Inspection of optab code shows that there must be only one widening
2501 ;; multiplication per mode widened to.
2503 (define_insn "mulsi3"
2504 [(set (match_operand:SI 0 "register_operand" "=r")
2505 (mult:SI (match_operand:SI 1 "register_operand" "0")
2506 (match_operand:SI 2 "register_operand" "r")))]
2507 "TARGET_HAS_MUL_INSNS"
2509 [(set_attr "slottable" "yes")
2510 ;; Just N unusable here, but let's be safe.
2511 (set_attr "cc" "clobber")])
2513 ;; A few multiply variations.
2515 ;; This really extends to SImode, so cc should be considered clobbered.
2517 (define_insn "mulqihi3"
2518 [(set (match_operand:HI 0 "register_operand" "=r")
2520 (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))
2521 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2522 "TARGET_HAS_MUL_INSNS"
2524 [(set_attr "slottable" "yes")
2525 (set_attr "cc" "clobber")])
2527 (define_insn "mulhisi3"
2528 [(set (match_operand:SI 0 "register_operand" "=r")
2530 (sign_extend:SI (match_operand:HI 1 "register_operand" "0"))
2531 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2532 "TARGET_HAS_MUL_INSNS"
2534 [(set_attr "slottable" "yes")
2535 ;; Just N unusable here, but let's be safe.
2536 (set_attr "cc" "clobber")])
2538 ;; When needed, we can get the high 32 bits from the overflow
2539 ;; register. We don't care to split and optimize these.
2541 ;; Note that cc0 is still valid after the move-from-overflow-register
2542 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2544 (define_insn "mulsidi3"
2545 [(set (match_operand:DI 0 "register_operand" "=r")
2547 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
2548 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2549 "TARGET_HAS_MUL_INSNS"
2550 "muls.d %2,%M0\;move $mof,%H0")
2552 (define_insn "umulsidi3"
2553 [(set (match_operand:DI 0 "register_operand" "=r")
2555 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
2556 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
2557 "TARGET_HAS_MUL_INSNS"
2558 "mulu.d %2,%M0\;move $mof,%H0")
2560 ;; This pattern would probably not be needed if we add "mof" in its own
2561 ;; register class (and open a can of worms about /not/ pairing it with a
2562 ;; "normal" register). Having multiple register classes here, and
2563 ;; applicable to the v10 variant only, seems worse than having these two
2564 ;; patterns with multi-insn contents for now (may change; having a free
2565 ;; call-clobbered register is worth some trouble).
2567 (define_insn "smulsi3_highpart"
2568 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2572 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2573 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2575 (clobber (match_scratch:SI 3 "=X,1,1"))]
2576 "TARGET_HAS_MUL_INSNS"
2577 "muls.d %2,%1\;move $mof,%0"
2578 [(set_attr "cc" "clobber")])
2580 (define_insn "umulsi3_highpart"
2581 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
2585 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
2586 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r,r")))
2588 (clobber (match_scratch:SI 3 "=X,1,1"))]
2589 "TARGET_HAS_MUL_INSNS"
2590 "mulu.d %2,%1\;move $mof,%0"
2591 [(set_attr "cc" "clobber")])
2593 ;; Divide and modulus instructions. CRIS only has a step instruction.
2595 (define_insn "dstep_shift"
2596 [(set (match_operand:SI 0 "register_operand" "=r")
2598 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2600 (match_operand:SI 2 "register_operand" "r"))
2601 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2603 (match_operand:SI 4 "register_operand" "2"))
2604 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2608 [(set_attr "slottable" "yes")])
2610 ;; Here's a variant with mult instead of ashift.
2612 ;; FIXME: This should be investigated. Which one matches through combination?
2614 (define_insn "dstep_mul"
2615 [(set (match_operand:SI 0 "register_operand" "=r")
2617 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2619 (match_operand:SI 2 "register_operand" "r"))
2620 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2622 (match_operand:SI 4 "register_operand" "2"))
2623 (mult:SI (match_operand:SI 5 "register_operand" "0")
2625 "operands[0] != frame_pointer_rtx
2626 && operands[1] != frame_pointer_rtx
2627 && operands[2] != frame_pointer_rtx
2628 && operands[3] != frame_pointer_rtx"
2630 [(set_attr "slottable" "yes")])
2632 ;; Logical operators.
2636 ;; There is no use in defining "anddi3", because gcc can expand this by
2637 ;; itself, and make reasonable code without interference.
2639 ;; If the first operand is memory or a register and is the same as the
2640 ;; second operand, and the third operand is -256 or -65536, we can use
2641 ;; CLEAR instead. Or, if the first operand is a register, and the third
2642 ;; operand is 255 or 65535, we can zero_extend.
2643 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2644 ;; to be common enough to be worthwhile.
2645 ;; FIXME: This should be made obsolete.
2647 (define_expand "andsi3"
2648 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2649 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2650 (match_operand:SI 2 "general_operand" "")))]
2654 if (! (GET_CODE (operands[2]) == CONST_INT
2655 && (((INTVAL (operands[2]) == -256
2656 || INTVAL (operands[2]) == -65536)
2657 && rtx_equal_p (operands[1], operands[0]))
2658 || ((INTVAL (operands[2]) == 255
2659 || INTVAL (operands[2]) == 65535)
2660 && REG_P (operands[0])))))
2662 /* Make intermediate steps if operand0 is not a register or
2663 operand1 is not a register, and hope that the reload pass will
2664 make something useful out of it. Note that the operands are
2665 *not* canonicalized. For the moment, I chicken out on this,
2666 because all or most ports do not describe 'and' with
2667 canonicalized operands, and I seem to remember magic in reload,
2668 checking that operand1 has constraint '%0', in which case
2669 operand0 and operand1 must have similar predicates.
2670 FIXME: Investigate. */
2671 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2672 rtx reg1 = operands[1];
2676 emit_move_insn (reg0, reg1);
2680 emit_insn (gen_rtx_SET (SImode, reg0,
2681 gen_rtx_AND (SImode, reg1, operands[2])));
2683 /* Make sure we get the right *final* destination. */
2684 if (! REG_P (operands[0]))
2685 emit_move_insn (operands[0], reg0);
2691 ;; Some special cases of andsi3.
2693 (define_insn "*andsi_movu"
2694 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2695 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q>,m")
2696 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2697 "INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535"
2699 [(set_attr "slottable" "yes,yes,no")])
2701 (define_insn "*andsi_clear"
2702 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q>,Q>,m,m")
2703 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2704 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2705 "INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256"
2713 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2714 (set_attr "cc" "none")])
2716 ;; This is a catch-all pattern, taking care of everything that was not
2717 ;; matched in the insns above.
2719 ;; Sidenote: the tightening from "nonimmediate_operand" to
2720 ;; "register_operand" for operand 1 actually increased the register
2721 ;; pressure (worse code). That will hopefully change with an
2722 ;; improved reload pass.
2724 (define_insn "*expanded_andsi"
2725 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2726 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,r")
2727 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2735 [(set_attr "slottable" "yes,yes,yes,no,no")])
2737 ;; For both QI and HI we may use the quick patterns. This results in
2738 ;; useless condition codes, but that is used rarely enough for it to
2739 ;; normally be a win (could check ahead for use of cc0, but seems to be
2740 ;; more pain than win).
2742 ;; FIXME: See note for andsi3
2744 (define_expand "andhi3"
2745 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2746 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2747 (match_operand:HI 2 "general_operand" "")))]
2751 if (! (GET_CODE (operands[2]) == CONST_INT
2752 && (((INTVAL (operands[2]) == -256
2753 || INTVAL (operands[2]) == 65280)
2754 && rtx_equal_p (operands[1], operands[0]))
2755 || (INTVAL (operands[2]) == 255
2756 && REG_P (operands[0])))))
2758 /* See comment for andsi3. */
2759 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2760 rtx reg1 = operands[1];
2764 emit_move_insn (reg0, reg1);
2768 emit_insn (gen_rtx_SET (HImode, reg0,
2769 gen_rtx_AND (HImode, reg1, operands[2])));
2771 /* Make sure we get the right destination. */
2772 if (! REG_P (operands[0]))
2773 emit_move_insn (operands[0], reg0);
2779 ;; Some fast andhi3 special cases.
2781 (define_insn "*andhi_movu"
2782 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2783 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")
2787 [(set_attr "slottable" "yes,yes,no")])
2789 (define_insn "*andhi_clear_signed"
2790 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
2791 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2795 [(set_attr "slottable" "yes,yes,no")
2796 (set_attr "cc" "none")])
2798 ;; FIXME: Either this or the pattern above should be redundant.
2799 (define_insn "*andhi_clear_unsigned"
2800 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q>,m")
2801 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2802 (const_int 65280)))]
2805 [(set_attr "slottable" "yes,yes,no")
2806 (set_attr "cc" "none")])
2808 ;; Catch-all andhi3 pattern.
2810 (define_insn "*expanded_andhi"
2811 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2812 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2813 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2815 ;; Sidenote: the tightening from "general_operand" to
2816 ;; "register_operand" for operand 1 actually increased the register
2817 ;; pressure (worse code). That will hopefully change with an
2818 ;; improved reload pass.
2829 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2830 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2832 ;; A strict_low_part pattern.
2834 (define_insn "*andhi_lowpart"
2835 [(set (strict_low_part
2836 (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r"))
2837 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
2838 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2847 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2848 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2850 (define_insn "andqi3"
2851 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2852 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2853 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2862 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2863 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2865 (define_insn "*andqi_lowpart"
2866 [(set (strict_low_part
2867 (match_operand:QI 0 "register_operand" "=r,r,r,r,r"))
2868 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,r")
2869 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2877 [(set_attr "slottable" "yes,yes,yes,no,no")
2878 (set_attr "cc" "normal,normal,clobber,normal,normal")])
2882 ;; Same comment as anddi3 applies here - no need for such a pattern.
2884 ;; It seems there's no need to jump through hoops to get good code such as
2887 (define_insn "iorsi3"
2888 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
2889 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,r")
2890 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g,!To")))]
2899 [(set_attr "slottable" "yes,yes,yes,no,no,no")
2900 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2902 (define_insn "iorhi3"
2903 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
2904 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
2905 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2915 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2916 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2918 (define_insn "iorqi3"
2919 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
2920 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
2921 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2930 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2931 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2935 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
2937 (define_insn "xorsi3"
2938 [(set (match_operand:SI 0 "register_operand" "=r")
2939 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2940 (match_operand:SI 2 "register_operand" "r")))]
2943 [(set_attr "slottable" "yes")])
2945 (define_insn "xorhi3"
2946 [(set (match_operand:HI 0 "register_operand" "=r")
2947 (xor:HI (match_operand:HI 1 "register_operand" "%0")
2948 (match_operand:HI 2 "register_operand" "r")))]
2951 [(set_attr "slottable" "yes")
2952 (set_attr "cc" "clobber")])
2954 (define_insn "xorqi3"
2955 [(set (match_operand:QI 0 "register_operand" "=r")
2956 (xor:QI (match_operand:QI 1 "register_operand" "%0")
2957 (match_operand:QI 2 "register_operand" "r")))]
2960 [(set_attr "slottable" "yes")
2961 (set_attr "cc" "clobber")])
2965 ;; Questionable use, here mostly as a (slightly usable) define_expand
2968 (define_expand "negsf2"
2971 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
2972 (neg:SF (match_operand:SF 1
2973 "register_operand" "0")))
2974 (use (match_dup 2))])]
2978 operands[2] = gen_reg_rtx (SImode);
2979 operands[3] = GEN_INT (1 << 31);
2982 (define_insn "*expanded_negsf2"
2983 [(set (match_operand:SF 0 "register_operand" "=r")
2984 (neg:SF (match_operand:SF 1 "register_operand" "0")))
2985 (use (match_operand:SI 2 "register_operand" "r"))]
2988 [(set_attr "slottable" "yes")])
2990 ;; No "negdi2" although we could make one up that may be faster than
2991 ;; the one in libgcc.
2993 (define_insn "negsi2"
2994 [(set (match_operand:SI 0 "register_operand" "=r")
2995 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
2998 [(set_attr "slottable" "yes")])
3000 (define_insn "neghi2"
3001 [(set (match_operand:HI 0 "register_operand" "=r")
3002 (neg:HI (match_operand:HI 1 "register_operand" "r")))]
3005 [(set_attr "slottable" "yes")])
3007 (define_insn "negqi2"
3008 [(set (match_operand:QI 0 "register_operand" "=r")
3009 (neg:QI (match_operand:QI 1 "register_operand" "r")))]
3012 [(set_attr "slottable" "yes")])
3016 ;; See comment on anddi3 - no need for a DImode pattern.
3018 (define_insn "one_cmplsi2"
3019 [(set (match_operand:SI 0 "register_operand" "=r")
3020 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3023 [(set_attr "slottable" "yes")])
3025 (define_insn "one_cmplhi2"
3026 [(set (match_operand:HI 0 "register_operand" "=r")
3027 (not:HI (match_operand:HI 1 "register_operand" "0")))]
3030 [(set_attr "slottable" "yes")
3031 (set_attr "cc" "clobber")])
3033 (define_insn "one_cmplqi2"
3034 [(set (match_operand:QI 0 "register_operand" "=r")
3035 (not:QI (match_operand:QI 1 "register_operand" "0")))]
3038 [(set_attr "slottable" "yes")
3039 (set_attr "cc" "clobber")])
3041 ;; Arithmetic shift right.
3043 (define_insn "ashrsi3"
3044 [(set (match_operand:SI 0 "register_operand" "=r")
3045 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
3046 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3050 if (REG_S_P (operands[2]))
3051 return \"asr.d %2,%0\";
3053 return \"asrq %2,%0\";
3055 [(set_attr "slottable" "yes")])
3057 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3058 ;; the destination) when it changes shifts of lower modes into SImode,
3059 ;; it is better to make these expands an anonymous patterns instead of
3060 ;; the more correct define_insns. This occurs when gcc thinks that is
3061 ;; is better to widen to SImode and use immediate shift count.
3063 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3065 (define_expand "ashrhi3"
3067 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))
3069 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm")))
3070 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3071 (set (match_operand:HI 0 "general_operand" "=g")
3072 (subreg:HI (match_dup 5) 0))]
3078 for (i = 3; i < 6; i++)
3079 operands[i] = gen_reg_rtx (SImode);
3082 (define_insn "*expanded_ashrhi"
3083 [(set (match_operand:HI 0 "register_operand" "=r")
3084 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
3085 (match_operand:HI 2 "register_operand" "r")))]
3088 [(set_attr "slottable" "yes")])
3090 (define_insn "*ashrhi_lowpart"
3091 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3092 (ashiftrt:HI (match_dup 0)
3093 (match_operand:HI 1 "register_operand" "r")))]
3096 [(set_attr "slottable" "yes")])
3098 ;; Same comment goes as for "ashrhi3".
3100 (define_expand "ashrqi3"
3102 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3104 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3105 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3106 (set (match_operand:QI 0 "general_operand" "=g")
3107 (subreg:QI (match_dup 5) 0))]
3113 for (i = 3; i < 6; i++)
3114 operands[i] = gen_reg_rtx (SImode);
3117 (define_insn "*expanded_ashrqi"
3118 [(set (match_operand:QI 0 "register_operand" "=r")
3119 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
3120 (match_operand:QI 2 "register_operand" "r")))]
3123 [(set_attr "slottable" "yes")])
3125 ;; A strict_low_part matcher.
3127 (define_insn "*ashrqi_lowpart"
3128 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3129 (ashiftrt:QI (match_dup 0)
3130 (match_operand:QI 1 "register_operand" "r")))]
3133 [(set_attr "slottable" "yes")])
3135 ;; Logical shift right.
3137 (define_insn "lshrsi3"
3138 [(set (match_operand:SI 0 "register_operand" "=r")
3139 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3140 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3144 if (REG_S_P (operands[2]))
3145 return \"lsr.d %2,%0\";
3147 return \"lsrq %2,%0\";
3149 [(set_attr "slottable" "yes")])
3151 ;; Same comments as for ashrhi3.
3153 (define_expand "lshrhi3"
3155 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
3157 (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "g")))
3158 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3159 (set (match_operand:HI 0 "general_operand" "=g")
3160 (subreg:HI (match_dup 5) 0))]
3166 for (i = 3; i < 6; i++)
3167 operands[i] = gen_reg_rtx (SImode);
3170 (define_insn "*expanded_lshrhi"
3171 [(set (match_operand:HI 0 "register_operand" "=r")
3172 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
3173 (match_operand:HI 2 "register_operand" "r")))]
3176 [(set_attr "slottable" "yes")])
3178 ;; A strict_low_part matcher.
3180 (define_insn "*lshrhi_lowpart"
3181 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3182 (lshiftrt:HI (match_dup 0)
3183 (match_operand:HI 1 "register_operand" "r")))]
3186 [(set_attr "slottable" "yes")])
3188 ;; Same comments as for ashrhi3.
3190 (define_expand "lshrqi3"
3192 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
3194 (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g")))
3195 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3196 (set (match_operand:QI 0 "general_operand" "=g")
3197 (subreg:QI (match_dup 5) 0))]
3203 for (i = 3; i < 6; i++)
3204 operands[i] = gen_reg_rtx (SImode);
3207 (define_insn "*expanded_lshrqi"
3208 [(set (match_operand:QI 0 "register_operand" "=r")
3209 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
3210 (match_operand:QI 2 "register_operand" "r")))]
3213 [(set_attr "slottable" "yes")])
3215 ;; A strict_low_part matcher.
3217 (define_insn "*lshrqi_lowpart"
3218 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3219 (lshiftrt:QI (match_dup 0)
3220 (match_operand:QI 1 "register_operand" "r")))]
3223 [(set_attr "slottable" "yes")])
3225 ;; Arithmetic/logical shift left.
3227 (define_insn "ashlsi3"
3228 [(set (match_operand:SI 0 "register_operand" "=r")
3229 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3230 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3234 if (REG_S_P (operands[2]))
3235 return \"lsl.d %2,%0\";
3237 return \"lslq %2,%0\";
3239 [(set_attr "slottable" "yes")])
3241 ;; For narrower modes than SI, we can use lslq although it makes cc
3242 ;; unusable. The win is that we do not have to reload the shift-count
3245 (define_insn "ashlhi3"
3246 [(set (match_operand:HI 0 "register_operand" "=r,r")
3247 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
3248 (match_operand:HI 2 "nonmemory_operand" "r,K")))]
3253 (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 15)
3255 : (CONSTANT_P (operands[2])
3256 ? \"lslq %2,%0\" : \"lsl.w %2,%0\");
3258 [(set_attr "slottable" "yes")
3259 (set_attr "cc" "normal,clobber")])
3261 ;; A strict_low_part matcher.
3263 (define_insn "*ashlhi_lowpart"
3264 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
3265 (ashift:HI (match_dup 0)
3266 (match_operand:HI 1 "register_operand" "r")))]
3269 [(set_attr "slottable" "yes")])
3271 (define_insn "ashlqi3"
3272 [(set (match_operand:QI 0 "register_operand" "=r,r")
3273 (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
3274 (match_operand:QI 2 "nonmemory_operand" "r,K")))]
3279 (GET_CODE (operands[2]) == CONST_INT
3280 && INTVAL (operands[2]) > 7)
3282 : (CONSTANT_P (operands[2])
3283 ? \"lslq %2,%0\" : \"lsl.b %2,%0\");
3285 [(set_attr "slottable" "yes")
3286 (set_attr "cc" "normal,clobber")])
3288 ;; A strict_low_part matcher.
3290 (define_insn "*ashlqi_lowpart"
3291 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
3292 (ashift:QI (match_dup 0)
3293 (match_operand:QI 1 "register_operand" "r")))]
3296 [(set_attr "slottable" "yes")])
3298 ;; Various strange insns that gcc likes.
3300 ;; Fortunately, it is simple to construct an abssf (although it may not
3301 ;; be very much used in practice).
3303 (define_insn "abssf2"
3304 [(set (match_operand:SF 0 "register_operand" "=r")
3305 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3307 "lslq 1,%0\;lsrq 1,%0")
3309 (define_insn "abssi2"
3310 [(set (match_operand:SI 0 "register_operand" "=r")
3311 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3314 [(set_attr "slottable" "yes")])
3316 ;; FIXME: GCC should be able to do these expansions itself.
3318 (define_expand "abshi2"
3320 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))
3321 (set (match_dup 3) (abs:SI (match_dup 2)))
3322 (set (match_operand:HI 0 "register_operand" "=r")
3323 (subreg:HI (match_dup 3) 0))]
3325 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3327 (define_expand "absqi2"
3329 (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))
3330 (set (match_dup 3) (abs:SI (match_dup 2)))
3331 (set (match_operand:QI 0 "register_operand" "=r")
3332 (subreg:QI (match_dup 3) 0))]
3334 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3336 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3337 ;; operation supported by gcc. Used in casesi, but used now and then in
3340 (define_insn "uminsi3"
3341 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3342 (umin:SI (match_operand:SI 1 "register_operand" "%0,0,0,r")
3343 (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
3347 if (GET_CODE (operands[2]) == CONST_INT)
3349 if (INTVAL (operands[2]) < 256)
3350 return \"bound.b %2,%0\";
3352 if (INTVAL (operands[2]) < 65536)
3353 return \"bound.w %2,%0\";
3355 else if (which_alternative == 3)
3356 return \"bound.d %2,%1,%0\";
3358 return \"bound.d %2,%0\";
3360 [(set_attr "slottable" "yes,yes,no,no")])
3362 ;; Jump and branch insns.
3366 (label_ref (match_operand 0 "" "")))]
3369 [(set_attr "slottable" "has_slot")])
3371 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3372 ;; here, since the insn is not recognized as an indirect jump by
3373 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3374 ;; change from general_operand to nonimmediate_operand (at least the docs
3375 ;; should be changed), but then again the pattern is called indirect_jump.
3376 (define_insn "indirect_jump"
3377 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3381 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3382 ;; a single ret or jump [sp+] or a contiguous sequence of movem:able saved
3383 ;; registers. No allocated stack space is allowed.
3384 ;; Note that for this pattern, although named, it is ok to check the
3385 ;; context of the insn in the test, not only compiler switches.
3387 (define_insn "return"
3389 "cris_simple_epilogue ()"
3394 /* Just needs to hold a 'movem [sp+],rN'. */
3395 char rd[sizeof (\"movem [$sp+],$r99\")];
3399 /* Start from the last call-saved register. We know that we have a
3400 simple epilogue, so we just have to find the last register in the
3402 for (i = 8; i >= 0; i--)
3403 if (regs_ever_live[i]
3404 || (i == PIC_OFFSET_TABLE_REGNUM
3405 && current_function_uses_pic_offset_table))
3409 sprintf (rd, \"movem [$sp+],$%s\", reg_names [i]);
3411 if (regs_ever_live[CRIS_SRP_REGNUM])
3414 output_asm_insn (rd, operands);
3415 return \"jump [$sp+]\";
3420 output_asm_insn (\"reT\", operands);
3421 output_asm_insn (rd, operands);
3427 [(set (attr "slottable")
3429 (ne (symbol_ref "regs_ever_live[CRIS_SRP_REGNUM]") (const_int 0))
3430 (const_string "no") ; If jump then not slottable.
3434 || (flag_pic != 0 && regs_ever_live[1])
3435 || (PIC_OFFSET_TABLE_REGNUM == 0
3436 && cris_cfun_uses_pic_table ()))")
3438 (const_string "no") ; ret+movem [sp+],rx: slot already filled.
3439 (const_string "has_slot")))) ; If ret then need to fill a slot.
3440 (set_attr "cc" "none")])
3442 ;; Conditional branches.
3444 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3445 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3450 (if_then_else (eq (cc0)
3452 (label_ref (match_operand 0 "" ""))
3456 [(set_attr "slottable" "has_slot")])
3460 (if_then_else (ne (cc0)
3462 (label_ref (match_operand 0 "" ""))
3466 [(set_attr "slottable" "has_slot")])
3470 (if_then_else (gt (cc0)
3472 (label_ref (match_operand 0 "" ""))
3478 (cc_prev_status.flags & CC_NO_OVERFLOW)
3479 ? 0 : \"bgt %l0%#\";
3481 [(set_attr "slottable" "has_slot")])
3485 (if_then_else (gtu (cc0)
3487 (label_ref (match_operand 0 "" ""))
3491 [(set_attr "slottable" "has_slot")])
3495 (if_then_else (lt (cc0)
3497 (label_ref (match_operand 0 "" ""))
3503 (cc_prev_status.flags & CC_NO_OVERFLOW)
3504 ? \"bmi %l0%#\" : \"blt %l0%#\";
3506 [(set_attr "slottable" "has_slot")])
3510 (if_then_else (ltu (cc0)
3512 (label_ref (match_operand 0 "" ""))
3516 [(set_attr "slottable" "has_slot")])
3520 (if_then_else (ge (cc0)
3522 (label_ref (match_operand 0 "" ""))
3528 (cc_prev_status.flags & CC_NO_OVERFLOW)
3529 ? \"bpl %l0%#\" : \"bge %l0%#\";
3531 [(set_attr "slottable" "has_slot")])
3535 (if_then_else (geu (cc0)
3537 (label_ref (match_operand 0 "" ""))
3541 [(set_attr "slottable" "has_slot")])
3545 (if_then_else (le (cc0)
3547 (label_ref (match_operand 0 "" ""))
3553 (cc_prev_status.flags & CC_NO_OVERFLOW)
3554 ? 0 : \"ble %l0%#\";
3556 [(set_attr "slottable" "has_slot")])
3560 (if_then_else (leu (cc0)
3562 (label_ref (match_operand 0 "" ""))
3566 [(set_attr "slottable" "has_slot")])
3568 ;; Reversed anonymous patterns to the ones above, as mandated.
3570 (define_insn "*beq_reversed"
3572 (if_then_else (eq (cc0)
3575 (label_ref (match_operand 0 "" ""))))]
3578 [(set_attr "slottable" "has_slot")])
3580 (define_insn "*bne_reversed"
3582 (if_then_else (ne (cc0)
3585 (label_ref (match_operand 0 "" ""))))]
3588 [(set_attr "slottable" "has_slot")])
3590 (define_insn "*bgt_reversed"
3592 (if_then_else (gt (cc0)
3595 (label_ref (match_operand 0 "" ""))))]
3600 (cc_prev_status.flags & CC_NO_OVERFLOW)
3601 ? 0 : \"ble %l0%#\";
3603 [(set_attr "slottable" "has_slot")])
3605 (define_insn "*bgtu_reversed"
3607 (if_then_else (gtu (cc0)
3610 (label_ref (match_operand 0 "" ""))))]
3613 [(set_attr "slottable" "has_slot")])
3615 (define_insn "*blt_reversed"
3617 (if_then_else (lt (cc0)
3620 (label_ref (match_operand 0 "" ""))))]
3625 (cc_prev_status.flags & CC_NO_OVERFLOW)
3626 ? \"bpl %l0%#\" : \"bge %l0%#\";
3628 [(set_attr "slottable" "has_slot")])
3630 (define_insn "*bltu_reversed"
3632 (if_then_else (ltu (cc0)
3635 (label_ref (match_operand 0 "" ""))))]
3638 [(set_attr "slottable" "has_slot")])
3640 (define_insn "*bge_reversed"
3642 (if_then_else (ge (cc0)
3645 (label_ref (match_operand 0 "" ""))))]
3650 (cc_prev_status.flags & CC_NO_OVERFLOW)
3651 ? \"bmi %l0%#\" : \"blt %l0%#\";
3653 [(set_attr "slottable" "has_slot")])
3655 (define_insn "*bgeu_reversed"
3657 (if_then_else (geu (cc0)
3660 (label_ref (match_operand 0 "" ""))))]
3663 [(set_attr "slottable" "has_slot")])
3665 (define_insn "*ble_reversed"
3667 (if_then_else (le (cc0)
3670 (label_ref (match_operand 0 "" ""))))]
3675 (cc_prev_status.flags & CC_NO_OVERFLOW)
3676 ? 0 : \"bgt %l0%#\";
3678 [(set_attr "slottable" "has_slot")])
3680 (define_insn "*bleu_reversed"
3682 (if_then_else (leu (cc0)
3685 (label_ref (match_operand 0 "" ""))))]
3688 [(set_attr "slottable" "has_slot")])
3690 ;; Set on condition: sCC.
3692 ;; Like bCC, we have to check the overflow bit for
3693 ;; signed conditions.
3696 [(set (match_operand:SI 0 "register_operand" "=r")
3697 (geu:SI (cc0) (const_int 0)))]
3700 [(set_attr "slottable" "yes")
3701 (set_attr "cc" "none")])
3704 [(set (match_operand:SI 0 "register_operand" "=r")
3705 (ltu:SI (cc0) (const_int 0)))]
3708 [(set_attr "slottable" "yes")
3709 (set_attr "cc" "none")])
3712 [(set (match_operand:SI 0 "register_operand" "=r")
3713 (eq:SI (cc0) (const_int 0)))]
3716 [(set_attr "slottable" "yes")
3717 (set_attr "cc" "none")])
3720 [(set (match_operand:SI 0 "register_operand" "=r")
3721 (ge:SI (cc0) (const_int 0)))]
3726 (cc_prev_status.flags & CC_NO_OVERFLOW)
3727 ? \"spl %0\" : \"sge %0\";
3729 [(set_attr "slottable" "yes")
3730 (set_attr "cc" "none")])
3733 [(set (match_operand:SI 0 "register_operand" "=r")
3734 (gt:SI (cc0) (const_int 0)))]
3739 (cc_prev_status.flags & CC_NO_OVERFLOW)
3742 [(set_attr "slottable" "yes")
3743 (set_attr "cc" "none")])
3746 [(set (match_operand:SI 0 "register_operand" "=r")
3747 (gtu:SI (cc0) (const_int 0)))]
3750 [(set_attr "slottable" "yes")
3751 (set_attr "cc" "none")])
3754 [(set (match_operand:SI 0 "register_operand" "=r")
3755 (le:SI (cc0) (const_int 0)))]
3760 (cc_prev_status.flags & CC_NO_OVERFLOW)
3763 [(set_attr "slottable" "yes")
3764 (set_attr "cc" "none")])
3767 [(set (match_operand:SI 0 "register_operand" "=r")
3768 (leu:SI (cc0) (const_int 0)))]
3771 [(set_attr "slottable" "yes")])
3774 [(set (match_operand:SI 0 "register_operand" "=r")
3775 (lt:SI (cc0) (const_int 0)))]
3780 (cc_prev_status.flags & CC_NO_OVERFLOW)
3781 ? \"smi %0\" : \"slt %0\";
3783 [(set_attr "slottable" "yes")
3784 (set_attr "cc" "none")])
3787 [(set (match_operand:SI 0 "register_operand" "=r")
3788 (ne:SI (cc0) (const_int 0)))]
3791 [(set_attr "slottable" "yes")
3792 (set_attr "cc" "none")])
3796 ;; We need to make these patterns "expand", since the real operand is
3797 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3798 ;; and cannot be checked if it were a "normal" pattern.
3799 ;; Note that "call" and "call_value" are *always* called with a
3800 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3801 ;; instructions is a different issue.
3803 (define_expand "call"
3804 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3805 (match_operand 1 "general_operand" ""))
3806 ;; 16 is the srp (can't use the symbolic name here)
3807 (clobber (reg:SI 16))])]
3813 if (GET_CODE (operands[0]) != MEM)
3818 op0 = XEXP (operands[0], 0);
3820 /* It might be that code can be generated that jumps to 0 (or to a
3821 specific address). Don't abort on that. At least there's a
3823 if (CONSTANT_ADDRESS_P (op0) && GET_CODE (op0) != CONST_INT)
3828 /* For local symbols (non-PLT), get the plain symbol reference
3829 into a register. For symbols that can be PLT, make them PLT. */
3830 if (cris_gotless_symbol (op0) || GET_CODE (op0) != SYMBOL_REF)
3831 op0 = force_reg (Pmode, op0);
3832 else if (cris_symbol (op0))
3833 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3834 for the symbol cause bad recombinatorial effects? */
3835 op0 = force_reg (Pmode,
3838 gen_rtx_UNSPEC (VOIDmode,
3839 gen_rtvec (1, op0), 0)));
3843 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]), op0);
3848 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3849 ;; order of preference (Q includes r, but r is shorter, faster)
3851 (define_insn "*expanded_call"
3852 [(call (mem:QI (match_operand:SI
3853 0 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3854 (match_operand 1 "" ""))
3855 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3856 "! TARGET_AVOID_GOTPLT"
3859 ;; Same as above, since can't afford wasting a constraint letter to mean
3860 ;; "S unless TARGET_AVOID_GOTPLT".
3861 (define_insn "*expanded_call_no_gotplt"
3862 [(call (mem:QI (match_operand:SI
3863 0 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3864 (match_operand 1 "" ""))
3865 (clobber (reg:SI 16))] ;; 16 is the srp (can't use symbolic name)
3866 "TARGET_AVOID_GOTPLT"
3869 (define_expand "call_value"
3870 [(parallel [(set (match_operand 0 "" "")
3871 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3872 (match_operand 2 "" "")))
3873 ;; 16 is the srp (can't use symbolic name)
3874 (clobber (reg:SI 16))])]
3880 if (GET_CODE (operands[1]) != MEM)
3885 op1 = XEXP (operands[1], 0);
3887 /* It might be that code can be generated that jumps to 0 (or to a
3888 specific address). Don't abort on that. At least there's a
3890 if (CONSTANT_ADDRESS_P (op1) && GET_CODE (op1) != CONST_INT)
3895 if (cris_gotless_symbol (op1))
3896 op1 = force_reg (Pmode, op1);
3897 else if (cris_symbol (op1))
3898 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
3899 for the symbol cause bad recombinatorial effects? */
3900 op1 = force_reg (Pmode,
3903 gen_rtx_UNSPEC (VOIDmode,
3904 gen_rtvec (1, op1), 0)));
3908 operands[1] = gen_rtx_MEM (GET_MODE (operands[1]), op1);
3913 ;; Accept *anything* as operand 2. The validity other than "general" of
3914 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3915 ;; order of preference (Q includes r, but r is shorter, faster).
3916 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3917 ;; than requiring getting rPIC + sym:PLT into a register.
3919 (define_insn "*expanded_call_value"
3920 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3921 (call (mem:QI (match_operand:SI
3922 1 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
3923 (match_operand 2 "" "")))
3924 (clobber (reg:SI 16))]
3925 "! TARGET_AVOID_GOTPLT"
3927 [(set_attr "cc" "clobber")])
3929 ;; Same as above, since can't afford wasting a constraint letter to mean
3930 ;; "S unless TARGET_AVOID_GOTPLT".
3931 (define_insn "*expanded_call_value_no_gotplt"
3932 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3933 (call (mem:QI (match_operand:SI
3934 1 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
3935 (match_operand 2 "" "")))
3936 (clobber (reg:SI 16))]
3937 "TARGET_AVOID_GOTPLT"
3939 [(set_attr "cc" "clobber")])
3941 ;; Used in debugging. No use for the direct pattern; unfilled
3942 ;; delayed-branches are taken care of by other means.
3948 [(set_attr "cc" "none")])
3950 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3951 ;; a table to pc" (adds.w [pc+%0.w],pc).
3953 ;; Note: if you change the "parallel" (or add anything after it) in
3954 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3955 ;; accordingly, to add the default case at the end of the jump-table.
3957 (define_expand "casesi"
3958 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3960 (minus:SI (match_dup 5)
3961 (match_operand:SI 1 "const_int_operand" "n")))
3963 (umin:SI (match_dup 6)
3964 (match_operand:SI 2 "const_int_operand" "n")))
3968 (ltu (match_dup 7) (match_dup 2))
3969 (plus:SI (sign_extend:SI
3971 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3974 (label_ref (match_operand 4 "" ""))))
3975 (use (label_ref (match_operand 3 "" "")))])]
3979 operands[2] = plus_constant (operands[2], 1);
3980 operands[5] = gen_reg_rtx (SImode);
3981 operands[6] = gen_reg_rtx (SImode);
3982 operands[7] = gen_reg_rtx (SImode);
3985 ;; Split-patterns. Some of them have modes unspecified. This
3986 ;; should always be ok; if for no other reason sparc.md has it as
3989 ;; When register_operand is specified for an operand, we can get a
3990 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3991 ;; for a register_operand and that REGNO can be used as is. It is best to
3992 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3994 ;; op [rx + 0],ry,rz
3995 ;; The index to rx is optimized into zero, and gone.
3997 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3998 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
4002 ;; Lose if rz=ry or rx=rz.
4003 ;; Call this op-extend-split
4006 [(set (match_operand 0 "register_operand" "")
4008 4 "cris_operand_extend_operator"
4009 [(match_operand 1 "register_operand" "")
4011 3 "cris_extend_operator"
4012 [(match_operand 2 "memory_operand" "")])]))]
4013 "REG_P (operands[0])
4014 && REG_P (operands[1])
4015 && REGNO (operands[1]) != REGNO (operands[0])
4016 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4017 && REG_P (XEXP (operands[2], 0))
4018 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4024 (match_op_dup 3 [(match_dup 2)])]))]
4027 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
4030 ;; Do this for plus or bound only, being commutative operations, since we
4031 ;; have swapped the operands.
4032 ;; Call this op-extend-split-rx=rz
4035 [(set (match_operand 0 "register_operand" "")
4037 4 "cris_plus_or_bound_operator"
4038 [(match_operand 1 "register_operand" "")
4040 3 "cris_extend_operator"
4041 [(match_operand 2 "memory_operand" "")])]))]
4042 "REG_P (operands[0])
4043 && REG_P (operands[1])
4044 && REGNO (operands[1]) != REGNO (operands[0])
4045 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4046 && REG_P (XEXP (operands[2], 0))
4047 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4049 (match_op_dup 3 [(match_dup 2)]))
4056 ;; As the op-extend-split, but swapped operands, and only for
4057 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4058 ;; this needed? Is it?
4059 ;; Call this op-extend-split-swapped
4062 [(set (match_operand 0 "register_operand" "")
4064 4 "cris_plus_or_bound_operator"
4066 3 "cris_extend_operator"
4067 [(match_operand 2 "memory_operand" "")])
4068 (match_operand 1 "register_operand" "")]))]
4069 "REG_P (operands[0])
4070 && REG_P (operands[1])
4071 && REGNO (operands[1]) != REGNO (operands[0])
4072 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4073 && REG_P (XEXP (operands[2], 0))
4074 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4080 (match_op_dup 3 [(match_dup 2)])]))]
4083 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4084 ;; bound. Call this op-extend-split-swapped-rx=rz.
4087 [(set (match_operand 0 "register_operand" "")
4089 4 "cris_plus_or_bound_operator"
4091 3 "cris_extend_operator"
4092 [(match_operand 2 "memory_operand" "")])
4093 (match_operand 1 "register_operand" "")]))]
4094 "REG_P (operands[0])
4095 && REG_P (operands[1])
4096 && REGNO (operands[1]) != REGNO (operands[0])
4097 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4098 && REG_P (XEXP (operands[2], 0))
4099 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4101 (match_op_dup 3 [(match_dup 2)]))
4108 ;; As op-extend-split, but the mem operand is not extended.
4110 ;; op [rx],ry,rz changed into
4113 ;; lose if ry=rz or rx=rz
4114 ;; Call this op-extend.
4117 [(set (match_operand 0 "register_operand" "")
4119 3 "cris_orthogonal_operator"
4120 [(match_operand 1 "register_operand" "")
4121 (match_operand 2 "memory_operand" "")]))]
4122 "REG_P (operands[0])
4123 && REG_P (operands[1])
4124 && REGNO (operands[1]) != REGNO (operands[0])
4125 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4126 && REG_P (XEXP (operands[2], 0))
4127 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4136 ;; As op-extend-split-rx=rz, non-extended.
4137 ;; Call this op-split-rx=rz
4140 [(set (match_operand 0 "register_operand" "")
4142 3 "cris_commutative_orth_op"
4143 [(match_operand 2 "memory_operand" "")
4144 (match_operand 1 "register_operand" "")]))]
4145 "REG_P (operands[0])
4146 && REG_P (operands[1])
4147 && REGNO (operands[1]) != REGNO (operands[0])
4148 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4149 && REG_P (XEXP (operands[2], 0))
4150 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4159 ;; As op-extend-split-swapped, nonextended.
4160 ;; Call this op-split-swapped.
4163 [(set (match_operand 0 "register_operand" "")
4165 3 "cris_commutative_orth_op"
4166 [(match_operand 1 "register_operand" "")
4167 (match_operand 2 "memory_operand" "")]))]
4168 "REG_P (operands[0]) && REG_P (operands[1])
4169 && REGNO (operands[1]) != REGNO (operands[0])
4170 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4171 && REG_P (XEXP (operands[2], 0))
4172 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4181 ;; As op-extend-split-swapped-rx=rz, non-extended.
4182 ;; Call this op-split-swapped-rx=rz.
4185 [(set (match_operand 0 "register_operand" "")
4187 3 "cris_orthogonal_operator"
4188 [(match_operand 2 "memory_operand" "")
4189 (match_operand 1 "register_operand" "")]))]
4190 "REG_P (operands[0]) && REG_P (operands[1])
4191 && REGNO (operands[1]) != REGNO (operands[0])
4192 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4193 && REG_P (XEXP (operands[2], 0))
4194 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4203 ;; Splits for all cases in side-effect insns where (possibly after reload
4204 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4206 ;; move.S1 [rx=rx+rz.S2],ry
4210 [(set (match_operand 0 "register_operand" "")
4212 (mult:SI (match_operand:SI 1 "register_operand" "")
4213 (match_operand:SI 2 "const_int_operand" ""))
4214 (match_operand:SI 3 "register_operand" ""))))
4215 (set (match_operand:SI 4 "register_operand" "")
4216 (plus:SI (mult:SI (match_dup 1)
4219 "REG_P (operands[3]) && REG_P (operands[4])
4220 && REGNO (operands[3]) == REGNO (operands[4])"
4221 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4223 (set (match_dup 0) (match_dup 5))]
4224 "operands[5] = gen_rtx_MEM (GET_MODE (operands[0]), operands[3]);")
4226 ;; move.S1 [rx=rx+i],ry
4230 [(set (match_operand 0 "register_operand" "")
4232 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4233 (match_operand:SI 2 "cris_bdap_operand" ""))))
4234 (set (match_operand:SI 3 "register_operand" "")
4235 (plus:SI (match_dup 1)
4237 "(rtx_equal_p (operands[3], operands[1])
4238 || rtx_equal_p (operands[3], operands[2]))"
4239 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4240 (set (match_dup 0) (match_dup 4))]
4241 "operands[4] = gen_rtx_MEM (GET_MODE (operands[0]), operands[3]);")
4243 ;; move.S1 ry,[rx=rx+rz.S2]
4248 (mult:SI (match_operand:SI 0 "register_operand" "")
4249 (match_operand:SI 1 "const_int_operand" ""))
4250 (match_operand:SI 2 "register_operand" "")))
4251 (match_operand 3 "register_operand" ""))
4252 (set (match_operand:SI 4 "register_operand" "")
4253 (plus:SI (mult:SI (match_dup 0)
4256 "REG_P (operands[2]) && REG_P (operands[4])
4257 && REGNO (operands[4]) == REGNO (operands[2])"
4258 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4260 (set (match_dup 5) (match_dup 3))]
4261 "operands[5] = gen_rtx_MEM (GET_MODE (operands[3]), operands[4]);")
4263 ;; move.S1 ry,[rx=rx+i]
4268 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4269 (match_operand:SI 1 "cris_bdap_operand" "")))
4270 (match_operand 2 "register_operand" ""))
4271 (set (match_operand:SI 3 "register_operand" "")
4272 (plus:SI (match_dup 0)
4274 "(rtx_equal_p (operands[3], operands[0])
4275 || rtx_equal_p (operands[3], operands[1]))"
4276 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4277 (set (match_dup 5) (match_dup 2))]
4278 "operands[5] = gen_rtx_MEM (GET_MODE (operands[2]), operands[3]);")
4280 ;; clear.d [rx=rx+rz.S2]
4284 [(set (mem:SI (plus:SI
4285 (mult:SI (match_operand:SI 0 "register_operand" "")
4286 (match_operand:SI 1 "const_int_operand" ""))
4287 (match_operand:SI 2 "register_operand" "")))
4289 (set (match_operand:SI 3 "register_operand" "")
4290 (plus:SI (mult:SI (match_dup 0)
4293 "REG_P (operands[2]) && REG_P (operands[3])
4294 && REGNO (operands[3]) == REGNO (operands[2])"
4295 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4297 (set (mem:SI (match_dup 3)) (const_int 0))]
4300 ;; clear.w [rx=rx+rz.S2]
4304 [(set (mem:HI (plus:SI
4305 (mult:SI (match_operand:SI 0 "register_operand" "")
4306 (match_operand:SI 1 "const_int_operand" ""))
4307 (match_operand:SI 2 "register_operand" "")))
4309 (set (match_operand:SI 3 "register_operand" "")
4310 (plus:SI (mult:SI (match_dup 0)
4313 "REG_P (operands[2]) && REG_P (operands[3])
4314 && REGNO (operands[3]) == REGNO (operands[2])"
4315 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4317 (set (mem:HI (match_dup 3)) (const_int 0))]
4320 ;; clear.b [rx=rx+rz.S2]
4324 [(set (mem:QI (plus:SI
4325 (mult:SI (match_operand:SI 0 "register_operand" "")
4326 (match_operand:SI 1 "const_int_operand" ""))
4327 (match_operand:SI 2 "register_operand" "")))
4329 (set (match_operand:SI 3 "register_operand" "")
4330 (plus:SI (mult:SI (match_dup 0)
4333 "REG_P (operands[2]) && REG_P (operands[3])
4334 && REGNO (operands[3]) == REGNO (operands[2])"
4335 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4337 (set (mem:QI (match_dup 3)) (const_int 0))]
4340 ;; clear.d [rx=rx+i]
4345 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4346 (match_operand:SI 1 "cris_bdap_operand" "")))
4348 (set (match_operand:SI 2 "register_operand" "")
4349 (plus:SI (match_dup 0)
4351 "(rtx_equal_p (operands[0], operands[2])
4352 || rtx_equal_p (operands[2], operands[1]))"
4353 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4354 (set (mem:SI (match_dup 2)) (const_int 0))]
4357 ;; clear.w [rx=rx+i]
4362 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4363 (match_operand:SI 1 "cris_bdap_operand" "")))
4365 (set (match_operand:SI 2 "register_operand" "")
4366 (plus:SI (match_dup 0)
4368 "(rtx_equal_p (operands[0], operands[2])
4369 || rtx_equal_p (operands[2], operands[1]))"
4370 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4371 (set (mem:HI (match_dup 2)) (const_int 0))]
4374 ;; clear.b [rx=rx+i]
4379 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4380 (match_operand:SI 1 "cris_bdap_operand" "")))
4382 (set (match_operand:SI 2 "register_operand" "")
4383 (plus:SI (match_dup 0)
4385 "(rtx_equal_p (operands[0], operands[2])
4386 || rtx_equal_p (operands[2], operands[1]))"
4387 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4388 (set (mem:QI (match_dup 2)) (const_int 0))]
4391 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4395 [(set (match_operand 0 "register_operand" "")
4397 5 "cris_extend_operator"
4399 (mult:SI (match_operand:SI 1 "register_operand" "")
4400 (match_operand:SI 2 "const_int_operand" ""))
4401 (match_operand:SI 3 "register_operand" "")))]))
4402 (set (match_operand:SI 4 "register_operand" "")
4403 (plus:SI (mult:SI (match_dup 1)
4406 "REG_P (operands[3])
4407 && REG_P (operands[4])
4408 && REGNO (operands[3]) == REGNO (operands[4])"
4409 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4411 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4412 "operands[6] = gen_rtx_MEM (GET_MODE (XEXP (operands[5],0)),
4415 ;; mov(s|u).S1 [rx=rx+i],ry
4419 [(set (match_operand 0 "register_operand" "")
4421 4 "cris_extend_operator"
4423 (match_operand:SI 1 "cris_bdap_operand" "")
4424 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4425 (set (match_operand:SI 3 "register_operand" "")
4426 (plus:SI (match_dup 1)
4428 "(rtx_equal_p (operands[1], operands[3])
4429 || rtx_equal_p (operands[2], operands[3]))"
4430 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4431 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4432 "operands[5] = gen_rtx_MEM (GET_MODE (XEXP (operands[4], 0)),
4435 ;; op.S1 [rx=rx+i],ry
4439 [(set (match_operand 0 "register_operand" "")
4441 5 "cris_orthogonal_operator"
4442 [(match_operand 1 "register_operand" "")
4444 (match_operand:SI 2 "cris_bdap_operand" "")
4445 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4446 (set (match_operand:SI 4 "register_operand" "")
4447 (plus:SI (match_dup 2)
4449 "(rtx_equal_p (operands[4], operands[2])
4450 || rtx_equal_p (operands[4], operands[3]))"
4451 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4452 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4453 "operands[6] = gen_rtx_MEM (GET_MODE (operands[0]), operands[4]);")
4455 ;; op.S1 [rx=rx+rz.S2],ry
4459 [(set (match_operand 0 "register_operand" "")
4461 6 "cris_orthogonal_operator"
4462 [(match_operand 1 "register_operand" "")
4464 (mult:SI (match_operand:SI 2 "register_operand" "")
4465 (match_operand:SI 3 "const_int_operand" ""))
4466 (match_operand:SI 4 "register_operand" "")))]))
4467 (set (match_operand:SI 5 "register_operand" "")
4468 (plus:SI (mult:SI (match_dup 2)
4471 "REG_P (operands[4])
4472 && REG_P (operands[5])
4473 && REGNO (operands[5]) == REGNO (operands[4])"
4474 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4476 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4477 "operands[7] = gen_rtx_MEM (GET_MODE (operands[0]), operands[5]);")
4479 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4483 [(set (match_operand 0 "register_operand" "")
4485 6 "cris_commutative_orth_op"
4487 (mult:SI (match_operand:SI 2 "register_operand" "")
4488 (match_operand:SI 3 "const_int_operand" ""))
4489 (match_operand:SI 4 "register_operand" "")))
4490 (match_operand 1 "register_operand" "")]))
4491 (set (match_operand:SI 5 "register_operand" "")
4492 (plus:SI (mult:SI (match_dup 2)
4495 "REG_P (operands[4])
4496 && REG_P (operands[5])
4497 && REGNO (operands[5]) == REGNO (operands[4])"
4498 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4500 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4501 "operands[7] = gen_rtx_MEM (GET_MODE (operands[0]), operands[5]);")
4503 ;; op.S1 [rx=rx+i],ry (swapped)
4507 [(set (match_operand 0 "register_operand" "")
4509 5 "cris_commutative_orth_op"
4511 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4512 (match_operand:SI 3 "cris_bdap_operand" "")))
4513 (match_operand 1 "register_operand" "")]))
4514 (set (match_operand:SI 4 "register_operand" "")
4515 (plus:SI (match_dup 2)
4517 "(rtx_equal_p (operands[4], operands[2])
4518 || rtx_equal_p (operands[4], operands[3]))"
4519 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4520 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4521 "operands[6] = gen_rtx_MEM (GET_MODE (operands[0]), operands[4]);")
4523 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4527 [(set (match_operand 0 "register_operand" "")
4529 6 "cris_operand_extend_operator"
4530 [(match_operand 1 "register_operand" "")
4532 7 "cris_extend_operator"
4534 (mult:SI (match_operand:SI 2 "register_operand" "")
4535 (match_operand:SI 3 "const_int_operand" ""))
4536 (match_operand:SI 4 "register_operand" "")))])]))
4537 (set (match_operand:SI 5 "register_operand" "")
4538 (plus:SI (mult:SI (match_dup 2)
4541 "REG_P (operands[4])
4542 && REG_P (operands[5])
4543 && REGNO (operands[5]) == REGNO (operands[4])"
4544 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4546 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4547 "operands[8] = gen_rtx (GET_CODE (operands[7]), GET_MODE (operands[7]),
4548 gen_rtx_MEM (GET_MODE (XEXP (operands[7], 0)),
4551 ;; op(s|u).S1 [rx=rx+i],ry
4555 [(set (match_operand 0 "register_operand" "")
4557 5 "cris_operand_extend_operator"
4558 [(match_operand 1 "register_operand" "")
4560 6 "cris_extend_operator"
4562 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4563 (match_operand:SI 3 "cris_bdap_operand" "")
4565 (set (match_operand:SI 4 "register_operand" "")
4566 (plus:SI (match_dup 2)
4568 "(rtx_equal_p (operands[4], operands[2])
4569 || rtx_equal_p (operands[4], operands[3]))"
4570 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4571 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4572 "operands[7] = gen_rtx (GET_CODE (operands[6]), GET_MODE (operands[6]),
4573 gen_rtx_MEM (GET_MODE (XEXP (operands[6], 0)),
4576 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4580 [(set (match_operand 0 "register_operand" "")
4582 7 "cris_plus_or_bound_operator"
4584 6 "cris_extend_operator"
4586 (mult:SI (match_operand:SI 2 "register_operand" "")
4587 (match_operand:SI 3 "const_int_operand" ""))
4588 (match_operand:SI 4 "register_operand" "")))])
4589 (match_operand 1 "register_operand" "")]))
4590 (set (match_operand:SI 5 "register_operand" "")
4591 (plus:SI (mult:SI (match_dup 2)
4594 "REG_P (operands[4]) && REG_P (operands[5])
4595 && REGNO (operands[5]) == REGNO (operands[4])"
4596 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4598 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4599 "operands[8] = gen_rtx (GET_CODE (operands[6]), GET_MODE (operands[6]),
4600 gen_rtx_MEM (GET_MODE (XEXP (operands[6], 0)),
4603 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4607 [(set (match_operand 0 "register_operand" "")
4609 6 "cris_plus_or_bound_operator"
4611 5 "cris_extend_operator"
4613 (match_operand:SI 2 "cris_bdap_operand" "")
4614 (match_operand:SI 3 "cris_bdap_operand" "")))])
4615 (match_operand 1 "register_operand" "")]))
4616 (set (match_operand:SI 4 "register_operand" "")
4617 (plus:SI (match_dup 2)
4619 "(rtx_equal_p (operands[4], operands[2])
4620 || rtx_equal_p (operands[4], operands[3]))"
4621 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4622 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4623 "operands[7] = gen_rtx (GET_CODE (operands[5]), GET_MODE (operands[5]),
4624 gen_rtx_MEM (GET_MODE (XEXP (operands[5], 0)),
4627 ;; Splits for addressing prefixes that have no side-effects, so we can
4628 ;; fill a delay slot. Never split if we lose something, though.
4631 ;; move [indirect_ref],rx
4632 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4633 ;; move indirect_ref,rx
4635 ;; Take care not to allow indirect_ref = register.
4637 ;; We're not allowed to generate copies of registers with different mode
4638 ;; until after reload; copying pseudos upsets reload. CVS as of
4639 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4640 ;; cselib_invalidate_regno.
4643 [(set (match_operand 0 "register_operand" "")
4644 (match_operand 1 "indirect_operand" ""))]
4646 && REG_P (operands[0])
4647 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4648 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4649 || CONSTANT_P (XEXP (operands[1], 0)))"
4650 [(set (match_dup 2) (match_dup 4))
4651 (set (match_dup 0) (match_dup 3))]
4652 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4653 operands[3] = gen_rtx_MEM (GET_MODE (operands[0]), operands[2]);
4654 operands[4] = XEXP (operands[1], 0);")
4656 ;; As the above, but MOVS and MOVU.
4659 [(set (match_operand 0 "register_operand" "")
4661 4 "cris_extend_operator"
4662 [(match_operand 1 "indirect_operand" "")]))]
4664 && REG_P (operands[0])
4665 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4666 && (GET_CODE (XEXP (operands[1], 0)) == MEM
4667 || CONSTANT_P (XEXP (operands[1], 0)))"
4668 [(set (match_dup 2) (match_dup 5))
4669 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4670 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4671 operands[3] = gen_rtx_MEM (GET_MODE (XEXP (operands[4], 0)), operands[2]);
4672 operands[5] = XEXP (operands[1], 0);")
4674 ;; Various peephole optimizations.
4676 ;; Watch out: when you exchange one set of instructions for another, the
4677 ;; condition codes setting must be the same, or you have to CC_INIT or
4678 ;; whatever is appropriate, in the pattern before you emit the
4679 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4680 ;; to keep changes local to their cause.
4682 ;; Do not add patterns that you do not know will be matched.
4683 ;; Please also add a self-contained test-case.
4685 ;; We have trouble with and:s and shifts. Maybe something is broken in
4686 ;; gcc? Or it could just be that bitfield insn expansion is a bit
4687 ;; suboptimal when not having extzv insns.
4690 [(set (match_operand 0 "register_operand" "=r")
4691 (ashiftrt:SI (match_dup 0)
4692 (match_operand:SI 1 "const_int_operand" "n")))
4694 (and:SI (match_dup 0)
4695 (match_operand 2 "const_int_operand" "n")))]
4696 "INTVAL (operands[2]) > 31
4697 && INTVAL (operands[2]) < 255
4698 && INTVAL (operands[1]) > 23"
4700 ;; The m flag should be ignored, because this will be a *byte* "and"
4705 cc_status.flags |= CC_NOT_NEGATIVE;
4707 return \"lsrq %1,%0\;and.b %2,%0\";
4711 [(set (match_operand 0 "register_operand" "=r")
4712 (ashiftrt:SI (match_dup 0)
4713 (match_operand:SI 1 "const_int_operand" "n")))
4715 (and:SI (match_dup 0)
4716 (match_operand 2 "const_int_operand" "n")))]
4717 "INTVAL (operands[2]) > 31
4718 && INTVAL (operands[2]) < 65535
4719 && INTVAL (operands[2]) != 255
4720 && INTVAL (operands[1]) > 15"
4722 ;; The m flag should be ignored, because this will be a *word* "and"
4727 cc_status.flags |= CC_NOT_NEGATIVE;
4729 return \"lsrq %1,%0\;and.w %2,%0\";
4733 [(set (match_operand 0 "register_operand" "=r")
4734 (lshiftrt:SI (match_dup 0)
4735 (match_operand:SI 1 "const_int_operand" "n")))
4737 (and:SI (match_dup 0)
4738 (match_operand 2 "const_int_operand" "n")))]
4739 "INTVAL (operands[2]) > 31
4740 && INTVAL (operands[2]) < 255
4741 && INTVAL (operands[1]) > 23"
4743 ;; The m flag should be ignored, because this will be a *byte* "and"
4748 cc_status.flags |= CC_NOT_NEGATIVE;
4750 return \"lsrq %1,%0\;and.b %2,%0\";
4754 [(set (match_operand 0 "register_operand" "=r")
4755 (lshiftrt:SI (match_dup 0)
4756 (match_operand:SI 1 "const_int_operand" "n")))
4758 (and:SI (match_dup 0)
4759 (match_operand 2 "const_int_operand" "n")))]
4760 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4761 && INTVAL (operands[2]) != 255
4762 && INTVAL (operands[1]) > 15"
4764 ;; The m flag should be ignored, because this will be a *word* "and"
4769 cc_status.flags |= CC_NOT_NEGATIVE;
4771 return \"lsrq %1,%0\;and.w %2,%0\";
4779 ;; move [rx=rx+n],ry
4780 ;; when -128 <= n <= 127.
4781 ;; This will reduce the size of the assembler code for n = [-128..127],
4782 ;; and speed up accordingly.
4785 [(set (match_operand:SI 0 "register_operand" "=r")
4786 (plus:SI (match_operand:SI 1 "register_operand" "0")
4787 (match_operand:SI 2 "const_int_operand" "n")))
4788 (set (match_operand 3 "register_operand" "=r")
4789 (mem (match_dup 0)))]
4790 "GET_MODE (operands[3]) != DImode
4791 && REGNO (operands[3]) != REGNO (operands[0])
4792 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4793 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4794 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4795 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4796 "move.%s3 [%0=%1%S2],%3")
4798 ;; Vice versa: move ry,[rx=rx+n]
4801 [(set (match_operand:SI 0 "register_operand" "=r")
4802 (plus:SI (match_operand:SI 1 "register_operand" "0")
4803 (match_operand:SI 2 "const_int_operand" "n")))
4804 (set (mem (match_dup 0))
4805 (match_operand 3 "register_operand" "=r"))]
4806 "GET_MODE (operands[3]) != DImode
4807 && REGNO (operands[3]) != REGNO (operands[0])
4808 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4809 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4810 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4811 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
4812 "move.%s3 %3,[%0=%1%S2]"
4813 [(set_attr "cc" "none")])
4815 ;; As above, change:
4819 ;; op.d [rx=rx+n],ry
4820 ;; Saves when n = [-128..127].
4822 ;; Splitting and joining combinations for side-effect modes are slightly
4823 ;; out of hand. They probably will not save the time they take typing in,
4824 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4825 ;; the splits and peepholes as possible.
4828 [(set (match_operand:SI 0 "register_operand" "=r")
4829 (plus:SI (match_operand:SI 1 "register_operand" "0")
4830 (match_operand:SI 2 "const_int_operand" "n")))
4831 (set (match_operand 3 "register_operand" "=r")
4832 (match_operator 4 "cris_orthogonal_operator"
4834 (mem (match_dup 0))]))]
4835 "GET_MODE (operands[3]) != DImode
4836 && REGNO (operands[0]) != REGNO (operands[3])
4837 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4838 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4839 && INTVAL (operands[2]) >= -128
4840 && INTVAL (operands[2]) <= 127"
4841 "%x4.%s3 [%0=%1%S2],%3")
4843 ;; Sometimes, for some reason the pattern
4847 ;; will occur. Solve this, and likewise for to-memory.
4850 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4851 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Ri,r,>Ri"))
4853 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Ri,r")
4854 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Ri,r,0,0")))
4855 (set (match_operand 4 "register_operand" "=r,r,r,r")
4856 (mem (match_dup 0)))]
4857 "(rtx_equal_p (operands[2], operands[0])
4858 || rtx_equal_p (operands[3], operands[0]))
4859 && cris_side_effect_mode_ok (PLUS, operands, 0,
4860 (REG_S_P (operands[1])
4862 : (rtx_equal_p (operands[2], operands[0])
4864 (! REG_S_P (operands[1])
4866 : (rtx_equal_p (operands[2], operands[0])
4870 move.%s4 [%0=%1%S3],%4
4871 move.%s4 [%0=%3%S1],%4
4872 move.%s4 [%0=%1%S2],%4
4873 move.%s4 [%0=%2%S1],%4")
4875 ;; As above but to memory.
4878 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4879 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Ri,r,>Ri"))
4881 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Ri,r")
4882 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Ri,r,0,0")))
4883 (set (mem (match_dup 0))
4884 (match_operand 4 "register_operand" "=r,r,r,r"))]
4885 "(rtx_equal_p (operands[2], operands[0])
4886 || rtx_equal_p (operands[3], operands[0]))
4887 && cris_side_effect_mode_ok (PLUS, operands, 0,
4888 (REG_S_P (operands[1])
4890 : (rtx_equal_p (operands[2], operands[0])
4892 (! REG_S_P (operands[1])
4894 : (rtx_equal_p (operands[2], operands[0])
4898 move.%s4 %4,[%0=%1%S3]
4899 move.%s4 %4,[%0=%3%S1]
4900 move.%s4 %4,[%0=%1%S2]
4901 move.%s4 %4,[%0=%2%S1]"
4902 [(set_attr "cc" "none")])
4905 ;; As the move from-memory above, but with an operation.
4908 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4909 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Ri,r,>Ri"))
4911 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Ri,r")
4912 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Ri,r,0,0")))
4913 (set (match_operand 4 "register_operand" "=r,r,r,r")
4914 (match_operator 5 "cris_orthogonal_operator"
4916 (mem (match_dup 0))]))]
4917 "(rtx_equal_p (operands[2], operands[0])
4918 || rtx_equal_p (operands[3], operands[0]))
4919 && cris_side_effect_mode_ok (PLUS, operands, 0,
4920 (REG_S_P (operands[1])
4922 : (rtx_equal_p (operands[2], operands[0])
4924 (! REG_S_P (operands[1])
4926 : (rtx_equal_p (operands[2], operands[0])
4930 %x5.%s4 [%0=%1%S3],%4
4931 %x5.%s4 [%0=%3%S1],%4
4932 %x5.%s4 [%0=%1%S2],%4
4933 %x5.%s4 [%0=%2%S1],%4")
4935 ;; Same, but with swapped operands (and commutative operation).
4938 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
4939 (match_operand:SI 1 "cris_bdap_biap_operand" "r,>Ri,r,>Ri"))
4941 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "0,0,r>Ri,r")
4942 (match_operand:SI 3 "cris_bdap_biap_operand" "r>Ri,r,0,0")))
4943 (set (match_operand 4 "register_operand" "=r,r,r,r")
4944 (match_operator 5 "cris_commutative_orth_op"
4945 [(mem (match_dup 0))
4947 "(rtx_equal_p (operands[2], operands[0])
4948 || rtx_equal_p (operands[3], operands[0]))
4949 && cris_side_effect_mode_ok (PLUS, operands, 0,
4950 (REG_S_P (operands[1])
4952 : (rtx_equal_p (operands[2], operands[0])
4954 (! REG_S_P (operands[1])
4956 : (rtx_equal_p (operands[2], operands[0])
4960 %x5.%s4 [%0=%1%S3],%4
4961 %x5.%s4 [%0=%3%S1],%4
4962 %x5.%s4 [%0=%1%S2],%4
4963 %x5.%s4 [%0=%2%S1],%4")
4965 ;; Another spotted bad code:
4970 [(set (match_operand:SI 0 "register_operand" "=r")
4971 (match_operand:SI 1 "register_operand" "r"))
4972 (set (match_operand 2 "register_operand" "=r")
4973 (mem (match_dup 0)))]
4974 "REGNO (operands[0]) == REGNO (operands[2])
4975 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4977 [(set_attr "slottable" "yes")])
4979 ;; And a simple variant with extended operand.
4982 [(set (match_operand:SI 0 "register_operand" "=r")
4983 (match_operand:SI 1 "register_operand" "r"))
4984 (set (match_operand 2 "register_operand" "=r")
4985 (match_operator 3 "cris_extend_operator" [(mem (match_dup 0))]))]
4986 "REGNO (operands[0]) == REGNO (operands[2])
4987 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4988 "mov%e3.%m3 [%1],%0"
4989 [(set_attr "slottable" "yes")])
4991 ;; Here are all peepholes that have a saved testcase.
4992 ;; Do not add new peepholes without testcases.
4995 ;; move.d [r10+16],r9
4998 ;; and.d [r10+16],r12,r9
4999 ;; With generalization of the operation, the size and the addressing mode.
5000 ;; This seems to be the result of a quirk in register allocation
5001 ;; missing the three-operand cases when having different predicates.
5002 ;; Maybe that it matters that it is a commutative operation.
5003 ;; This pattern helps that situation, but there's still the increased
5004 ;; register pressure.
5005 ;; Note that adding the noncommutative variant did not show any matches
5006 ;; in ipps and cc1, so it's not here.
5009 [(set (match_operand 0 "register_operand" "=r,r,r,r")
5011 (match_operand:SI 1 "cris_bdap_biap_operand" "r,r>Ri,r,r>Ri")
5012 (match_operand:SI 2 "cris_bdap_biap_operand" "r>Ri,r,r>Ri,r"))))
5014 (match_operator 5 "cris_commutative_orth_op"
5015 [(match_operand 3 "register_operand" "0,0,r,r")
5016 (match_operand 4 "register_operand" "r,r,0,0")]))]
5017 "(rtx_equal_p (operands[3], operands[0])
5018 || rtx_equal_p (operands[4], operands[0]))
5019 && ! rtx_equal_p (operands[3], operands[4])
5020 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
5021 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
5023 %x5.%s0 [%1%S2],%4,%0
5024 %x5.%s0 [%2%S1],%4,%0
5025 %x5.%s0 [%1%S2],%3,%0
5026 %x5.%s0 [%2%S1],%3,%0")
5029 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
5031 ;; and.b some_byte,const,reg_32
5032 ;; where reg_32 is the destination of the "three-address" code optimally.
5034 ;; movu.b some_byte,reg_32
5035 ;; and.b const,reg_32
5036 ;; but is turns into:
5037 ;; move.b some_byte,reg_32
5038 ;; and.d const,reg_32
5042 [(set (match_operand:SI 0 "register_operand" "=r")
5043 (match_operand:SI 1 "nonimmediate_operand" "rm"))
5044 (set (match_operand:SI 2 "register_operand" "=0")
5045 (and:SI (match_dup 0)
5046 (match_operand:SI 3 "const_int_operand" "n")))]
5048 ;; Since the size of the memory access could be made different here,
5049 ;; don't do this for a mem-volatile access.
5051 "REGNO (operands[2]) == REGNO (operands[0])
5052 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
5053 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
5054 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
5057 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O'))
5058 return \"movu.%z3 %1,%0\;andq %b3,%0\";
5060 cc_status.flags |= CC_NOT_NEGATIVE;
5062 return \"movu.%z3 %1,%0\;and.%z3 %3,%0\";
5068 [(set (match_operand 0 "register_operand" "=r")
5069 (match_operand 1 "nonimmediate_operand" "rm"))
5070 (set (match_operand:SI 2 "register_operand" "=r")
5071 (and:SI (subreg:SI (match_dup 0) 0)
5072 (match_operand 3 "const_int_operand" "n")))]
5074 ;; Since the size of the memory access could be made different here,
5075 ;; don't do this for a mem-volatile access.
5077 "REGNO (operands[0]) == REGNO (operands[2])
5078 && INTVAL (operands[3]) > 0
5079 && INTVAL (operands[3]) <= 65535
5080 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
5081 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
5084 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O'))
5085 return \"movu.%z3 %1,%0\;andq %b3,%0\";
5087 cc_status.flags |= CC_NOT_NEGATIVE;
5089 return \"movu.%z3 %1,%0\;and.%z3 %3,%0\";
5094 ;; comment-start: ";; "
5095 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5096 ;; eval: (modify-syntax-entry ?[ "(]")
5097 ;; eval: (modify-syntax-entry ?] ")[")
5098 ;; eval: (modify-syntax-entry ?{ "(}")
5099 ;; eval: (modify-syntax-entry ?} "){")
5100 ;; eval: (setq indent-tabs-mode t)