1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
29 ;; The function cris_notice_update_cc in cris.c handles condition code
30 ;; updates for most instructions, helped by the "cc" attribute.
32 ;; There are several instructions that are orthogonal in size, and seems
33 ;; they could be matched by a single pattern without a specified size
34 ;; for the operand that is orthogonal. However, this did not work on
35 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
36 ;; constant is substituted into an operand, the actual mode must be
37 ;; deduced from the pattern. There is reasonable hope that that has been
38 ;; fixed, so FIXME: try again.
40 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
41 ;; are marked with a "!" constraint modifier to avoid being reloaded
42 ;; into. This is because gcc would otherwise prefer to use the constant
43 ;; pool and its offsettable address instead of reloading to an
44 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
45 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
47 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
48 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
49 ;; pointer). Thus the instructions that get into trouble have specific
50 ;; checks against matching frame_pointer_rtx.
51 ;; ??? But it should be re-checked for gcc > 2.7.2
52 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
54 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
55 ;; [rX=gotless_symbol].
56 ;; The movsi for a gotless symbol could be split (post reload).
59 ;; 0 PLT reference from call expansion: operand 0 is the address,
60 ;; the mode is VOIDmode. Always wrapped in CONST.
61 ;; 1 Stack frame deallocation barrier.
62 ;; 2 The address of the global offset table as a source operand.
66 (CRIS_UNSPEC_FRAME_DEALLOC 1)
72 (CRIS_STATIC_CHAIN_REGNUM 7)
80 ;; We need an attribute to define whether an instruction can be put in
81 ;; a branch-delay slot or not, and whether it has a delay slot.
83 ;; Branches and return instructions have a delay slot, and cannot
84 ;; themselves be put in a delay slot. This has changed *for short
85 ;; branches only* between architecture variants, but the possible win
86 ;; is presumed negligible compared to the added complexity of the machine
87 ;; description: one would have to add always-correct infrastructure to
88 ;; distinguish short branches.
90 ;; Whether an instruction can be put in a delay slot depends on the
91 ;; instruction (all short instructions except jumps and branches)
92 ;; and the addressing mode (must not be prefixed or referring to pc).
93 ;; In short, any "slottable" instruction must be 16 bit and not refer
94 ;; to pc, or alter it.
96 ;; The possible values are "yes", "no" and "has_slot". Yes/no means if
97 ;; the insn is slottable or not. Has_slot means that the insn is a
98 ;; return insn or branch insn (which are not considered slottable since
99 ;; that is generally true). Having the seemingly illogical value
100 ;; "has_slot" means we do not have to add another attribute just to say
101 ;; that an insn has a delay-slot, since it also infers that it is not
102 ;; slottable. Better names for the attribute were found to be longer and
103 ;; not add readability to the machine description.
105 ;; The default that is defined here for this attribute is "no", not
106 ;; slottable, not having a delay-slot, so there's no need to worry about
107 ;; it being wrong for non-branch and return instructions.
108 ;; The default could depend on the kind of insn and the addressing
109 ;; mode, but that would need more attributes and hairier, more error
112 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
113 ;; register. The constraints 'Q' and '>' together match all possible
114 ;; memory operands that are slottable.
115 ;; For other operands, you need to check if it has a valid "slottable"
116 ;; quick-immediate operand, where the particular signedness-variation
117 ;; may match the constraints 'I' or 'J'.), and include it in the
118 ;; constraint pattern for the slottable pattern. An alternative using
119 ;; only "r" constraints is most often slottable.
121 (define_attr "slottable" "no,yes,has_slot" (const_string "no"))
123 ;; We also need attributes to sanely determine the condition code
124 ;; state. See cris_notice_update_cc for how this is used.
126 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
128 ;; At the moment, this attribute is just used to help bb-reorder do its
129 ;; work; the default 0 doesn't help it. Many insns have other lengths,
130 ;; though none are shorter.
131 (define_attr "length" "" (const_int 2))
133 ;; A branch or return has one delay-slot. The instruction in the
134 ;; delay-slot is always executed, independent of whether the branch is
135 ;; taken or not. Note that besides setting "slottable" to "has_slot",
136 ;; there also has to be a "%#" at the end of a "delayed" instruction
137 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
138 ;; catch it and print a "nop" if necessary. This method was stolen from
141 (define_delay (eq_attr "slottable" "has_slot")
142 [(eq_attr "slottable" "yes") (nil) (nil)])
144 ;; Iterator definitions.
146 ;; For the "usual" pattern size alternatives.
147 (define_mode_macro BWD [SI HI QI])
148 (define_mode_macro WD [SI HI])
149 (define_mode_macro BW [HI QI])
150 (define_mode_attr S [(SI "HI") (HI "QI")])
151 (define_mode_attr s [(SI "hi") (HI "qi")])
152 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
153 (define_mode_attr mm [(SI ".w") (HI ".b")])
154 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
156 ;; For the sign_extend+zero_extend variants.
157 (define_code_macro szext [sign_extend zero_extend])
158 (define_code_attr u [(sign_extend "") (zero_extend "u")])
159 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
161 ;; For the shift variants.
162 (define_code_macro shift [ashiftrt lshiftrt ashift])
163 (define_code_macro shiftrt [ashiftrt lshiftrt])
164 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
165 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
167 ;; For conditional branches and sCC. We define an attribute by the
168 ;; same name as the macro, so the insn names here is seen as
169 ;; b<ncond>, b<ocond> etc. rather than b<code> b<code> etc.
170 (define_code_macro ncond [eq ne gtu ltu geu leu])
171 (define_code_attr ncond [(eq "eq") (ne "ne") (gtu "gtu") (ltu "ltu")
172 (geu "geu") (leu "leu")])
173 (define_code_macro ocond [gt le])
174 (define_code_attr ocond [(gt "gt") (le "le")])
175 (define_code_macro rcond [lt ge])
176 (define_code_attr rcond [(lt "lt") (ge "ge")])
177 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
178 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
179 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
180 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
181 (define_code_attr oCC [(lt "mi") (ge "pl")])
182 (define_code_attr roCC [(lt "pl") (ge "mi")])
184 ;; Operand and operator predicates.
186 (include "predicates.md")
192 ;; Allow register and offsettable mem operands only; post-increment is
193 ;; not worth the trouble.
197 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
199 "test.d %M0\;ax\;test.d %H0")
201 ;; No test insns with side-effect on the mem addressing.
203 ;; See note on cmp-insns with side-effects (or lack of them)
205 ;; Normal named test patterns from SI on.
206 ;; FIXME: Seems they should change to be in order smallest..largest.
208 (define_insn "tst<mode>"
210 (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m"))]
213 [(set_attr "slottable" "yes,yes,no")])
215 ;; It seems that the position of the sign-bit and the fact that 0.0 is
216 ;; all 0-bits would make "tstsf" a straight-forward implementation;
217 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
220 ;; FIXME: Do that some time; check next_cc0_user to determine if
221 ;; zero or negative is tested for.
225 ;; We could optimize the sizes of the immediate operands for various
226 ;; cases, but that is not worth it because of the very little usage of
227 ;; DImode for anything else but a structure/block-mode. Just do the
228 ;; obvious stuff for the straight-forward constraint letters.
232 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
233 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
236 cmpq %1,%M0\;ax\;cmpq 0,%H0
237 cmpq %1,%M0\;ax\;cmpq -1,%H0
238 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
239 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
240 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
241 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
242 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
244 ;; Note that compare insns with side effect addressing mode (e.g.):
246 ;; cmp.S [rx=ry+i],rz;
247 ;; cmp.S [%3=%1+%2],%0
249 ;; are *not* usable for gcc since the reloader *does not accept*
250 ;; cc0-changing insns with side-effects other than setting the condition
251 ;; codes. The reason is that the reload stage *may* cause another insn to
252 ;; be output after the main instruction, in turn invalidating cc0 for the
253 ;; insn using the test. (This does not apply to the CRIS case, since a
254 ;; reload for output -- move to memory -- does not change the condition
255 ;; code. Unfortunately we have no way to describe that at the moment. I
256 ;; think code would improve being in the order of one percent faster.
258 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
259 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
260 ;; constants, but sometimes gcc will find its way to use it for other
261 ;; (memory) operands. Avoid side-effect patterns, though (see above).
263 (define_insn "*cmp_ext<mode>"
266 (match_operand:SI 0 "register_operand" "r,r")
267 (match_operator:SI 2 "cris_extend_operator"
268 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
271 [(set_attr "slottable" "yes,no")])
273 ;; Swap operands; it seems the canonical look (if any) is not enforced.
275 ;; FIXME: Investigate that.
277 (define_insn "*cmp_swapext<mode>"
280 (match_operator:SI 2 "cris_extend_operator"
281 [(match_operand:BW 0 "memory_operand" "Q>,m")])
282 (match_operand:SI 1 "register_operand" "r,r")))]
284 "cmp%e2<m> %0,%1" ; The function cris_notice_update_cc knows about
285 ; swapped operands to compares.
286 [(set_attr "slottable" "yes,no")])
288 ;; The "normal" compare patterns, from SI on.
293 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, r,Q>,Q>,r,r,m,m")
294 (match_operand:SI 1 "general_operand" "I,r,Q>,M,M, r, P,g,M,r")))]
307 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])
309 (define_insn "cmp<mode>"
312 (match_operand:BW 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m")
313 (match_operand:BW 1 "general_operand" "r,Q>,M,M, r, g,M,r")))]
324 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
326 ;; Pattern matching the BTST insn.
327 ;; It is useful for "if (i & val)" constructs, where val is an exact
328 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
329 ;; of zeros starting at bit 0).
331 ;; SImode. This mode is the only one needed, since gcc automatically
332 ;; extends subregs for lower-size modes. FIXME: Add testcase.
336 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
337 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
338 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
339 ;; Either it is a single bit, or consecutive ones starting at 0.
340 "GET_CODE (operands[1]) == CONST_INT
341 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
342 && (REG_S_P (operands[0])
343 || (operands[1] == const1_rtx
344 && REG_S_P (operands[2])
345 && GET_CODE (operands[0]) == CONST_INT
346 && exact_log2 (INTVAL (operands[0])) >= 0))"
348 ;; The last "&&" condition above should be caught by some kind of
349 ;; canonicalization in gcc, but we can easily help with it here.
350 ;; It results from expressions of the type
351 ;; "power_of_2_value & (1 << y)".
353 ;; Since there may be codes with tests in on bits (in constant position)
354 ;; beyond the size of a word, handle that by assuming those bits are 0.
355 ;; GCC should handle that, but it's a matter of easily-added belts while
356 ;; having suspenders.
366 [(set_attr "slottable" "yes")])
370 ;; The whole mandatory movdi family is here; expander, "anonymous"
371 ;; recognizer and splitter. We're forced to have a movdi pattern,
372 ;; although GCC should be able to split it up itself. Normally it can,
373 ;; but if other insns have DI operands (as is the case here), reload
374 ;; must be able to generate or match a movdi. many testcases fail at
375 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
376 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
377 ;; However, a patch from Richard Kenner (similar to the cause of
378 ;; discussion at the URL above), indicates otherwise. See
379 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
380 ;; The truth has IMO is not been decided yet, so check from time to
381 ;; time by disabling the movdi patterns.
383 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
384 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
385 ;; A cmpdi RTX needs reloading (global):
386 ;; (insn 185 326 186 (set (cc0)
387 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
388 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
390 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
391 ;; out of the instruction (into a register), since one of the operands
392 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
393 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
394 ;; wrt. overlap). The bad things happen with the synthesis in
395 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
396 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
397 ;; 22 is recognized to have an equivalent in memory which is substituted
398 ;; straight in, and we end up with an unrecognizable insn:
399 ;; (insn 325 324 326 (set (reg:SI 9 r9)
400 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
401 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
403 ;; which is the first part of the reloaded synthesized "movdi".
404 ;; The right thing would be to add equivalent replacement locations for
405 ;; insn with pseudos that need more reloading. The question is where.
407 (define_expand "movdi"
408 [(set (match_operand:DI 0 "nonimmediate_operand" "")
409 (match_operand:DI 1 "general_operand" ""))]
412 if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
413 operands[1] = copy_to_mode_reg (DImode, operands[1]);
415 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
416 prefer to split up constants early, like this. The testcase in
417 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
418 resulting subreg sets when using the construct from mcore (as of FSF
419 CVS, version -r 1.5), and it believes that the high part (the last one
420 emitted) is the final value. This construct from romp seems more
421 robust, especially considering the head comments from
422 emit_no_conflict_block. */
423 if ((GET_CODE (operands[1]) == CONST_INT
424 || GET_CODE (operands[1]) == CONST_DOUBLE)
425 && ! reload_completed
426 && ! reload_in_progress)
429 rtx op0 = operands[0];
430 rtx op1 = operands[1];
433 emit_move_insn (operand_subword (op0, 0, 1, DImode),
434 operand_subword (op1, 0, 1, DImode));
435 emit_move_insn (operand_subword (op0, 1, 1, DImode),
436 operand_subword (op1, 1, 1, DImode));
437 insns = get_insns ();
440 emit_no_conflict_block (insns, op0, op1, 0, op1);
445 (define_insn "*movdi_insn"
446 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
447 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
448 "register_operand (operands[0], DImode)
449 || register_operand (operands[1], DImode)
450 || operands[1] == const0_rtx"
454 [(set (match_operand:DI 0 "nonimmediate_operand" "")
455 (match_operand:DI 1 "general_operand" ""))]
458 "operands[2] = cris_split_movdx (operands);")
460 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
461 ;; and move.S1 [rx=ry+i],rz
462 ;; Then movs.S1 and movu.S1 for both modes.
464 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
465 ;; FIXME: These could have anonymous mode for operand 0.
467 (define_insn "*mov_side<mode>_biap"
468 [(set (match_operand:BW 0 "register_operand" "=r,r")
470 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
471 (match_operand:SI 2 "const_int_operand" "n,n"))
472 (match_operand:SI 3 "register_operand" "r,r"))))
473 (set (match_operand:SI 4 "register_operand" "=*3,r")
474 (plus:SI (mult:SI (match_dup 1)
477 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
480 move<m> [%4=%3+%1%T2],%0")
482 (define_insn "*mov_sidesisf_biap"
483 [(set (match_operand 0 "register_operand" "=r,r,x,x")
485 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
486 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
487 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
488 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
489 (plus:SI (mult:SI (match_dup 1)
492 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
493 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
496 move.%s0 [%4=%3+%1%T2],%0
498 move [%4=%3+%1%T2],%0")
500 ;; move.S1 [rx=ry+i],rz
501 ;; avoiding move.S1 [ry=ry+i],rz
502 ;; and move.S1 [rz=ry+i],rz
503 ;; Note that "i" is allowed to be a register.
505 (define_insn "*mov_side<mode>"
506 [(set (match_operand:BW 0 "register_operand" "=r,r,r")
508 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
509 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
510 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
511 (plus:SI (match_dup 1)
513 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
515 if (which_alternative == 0
516 && (GET_CODE (operands[2]) != CONST_INT
517 || INTVAL (operands[2]) > 127
518 || INTVAL (operands[2]) < -128
519 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
520 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
522 return "move<m> [%3=%1%S2],%0";
525 (define_insn "*mov_sidesisf"
526 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x")
529 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r")
530 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn"))))
531 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r")
532 (plus:SI (match_dup 1)
534 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
535 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
537 if ((which_alternative == 0 || which_alternative == 3)
538 && (GET_CODE (operands[2]) != CONST_INT
539 || INTVAL (operands[2]) > 127
540 || INTVAL (operands[2]) < -128
541 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
542 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
544 if (which_alternative < 3)
545 return "move.%s0 [%3=%1%S2],%0";
546 return "move [%3=%1%S2],%0";
549 ;; Other way around; move to memory.
551 ;; Note that the condition (which for side-effect patterns is usually a
552 ;; call to cris_side_effect_mode_ok), isn't consulted for register
553 ;; allocation preferences -- constraints is the method for that. The
554 ;; drawback is that we can't exclude register allocation to cause
555 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
556 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
557 ;; Instead of that, we recognize and split the cases where dangerous
558 ;; register combinations are spotted: where a register is set in the
559 ;; side-effect, and used in the main insn. We don't handle the case where
560 ;; the set in the main insn overlaps the set in the side-effect; that case
561 ;; must be handled in gcc. We handle just the case where the set in the
562 ;; side-effect overlaps the input operand of the main insn (i.e. just
566 ;; move.s rz,[ry=rx+rw.S]
568 (define_insn "*mov_side<mode>_biap_mem"
569 [(set (mem:BW (plus:SI
570 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
571 (match_operand:SI 1 "const_int_operand" "n,n,n"))
572 (match_operand:SI 2 "register_operand" "r,r,r")))
573 (match_operand:BW 3 "register_operand" "r,r,r"))
574 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
575 (plus:SI (mult:SI (match_dup 0)
578 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
582 move<m> %3,[%4=%2+%0%T1]")
584 (define_insn "*mov_sidesisf_biap_mem"
586 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
587 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
588 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
589 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
590 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
591 (plus:SI (mult:SI (match_dup 0)
594 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
595 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
599 move.%s3 %3,[%4=%2+%0%T1]
602 move %3,[%4=%2+%0%T1]")
604 ;; Split for the case above where we're out of luck with register
605 ;; allocation (again, the condition isn't checked for that), and we end up
606 ;; with the set in the side-effect getting the same register as the input
611 [(set (match_operator
614 (mult:SI (match_operand:SI 0 "register_operand" "")
615 (match_operand:SI 1 "const_int_operand" ""))
616 (match_operand:SI 2 "register_operand" ""))])
617 (match_operand 3 "register_operand" ""))
618 (set (match_operand:SI 4 "register_operand" "")
619 (plus:SI (mult:SI (match_dup 0)
622 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
623 [(set (match_dup 5) (match_dup 3))
624 (set (match_dup 4) (match_dup 2))
626 (plus:SI (mult:SI (match_dup 0)
630 = replace_equiv_address (operands[6],
631 gen_rtx_PLUS (SImode,
632 gen_rtx_MULT (SImode,
637 ;; move.s rx,[ry=rz+i]
638 ;; FIXME: These could have anonymous mode for operand 2.
642 (define_insn "*mov_side<mode>_mem"
644 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r")
645 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn")))
646 (match_operand:BW 2 "register_operand" "r,r,r,r"))
647 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r")
648 (plus:SI (match_dup 0)
650 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
652 if (which_alternative == 0
653 && (GET_CODE (operands[1]) != CONST_INT
654 || INTVAL (operands[1]) > 127
655 || INTVAL (operands[1]) < -128
656 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
657 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
659 if (which_alternative == 1)
661 return "move<m> %2,[%3=%0%S1]";
666 (define_insn "*mov_sidesisf_mem"
670 0 "cris_bdap_operand" "%r,r,r,r,r,r,r,r")
672 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r>Rn,r>Rn,r,>Rn")))
673 (match_operand 2 "register_operand" "r,r,r,r,x,x,x,x"))
674 (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r,*0,!2,r,r")
675 (plus:SI (match_dup 0)
677 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
678 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
680 if ((which_alternative == 0 || which_alternative == 4)
681 && (GET_CODE (operands[1]) != CONST_INT
682 || INTVAL (operands[1]) > 127
683 || INTVAL (operands[1]) < -128
684 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
685 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
687 if (which_alternative == 1 || which_alternative == 5)
689 if (which_alternative < 4)
690 return "move.%s2 %2,[%3=%0%S1]";
691 return "move %2,[%3=%0%S1]";
694 ;; Like the biap case, a split where the set in the side-effect gets the
695 ;; same register as the input register to the main insn, since the
696 ;; condition isn't checked at register allocation.
700 [(set (match_operator
703 (match_operand:SI 0 "cris_bdap_operand" "")
704 (match_operand:SI 1 "cris_bdap_operand" ""))])
705 (match_operand 2 "register_operand" ""))
706 (set (match_operand:SI 3 "register_operand" "")
707 (plus:SI (match_dup 0) (match_dup 1)))])]
708 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
709 [(set (match_dup 4) (match_dup 2))
710 (set (match_dup 3) (match_dup 0))
711 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
714 ;; Clear memory side-effect patterns. It is hard to get to the mode if
715 ;; the MEM was anonymous, so there will be one for each mode.
717 ;; clear.[bwd] [ry=rx+rw.s2]
719 (define_insn "*clear_side<mode>_biap"
720 [(set (mem:BWD (plus:SI
721 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
722 (match_operand:SI 1 "const_int_operand" "n,n"))
723 (match_operand:SI 2 "register_operand" "r,r")))
725 (set (match_operand:SI 3 "register_operand" "=*2,r")
726 (plus:SI (mult:SI (match_dup 0)
729 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
732 clear<m> [%3=%2+%0%T1]")
734 ;; clear.[bwd] [ry=rz+i]
736 (define_insn "*clear_side<mode>"
738 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r")
739 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))
741 (set (match_operand:SI 2 "register_operand" "=*0,r,r")
742 (plus:SI (match_dup 0)
744 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
746 if (which_alternative == 0
747 && (GET_CODE (operands[1]) != CONST_INT
748 || INTVAL (operands[1]) > 127
749 || INTVAL (operands[1]) < -128
750 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
751 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
753 return "clear<m> [%2=%0%S1]";
756 ;; Normal move patterns from SI on.
758 (define_expand "movsi"
760 (match_operand:SI 0 "nonimmediate_operand" "")
761 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
764 /* If the output goes to a MEM, make sure we have zero or a register as
766 if (GET_CODE (operands[0]) == MEM
767 && ! REG_S_P (operands[1])
768 && operands[1] != const0_rtx
770 operands[1] = force_reg (SImode, operands[1]);
772 /* If we're generating PIC and have an incoming symbol, validize it to a
773 general operand or something that will match a special pattern.
775 FIXME: Do we *have* to recognize anything that would normally be a
776 valid symbol? Can we exclude global PIC addresses with an added
779 && CONSTANT_ADDRESS_P (operands[1])
780 && cris_symbol (operands[1]))
782 /* We must have a register as destination for what we're about to
783 do, and for the patterns we generate. */
784 if (! REG_S_P (operands[0]))
786 CRIS_ASSERT (!no_new_pseudos);
787 operands[1] = force_reg (SImode, operands[1]);
791 /* Mark a needed PIC setup for a LABEL_REF:s coming in here:
792 they are so rare not-being-branch-targets that we don't mark
793 a function as needing PIC setup just because we have
794 inspected LABEL_REF:s as operands. It is only in
795 __builtin_setjmp and such that we can get a LABEL_REF
796 assigned to a register. */
797 if (GET_CODE (operands[1]) == LABEL_REF)
798 current_function_uses_pic_offset_table = 1;
800 /* We don't have to do anything for global PIC operands; they
801 look just like ``[rPIC+sym]''. */
802 if (! cris_got_symbol (operands[1])
803 /* We don't do anything for local PIC operands; we match
804 that with a special alternative. */
805 && ! cris_gotless_symbol (operands[1]))
807 /* We get here when we have to change something that would
808 be recognizable if it wasn't PIC. A ``sym'' is ok for
809 PIC symbols both with and without a GOT entry. And ``sym
810 + offset'' is ok for local symbols, so the only thing it
811 could be, is a global symbol with an offset. Check and
813 rtx sym = get_related_value (operands[1]);
814 HOST_WIDE_INT offs = get_integer_term (operands[1]);
816 CRIS_ASSERT (sym != NULL_RTX && offs != 0);
818 emit_move_insn (operands[0], sym);
819 if (expand_binop (SImode, add_optab, operands[0],
820 GEN_INT (offs), operands[0], 0,
821 OPTAB_LIB_WIDEN) != operands[0])
822 internal_error ("expand_binop failed in movsi");
829 (define_insn "*movsi_internal"
831 (match_operand:SI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
833 ;; FIXME: We want to put S last, but apparently g matches S.
834 ;; It's a bug: an S is not a general_operand and shouldn't match g.
835 "cris_general_operand_or_gotless_symbol" "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
838 /* Better to have c-switch here; it is worth it to optimize the size of
839 move insns. The alternative would be to try to find more constraint
840 letters. FIXME: Check again. It seems this could shrink a bit. */
841 switch (which_alternative)
848 return "move.d %1,%0";
854 return "move %d1,%0";
861 /* Constants -32..31 except 0. */
863 return "moveq %1,%0";
865 /* We can win a little on constants -32768..-33, 32..65535. */
867 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
869 if (INTVAL (operands[1]) < 256)
870 return "movu.b %1,%0";
871 return "movu.w %1,%0";
873 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
875 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
876 return "movs.b %1,%0";
877 return "movs.w %1,%0";
879 return "move.d %1,%0";
882 /* FIXME: Try and split this into pieces GCC makes better code of,
883 than this multi-insn pattern. Synopsis: wrap the GOT-relative
884 symbol into an unspec, and when PIC, recognize the unspec
885 everywhere a symbol is normally recognized. (The PIC register
886 should be recognized by GCC as pic_offset_table_rtx when needed
887 and similar for PC.) Each component can then be optimized with
888 the rest of the code; it should be possible to have a constant
889 term added on an unspec. Don't forget to add a REG_EQUAL (or
890 is it REG_EQUIV) note to the destination. It might not be
893 Note that the 'v' modifier makes PLT references be output as
894 sym:PLT rather than [rPIC+sym:GOTPLT]. */
895 if (GET_CODE (operands[1]) == UNSPEC
896 && XINT (operands[1], 1) == CRIS_UNSPEC_GOT)
898 /* We clobber cc0 rather than set it to GOT. Should not
901 CRIS_ASSERT (REGNO (operands[0]) == PIC_OFFSET_TABLE_REGNUM);
903 return "move.d $pc,%0\;sub.d .:GOTOFF,%0";
906 return "move.d %v1,%0\;add.d %P1,%0";
909 return "BOGUS: %1 to %0";
912 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
913 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
915 ;; Extend operations with side-effect from mem to register, using
916 ;; MOVS/MOVU. These are from mem to register only.
922 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
923 ;; HImode by itself? Perhaps use only anonymous modes?
925 (define_insn "*ext_sideqihi_biap"
926 [(set (match_operand:HI 0 "register_operand" "=r,r")
928 5 "cris_extend_operator"
930 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
931 (match_operand:SI 2 "const_int_operand" "n,n"))
932 (match_operand:SI 3 "register_operand" "r,r")))]))
933 (set (match_operand:SI 4 "register_operand" "=*3,r")
934 (plus:SI (mult:SI (match_dup 1)
937 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
940 mov%e5.%m5 [%4=%3+%1%T2],%0")
942 (define_insn "*ext_side<mode>si_biap"
943 [(set (match_operand:SI 0 "register_operand" "=r,r")
945 5 "cris_extend_operator"
947 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
948 (match_operand:SI 2 "const_int_operand" "n,n"))
949 (match_operand:SI 3 "register_operand" "r,r")))]))
950 (set (match_operand:SI 4 "register_operand" "=*3,r")
951 (plus:SI (mult:SI (match_dup 1)
954 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
957 mov%e5<m> [%4=%3+%1%T2],%0")
959 ;; Same but [rx=ry+i]
963 (define_insn "*ext_sideqihi"
964 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
966 4 "cris_extend_operator"
968 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
969 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
970 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
971 (plus:SI (match_dup 1)
973 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
975 if (which_alternative == 0
976 && (GET_CODE (operands[2]) != CONST_INT
977 || INTVAL (operands[2]) > 127
978 || INTVAL (operands[2]) < -128
979 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
980 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
982 return "mov%e4.%m4 [%3=%1%S2],%0";
985 (define_insn "*ext_side<mode>si"
986 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
988 4 "cris_extend_operator"
990 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r")
991 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
992 (set (match_operand:SI 3 "register_operand" "=*1,r,r")
993 (plus:SI (match_dup 1)
995 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
997 if (which_alternative == 0
998 && (GET_CODE (operands[2]) != CONST_INT
999 || INTVAL (operands[2]) > 127
1000 || INTVAL (operands[2]) < -128
1001 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1002 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1004 return "mov%e4<m> [%3=%1%S2],%0";
1007 ;; FIXME: See movsi.
1009 (define_insn "movhi"
1011 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1012 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1015 switch (which_alternative)
1022 return "move.w %1,%0";
1025 return "move %1,%0";
1029 return "clear.w %0";
1031 return "moveq %1,%0";
1034 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1036 if (INTVAL (operands[1]) > 0)
1037 return "movu.b %1,%0";
1038 return "movs.b %1,%0";
1040 return "move.w %1,%0";
1042 return "movEq %b1,%0";
1044 return "BOGUS: %1 to %0";
1047 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1048 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1050 (define_insn "movstricthi"
1053 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1054 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1065 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1067 (define_expand "reload_in<mode>"
1068 [(set (match_operand:BW 2 "register_operand" "=r")
1069 (match_operand:BW 1 "memory_operand" "m"))
1070 (set (match_operand:BW 0 "register_operand" "=x")
1075 (define_expand "reload_out<mode>"
1076 [(set (match_operand:BW 2 "register_operand" "=r")
1077 (match_operand:BW 1 "register_operand" "x"))
1078 (set (match_operand:BW 0 "memory_operand" "=m")
1083 (define_insn "movqi"
1084 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1085 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1100 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1101 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1103 (define_insn "movstrictqi"
1104 [(set (strict_low_part
1105 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1106 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1117 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1119 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1120 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1121 ;; all ones); the worthwhile one is "0.0".
1122 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1124 (define_insn "movsf"
1125 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1126 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1143 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1145 ;; Note that the memory layout of the registers is the reverse of that
1146 ;; of the standard patterns "load_multiple" and "store_multiple".
1147 (define_insn "*cris_load_multiple"
1148 [(match_parallel 0 "cris_load_multiple_op"
1149 [(set (match_operand:SI 1 "register_operand" "=r,r")
1150 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1153 [(set_attr "cc" "none")
1154 (set_attr "slottable" "yes,no")
1155 ;; Not true, but setting the length to 0 causes return sequences (ret
1156 ;; movem) to have the cost they had when (return) included the movem
1157 ;; and reduces the performance penalty taken for needing to emit an
1158 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1159 ;; FIXME: temporary change until all insn lengths are correctly
1160 ;; described. FIXME: have better target control over bb-reorder.
1161 (set_attr "length" "0")])
1163 (define_insn "*cris_store_multiple"
1164 [(match_parallel 0 "cris_store_multiple_op"
1165 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1166 (match_operand:SI 1 "register_operand" "r,r"))])]
1169 [(set_attr "cc" "none")
1170 (set_attr "slottable" "yes,no")])
1173 ;; Sign- and zero-extend insns with standard names.
1174 ;; Those for integer source operand are ordered with the widest source
1179 (define_insn "extendsidi2"
1180 [(set (match_operand:DI 0 "register_operand" "=r")
1181 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1183 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1185 (define_insn "extend<mode>di2"
1186 [(set (match_operand:DI 0 "register_operand" "=r")
1187 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1189 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1191 (define_insn "extend<mode>si2"
1192 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1193 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1196 [(set_attr "slottable" "yes,yes,no")])
1198 ;; To do a byte->word extension, extend to dword, exept that the top half
1199 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1201 (define_insn "extendqihi2"
1202 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1203 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1206 [(set_attr "slottable" "yes,yes,no")])
1209 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1210 ;; specify them here.
1212 (define_insn "zero_extend<mode>si2"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1215 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1218 [(set_attr "slottable" "yes,yes,no")])
1220 ;; Same comment as sign-extend QImode to HImode above applies.
1222 (define_insn "zero_extendqihi2"
1223 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1225 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1228 [(set_attr "slottable" "yes,yes,no")])
1230 ;; All kinds of arithmetic and logical instructions.
1232 ;; First, anonymous patterns to match addressing modes with
1235 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1239 (define_insn "*op_side<mode>_biap"
1240 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1242 6 "cris_orthogonal_operator"
1243 [(match_operand:BWD 1 "register_operand" "0,0")
1245 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1246 (match_operand:SI 3 "const_int_operand" "n,n"))
1247 (match_operand:SI 4 "register_operand" "r,r")))]))
1248 (set (match_operand:SI 5 "register_operand" "=*4,r")
1249 (plus:SI (mult:SI (match_dup 2)
1252 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1255 %x6<m> [%5=%4+%2%T3],%0")
1257 ;; [rx=ry+i] ([%4=%2+%3])
1259 (define_insn "*op_side<mode>"
1260 [(set (match_operand:BWD 0 "register_operand" "=r,r,r")
1262 5 "cris_orthogonal_operator"
1263 [(match_operand:BWD 1 "register_operand" "0,0,0")
1265 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1266 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]))
1267 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1268 (plus:SI (match_dup 2)
1270 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1272 if (which_alternative == 0
1273 && (GET_CODE (operands[3]) != CONST_INT
1274 || INTVAL (operands[3]) > 127
1275 || INTVAL (operands[3]) < -128
1276 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1277 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1279 return "%x5<m> [%4=%2%S3],%0";
1282 ;; To match all cases for commutative operations we may have to have the
1283 ;; following pattern for add, or & and. I do not know really, but it does
1284 ;; not break anything.
1286 ;; FIXME: This really ought to be checked.
1288 ;; op.S [rx=ry+I],rz;
1292 (define_insn "*op_swap_side<mode>_biap"
1293 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1295 6 "cris_commutative_orth_op"
1297 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1298 (match_operand:SI 3 "const_int_operand" "n,n"))
1299 (match_operand:SI 4 "register_operand" "r,r")))
1300 (match_operand:BWD 1 "register_operand" "0,0")]))
1301 (set (match_operand:SI 5 "register_operand" "=*4,r")
1302 (plus:SI (mult:SI (match_dup 2)
1305 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1308 %x6<m> [%5=%4+%2%T3],%0")
1310 ;; [rx=ry+i] ([%4=%2+%3])
1311 ;; FIXME: These could have anonymous mode for operand 0.
1315 (define_insn "*op_swap_side<mode>"
1316 [(set (match_operand:BWD 0 "register_operand" "=r,r,r")
1318 5 "cris_commutative_orth_op"
1320 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1321 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))
1322 (match_operand:BWD 1 "register_operand" "0,0,0")]))
1323 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1324 (plus:SI (match_dup 2)
1326 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1328 if (which_alternative == 0
1329 && (GET_CODE (operands[3]) != CONST_INT
1330 || INTVAL (operands[3]) > 127
1331 || INTVAL (operands[3]) < -128
1332 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1333 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1335 return "%x5<m> [%4=%2%S3],%0";
1338 ;; Add operations, standard names.
1340 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1341 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1343 (define_insn "adddi3"
1344 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1345 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1346 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1349 addq %2,%M0\;ax\;addq 0,%H0
1350 subq %n2,%M0\;ax\;subq 0,%H0
1351 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1352 add.d %M2,%M0\;ax\;add.d %H2,%H0
1353 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1355 (define_insn "addsi3"
1356 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r, r")
1358 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0,r, r")
1359 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
1361 ;; The last constraint is due to that after reload, the '%' is not
1362 ;; honored, and canonicalization doesn't care about keeping the same
1363 ;; register as in destination. This will happen after insn splitting.
1364 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1368 switch (which_alternative)
1372 return "add.d %2,%0";
1374 return "addq %2,%0";
1376 return "subq %n2,%0";
1378 /* 'Known value', but not in -63..63.
1379 Check if addu/subu may be used. */
1380 if (INTVAL (operands[2]) > 0)
1382 if (INTVAL (operands[2]) < 256)
1383 return "addu.b %2,%0";
1384 if (INTVAL (operands[2]) < 65536)
1385 return "addu.w %2,%0";
1389 if (INTVAL (operands[2]) >= -255)
1390 return "subu.b %n2,%0";
1391 if (INTVAL (operands[2]) >= -65535)
1392 return "subu.w %n2,%0";
1394 return "add.d %2,%0";
1396 return "add.d %2,%1,%0";
1398 return "add.d %2,%0";
1400 return "add.d %1,%0";
1402 return "BOGUS addsi %2+%1 to %0";
1405 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
1407 (define_insn "addhi3"
1408 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1409 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1410 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1419 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1420 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1422 (define_insn "addqi3"
1423 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1424 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1425 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1435 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1436 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1440 ;; Note that because of insn canonicalization these will *seldom* but
1441 ;; rarely be used with a known constant as an operand.
1443 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1444 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1446 (define_insn "subdi3"
1447 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1448 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1449 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1452 subq %2,%M0\;ax\;subq 0,%H0
1453 addq %n2,%M0\;ax\;addq 0,%H0
1454 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1455 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1456 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1458 (define_insn "subsi3"
1459 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1461 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1462 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1465 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1466 ;; But then again, %2 should not be negative.
1477 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1479 (define_insn "sub<mode>3"
1480 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
1481 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
1482 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
1491 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1492 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1494 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
1495 ;; Although these perform sign/zero-extension to SImode, they are
1496 ;; equally applicable for the HImode case.
1497 ;; FIXME: Check; GCC should handle the widening.
1498 ;; Note that these must be located after the normal add/sub patterns,
1499 ;; so not to get constants into any less specific operands.
1501 ;; Extend with add/sub and side-effect.
1503 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
1505 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
1508 ;; FIXME: GCC should widen.
1510 (define_insn "*extopqihi_side_biap"
1511 [(set (match_operand:HI 0 "register_operand" "=r,r")
1513 6 "cris_additive_operand_extend_operator"
1514 [(match_operand:HI 1 "register_operand" "0,0")
1516 7 "cris_extend_operator"
1518 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1519 (match_operand:SI 3 "const_int_operand" "n,n"))
1520 (match_operand:SI 4 "register_operand" "r,r")))])]))
1521 (set (match_operand:SI 5 "register_operand" "=*4,r")
1522 (plus:SI (mult:SI (match_dup 2)
1525 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1528 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1530 (define_insn "*extop<mode>si_side_biap"
1531 [(set (match_operand:SI 0 "register_operand" "=r,r")
1533 6 "cris_operand_extend_operator"
1534 [(match_operand:SI 1 "register_operand" "0,0")
1536 7 "cris_extend_operator"
1538 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1539 (match_operand:SI 3 "const_int_operand" "n,n"))
1540 (match_operand:SI 4 "register_operand" "r,r")))])]))
1541 (set (match_operand:SI 5 "register_operand" "=*4,r")
1542 (plus:SI (mult:SI (match_dup 2)
1545 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1546 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1549 %x6%e7<m> [%5=%4+%2%T3],%0")
1556 (define_insn "*extopqihi_side"
1557 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1559 5 "cris_additive_operand_extend_operator"
1560 [(match_operand:HI 1 "register_operand" "0,0,0")
1562 6 "cris_extend_operator"
1564 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1565 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
1567 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1568 (plus:SI (match_dup 2)
1570 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1572 if (which_alternative == 0
1573 && (GET_CODE (operands[3]) != CONST_INT
1574 || INTVAL (operands[3]) > 127
1575 || INTVAL (operands[3]) < -128
1576 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1577 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1579 return "%x5%e6.%m6 [%4=%2%S3],%0";
1582 (define_insn "*extop<mode>si_side"
1583 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1585 5 "cris_operand_extend_operator"
1586 [(match_operand:SI 1 "register_operand" "0,0,0")
1588 6 "cris_extend_operator"
1590 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1591 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")
1593 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1594 (plus:SI (match_dup 2)
1596 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
1597 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1599 if (which_alternative == 0
1600 && (GET_CODE (operands[3]) != CONST_INT
1601 || INTVAL (operands[3]) > 127
1602 || INTVAL (operands[3]) < -128
1603 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1604 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1606 return "%x5%e6<m> [%4=%2%S3],%0";
1610 ;; As with op.S we may have to add special pattern to match commuted
1611 ;; operands to adds/addu and bound
1613 ;; adds/addu/bound [rx=ry+rz.S]
1616 ;; FIXME: GCC should widen.
1618 (define_insn "*extopqihi_swap_side_biap"
1619 [(set (match_operand:HI 0 "register_operand" "=r,r")
1622 6 "cris_extend_operator"
1624 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1625 (match_operand:SI 3 "const_int_operand" "n,n"))
1626 (match_operand:SI 4 "register_operand" "r,r")))])
1627 (match_operand:HI 1 "register_operand" "0,0")))
1628 (set (match_operand:SI 5 "register_operand" "=*4,r")
1629 (plus:SI (mult:SI (match_dup 2)
1632 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1635 add%e6.b [%5=%4+%2%T3],%0")
1637 (define_insn "*extop<mode>si_swap_side_biap"
1638 [(set (match_operand:SI 0 "register_operand" "=r,r")
1640 7 "cris_plus_or_bound_operator"
1642 6 "cris_extend_operator"
1644 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1645 (match_operand:SI 3 "const_int_operand" "n,n"))
1646 (match_operand:SI 4 "register_operand" "r,r")))])
1647 (match_operand:SI 1 "register_operand" "0,0")]))
1648 (set (match_operand:SI 5 "register_operand" "=*4,r")
1649 (plus:SI (mult:SI (match_dup 2)
1652 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
1653 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1656 %x7%e6<m> [%5=%4+%2%T3],%0")
1659 ;; FIXME: GCC should widen.
1663 (define_insn "*extopqihi_swap_side"
1664 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1667 5 "cris_extend_operator"
1669 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1670 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
1671 (match_operand:HI 1 "register_operand" "0,0,0")))
1672 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1673 (plus:SI (match_dup 2)
1675 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1677 if (which_alternative == 0
1678 && (GET_CODE (operands[3]) != CONST_INT
1679 || INTVAL (operands[3]) > 127
1680 || INTVAL (operands[3]) < -128
1681 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1682 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1684 return "add%e5.b [%4=%2%S3],%0";
1687 (define_insn "*extop<mode>si_swap_side"
1688 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1690 6 "cris_plus_or_bound_operator"
1692 5 "cris_extend_operator"
1694 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r")
1695 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])
1696 (match_operand:SI 1 "register_operand" "0,0,0")]))
1697 (set (match_operand:SI 4 "register_operand" "=*2,r,r")
1698 (plus:SI (match_dup 2)
1700 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
1701 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1703 if (which_alternative == 0
1704 && (GET_CODE (operands[3]) != CONST_INT
1705 || INTVAL (operands[3]) > 127
1706 || INTVAL (operands[3]) < -128
1707 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1708 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1710 return "%x6%e5<m> [%4=%2%S3],%0";
1713 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
1716 ;; FIXME: GCC should widen.
1718 (define_insn "*extopqihi"
1719 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1721 3 "cris_additive_operand_extend_operator"
1722 [(match_operand:HI 1 "register_operand" "0,0,0,r")
1724 4 "cris_extend_operator"
1725 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
1726 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
1727 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
1732 %x3%e4.%m4 %2,%1,%0"
1733 [(set_attr "slottable" "yes,yes,no,no")
1734 (set_attr "cc" "clobber")])
1738 (define_insn "*extop<mode>si"
1739 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1741 3 "cris_operand_extend_operator"
1742 [(match_operand:SI 1 "register_operand" "0,0,0,r")
1744 4 "cris_extend_operator"
1745 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
1746 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
1747 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
1748 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
1754 [(set_attr "slottable" "yes,yes,no,no")])
1757 ;; As with the side-effect patterns, may have to have swapped operands for add.
1758 ;; FIXME: *should* be redundant to gcc.
1762 (define_insn "*extopqihi_swap"
1763 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1766 3 "cris_extend_operator"
1767 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
1768 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
1769 "operands[1] != frame_pointer_rtx"
1775 [(set_attr "slottable" "yes,yes,no,no")
1776 (set_attr "cc" "clobber")])
1778 (define_insn "*extop<mode>si_swap"
1779 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1781 4 "cris_plus_or_bound_operator"
1783 3 "cris_extend_operator"
1784 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
1785 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
1786 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
1787 && operands[1] != frame_pointer_rtx"
1793 [(set_attr "slottable" "yes,yes,no,no")])
1795 ;; This is the special case when we use what corresponds to the
1796 ;; instruction above in "casesi". Do *not* change it to use the generic
1797 ;; pattern and "REG 15" as pc; I did that and it led to madness and
1798 ;; maintenance problems: Instead of (as imagined) recognizing and removing
1799 ;; or replacing this pattern with something simpler, other variant
1800 ;; patterns were recognized or combined, including some prefix variants
1801 ;; where the value in pc is not that of the next instruction (which means
1802 ;; this instruction actually *is* special and *should* be marked as such).
1803 ;; When switching from the "generic pattern match" approach to this simpler
1804 ;; approach, there were insignificant differences in gcc, ipps and
1805 ;; product code, somehow due to scratching reload behind the ear or
1806 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
1807 ;; product code became .001% smaller but "looked better". The testcase
1808 ;; "ipps" was just different at register allocation).
1810 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
1811 ;; pattern with the default-label as the else, with the "if" being
1812 ;; index-is-less-than the max number of cases plus one. The default-label
1813 ;; is attached to the end of the case-table at time of output.
1815 (define_insn "*casesi_adds_w"
1818 (ltu (match_operand:SI 0 "register_operand" "r")
1819 (match_operand:SI 1 "const_int_operand" "n"))
1820 (plus:SI (sign_extend:SI
1822 (plus:SI (mult:SI (match_dup 0) (const_int 2))
1825 (label_ref (match_operand 2 "" ""))))
1826 (use (label_ref (match_operand 3 "" "")))]
1828 "operands[0] != frame_pointer_rtx"
1830 "adds.w [$pc+%0.w],$pc"
1831 [(set_attr "cc" "clobber")])
1833 ;; Multiply instructions.
1835 ;; Sometimes powers of 2 (which are normally canonicalized to a
1836 ;; left-shift) appear here, as a result of address reloading.
1837 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
1839 ;; FIXME: This may be unnecessary now.
1840 ;; Explicitly named for convenience of having a gen_... function.
1842 (define_insn "addi_mul"
1843 [(set (match_operand:SI 0 "register_operand" "=r")
1845 (match_operand:SI 1 "register_operand" "%0")
1846 (match_operand:SI 2 "const_int_operand" "n")))]
1847 "operands[0] != frame_pointer_rtx
1848 && operands[1] != frame_pointer_rtx
1849 && GET_CODE (operands[2]) == CONST_INT
1850 && (INTVAL (operands[2]) == 2
1851 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
1852 || INTVAL (operands[2]) == 5)"
1854 if (INTVAL (operands[2]) == 2)
1856 else if (INTVAL (operands[2]) == 4)
1858 else if (INTVAL (operands[2]) == 3)
1859 return "addi %0.w,%0";
1860 else if (INTVAL (operands[2]) == 5)
1861 return "addi %0.d,%0";
1862 return "BAD: adr_mulsi: %0=%1*%2";
1864 [(set_attr "slottable" "yes")
1865 ;; No flags are changed if this insn is "addi", but it does not seem
1866 ;; worth the trouble to distinguish that to the lslq cases.
1867 (set_attr "cc" "clobber")])
1869 ;; The addi insn as it is normally used.
1871 (define_insn "*addi"
1872 [(set (match_operand:SI 0 "register_operand" "=r")
1874 (mult:SI (match_operand:SI 2 "register_operand" "r")
1875 (match_operand:SI 3 "const_int_operand" "n"))
1876 (match_operand:SI 1 "register_operand" "0")))]
1877 "operands[0] != frame_pointer_rtx
1878 && operands[1] != frame_pointer_rtx
1879 && GET_CODE (operands[3]) == CONST_INT
1880 && (INTVAL (operands[3]) == 1
1881 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
1883 [(set_attr "slottable" "yes")
1884 (set_attr "cc" "none")])
1886 ;; The mstep instruction. Probably not useful by itself; it's to
1887 ;; non-linear wrt. the other insns. We used to expand to it, so at least
1890 (define_insn "mstep_shift"
1891 [(set (match_operand:SI 0 "register_operand" "=r")
1893 (lt:SI (cc0) (const_int 0))
1894 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1896 (match_operand:SI 2 "register_operand" "r"))
1897 (ashift:SI (match_operand:SI 3 "register_operand" "0")
1901 [(set_attr "slottable" "yes")])
1903 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
1904 ;; to canonicalize the multiplications.
1906 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
1908 (define_insn "mstep_mul"
1909 [(set (match_operand:SI 0 "register_operand" "=r")
1911 (lt:SI (cc0) (const_int 0))
1912 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1914 (match_operand:SI 2 "register_operand" "r"))
1915 (mult:SI (match_operand:SI 3 "register_operand" "0")
1917 "operands[0] != frame_pointer_rtx
1918 && operands[1] != frame_pointer_rtx
1919 && operands[2] != frame_pointer_rtx
1920 && operands[3] != frame_pointer_rtx"
1922 [(set_attr "slottable" "yes")])
1924 (define_insn "<u>mul<s><mode>3"
1925 [(set (match_operand:WD 0 "register_operand" "=r")
1927 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
1928 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
1929 (clobber (match_scratch:SI 3 "=h"))]
1930 "TARGET_HAS_MUL_INSNS"
1931 "%!mul<su><mm> %2,%0"
1932 [(set (attr "slottable")
1933 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
1935 (const_string "yes")))
1936 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
1937 ;; For muls.b, this really extends to SImode, so cc should be
1938 ;; considered clobbered.
1939 ;; For muls.w, it's just N unusable here, but let's be safe.
1940 (set_attr "cc" "clobber")])
1942 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
1943 ;; confused and will erroneously use it instead of umulhisi3, failing (at
1944 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
1945 ;; Inspection of optab code shows that there must be only one widening
1946 ;; multiplication per mode widened to.
1948 (define_insn "mulsi3"
1949 [(set (match_operand:SI 0 "register_operand" "=r")
1950 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1951 (match_operand:SI 2 "register_operand" "r")))
1952 (clobber (match_scratch:SI 3 "=h"))]
1953 "TARGET_HAS_MUL_INSNS"
1955 [(set (attr "slottable")
1956 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
1958 (const_string "yes")))
1959 ;; Just N unusable here, but let's be safe.
1960 (set_attr "cc" "clobber")])
1962 ;; A few multiply variations.
1964 ;; When needed, we can get the high 32 bits from the overflow
1965 ;; register. We don't care to split and optimize these.
1967 ;; Note that cc0 is still valid after the move-from-overflow-register
1968 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
1970 (define_insn "<u>mulsidi3"
1971 [(set (match_operand:DI 0 "register_operand" "=r")
1973 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
1974 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
1975 (clobber (match_scratch:SI 3 "=h"))]
1976 "TARGET_HAS_MUL_INSNS"
1977 "%!mul<su>.d %2,%M0\;move $mof,%H0")
1979 ;; These two patterns may be expressible by other means, perhaps by making
1980 ;; [u]?mulsidi3 a define_expand.
1982 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
1983 ;; cause a move into the clobbered register *before* the insn, then
1984 ;; after the insn, mof is moved too, rather than the clobber assigned
1985 ;; the last mof target. This became apparent when making MOF and SRP
1986 ;; visible registers, with the necessary tweak to smulsi3_highpart.
1987 ;; Because these patterns are used in division by constants, that damage
1988 ;; is visible (ipps regression tests). Therefore the last two
1989 ;; alternatives, "helping" reload to avoid an unnecessary move, but
1990 ;; punished by force of one "?". Check code from "int d (int a) {return
1991 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
1993 (define_insn "<su>mulsi3_highpart"
1994 [(set (match_operand:SI 0 "nonimmediate_operand" "=h,h,?r,?r")
1998 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
1999 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2001 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2002 "TARGET_HAS_MUL_INSNS"
2006 %!mul<su>.d %2,%1\;move $mof,%0
2007 %!mul<su>.d %1,%2\;move $mof,%0"
2008 [(set_attr "slottable" "yes,yes,no,no")
2009 (set_attr "cc" "clobber")])
2011 ;; Divide and modulus instructions. CRIS only has a step instruction.
2013 (define_insn "dstep_shift"
2014 [(set (match_operand:SI 0 "register_operand" "=r")
2016 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2018 (match_operand:SI 2 "register_operand" "r"))
2019 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2021 (match_operand:SI 4 "register_operand" "2"))
2022 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2026 [(set_attr "slottable" "yes")])
2028 ;; Here's a variant with mult instead of ashift.
2030 ;; FIXME: This should be investigated. Which one matches through combination?
2032 (define_insn "dstep_mul"
2033 [(set (match_operand:SI 0 "register_operand" "=r")
2035 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2037 (match_operand:SI 2 "register_operand" "r"))
2038 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2040 (match_operand:SI 4 "register_operand" "2"))
2041 (mult:SI (match_operand:SI 5 "register_operand" "0")
2043 "operands[0] != frame_pointer_rtx
2044 && operands[1] != frame_pointer_rtx
2045 && operands[2] != frame_pointer_rtx
2046 && operands[3] != frame_pointer_rtx"
2048 [(set_attr "slottable" "yes")])
2050 ;; Logical operators.
2054 ;; There is no use in defining "anddi3", because gcc can expand this by
2055 ;; itself, and make reasonable code without interference.
2057 ;; If the first operand is memory or a register and is the same as the
2058 ;; second operand, and the third operand is -256 or -65536, we can use
2059 ;; CLEAR instead. Or, if the first operand is a register, and the third
2060 ;; operand is 255 or 65535, we can zero_extend.
2061 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2062 ;; to be common enough to be worthwhile.
2063 ;; FIXME: This should be made obsolete.
2065 (define_expand "andsi3"
2066 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2067 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2068 (match_operand:SI 2 "general_operand" "")))]
2071 if (! (GET_CODE (operands[2]) == CONST_INT
2072 && (((INTVAL (operands[2]) == -256
2073 || INTVAL (operands[2]) == -65536)
2074 && rtx_equal_p (operands[1], operands[0]))
2075 || ((INTVAL (operands[2]) == 255
2076 || INTVAL (operands[2]) == 65535)
2077 && REG_P (operands[0])))))
2079 /* Make intermediate steps if operand0 is not a register or
2080 operand1 is not a register, and hope that the reload pass will
2081 make something useful out of it. Note that the operands are
2082 *not* canonicalized. For the moment, I chicken out on this,
2083 because all or most ports do not describe 'and' with
2084 canonicalized operands, and I seem to remember magic in reload,
2085 checking that operand1 has constraint '%0', in which case
2086 operand0 and operand1 must have similar predicates.
2087 FIXME: Investigate. */
2088 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2089 rtx reg1 = operands[1];
2093 emit_move_insn (reg0, reg1);
2097 emit_insn (gen_rtx_SET (SImode, reg0,
2098 gen_rtx_AND (SImode, reg1, operands[2])));
2100 /* Make sure we get the right *final* destination. */
2101 if (! REG_P (operands[0]))
2102 emit_move_insn (operands[0], reg0);
2108 ;; Some special cases of andsi3.
2110 (define_insn "*andsi_movu"
2111 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2112 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2113 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2114 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2115 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
2117 [(set_attr "slottable" "yes,yes,no")])
2119 (define_insn "*andsi_clear"
2120 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2121 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2122 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2123 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2124 && (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0]))"
2132 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2133 (set_attr "cc" "none")])
2135 ;; This is a catch-all pattern, taking care of everything that was not
2136 ;; matched in the insns above.
2138 ;; Sidenote: the tightening from "nonimmediate_operand" to
2139 ;; "register_operand" for operand 1 actually increased the register
2140 ;; pressure (worse code). That will hopefully change with an
2141 ;; improved reload pass.
2143 (define_insn "*expanded_andsi"
2144 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2145 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2146 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2154 [(set_attr "slottable" "yes,yes,yes,no,no")])
2156 ;; For both QI and HI we may use the quick patterns. This results in
2157 ;; useless condition codes, but that is used rarely enough for it to
2158 ;; normally be a win (could check ahead for use of cc0, but seems to be
2159 ;; more pain than win).
2161 ;; FIXME: See note for andsi3
2163 (define_expand "andhi3"
2164 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2165 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2166 (match_operand:HI 2 "general_operand" "")))]
2169 if (! (GET_CODE (operands[2]) == CONST_INT
2170 && (((INTVAL (operands[2]) == -256
2171 || INTVAL (operands[2]) == 65280)
2172 && rtx_equal_p (operands[1], operands[0]))
2173 || (INTVAL (operands[2]) == 255
2174 && REG_P (operands[0])))))
2176 /* See comment for andsi3. */
2177 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2178 rtx reg1 = operands[1];
2182 emit_move_insn (reg0, reg1);
2186 emit_insn (gen_rtx_SET (HImode, reg0,
2187 gen_rtx_AND (HImode, reg1, operands[2])));
2189 /* Make sure we get the right destination. */
2190 if (! REG_P (operands[0]))
2191 emit_move_insn (operands[0], reg0);
2197 ;; Some fast andhi3 special cases.
2199 (define_insn "*andhi_movu"
2200 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2201 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2203 "GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1])"
2205 [(set_attr "slottable" "yes,yes,no")])
2207 (define_insn "*andhi_clear"
2208 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2209 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2211 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
2213 [(set_attr "slottable" "yes,yes,no")
2214 (set_attr "cc" "none")])
2216 ;; Catch-all andhi3 pattern.
2218 (define_insn "*expanded_andhi"
2219 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2220 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2221 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2223 ;; Sidenote: the tightening from "general_operand" to
2224 ;; "register_operand" for operand 1 actually increased the register
2225 ;; pressure (worse code). That will hopefully change with an
2226 ;; improved reload pass.
2237 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2238 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2240 ;; A strict_low_part pattern.
2242 (define_insn "*andhi_lowpart"
2243 [(set (strict_low_part
2244 (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
2245 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
2246 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2255 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2256 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2258 (define_insn "andqi3"
2259 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2260 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2261 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2270 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2271 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2273 (define_insn "*andqi_lowpart"
2274 [(set (strict_low_part
2275 (match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
2276 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
2277 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2285 [(set_attr "slottable" "yes,yes,yes,no,no")
2286 (set_attr "cc" "normal,normal,clobber,normal,normal")])
2290 ;; Same comment as anddi3 applies here - no need for such a pattern.
2292 ;; It seems there's no need to jump through hoops to get good code such as
2295 (define_insn "iorsi3"
2296 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
2297 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
2298 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
2307 [(set_attr "slottable" "yes,yes,yes,no,no,no")
2308 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2310 (define_insn "iorhi3"
2311 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2312 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2313 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2323 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2324 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2326 (define_insn "iorqi3"
2327 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2328 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2329 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2338 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2339 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2343 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
2344 ;; FIXME: Do we really need the shorter variants?
2346 (define_insn "xorsi3"
2347 [(set (match_operand:SI 0 "register_operand" "=r")
2348 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2349 (match_operand:SI 2 "register_operand" "r")))]
2352 [(set_attr "slottable" "yes")])
2354 (define_insn "xor<mode>3"
2355 [(set (match_operand:BW 0 "register_operand" "=r")
2356 (xor:BW (match_operand:BW 1 "register_operand" "%0")
2357 (match_operand:BW 2 "register_operand" "r")))]
2360 [(set_attr "slottable" "yes")
2361 (set_attr "cc" "clobber")])
2365 ;; Questionable use, here mostly as a (slightly usable) define_expand
2368 (define_expand "negsf2"
2371 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
2372 (neg:SF (match_operand:SF 1
2373 "register_operand" "0")))
2374 (use (match_dup 2))])]
2377 operands[2] = gen_reg_rtx (SImode);
2378 operands[3] = GEN_INT (1 << 31);
2381 (define_insn "*expanded_negsf2"
2382 [(set (match_operand:SF 0 "register_operand" "=r")
2383 (neg:SF (match_operand:SF 1 "register_operand" "0")))
2384 (use (match_operand:SI 2 "register_operand" "r"))]
2387 [(set_attr "slottable" "yes")])
2389 ;; No "negdi2" although we could make one up that may be faster than
2390 ;; the one in libgcc.
2392 (define_insn "neg<mode>2"
2393 [(set (match_operand:BWD 0 "register_operand" "=r")
2394 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
2397 [(set_attr "slottable" "yes")])
2401 ;; See comment on anddi3 - no need for a DImode pattern.
2402 ;; See also xor comment.
2404 (define_insn "one_cmplsi2"
2405 [(set (match_operand:SI 0 "register_operand" "=r")
2406 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2409 [(set_attr "slottable" "yes")])
2411 (define_insn "one_cmpl<mode>2"
2412 [(set (match_operand:BW 0 "register_operand" "=r")
2413 (not:BW (match_operand:BW 1 "register_operand" "0")))]
2416 [(set_attr "slottable" "yes")
2417 (set_attr "cc" "clobber")])
2419 ;; Arithmetic/Logical shift right (and SI left).
2421 (define_insn "<shlr>si3"
2422 [(set (match_operand:SI 0 "register_operand" "=r")
2423 (shift:SI (match_operand:SI 1 "register_operand" "0")
2424 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
2427 if (REG_S_P (operands[2]))
2428 return "<slr>.d %2,%0";
2430 return "<slr>q %2,%0";
2432 [(set_attr "slottable" "yes")])
2434 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
2435 ;; the destination) when it changes shifts of lower modes into SImode,
2436 ;; it is better to make these expands an anonymous patterns instead of
2437 ;; the more correct define_insns. This occurs when gcc thinks that is
2438 ;; is better to widen to SImode and use immediate shift count.
2440 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
2442 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
2443 ;; mentioning "shiftrt"), so we need two patterns.
2444 (define_expand "ashr<mode>3"
2446 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
2448 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
2449 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
2450 (set (match_operand:BW 0 "general_operand" "")
2451 (subreg:BW (match_dup 5) 0))]
2456 for (i = 3; i < 6; i++)
2457 operands[i] = gen_reg_rtx (SImode);
2460 (define_expand "lshr<mode>3"
2462 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
2464 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
2465 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
2466 (set (match_operand:BW 0 "general_operand" "")
2467 (subreg:BW (match_dup 5) 0))]
2472 for (i = 3; i < 6; i++)
2473 operands[i] = gen_reg_rtx (SImode);
2476 (define_insn "*expanded_<shlr><mode>"
2477 [(set (match_operand:BW 0 "register_operand" "=r")
2478 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
2479 (match_operand:BW 2 "register_operand" "r")))]
2482 [(set_attr "slottable" "yes")])
2484 (define_insn "*<shlr><mode>_lowpart"
2485 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2486 (shiftrt:BW (match_dup 0)
2487 (match_operand:BW 1 "register_operand" "r")))]
2490 [(set_attr "slottable" "yes")])
2492 ;; Arithmetic/logical shift left.
2494 ;; For narrower modes than SI, we can use lslq although it makes cc
2495 ;; unusable. The win is that we do not have to reload the shift-count
2498 (define_insn "ashl<mode>3"
2499 [(set (match_operand:BW 0 "register_operand" "=r,r")
2500 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
2501 (match_operand:BW 2 "nonmemory_operand" "r,K")))]
2505 (GET_CODE (operands[2]) == CONST_INT
2506 && INTVAL (operands[2]) > <nbitsm1>)
2508 : (CONSTANT_P (operands[2])
2509 ? "lslq %2,%0" : "lsl<m> %2,%0");
2511 [(set_attr "slottable" "yes")
2512 (set_attr "cc" "normal,clobber")])
2514 ;; A strict_low_part matcher.
2516 (define_insn "*ashl<mode>_lowpart"
2517 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2518 (ashift:BW (match_dup 0)
2519 (match_operand:HI 1 "register_operand" "r")))]
2522 [(set_attr "slottable" "yes")])
2524 ;; Various strange insns that gcc likes.
2526 ;; Fortunately, it is simple to construct an abssf (although it may not
2527 ;; be very much used in practice).
2529 (define_insn "abssf2"
2530 [(set (match_operand:SF 0 "register_operand" "=r")
2531 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2533 "lslq 1,%0\;lsrq 1,%0")
2535 (define_insn "abssi2"
2536 [(set (match_operand:SI 0 "register_operand" "=r")
2537 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
2540 [(set_attr "slottable" "yes")])
2542 ;; FIXME: GCC should be able to do these expansions itself.
2544 (define_expand "abs<mode>2"
2546 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
2547 (set (match_dup 3) (abs:SI (match_dup 2)))
2548 (set (match_operand:BW 0 "register_operand" "")
2549 (subreg:BW (match_dup 3) 0))]
2551 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
2553 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
2554 ;; operation supported by gcc. Used in casesi, but used now and then in
2557 (define_insn "uminsi3"
2558 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
2559 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
2560 (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
2563 if (GET_CODE (operands[2]) == CONST_INT)
2565 if (INTVAL (operands[2]) < 256)
2566 return "bound.b %2,%0";
2568 if (INTVAL (operands[2]) < 65536)
2569 return "bound.w %2,%0";
2571 else if (which_alternative == 3)
2572 return "bound.d %2,%1,%0";
2574 return "bound.d %2,%0";
2576 [(set_attr "slottable" "yes,yes,no,no")])
2578 ;; Jump and branch insns.
2582 (label_ref (match_operand 0 "" "")))]
2585 [(set_attr "slottable" "has_slot")])
2587 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
2588 ;; here, since the insn is not recognized as an indirect jump by
2589 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
2590 ;; change from general_operand to nonimmediate_operand (at least the docs
2591 ;; should be changed), but then again the pattern is called indirect_jump.
2592 (define_insn "indirect_jump"
2593 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
2597 ;; Return insn. Used whenever the epilogue is very simple; if it is only
2598 ;; a single ret or jump [sp+]. No allocated stack space or saved
2599 ;; registers are allowed.
2600 ;; Note that for this pattern, although named, it is ok to check the
2601 ;; context of the insn in the test, not only compiler switches.
2603 (define_expand "return"
2605 "cris_simple_epilogue ()"
2606 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
2608 (define_insn "*return_expanded"
2612 return cris_return_address_on_stack_for_return ()
2613 ? "jump [$sp+]" : "ret%#";
2615 [(set (attr "slottable")
2618 "(cris_return_address_on_stack_for_return ())")
2621 (const_string "has_slot")))])
2623 (define_expand "prologue"
2625 "TARGET_PROLOGUE_EPILOGUE"
2626 "cris_expand_prologue (); DONE;")
2628 ;; Note that the (return) from the expander itself is always the last
2629 ;; insn in the epilogue.
2630 (define_expand "epilogue"
2632 "TARGET_PROLOGUE_EPILOGUE"
2633 "cris_expand_epilogue (); DONE;")
2635 ;; Conditional branches.
2637 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
2638 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
2641 (define_insn "b<ncond>"
2643 (if_then_else (ncond (cc0)
2645 (label_ref (match_operand 0 "" ""))
2649 [(set_attr "slottable" "has_slot")])
2651 (define_insn "b<ocond>"
2653 (if_then_else (ocond (cc0)
2655 (label_ref (match_operand 0 "" ""))
2660 (cc_prev_status.flags & CC_NO_OVERFLOW)
2661 ? 0 : \"b<CC> %l0%#\";
2663 [(set_attr "slottable" "has_slot")])
2665 (define_insn "b<rcond>"
2667 (if_then_else (rcond (cc0)
2669 (label_ref (match_operand 0 "" ""))
2674 (cc_prev_status.flags & CC_NO_OVERFLOW)
2675 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
2677 [(set_attr "slottable" "has_slot")])
2679 ;; Reversed anonymous patterns to the ones above, as mandated.
2681 (define_insn "*b<ncond>_reversed"
2683 (if_then_else (ncond (cc0)
2686 (label_ref (match_operand 0 "" ""))))]
2689 [(set_attr "slottable" "has_slot")])
2691 (define_insn "*b<ocond>_reversed"
2693 (if_then_else (ocond (cc0)
2696 (label_ref (match_operand 0 "" ""))))]
2700 (cc_prev_status.flags & CC_NO_OVERFLOW)
2701 ? 0 : \"b<rCC> %l0%#\";
2703 [(set_attr "slottable" "has_slot")])
2705 (define_insn "*b<rcond>_reversed"
2707 (if_then_else (rcond (cc0)
2710 (label_ref (match_operand 0 "" ""))))]
2714 (cc_prev_status.flags & CC_NO_OVERFLOW)
2715 ? \"b<roCC> %l0%#\" : \"b<rCC> %l0%#\";
2717 [(set_attr "slottable" "has_slot")])
2719 ;; Set on condition: sCC.
2721 ;; Like bCC, we have to check the overflow bit for
2722 ;; signed conditions.
2724 (define_insn "s<ncond>"
2725 [(set (match_operand:SI 0 "register_operand" "=r")
2726 (ncond:SI (cc0) (const_int 0)))]
2729 [(set_attr "slottable" "yes")
2730 (set_attr "cc" "none")])
2732 (define_insn "s<rcond>"
2733 [(set (match_operand:SI 0 "register_operand" "=r")
2734 (rcond:SI (cc0) (const_int 0)))]
2738 (cc_prev_status.flags & CC_NO_OVERFLOW)
2739 ? "s<oCC> %0" : "s<CC> %0";
2741 [(set_attr "slottable" "yes")
2742 (set_attr "cc" "none")])
2744 (define_insn "s<ocond>"
2745 [(set (match_operand:SI 0 "register_operand" "=r")
2746 (ocond:SI (cc0) (const_int 0)))]
2750 (cc_prev_status.flags & CC_NO_OVERFLOW)
2753 [(set_attr "slottable" "yes")
2754 (set_attr "cc" "none")])
2758 ;; We need to make these patterns "expand", since the real operand is
2759 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
2760 ;; and cannot be checked if it were a "normal" pattern.
2761 ;; Note that "call" and "call_value" are *always* called with a
2762 ;; mem-operand for operand 0 and 1 respective. What happens for combined
2763 ;; instructions is a different issue.
2765 (define_expand "call"
2766 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
2767 (match_operand 1 "general_operand" ""))
2768 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2773 gcc_assert (GET_CODE (operands[0]) == MEM);
2777 op0 = XEXP (operands[0], 0);
2779 /* It might be that code can be generated that jumps to 0 (or to a
2780 specific address). Don't die on that. (There is a testcase.) */
2781 if (CONSTANT_ADDRESS_P (op0) && GET_CODE (op0) != CONST_INT)
2783 CRIS_ASSERT (!no_new_pseudos);
2785 /* For local symbols (non-PLT), get the plain symbol reference
2786 into a register. For symbols that can be PLT, make them PLT. */
2787 if (cris_gotless_symbol (op0) || GET_CODE (op0) != SYMBOL_REF)
2788 op0 = force_reg (Pmode, op0);
2789 else if (cris_symbol (op0))
2790 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
2791 for the symbol cause bad recombinatorial effects? */
2792 op0 = force_reg (Pmode,
2795 gen_rtx_UNSPEC (VOIDmode,
2799 internal_error ("Unidentifiable op0");
2801 operands[0] = replace_equiv_address (operands[0], op0);
2806 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
2807 ;; order of preference.
2809 (define_insn "*expanded_call"
2810 [(call (mem:QI (match_operand:SI
2811 0 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
2812 (match_operand 1 "" ""))
2813 (clobber (reg:SI CRIS_SRP_REGNUM))]
2814 "! TARGET_AVOID_GOTPLT"
2817 ;; Same as above, since can't afford wasting a constraint letter to mean
2818 ;; "S unless TARGET_AVOID_GOTPLT".
2819 (define_insn "*expanded_call_no_gotplt"
2820 [(call (mem:QI (match_operand:SI
2821 0 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
2822 (match_operand 1 "" ""))
2823 (clobber (reg:SI CRIS_SRP_REGNUM))]
2824 "TARGET_AVOID_GOTPLT"
2827 (define_expand "call_value"
2828 [(parallel [(set (match_operand 0 "" "")
2829 (call (match_operand:QI 1 "cris_mem_call_operand" "")
2830 (match_operand 2 "" "")))
2831 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2836 gcc_assert (GET_CODE (operands[1]) == MEM);
2840 op1 = XEXP (operands[1], 0);
2842 /* It might be that code can be generated that jumps to 0 (or to a
2843 specific address). Don't die on that. (There is a testcase.) */
2844 if (CONSTANT_ADDRESS_P (op1) && GET_CODE (op1) != CONST_INT)
2846 CRIS_ASSERT (!no_new_pseudos);
2848 if (cris_gotless_symbol (op1))
2849 op1 = force_reg (Pmode, op1);
2850 else if (cris_symbol (op1))
2851 /* FIXME: Would hanging a REG_EQUIV/EQUAL on that register
2852 for the symbol cause bad recombinatorial effects? */
2853 op1 = force_reg (Pmode,
2856 gen_rtx_UNSPEC (VOIDmode,
2860 internal_error ("Unidentifiable op0");
2862 operands[1] = replace_equiv_address (operands[1], op1);
2867 ;; Accept *anything* as operand 2. The validity other than "general" of
2868 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
2869 ;; order of preference (Q includes r, but r is shorter, faster).
2870 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
2871 ;; than requiring getting rPIC + sym:PLT into a register.
2873 (define_insn "*expanded_call_value"
2874 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
2875 (call (mem:QI (match_operand:SI
2876 1 "cris_general_operand_or_plt_symbol" "r,Q>,g,S"))
2877 (match_operand 2 "" "")))
2878 (clobber (reg:SI CRIS_SRP_REGNUM))]
2879 "! TARGET_AVOID_GOTPLT"
2881 [(set_attr "cc" "clobber")])
2883 ;; Same as above, since can't afford wasting a constraint letter to mean
2884 ;; "S unless TARGET_AVOID_GOTPLT".
2885 (define_insn "*expanded_call_value_no_gotplt"
2886 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
2887 (call (mem:QI (match_operand:SI
2888 1 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
2889 (match_operand 2 "" "")))
2890 (clobber (reg:SI CRIS_SRP_REGNUM))]
2891 "TARGET_AVOID_GOTPLT"
2893 [(set_attr "cc" "clobber")])
2895 ;; Used in debugging. No use for the direct pattern; unfilled
2896 ;; delayed-branches are taken care of by other means.
2902 [(set_attr "cc" "none")])
2904 ;; We need to stop accesses to the stack after the memory is
2905 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
2906 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
2907 ;; want to use a naked (unspec_volatile) as that would stop any
2908 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
2909 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
2910 ;; still has the effect of an unspec_volatile.
2911 (define_insn "cris_frame_deallocated_barrier"
2912 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
2913 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
2916 [(set_attr "length" "0")])
2918 ;; We expand on casesi so we can use "bound" and "add offset fetched from
2919 ;; a table to pc" (adds.w [pc+%0.w],pc).
2921 ;; Note: if you change the "parallel" (or add anything after it) in
2922 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
2923 ;; accordingly, to add the default case at the end of the jump-table.
2925 (define_expand "casesi"
2926 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
2928 (minus:SI (match_dup 5)
2929 (match_operand:SI 1 "const_int_operand" "n")))
2931 (umin:SI (match_dup 6)
2932 (match_operand:SI 2 "const_int_operand" "n")))
2936 (ltu (match_dup 7) (match_dup 2))
2937 (plus:SI (sign_extend:SI
2939 (plus:SI (mult:SI (match_dup 7) (const_int 2))
2942 (label_ref (match_operand 4 "" ""))))
2943 (use (label_ref (match_operand 3 "" "")))])]
2946 operands[2] = plus_constant (operands[2], 1);
2947 operands[5] = gen_reg_rtx (SImode);
2948 operands[6] = gen_reg_rtx (SImode);
2949 operands[7] = gen_reg_rtx (SImode);
2952 ;; Split-patterns. Some of them have modes unspecified. This
2953 ;; should always be ok; if for no other reason sparc.md has it as
2956 ;; When register_operand is specified for an operand, we can get a
2957 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
2958 ;; for a register_operand and that REGNO can be used as is. It is best to
2959 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
2961 ;; op [rx + 0],ry,rz
2962 ;; The index to rx is optimized into zero, and gone.
2964 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
2965 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
2969 ;; Lose if rz=ry or rx=rz.
2970 ;; Call this op-extend-split
2973 [(set (match_operand 0 "register_operand" "")
2975 4 "cris_operand_extend_operator"
2976 [(match_operand 1 "register_operand" "")
2978 3 "cris_extend_operator"
2979 [(match_operand 2 "memory_operand" "")])]))]
2980 "REG_P (operands[0])
2981 && REG_P (operands[1])
2982 && REGNO (operands[1]) != REGNO (operands[0])
2983 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2984 && REG_P (XEXP (operands[2], 0))
2985 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
2991 (match_op_dup 3 [(match_dup 2)])]))]
2994 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
2997 ;; Do this for plus or bound only, being commutative operations, since we
2998 ;; have swapped the operands.
2999 ;; Call this op-extend-split-rx=rz
3002 [(set (match_operand 0 "register_operand" "")
3004 4 "cris_plus_or_bound_operator"
3005 [(match_operand 1 "register_operand" "")
3007 3 "cris_extend_operator"
3008 [(match_operand 2 "memory_operand" "")])]))]
3009 "REG_P (operands[0])
3010 && REG_P (operands[1])
3011 && REGNO (operands[1]) != REGNO (operands[0])
3012 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3013 && REG_P (XEXP (operands[2], 0))
3014 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3016 (match_op_dup 3 [(match_dup 2)]))
3023 ;; As the op-extend-split, but swapped operands, and only for
3024 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
3025 ;; this needed? Is it?
3026 ;; Call this op-extend-split-swapped
3029 [(set (match_operand 0 "register_operand" "")
3031 4 "cris_plus_or_bound_operator"
3033 3 "cris_extend_operator"
3034 [(match_operand 2 "memory_operand" "")])
3035 (match_operand 1 "register_operand" "")]))]
3036 "REG_P (operands[0])
3037 && REG_P (operands[1])
3038 && REGNO (operands[1]) != REGNO (operands[0])
3039 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3040 && REG_P (XEXP (operands[2], 0))
3041 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3047 (match_op_dup 3 [(match_dup 2)])]))]
3050 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
3051 ;; bound. Call this op-extend-split-swapped-rx=rz.
3054 [(set (match_operand 0 "register_operand" "")
3056 4 "cris_plus_or_bound_operator"
3058 3 "cris_extend_operator"
3059 [(match_operand 2 "memory_operand" "")])
3060 (match_operand 1 "register_operand" "")]))]
3061 "REG_P (operands[0])
3062 && REG_P (operands[1])
3063 && REGNO (operands[1]) != REGNO (operands[0])
3064 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3065 && REG_P (XEXP (operands[2], 0))
3066 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3068 (match_op_dup 3 [(match_dup 2)]))
3075 ;; As op-extend-split, but the mem operand is not extended.
3077 ;; op [rx],ry,rz changed into
3080 ;; lose if ry=rz or rx=rz
3081 ;; Call this op-extend.
3084 [(set (match_operand 0 "register_operand" "")
3086 3 "cris_orthogonal_operator"
3087 [(match_operand 1 "register_operand" "")
3088 (match_operand 2 "memory_operand" "")]))]
3089 "REG_P (operands[0])
3090 && REG_P (operands[1])
3091 && REGNO (operands[1]) != REGNO (operands[0])
3092 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3093 && REG_P (XEXP (operands[2], 0))
3094 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3103 ;; As op-extend-split-rx=rz, non-extended.
3104 ;; Call this op-split-rx=rz
3107 [(set (match_operand 0 "register_operand" "")
3109 3 "cris_commutative_orth_op"
3110 [(match_operand 2 "memory_operand" "")
3111 (match_operand 1 "register_operand" "")]))]
3112 "REG_P (operands[0])
3113 && REG_P (operands[1])
3114 && REGNO (operands[1]) != REGNO (operands[0])
3115 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3116 && REG_P (XEXP (operands[2], 0))
3117 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3126 ;; As op-extend-split-swapped, nonextended.
3127 ;; Call this op-split-swapped.
3130 [(set (match_operand 0 "register_operand" "")
3132 3 "cris_commutative_orth_op"
3133 [(match_operand 1 "register_operand" "")
3134 (match_operand 2 "memory_operand" "")]))]
3135 "REG_P (operands[0]) && REG_P (operands[1])
3136 && REGNO (operands[1]) != REGNO (operands[0])
3137 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3138 && REG_P (XEXP (operands[2], 0))
3139 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3148 ;; As op-extend-split-swapped-rx=rz, non-extended.
3149 ;; Call this op-split-swapped-rx=rz.
3152 [(set (match_operand 0 "register_operand" "")
3154 3 "cris_orthogonal_operator"
3155 [(match_operand 2 "memory_operand" "")
3156 (match_operand 1 "register_operand" "")]))]
3157 "REG_P (operands[0]) && REG_P (operands[1])
3158 && REGNO (operands[1]) != REGNO (operands[0])
3159 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3160 && REG_P (XEXP (operands[2], 0))
3161 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3170 ;; Splits for all cases in side-effect insns where (possibly after reload
3171 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
3173 ;; move.S1 [rx=rx+rz.S2],ry
3177 [(set (match_operand 0 "register_operand" "")
3181 (mult:SI (match_operand:SI 1 "register_operand" "")
3182 (match_operand:SI 2 "const_int_operand" ""))
3183 (match_operand:SI 3 "register_operand" ""))]))
3184 (set (match_operand:SI 4 "register_operand" "")
3185 (plus:SI (mult:SI (match_dup 1)
3188 "REG_P (operands[3]) && REG_P (operands[4])
3189 && REGNO (operands[3]) == REGNO (operands[4])"
3190 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
3192 (set (match_dup 0) (match_dup 5))]
3193 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
3195 ;; move.S1 [rx=rx+i],ry
3199 [(set (match_operand 0 "register_operand" "")
3202 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
3203 (match_operand:SI 2 "cris_bdap_operand" ""))]))
3204 (set (match_operand:SI 3 "register_operand" "")
3205 (plus:SI (match_dup 1)
3207 "(rtx_equal_p (operands[3], operands[1])
3208 || rtx_equal_p (operands[3], operands[2]))"
3209 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
3210 (set (match_dup 0) (match_dup 4))]
3211 "operands[4] = replace_equiv_address (operands[5], operands[3]);")
3213 ;; move.S1 ry,[rx=rx+rz.S2]
3217 [(set (match_operator
3220 (mult:SI (match_operand:SI 0 "register_operand" "")
3221 (match_operand:SI 1 "const_int_operand" ""))
3222 (match_operand:SI 2 "register_operand" ""))])
3223 (match_operand 3 "register_operand" ""))
3224 (set (match_operand:SI 4 "register_operand" "")
3225 (plus:SI (mult:SI (match_dup 0)
3228 "REG_P (operands[2]) && REG_P (operands[4])
3229 && REGNO (operands[4]) == REGNO (operands[2])"
3230 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3232 (set (match_dup 5) (match_dup 3))]
3233 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
3235 ;; move.S1 ry,[rx=rx+i]
3239 [(set (match_operator
3241 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
3242 (match_operand:SI 1 "cris_bdap_operand" ""))])
3243 (match_operand 2 "register_operand" ""))
3244 (set (match_operand:SI 3 "register_operand" "")
3245 (plus:SI (match_dup 0)
3247 "(rtx_equal_p (operands[3], operands[0])
3248 || rtx_equal_p (operands[3], operands[1]))"
3249 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
3250 (set (match_dup 5) (match_dup 2))]
3251 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
3253 ;; clear.[bwd] [rx=rx+rz.S2]
3257 [(set (mem:BWD (plus:SI
3258 (mult:SI (match_operand:SI 0 "register_operand" "")
3259 (match_operand:SI 1 "const_int_operand" ""))
3260 (match_operand:SI 2 "register_operand" "")))
3262 (set (match_operand:SI 3 "register_operand" "")
3263 (plus:SI (mult:SI (match_dup 0)
3266 "REG_P (operands[2]) && REG_P (operands[3])
3267 && REGNO (operands[3]) == REGNO (operands[2])"
3268 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3270 (set (mem:BWD (match_dup 3)) (const_int 0))]
3273 ;; clear.[bwd] [rx=rx+i]
3278 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
3279 (match_operand:SI 1 "cris_bdap_operand" "")))
3281 (set (match_operand:SI 2 "register_operand" "")
3282 (plus:SI (match_dup 0)
3284 "(rtx_equal_p (operands[0], operands[2])
3285 || rtx_equal_p (operands[2], operands[1]))"
3286 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
3287 (set (mem:BWD (match_dup 2)) (const_int 0))]
3290 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
3294 [(set (match_operand 0 "register_operand" "")
3296 5 "cris_extend_operator"
3298 (mult:SI (match_operand:SI 1 "register_operand" "")
3299 (match_operand:SI 2 "const_int_operand" ""))
3300 (match_operand:SI 3 "register_operand" "")))]))
3301 (set (match_operand:SI 4 "register_operand" "")
3302 (plus:SI (mult:SI (match_dup 1)
3305 "REG_P (operands[3])
3306 && REG_P (operands[4])
3307 && REGNO (operands[3]) == REGNO (operands[4])"
3308 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
3310 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
3311 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
3313 ;; mov(s|u).S1 [rx=rx+i],ry
3317 [(set (match_operand 0 "register_operand" "")
3319 4 "cris_extend_operator"
3321 (match_operand:SI 1 "cris_bdap_operand" "")
3322 (match_operand:SI 2 "cris_bdap_operand" "")))]))
3323 (set (match_operand:SI 3 "register_operand" "")
3324 (plus:SI (match_dup 1)
3326 "(rtx_equal_p (operands[1], operands[3])
3327 || rtx_equal_p (operands[2], operands[3]))"
3328 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
3329 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
3330 "operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);")
3332 ;; op.S1 [rx=rx+i],ry
3336 [(set (match_operand 0 "register_operand" "")
3338 5 "cris_orthogonal_operator"
3339 [(match_operand 1 "register_operand" "")
3341 (match_operand:SI 2 "cris_bdap_operand" "")
3342 (match_operand:SI 3 "cris_bdap_operand" "")))]))
3343 (set (match_operand:SI 4 "register_operand" "")
3344 (plus:SI (match_dup 2)
3346 "(rtx_equal_p (operands[4], operands[2])
3347 || rtx_equal_p (operands[4], operands[3]))"
3348 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3349 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
3350 "operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);")
3352 ;; op.S1 [rx=rx+rz.S2],ry
3356 [(set (match_operand 0 "register_operand" "")
3358 6 "cris_orthogonal_operator"
3359 [(match_operand 1 "register_operand" "")
3361 (mult:SI (match_operand:SI 2 "register_operand" "")
3362 (match_operand:SI 3 "const_int_operand" ""))
3363 (match_operand:SI 4 "register_operand" "")))]))
3364 (set (match_operand:SI 5 "register_operand" "")
3365 (plus:SI (mult:SI (match_dup 2)
3368 "REG_P (operands[4])
3369 && REG_P (operands[5])
3370 && REGNO (operands[5]) == REGNO (operands[4])"
3371 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3373 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
3374 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
3376 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
3380 [(set (match_operand 0 "register_operand" "")
3382 6 "cris_commutative_orth_op"
3384 (mult:SI (match_operand:SI 2 "register_operand" "")
3385 (match_operand:SI 3 "const_int_operand" ""))
3386 (match_operand:SI 4 "register_operand" "")))
3387 (match_operand 1 "register_operand" "")]))
3388 (set (match_operand:SI 5 "register_operand" "")
3389 (plus:SI (mult:SI (match_dup 2)
3392 "REG_P (operands[4])
3393 && REG_P (operands[5])
3394 && REGNO (operands[5]) == REGNO (operands[4])"
3395 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3397 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
3398 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
3400 ;; op.S1 [rx=rx+i],ry (swapped)
3404 [(set (match_operand 0 "register_operand" "")
3406 5 "cris_commutative_orth_op"
3408 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
3409 (match_operand:SI 3 "cris_bdap_operand" "")))
3410 (match_operand 1 "register_operand" "")]))
3411 (set (match_operand:SI 4 "register_operand" "")
3412 (plus:SI (match_dup 2)
3414 "(rtx_equal_p (operands[4], operands[2])
3415 || rtx_equal_p (operands[4], operands[3]))"
3416 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3417 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
3418 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
3420 ;; op(s|u).S1 [rx=rx+rz.S2],ry
3424 [(set (match_operand 0 "register_operand" "")
3426 6 "cris_operand_extend_operator"
3427 [(match_operand 1 "register_operand" "")
3429 7 "cris_extend_operator"
3431 (mult:SI (match_operand:SI 2 "register_operand" "")
3432 (match_operand:SI 3 "const_int_operand" ""))
3433 (match_operand:SI 4 "register_operand" "")))])]))
3434 (set (match_operand:SI 5 "register_operand" "")
3435 (plus:SI (mult:SI (match_dup 2)
3438 "REG_P (operands[4])
3439 && REG_P (operands[5])
3440 && REGNO (operands[5]) == REGNO (operands[4])"
3441 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3443 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
3444 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
3445 replace_equiv_address (XEXP (operands[7], 0),
3448 ;; op(s|u).S1 [rx=rx+i],ry
3452 [(set (match_operand 0 "register_operand" "")
3454 5 "cris_operand_extend_operator"
3455 [(match_operand 1 "register_operand" "")
3457 6 "cris_extend_operator"
3459 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
3460 (match_operand:SI 3 "cris_bdap_operand" "")
3462 (set (match_operand:SI 4 "register_operand" "")
3463 (plus:SI (match_dup 2)
3465 "(rtx_equal_p (operands[4], operands[2])
3466 || rtx_equal_p (operands[4], operands[3]))"
3467 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3468 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
3469 "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
3470 replace_equiv_address (XEXP (operands[6], 0),
3473 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
3477 [(set (match_operand 0 "register_operand" "")
3479 7 "cris_plus_or_bound_operator"
3481 6 "cris_extend_operator"
3483 (mult:SI (match_operand:SI 2 "register_operand" "")
3484 (match_operand:SI 3 "const_int_operand" ""))
3485 (match_operand:SI 4 "register_operand" "")))])
3486 (match_operand 1 "register_operand" "")]))
3487 (set (match_operand:SI 5 "register_operand" "")
3488 (plus:SI (mult:SI (match_dup 2)
3491 "REG_P (operands[4]) && REG_P (operands[5])
3492 && REGNO (operands[5]) == REGNO (operands[4])"
3493 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3495 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
3496 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
3497 replace_equiv_address (XEXP (operands[6], 0),
3500 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
3504 [(set (match_operand 0 "register_operand" "")
3506 6 "cris_plus_or_bound_operator"
3508 5 "cris_extend_operator"
3510 (match_operand:SI 2 "cris_bdap_operand" "")
3511 (match_operand:SI 3 "cris_bdap_operand" "")))])
3512 (match_operand 1 "register_operand" "")]))
3513 (set (match_operand:SI 4 "register_operand" "")
3514 (plus:SI (match_dup 2)
3516 "(rtx_equal_p (operands[4], operands[2])
3517 || rtx_equal_p (operands[4], operands[3]))"
3518 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3519 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
3520 "operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
3521 replace_equiv_address (XEXP (operands[5], 0),
3524 ;; Splits for addressing prefixes that have no side-effects, so we can
3525 ;; fill a delay slot. Never split if we lose something, though.
3528 ;; move [indirect_ref],rx
3529 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
3530 ;; move indirect_ref,rx
3532 ;; Take care not to allow indirect_ref = register.
3534 ;; We're not allowed to generate copies of registers with different mode
3535 ;; until after reload; copying pseudos upsets reload. CVS as of
3536 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
3537 ;; cselib_invalidate_regno.
3539 (define_split ; indir_to_reg_split
3540 [(set (match_operand 0 "register_operand" "")
3541 (match_operand 1 "indirect_operand" ""))]
3543 && REG_P (operands[0])
3544 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3545 && (GET_CODE (XEXP (operands[1], 0)) == MEM
3546 || CONSTANT_P (XEXP (operands[1], 0)))
3547 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
3548 [(set (match_dup 2) (match_dup 4))
3549 (set (match_dup 0) (match_dup 3))]
3550 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
3551 operands[3] = replace_equiv_address (operands[1], operands[2]);
3552 operands[4] = XEXP (operands[1], 0);")
3554 ;; As the above, but MOVS and MOVU.
3557 [(set (match_operand 0 "register_operand" "")
3559 4 "cris_extend_operator"
3560 [(match_operand 1 "indirect_operand" "")]))]
3562 && REG_P (operands[0])
3563 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3564 && (GET_CODE (XEXP (operands[1], 0)) == MEM
3565 || CONSTANT_P (XEXP (operands[1], 0)))"
3566 [(set (match_dup 2) (match_dup 5))
3567 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
3568 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
3569 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
3570 operands[5] = XEXP (operands[1], 0);")
3572 ;; Various peephole optimizations.
3574 ;; Watch out: when you exchange one set of instructions for another, the
3575 ;; condition codes setting must be the same, or you have to CC_INIT or
3576 ;; whatever is appropriate, in the pattern before you emit the
3577 ;; assembly text. This is best done here, not in cris_notice_update_cc,
3578 ;; to keep changes local to their cause.
3580 ;; Do not add patterns that you do not know will be matched.
3581 ;; Please also add a self-contained testcase.
3583 ;; We have trouble with and:s and shifts. Maybe something is broken in
3584 ;; gcc? Or it could just be that bit-field insn expansion is a bit
3585 ;; suboptimal when not having extzv insns.
3586 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
3588 (define_peephole2 ; asrandb (peephole casesi+31)
3589 [(set (match_operand:SI 0 "register_operand" "")
3590 (ashiftrt:SI (match_dup 0)
3591 (match_operand:SI 1 "const_int_operand" "")))
3593 (and:SI (match_dup 0)
3594 (match_operand 2 "const_int_operand" "")))]
3595 "INTVAL (operands[2]) > 31
3596 && INTVAL (operands[2]) < 255
3597 && INTVAL (operands[1]) > 23
3598 /* Check that the and-operation enables us to use logical-shift. */
3599 && (INTVAL (operands[2])
3600 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
3601 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3602 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
3603 ;; FIXME: CC0 is valid except for the M bit.
3605 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
3606 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
3609 (define_peephole2 ; asrandw (peephole casesi+32)
3610 [(set (match_operand:SI 0 "register_operand" "")
3611 (ashiftrt:SI (match_dup 0)
3612 (match_operand:SI 1 "const_int_operand" "")))
3614 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3615 "INTVAL (operands[2]) > 31
3616 && INTVAL (operands[2]) < 65535
3617 && INTVAL (operands[2]) != 255
3618 && INTVAL (operands[1]) > 15
3619 /* Check that the and-operation enables us to use logical-shift. */
3620 && (INTVAL (operands[2])
3621 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
3622 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3623 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
3624 ;; FIXME: CC0 is valid except for the M bit.
3626 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3627 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
3630 (define_peephole2 ; lsrandb (peephole casesi+33)
3631 [(set (match_operand:SI 0 "register_operand" "")
3632 (lshiftrt:SI (match_dup 0)
3633 (match_operand:SI 1 "const_int_operand" "")))
3635 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3636 "INTVAL (operands[2]) > 31
3637 && INTVAL (operands[2]) < 255
3638 && INTVAL (operands[1]) > 23"
3639 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3640 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
3641 ;; FIXME: CC0 is valid except for the M bit.
3643 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
3644 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
3647 (define_peephole2 ; lsrandw (peephole casesi+34)
3648 [(set (match_operand:SI 0 "register_operand" "")
3649 (lshiftrt:SI (match_dup 0)
3650 (match_operand:SI 1 "const_int_operand" "")))
3652 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3653 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
3654 && INTVAL (operands[2]) != 255
3655 && INTVAL (operands[1]) > 15"
3656 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3657 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
3658 ;; FIXME: CC0 is valid except for the M bit.
3660 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3661 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
3669 ;; move [rx=rx+n],ry
3670 ;; when -128 <= n <= 127.
3671 ;; This will reduce the size of the assembler code for n = [-128..127],
3672 ;; and speed up accordingly. Don't match if the previous insn is
3673 ;; (set rx rz) because that combination is matched by another peephole.
3674 ;; No stable test-case.
3676 (define_peephole2 ; moversideqi (peephole casesi+35)
3677 [(set (match_operand:SI 0 "register_operand" "")
3678 (plus:SI (match_operand:SI 1 "register_operand" "")
3679 (match_operand:SI 2 "const_int_operand" "")))
3680 (set (match_operand 3 "register_operand" "")
3681 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
3682 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
3683 && REGNO (operands[3]) != REGNO (operands[0])
3684 && (BASE_P (operands[1]) || BASE_P (operands[2]))
3685 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3686 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3687 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
3689 [(set (match_dup 3) (match_dup 5))
3690 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3691 ;; Checking the previous insn is a bit too awkward for the condition.
3693 rtx prev = prev_nonnote_insn (curr_insn);
3694 if (prev != NULL_RTX)
3696 rtx set = single_set (prev);
3698 && REG_S_P (SET_DEST (set))
3699 && REGNO (SET_DEST (set)) == REGNO (operands[0])
3700 && REG_S_P (SET_SRC (set)))
3704 = replace_equiv_address (operands[4],
3705 gen_rtx_PLUS (SImode,
3706 operands[1], operands[2]));
3709 ;; Vice versa: move ry,[rx=rx+n]
3711 (define_peephole2 ; movemsideqi (peephole casesi+36)
3712 [(set (match_operand:SI 0 "register_operand" "")
3713 (plus:SI (match_operand:SI 1 "register_operand" "")
3714 (match_operand:SI 2 "const_int_operand" "")))
3715 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
3716 (match_operand 4 "register_operand" ""))]
3717 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
3718 && REGNO (operands[4]) != REGNO (operands[0])
3719 && (BASE_P (operands[1]) || BASE_P (operands[2]))
3720 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3721 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3722 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
3724 [(set (match_dup 5) (match_dup 4))
3725 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3727 = replace_equiv_address (operands[3],
3728 gen_rtx_PLUS (SImode,
3729 operands[1], operands[2]));")
3731 ;; As above, change:
3735 ;; op.d [rx=rx+n],ry
3736 ;; Saves when n = [-128..127].
3738 ;; Splitting and joining combinations for side-effect modes are slightly
3739 ;; out of hand. They probably will not save the time they take typing in,
3740 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
3741 ;; the splits and peepholes as possible.
3742 ;; No stable test-case.
3744 (define_peephole2 ; mover2side (peephole casesi+37)
3745 [(set (match_operand:SI 0 "register_operand" "")
3746 (plus:SI (match_operand:SI 1 "register_operand" "")
3747 (match_operand:SI 2 "const_int_operand" "")))
3748 (set (match_operand 3 "register_operand" "")
3749 (match_operator 4 "cris_orthogonal_operator"
3752 5 "cris_mem_op" [(match_dup 0)])]))]
3753 ;; FIXME: What about DFmode?
3754 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
3755 "GET_MODE (operands[3]) != DImode
3756 && REGNO (operands[0]) != REGNO (operands[3])
3757 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3758 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3759 && INTVAL (operands[2]) >= -128
3760 && INTVAL (operands[2]) <= 127"
3762 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
3763 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3765 = replace_equiv_address (operands[5],
3766 gen_rtx_PLUS (SImode,
3767 operands[1], operands[2]));")
3769 ;; Sometimes, for some reason the pattern
3773 ;; will occur. Solve this, and likewise for to-memory.
3774 ;; No stable test-case.
3776 (define_peephole2 ; moverside (peephole casesi+38)
3777 [(set (match_operand:SI 0 "register_operand" "")
3778 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
3780 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
3781 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
3782 (set (match_operand 4 "register_operand" "")
3783 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
3784 "(rtx_equal_p (operands[2], operands[0])
3785 || rtx_equal_p (operands[3], operands[0]))
3786 && cris_side_effect_mode_ok (PLUS, operands, 0,
3787 (REG_S_P (operands[1])
3789 : (rtx_equal_p (operands[2], operands[0])
3791 (! REG_S_P (operands[1])
3793 : (rtx_equal_p (operands[2], operands[0])
3797 [(set (match_dup 4) (match_dup 6))
3798 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
3801 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
3803 /* Make sure we have canonical RTX so we match the insn pattern -
3804 not a constant in the first operand. We also require the order
3805 (plus reg mem) to match the final pattern. */
3806 if (CONSTANT_P (otherop) || MEM_P (otherop))
3808 operands[7] = operands[1];
3809 operands[8] = otherop;
3813 operands[7] = otherop;
3814 operands[8] = operands[1];
3817 = replace_equiv_address (operands[5],
3818 gen_rtx_PLUS (SImode,
3819 operands[7], operands[8]));
3822 ;; As above but to memory.
3823 ;; FIXME: Split movemside and moverside into variants and prune
3824 ;; the ones that don't trig.
3825 ;; No stable test-case.
3827 (define_peephole2 ; movemside (peephole casesi+39)
3828 [(set (match_operand:SI 0 "register_operand" "")
3829 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
3831 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
3832 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
3833 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
3834 (match_operand 5 "register_operand" ""))]
3835 "(rtx_equal_p (operands[2], operands[0])
3836 || rtx_equal_p (operands[3], operands[0]))
3837 && cris_side_effect_mode_ok (PLUS, operands, 0,
3838 (REG_S_P (operands[1])
3840 : (rtx_equal_p (operands[2], operands[0])
3842 (! REG_S_P (operands[1])
3844 : (rtx_equal_p (operands[2], operands[0])
3848 [(set (match_dup 6) (match_dup 5))
3849 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
3852 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
3854 /* Make sure we have canonical RTX so we match the insn pattern -
3855 not a constant in the first operand. We also require the order
3856 (plus reg mem) to match the final pattern. */
3857 if (CONSTANT_P (otherop) || MEM_P (otherop))
3859 operands[7] = operands[1];
3860 operands[8] = otherop;
3864 operands[7] = otherop;
3865 operands[8] = operands[1];
3868 = replace_equiv_address (operands[4],
3869 gen_rtx_PLUS (SImode,
3870 operands[7], operands[8]));
3873 ;; Another spotted bad code:
3876 ;; No stable test-case.
3878 (define_peephole2 ; movei (peephole casesi+42)
3879 [(set (match_operand:SI 0 "register_operand" "")
3880 (match_operand:SI 1 "register_operand" ""))
3881 (set (match_operand 2 "register_operand" "")
3882 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
3883 "REGNO (operands[0]) == REGNO (operands[2])
3884 && (REGNO_REG_CLASS (REGNO (operands[0]))
3885 == REGNO_REG_CLASS (REGNO (operands[1])))
3886 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
3887 [(set (match_dup 2) (match_dup 4))]
3888 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
3890 ;; move.d [r10+16],r9
3893 ;; and.d [r10+16],r12,r9
3894 ;; With generalization of the operation, the size and the addressing mode.
3895 ;; This seems to be the result of a quirk in register allocation
3896 ;; missing the three-operand cases when having different predicates.
3897 ;; Maybe that it matters that it is a commutative operation.
3898 ;; This pattern helps that situation, but there's still the increased
3899 ;; register pressure.
3900 ;; Note that adding the noncommutative variant did not show any matches
3901 ;; in ipps and cc1, so it's not here.
3902 ;; No stable test-case.
3904 (define_peephole2 ; op3 (peephole casesi+44)
3905 [(set (match_operand 0 "register_operand" "")
3909 (match_operand:SI 1 "cris_bdap_biap_operand" "")
3910 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
3913 5 "cris_commutative_orth_op"
3914 [(match_operand 3 "register_operand" "")
3915 (match_operand 4 "register_operand" "")]))]
3916 "(rtx_equal_p (operands[3], operands[0])
3917 || rtx_equal_p (operands[4], operands[0]))
3918 && ! rtx_equal_p (operands[3], operands[4])
3919 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
3920 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
3921 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
3923 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
3925 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
3927 ;; and.b some_byte,const,reg_32
3928 ;; where reg_32 is the destination of the "three-address" code optimally.
3930 ;; movu.b some_byte,reg_32
3931 ;; and.b const,reg_32
3932 ;; but is turns into:
3933 ;; move.b some_byte,reg_32
3934 ;; and.d const,reg_32
3936 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
3938 (define_peephole2 ; andu (casesi+45)
3939 [(set (match_operand:SI 0 "register_operand" "")
3940 (match_operand:SI 1 "nonimmediate_operand" ""))
3941 (set (match_operand:SI 2 "register_operand" "")
3942 (and:SI (match_dup 0)
3943 (match_operand:SI 3 "const_int_operand" "")))]
3944 ;; Since the size of the memory access could be made different here,
3945 ;; don't do this for a mem-volatile access.
3946 "REGNO (operands[2]) == REGNO (operands[0])
3947 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
3948 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
3949 && (GET_CODE (operands[1]) != MEM || ! MEM_VOLATILE_P (operands[1]))"
3950 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
3951 [(set (match_dup 0) (match_dup 4))
3952 (set (match_dup 5) (match_dup 6))]
3954 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
3955 enum machine_mode amode
3956 = CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
3958 = (REG_S_P (operands[1])
3959 ? gen_rtx_REG (zmode, REGNO (operands[1]))
3960 : adjust_address (operands[1], zmode, 0));
3962 = gen_rtx_ZERO_EXTEND (SImode, op1);
3963 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
3965 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
3966 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
3968 ? QImode : amode)));
3973 ;; comment-start: ";; "
3974 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
3975 ;; eval: (modify-syntax-entry ?[ "(]")
3976 ;; eval: (modify-syntax-entry ?] ")[")
3977 ;; eval: (modify-syntax-entry ?{ "(}")
3978 ;; eval: (modify-syntax-entry ?} "){")
3979 ;; eval: (setq indent-tabs-mode t)