1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* RUN-TIME TARGET SPECIFICATION. */
29 #define TARGET_CPU_CPP_BUILTINS() \
33 builtin_define ("_BIGMODEL"); \
34 if (!TARGET_MEMPARM) \
35 builtin_define ("_REGPARM"); \
36 if (flag_inline_functions \
37 || flag_inline_trees) \
38 builtin_define ("_INLINE"); \
41 builtin_define ("_TMS320C3x"); \
42 builtin_define ("_C3x"); \
45 builtin_define ("_TMS320C30"); \
46 builtin_define ("_C30"); \
48 else if (TARGET_C31) \
50 builtin_define ("_TMS320C31"); \
51 builtin_define ("_C31"); \
53 else if (TARGET_C32) \
55 builtin_define ("_TMS320C32"); \
56 builtin_define ("_C32"); \
58 else if (TARGET_C33) \
60 builtin_define ("_TMS320C33"); \
61 builtin_define ("_C33"); \
66 builtin_define ("_TMS320C4x"); \
67 builtin_define ("_C4x"); \
70 builtin_define ("_TMS320C40"); \
71 builtin_define ("_C40"); \
73 else if (TARGET_C44) \
75 builtin_define ("_TMS320C44"); \
76 builtin_define ("_C44"); \
82 /* Name of the c4x assembler. */
84 #define ASM_PROG "c4x-as"
86 /* Name of the c4x linker. */
88 #define LD_PROG "c4x-ld"
90 /* Define assembler options. */
93 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
94 %{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
107 %{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
108 %{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
110 /* Define linker options. */
113 %{m30:--architecture c3x} \
114 %{m31:--architecture c3x} \
115 %{m32:--architecture c3x} \
116 %{m33:--architecture c3x} \
117 %{mcpu=30:--architecture c3x} \
118 %{mcpu=31:--architecture c3x} \
119 %{mcpu=32:--architecture c3x} \
120 %{mcpu=33:--architecture c3x}"
122 /* Specify the end file to link with. */
124 #define ENDFILE_SPEC ""
126 /* Target compilation option flags. */
128 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
129 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
130 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
131 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
132 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
133 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
134 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
135 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
136 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
137 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
138 #define BK_FLAG 0x0000400 /* Use BK as general register. */
139 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
140 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
141 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
142 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
143 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
144 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
145 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
146 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
147 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
149 #define C30_FLAG 0x0100000 /* Emit C30 code. */
150 #define C31_FLAG 0x0200000 /* Emit C31 code. */
151 #define C32_FLAG 0x0400000 /* Emit C32 code. */
152 #define C33_FLAG 0x0800000 /* Emit C33 code. */
153 #define C40_FLAG 0x1000000 /* Emit C40 code. */
154 #define C44_FLAG 0x2000000 /* Emit C44 code. */
156 /* Run-time compilation parameters selecting different hardware subsets.
158 Macro to define tables used to set the flags.
159 This is a list in braces of triplets in braces,
160 each pair being { "NAME", VALUE, "DESCRIPTION" }
161 where VALUE is the bits to set or minus the bits to clear.
162 An empty string NAME is used to identify the default VALUE. */
164 #define TARGET_SWITCHES \
165 { { "small", SMALL_MEMORY_FLAG, \
166 N_("Small memory model") }, \
167 { "big", -SMALL_MEMORY_FLAG, \
168 N_("Big memory model") }, \
169 { "mpyi", MPYI_FLAG, \
170 N_("Use MPYI instruction for C3x") }, \
171 { "no-mpyi", -MPYI_FLAG, \
172 N_("Do not use MPYI instruction for C3x") }, \
173 { "fast-fix", FAST_FIX_FLAG, \
174 N_("Use fast but approximate float to integer conversion") }, \
175 { "no-fast-fix", -FAST_FIX_FLAG, \
176 N_("Use slow but accurate float to integer conversion") }, \
177 { "rpts", RPTS_FLAG, \
178 N_("Enable use of RTPS instruction") }, \
179 { "no-rpts", -RPTS_FLAG, \
180 N_("Disable use of RTPS instruction") }, \
181 { "rptb", RPTB_FLAG, \
182 N_("Enable use of RTPB instruction") }, \
183 { "no-rptb", -RPTB_FLAG, \
184 N_("Disable use of RTPB instruction") }, \
186 N_("Generate code for C30 CPU")}, \
188 N_("Generate code for C31 CPU")}, \
190 N_("Generate code for C32 CPU")}, \
192 N_("Generate code for C33 CPU")}, \
194 N_("Generate code for C40 CPU")}, \
196 N_("Generate code for C44 CPU")}, \
198 N_("Emit code compatible with TI tools")}, \
199 { "no-ti", -TI_FLAG, \
200 N_("Emit code to use GAS extensions")}, \
201 { "paranoid", PARANOID_FLAG, \
202 N_("Save DP across ISR in small memory model") }, \
203 { "no-paranoid", -PARANOID_FLAG, \
204 N_("Don't save DP across ISR in small memory model") }, \
205 { "isr-dp-reload", PARANOID_FLAG, \
206 N_("Save DP across ISR in small memory model") }, \
207 { "no-isr-dp-reload", -PARANOID_FLAG, \
208 N_("Don't save DP across ISR in small memory model") }, \
209 { "memparm", MEMPARM_FLAG, \
210 N_("Pass arguments on the stack") }, \
211 { "regparm", -MEMPARM_FLAG, \
212 N_("Pass arguments in registers") }, \
213 { "devel", DEVEL_FLAG, \
214 N_("Enable new features under development") }, \
215 { "no-devel", -DEVEL_FLAG, \
216 N_("Disable new features under development") }, \
218 N_("Use the BK register as a general purpose register") }, \
219 { "no-bk", -BK_FLAG, \
220 N_("Do not allocate BK register") }, \
222 N_("Enable use of DB instruction") }, \
223 { "no-db", -DB_FLAG, \
224 N_("Disable use of DB instruction") }, \
225 { "debug", DEBUG_FLAG, \
226 N_("Enable debugging") }, \
227 { "no-debug", -DEBUG_FLAG, \
228 N_("Disable debugging") }, \
229 { "hoist", HOIST_FLAG, \
230 N_("Force constants into registers to improve hoisting") }, \
231 { "no-hoist", -HOIST_FLAG, \
232 N_("Don't force constants into registers") }, \
233 { "force", FORCE_FLAG, \
234 N_("Force RTL generation to emit valid 3 operand insns") }, \
235 { "no-force", -FORCE_FLAG, \
236 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
237 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
238 N_("Allow unsigned interation counts for RPTB/DB") }, \
239 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
240 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
241 { "preserve-float", PRESERVE_FLOAT_FLAG, \
242 N_("Preserve all 40 bits of FP reg across call") }, \
243 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
244 N_("Only preserve 32 bits of FP reg across call") }, \
245 { "parallel-insns", PARALLEL_INSN_FLAG, \
246 N_("Enable parallel instructions") }, \
247 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
248 N_("Disable parallel instructions") }, \
249 { "parallel-mpy", PARALLEL_MPY_FLAG, \
250 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
251 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
252 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
253 { "aliases", ALIASES_FLAG, \
254 N_("Assume that pointers may be aliased") }, \
255 { "no-aliases", -ALIASES_FLAG, \
256 N_("Assume that pointers not aliased") }, \
257 { "", TARGET_DEFAULT, ""} }
259 /* Default target switches. */
261 /* Play safe, not the fastest code. */
262 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
263 | PARALLEL_MPY_FLAG | RPTB_FLAG
266 Max iteration count for RPTB/RPTS is 2^31 + 1.
267 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
268 RPTS blocks interrupts. */
271 extern int target_flags;
273 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
274 #define TARGET_SMALL_REG_CLASS 0
276 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
277 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
278 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
279 #define TARGET_RPTS (target_flags & RPTS_FLAG)
280 #define TARGET_TI (target_flags & TI_FLAG)
281 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
282 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
283 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
284 #define TARGET_RPTB (target_flags & RPTB_FLAG \
286 #define TARGET_BK (target_flags & BK_FLAG)
287 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
288 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
289 #define TARGET_HOIST (target_flags & HOIST_FLAG)
290 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
291 #define TARGET_FORCE (target_flags & FORCE_FLAG)
292 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
293 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
295 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
296 && (target_flags & PARALLEL_MPY_FLAG))
297 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
299 #define TARGET_C3X (target_flags & C3X_FLAG)
300 #define TARGET_C30 (target_flags & C30_FLAG)
301 #define TARGET_C31 (target_flags & C31_FLAG)
302 #define TARGET_C32 (target_flags & C32_FLAG)
303 #define TARGET_C33 (target_flags & C33_FLAG)
304 #define TARGET_C40 (target_flags & C40_FLAG)
305 #define TARGET_C44 (target_flags & C44_FLAG)
307 /* Define some options to control code generation. */
308 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
309 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
310 during RTL generation. */
311 #define TARGET_EXPOSE_LDP 0
312 /* Nonzero to force loading of direct memory references into a register. */
313 #define TARGET_LOAD_DIRECT_MEMS 0
315 /* -mrpts allows the use of the RPTS instruction irregardless.
316 -mrpts=max-cycles will use RPTS if the number of cycles is constant
317 and less than max-cycles. */
319 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
321 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
323 /* -mcpu=XX with XX = target DSP version number. */
325 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
327 #define TARGET_OPTIONS \
328 { {"rpts=", &c4x_rpts_cycles_string, \
329 N_("Specify maximum number of iterations for RPTS") }, \
330 {"cpu=", &c4x_cpu_version_string, \
331 N_("Select CPU to generate code for") } }
333 /* Sometimes certain combinations of command options do not make sense
334 on a particular target machine. You can define a macro
335 `OVERRIDE_OPTIONS' to take account of this. This macro, if
336 defined, is executed once just after all the command options have
339 #define OVERRIDE_OPTIONS c4x_override_options ()
341 /* Define this to change the optimizations performed by default. */
343 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
345 /* Run Time Target Specification. */
347 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
349 /* Storage Layout. */
351 #define BITS_BIG_ENDIAN 0
352 #define BYTES_BIG_ENDIAN 0
353 #define WORDS_BIG_ENDIAN 0
355 /* Technically, we are little endian, but we put the floats out as
356 whole longs and this makes GCC put them out in the right order. */
358 #define FLOAT_WORDS_BIG_ENDIAN 1
360 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
361 all integral and floating point data types are stored in memory as
362 32-bits (floating point types can be stored as 40-bits in the
363 extended precision registers), so sizeof(char) = sizeof(short) =
364 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
366 #define BITS_PER_UNIT 32
367 #define UNITS_PER_WORD 1
368 #define PARM_BOUNDARY 32
369 #define STACK_BOUNDARY 32
370 #define FUNCTION_BOUNDARY 32
371 #define BIGGEST_ALIGNMENT 32
372 #define EMPTY_FIELD_BOUNDARY 32
373 #define STRICT_ALIGNMENT 0
374 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
375 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
377 /* If a structure has a floating point field then force structure
378 to have BLKMODE, unless it is the only field. */
379 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
380 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
382 /* Number of bits in the high and low parts of a two stage
383 load of an immediate constant. */
384 #define BITS_PER_HIGH 16
385 #define BITS_PER_LO_SUM 16
387 /* Define register numbers. */
389 /* Extended-precision registers. */
400 /* Auxiliary (address) registers. */
411 /* Data page register. */
415 /* Index registers. */
420 /* Block size register. */
428 /* Status register. */
432 /* Misc. interrupt registers. */
434 #define DIE_REGNO 22 /* C4x only. */
435 #define IE_REGNO 22 /* C3x only. */
436 #define IIE_REGNO 23 /* C4x only. */
437 #define IF_REGNO 23 /* C3x only. */
438 #define IIF_REGNO 24 /* C4x only. */
439 #define IOF_REGNO 24 /* C3x only. */
441 /* Repeat block registers. */
447 /* Additional extended-precision registers. */
449 #define R8_REGNO 28 /* C4x only. */
450 #define R9_REGNO 29 /* C4x only. */
451 #define R10_REGNO 30 /* C4x only. */
452 #define R11_REGNO 31 /* C4x only. */
454 #define FIRST_PSEUDO_REGISTER 32
456 /* Extended precision registers (low set). */
458 #define IS_R0R1_REGNO(r) \
459 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
460 #define IS_R2R3_REGNO(r) \
461 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
462 #define IS_EXT_LOW_REGNO(r) \
463 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
465 /* Extended precision registers (high set). */
467 #define IS_EXT_HIGH_REGNO(r) \
469 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
471 /* Address registers. */
473 #define IS_AUX_REGNO(r) \
474 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
475 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
476 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
477 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
478 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
479 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
481 /* Misc registers. */
483 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
484 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
485 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
487 /* Composite register sets. */
489 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
490 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
491 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
492 || IS_REPEAT_REGNO(r) \
495 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
496 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
497 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
498 || ((r) == R8_REGNO))
499 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
501 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
502 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
503 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
504 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
505 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
506 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
509 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
510 || IS_PSEUDO_REGNO(r))
511 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
512 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
513 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
514 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
516 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
517 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
518 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
519 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
520 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
521 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
522 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
524 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
525 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
526 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
527 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
528 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
529 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
531 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
532 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
533 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
534 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
535 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
536 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
538 /* 1 for registers that have pervasive standard uses
539 and are not available for the register allocator. */
541 #define FIXED_REGISTERS \
543 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
545 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
546 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
549 /* 1 for registers not available across function calls.
550 These must include the FIXED_REGISTERS and also any
551 registers that can be used without being saved.
552 The latter must include the registers where values are returned
553 and the register where structure-value addresses are passed.
554 Aside from that, you can include as many other registers as you like.
556 Note that the extended precision registers are only saved in some
557 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
558 get clobbered for a given regno. */
560 #define CALL_USED_REGISTERS \
562 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
563 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
564 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
568 /* Macro to conditionally modify fixed_regs/call_used_regs. */
570 #define CONDITIONAL_REGISTER_USAGE \
574 fixed_regs[BK_REGNO] = 1; \
575 call_used_regs[BK_REGNO] = 1; \
576 c4x_regclass_map[BK_REGNO] = NO_REGS; \
582 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
583 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
584 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
586 for (i = R8_REGNO; i <= R11_REGNO; i++) \
588 fixed_regs[i] = call_used_regs[i] = 1; \
589 c4x_regclass_map[i] = NO_REGS; \
592 if (TARGET_PRESERVE_FLOAT) \
594 c4x_caller_save_map[R6_REGNO] = HFmode; \
595 c4x_caller_save_map[R7_REGNO] = HFmode; \
599 /* Order of Allocation of Registers. */
601 /* List the order in which to allocate registers. Each register must be
602 listed once, even those in FIXED_REGISTERS.
604 First allocate registers that don't need preservation across calls,
605 except index and address registers. Then allocate data registers
606 that require preservation across calls (even though this invokes an
607 extra overhead of having to save/restore these registers). Next
608 allocate the address and index registers, since using these
609 registers for arithmetic can cause pipeline stalls. Finally
610 allocated the fixed registers which won't be allocated anyhow. */
612 #define REG_ALLOC_ORDER \
613 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
614 R9_REGNO, R10_REGNO, R11_REGNO, \
615 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
616 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
617 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
618 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
619 IR0_REGNO, IR1_REGNO, \
620 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
622 /* A C expression that is nonzero if hard register number REGNO2 can be
623 considered for use as a rename register for REGNO1 */
625 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
626 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
628 /* Determine which register classes are very likely used by spill registers.
629 local-alloc.c won't allocate pseudos that have these classes as their
630 preferred class unless they are "preferred or nothing". */
632 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
634 /* CCmode is wrongly defined in machmode.def. It should have a size
635 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
636 extended precision register. Similarly, HCmode fits within two
637 extended precision registers. */
639 #define HARD_REGNO_NREGS(REGNO, MODE) \
640 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
641 ((MODE) == HFmode) ? 1 : \
642 ((MODE) == HCmode) ? 2 : \
643 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
646 /* A C expression that is nonzero if the hard register REGNO is preserved
647 across a call in mode MODE. This does not have to include the call used
650 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
651 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
652 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
653 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
655 /* Specify the modes required to caller save a given hard regno. */
657 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
659 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
661 /* A C expression that is nonzero if it is desirable to choose
662 register allocation so as to avoid move instructions between a
663 value of mode MODE1 and a value of mode MODE2.
665 Value is 1 if it is a good idea to tie two pseudo registers
666 when one has mode MODE1 and one has mode MODE2.
667 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
668 for any hard reg, then this must be 0 for correct output. */
670 #define MODES_TIEABLE_P(MODE1, MODE2) 0
673 /* Define the classes of registers for register constraints in the
674 machine description. Also define ranges of constants.
676 One of the classes must always be named ALL_REGS and include all hard regs.
677 If there is more than one class, another class must be named NO_REGS
678 and contain no registers.
680 The name GENERAL_REGS must be the name of a class (or an alias for
681 another name such as ALL_REGS). This is the class of registers
682 that is allowed by "g" or "r" in a register constraint.
683 Also, registers outside this class are allocated only when
684 instructions express preferences for them.
686 The classes must be numbered in nondecreasing order; that is,
687 a larger-numbered class must never be contained completely
688 in a smaller-numbered class.
690 For any two classes, it is very desirable that there be another
691 class that represents their union. */
696 R0R1_REGS, /* 't'. */
697 R2R3_REGS, /* 'u'. */
698 EXT_LOW_REGS, /* 'q'. */
700 ADDR_REGS, /* 'a'. */
701 INDEX_REGS, /* 'x'. */
707 GENERAL_REGS, /* 'r'. */
714 #define N_REG_CLASSES (int) LIM_REG_CLASSES
716 #define REG_CLASS_NAMES \
736 /* Define which registers fit in which classes.
737 This is an initializer for a vector of HARD_REG_SET
738 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
739 since the register allocator will often choose a general register
740 in preference to RC for the decrement_and_branch_on_count pattern. */
742 #define REG_CLASS_CONTENTS \
744 {0x00000000}, /* No registers. */ \
745 {0x00000003}, /* 't' R0-R1 . */ \
746 {0x0000000c}, /* 'u' R2-R3 . */ \
747 {0x000000ff}, /* 'q' R0-R7 . */ \
748 {0xf00000ff}, /* 'f' R0-R11 */ \
749 {0x0000ff00}, /* 'a' AR0-AR7. */ \
750 {0x00060000}, /* 'x' IR0-IR1. */ \
751 {0x00080000}, /* 'k' BK. */ \
752 {0x00100000}, /* 'b' SP. */ \
753 {0x08000000}, /* 'v' RC. */ \
754 {0x0800ff00}, /* RC,AR0-AR7. */ \
755 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
756 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
757 {0x00010000}, /* 'z' DP. */ \
758 {0x00200000}, /* 'y' ST. */ \
759 {0xffffffff}, /* All registers. */ \
762 /* The same information, inverted:
763 Return the class number of the smallest class containing
764 reg number REGNO. This could be a conditional expression
765 or could index an array. */
767 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
769 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
770 explicitly used in the rtl is kept as short as possible.
772 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
773 is defined since the MPY|ADD insns require the classes R0R1_REGS and
774 R2R3_REGS which are used by the function return registers (R0,R1) and
775 the register arguments (R2,R3), respectively. I'm reluctant to define
776 this macro since it stomps on many potential optimisations. Ideally
777 it should have a register class argument so that not all the register
778 classes gets penalised for the sake of a naughty few... For long
779 double arithmetic we need two additional registers that we can use as
782 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
784 #define BASE_REG_CLASS ADDR_REGS
785 #define INDEX_REG_CLASS INDEX_REGS
788 Register constraints for the C4x
790 a - address reg (ar0-ar7)
792 c - other gp int-only reg
793 d - data/int reg (equiv. to f)
795 h - data/long double reg (equiv. to f)
800 v - repeat count (rc)
801 x - index register (ir0-ir1)
802 y - status register (st)
805 Memory/constant constraints for the C4x
807 G - short float 16-bit
808 I - signed 16-bit constant (sign extended)
809 J - signed 8-bit constant (sign extended) (C4x only)
810 K - signed 5-bit constant (sign extended) (C4x only for stik)
811 L - unsigned 16-bit constant
812 M - unsigned 8-bit constant (C4x only)
813 N - ones complement of unsigned 16-bit constant
814 Q - indirect arx + 9-bit signed displacement
815 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
816 R - indirect arx + 5-bit unsigned displacement (C4x only)
817 S - indirect arx + 0, 1, or irn displacement
818 T - direct symbol ref
819 > - indirect with autoincrement
820 < - indirect with autodecrement
821 } - indirect with post-modify
822 { - indirect with pre-modify
825 #define REG_CLASS_FROM_LETTER(CC) \
826 ( ((CC) == 'a') ? ADDR_REGS \
827 : ((CC) == 'b') ? SP_REG \
828 : ((CC) == 'c') ? INT_REGS \
829 : ((CC) == 'd') ? EXT_REGS \
830 : ((CC) == 'f') ? EXT_REGS \
831 : ((CC) == 'h') ? EXT_REGS \
832 : ((CC) == 'k') ? BK_REG \
833 : ((CC) == 'q') ? EXT_LOW_REGS \
834 : ((CC) == 't') ? R0R1_REGS \
835 : ((CC) == 'u') ? R2R3_REGS \
836 : ((CC) == 'v') ? RC_REG \
837 : ((CC) == 'x') ? INDEX_REGS \
838 : ((CC) == 'y') ? ST_REG \
839 : ((CC) == 'z') ? DP_REG \
842 /* These assume that REGNO is a hard or pseudo reg number.
843 They give nonzero only if REGNO is a hard reg of the suitable class
844 or a pseudo reg currently allocated to a suitable hard reg.
845 Since they use reg_renumber, they are safe only once reg_renumber
846 has been allocated, which happens in local-alloc.c. */
848 #define REGNO_OK_FOR_BASE_P(REGNO) \
849 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
851 #define REGNO_OK_FOR_INDEX_P(REGNO) \
852 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
854 /* If we have to generate framepointer + constant prefer an ADDR_REGS
855 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
857 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
858 (GET_CODE (X) == PLUS \
859 && GET_MODE (X) == Pmode \
860 && GET_CODE (XEXP ((X), 0)) == REG \
861 && GET_MODE (XEXP ((X), 0)) == Pmode \
862 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
863 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
864 ? ADDR_REGS : (CLASS))
866 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
868 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
870 #define CLASS_MAX_NREGS(CLASS, MODE) \
871 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
872 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
874 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
876 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
878 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
880 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
882 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
884 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
886 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
888 #define IS_HIGH_CONST(VAL) \
889 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
892 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
894 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
896 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
897 && IS_DISP1_CONST (VAL + 1))
899 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
900 && IS_DISP8_CONST (VAL + 1))
902 #define CONST_OK_FOR_LETTER_P(VAL, C) \
903 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
904 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
905 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
906 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
907 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
908 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
909 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
912 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
913 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
914 : ((C) == 'H') ? (c4x_H_constant (OP)) \
917 #define EXTRA_CONSTRAINT(OP, C) \
918 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
919 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
920 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
921 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
922 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
925 #define SMALL_CONST(VAL, insn) \
926 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
927 ? IS_INT16_CONST (VAL) \
928 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
929 ? IS_NOT_UINT16_CONST (VAL) \
930 : ( (get_attr_data (insn) == DATA_HIGH_16) \
931 ? IS_HIGH_CONST (VAL) \
932 : IS_UINT16_CONST (VAL) \
938 I. Routine calling with arguments in registers
939 ----------------------------------------------
941 The TI C3x compiler has a rather unusual register passing algorithm.
942 Data is passed in the following registers (in order):
944 AR2, R2, R3, RC, RS, RE
946 However, the first and second floating point values are always in R2
947 and R3 (and all other floats are on the stack). Structs are always
948 passed on the stack. If the last argument is an ellipsis, the
949 previous argument is passed on the stack so that its address can be
950 taken for the stdargs macros.
952 Because of this, we have to pre-scan the list of arguments to figure
953 out what goes where in the list.
955 II. Routine calling with arguments on stack
956 -------------------------------------------
958 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
959 variables loc0, loc1, and loc2. After the function prologue has
960 been executed, the stack frame will look like:
962 [stack grows towards increasing addresses]
964 5 I saved reg1 I <= SP points here
974 0 I old FP I <= FP (AR3) points here
985 All local variables (locn) are accessible by means of +FP(n+1)
986 addressing, where n is the local variable number.
988 All stack arguments (argn) are accessible by means of -FP(n-2).
990 The stack pointer (SP) points to the last register saved in the
993 Note that a push instruction performs a preincrement of the stack
994 pointer. (STACK_PUSH_CODE == PRE_INC)
996 III. Registers used in function calling convention
997 --------------------------------------------------
999 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
1000 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1003 (Because of this model, we only assign FP values in R6, R7 and
1004 only assign integer values in R4, R5.)
1006 These registers are saved at each function entry and restored at
1007 the exit. Also it is expected any of these not affected by any
1008 call to user-defined (not service) functions.
1010 Not preserved across calls: R0...R3
1011 R4...R5 (upper 8 bits)
1012 R6...R7 (lower 8 bits)
1013 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1015 These registers are used arbitrary in a function without being preserved.
1016 It is also expected that any of these can be clobbered by any call.
1018 Not used by GCC (except for in user "asm" statements):
1019 IE (DIE), IF (IIE), IOF (IIF)
1021 These registers are never used by GCC for any data, but can be used
1022 with "asm" statements. */
1027 /* Basic Stack Layout. */
1029 /* The stack grows upward, stack frame grows upward, and args grow
1032 #define STARTING_FRAME_OFFSET C4X_LOC0
1033 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1034 #define ARGS_GROW_DOWNWARD
1035 #define STACK_POINTER_OFFSET 1
1037 /* Define this if pushing a word on the stack
1038 makes the stack pointer a smaller address. */
1040 /* #define STACK_GROWS_DOWNWARD. */
1041 /* Like the dsp16xx, i370, i960, and we32k ports. */
1043 /* Define this if the nominal address of the stack frame
1044 is at the high-address end of the local variables;
1045 that is, each additional local variable allocated
1046 goes at a more negative offset in the frame. */
1048 /* #define FRAME_GROWS_DOWNWARD. */
1051 /* Registers That Address the Stack Frame. */
1053 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1054 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1055 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1056 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1058 /* Eliminating Frame Pointer and Arg Pointer. */
1060 #define FRAME_POINTER_REQUIRED 0
1062 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1066 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1067 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1068 offset += TARGET_PRESERVE_FLOAT \
1069 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1070 (DEPTH) = -(offset + get_frame_size ()); \
1073 /* This is a hack... We need to specify a register. */
1074 #define ELIMINABLE_REGS \
1075 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1077 #define CAN_ELIMINATE(FROM, TO) \
1078 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1079 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1081 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1085 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1086 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1087 offset += TARGET_PRESERVE_FLOAT \
1088 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1089 (OFFSET) = -(offset + get_frame_size ()); \
1093 /* Passing Function Arguments on the Stack. */
1096 #define PUSH_ROUNDING(BYTES) (BYTES)
1097 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1099 /* The following structure is used by calls.c, function.c, c4x.c. */
1101 typedef struct c4x_args
1114 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1115 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1117 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1118 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1120 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1121 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1123 /* Define the profitability of saving registers around calls.
1124 We disable caller save to avoid a bug in flow.c (this also affects
1125 other targets such as m68k). Since we must use stf/sti,
1126 the profitability is marginal anyway. */
1128 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1130 /* Never pass data by reference. */
1132 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1134 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1136 /* 1 if N is a possible register number for function argument passing. */
1138 #define FUNCTION_ARG_REGNO_P(REGNO) \
1139 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1140 || ((REGNO) == R2_REGNO) /* R2. */ \
1141 || ((REGNO) == R3_REGNO) /* R3. */ \
1142 || ((REGNO) == RC_REGNO) /* RC. */ \
1143 || ((REGNO) == RS_REGNO) /* RS. */ \
1144 || ((REGNO) == RE_REGNO)) /* RE. */ \
1148 /* How Scalar Function Values Are Returned. */
1150 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1151 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1153 #define LIBCALL_VALUE(MODE) \
1154 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1156 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1158 /* How Large Values Are Returned. */
1160 #define DEFAULT_PCC_STRUCT_RETURN 0
1161 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1163 /* Varargs handling. */
1165 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1166 c4x_va_arg (valist, type)
1168 /* Generating Code for Profiling. */
1170 /* Note that the generated assembly uses the ^ operator to load the 16
1171 MSBs of the address. This is not supported by the TI assembler.
1172 The FUNCTION profiler needs a function mcount which gets passed
1173 a pointer to the LABELNO. */
1175 #define FUNCTION_PROFILER(FILE, LABELNO) \
1178 fprintf (FILE, "\tpush\tar2\n"); \
1179 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1180 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1181 fprintf (FILE, "\tcall\tmcount\n"); \
1182 fprintf (FILE, "\tpop\tar2\n"); \
1186 fprintf (FILE, "\tpush\tar2\n"); \
1187 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1188 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1189 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1190 fprintf (FILE, "\tcall\tmcount\n"); \
1191 fprintf (FILE, "\tpop\tar2\n"); \
1194 /* Implicit Calls to Library Routines. */
1196 #define MULQI3_LIBCALL "__mulqi3"
1197 #define DIVQI3_LIBCALL "__divqi3"
1198 #define UDIVQI3_LIBCALL "__udivqi3"
1199 #define MODQI3_LIBCALL "__modqi3"
1200 #define UMODQI3_LIBCALL "__umodqi3"
1202 #define DIVQF3_LIBCALL "__divqf3"
1204 #define MULHF3_LIBCALL "__mulhf3"
1205 #define DIVHF3_LIBCALL "__divhf3"
1207 #define MULHI3_LIBCALL "__mulhi3"
1208 #define SMULHI3_LIBCALL "__smulhi3_high"
1209 #define UMULHI3_LIBCALL "__umulhi3_high"
1210 #define DIVHI3_LIBCALL "__divhi3"
1211 #define UDIVHI3_LIBCALL "__udivhi3"
1212 #define MODHI3_LIBCALL "__modhi3"
1213 #define UMODHI3_LIBCALL "__umodhi3"
1215 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1216 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1217 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1218 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1220 #define FLOATHIHF2_LIBCALL "__floathihf2"
1221 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1222 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1223 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1225 #define FFS_LIBCALL "__ffs"
1227 #define INIT_TARGET_OPTABS \
1229 smul_optab->handlers[(int) QImode].libfunc \
1230 = init_one_libfunc (MULQI3_LIBCALL); \
1231 sdiv_optab->handlers[(int) QImode].libfunc \
1232 = init_one_libfunc (DIVQI3_LIBCALL); \
1233 udiv_optab->handlers[(int) QImode].libfunc \
1234 = init_one_libfunc (UDIVQI3_LIBCALL); \
1235 smod_optab->handlers[(int) QImode].libfunc \
1236 = init_one_libfunc (MODQI3_LIBCALL); \
1237 umod_optab->handlers[(int) QImode].libfunc \
1238 = init_one_libfunc (UMODQI3_LIBCALL); \
1239 sdiv_optab->handlers[(int) QFmode].libfunc \
1240 = init_one_libfunc (DIVQF3_LIBCALL); \
1241 smul_optab->handlers[(int) HFmode].libfunc \
1242 = init_one_libfunc (MULHF3_LIBCALL); \
1243 sdiv_optab->handlers[(int) HFmode].libfunc \
1244 = init_one_libfunc (DIVHF3_LIBCALL); \
1245 smul_optab->handlers[(int) HImode].libfunc \
1246 = init_one_libfunc (MULHI3_LIBCALL); \
1247 sdiv_optab->handlers[(int) HImode].libfunc \
1248 = init_one_libfunc (DIVHI3_LIBCALL); \
1249 udiv_optab->handlers[(int) HImode].libfunc \
1250 = init_one_libfunc (UDIVHI3_LIBCALL); \
1251 smod_optab->handlers[(int) HImode].libfunc \
1252 = init_one_libfunc (MODHI3_LIBCALL); \
1253 umod_optab->handlers[(int) HImode].libfunc \
1254 = init_one_libfunc (UMODHI3_LIBCALL); \
1255 ffs_optab->handlers[(int) QImode].libfunc \
1256 = init_one_libfunc (FFS_LIBCALL); \
1258 = init_one_libfunc(SMULHI3_LIBCALL); \
1260 = init_one_libfunc(UMULHI3_LIBCALL); \
1261 fix_truncqfhi2_libfunc \
1262 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
1263 fixuns_truncqfhi2_libfunc \
1264 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
1265 fix_trunchfhi2_libfunc \
1266 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
1267 fixuns_trunchfhi2_libfunc \
1268 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
1269 floathiqf2_libfunc \
1270 = init_one_libfunc(FLOATHIQF2_LIBCALL); \
1271 floatunshiqf2_libfunc \
1272 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
1273 floathihf2_libfunc \
1274 = init_one_libfunc(FLOATHIHF2_LIBCALL); \
1275 floatunshihf2_libfunc \
1276 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
1279 #define TARGET_MEM_FUNCTIONS
1281 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1283 CCmode should be used when no special processing is needed. */
1284 #define SELECT_CC_MODE(OP,X,Y) \
1285 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1286 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1287 || GET_MODE (X) == ABS \
1288 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1289 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1290 || GET_MODE (Y) == ABS) \
1291 ? CC_NOOVmode : CCmode)
1293 /* Addressing Modes. */
1295 #define HAVE_POST_INCREMENT 1
1296 #define HAVE_PRE_INCREMENT 1
1297 #define HAVE_POST_DECREMENT 1
1298 #define HAVE_PRE_DECREMENT 1
1299 #define HAVE_PRE_MODIFY_REG 1
1300 #define HAVE_POST_MODIFY_REG 1
1301 #define HAVE_PRE_MODIFY_DISP 1
1302 #define HAVE_POST_MODIFY_DISP 1
1304 /* The number of insns that can be packed into a single opcode. */
1305 #define PACK_INSNS 2
1307 /* Recognize any constant value that is a valid address.
1308 We could allow arbitrary constant addresses in the large memory
1309 model but for the small memory model we can only accept addresses
1310 within the data page. I suppose we could also allow
1311 CONST PLUS SYMBOL_REF. */
1312 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1314 /* Maximum number of registers that can appear in a valid memory
1316 #define MAX_REGS_PER_ADDRESS 2
1318 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1319 and check its validity for a certain class.
1320 We have two alternate definitions for each of them.
1321 The usual definition accepts all pseudo regs; the other rejects
1322 them unless they have been allocated suitable hard regs.
1323 The symbol REG_OK_STRICT causes the latter definition to be used.
1325 Most source files want to accept pseudo regs in the hope that
1326 they will get allocated to the class that the insn wants them to be in.
1327 Source files for reload pass need to be strict.
1328 After reload, it makes no difference, since pseudo regs have
1329 been eliminated by then. */
1331 #ifndef REG_OK_STRICT
1333 /* Nonzero if X is a hard or pseudo reg that can be used as a base. */
1335 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1337 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1339 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1341 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1343 if (c4x_check_legit_addr (MODE, X, 0)) \
1349 /* Nonzero if X is a hard reg that can be used as an index. */
1351 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1353 /* Nonzero if X is a hard reg that can be used as a base reg. */
1355 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1357 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1359 if (c4x_check_legit_addr (MODE, X, 1)) \
1365 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1368 new = c4x_legitimize_address (X, MODE); \
1369 if (new != NULL_RTX) \
1376 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1378 if (MODE != HImode \
1380 && GET_MODE (X) != HImode \
1381 && GET_MODE (X) != HFmode \
1382 && (GET_CODE (X) == CONST \
1383 || GET_CODE (X) == SYMBOL_REF \
1384 || GET_CODE (X) == LABEL_REF)) \
1386 if (! TARGET_SMALL) \
1389 X = gen_rtx_LO_SUM (GET_MODE (X), \
1390 gen_rtx_HIGH (GET_MODE (X), X), X); \
1391 i = push_reload (XEXP (X, 0), NULL_RTX, \
1392 &XEXP (X, 0), NULL, \
1393 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1395 /* The only valid reg is DP. This is a fixed reg and will \
1396 normally not be used so force it. */ \
1397 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1398 rld[i].nocombine = 1; \
1402 else if (MODE != HImode \
1404 && GET_MODE (X) != HImode \
1405 && GET_MODE (X) != HFmode \
1406 && GET_CODE (X) == LO_SUM \
1407 && GET_CODE (XEXP (X,0)) == HIGH \
1408 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1409 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1410 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1412 if (! TARGET_SMALL) \
1414 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1415 &XEXP (X, 0), NULL, \
1416 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1418 /* The only valid reg is DP. This is a fixed reg and will \
1419 normally not be used so force it. */ \
1420 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1421 rld[i].nocombine = 1; \
1427 /* No mode-dependent addresses on the C4x are autoincrements. */
1429 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1430 if (GET_CODE (ADDR) == PRE_DEC \
1431 || GET_CODE (ADDR) == POST_DEC \
1432 || GET_CODE (ADDR) == PRE_INC \
1433 || GET_CODE (ADDR) == POST_INC \
1434 || GET_CODE (ADDR) == POST_MODIFY \
1435 || GET_CODE (ADDR) == PRE_MODIFY) \
1439 /* Nonzero if the constant value X is a legitimate general operand.
1440 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1442 The C4x can only load 16-bit immediate values, so we only allow a
1443 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1444 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1445 model) so that the symbols will be forced into the constant pool.
1446 On second thoughts, let's do this with the move expanders since
1447 the alias analysis has trouble if we force constant addresses
1451 #define LEGITIMATE_CONSTANT_P(X) \
1452 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1453 || (GET_CODE (X) == CONST_INT) \
1454 || (GET_CODE (X) == SYMBOL_REF) \
1455 || (GET_CODE (X) == LABEL_REF) \
1456 || (GET_CODE (X) == CONST) \
1457 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1458 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1460 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1462 /* Descripting Relative Cost of Operations. */
1464 /* Compute the cost of an address. This is meant to approximate the size
1465 and/or execution delay of an insn using that address. The value of this
1466 macro only matters for valid addresses. We handle the most common address
1467 without a call to c4x_address_cost. */
1469 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1471 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1472 if (REG_P (OP1) && ! REG_P (OP0)) \
1474 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1475 CODE = swap_condition (CODE); \
1478 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1479 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1480 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1481 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1482 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1484 /* Compute extra cost of moving data between one register class
1487 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1489 /* Memory move cost is same as fast register move. Maybe this should
1492 #define MEMORY_MOVE_COST(M,C,I) 4
1494 /* Branches are kind of expensive (even with delayed branching) so
1495 make their cost higher. */
1497 #define BRANCH_COST 8
1499 #define WORD_REGISTER_OPERATIONS
1501 /* Dividing the Output into Sections. */
1503 #define TEXT_SECTION_ASM_OP "\t.text"
1505 #define DATA_SECTION_ASM_OP "\t.data"
1507 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
1509 /* Do not use .init section so __main will be called on startup. This will
1510 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1513 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1516 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1518 #undef EXTRA_SECTIONS
1519 #define EXTRA_SECTIONS in_init, in_fini
1521 #undef EXTRA_SECTION_FUNCTIONS
1522 #define EXTRA_SECTION_FUNCTIONS \
1523 INIT_SECTION_FUNCTION \
1524 FINI_SECTION_FUNCTION
1526 #define INIT_SECTION_FUNCTION \
1527 extern void init_section PARAMS ((void)); \
1531 if (in_section != in_init) \
1533 fprintf (asm_out_file, ";\t.init\n"); \
1534 in_section = in_init; \
1538 #define FINI_SECTION_FUNCTION \
1542 if (in_section != in_fini) \
1544 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
1545 in_section = in_fini; \
1549 #define ASM_STABS_OP "\t.stabs\t"
1551 /* Switch into a generic section. */
1552 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
1555 /* Overall Framework of an Assembler File. */
1556 /* We need to have a data section we can identify so that we can set
1557 the DP register back to a data pointer in the small memory model.
1558 This is only required for ISRs if we are paranoid that someone
1559 may have quietly changed this register on the sly. */
1561 #define ASM_FILE_START(FILE) \
1563 int dspversion = 0; \
1564 if (TARGET_C30) dspversion = 30; \
1565 if (TARGET_C31) dspversion = 31; \
1566 if (TARGET_C32) dspversion = 32; \
1567 if (TARGET_C33) dspversion = 33; \
1568 if (TARGET_C40) dspversion = 40; \
1569 if (TARGET_C44) dspversion = 44; \
1570 fprintf (FILE, "\t.version\t%d\n", dspversion); \
1571 fprintf (FILE, "\t.file\t"); \
1575 const char *after_dir = main_input_filename; \
1576 for (p = main_input_filename; *p; p++) \
1578 after_dir = p + 1; \
1579 output_quoted_string (FILE, after_dir); \
1582 output_quoted_string (FILE, main_input_filename); \
1583 fputs ("\n\t.data\ndata_sec:\n", FILE); \
1586 #define ASM_COMMENT_START ";"
1588 #define ASM_APP_ON ""
1589 #define ASM_APP_OFF ""
1591 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
1593 /* Output and Generation of Labels. */
1595 #define NO_DOT_IN_LABEL /* Only required for TI format. */
1597 /* Globalizing directive for a label. */
1598 #define GLOBAL_ASM_OP "\t.global\t"
1600 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1601 c4x_external_ref (NAME)
1603 /* A C statement to output on FILE an assembler pseudo-op to
1604 declare a library function named external.
1605 (Only needed to keep asm30 happy for ___divqf3 etc.) */
1607 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1608 c4x_external_ref (XSTR (FUN, 0))
1610 #define ASM_FILE_END(FILE) \
1613 /* The prefix to add to user-visible assembler symbols. */
1615 #define USER_LABEL_PREFIX "_"
1617 /* This is how to store into the string LABEL
1618 the symbol_ref name of an internal numbered label where
1619 PREFIX is the class of label and NUM is the number within the class.
1620 This is suitable for output with `assemble_name'. */
1622 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
1623 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
1625 /* A C statement to output to the stdio stream STREAM assembler code which
1626 defines (equates) the symbol NAME to have the value VALUE. */
1628 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1630 assemble_name (STREAM, NAME); \
1631 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
1634 /* Output of Dispatch Tables. */
1636 /* This is how to output an element of a case-vector that is absolute. */
1638 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1639 fprintf (FILE, "\t.long\tL%d\n", VALUE);
1641 /* This is how to output an element of a case-vector that is relative. */
1643 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1644 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
1647 #define SIZE_TYPE "unsigned int"
1650 #define PTRDIFF_TYPE "int"
1653 #define WCHAR_TYPE "long int"
1655 #undef WCHAR_TYPE_SIZE
1656 #define WCHAR_TYPE_SIZE 32
1658 #define INT_TYPE_SIZE 32
1659 #define LONG_LONG_TYPE_SIZE 64
1660 #define FLOAT_TYPE_SIZE 32
1661 #define DOUBLE_TYPE_SIZE 32
1662 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
1664 /* Output #ident as a .ident. */
1666 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1667 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
1669 /* Output of Uninitialized Variables. */
1671 /* This says how to output an assembler line to define a local
1672 uninitialized variable. */
1674 #undef ASM_OUTPUT_LOCAL
1675 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1676 ( fputs ("\t.bss\t", FILE), \
1677 assemble_name (FILE, (NAME)), \
1678 fprintf (FILE, ",%u\n", (ROUNDED)))
1680 /* This says how to output an assembler line to define a global
1681 uninitialized variable. */
1683 #undef ASM_OUTPUT_COMMON
1684 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1685 ( fputs ("\t.globl\t", FILE), \
1686 assemble_name (FILE, (NAME)), \
1687 fputs ("\n\t.bss\t", FILE), \
1688 assemble_name (FILE, (NAME)), \
1689 fprintf (FILE, ",%u\n", (ROUNDED)))
1691 #undef ASM_OUTPUT_BSS
1692 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1693 ( fputs ("\t.globl\t", FILE), \
1694 assemble_name (FILE, (NAME)), \
1695 fputs ("\n\t.bss\t", FILE), \
1696 assemble_name (FILE, (NAME)), \
1697 fprintf (FILE, ",%u\n", (SIZE)))
1699 /* Macros Controlling Initialization Routines. */
1701 #define OBJECT_FORMAT_COFF
1702 #define REAL_NM_FILE_NAME "c4x-nm"
1704 /* Output of Assembler Instructions. */
1706 /* Register names when used for integer modes. */
1708 #define REGISTER_NAMES \
1710 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1711 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1712 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1713 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
1716 /* Alternate register names when used for floating point modes. */
1718 #define FLOAT_REGISTER_NAMES \
1720 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1721 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1722 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1723 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
1726 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
1728 /* Determine which codes are valid without a following integer. These must
1729 not be alphabetic. */
1731 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
1733 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
1735 /* C4x specific pragmas. */
1736 #define REGISTER_TARGET_PRAGMAS() do { \
1737 c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
1738 c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
1739 c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
1740 c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
1741 c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
1742 c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
1743 c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
1744 c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
1745 c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
1746 c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
1749 /* Assembler Commands for Alignment. */
1751 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
1753 for (; c > 0; --c) \
1754 fprintf (FILE,"\t.word\t0\n"); \
1757 #define ASM_NO_SKIP_IN_TEXT 1
1759 /* I'm not sure about this one. FIXME. */
1761 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
1763 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
1766 /* Macros for SDB and DWARF Output (use .sdef instead of .def
1767 to avoid conflict with TI's use of .def). */
1769 #define SDB_DELIM "\n"
1770 #define SDB_DEBUGGING_INFO 1
1772 /* Don't use octal since this can confuse gas for the c4x. */
1773 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
1775 #define PUT_SDB_DEF(A) \
1776 do { fprintf (asm_out_file, "\t.sdef\t"); \
1777 ASM_OUTPUT_LABELREF (asm_out_file, A); \
1778 fprintf (asm_out_file, SDB_DELIM); } while (0)
1780 #define PUT_SDB_PLAIN_DEF(A) \
1781 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
1783 #define PUT_SDB_BLOCK_START(LINE) \
1784 fprintf (asm_out_file, \
1785 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1786 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1788 #define PUT_SDB_BLOCK_END(LINE) \
1789 fprintf (asm_out_file, \
1790 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1791 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1793 #define PUT_SDB_FUNCTION_START(LINE) \
1794 fprintf (asm_out_file, \
1795 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1796 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1798 /* Note we output relative line numbers for .ef which gas converts
1799 to absolute line numbers. The TI compiler outputs absolute line numbers
1800 in the .sym directive which gas does not support. */
1801 #define PUT_SDB_FUNCTION_END(LINE) \
1802 fprintf (asm_out_file, \
1803 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1804 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
1807 #define PUT_SDB_EPILOGUE_END(NAME) \
1808 do { fprintf (asm_out_file, "\t.sdef\t"); \
1809 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
1810 fprintf (asm_out_file, \
1811 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
1812 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
1814 /* Define this as 1 if `char' should by default be signed; else as 0. */
1816 #define DEFAULT_SIGNED_CHAR 1
1818 /* A function address in a call instruction is a byte address (for
1819 indexing purposes) so give the MEM rtx a byte's mode. */
1821 #define FUNCTION_MODE QImode
1823 #define SLOW_BYTE_ACCESS 0
1825 /* Specify the machine mode that pointers have. After generation of
1826 RTL, the compiler makes no further distinction between pointers and
1827 any other objects of this machine mode. */
1829 #define Pmode QImode
1831 /* On the C4x we can write the following code. We have to clear the cache
1832 every time we execute it because the data in the stack could change.
1845 On the c3x this is a bit more difficult. We have to write self
1846 modifying code here. So we have to clear the cache every time
1847 we execute it because the data in the stack could change.
1849 ldiu TOP_OF_FUNCTION,ar1
1851 or BOTTOM_OF_FUNCTION,ar1
1852 ldiu TOP_OF_STATIC,ar0
1855 or BOTTOM_OF_STATIC,ar0
1860 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
1862 #define TRAMPOLINE_TEMPLATE(FILE) \
1866 fprintf (FILE, "\tldiu\t0,ar1\n"); \
1867 fprintf (FILE, "\tlsh\t16,ar1\n"); \
1868 fprintf (FILE, "\tor\t0,ar1\n"); \
1869 fprintf (FILE, "\tldiu\t0,ar0\n"); \
1870 fprintf (FILE, "\tbud\tar1\n"); \
1871 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1872 fprintf (FILE, "\tor\t0,ar0\n"); \
1873 fprintf (FILE, "\tor\t1000h,st\n"); \
1877 fprintf (FILE, "\tlaj\t$+4\n"); \
1878 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
1879 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
1880 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
1881 fprintf (FILE, "\tbud\tar1\n"); \
1882 fprintf (FILE, "\tnop\n"); \
1883 fprintf (FILE, "\tnop\n"); \
1884 fprintf (FILE, "\tor\t1000h,st\n"); \
1885 fprintf (FILE, "\t.word\t0\n"); \
1886 fprintf (FILE, "\t.word\t0\n"); \
1890 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1895 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
1896 size_int (16), 0, 1); \
1897 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1898 GEN_INT (0x5069), size_int (16), 0, 1); \
1899 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1900 emit_move_insn (gen_rtx (MEM, QImode, \
1901 plus_constant (tramp, 0)), tmp1); \
1902 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
1903 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1904 GEN_INT (0x1069), size_int (16), 0, 1); \
1905 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1906 emit_move_insn (gen_rtx (MEM, QImode, \
1907 plus_constant (tramp, 2)), tmp1); \
1908 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
1909 size_int (16), 0, 1); \
1910 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1911 GEN_INT (0x5068), size_int (16), 0, 1); \
1912 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1913 emit_move_insn (gen_rtx (MEM, QImode, \
1914 plus_constant (tramp, 3)), tmp1); \
1915 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
1916 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1917 GEN_INT (0x1068), size_int (16), 0, 1); \
1918 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1919 emit_move_insn (gen_rtx (MEM, QImode, \
1920 plus_constant (tramp, 6)), tmp1); \
1924 emit_move_insn (gen_rtx (MEM, QImode, \
1925 plus_constant (TRAMP, 8)), FNADDR); \
1926 emit_move_insn (gen_rtx (MEM, QImode, \
1927 plus_constant (TRAMP, 9)), CXT); \
1931 /* Specify the machine mode that this machine uses for the index in
1932 the tablejump instruction. */
1934 #define CASE_VECTOR_MODE Pmode
1936 /* Max number of (32-bit) bytes we can move from memory to memory
1937 in one reasonably fast instruction. */
1941 /* MOVE_RATIO is the number of move instructions that is better than a
1944 #define MOVE_RATIO 3
1946 #define BSS_SECTION_ASM_OP "\t.bss"
1948 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1949 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
1951 /* This is how to output an insn to pop a register from the stack.
1952 It need not be very fast code. */
1954 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1955 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
1957 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1958 is done just by pretending it is already truncated. */
1960 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1962 /* We need to use direct addressing for large constants and addresses
1963 that cannot fit within an instruction. We must check for these
1964 after after the final jump optimisation pass, since this may
1965 introduce a local_move insn for a SYMBOL_REF. This pass
1966 must come before delayed branch slot filling since it can generate
1967 additional instructions. */
1969 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
1971 #define DBR_OUTPUT_SEQEND(FILE) \
1972 if (final_sequence != NULL_RTX) \
1975 rtx insn = XVECEXP (final_sequence, 0, 0); \
1976 int laj = GET_CODE (insn) == CALL_INSN \
1977 || (GET_CODE (insn) == INSN \
1978 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
1980 count = dbr_sequence_length(); \
1981 while (count < (laj ? 2 : 3)) \
1983 fputs("\tnop\n", FILE); \
1987 fputs("\tpush\tr11\n", FILE); \
1990 #define NO_FUNCTION_CSE
1992 /* We don't want a leading tab. */
1994 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
1996 /* Define the codes that are matched by predicates in c4x.c. */
1998 #define PREDICATE_CODES \
1999 {"fp_zero_operand", {CONST_DOUBLE}}, \
2000 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2001 {"stik_const_operand", {CONST_INT}}, \
2002 {"not_const_operand", {CONST_INT}}, \
2003 {"reg_operand", {REG, SUBREG}}, \
2004 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2005 {"r0r1_reg_operand", {REG, SUBREG}}, \
2006 {"r2r3_reg_operand", {REG, SUBREG}}, \
2007 {"ext_low_reg_operand", {REG, SUBREG}}, \
2008 {"ext_reg_operand", {REG, SUBREG}}, \
2009 {"std_reg_operand", {REG, SUBREG}}, \
2010 {"std_or_reg_operand", {REG, SUBREG}}, \
2011 {"addr_reg_operand", {REG, SUBREG}}, \
2012 {"index_reg_operand", {REG, SUBREG}}, \
2013 {"dp_reg_operand", {REG}}, \
2014 {"sp_reg_operand", {REG}}, \
2015 {"st_reg_operand", {REG}}, \
2016 {"rc_reg_operand", {REG}}, \
2017 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2018 {"dst_operand", {SUBREG, REG, MEM}}, \
2019 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2020 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2021 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2022 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2023 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
2024 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
2025 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2026 {"par_ind_operand", {MEM}}, \
2027 {"parallel_operand", {SUBREG, REG, MEM}}, \
2028 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2029 {"mem_operand", {MEM}},
2032 /* Define the intrinsic functions for the c3x/c4x. */
2036 /* intrinsic name */
2037 C4X_BUILTIN_FIX, /* fast_ftoi */
2038 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
2039 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
2040 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
2041 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
2042 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
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