1 /* Subroutines for assembler code output on the TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Some output-actions in c4x.md need these. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "basic-block.h"
36 #include "insn-config.h"
37 #include "insn-attr.h"
38 #include "conditions.h"
53 #include "target-def.h"
57 rtx fix_truncqfhi2_libfunc;
58 rtx fixuns_truncqfhi2_libfunc;
59 rtx fix_trunchfhi2_libfunc;
60 rtx fixuns_trunchfhi2_libfunc;
61 rtx floathiqf2_libfunc;
62 rtx floatunshiqf2_libfunc;
63 rtx floathihf2_libfunc;
64 rtx floatunshihf2_libfunc;
66 static int c4x_leaf_function;
68 static const char *const float_reg_names[] = FLOAT_REGISTER_NAMES;
70 /* Array of the smallest class containing reg number REGNO, indexed by
71 REGNO. Used by REGNO_REG_CLASS in c4x.h. We assume that all these
72 registers are available and set the class to NO_REGS for registers
73 that the target switches say are unavailable. */
75 enum reg_class c4x_regclass_map[FIRST_PSEUDO_REGISTER] =
77 /* Reg Modes Saved. */
78 R0R1_REGS, /* R0 QI, QF, HF No. */
79 R0R1_REGS, /* R1 QI, QF, HF No. */
80 R2R3_REGS, /* R2 QI, QF, HF No. */
81 R2R3_REGS, /* R3 QI, QF, HF No. */
82 EXT_LOW_REGS, /* R4 QI, QF, HF QI. */
83 EXT_LOW_REGS, /* R5 QI, QF, HF QI. */
84 EXT_LOW_REGS, /* R6 QI, QF, HF QF. */
85 EXT_LOW_REGS, /* R7 QI, QF, HF QF. */
86 ADDR_REGS, /* AR0 QI No. */
87 ADDR_REGS, /* AR1 QI No. */
88 ADDR_REGS, /* AR2 QI No. */
89 ADDR_REGS, /* AR3 QI QI. */
90 ADDR_REGS, /* AR4 QI QI. */
91 ADDR_REGS, /* AR5 QI QI. */
92 ADDR_REGS, /* AR6 QI QI. */
93 ADDR_REGS, /* AR7 QI QI. */
94 DP_REG, /* DP QI No. */
95 INDEX_REGS, /* IR0 QI No. */
96 INDEX_REGS, /* IR1 QI No. */
97 BK_REG, /* BK QI QI. */
98 SP_REG, /* SP QI No. */
99 ST_REG, /* ST CC No. */
100 NO_REGS, /* DIE/IE No. */
101 NO_REGS, /* IIE/IF No. */
102 NO_REGS, /* IIF/IOF No. */
103 INT_REGS, /* RS QI No. */
104 INT_REGS, /* RE QI No. */
105 RC_REG, /* RC QI No. */
106 EXT_REGS, /* R8 QI, QF, HF QI. */
107 EXT_REGS, /* R9 QI, QF, HF No. */
108 EXT_REGS, /* R10 QI, QF, HF No. */
109 EXT_REGS, /* R11 QI, QF, HF No. */
112 enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
114 /* Reg Modes Saved. */
115 HFmode, /* R0 QI, QF, HF No. */
116 HFmode, /* R1 QI, QF, HF No. */
117 HFmode, /* R2 QI, QF, HF No. */
118 HFmode, /* R3 QI, QF, HF No. */
119 QFmode, /* R4 QI, QF, HF QI. */
120 QFmode, /* R5 QI, QF, HF QI. */
121 QImode, /* R6 QI, QF, HF QF. */
122 QImode, /* R7 QI, QF, HF QF. */
123 QImode, /* AR0 QI No. */
124 QImode, /* AR1 QI No. */
125 QImode, /* AR2 QI No. */
126 QImode, /* AR3 QI QI. */
127 QImode, /* AR4 QI QI. */
128 QImode, /* AR5 QI QI. */
129 QImode, /* AR6 QI QI. */
130 QImode, /* AR7 QI QI. */
131 VOIDmode, /* DP QI No. */
132 QImode, /* IR0 QI No. */
133 QImode, /* IR1 QI No. */
134 QImode, /* BK QI QI. */
135 VOIDmode, /* SP QI No. */
136 VOIDmode, /* ST CC No. */
137 VOIDmode, /* DIE/IE No. */
138 VOIDmode, /* IIE/IF No. */
139 VOIDmode, /* IIF/IOF No. */
140 QImode, /* RS QI No. */
141 QImode, /* RE QI No. */
142 VOIDmode, /* RC QI No. */
143 QFmode, /* R8 QI, QF, HF QI. */
144 HFmode, /* R9 QI, QF, HF No. */
145 HFmode, /* R10 QI, QF, HF No. */
146 HFmode, /* R11 QI, QF, HF No. */
150 /* Test and compare insns in c4x.md store the information needed to
151 generate branch and scc insns here. */
156 const char *c4x_rpts_cycles_string;
157 int c4x_rpts_cycles = 0; /* Max. cycles for RPTS. */
158 const char *c4x_cpu_version_string;
159 int c4x_cpu_version = 40; /* CPU version C30/31/32/33/40/44. */
161 /* Pragma definitions. */
163 tree code_tree = NULL_TREE;
164 tree data_tree = NULL_TREE;
165 tree pure_tree = NULL_TREE;
166 tree noreturn_tree = NULL_TREE;
167 tree interrupt_tree = NULL_TREE;
168 tree naked_tree = NULL_TREE;
170 /* Forward declarations */
171 static int c4x_isr_reg_used_p PARAMS ((unsigned int));
172 static int c4x_leaf_function_p PARAMS ((void));
173 static int c4x_naked_function_p PARAMS ((void));
174 static int c4x_immed_float_p PARAMS ((rtx));
175 static int c4x_a_register PARAMS ((rtx));
176 static int c4x_x_register PARAMS ((rtx));
177 static int c4x_immed_int_constant PARAMS ((rtx));
178 static int c4x_immed_float_constant PARAMS ((rtx));
179 static int c4x_K_constant PARAMS ((rtx));
180 static int c4x_N_constant PARAMS ((rtx));
181 static int c4x_O_constant PARAMS ((rtx));
182 static int c4x_R_indirect PARAMS ((rtx));
183 static int c4x_S_indirect PARAMS ((rtx));
184 static void c4x_S_address_parse PARAMS ((rtx , int *, int *, int *, int *));
185 static int c4x_valid_operands PARAMS ((enum rtx_code, rtx *,
186 enum machine_mode, int));
187 static int c4x_arn_reg_operand PARAMS ((rtx, enum machine_mode, unsigned int));
188 static int c4x_arn_mem_operand PARAMS ((rtx, enum machine_mode, unsigned int));
189 static void c4x_check_attribute PARAMS ((const char *, tree, tree, tree *));
190 static int c4x_r11_set_p PARAMS ((rtx));
191 static int c4x_rptb_valid_p PARAMS ((rtx, rtx));
192 static int c4x_label_ref_used_p PARAMS ((rtx, rtx));
193 static tree c4x_handle_fntype_attribute PARAMS ((tree *, tree, tree, int, bool *));
194 const struct attribute_spec c4x_attribute_table[];
195 static void c4x_insert_attributes PARAMS ((tree, tree *));
196 static void c4x_asm_named_section PARAMS ((const char *, unsigned int));
197 static int c4x_adjust_cost PARAMS ((rtx, rtx, rtx, int));
198 static void c4x_encode_section_info PARAMS ((tree, int));
199 static void c4x_globalize_label PARAMS ((FILE *, const char *));
200 static bool c4x_rtx_costs PARAMS ((rtx, int, int, int *));
202 /* Initialize the GCC target structure. */
203 #undef TARGET_ASM_BYTE_OP
204 #define TARGET_ASM_BYTE_OP "\t.word\t"
205 #undef TARGET_ASM_ALIGNED_HI_OP
206 #define TARGET_ASM_ALIGNED_HI_OP NULL
207 #undef TARGET_ASM_ALIGNED_SI_OP
208 #define TARGET_ASM_ALIGNED_SI_OP NULL
210 #undef TARGET_ATTRIBUTE_TABLE
211 #define TARGET_ATTRIBUTE_TABLE c4x_attribute_table
213 #undef TARGET_INSERT_ATTRIBUTES
214 #define TARGET_INSERT_ATTRIBUTES c4x_insert_attributes
216 #undef TARGET_INIT_BUILTINS
217 #define TARGET_INIT_BUILTINS c4x_init_builtins
219 #undef TARGET_EXPAND_BUILTIN
220 #define TARGET_EXPAND_BUILTIN c4x_expand_builtin
222 #undef TARGET_SCHED_ADJUST_COST
223 #define TARGET_SCHED_ADJUST_COST c4x_adjust_cost
225 #undef TARGET_ENCODE_SECTION_INFO
226 #define TARGET_ENCODE_SECTION_INFO c4x_encode_section_info
228 #undef TARGET_ASM_GLOBALIZE_LABEL
229 #define TARGET_ASM_GLOBALIZE_LABEL c4x_globalize_label
231 #undef TARGET_RTX_COSTS
232 #define TARGET_RTX_COSTS c4x_rtx_costs
234 struct gcc_target targetm = TARGET_INITIALIZER;
236 /* Override command line options.
237 Called once after all options have been parsed.
238 Mostly we process the processor
239 type and sometimes adjust other TARGET_ options. */
242 c4x_override_options ()
244 if (c4x_rpts_cycles_string)
245 c4x_rpts_cycles = atoi (c4x_rpts_cycles_string);
250 c4x_cpu_version = 30;
252 c4x_cpu_version = 31;
254 c4x_cpu_version = 32;
256 c4x_cpu_version = 33;
258 c4x_cpu_version = 40;
260 c4x_cpu_version = 44;
262 c4x_cpu_version = 40;
264 /* -mcpu=xx overrides -m40 etc. */
265 if (c4x_cpu_version_string)
267 const char *p = c4x_cpu_version_string;
269 /* Also allow -mcpu=c30 etc. */
270 if (*p == 'c' || *p == 'C')
272 c4x_cpu_version = atoi (p);
275 target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG |
276 C40_FLAG | C44_FLAG);
278 switch (c4x_cpu_version)
280 case 30: target_flags |= C30_FLAG; break;
281 case 31: target_flags |= C31_FLAG; break;
282 case 32: target_flags |= C32_FLAG; break;
283 case 33: target_flags |= C33_FLAG; break;
284 case 40: target_flags |= C40_FLAG; break;
285 case 44: target_flags |= C44_FLAG; break;
287 warning ("unknown CPU version %d, using 40.\n", c4x_cpu_version);
288 c4x_cpu_version = 40;
289 target_flags |= C40_FLAG;
292 if (TARGET_C30 || TARGET_C31 || TARGET_C32 || TARGET_C33)
293 target_flags |= C3X_FLAG;
295 target_flags &= ~C3X_FLAG;
297 /* Convert foo / 8.0 into foo * 0.125, etc. */
298 set_fast_math_flags (1);
300 /* We should phase out the following at some stage.
301 This provides compatibility with the old -mno-aliases option. */
302 if (! TARGET_ALIASES && ! flag_argument_noalias)
303 flag_argument_noalias = 1;
305 /* We're C4X floating point, not IEEE floating point. */
306 memset (real_format_for_mode, 0, sizeof real_format_for_mode);
307 real_format_for_mode[QFmode - QFmode] = &c4x_single_format;
308 real_format_for_mode[HFmode - QFmode] = &c4x_extended_format;
312 /* This is called before c4x_override_options. */
315 c4x_optimization_options (level, size)
316 int level ATTRIBUTE_UNUSED;
317 int size ATTRIBUTE_UNUSED;
319 /* Scheduling before register allocation can screw up global
320 register allocation, especially for functions that use MPY||ADD
321 instructions. The benefit we gain we get by scheduling before
322 register allocation is probably marginal anyhow. */
323 flag_schedule_insns = 0;
327 /* Write an ASCII string. */
329 #define C4X_ASCII_LIMIT 40
332 c4x_output_ascii (stream, ptr, len)
337 char sbuf[C4X_ASCII_LIMIT + 1];
338 int s, l, special, first = 1, onlys;
341 fprintf (stream, "\t.byte\t");
343 for (s = l = 0; len > 0; --len, ++ptr)
347 /* Escape " and \ with a \". */
348 special = *ptr == '\"' || *ptr == '\\';
350 /* If printable - add to buff. */
351 if ((! TARGET_TI || ! special) && *ptr >= 0x20 && *ptr < 0x7f)
356 if (s < C4X_ASCII_LIMIT - 1)
371 fprintf (stream, "\"%s\"", sbuf);
373 if (TARGET_TI && l >= 80 && len > 1)
375 fprintf (stream, "\n\t.byte\t");
393 fprintf (stream, "%d", *ptr);
395 if (TARGET_TI && l >= 80 && len > 1)
397 fprintf (stream, "\n\t.byte\t");
408 fprintf (stream, "\"%s\"", sbuf);
411 fputc ('\n', stream);
416 c4x_hard_regno_mode_ok (regno, mode)
418 enum machine_mode mode;
423 case Pmode: /* Pointer (24/32 bits). */
425 case QImode: /* Integer (32 bits). */
426 return IS_INT_REGNO (regno);
428 case QFmode: /* Float, Double (32 bits). */
429 case HFmode: /* Long Double (40 bits). */
430 return IS_EXT_REGNO (regno);
432 case CCmode: /* Condition Codes. */
433 case CC_NOOVmode: /* Condition Codes. */
434 return IS_ST_REGNO (regno);
436 case HImode: /* Long Long (64 bits). */
437 /* We need two registers to store long longs. Note that
438 it is much easier to constrain the first register
439 to start on an even boundary. */
440 return IS_INT_REGNO (regno)
441 && IS_INT_REGNO (regno + 1)
445 return 0; /* We don't support these modes. */
451 /* Return nonzero if REGNO1 can be renamed to REGNO2. */
453 c4x_hard_regno_rename_ok (regno1, regno2)
457 /* We can not copy call saved registers from mode QI into QF or from
459 if (IS_FLOAT_CALL_SAVED_REGNO (regno1) && IS_INT_CALL_SAVED_REGNO (regno2))
461 if (IS_INT_CALL_SAVED_REGNO (regno1) && IS_FLOAT_CALL_SAVED_REGNO (regno2))
463 /* We cannot copy from an extended (40 bit) register to a standard
464 (32 bit) register because we only set the condition codes for
465 extended registers. */
466 if (IS_EXT_REGNO (regno1) && ! IS_EXT_REGNO (regno2))
468 if (IS_EXT_REGNO (regno2) && ! IS_EXT_REGNO (regno1))
473 /* The TI C3x C compiler register argument runtime model uses 6 registers,
474 AR2, R2, R3, RC, RS, RE.
476 The first two floating point arguments (float, double, long double)
477 that are found scanning from left to right are assigned to R2 and R3.
479 The remaining integer (char, short, int, long) or pointer arguments
480 are assigned to the remaining registers in the order AR2, R2, R3,
481 RC, RS, RE when scanning left to right, except for the last named
482 argument prior to an ellipsis denoting variable number of
483 arguments. We don't have to worry about the latter condition since
484 function.c treats the last named argument as anonymous (unnamed).
486 All arguments that cannot be passed in registers are pushed onto
487 the stack in reverse order (right to left). GCC handles that for us.
489 c4x_init_cumulative_args() is called at the start, so we can parse
490 the args to see how many floating point arguments and how many
491 integer (or pointer) arguments there are. c4x_function_arg() is
492 then called (sometimes repeatedly) for each argument (parsed left
493 to right) to obtain the register to pass the argument in, or zero
494 if the argument is to be passed on the stack. Once the compiler is
495 happy, c4x_function_arg_advance() is called.
497 Don't use R0 to pass arguments in, we use 0 to indicate a stack
500 static const int c4x_int_reglist[3][6] =
502 {AR2_REGNO, R2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO},
503 {AR2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0},
504 {AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
507 static const int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
510 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
511 function whose data type is FNTYPE.
512 For a library call, FNTYPE is 0. */
515 c4x_init_cumulative_args (cum, fntype, libname)
516 CUMULATIVE_ARGS *cum; /* Argument info to initialize. */
517 tree fntype; /* Tree ptr for function decl. */
518 rtx libname; /* SYMBOL_REF of library name or 0. */
520 tree param, next_param;
522 cum->floats = cum->ints = 0;
529 fprintf (stderr, "\nc4x_init_cumulative_args (");
532 tree ret_type = TREE_TYPE (fntype);
534 fprintf (stderr, "fntype code = %s, ret code = %s",
535 tree_code_name[(int) TREE_CODE (fntype)],
536 tree_code_name[(int) TREE_CODE (ret_type)]);
539 fprintf (stderr, "no fntype");
542 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
545 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
547 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
548 param; param = next_param)
552 next_param = TREE_CHAIN (param);
554 type = TREE_VALUE (param);
555 if (type && type != void_type_node)
557 enum machine_mode mode;
559 /* If the last arg doesn't have void type then we have
560 variable arguments. */
564 if ((mode = TYPE_MODE (type)))
566 if (! MUST_PASS_IN_STACK (mode, type))
568 /* Look for float, double, or long double argument. */
569 if (mode == QFmode || mode == HFmode)
571 /* Look for integer, enumeral, boolean, char, or pointer
573 else if (mode == QImode || mode == Pmode)
582 fprintf (stderr, "%s%s, args = %d)\n",
583 cum->prototype ? ", prototype" : "",
584 cum->var ? ", variable args" : "",
589 /* Update the data in CUM to advance over an argument
590 of mode MODE and data type TYPE.
591 (TYPE is null for libcalls where that information may not be available.) */
594 c4x_function_arg_advance (cum, mode, type, named)
595 CUMULATIVE_ARGS *cum; /* Current arg information. */
596 enum machine_mode mode; /* Current arg mode. */
597 tree type; /* Type of the arg or 0 if lib support. */
598 int named; /* Whether or not the argument was named. */
601 fprintf (stderr, "c4x_function_adv(mode=%s, named=%d)\n\n",
602 GET_MODE_NAME (mode), named);
606 && ! MUST_PASS_IN_STACK (mode, type))
608 /* Look for float, double, or long double argument. */
609 if (mode == QFmode || mode == HFmode)
611 /* Look for integer, enumeral, boolean, char, or pointer argument. */
612 else if (mode == QImode || mode == Pmode)
615 else if (! TARGET_MEMPARM && ! type)
617 /* Handle libcall arguments. */
618 if (mode == QFmode || mode == HFmode)
620 else if (mode == QImode || mode == Pmode)
627 /* Define where to put the arguments to a function. Value is zero to
628 push the argument on the stack, or a hard register in which to
631 MODE is the argument's machine mode.
632 TYPE is the data type of the argument (as a tree).
633 This is null for libcalls where that information may
635 CUM is a variable of type CUMULATIVE_ARGS which gives info about
636 the preceding args and about the function being called.
637 NAMED is nonzero if this argument is a named parameter
638 (otherwise it is an extra parameter matching an ellipsis). */
641 c4x_function_arg (cum, mode, type, named)
642 CUMULATIVE_ARGS *cum; /* Current arg information. */
643 enum machine_mode mode; /* Current arg mode. */
644 tree type; /* Type of the arg or 0 if lib support. */
645 int named; /* != 0 for normal args, == 0 for ... args. */
647 int reg = 0; /* Default to passing argument on stack. */
651 /* We can handle at most 2 floats in R2, R3. */
652 cum->maxfloats = (cum->floats > 2) ? 2 : cum->floats;
654 /* We can handle at most 6 integers minus number of floats passed
656 cum->maxints = (cum->ints > 6 - cum->maxfloats) ?
657 6 - cum->maxfloats : cum->ints;
659 /* If there is no prototype, assume all the arguments are integers. */
660 if (! cum->prototype)
663 cum->ints = cum->floats = 0;
667 /* This marks the last argument. We don't need to pass this through
669 if (type == void_type_node)
675 && ! MUST_PASS_IN_STACK (mode, type))
677 /* Look for float, double, or long double argument. */
678 if (mode == QFmode || mode == HFmode)
680 if (cum->floats < cum->maxfloats)
681 reg = c4x_fp_reglist[cum->floats];
683 /* Look for integer, enumeral, boolean, char, or pointer argument. */
684 else if (mode == QImode || mode == Pmode)
686 if (cum->ints < cum->maxints)
687 reg = c4x_int_reglist[cum->maxfloats][cum->ints];
690 else if (! TARGET_MEMPARM && ! type)
692 /* We could use a different argument calling model for libcalls,
693 since we're only calling functions in libgcc. Thus we could
694 pass arguments for long longs in registers rather than on the
695 stack. In the meantime, use the odd TI format. We make the
696 assumption that we won't have more than two floating point
697 args, six integer args, and that all the arguments are of the
699 if (mode == QFmode || mode == HFmode)
700 reg = c4x_fp_reglist[cum->floats];
701 else if (mode == QImode || mode == Pmode)
702 reg = c4x_int_reglist[0][cum->ints];
707 fprintf (stderr, "c4x_function_arg(mode=%s, named=%d",
708 GET_MODE_NAME (mode), named);
710 fprintf (stderr, ", reg=%s", reg_names[reg]);
712 fprintf (stderr, ", stack");
713 fprintf (stderr, ")\n");
716 return gen_rtx_REG (mode, reg);
721 /* C[34]x arguments grow in weird ways (downwards) that the standard
722 varargs stuff can't handle.. */
724 c4x_va_arg (valist, type)
729 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
730 build_int_2 (int_size_in_bytes (type), 0));
731 TREE_SIDE_EFFECTS (t) = 1;
733 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
738 c4x_isr_reg_used_p (regno)
741 /* Don't save/restore FP or ST, we handle them separately. */
742 if (regno == FRAME_POINTER_REGNUM
743 || IS_ST_REGNO (regno))
746 /* We could be a little smarter abut saving/restoring DP.
747 We'll only save if for the big memory model or if
748 we're paranoid. ;-) */
749 if (IS_DP_REGNO (regno))
750 return ! TARGET_SMALL || TARGET_PARANOID;
752 /* Only save/restore regs in leaf function that are used. */
753 if (c4x_leaf_function)
754 return regs_ever_live[regno] && fixed_regs[regno] == 0;
756 /* Only save/restore regs that are used by the ISR and regs
757 that are likely to be used by functions the ISR calls
758 if they are not fixed. */
759 return IS_EXT_REGNO (regno)
760 || ((regs_ever_live[regno] || call_used_regs[regno])
761 && fixed_regs[regno] == 0);
766 c4x_leaf_function_p ()
768 /* A leaf function makes no calls, so we only need
769 to save/restore the registers we actually use.
770 For the global variable leaf_function to be set, we need
771 to define LEAF_REGISTERS and all that it entails.
772 Let's check ourselves... */
774 if (lookup_attribute ("leaf_pretend",
775 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
778 /* Use the leaf_pretend attribute at your own risk. This is a hack
779 to speed up ISRs that call a function infrequently where the
780 overhead of saving and restoring the additional registers is not
781 warranted. You must save and restore the additional registers
782 required by the called function. Caveat emptor. Here's enough
785 if (leaf_function_p ())
793 c4x_naked_function_p ()
797 type = TREE_TYPE (current_function_decl);
798 return lookup_attribute ("naked", TYPE_ATTRIBUTES (type)) != NULL;
803 c4x_interrupt_function_p ()
805 if (lookup_attribute ("interrupt",
806 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
809 /* Look for TI style c_intnn. */
810 return current_function_name[0] == 'c'
811 && current_function_name[1] == '_'
812 && current_function_name[2] == 'i'
813 && current_function_name[3] == 'n'
814 && current_function_name[4] == 't'
815 && ISDIGIT (current_function_name[5])
816 && ISDIGIT (current_function_name[6]);
820 c4x_expand_prologue ()
823 int size = get_frame_size ();
826 /* In functions where ar3 is not used but frame pointers are still
827 specified, frame pointers are not adjusted (if >= -O2) and this
828 is used so it won't needlessly push the frame pointer. */
831 /* For __naked__ function don't build a prologue. */
832 if (c4x_naked_function_p ())
837 /* For __interrupt__ function build specific prologue. */
838 if (c4x_interrupt_function_p ())
840 c4x_leaf_function = c4x_leaf_function_p ();
842 insn = emit_insn (gen_push_st ());
843 RTX_FRAME_RELATED_P (insn) = 1;
846 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
847 RTX_FRAME_RELATED_P (insn) = 1;
848 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
849 gen_rtx_REG (QImode, SP_REGNO)));
850 RTX_FRAME_RELATED_P (insn) = 1;
851 /* We require that an ISR uses fewer than 32768 words of
852 local variables, otherwise we have to go to lots of
853 effort to save a register, load it with the desired size,
854 adjust the stack pointer, and then restore the modified
855 register. Frankly, I think it is a poor ISR that
856 requires more than 32767 words of local temporary
859 error ("ISR %s requires %d words of local vars, max is 32767",
860 current_function_name, size);
862 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
863 gen_rtx_REG (QImode, SP_REGNO),
865 RTX_FRAME_RELATED_P (insn) = 1;
867 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
869 if (c4x_isr_reg_used_p (regno))
871 if (regno == DP_REGNO)
873 insn = emit_insn (gen_push_dp ());
874 RTX_FRAME_RELATED_P (insn) = 1;
878 insn = emit_insn (gen_pushqi (gen_rtx_REG (QImode, regno)));
879 RTX_FRAME_RELATED_P (insn) = 1;
880 if (IS_EXT_REGNO (regno))
882 insn = emit_insn (gen_pushqf
883 (gen_rtx_REG (QFmode, regno)));
884 RTX_FRAME_RELATED_P (insn) = 1;
889 /* We need to clear the repeat mode flag if the ISR is
890 going to use a RPTB instruction or uses the RC, RS, or RE
892 if (regs_ever_live[RC_REGNO]
893 || regs_ever_live[RS_REGNO]
894 || regs_ever_live[RE_REGNO])
896 insn = emit_insn (gen_andn_st (GEN_INT(~0x100)));
897 RTX_FRAME_RELATED_P (insn) = 1;
900 /* Reload DP reg if we are paranoid about some turkey
901 violating small memory model rules. */
902 if (TARGET_SMALL && TARGET_PARANOID)
904 insn = emit_insn (gen_set_ldp_prologue
905 (gen_rtx_REG (QImode, DP_REGNO),
906 gen_rtx_SYMBOL_REF (QImode, "data_sec")));
907 RTX_FRAME_RELATED_P (insn) = 1;
912 if (frame_pointer_needed)
915 || (current_function_args_size != 0)
918 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
919 RTX_FRAME_RELATED_P (insn) = 1;
920 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
921 gen_rtx_REG (QImode, SP_REGNO)));
922 RTX_FRAME_RELATED_P (insn) = 1;
927 /* Since ar3 is not used, we don't need to push it. */
933 /* If we use ar3, we need to push it. */
935 if ((size != 0) || (current_function_args_size != 0))
937 /* If we are omitting the frame pointer, we still have
938 to make space for it so the offsets are correct
939 unless we don't use anything on the stack at all. */
946 /* Local vars are too big, it will take multiple operations
950 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
951 GEN_INT(size >> 16)));
952 RTX_FRAME_RELATED_P (insn) = 1;
953 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R1_REGNO),
954 gen_rtx_REG (QImode, R1_REGNO),
956 RTX_FRAME_RELATED_P (insn) = 1;
960 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
961 GEN_INT(size & ~0xffff)));
962 RTX_FRAME_RELATED_P (insn) = 1;
964 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R1_REGNO),
965 gen_rtx_REG (QImode, R1_REGNO),
966 GEN_INT(size & 0xffff)));
967 RTX_FRAME_RELATED_P (insn) = 1;
968 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
969 gen_rtx_REG (QImode, SP_REGNO),
970 gen_rtx_REG (QImode, R1_REGNO)));
971 RTX_FRAME_RELATED_P (insn) = 1;
975 /* Local vars take up less than 32767 words, so we can directly
977 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
978 gen_rtx_REG (QImode, SP_REGNO),
980 RTX_FRAME_RELATED_P (insn) = 1;
983 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
985 if (regs_ever_live[regno] && ! call_used_regs[regno])
987 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
989 if (TARGET_PRESERVE_FLOAT)
991 insn = emit_insn (gen_pushqi
992 (gen_rtx_REG (QImode, regno)));
993 RTX_FRAME_RELATED_P (insn) = 1;
995 insn = emit_insn (gen_pushqf (gen_rtx_REG (QFmode, regno)));
996 RTX_FRAME_RELATED_P (insn) = 1;
998 else if ((! dont_push_ar3) || (regno != AR3_REGNO))
1000 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, regno)));
1001 RTX_FRAME_RELATED_P (insn) = 1;
1010 c4x_expand_epilogue()
1016 int size = get_frame_size ();
1018 /* For __naked__ function build no epilogue. */
1019 if (c4x_naked_function_p ())
1021 insn = emit_jump_insn (gen_return_from_epilogue ());
1022 RTX_FRAME_RELATED_P (insn) = 1;
1026 /* For __interrupt__ function build specific epilogue. */
1027 if (c4x_interrupt_function_p ())
1029 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
1031 if (! c4x_isr_reg_used_p (regno))
1033 if (regno == DP_REGNO)
1035 insn = emit_insn (gen_pop_dp ());
1036 RTX_FRAME_RELATED_P (insn) = 1;
1040 /* We have to use unspec because the compiler will delete insns
1041 that are not call-saved. */
1042 if (IS_EXT_REGNO (regno))
1044 insn = emit_insn (gen_popqf_unspec
1045 (gen_rtx_REG (QFmode, regno)));
1046 RTX_FRAME_RELATED_P (insn) = 1;
1048 insn = emit_insn (gen_popqi_unspec (gen_rtx_REG (QImode, regno)));
1049 RTX_FRAME_RELATED_P (insn) = 1;
1054 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1055 gen_rtx_REG (QImode, SP_REGNO),
1057 RTX_FRAME_RELATED_P (insn) = 1;
1058 insn = emit_insn (gen_popqi
1059 (gen_rtx_REG (QImode, AR3_REGNO)));
1060 RTX_FRAME_RELATED_P (insn) = 1;
1062 insn = emit_insn (gen_pop_st ());
1063 RTX_FRAME_RELATED_P (insn) = 1;
1064 insn = emit_jump_insn (gen_return_from_interrupt_epilogue ());
1065 RTX_FRAME_RELATED_P (insn) = 1;
1069 if (frame_pointer_needed)
1072 || (current_function_args_size != 0)
1076 (gen_movqi (gen_rtx_REG (QImode, R2_REGNO),
1077 gen_rtx_MEM (QImode,
1079 (QImode, gen_rtx_REG (QImode,
1082 RTX_FRAME_RELATED_P (insn) = 1;
1084 /* We already have the return value and the fp,
1085 so we need to add those to the stack. */
1092 /* Since ar3 is not used for anything, we don't need to
1099 dont_pop_ar3 = 0; /* If we use ar3, we need to pop it. */
1100 if (size || current_function_args_size)
1102 /* If we are ommitting the frame pointer, we still have
1103 to make space for it so the offsets are correct
1104 unless we don't use anything on the stack at all. */
1109 /* Now restore the saved registers, putting in the delayed branch
1111 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1113 if (regs_ever_live[regno] && ! call_used_regs[regno])
1115 if (regno == AR3_REGNO && dont_pop_ar3)
1118 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
1120 insn = emit_insn (gen_popqf_unspec
1121 (gen_rtx_REG (QFmode, regno)));
1122 RTX_FRAME_RELATED_P (insn) = 1;
1123 if (TARGET_PRESERVE_FLOAT)
1125 insn = emit_insn (gen_popqi_unspec
1126 (gen_rtx_REG (QImode, regno)));
1127 RTX_FRAME_RELATED_P (insn) = 1;
1132 insn = emit_insn (gen_popqi (gen_rtx_REG (QImode, regno)));
1133 RTX_FRAME_RELATED_P (insn) = 1;
1138 if (frame_pointer_needed)
1141 || (current_function_args_size != 0)
1144 /* Restore the old FP. */
1147 (gen_rtx_REG (QImode, AR3_REGNO),
1148 gen_rtx_MEM (QImode, gen_rtx_REG (QImode, AR3_REGNO))));
1150 RTX_FRAME_RELATED_P (insn) = 1;
1156 /* Local vars are too big, it will take multiple operations
1160 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1161 GEN_INT(size >> 16)));
1162 RTX_FRAME_RELATED_P (insn) = 1;
1163 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R3_REGNO),
1164 gen_rtx_REG (QImode, R3_REGNO),
1166 RTX_FRAME_RELATED_P (insn) = 1;
1170 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1171 GEN_INT(size & ~0xffff)));
1172 RTX_FRAME_RELATED_P (insn) = 1;
1174 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R3_REGNO),
1175 gen_rtx_REG (QImode, R3_REGNO),
1176 GEN_INT(size & 0xffff)));
1177 RTX_FRAME_RELATED_P (insn) = 1;
1178 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1179 gen_rtx_REG (QImode, SP_REGNO),
1180 gen_rtx_REG (QImode, R3_REGNO)));
1181 RTX_FRAME_RELATED_P (insn) = 1;
1185 /* Local vars take up less than 32768 words, so we can directly
1186 subtract the number. */
1187 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1188 gen_rtx_REG (QImode, SP_REGNO),
1190 RTX_FRAME_RELATED_P (insn) = 1;
1195 insn = emit_jump_insn (gen_return_indirect_internal
1196 (gen_rtx_REG (QImode, R2_REGNO)));
1197 RTX_FRAME_RELATED_P (insn) = 1;
1201 insn = emit_jump_insn (gen_return_from_epilogue ());
1202 RTX_FRAME_RELATED_P (insn) = 1;
1209 c4x_null_epilogue_p ()
1213 if (reload_completed
1214 && ! c4x_naked_function_p ()
1215 && ! c4x_interrupt_function_p ()
1216 && ! current_function_calls_alloca
1217 && ! current_function_args_size
1219 && ! get_frame_size ())
1221 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1222 if (regs_ever_live[regno] && ! call_used_regs[regno]
1223 && (regno != AR3_REGNO))
1232 c4x_emit_move_sequence (operands, mode)
1234 enum machine_mode mode;
1236 rtx op0 = operands[0];
1237 rtx op1 = operands[1];
1239 if (! reload_in_progress
1242 && ! (stik_const_operand (op1, mode) && ! push_operand (op0, mode)))
1243 op1 = force_reg (mode, op1);
1245 if (GET_CODE (op1) == LO_SUM
1246 && GET_MODE (op1) == Pmode
1247 && dp_reg_operand (XEXP (op1, 0), mode))
1249 /* expand_increment will sometimes create a LO_SUM immediate
1251 op1 = XEXP (op1, 1);
1253 else if (symbolic_address_operand (op1, mode))
1255 if (TARGET_LOAD_ADDRESS)
1257 /* Alias analysis seems to do a better job if we force
1258 constant addresses to memory after reload. */
1259 emit_insn (gen_load_immed_address (op0, op1));
1264 /* Stick symbol or label address into the constant pool. */
1265 op1 = force_const_mem (Pmode, op1);
1268 else if (mode == HFmode && CONSTANT_P (op1) && ! LEGITIMATE_CONSTANT_P (op1))
1270 /* We could be a lot smarter about loading some of these
1272 op1 = force_const_mem (mode, op1);
1275 /* Convert (MEM (SYMREF)) to a (MEM (LO_SUM (REG) (SYMREF)))
1276 and emit associated (HIGH (SYMREF)) if large memory model.
1277 c4x_legitimize_address could be used to do this,
1278 perhaps by calling validize_address. */
1279 if (TARGET_EXPOSE_LDP
1280 && ! (reload_in_progress || reload_completed)
1281 && GET_CODE (op1) == MEM
1282 && symbolic_address_operand (XEXP (op1, 0), Pmode))
1284 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1286 emit_insn (gen_set_ldp (dp_reg, XEXP (op1, 0)));
1287 op1 = change_address (op1, mode,
1288 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op1, 0)));
1291 if (TARGET_EXPOSE_LDP
1292 && ! (reload_in_progress || reload_completed)
1293 && GET_CODE (op0) == MEM
1294 && symbolic_address_operand (XEXP (op0, 0), Pmode))
1296 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1298 emit_insn (gen_set_ldp (dp_reg, XEXP (op0, 0)));
1299 op0 = change_address (op0, mode,
1300 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op0, 0)));
1303 if (GET_CODE (op0) == SUBREG
1304 && mixed_subreg_operand (op0, mode))
1306 /* We should only generate these mixed mode patterns
1307 during RTL generation. If we need do it later on
1308 then we'll have to emit patterns that won't clobber CC. */
1309 if (reload_in_progress || reload_completed)
1311 if (GET_MODE (SUBREG_REG (op0)) == QImode)
1312 op0 = SUBREG_REG (op0);
1313 else if (GET_MODE (SUBREG_REG (op0)) == HImode)
1315 op0 = copy_rtx (op0);
1316 PUT_MODE (op0, QImode);
1322 emit_insn (gen_storeqf_int_clobber (op0, op1));
1328 if (GET_CODE (op1) == SUBREG
1329 && mixed_subreg_operand (op1, mode))
1331 /* We should only generate these mixed mode patterns
1332 during RTL generation. If we need do it later on
1333 then we'll have to emit patterns that won't clobber CC. */
1334 if (reload_in_progress || reload_completed)
1336 if (GET_MODE (SUBREG_REG (op1)) == QImode)
1337 op1 = SUBREG_REG (op1);
1338 else if (GET_MODE (SUBREG_REG (op1)) == HImode)
1340 op1 = copy_rtx (op1);
1341 PUT_MODE (op1, QImode);
1347 emit_insn (gen_loadqf_int_clobber (op0, op1));
1354 && reg_operand (op0, mode)
1355 && const_int_operand (op1, mode)
1356 && ! IS_INT16_CONST (INTVAL (op1))
1357 && ! IS_HIGH_CONST (INTVAL (op1)))
1359 emit_insn (gen_loadqi_big_constant (op0, op1));
1364 && reg_operand (op0, mode)
1365 && const_int_operand (op1, mode))
1367 emit_insn (gen_loadhi_big_constant (op0, op1));
1371 /* Adjust operands in case we have modified them. */
1375 /* Emit normal pattern. */
1381 c4x_emit_libcall (libcall, code, dmode, smode, noperands, operands)
1384 enum machine_mode dmode;
1385 enum machine_mode smode;
1397 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 1,
1398 operands[1], smode);
1399 equiv = gen_rtx (code, dmode, operands[1]);
1403 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 2,
1404 operands[1], smode, operands[2], smode);
1405 equiv = gen_rtx (code, dmode, operands[1], operands[2]);
1412 insns = get_insns ();
1414 emit_libcall_block (insns, operands[0], ret, equiv);
1419 c4x_emit_libcall3 (libcall, code, mode, operands)
1422 enum machine_mode mode;
1425 c4x_emit_libcall (libcall, code, mode, mode, 3, operands);
1430 c4x_emit_libcall_mulhi (libcall, code, mode, operands)
1433 enum machine_mode mode;
1441 ret = emit_library_call_value (libcall, NULL_RTX, 1, mode, 2,
1442 operands[1], mode, operands[2], mode);
1443 equiv = gen_rtx_TRUNCATE (mode,
1444 gen_rtx_LSHIFTRT (HImode,
1445 gen_rtx_MULT (HImode,
1446 gen_rtx (code, HImode, operands[1]),
1447 gen_rtx (code, HImode, operands[2])),
1449 insns = get_insns ();
1451 emit_libcall_block (insns, operands[0], ret, equiv);
1455 /* Set the SYMBOL_REF_FLAG for a function decl. However, wo do not
1456 yet use this info. */
1459 c4x_encode_section_info (decl, first)
1461 int first ATTRIBUTE_UNUSED;
1463 if (TREE_CODE (decl) == FUNCTION_DECL)
1464 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
1469 c4x_check_legit_addr (mode, addr, strict)
1470 enum machine_mode mode;
1474 rtx base = NULL_RTX; /* Base register (AR0-AR7). */
1475 rtx indx = NULL_RTX; /* Index register (IR0,IR1). */
1476 rtx disp = NULL_RTX; /* Displacement. */
1479 code = GET_CODE (addr);
1482 /* Register indirect with auto increment/decrement. We don't
1483 allow SP here---push_operand should recognize an operand
1484 being pushed on the stack. */
1489 if (mode != QImode && mode != QFmode)
1493 base = XEXP (addr, 0);
1501 rtx op0 = XEXP (addr, 0);
1502 rtx op1 = XEXP (addr, 1);
1504 if (mode != QImode && mode != QFmode)
1508 || (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS))
1510 base = XEXP (op1, 0);
1513 if (REG_P (XEXP (op1, 1)))
1514 indx = XEXP (op1, 1);
1516 disp = XEXP (op1, 1);
1520 /* Register indirect. */
1525 /* Register indirect with displacement or index. */
1528 rtx op0 = XEXP (addr, 0);
1529 rtx op1 = XEXP (addr, 1);
1530 enum rtx_code code0 = GET_CODE (op0);
1537 base = op0; /* Base + index. */
1539 if (IS_INDEX_REG (base) || IS_ADDR_REG (indx))
1547 base = op0; /* Base + displacement. */
1558 /* Direct addressing with DP register. */
1561 rtx op0 = XEXP (addr, 0);
1562 rtx op1 = XEXP (addr, 1);
1564 /* HImode and HFmode direct memory references aren't truly
1565 offsettable (consider case at end of data page). We
1566 probably get better code by loading a pointer and using an
1567 indirect memory reference. */
1568 if (mode == HImode || mode == HFmode)
1571 if (!REG_P (op0) || REGNO (op0) != DP_REGNO)
1574 if ((GET_CODE (op1) == SYMBOL_REF || GET_CODE (op1) == LABEL_REF))
1577 if (GET_CODE (op1) == CONST)
1583 /* Direct addressing with some work for the assembler... */
1585 /* Direct addressing. */
1588 if (! TARGET_EXPOSE_LDP && ! strict && mode != HFmode && mode != HImode)
1590 /* These need to be converted to a LO_SUM (...).
1591 LEGITIMIZE_RELOAD_ADDRESS will do this during reload. */
1594 /* Do not allow direct memory access to absolute addresses.
1595 This is more pain than it's worth, especially for the
1596 small memory model where we can't guarantee that
1597 this address is within the data page---we don't want
1598 to modify the DP register in the small memory model,
1599 even temporarily, since an interrupt can sneak in.... */
1603 /* Indirect indirect addressing. */
1608 fatal_insn ("using CONST_DOUBLE for address", addr);
1614 /* Validate the base register. */
1617 /* Check that the address is offsettable for HImode and HFmode. */
1618 if (indx && (mode == HImode || mode == HFmode))
1621 /* Handle DP based stuff. */
1622 if (REGNO (base) == DP_REGNO)
1624 if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
1626 else if (! strict && ! IS_ADDR_OR_PSEUDO_REG (base))
1630 /* Now validate the index register. */
1633 if (GET_CODE (indx) != REG)
1635 if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
1637 else if (! strict && ! IS_INDEX_OR_PSEUDO_REG (indx))
1641 /* Validate displacement. */
1644 if (GET_CODE (disp) != CONST_INT)
1646 if (mode == HImode || mode == HFmode)
1648 /* The offset displacement must be legitimate. */
1649 if (! IS_DISP8_OFF_CONST (INTVAL (disp)))
1654 if (! IS_DISP8_CONST (INTVAL (disp)))
1657 /* Can't add an index with a disp. */
1666 c4x_legitimize_address (orig, mode)
1667 rtx orig ATTRIBUTE_UNUSED;
1668 enum machine_mode mode ATTRIBUTE_UNUSED;
1670 if (GET_CODE (orig) == SYMBOL_REF
1671 || GET_CODE (orig) == LABEL_REF)
1673 if (mode == HImode || mode == HFmode)
1675 /* We need to force the address into
1676 a register so that it is offsettable. */
1677 rtx addr_reg = gen_reg_rtx (Pmode);
1678 emit_move_insn (addr_reg, orig);
1683 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1686 emit_insn (gen_set_ldp (dp_reg, orig));
1688 return gen_rtx_LO_SUM (Pmode, dp_reg, orig);
1696 /* Provide the costs of an addressing mode that contains ADDR.
1697 If ADDR is not a valid address, its cost is irrelevant.
1698 This is used in cse and loop optimisation to determine
1699 if it is worthwhile storing a common address into a register.
1700 Unfortunately, the C4x address cost depends on other operands. */
1703 c4x_address_cost (addr)
1706 switch (GET_CODE (addr))
1717 /* These shouldn't be directly generated. */
1725 rtx op1 = XEXP (addr, 1);
1727 if (GET_CODE (op1) == LABEL_REF || GET_CODE (op1) == SYMBOL_REF)
1728 return TARGET_SMALL ? 3 : 4;
1730 if (GET_CODE (op1) == CONST)
1732 rtx offset = const0_rtx;
1734 op1 = eliminate_constant_term (op1, &offset);
1736 /* ??? These costs need rethinking... */
1737 if (GET_CODE (op1) == LABEL_REF)
1740 if (GET_CODE (op1) != SYMBOL_REF)
1743 if (INTVAL (offset) == 0)
1748 fatal_insn ("c4x_address_cost: Invalid addressing mode", addr);
1754 register rtx op0 = XEXP (addr, 0);
1755 register rtx op1 = XEXP (addr, 1);
1757 if (GET_CODE (op0) != REG)
1760 switch (GET_CODE (op1))
1766 /* This cost for REG+REG must be greater than the cost
1767 for REG if we want autoincrement addressing modes. */
1771 /* The following tries to improve GIV combination
1772 in strength reduce but appears not to help. */
1773 if (TARGET_DEVEL && IS_UINT5_CONST (INTVAL (op1)))
1776 if (IS_DISP1_CONST (INTVAL (op1)))
1779 if (! TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
1794 c4x_gen_compare_reg (code, x, y)
1798 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1801 if (mode == CC_NOOVmode
1802 && (code == LE || code == GE || code == LT || code == GT))
1805 cc_reg = gen_rtx_REG (mode, ST_REGNO);
1806 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1807 gen_rtx_COMPARE (mode, x, y)));
1812 c4x_output_cbranch (form, seq)
1821 static char str[100];
1825 delay = XVECEXP (final_sequence, 0, 1);
1826 delayed = ! INSN_ANNULLED_BRANCH_P (seq);
1827 annultrue = INSN_ANNULLED_BRANCH_P (seq) && ! INSN_FROM_TARGET_P (delay);
1828 annulfalse = INSN_ANNULLED_BRANCH_P (seq) && INSN_FROM_TARGET_P (delay);
1831 cp = &str [strlen (str)];
1856 c4x_print_operand (file, op, letter)
1857 FILE *file; /* File to write to. */
1858 rtx op; /* Operand to print. */
1859 int letter; /* %<letter> or 0. */
1866 case '#': /* Delayed. */
1868 fprintf (file, "d");
1872 code = GET_CODE (op);
1875 case 'A': /* Direct address. */
1876 if (code == CONST_INT || code == SYMBOL_REF || code == CONST)
1877 fprintf (file, "@");
1880 case 'H': /* Sethi. */
1881 output_addr_const (file, op);
1884 case 'I': /* Reversed condition. */
1885 code = reverse_condition (code);
1888 case 'L': /* Log 2 of constant. */
1889 if (code != CONST_INT)
1890 fatal_insn ("c4x_print_operand: %%L inconsistency", op);
1891 fprintf (file, "%d", exact_log2 (INTVAL (op)));
1894 case 'N': /* Ones complement of small constant. */
1895 if (code != CONST_INT)
1896 fatal_insn ("c4x_print_operand: %%N inconsistency", op);
1897 fprintf (file, "%d", ~INTVAL (op));
1900 case 'K': /* Generate ldp(k) if direct address. */
1903 && GET_CODE (XEXP (op, 0)) == LO_SUM
1904 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
1905 && REGNO (XEXP (XEXP (op, 0), 0)) == DP_REGNO)
1907 op1 = XEXP (XEXP (op, 0), 1);
1908 if (GET_CODE(op1) == CONST_INT || GET_CODE(op1) == SYMBOL_REF)
1910 fprintf (file, "\t%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1911 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1912 fprintf (file, "\n");
1917 case 'M': /* Generate ldp(k) if direct address. */
1918 if (! TARGET_SMALL /* Only used in asm statements. */
1920 && (GET_CODE (XEXP (op, 0)) == CONST
1921 || GET_CODE (XEXP (op, 0)) == SYMBOL_REF))
1923 fprintf (file, "%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1924 output_address (XEXP (op, 0));
1925 fprintf (file, "\n\t");
1929 case 'O': /* Offset address. */
1930 if (code == MEM && c4x_autoinc_operand (op, Pmode))
1932 else if (code == MEM)
1933 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1934 else if (code == REG)
1935 fprintf (file, "%s", reg_names[REGNO (op) + 1]);
1937 fatal_insn ("c4x_print_operand: %%O inconsistency", op);
1940 case 'C': /* Call. */
1943 case 'U': /* Call/callu. */
1944 if (code != SYMBOL_REF)
1945 fprintf (file, "u");
1955 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
1957 fprintf (file, "%s", float_reg_names[REGNO (op)]);
1959 fprintf (file, "%s", reg_names[REGNO (op)]);
1963 output_address (XEXP (op, 0));
1970 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (op),
1971 sizeof (str), 0, 1);
1972 fprintf (file, "%s", str);
1977 fprintf (file, "%d", INTVAL (op));
1981 fprintf (file, "ne");
1985 fprintf (file, "eq");
1989 fprintf (file, "ge");
1993 fprintf (file, "gt");
1997 fprintf (file, "le");
2001 fprintf (file, "lt");
2005 fprintf (file, "hs");
2009 fprintf (file, "hi");
2013 fprintf (file, "ls");
2017 fprintf (file, "lo");
2021 output_addr_const (file, op);
2025 output_addr_const (file, XEXP (op, 0));
2032 fatal_insn ("c4x_print_operand: Bad operand case", op);
2039 c4x_print_operand_address (file, addr)
2043 switch (GET_CODE (addr))
2046 fprintf (file, "*%s", reg_names[REGNO (addr)]);
2050 fprintf (file, "*--%s", reg_names[REGNO (XEXP (addr, 0))]);
2054 fprintf (file, "*%s++", reg_names[REGNO (XEXP (addr, 0))]);
2059 rtx op0 = XEXP (XEXP (addr, 1), 0);
2060 rtx op1 = XEXP (XEXP (addr, 1), 1);
2062 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2063 fprintf (file, "*%s++(%s)", reg_names[REGNO (op0)],
2064 reg_names[REGNO (op1)]);
2065 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2066 fprintf (file, "*%s++(%d)", reg_names[REGNO (op0)],
2068 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2069 fprintf (file, "*%s--(%d)", reg_names[REGNO (op0)],
2071 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2072 fprintf (file, "*%s--(%s)", reg_names[REGNO (op0)],
2073 reg_names[REGNO (op1)]);
2075 fatal_insn ("c4x_print_operand_address: Bad post_modify", addr);
2081 rtx op0 = XEXP (XEXP (addr, 1), 0);
2082 rtx op1 = XEXP (XEXP (addr, 1), 1);
2084 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2085 fprintf (file, "*++%s(%s)", reg_names[REGNO (op0)],
2086 reg_names[REGNO (op1)]);
2087 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2088 fprintf (file, "*++%s(%d)", reg_names[REGNO (op0)],
2090 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2091 fprintf (file, "*--%s(%d)", reg_names[REGNO (op0)],
2093 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2094 fprintf (file, "*--%s(%s)", reg_names[REGNO (op0)],
2095 reg_names[REGNO (op1)]);
2097 fatal_insn ("c4x_print_operand_address: Bad pre_modify", addr);
2102 fprintf (file, "*++%s", reg_names[REGNO (XEXP (addr, 0))]);
2106 fprintf (file, "*%s--", reg_names[REGNO (XEXP (addr, 0))]);
2109 case PLUS: /* Indirect with displacement. */
2111 rtx op0 = XEXP (addr, 0);
2112 rtx op1 = XEXP (addr, 1);
2118 if (IS_INDEX_REG (op0))
2120 fprintf (file, "*+%s(%s)",
2121 reg_names[REGNO (op1)],
2122 reg_names[REGNO (op0)]); /* Index + base. */
2126 fprintf (file, "*+%s(%s)",
2127 reg_names[REGNO (op0)],
2128 reg_names[REGNO (op1)]); /* Base + index. */
2131 else if (INTVAL (op1) < 0)
2133 fprintf (file, "*-%s(%d)",
2134 reg_names[REGNO (op0)],
2135 -INTVAL (op1)); /* Base - displacement. */
2139 fprintf (file, "*+%s(%d)",
2140 reg_names[REGNO (op0)],
2141 INTVAL (op1)); /* Base + displacement. */
2145 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2151 rtx op0 = XEXP (addr, 0);
2152 rtx op1 = XEXP (addr, 1);
2154 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
2155 c4x_print_operand_address (file, op1);
2157 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2164 fprintf (file, "@");
2165 output_addr_const (file, addr);
2168 /* We shouldn't access CONST_INT addresses. */
2172 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2178 /* Return nonzero if the floating point operand will fit
2179 in the immediate field. */
2182 c4x_immed_float_p (op)
2189 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2190 if (GET_MODE (op) == HFmode)
2191 REAL_VALUE_TO_TARGET_DOUBLE (r, convval);
2194 REAL_VALUE_TO_TARGET_SINGLE (r, convval[0]);
2198 /* Sign extend exponent. */
2199 exponent = (((convval[0] >> 24) & 0xff) ^ 0x80) - 0x80;
2200 if (exponent == -128)
2202 if ((convval[0] & 0x00000fff) != 0 || convval[1] != 0)
2203 return 0; /* Precision doesn't fit. */
2204 return (exponent <= 7) /* Positive exp. */
2205 && (exponent >= -7); /* Negative exp. */
2209 /* The last instruction in a repeat block cannot be a Bcond, DBcound,
2210 CALL, CALLCond, TRAPcond, RETIcond, RETScond, IDLE, RPTB or RPTS.
2212 None of the last four instructions from the bottom of the block can
2213 be a BcondD, BRD, DBcondD, RPTBD, LAJ, LAJcond, LATcond, BcondAF,
2214 BcondAT or RETIcondD.
2216 This routine scans the four previous insns for a jump insn, and if
2217 one is found, returns 1 so that we bung in a nop instruction.
2218 This simple minded strategy will add a nop, when it may not
2219 be required. Say when there is a JUMP_INSN near the end of the
2220 block that doesn't get converted into a delayed branch.
2222 Note that we cannot have a call insn, since we don't generate
2223 repeat loops with calls in them (although I suppose we could, but
2224 there's no benefit.)
2226 !!! FIXME. The rptb_top insn may be sucked into a SEQUENCE. */
2229 c4x_rptb_nop_p (insn)
2235 /* Extract the start label from the jump pattern (rptb_end). */
2236 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2238 /* If there is a label at the end of the loop we must insert
2241 insn = previous_insn (insn);
2242 } while (GET_CODE (insn) == NOTE
2243 || GET_CODE (insn) == USE
2244 || GET_CODE (insn) == CLOBBER);
2245 if (GET_CODE (insn) == CODE_LABEL)
2248 for (i = 0; i < 4; i++)
2250 /* Search back for prev non-note and non-label insn. */
2251 while (GET_CODE (insn) == NOTE || GET_CODE (insn) == CODE_LABEL
2252 || GET_CODE (insn) == USE || GET_CODE (insn) == CLOBBER)
2254 if (insn == start_label)
2257 insn = previous_insn (insn);
2260 /* If we have a jump instruction we should insert a NOP. If we
2261 hit repeat block top we should only insert a NOP if the loop
2263 if (GET_CODE (insn) == JUMP_INSN)
2265 insn = previous_insn (insn);
2271 /* The C4x looping instruction needs to be emitted at the top of the
2272 loop. Emitting the true RTL for a looping instruction at the top of
2273 the loop can cause problems with flow analysis. So instead, a dummy
2274 doloop insn is emitted at the end of the loop. This routine checks
2275 for the presence of this doloop insn and then searches back to the
2276 top of the loop, where it inserts the true looping insn (provided
2277 there are no instructions in the loop which would cause problems).
2278 Any additional labels can be emitted at this point. In addition, if
2279 the desired loop count register was not allocated, this routine does
2282 Before we can create a repeat block looping instruction we have to
2283 verify that there are no jumps outside the loop and no jumps outside
2284 the loop go into this loop. This can happen in the basic blocks reorder
2285 pass. The C4x cpu can not handle this. */
2288 c4x_label_ref_used_p (x, code_label)
2298 code = GET_CODE (x);
2299 if (code == LABEL_REF)
2300 return INSN_UID (XEXP (x,0)) == INSN_UID (code_label);
2302 fmt = GET_RTX_FORMAT (code);
2303 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2307 if (c4x_label_ref_used_p (XEXP (x, i), code_label))
2310 else if (fmt[i] == 'E')
2311 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2312 if (c4x_label_ref_used_p (XVECEXP (x, i, j), code_label))
2320 c4x_rptb_valid_p (insn, start_label)
2321 rtx insn, start_label;
2327 /* Find the start label. */
2328 for (; insn; insn = PREV_INSN (insn))
2329 if (insn == start_label)
2332 /* Note found then we can not use a rptb or rpts. The label was
2333 probably moved by the basic block reorder pass. */
2338 /* If any jump jumps inside this block then we must fail. */
2339 for (insn = PREV_INSN (start); insn; insn = PREV_INSN (insn))
2341 if (GET_CODE (insn) == CODE_LABEL)
2343 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2344 if (GET_CODE (tmp) == JUMP_INSN
2345 && c4x_label_ref_used_p (tmp, insn))
2349 for (insn = NEXT_INSN (end); insn; insn = NEXT_INSN (insn))
2351 if (GET_CODE (insn) == CODE_LABEL)
2353 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2354 if (GET_CODE (tmp) == JUMP_INSN
2355 && c4x_label_ref_used_p (tmp, insn))
2359 /* If any jump jumps outside this block then we must fail. */
2360 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
2362 if (GET_CODE (insn) == CODE_LABEL)
2364 for (tmp = NEXT_INSN (end); tmp; tmp = NEXT_INSN(tmp))
2365 if (GET_CODE (tmp) == JUMP_INSN
2366 && c4x_label_ref_used_p (tmp, insn))
2368 for (tmp = PREV_INSN (start); tmp; tmp = PREV_INSN(tmp))
2369 if (GET_CODE (tmp) == JUMP_INSN
2370 && c4x_label_ref_used_p (tmp, insn))
2375 /* All checks OK. */
2381 c4x_rptb_insert (insn)
2386 rtx new_start_label;
2389 /* If the count register has not been allocated to RC, say if
2390 there is a movstr pattern in the loop, then do not insert a
2391 RPTB instruction. Instead we emit a decrement and branch
2392 at the end of the loop. */
2393 count_reg = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0), 0);
2394 if (REGNO (count_reg) != RC_REGNO)
2397 /* Extract the start label from the jump pattern (rptb_end). */
2398 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2400 if (! c4x_rptb_valid_p (insn, start_label))
2402 /* We can not use the rptb insn. Replace it so reorg can use
2403 the delay slots of the jump insn. */
2404 emit_insn_before (gen_addqi3 (count_reg, count_reg, GEN_INT (-1)), insn);
2405 emit_insn_before (gen_cmpqi (count_reg, GEN_INT (0)), insn);
2406 emit_insn_before (gen_bge (start_label), insn);
2407 LABEL_NUSES (start_label)++;
2412 end_label = gen_label_rtx ();
2413 LABEL_NUSES (end_label)++;
2414 emit_label_after (end_label, insn);
2416 new_start_label = gen_label_rtx ();
2417 LABEL_NUSES (new_start_label)++;
2419 for (; insn; insn = PREV_INSN (insn))
2421 if (insn == start_label)
2423 if (GET_CODE (insn) == JUMP_INSN &&
2424 JUMP_LABEL (insn) == start_label)
2425 redirect_jump (insn, new_start_label, 0);
2428 fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
2430 emit_label_after (new_start_label, insn);
2432 if (TARGET_RPTS && c4x_rptb_rpts_p (PREV_INSN (insn), 0))
2433 emit_insn_after (gen_rpts_top (new_start_label, end_label), insn);
2435 emit_insn_after (gen_rptb_top (new_start_label, end_label), insn);
2436 if (LABEL_NUSES (start_label) == 0)
2437 delete_insn (start_label);
2441 /* This function is a C4x special called immediately before delayed
2442 branch scheduling. We fix up RTPB style loops that didn't get RC
2443 allocated as the loop counter. */
2446 c4x_process_after_reload (first)
2451 for (insn = first; insn; insn = NEXT_INSN (insn))
2453 /* Look for insn. */
2456 int insn_code_number;
2459 insn_code_number = recog_memoized (insn);
2461 if (insn_code_number < 0)
2464 /* Insert the RTX for RPTB at the top of the loop
2465 and a label at the end of the loop. */
2466 if (insn_code_number == CODE_FOR_rptb_end)
2467 c4x_rptb_insert(insn);
2469 /* We need to split the insn here. Otherwise the calls to
2470 force_const_mem will not work for load_immed_address. */
2473 /* Don't split the insn if it has been deleted. */
2474 if (! INSN_DELETED_P (old))
2475 insn = try_split (PATTERN(old), old, 1);
2477 /* When not optimizing, the old insn will be still left around
2478 with only the 'deleted' bit set. Transform it into a note
2479 to avoid confusion of subsequent processing. */
2480 if (INSN_DELETED_P (old))
2482 PUT_CODE (old, NOTE);
2483 NOTE_LINE_NUMBER (old) = NOTE_INSN_DELETED;
2484 NOTE_SOURCE_FILE (old) = 0;
2495 return REG_P (op) && IS_ADDR_OR_PSEUDO_REG (op);
2503 return REG_P (op) && IS_INDEX_OR_PSEUDO_REG (op);
2508 c4x_immed_int_constant (op)
2511 if (GET_CODE (op) != CONST_INT)
2514 return GET_MODE (op) == VOIDmode
2515 || GET_MODE_CLASS (op) == MODE_INT
2516 || GET_MODE_CLASS (op) == MODE_PARTIAL_INT;
2521 c4x_immed_float_constant (op)
2524 if (GET_CODE (op) != CONST_DOUBLE)
2527 /* Do not check if the CONST_DOUBLE is in memory. If there is a MEM
2528 present this only means that a MEM rtx has been generated. It does
2529 not mean the rtx is really in memory. */
2531 return GET_MODE (op) == QFmode || GET_MODE (op) == HFmode;
2536 c4x_shiftable_constant (op)
2541 int val = INTVAL (op);
2543 for (i = 0; i < 16; i++)
2548 mask = ((0xffff >> i) << 16) | 0xffff;
2549 if (IS_INT16_CONST (val & (1 << 31) ? (val >> i) | ~mask
2550 : (val >> i) & mask))
2560 return c4x_immed_float_constant (op) && c4x_immed_float_p (op);
2568 return c4x_immed_int_constant (op) && IS_INT16_CONST (INTVAL (op));
2578 return c4x_immed_int_constant (op) && IS_INT8_CONST (INTVAL (op));
2586 if (TARGET_C3X || ! c4x_immed_int_constant (op))
2588 return IS_INT5_CONST (INTVAL (op));
2596 return c4x_immed_int_constant (op) && IS_UINT16_CONST (INTVAL (op));
2604 return c4x_immed_int_constant (op) && IS_NOT_UINT16_CONST (INTVAL (op));
2612 return c4x_immed_int_constant (op) && IS_HIGH_CONST (INTVAL (op));
2616 /* The constraints do not have to check the register class,
2617 except when needed to discriminate between the constraints.
2618 The operand has been checked by the predicates to be valid. */
2620 /* ARx + 9-bit signed const or IRn
2621 *ARx, *+ARx(n), *-ARx(n), *+ARx(IRn), *-Arx(IRn) for -256 < n < 256
2622 We don't include the pre/post inc/dec forms here since
2623 they are handled by the <> constraints. */
2626 c4x_Q_constraint (op)
2629 enum machine_mode mode = GET_MODE (op);
2631 if (GET_CODE (op) != MEM)
2634 switch (GET_CODE (op))
2641 rtx op0 = XEXP (op, 0);
2642 rtx op1 = XEXP (op, 1);
2650 if (GET_CODE (op1) != CONST_INT)
2653 /* HImode and HFmode must be offsettable. */
2654 if (mode == HImode || mode == HFmode)
2655 return IS_DISP8_OFF_CONST (INTVAL (op1));
2657 return IS_DISP8_CONST (INTVAL (op1));
2668 /* ARx + 5-bit unsigned const
2669 *ARx, *+ARx(n) for n < 32. */
2672 c4x_R_constraint (op)
2675 enum machine_mode mode = GET_MODE (op);
2679 if (GET_CODE (op) != MEM)
2682 switch (GET_CODE (op))
2689 rtx op0 = XEXP (op, 0);
2690 rtx op1 = XEXP (op, 1);
2695 if (GET_CODE (op1) != CONST_INT)
2698 /* HImode and HFmode must be offsettable. */
2699 if (mode == HImode || mode == HFmode)
2700 return IS_UINT5_CONST (INTVAL (op1) + 1);
2702 return IS_UINT5_CONST (INTVAL (op1));
2717 enum machine_mode mode = GET_MODE (op);
2719 if (TARGET_C3X || GET_CODE (op) != MEM)
2723 switch (GET_CODE (op))
2726 return IS_ADDR_OR_PSEUDO_REG (op);
2730 rtx op0 = XEXP (op, 0);
2731 rtx op1 = XEXP (op, 1);
2733 /* HImode and HFmode must be offsettable. */
2734 if (mode == HImode || mode == HFmode)
2735 return IS_ADDR_OR_PSEUDO_REG (op0)
2736 && GET_CODE (op1) == CONST_INT
2737 && IS_UINT5_CONST (INTVAL (op1) + 1);
2740 && IS_ADDR_OR_PSEUDO_REG (op0)
2741 && GET_CODE (op1) == CONST_INT
2742 && IS_UINT5_CONST (INTVAL (op1));
2753 /* ARx + 1-bit unsigned const or IRn
2754 *ARx, *+ARx(1), *-ARx(1), *+ARx(IRn), *-Arx(IRn)
2755 We don't include the pre/post inc/dec forms here since
2756 they are handled by the <> constraints. */
2759 c4x_S_constraint (op)
2762 enum machine_mode mode = GET_MODE (op);
2763 if (GET_CODE (op) != MEM)
2766 switch (GET_CODE (op))
2774 rtx op0 = XEXP (op, 0);
2775 rtx op1 = XEXP (op, 1);
2777 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2778 || (op0 != XEXP (op1, 0)))
2781 op0 = XEXP (op1, 0);
2782 op1 = XEXP (op1, 1);
2783 return REG_P (op0) && REG_P (op1);
2784 /* Pre or post_modify with a displacement of 0 or 1
2785 should not be generated. */
2791 rtx op0 = XEXP (op, 0);
2792 rtx op1 = XEXP (op, 1);
2800 if (GET_CODE (op1) != CONST_INT)
2803 /* HImode and HFmode must be offsettable. */
2804 if (mode == HImode || mode == HFmode)
2805 return IS_DISP1_OFF_CONST (INTVAL (op1));
2807 return IS_DISP1_CONST (INTVAL (op1));
2822 enum machine_mode mode = GET_MODE (op);
2823 if (GET_CODE (op) != MEM)
2827 switch (GET_CODE (op))
2831 if (mode != QImode && mode != QFmode)
2838 return IS_ADDR_OR_PSEUDO_REG (op);
2843 rtx op0 = XEXP (op, 0);
2844 rtx op1 = XEXP (op, 1);
2846 if (mode != QImode && mode != QFmode)
2849 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2850 || (op0 != XEXP (op1, 0)))
2853 op0 = XEXP (op1, 0);
2854 op1 = XEXP (op1, 1);
2855 return REG_P (op0) && IS_ADDR_OR_PSEUDO_REG (op0)
2856 && REG_P (op1) && IS_INDEX_OR_PSEUDO_REG (op1);
2857 /* Pre or post_modify with a displacement of 0 or 1
2858 should not be generated. */
2863 rtx op0 = XEXP (op, 0);
2864 rtx op1 = XEXP (op, 1);
2868 /* HImode and HFmode must be offsettable. */
2869 if (mode == HImode || mode == HFmode)
2870 return IS_ADDR_OR_PSEUDO_REG (op0)
2871 && GET_CODE (op1) == CONST_INT
2872 && IS_DISP1_OFF_CONST (INTVAL (op1));
2875 return (IS_INDEX_OR_PSEUDO_REG (op1)
2876 && IS_ADDR_OR_PSEUDO_REG (op0))
2877 || (IS_ADDR_OR_PSEUDO_REG (op1)
2878 && IS_INDEX_OR_PSEUDO_REG (op0));
2880 return IS_ADDR_OR_PSEUDO_REG (op0)
2881 && GET_CODE (op1) == CONST_INT
2882 && IS_DISP1_CONST (INTVAL (op1));
2894 /* Direct memory operand. */
2897 c4x_T_constraint (op)
2900 if (GET_CODE (op) != MEM)
2904 if (GET_CODE (op) != LO_SUM)
2906 /* Allow call operands. */
2907 return GET_CODE (op) == SYMBOL_REF
2908 && GET_MODE (op) == Pmode
2909 && SYMBOL_REF_FLAG (op);
2912 /* HImode and HFmode are not offsettable. */
2913 if (GET_MODE (op) == HImode || GET_CODE (op) == HFmode)
2916 if ((GET_CODE (XEXP (op, 0)) == REG)
2917 && (REGNO (XEXP (op, 0)) == DP_REGNO))
2918 return c4x_U_constraint (XEXP (op, 1));
2924 /* Symbolic operand. */
2927 c4x_U_constraint (op)
2930 /* Don't allow direct addressing to an arbitrary constant. */
2931 return GET_CODE (op) == CONST
2932 || GET_CODE (op) == SYMBOL_REF
2933 || GET_CODE (op) == LABEL_REF;
2938 c4x_autoinc_operand (op, mode)
2940 enum machine_mode mode ATTRIBUTE_UNUSED;
2942 if (GET_CODE (op) == MEM)
2944 enum rtx_code code = GET_CODE (XEXP (op, 0));
2950 || code == PRE_MODIFY
2951 || code == POST_MODIFY
2959 /* Match any operand. */
2962 any_operand (op, mode)
2963 register rtx op ATTRIBUTE_UNUSED;
2964 enum machine_mode mode ATTRIBUTE_UNUSED;
2970 /* Nonzero if OP is a floating point value with value 0.0. */
2973 fp_zero_operand (op, mode)
2975 enum machine_mode mode ATTRIBUTE_UNUSED;
2979 if (GET_CODE (op) != CONST_DOUBLE)
2981 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2982 return REAL_VALUES_EQUAL (r, dconst0);
2987 const_operand (op, mode)
2989 register enum machine_mode mode;
2995 if (GET_CODE (op) != CONST_DOUBLE
2996 || GET_MODE (op) != mode
2997 || GET_MODE_CLASS (mode) != MODE_FLOAT)
3000 return c4x_immed_float_p (op);
3006 if (GET_CODE (op) == CONSTANT_P_RTX)
3009 if (GET_CODE (op) != CONST_INT
3010 || (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
3011 || GET_MODE_CLASS (mode) != MODE_INT)
3014 return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
3026 stik_const_operand (op, mode)
3028 enum machine_mode mode ATTRIBUTE_UNUSED;
3030 return c4x_K_constant (op);
3035 not_const_operand (op, mode)
3037 enum machine_mode mode ATTRIBUTE_UNUSED;
3039 return c4x_N_constant (op);
3044 reg_operand (op, mode)
3046 enum machine_mode mode;
3048 if (GET_CODE (op) == SUBREG
3049 && GET_MODE (op) == QFmode)
3051 return register_operand (op, mode);
3056 mixed_subreg_operand (op, mode)
3058 enum machine_mode mode ATTRIBUTE_UNUSED;
3060 /* Allow (subreg:HF (reg:HI)) that be generated for a union of an
3061 int and a long double. */
3062 if (GET_CODE (op) == SUBREG
3063 && (GET_MODE (op) == QFmode)
3064 && (GET_MODE (SUBREG_REG (op)) == QImode
3065 || GET_MODE (SUBREG_REG (op)) == HImode))
3072 reg_imm_operand (op, mode)
3074 enum machine_mode mode ATTRIBUTE_UNUSED;
3076 if (REG_P (op) || CONSTANT_P (op))
3083 not_modify_reg (op, mode)
3085 enum machine_mode mode ATTRIBUTE_UNUSED;
3087 if (REG_P (op) || CONSTANT_P (op))
3089 if (GET_CODE (op) != MEM)
3092 switch (GET_CODE (op))
3099 rtx op0 = XEXP (op, 0);
3100 rtx op1 = XEXP (op, 1);
3105 if (REG_P (op1) || GET_CODE (op1) == CONST_INT)
3111 rtx op0 = XEXP (op, 0);
3113 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
3131 not_rc_reg (op, mode)
3133 enum machine_mode mode ATTRIBUTE_UNUSED;
3135 if (REG_P (op) && REGNO (op) == RC_REGNO)
3141 /* Extended precision register R0-R1. */
3144 r0r1_reg_operand (op, mode)
3146 enum machine_mode mode;
3148 if (! reg_operand (op, mode))
3150 if (GET_CODE (op) == SUBREG)
3151 op = SUBREG_REG (op);
3152 return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
3156 /* Extended precision register R2-R3. */
3159 r2r3_reg_operand (op, mode)
3161 enum machine_mode mode;
3163 if (! reg_operand (op, mode))
3165 if (GET_CODE (op) == SUBREG)
3166 op = SUBREG_REG (op);
3167 return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
3171 /* Low extended precision register R0-R7. */
3174 ext_low_reg_operand (op, mode)
3176 enum machine_mode mode;
3178 if (! reg_operand (op, mode))
3180 if (GET_CODE (op) == SUBREG)
3181 op = SUBREG_REG (op);
3182 return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
3186 /* Extended precision register. */
3189 ext_reg_operand (op, mode)
3191 enum machine_mode mode;
3193 if (! reg_operand (op, mode))
3195 if (GET_CODE (op) == SUBREG)
3196 op = SUBREG_REG (op);
3199 return IS_EXT_OR_PSEUDO_REG (op);
3203 /* Standard precision register. */
3206 std_reg_operand (op, mode)
3208 enum machine_mode mode;
3210 if (! reg_operand (op, mode))
3212 if (GET_CODE (op) == SUBREG)
3213 op = SUBREG_REG (op);
3214 return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
3217 /* Standard precision or normal register. */
3220 std_or_reg_operand (op, mode)
3222 enum machine_mode mode;
3224 if (reload_in_progress)
3225 return std_reg_operand (op, mode);
3226 return reg_operand (op, mode);
3229 /* Address register. */
3232 addr_reg_operand (op, mode)
3234 enum machine_mode mode;
3236 if (! reg_operand (op, mode))
3238 return c4x_a_register (op);
3242 /* Index register. */
3245 index_reg_operand (op, mode)
3247 enum machine_mode mode;
3249 if (! reg_operand (op, mode))
3251 if (GET_CODE (op) == SUBREG)
3252 op = SUBREG_REG (op);
3253 return c4x_x_register (op);
3260 dp_reg_operand (op, mode)
3262 enum machine_mode mode ATTRIBUTE_UNUSED;
3264 return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
3271 sp_reg_operand (op, mode)
3273 enum machine_mode mode ATTRIBUTE_UNUSED;
3275 return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
3282 st_reg_operand (op, mode)
3284 enum machine_mode mode ATTRIBUTE_UNUSED;
3286 return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
3293 rc_reg_operand (op, mode)
3295 enum machine_mode mode ATTRIBUTE_UNUSED;
3297 return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
3302 call_address_operand (op, mode)
3304 enum machine_mode mode ATTRIBUTE_UNUSED;
3306 return (REG_P (op) || symbolic_address_operand (op, mode));
3310 /* Symbolic address operand. */
3313 symbolic_address_operand (op, mode)
3315 enum machine_mode mode ATTRIBUTE_UNUSED;
3317 switch (GET_CODE (op))
3329 /* Check dst operand of a move instruction. */
3332 dst_operand (op, mode)
3334 enum machine_mode mode;
3336 if (GET_CODE (op) == SUBREG
3337 && mixed_subreg_operand (op, mode))
3341 return reg_operand (op, mode);
3343 return nonimmediate_operand (op, mode);
3347 /* Check src operand of two operand arithmetic instructions. */
3350 src_operand (op, mode)
3352 enum machine_mode mode;
3354 if (GET_CODE (op) == SUBREG
3355 && mixed_subreg_operand (op, mode))
3359 return reg_operand (op, mode);
3361 if (mode == VOIDmode)
3362 mode = GET_MODE (op);
3364 if (GET_CODE (op) == CONST_INT)
3365 return (mode == QImode || mode == Pmode || mode == HImode)
3366 && c4x_I_constant (op);
3368 /* We don't like CONST_DOUBLE integers. */
3369 if (GET_CODE (op) == CONST_DOUBLE)
3370 return c4x_H_constant (op);
3372 /* Disallow symbolic addresses. Only the predicate
3373 symbolic_address_operand will match these. */
3374 if (GET_CODE (op) == SYMBOL_REF
3375 || GET_CODE (op) == LABEL_REF
3376 || GET_CODE (op) == CONST)
3379 /* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
3380 access to symbolic addresses. These operands will get forced
3381 into a register and the movqi expander will generate a
3382 HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
3383 if (GET_CODE (op) == MEM
3384 && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3385 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3386 || GET_CODE (XEXP (op, 0)) == CONST)))
3387 return ! TARGET_LOAD_DIRECT_MEMS && GET_MODE (op) == mode;
3389 return general_operand (op, mode);
3394 src_hi_operand (op, mode)
3396 enum machine_mode mode;
3398 if (c4x_O_constant (op))
3400 return src_operand (op, mode);
3404 /* Check src operand of two operand logical instructions. */
3407 lsrc_operand (op, mode)
3409 enum machine_mode mode;
3411 if (mode == VOIDmode)
3412 mode = GET_MODE (op);
3414 if (mode != QImode && mode != Pmode)
3415 fatal_insn ("mode not QImode", op);
3417 if (GET_CODE (op) == CONST_INT)
3418 return c4x_L_constant (op) || c4x_J_constant (op);
3420 return src_operand (op, mode);
3424 /* Check src operand of two operand tricky instructions. */
3427 tsrc_operand (op, mode)
3429 enum machine_mode mode;
3431 if (mode == VOIDmode)
3432 mode = GET_MODE (op);
3434 if (mode != QImode && mode != Pmode)
3435 fatal_insn ("mode not QImode", op);
3437 if (GET_CODE (op) == CONST_INT)
3438 return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
3440 return src_operand (op, mode);
3444 /* Check src operand of two operand non immedidate instructions. */
3447 nonimmediate_src_operand (op, mode)
3449 enum machine_mode mode;
3451 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3454 return src_operand (op, mode);
3458 /* Check logical src operand of two operand non immedidate instructions. */
3461 nonimmediate_lsrc_operand (op, mode)
3463 enum machine_mode mode;
3465 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3468 return lsrc_operand (op, mode);
3473 reg_or_const_operand (op, mode)
3475 enum machine_mode mode;
3477 return reg_operand (op, mode) || const_operand (op, mode);
3481 /* Check for indirect operands allowable in parallel instruction. */
3484 par_ind_operand (op, mode)
3486 enum machine_mode mode;
3488 if (mode != VOIDmode && mode != GET_MODE (op))
3491 return c4x_S_indirect (op);
3495 /* Check for operands allowable in parallel instruction. */
3498 parallel_operand (op, mode)
3500 enum machine_mode mode;
3502 return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
3507 c4x_S_address_parse (op, base, incdec, index, disp)
3519 if (GET_CODE (op) != MEM)
3520 fatal_insn ("invalid indirect memory address", op);
3523 switch (GET_CODE (op))
3526 *base = REGNO (XEXP (op, 0));
3532 *base = REGNO (XEXP (op, 0));
3538 *base = REGNO (XEXP (op, 0));
3544 *base = REGNO (XEXP (op, 0));
3550 *base = REGNO (XEXP (op, 0));
3551 if (REG_P (XEXP (XEXP (op, 1), 1)))
3553 *index = REGNO (XEXP (XEXP (op, 1), 1));
3554 *disp = 0; /* ??? */
3557 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3562 *base = REGNO (XEXP (op, 0));
3563 if (REG_P (XEXP (XEXP (op, 1), 1)))
3565 *index = REGNO (XEXP (XEXP (op, 1), 1));
3566 *disp = 1; /* ??? */
3569 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3580 rtx op0 = XEXP (op, 0);
3581 rtx op1 = XEXP (op, 1);
3583 if (c4x_a_register (op0))
3585 if (c4x_x_register (op1))
3587 *base = REGNO (op0);
3588 *index = REGNO (op1);
3591 else if ((GET_CODE (op1) == CONST_INT
3592 && IS_DISP1_CONST (INTVAL (op1))))
3594 *base = REGNO (op0);
3595 *disp = INTVAL (op1);
3599 else if (c4x_x_register (op0) && c4x_a_register (op1))
3601 *base = REGNO (op1);
3602 *index = REGNO (op0);
3609 fatal_insn ("invalid indirect (S) memory address", op);
3615 c4x_address_conflict (op0, op1, store0, store1)
3630 if (MEM_VOLATILE_P (op0) && MEM_VOLATILE_P (op1))
3633 c4x_S_address_parse (op0, &base0, &incdec0, &index0, &disp0);
3634 c4x_S_address_parse (op1, &base1, &incdec1, &index1, &disp1);
3636 if (store0 && store1)
3638 /* If we have two stores in parallel to the same address, then
3639 the C4x only executes one of the stores. This is unlikely to
3640 cause problems except when writing to a hardware device such
3641 as a FIFO since the second write will be lost. The user
3642 should flag the hardware location as being volatile so that
3643 we don't do this optimisation. While it is unlikely that we
3644 have an aliased address if both locations are not marked
3645 volatile, it is probably safer to flag a potential conflict
3646 if either location is volatile. */
3647 if (! flag_argument_noalias)
3649 if (MEM_VOLATILE_P (op0) || MEM_VOLATILE_P (op1))
3654 /* If have a parallel load and a store to the same address, the load
3655 is performed first, so there is no conflict. Similarly, there is
3656 no conflict if have parallel loads from the same address. */
3658 /* Cannot use auto increment or auto decrement twice for same
3660 if (base0 == base1 && incdec0 && incdec0)
3663 /* It might be too confusing for GCC if we have use a base register
3664 with a side effect and a memory reference using the same register
3666 if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
3669 /* We can not optimize the case where op1 and op2 refer to the same
3671 if (base0 == base1 && disp0 == disp1 && index0 == index1)
3679 /* Check for while loop inside a decrement and branch loop. */
3682 c4x_label_conflict (insn, jump, db)
3689 if (GET_CODE (insn) == CODE_LABEL)
3691 if (CODE_LABEL_NUMBER (jump) == CODE_LABEL_NUMBER (insn))
3693 if (CODE_LABEL_NUMBER (db) == CODE_LABEL_NUMBER (insn))
3696 insn = PREV_INSN (insn);
3702 /* Validate combination of operands for parallel load/store instructions. */
3705 valid_parallel_load_store (operands, mode)
3707 enum machine_mode mode ATTRIBUTE_UNUSED;
3709 rtx op0 = operands[0];
3710 rtx op1 = operands[1];
3711 rtx op2 = operands[2];
3712 rtx op3 = operands[3];
3714 if (GET_CODE (op0) == SUBREG)
3715 op0 = SUBREG_REG (op0);
3716 if (GET_CODE (op1) == SUBREG)
3717 op1 = SUBREG_REG (op1);
3718 if (GET_CODE (op2) == SUBREG)
3719 op2 = SUBREG_REG (op2);
3720 if (GET_CODE (op3) == SUBREG)
3721 op3 = SUBREG_REG (op3);
3723 /* The patterns should only allow ext_low_reg_operand() or
3724 par_ind_operand() operands. Thus of the 4 operands, only 2
3725 should be REGs and the other 2 should be MEMs. */
3727 /* This test prevents the multipack pass from using this pattern if
3728 op0 is used as an index or base register in op2 or op3, since
3729 this combination will require reloading. */
3730 if (GET_CODE (op0) == REG
3731 && ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
3732 || (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
3736 if (GET_CODE (op0) == REG && GET_CODE (op2) == REG)
3737 return (REGNO (op0) != REGNO (op2))
3738 && GET_CODE (op1) == MEM && GET_CODE (op3) == MEM
3739 && ! c4x_address_conflict (op1, op3, 0, 0);
3742 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG)
3743 return GET_CODE (op0) == MEM && GET_CODE (op2) == MEM
3744 && ! c4x_address_conflict (op0, op2, 1, 1);
3747 if (GET_CODE (op0) == REG && GET_CODE (op3) == REG)
3748 return GET_CODE (op1) == MEM && GET_CODE (op2) == MEM
3749 && ! c4x_address_conflict (op1, op2, 0, 1);
3752 if (GET_CODE (op1) == REG && GET_CODE (op2) == REG)
3753 return GET_CODE (op0) == MEM && GET_CODE (op3) == MEM
3754 && ! c4x_address_conflict (op0, op3, 1, 0);
3761 valid_parallel_operands_4 (operands, mode)
3763 enum machine_mode mode ATTRIBUTE_UNUSED;
3765 rtx op0 = operands[0];
3766 rtx op2 = operands[2];
3768 if (GET_CODE (op0) == SUBREG)
3769 op0 = SUBREG_REG (op0);
3770 if (GET_CODE (op2) == SUBREG)
3771 op2 = SUBREG_REG (op2);
3773 /* This test prevents the multipack pass from using this pattern if
3774 op0 is used as an index or base register in op2, since this combination
3775 will require reloading. */
3776 if (GET_CODE (op0) == REG
3777 && GET_CODE (op2) == MEM
3778 && reg_mentioned_p (op0, XEXP (op2, 0)))
3786 valid_parallel_operands_5 (operands, mode)
3788 enum machine_mode mode ATTRIBUTE_UNUSED;
3791 rtx op0 = operands[0];
3792 rtx op1 = operands[1];
3793 rtx op2 = operands[2];
3794 rtx op3 = operands[3];
3796 if (GET_CODE (op0) == SUBREG)
3797 op0 = SUBREG_REG (op0);
3798 if (GET_CODE (op1) == SUBREG)
3799 op1 = SUBREG_REG (op1);
3800 if (GET_CODE (op2) == SUBREG)
3801 op2 = SUBREG_REG (op2);
3803 /* The patterns should only allow ext_low_reg_operand() or
3804 par_ind_operand() operands. Operands 1 and 2 may be commutative
3805 but only one of them can be a register. */
3806 if (GET_CODE (op1) == REG)
3808 if (GET_CODE (op2) == REG)
3814 /* This test prevents the multipack pass from using this pattern if
3815 op0 is used as an index or base register in op3, since this combination
3816 will require reloading. */
3817 if (GET_CODE (op0) == REG
3818 && GET_CODE (op3) == MEM
3819 && reg_mentioned_p (op0, XEXP (op3, 0)))
3827 valid_parallel_operands_6 (operands, mode)
3829 enum machine_mode mode ATTRIBUTE_UNUSED;
3832 rtx op0 = operands[0];
3833 rtx op1 = operands[1];
3834 rtx op2 = operands[2];
3835 rtx op4 = operands[4];
3836 rtx op5 = operands[5];
3838 if (GET_CODE (op1) == SUBREG)
3839 op1 = SUBREG_REG (op1);
3840 if (GET_CODE (op2) == SUBREG)
3841 op2 = SUBREG_REG (op2);
3842 if (GET_CODE (op4) == SUBREG)
3843 op4 = SUBREG_REG (op4);
3844 if (GET_CODE (op5) == SUBREG)
3845 op5 = SUBREG_REG (op5);
3847 /* The patterns should only allow ext_low_reg_operand() or
3848 par_ind_operand() operands. Thus of the 4 input operands, only 2
3849 should be REGs and the other 2 should be MEMs. */
3851 if (GET_CODE (op1) == REG)
3853 if (GET_CODE (op2) == REG)
3855 if (GET_CODE (op4) == REG)
3857 if (GET_CODE (op5) == REG)
3860 /* The new C30/C40 silicon dies allow 3 regs of the 4 input operands.
3861 Perhaps we should count the MEMs as well? */
3865 /* This test prevents the multipack pass from using this pattern if
3866 op0 is used as an index or base register in op4 or op5, since
3867 this combination will require reloading. */
3868 if (GET_CODE (op0) == REG
3869 && ((GET_CODE (op4) == MEM && reg_mentioned_p (op0, XEXP (op4, 0)))
3870 || (GET_CODE (op5) == MEM && reg_mentioned_p (op0, XEXP (op5, 0)))))
3877 /* Validate combination of src operands. Note that the operands have
3878 been screened by the src_operand predicate. We just have to check
3879 that the combination of operands is valid. If FORCE is set, ensure
3880 that the destination regno is valid if we have a 2 operand insn. */
3883 c4x_valid_operands (code, operands, mode, force)
3886 enum machine_mode mode ATTRIBUTE_UNUSED;
3891 enum rtx_code code1;
3892 enum rtx_code code2;
3894 if (code == COMPARE)
3905 if (GET_CODE (op1) == SUBREG)
3906 op1 = SUBREG_REG (op1);
3907 if (GET_CODE (op2) == SUBREG)
3908 op2 = SUBREG_REG (op2);
3910 code1 = GET_CODE (op1);
3911 code2 = GET_CODE (op2);
3913 if (code1 == REG && code2 == REG)
3916 if (code1 == MEM && code2 == MEM)
3918 if (c4x_S_indirect (op1) && c4x_S_indirect (op2))
3920 return c4x_R_indirect (op1) && c4x_R_indirect (op2);
3931 if (c4x_J_constant (op2) && c4x_R_indirect (op1))
3936 if (! c4x_H_constant (op2))
3940 /* Any valid memory operand screened by src_operand is OK. */
3943 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3944 into a stack slot memory address comprising a PLUS and a
3950 fatal_insn ("c4x_valid_operands: Internal error", op2);
3954 /* Check that we have a valid destination register for a two operand
3956 return ! force || code == COMPARE || REGNO (op1) == REGNO (operands[0]);
3959 /* We assume MINUS is commutative since the subtract patterns
3960 also support the reverse subtract instructions. Since op1
3961 is not a register, and op2 is a register, op1 can only
3962 be a restricted memory operand for a shift instruction. */
3963 if (code == ASHIFTRT || code == LSHIFTRT
3964 || code == ASHIFT || code == COMPARE)
3966 && (c4x_S_indirect (op1) || c4x_R_indirect (op1));
3971 if (c4x_J_constant (op1) && c4x_R_indirect (op2))
3976 if (! c4x_H_constant (op1))
3980 /* Any valid memory operand screened by src_operand is OK. */
3988 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3989 into a stack slot memory address comprising a PLUS and a
3999 /* Check that we have a valid destination register for a two operand
4001 return ! force || REGNO (op1) == REGNO (operands[0]);
4005 int valid_operands (code, operands, mode)
4008 enum machine_mode mode;
4011 /* If we are not optimizing then we have to let anything go and let
4012 reload fix things up. instantiate_decl in function.c can produce
4013 invalid insns by changing the offset of a memory operand from a
4014 valid one into an invalid one, when the second operand is also a
4015 memory operand. The alternative is not to allow two memory
4016 operands for an insn when not optimizing. The problem only rarely
4017 occurs, for example with the C-torture program DFcmp.c. */
4019 return ! optimize || c4x_valid_operands (code, operands, mode, 0);
4024 legitimize_operands (code, operands, mode)
4027 enum machine_mode mode;
4029 /* Compare only has 2 operands. */
4030 if (code == COMPARE)
4032 /* During RTL generation, force constants into pseudos so that
4033 they can get hoisted out of loops. This will tie up an extra
4034 register but can save an extra cycle. Only do this if loop
4035 optimisation enabled. (We cannot pull this trick for add and
4036 sub instructions since the flow pass won't find
4037 autoincrements etc.) This allows us to generate compare
4038 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
4039 of LDI *AR0++, R0; CMPI 42, R0.
4041 Note that expand_binops will try to load an expensive constant
4042 into a register if it is used within a loop. Unfortunately,
4043 the cost mechanism doesn't allow us to look at the other
4044 operand to decide whether the constant is expensive. */
4046 if (! reload_in_progress
4049 && GET_CODE (operands[1]) == CONST_INT
4050 && preserve_subexpressions_p ()
4051 && rtx_cost (operands[1], code) > 1)
4052 operands[1] = force_reg (mode, operands[1]);
4054 if (! reload_in_progress
4055 && ! c4x_valid_operands (code, operands, mode, 0))
4056 operands[0] = force_reg (mode, operands[0]);
4060 /* We cannot do this for ADDI/SUBI insns since we will
4061 defeat the flow pass from finding autoincrement addressing
4063 if (! reload_in_progress
4064 && ! ((code == PLUS || code == MINUS) && mode == Pmode)
4067 && GET_CODE (operands[2]) == CONST_INT
4068 && preserve_subexpressions_p ()
4069 && rtx_cost (operands[2], code) > 1)
4070 operands[2] = force_reg (mode, operands[2]);
4072 /* We can get better code on a C30 if we force constant shift counts
4073 into a register. This way they can get hoisted out of loops,
4074 tying up a register, but saving an instruction. The downside is
4075 that they may get allocated to an address or index register, and
4076 thus we will get a pipeline conflict if there is a nearby
4077 indirect address using an address register.
4079 Note that expand_binops will not try to load an expensive constant
4080 into a register if it is used within a loop for a shift insn. */
4082 if (! reload_in_progress
4083 && ! c4x_valid_operands (code, operands, mode, TARGET_FORCE))
4085 /* If the operand combination is invalid, we force operand1 into a
4086 register, preventing reload from having doing to do this at a
4088 operands[1] = force_reg (mode, operands[1]);
4091 emit_move_insn (operands[0], operands[1]);
4092 operands[1] = copy_rtx (operands[0]);
4096 /* Just in case... */
4097 if (! c4x_valid_operands (code, operands, mode, 0))
4098 operands[2] = force_reg (mode, operands[2]);
4102 /* Right shifts require a negative shift count, but GCC expects
4103 a positive count, so we emit a NEG. */
4104 if ((code == ASHIFTRT || code == LSHIFTRT)
4105 && (GET_CODE (operands[2]) != CONST_INT))
4106 operands[2] = gen_rtx_NEG (mode, negate_rtx (mode, operands[2]));
4112 /* The following predicates are used for instruction scheduling. */
4115 group1_reg_operand (op, mode)
4117 enum machine_mode mode;
4119 if (mode != VOIDmode && mode != GET_MODE (op))
4121 if (GET_CODE (op) == SUBREG)
4122 op = SUBREG_REG (op);
4123 return REG_P (op) && (! reload_completed || IS_GROUP1_REG (op));
4128 group1_mem_operand (op, mode)
4130 enum machine_mode mode;
4132 if (mode != VOIDmode && mode != GET_MODE (op))
4135 if (GET_CODE (op) == MEM)
4138 if (GET_CODE (op) == PLUS)
4140 rtx op0 = XEXP (op, 0);
4141 rtx op1 = XEXP (op, 1);
4143 if ((REG_P (op0) && (! reload_completed || IS_GROUP1_REG (op0)))
4144 || (REG_P (op1) && (! reload_completed || IS_GROUP1_REG (op1))))
4147 else if ((REG_P (op)) && (! reload_completed || IS_GROUP1_REG (op)))
4155 /* Return true if any one of the address registers. */
4158 arx_reg_operand (op, mode)
4160 enum machine_mode mode;
4162 if (mode != VOIDmode && mode != GET_MODE (op))
4164 if (GET_CODE (op) == SUBREG)
4165 op = SUBREG_REG (op);
4166 return REG_P (op) && (! reload_completed || IS_ADDR_REG (op));
4171 c4x_arn_reg_operand (op, mode, regno)
4173 enum machine_mode mode;
4176 if (mode != VOIDmode && mode != GET_MODE (op))
4178 if (GET_CODE (op) == SUBREG)
4179 op = SUBREG_REG (op);
4180 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4185 c4x_arn_mem_operand (op, mode, regno)
4187 enum machine_mode mode;
4190 if (mode != VOIDmode && mode != GET_MODE (op))
4193 if (GET_CODE (op) == MEM)
4196 switch (GET_CODE (op))
4205 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4209 if (REG_P (XEXP (op, 0)) && (! reload_completed
4210 || (REGNO (XEXP (op, 0)) == regno)))
4212 if (REG_P (XEXP (XEXP (op, 1), 1))
4213 && (! reload_completed
4214 || (REGNO (XEXP (XEXP (op, 1), 1)) == regno)))
4220 rtx op0 = XEXP (op, 0);
4221 rtx op1 = XEXP (op, 1);
4223 if ((REG_P (op0) && (! reload_completed
4224 || (REGNO (op0) == regno)))
4225 || (REG_P (op1) && (! reload_completed
4226 || (REGNO (op1) == regno))))
4240 ar0_reg_operand (op, mode)
4242 enum machine_mode mode;
4244 return c4x_arn_reg_operand (op, mode, AR0_REGNO);
4249 ar0_mem_operand (op, mode)
4251 enum machine_mode mode;
4253 return c4x_arn_mem_operand (op, mode, AR0_REGNO);
4258 ar1_reg_operand (op, mode)
4260 enum machine_mode mode;
4262 return c4x_arn_reg_operand (op, mode, AR1_REGNO);
4267 ar1_mem_operand (op, mode)
4269 enum machine_mode mode;
4271 return c4x_arn_mem_operand (op, mode, AR1_REGNO);
4276 ar2_reg_operand (op, mode)
4278 enum machine_mode mode;
4280 return c4x_arn_reg_operand (op, mode, AR2_REGNO);
4285 ar2_mem_operand (op, mode)
4287 enum machine_mode mode;
4289 return c4x_arn_mem_operand (op, mode, AR2_REGNO);
4294 ar3_reg_operand (op, mode)
4296 enum machine_mode mode;
4298 return c4x_arn_reg_operand (op, mode, AR3_REGNO);
4303 ar3_mem_operand (op, mode)
4305 enum machine_mode mode;
4307 return c4x_arn_mem_operand (op, mode, AR3_REGNO);
4312 ar4_reg_operand (op, mode)
4314 enum machine_mode mode;
4316 return c4x_arn_reg_operand (op, mode, AR4_REGNO);
4321 ar4_mem_operand (op, mode)
4323 enum machine_mode mode;
4325 return c4x_arn_mem_operand (op, mode, AR4_REGNO);
4330 ar5_reg_operand (op, mode)
4332 enum machine_mode mode;
4334 return c4x_arn_reg_operand (op, mode, AR5_REGNO);
4339 ar5_mem_operand (op, mode)
4341 enum machine_mode mode;
4343 return c4x_arn_mem_operand (op, mode, AR5_REGNO);
4348 ar6_reg_operand (op, mode)
4350 enum machine_mode mode;
4352 return c4x_arn_reg_operand (op, mode, AR6_REGNO);
4357 ar6_mem_operand (op, mode)
4359 enum machine_mode mode;
4361 return c4x_arn_mem_operand (op, mode, AR6_REGNO);
4366 ar7_reg_operand (op, mode)
4368 enum machine_mode mode;
4370 return c4x_arn_reg_operand (op, mode, AR7_REGNO);
4375 ar7_mem_operand (op, mode)
4377 enum machine_mode mode;
4379 return c4x_arn_mem_operand (op, mode, AR7_REGNO);
4384 ir0_reg_operand (op, mode)
4386 enum machine_mode mode;
4388 return c4x_arn_reg_operand (op, mode, IR0_REGNO);
4393 ir0_mem_operand (op, mode)
4395 enum machine_mode mode;
4397 return c4x_arn_mem_operand (op, mode, IR0_REGNO);
4402 ir1_reg_operand (op, mode)
4404 enum machine_mode mode;
4406 return c4x_arn_reg_operand (op, mode, IR1_REGNO);
4411 ir1_mem_operand (op, mode)
4413 enum machine_mode mode;
4415 return c4x_arn_mem_operand (op, mode, IR1_REGNO);
4419 /* This is similar to operand_subword but allows autoincrement
4423 c4x_operand_subword (op, i, validate_address, mode)
4426 int validate_address;
4427 enum machine_mode mode;
4429 if (mode != HImode && mode != HFmode)
4430 fatal_insn ("c4x_operand_subword: invalid mode", op);
4432 if (mode == HFmode && REG_P (op))
4433 fatal_insn ("c4x_operand_subword: invalid operand", op);
4435 if (GET_CODE (op) == MEM)
4437 enum rtx_code code = GET_CODE (XEXP (op, 0));
4438 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4439 enum machine_mode submode;
4444 else if (mode == HFmode)
4451 return gen_rtx_MEM (submode, XEXP (op, 0));
4457 /* We could handle these with some difficulty.
4458 e.g., *p-- => *(p-=2); *(p+1). */
4459 fatal_insn ("c4x_operand_subword: invalid autoincrement", op);
4465 fatal_insn ("c4x_operand_subword: invalid address", op);
4467 /* Even though offsettable_address_p considers (MEM
4468 (LO_SUM)) to be offsettable, it is not safe if the
4469 address is at the end of the data page since we also have
4470 to fix up the associated high PART. In this case where
4471 we are trying to split a HImode or HFmode memory
4472 reference, we would have to emit another insn to reload a
4473 new HIGH value. It's easier to disable LO_SUM memory references
4474 in HImode or HFmode and we probably get better code. */
4476 fatal_insn ("c4x_operand_subword: address not offsettable", op);
4483 return operand_subword (op, i, validate_address, mode);
4488 struct name_list *next;
4492 static struct name_list *global_head;
4493 static struct name_list *extern_head;
4496 /* Add NAME to list of global symbols and remove from external list if
4497 present on external list. */
4500 c4x_global_label (name)
4503 struct name_list *p, *last;
4505 /* Do not insert duplicate names, so linearly search through list of
4510 if (strcmp (p->name, name) == 0)
4514 p = (struct name_list *) xmalloc (sizeof *p);
4515 p->next = global_head;
4519 /* Remove this name from ref list if present. */
4524 if (strcmp (p->name, name) == 0)
4527 last->next = p->next;
4529 extern_head = p->next;
4538 /* Add NAME to list of external symbols. */
4541 c4x_external_ref (name)
4544 struct name_list *p;
4546 /* Do not insert duplicate names. */
4550 if (strcmp (p->name, name) == 0)
4555 /* Do not insert ref if global found. */
4559 if (strcmp (p->name, name) == 0)
4563 p = (struct name_list *) xmalloc (sizeof *p);
4564 p->next = extern_head;
4574 struct name_list *p;
4576 /* Output all external names that are not global. */
4580 fprintf (fp, "\t.ref\t");
4581 assemble_name (fp, p->name);
4585 fprintf (fp, "\t.end\n");
4590 c4x_check_attribute (attrib, list, decl, attributes)
4592 tree list, decl, *attributes;
4594 while (list != NULL_TREE
4595 && IDENTIFIER_POINTER (TREE_PURPOSE (list))
4596 != IDENTIFIER_POINTER (DECL_NAME (decl)))
4597 list = TREE_CHAIN (list);
4599 *attributes = tree_cons (get_identifier (attrib), TREE_VALUE (list),
4605 c4x_insert_attributes (decl, attributes)
4606 tree decl, *attributes;
4608 switch (TREE_CODE (decl))
4611 c4x_check_attribute ("section", code_tree, decl, attributes);
4612 c4x_check_attribute ("const", pure_tree, decl, attributes);
4613 c4x_check_attribute ("noreturn", noreturn_tree, decl, attributes);
4614 c4x_check_attribute ("interrupt", interrupt_tree, decl, attributes);
4615 c4x_check_attribute ("naked", naked_tree, decl, attributes);
4619 c4x_check_attribute ("section", data_tree, decl, attributes);
4627 /* Table of valid machine attributes. */
4628 const struct attribute_spec c4x_attribute_table[] =
4630 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4631 { "interrupt", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4632 { "naked", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4633 { "leaf_pretend", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4634 { NULL, 0, 0, false, false, false, NULL }
4637 /* Handle an attribute requiring a FUNCTION_TYPE;
4638 arguments as in struct attribute_spec.handler. */
4640 c4x_handle_fntype_attribute (node, name, args, flags, no_add_attrs)
4643 tree args ATTRIBUTE_UNUSED;
4644 int flags ATTRIBUTE_UNUSED;
4647 if (TREE_CODE (*node) != FUNCTION_TYPE)
4649 warning ("`%s' attribute only applies to functions",
4650 IDENTIFIER_POINTER (name));
4651 *no_add_attrs = true;
4658 /* !!! FIXME to emit RPTS correctly. */
4661 c4x_rptb_rpts_p (insn, op)
4664 /* The next insn should be our label marking where the
4665 repeat block starts. */
4666 insn = NEXT_INSN (insn);
4667 if (GET_CODE (insn) != CODE_LABEL)
4669 /* Some insns may have been shifted between the RPTB insn
4670 and the top label... They were probably destined to
4671 be moved out of the loop. For now, let's leave them
4672 where they are and print a warning. We should
4673 probably move these insns before the repeat block insn. */
4675 fatal_insn("c4x_rptb_rpts_p: Repeat block top label moved\n",
4680 /* Skip any notes. */
4681 insn = next_nonnote_insn (insn);
4683 /* This should be our first insn in the loop. */
4684 if (! INSN_P (insn))
4687 /* Skip any notes. */
4688 insn = next_nonnote_insn (insn);
4690 if (! INSN_P (insn))
4693 if (recog_memoized (insn) != CODE_FOR_rptb_end)
4699 return (GET_CODE (op) == CONST_INT) && TARGET_RPTS_CYCLES (INTVAL (op));
4703 /* Check if register r11 is used as the destination of an insn. */
4716 if (INSN_P (x) && GET_CODE (PATTERN (x)) == SEQUENCE)
4717 x = XVECEXP (PATTERN (x), 0, XVECLEN (PATTERN (x), 0) - 1);
4719 if (INSN_P (x) && (set = single_set (x)))
4722 if (GET_CODE (x) == REG && REGNO (x) == R11_REGNO)
4725 fmt = GET_RTX_FORMAT (GET_CODE (x));
4726 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4730 if (c4x_r11_set_p (XEXP (x, i)))
4733 else if (fmt[i] == 'E')
4734 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4735 if (c4x_r11_set_p (XVECEXP (x, i, j)))
4742 /* The c4x sometimes has a problem when the insn before the laj insn
4743 sets the r11 register. Check for this situation. */
4746 c4x_check_laj_p (insn)
4749 insn = prev_nonnote_insn (insn);
4751 /* If this is the start of the function no nop is needed. */
4755 /* If the previous insn is a code label we have to insert a nop. This
4756 could be a jump or table jump. We can find the normal jumps by
4757 scanning the function but this will not find table jumps. */
4758 if (GET_CODE (insn) == CODE_LABEL)
4761 /* If the previous insn sets register r11 we have to insert a nop. */
4762 if (c4x_r11_set_p (insn))
4765 /* No nop needed. */
4770 /* Adjust the cost of a scheduling dependency. Return the new cost of
4771 a dependency LINK or INSN on DEP_INSN. COST is the current cost.
4772 A set of an address register followed by a use occurs a 2 cycle
4773 stall (reduced to a single cycle on the c40 using LDA), while
4774 a read of an address register followed by a use occurs a single cycle. */
4776 #define SET_USE_COST 3
4777 #define SETLDA_USE_COST 2
4778 #define READ_USE_COST 2
4781 c4x_adjust_cost (insn, link, dep_insn, cost)
4787 /* Don't worry about this until we know what registers have been
4789 if (flag_schedule_insns == 0 && ! reload_completed)
4792 /* How do we handle dependencies where a read followed by another
4793 read causes a pipeline stall? For example, a read of ar0 followed
4794 by the use of ar0 for a memory reference. It looks like we
4795 need to extend the scheduler to handle this case. */
4797 /* Reload sometimes generates a CLOBBER of a stack slot, e.g.,
4798 (clobber (mem:QI (plus:QI (reg:QI 11 ar3) (const_int 261)))),
4799 so only deal with insns we know about. */
4800 if (recog_memoized (dep_insn) < 0)
4803 if (REG_NOTE_KIND (link) == 0)
4807 /* Data dependency; DEP_INSN writes a register that INSN reads some
4811 if (get_attr_setgroup1 (dep_insn) && get_attr_usegroup1 (insn))
4812 max = SET_USE_COST > max ? SET_USE_COST : max;
4813 if (get_attr_readarx (dep_insn) && get_attr_usegroup1 (insn))
4814 max = READ_USE_COST > max ? READ_USE_COST : max;
4818 /* This could be significantly optimized. We should look
4819 to see if dep_insn sets ar0-ar7 or ir0-ir1 and if
4820 insn uses ar0-ar7. We then test if the same register
4821 is used. The tricky bit is that some operands will
4822 use several registers... */
4823 if (get_attr_setar0 (dep_insn) && get_attr_usear0 (insn))
4824 max = SET_USE_COST > max ? SET_USE_COST : max;
4825 if (get_attr_setlda_ar0 (dep_insn) && get_attr_usear0 (insn))
4826 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4827 if (get_attr_readar0 (dep_insn) && get_attr_usear0 (insn))
4828 max = READ_USE_COST > max ? READ_USE_COST : max;
4830 if (get_attr_setar1 (dep_insn) && get_attr_usear1 (insn))
4831 max = SET_USE_COST > max ? SET_USE_COST : max;
4832 if (get_attr_setlda_ar1 (dep_insn) && get_attr_usear1 (insn))
4833 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4834 if (get_attr_readar1 (dep_insn) && get_attr_usear1 (insn))
4835 max = READ_USE_COST > max ? READ_USE_COST : max;
4837 if (get_attr_setar2 (dep_insn) && get_attr_usear2 (insn))
4838 max = SET_USE_COST > max ? SET_USE_COST : max;
4839 if (get_attr_setlda_ar2 (dep_insn) && get_attr_usear2 (insn))
4840 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4841 if (get_attr_readar2 (dep_insn) && get_attr_usear2 (insn))
4842 max = READ_USE_COST > max ? READ_USE_COST : max;
4844 if (get_attr_setar3 (dep_insn) && get_attr_usear3 (insn))
4845 max = SET_USE_COST > max ? SET_USE_COST : max;
4846 if (get_attr_setlda_ar3 (dep_insn) && get_attr_usear3 (insn))
4847 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4848 if (get_attr_readar3 (dep_insn) && get_attr_usear3 (insn))
4849 max = READ_USE_COST > max ? READ_USE_COST : max;
4851 if (get_attr_setar4 (dep_insn) && get_attr_usear4 (insn))
4852 max = SET_USE_COST > max ? SET_USE_COST : max;
4853 if (get_attr_setlda_ar4 (dep_insn) && get_attr_usear4 (insn))
4854 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4855 if (get_attr_readar4 (dep_insn) && get_attr_usear4 (insn))
4856 max = READ_USE_COST > max ? READ_USE_COST : max;
4858 if (get_attr_setar5 (dep_insn) && get_attr_usear5 (insn))
4859 max = SET_USE_COST > max ? SET_USE_COST : max;
4860 if (get_attr_setlda_ar5 (dep_insn) && get_attr_usear5 (insn))
4861 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4862 if (get_attr_readar5 (dep_insn) && get_attr_usear5 (insn))
4863 max = READ_USE_COST > max ? READ_USE_COST : max;
4865 if (get_attr_setar6 (dep_insn) && get_attr_usear6 (insn))
4866 max = SET_USE_COST > max ? SET_USE_COST : max;
4867 if (get_attr_setlda_ar6 (dep_insn) && get_attr_usear6 (insn))
4868 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4869 if (get_attr_readar6 (dep_insn) && get_attr_usear6 (insn))
4870 max = READ_USE_COST > max ? READ_USE_COST : max;
4872 if (get_attr_setar7 (dep_insn) && get_attr_usear7 (insn))
4873 max = SET_USE_COST > max ? SET_USE_COST : max;
4874 if (get_attr_setlda_ar7 (dep_insn) && get_attr_usear7 (insn))
4875 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4876 if (get_attr_readar7 (dep_insn) && get_attr_usear7 (insn))
4877 max = READ_USE_COST > max ? READ_USE_COST : max;
4879 if (get_attr_setir0 (dep_insn) && get_attr_useir0 (insn))
4880 max = SET_USE_COST > max ? SET_USE_COST : max;
4881 if (get_attr_setlda_ir0 (dep_insn) && get_attr_useir0 (insn))
4882 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4884 if (get_attr_setir1 (dep_insn) && get_attr_useir1 (insn))
4885 max = SET_USE_COST > max ? SET_USE_COST : max;
4886 if (get_attr_setlda_ir1 (dep_insn) && get_attr_useir1 (insn))
4887 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4893 /* For other data dependencies, the default cost specified in the
4897 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4899 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4902 /* For c4x anti dependencies, the cost is 0. */
4905 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4907 /* Output dependency; DEP_INSN writes a register that INSN writes some
4910 /* For c4x output dependencies, the cost is 0. */
4918 c4x_init_builtins ()
4920 tree endlink = void_list_node;
4922 builtin_function ("fast_ftoi",
4925 tree_cons (NULL_TREE, double_type_node, endlink)),
4926 C4X_BUILTIN_FIX, BUILT_IN_MD, NULL, NULL_TREE);
4927 builtin_function ("ansi_ftoi",
4930 tree_cons (NULL_TREE, double_type_node, endlink)),
4931 C4X_BUILTIN_FIX_ANSI, BUILT_IN_MD, NULL, NULL_TREE);
4933 builtin_function ("fast_imult",
4936 tree_cons (NULL_TREE, integer_type_node,
4937 tree_cons (NULL_TREE,
4938 integer_type_node, endlink))),
4939 C4X_BUILTIN_MPYI, BUILT_IN_MD, NULL, NULL_TREE);
4942 builtin_function ("toieee",
4945 tree_cons (NULL_TREE, double_type_node, endlink)),
4946 C4X_BUILTIN_TOIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4947 builtin_function ("frieee",
4950 tree_cons (NULL_TREE, double_type_node, endlink)),
4951 C4X_BUILTIN_FRIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4952 builtin_function ("fast_invf",
4955 tree_cons (NULL_TREE, double_type_node, endlink)),
4956 C4X_BUILTIN_RCPF, BUILT_IN_MD, NULL, NULL_TREE);
4962 c4x_expand_builtin (exp, target, subtarget, mode, ignore)
4965 rtx subtarget ATTRIBUTE_UNUSED;
4966 enum machine_mode mode ATTRIBUTE_UNUSED;
4967 int ignore ATTRIBUTE_UNUSED;
4969 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4970 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4971 tree arglist = TREE_OPERAND (exp, 1);
4977 case C4X_BUILTIN_FIX:
4978 arg0 = TREE_VALUE (arglist);
4979 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4980 r0 = protect_from_queue (r0, 0);
4981 if (! target || ! register_operand (target, QImode))
4982 target = gen_reg_rtx (QImode);
4983 emit_insn (gen_fixqfqi_clobber (target, r0));
4986 case C4X_BUILTIN_FIX_ANSI:
4987 arg0 = TREE_VALUE (arglist);
4988 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4989 r0 = protect_from_queue (r0, 0);
4990 if (! target || ! register_operand (target, QImode))
4991 target = gen_reg_rtx (QImode);
4992 emit_insn (gen_fix_truncqfqi2 (target, r0));
4995 case C4X_BUILTIN_MPYI:
4998 arg0 = TREE_VALUE (arglist);
4999 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5000 r0 = expand_expr (arg0, NULL_RTX, QImode, 0);
5001 r1 = expand_expr (arg1, NULL_RTX, QImode, 0);
5002 r0 = protect_from_queue (r0, 0);
5003 r1 = protect_from_queue (r1, 0);
5004 if (! target || ! register_operand (target, QImode))
5005 target = gen_reg_rtx (QImode);
5006 emit_insn (gen_mulqi3_24_clobber (target, r0, r1));
5009 case C4X_BUILTIN_TOIEEE:
5012 arg0 = TREE_VALUE (arglist);
5013 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
5014 r0 = protect_from_queue (r0, 0);
5015 if (! target || ! register_operand (target, QFmode))
5016 target = gen_reg_rtx (QFmode);
5017 emit_insn (gen_toieee (target, r0));
5020 case C4X_BUILTIN_FRIEEE:
5023 arg0 = TREE_VALUE (arglist);
5024 if (TREE_CODE (arg0) == VAR_DECL || TREE_CODE (arg0) == PARM_DECL)
5025 put_var_into_stack (arg0);
5026 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
5027 r0 = protect_from_queue (r0, 0);
5028 if (register_operand (r0, QFmode))
5030 r1 = assign_stack_local (QFmode, GET_MODE_SIZE (QFmode), 0);
5031 emit_move_insn (r1, r0);
5034 if (! target || ! register_operand (target, QFmode))
5035 target = gen_reg_rtx (QFmode);
5036 emit_insn (gen_frieee (target, r0));
5039 case C4X_BUILTIN_RCPF:
5042 arg0 = TREE_VALUE (arglist);
5043 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
5044 r0 = protect_from_queue (r0, 0);
5045 if (! target || ! register_operand (target, QFmode))
5046 target = gen_reg_rtx (QFmode);
5047 emit_insn (gen_rcpfqf_clobber (target, r0));
5054 c4x_asm_named_section (name, flags)
5056 unsigned int flags ATTRIBUTE_UNUSED;
5058 fprintf (asm_out_file, "\t.sect\t\"%s\"\n", name);
5062 c4x_globalize_label (stream, name)
5066 default_globalize_label (stream, name);
5067 c4x_global_label (name);
5070 #define SHIFT_CODE_P(C) \
5071 ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
5072 #define LOGICAL_CODE_P(C) \
5073 ((C) == NOT || (C) == AND || (C) == IOR || (C) == XOR)
5075 /* Compute a (partial) cost for rtx X. Return true if the complete
5076 cost has been computed, and false if subexpressions should be
5077 scanned. In either case, *TOTAL contains the cost result. */
5080 c4x_rtx_costs (x, code, outer_code, total)
5082 int code, outer_code;
5089 /* Some small integers are effectively free for the C40. We should
5090 also consider if we are using the small memory model. With
5091 the big memory model we require an extra insn for a constant
5092 loaded from memory. */
5096 if (c4x_J_constant (x))
5098 else if (! TARGET_C3X
5099 && outer_code == AND
5100 && (val == 255 || val == 65535))
5102 else if (! TARGET_C3X
5103 && (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
5104 && (val == 16 || val == 24))
5106 else if (TARGET_C3X && SHIFT_CODE_P (outer_code))
5108 else if (LOGICAL_CODE_P (outer_code)
5109 ? c4x_L_constant (x) : c4x_I_constant (x))
5122 if (c4x_H_constant (x))
5124 else if (GET_MODE (x) == QFmode)
5130 /* ??? Note that we return true, rather than false so that rtx_cost
5131 doesn't include the constant costs. Otherwise expand_mult will
5132 think that it is cheaper to synthesize a multiply rather than to
5133 use a multiply instruction. I think this is because the algorithm
5134 synth_mult doesn't take into account the loading of the operands,
5135 whereas the calculation of mult_cost does. */
5144 *total = COSTS_N_INSNS (1);
5148 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
5149 || TARGET_MPYI ? 1 : 14);
5156 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT