1 /* Subroutines for assembler code output on the TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Some output-actions in c4x.md need these. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "basic-block.h"
36 #include "insn-config.h"
37 #include "insn-attr.h"
38 #include "conditions.h"
52 #include "target-def.h"
56 rtx fix_truncqfhi2_libfunc;
57 rtx fixuns_truncqfhi2_libfunc;
58 rtx fix_trunchfhi2_libfunc;
59 rtx fixuns_trunchfhi2_libfunc;
60 rtx floathiqf2_libfunc;
61 rtx floatunshiqf2_libfunc;
62 rtx floathihf2_libfunc;
63 rtx floatunshihf2_libfunc;
65 static int c4x_leaf_function;
67 static const char *const float_reg_names[] = FLOAT_REGISTER_NAMES;
69 /* Array of the smallest class containing reg number REGNO, indexed by
70 REGNO. Used by REGNO_REG_CLASS in c4x.h. We assume that all these
71 registers are available and set the class to NO_REGS for registers
72 that the target switches say are unavailable. */
74 enum reg_class c4x_regclass_map[FIRST_PSEUDO_REGISTER] =
76 /* Reg Modes Saved. */
77 R0R1_REGS, /* R0 QI, QF, HF No. */
78 R0R1_REGS, /* R1 QI, QF, HF No. */
79 R2R3_REGS, /* R2 QI, QF, HF No. */
80 R2R3_REGS, /* R3 QI, QF, HF No. */
81 EXT_LOW_REGS, /* R4 QI, QF, HF QI. */
82 EXT_LOW_REGS, /* R5 QI, QF, HF QI. */
83 EXT_LOW_REGS, /* R6 QI, QF, HF QF. */
84 EXT_LOW_REGS, /* R7 QI, QF, HF QF. */
85 ADDR_REGS, /* AR0 QI No. */
86 ADDR_REGS, /* AR1 QI No. */
87 ADDR_REGS, /* AR2 QI No. */
88 ADDR_REGS, /* AR3 QI QI. */
89 ADDR_REGS, /* AR4 QI QI. */
90 ADDR_REGS, /* AR5 QI QI. */
91 ADDR_REGS, /* AR6 QI QI. */
92 ADDR_REGS, /* AR7 QI QI. */
93 DP_REG, /* DP QI No. */
94 INDEX_REGS, /* IR0 QI No. */
95 INDEX_REGS, /* IR1 QI No. */
96 BK_REG, /* BK QI QI. */
97 SP_REG, /* SP QI No. */
98 ST_REG, /* ST CC No. */
99 NO_REGS, /* DIE/IE No. */
100 NO_REGS, /* IIE/IF No. */
101 NO_REGS, /* IIF/IOF No. */
102 INT_REGS, /* RS QI No. */
103 INT_REGS, /* RE QI No. */
104 RC_REG, /* RC QI No. */
105 EXT_REGS, /* R8 QI, QF, HF QI. */
106 EXT_REGS, /* R9 QI, QF, HF No. */
107 EXT_REGS, /* R10 QI, QF, HF No. */
108 EXT_REGS, /* R11 QI, QF, HF No. */
111 enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
113 /* Reg Modes Saved. */
114 HFmode, /* R0 QI, QF, HF No. */
115 HFmode, /* R1 QI, QF, HF No. */
116 HFmode, /* R2 QI, QF, HF No. */
117 HFmode, /* R3 QI, QF, HF No. */
118 QFmode, /* R4 QI, QF, HF QI. */
119 QFmode, /* R5 QI, QF, HF QI. */
120 QImode, /* R6 QI, QF, HF QF. */
121 QImode, /* R7 QI, QF, HF QF. */
122 QImode, /* AR0 QI No. */
123 QImode, /* AR1 QI No. */
124 QImode, /* AR2 QI No. */
125 QImode, /* AR3 QI QI. */
126 QImode, /* AR4 QI QI. */
127 QImode, /* AR5 QI QI. */
128 QImode, /* AR6 QI QI. */
129 QImode, /* AR7 QI QI. */
130 VOIDmode, /* DP QI No. */
131 QImode, /* IR0 QI No. */
132 QImode, /* IR1 QI No. */
133 QImode, /* BK QI QI. */
134 VOIDmode, /* SP QI No. */
135 VOIDmode, /* ST CC No. */
136 VOIDmode, /* DIE/IE No. */
137 VOIDmode, /* IIE/IF No. */
138 VOIDmode, /* IIF/IOF No. */
139 QImode, /* RS QI No. */
140 QImode, /* RE QI No. */
141 VOIDmode, /* RC QI No. */
142 QFmode, /* R8 QI, QF, HF QI. */
143 HFmode, /* R9 QI, QF, HF No. */
144 HFmode, /* R10 QI, QF, HF No. */
145 HFmode, /* R11 QI, QF, HF No. */
149 /* Test and compare insns in c4x.md store the information needed to
150 generate branch and scc insns here. */
155 const char *c4x_rpts_cycles_string;
156 int c4x_rpts_cycles = 0; /* Max. cycles for RPTS. */
157 const char *c4x_cpu_version_string;
158 int c4x_cpu_version = 40; /* CPU version C30/31/32/33/40/44. */
160 /* Pragma definitions. */
162 tree code_tree = NULL_TREE;
163 tree data_tree = NULL_TREE;
164 tree pure_tree = NULL_TREE;
165 tree noreturn_tree = NULL_TREE;
166 tree interrupt_tree = NULL_TREE;
167 tree naked_tree = NULL_TREE;
169 /* Forward declarations */
170 static int c4x_isr_reg_used_p (unsigned int);
171 static int c4x_leaf_function_p (void);
172 static int c4x_naked_function_p (void);
173 static int c4x_immed_float_p (rtx);
174 static int c4x_a_register (rtx);
175 static int c4x_x_register (rtx);
176 static int c4x_immed_int_constant (rtx);
177 static int c4x_immed_float_constant (rtx);
178 static int c4x_K_constant (rtx);
179 static int c4x_N_constant (rtx);
180 static int c4x_O_constant (rtx);
181 static int c4x_R_indirect (rtx);
182 static int c4x_S_indirect (rtx);
183 static void c4x_S_address_parse (rtx , int *, int *, int *, int *);
184 static int c4x_valid_operands (enum rtx_code, rtx *, enum machine_mode, int);
185 static int c4x_arn_reg_operand (rtx, enum machine_mode, unsigned int);
186 static int c4x_arn_mem_operand (rtx, enum machine_mode, unsigned int);
187 static void c4x_file_start (void);
188 static void c4x_file_end (void);
189 static void c4x_check_attribute (const char *, tree, tree, tree *);
190 static int c4x_r11_set_p (rtx);
191 static int c4x_rptb_valid_p (rtx, rtx);
192 static void c4x_reorg (void);
193 static int c4x_label_ref_used_p (rtx, rtx);
194 static tree c4x_handle_fntype_attribute (tree *, tree, tree, int, bool *);
195 const struct attribute_spec c4x_attribute_table[];
196 static void c4x_insert_attributes (tree, tree *);
197 static void c4x_asm_named_section (const char *, unsigned int);
198 static int c4x_adjust_cost (rtx, rtx, rtx, int);
199 static void c4x_globalize_label (FILE *, const char *);
200 static bool c4x_rtx_costs (rtx, int, int, int *);
201 static int c4x_address_cost (rtx);
202 static void c4x_init_libfuncs (void);
204 /* Initialize the GCC target structure. */
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\t.word\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP NULL
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP NULL
211 #undef TARGET_ASM_FILE_START
212 #define TARGET_ASM_FILE_START c4x_file_start
213 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
214 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END c4x_file_end
218 #undef TARGET_ATTRIBUTE_TABLE
219 #define TARGET_ATTRIBUTE_TABLE c4x_attribute_table
221 #undef TARGET_INSERT_ATTRIBUTES
222 #define TARGET_INSERT_ATTRIBUTES c4x_insert_attributes
224 #undef TARGET_INIT_BUILTINS
225 #define TARGET_INIT_BUILTINS c4x_init_builtins
227 #undef TARGET_EXPAND_BUILTIN
228 #define TARGET_EXPAND_BUILTIN c4x_expand_builtin
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST c4x_adjust_cost
233 #undef TARGET_ASM_GLOBALIZE_LABEL
234 #define TARGET_ASM_GLOBALIZE_LABEL c4x_globalize_label
236 #undef TARGET_RTX_COSTS
237 #define TARGET_RTX_COSTS c4x_rtx_costs
238 #undef TARGET_ADDRESS_COST
239 #define TARGET_ADDRESS_COST c4x_address_cost
241 #undef TARGET_MACHINE_DEPENDENT_REORG
242 #define TARGET_MACHINE_DEPENDENT_REORG c4x_reorg
244 #undef TARGET_INIT_LIBFUNCS
245 #define TARGET_INIT_LIBFUNCS c4x_init_libfuncs
247 struct gcc_target targetm = TARGET_INITIALIZER;
249 /* Override command line options.
250 Called once after all options have been parsed.
251 Mostly we process the processor
252 type and sometimes adjust other TARGET_ options. */
255 c4x_override_options (void)
257 if (c4x_rpts_cycles_string)
258 c4x_rpts_cycles = atoi (c4x_rpts_cycles_string);
263 c4x_cpu_version = 30;
265 c4x_cpu_version = 31;
267 c4x_cpu_version = 32;
269 c4x_cpu_version = 33;
271 c4x_cpu_version = 40;
273 c4x_cpu_version = 44;
275 c4x_cpu_version = 40;
277 /* -mcpu=xx overrides -m40 etc. */
278 if (c4x_cpu_version_string)
280 const char *p = c4x_cpu_version_string;
282 /* Also allow -mcpu=c30 etc. */
283 if (*p == 'c' || *p == 'C')
285 c4x_cpu_version = atoi (p);
288 target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG |
289 C40_FLAG | C44_FLAG);
291 switch (c4x_cpu_version)
293 case 30: target_flags |= C30_FLAG; break;
294 case 31: target_flags |= C31_FLAG; break;
295 case 32: target_flags |= C32_FLAG; break;
296 case 33: target_flags |= C33_FLAG; break;
297 case 40: target_flags |= C40_FLAG; break;
298 case 44: target_flags |= C44_FLAG; break;
300 warning ("unknown CPU version %d, using 40.\n", c4x_cpu_version);
301 c4x_cpu_version = 40;
302 target_flags |= C40_FLAG;
305 if (TARGET_C30 || TARGET_C31 || TARGET_C32 || TARGET_C33)
306 target_flags |= C3X_FLAG;
308 target_flags &= ~C3X_FLAG;
310 /* Convert foo / 8.0 into foo * 0.125, etc. */
311 set_fast_math_flags (1);
313 /* We should phase out the following at some stage.
314 This provides compatibility with the old -mno-aliases option. */
315 if (! TARGET_ALIASES && ! flag_argument_noalias)
316 flag_argument_noalias = 1;
320 /* This is called before c4x_override_options. */
323 c4x_optimization_options (int level ATTRIBUTE_UNUSED,
324 int size ATTRIBUTE_UNUSED)
326 /* Scheduling before register allocation can screw up global
327 register allocation, especially for functions that use MPY||ADD
328 instructions. The benefit we gain we get by scheduling before
329 register allocation is probably marginal anyhow. */
330 flag_schedule_insns = 0;
334 /* Write an ASCII string. */
336 #define C4X_ASCII_LIMIT 40
339 c4x_output_ascii (FILE *stream, const char *ptr, int len)
341 char sbuf[C4X_ASCII_LIMIT + 1];
342 int s, l, special, first = 1, onlys;
345 fprintf (stream, "\t.byte\t");
347 for (s = l = 0; len > 0; --len, ++ptr)
351 /* Escape " and \ with a \". */
352 special = *ptr == '\"' || *ptr == '\\';
354 /* If printable - add to buff. */
355 if ((! TARGET_TI || ! special) && *ptr >= 0x20 && *ptr < 0x7f)
360 if (s < C4X_ASCII_LIMIT - 1)
375 fprintf (stream, "\"%s\"", sbuf);
377 if (TARGET_TI && l >= 80 && len > 1)
379 fprintf (stream, "\n\t.byte\t");
397 fprintf (stream, "%d", *ptr);
399 if (TARGET_TI && l >= 80 && len > 1)
401 fprintf (stream, "\n\t.byte\t");
412 fprintf (stream, "\"%s\"", sbuf);
415 fputc ('\n', stream);
420 c4x_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
425 case Pmode: /* Pointer (24/32 bits). */
427 case QImode: /* Integer (32 bits). */
428 return IS_INT_REGNO (regno);
430 case QFmode: /* Float, Double (32 bits). */
431 case HFmode: /* Long Double (40 bits). */
432 return IS_EXT_REGNO (regno);
434 case CCmode: /* Condition Codes. */
435 case CC_NOOVmode: /* Condition Codes. */
436 return IS_ST_REGNO (regno);
438 case HImode: /* Long Long (64 bits). */
439 /* We need two registers to store long longs. Note that
440 it is much easier to constrain the first register
441 to start on an even boundary. */
442 return IS_INT_REGNO (regno)
443 && IS_INT_REGNO (regno + 1)
447 return 0; /* We don't support these modes. */
453 /* Return nonzero if REGNO1 can be renamed to REGNO2. */
455 c4x_hard_regno_rename_ok (unsigned int regno1, unsigned int regno2)
457 /* We can not copy call saved registers from mode QI into QF or from
459 if (IS_FLOAT_CALL_SAVED_REGNO (regno1) && IS_INT_CALL_SAVED_REGNO (regno2))
461 if (IS_INT_CALL_SAVED_REGNO (regno1) && IS_FLOAT_CALL_SAVED_REGNO (regno2))
463 /* We cannot copy from an extended (40 bit) register to a standard
464 (32 bit) register because we only set the condition codes for
465 extended registers. */
466 if (IS_EXT_REGNO (regno1) && ! IS_EXT_REGNO (regno2))
468 if (IS_EXT_REGNO (regno2) && ! IS_EXT_REGNO (regno1))
473 /* The TI C3x C compiler register argument runtime model uses 6 registers,
474 AR2, R2, R3, RC, RS, RE.
476 The first two floating point arguments (float, double, long double)
477 that are found scanning from left to right are assigned to R2 and R3.
479 The remaining integer (char, short, int, long) or pointer arguments
480 are assigned to the remaining registers in the order AR2, R2, R3,
481 RC, RS, RE when scanning left to right, except for the last named
482 argument prior to an ellipsis denoting variable number of
483 arguments. We don't have to worry about the latter condition since
484 function.c treats the last named argument as anonymous (unnamed).
486 All arguments that cannot be passed in registers are pushed onto
487 the stack in reverse order (right to left). GCC handles that for us.
489 c4x_init_cumulative_args() is called at the start, so we can parse
490 the args to see how many floating point arguments and how many
491 integer (or pointer) arguments there are. c4x_function_arg() is
492 then called (sometimes repeatedly) for each argument (parsed left
493 to right) to obtain the register to pass the argument in, or zero
494 if the argument is to be passed on the stack. Once the compiler is
495 happy, c4x_function_arg_advance() is called.
497 Don't use R0 to pass arguments in, we use 0 to indicate a stack
500 static const int c4x_int_reglist[3][6] =
502 {AR2_REGNO, R2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO},
503 {AR2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0},
504 {AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
507 static const int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
510 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
511 function whose data type is FNTYPE.
512 For a library call, FNTYPE is 0. */
515 c4x_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname)
517 tree param, next_param;
519 cum->floats = cum->ints = 0;
526 fprintf (stderr, "\nc4x_init_cumulative_args (");
529 tree ret_type = TREE_TYPE (fntype);
531 fprintf (stderr, "fntype code = %s, ret code = %s",
532 tree_code_name[(int) TREE_CODE (fntype)],
533 tree_code_name[(int) TREE_CODE (ret_type)]);
536 fprintf (stderr, "no fntype");
539 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
542 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
544 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
545 param; param = next_param)
549 next_param = TREE_CHAIN (param);
551 type = TREE_VALUE (param);
552 if (type && type != void_type_node)
554 enum machine_mode mode;
556 /* If the last arg doesn't have void type then we have
557 variable arguments. */
561 if ((mode = TYPE_MODE (type)))
563 if (! MUST_PASS_IN_STACK (mode, type))
565 /* Look for float, double, or long double argument. */
566 if (mode == QFmode || mode == HFmode)
568 /* Look for integer, enumeral, boolean, char, or pointer
570 else if (mode == QImode || mode == Pmode)
579 fprintf (stderr, "%s%s, args = %d)\n",
580 cum->prototype ? ", prototype" : "",
581 cum->var ? ", variable args" : "",
586 /* Update the data in CUM to advance over an argument
587 of mode MODE and data type TYPE.
588 (TYPE is null for libcalls where that information may not be available.) */
591 c4x_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
592 tree type, int named)
595 fprintf (stderr, "c4x_function_adv(mode=%s, named=%d)\n\n",
596 GET_MODE_NAME (mode), named);
600 && ! MUST_PASS_IN_STACK (mode, type))
602 /* Look for float, double, or long double argument. */
603 if (mode == QFmode || mode == HFmode)
605 /* Look for integer, enumeral, boolean, char, or pointer argument. */
606 else if (mode == QImode || mode == Pmode)
609 else if (! TARGET_MEMPARM && ! type)
611 /* Handle libcall arguments. */
612 if (mode == QFmode || mode == HFmode)
614 else if (mode == QImode || mode == Pmode)
621 /* Define where to put the arguments to a function. Value is zero to
622 push the argument on the stack, or a hard register in which to
625 MODE is the argument's machine mode.
626 TYPE is the data type of the argument (as a tree).
627 This is null for libcalls where that information may
629 CUM is a variable of type CUMULATIVE_ARGS which gives info about
630 the preceding args and about the function being called.
631 NAMED is nonzero if this argument is a named parameter
632 (otherwise it is an extra parameter matching an ellipsis). */
635 c4x_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
636 tree type, int named)
638 int reg = 0; /* Default to passing argument on stack. */
642 /* We can handle at most 2 floats in R2, R3. */
643 cum->maxfloats = (cum->floats > 2) ? 2 : cum->floats;
645 /* We can handle at most 6 integers minus number of floats passed
647 cum->maxints = (cum->ints > 6 - cum->maxfloats) ?
648 6 - cum->maxfloats : cum->ints;
650 /* If there is no prototype, assume all the arguments are integers. */
651 if (! cum->prototype)
654 cum->ints = cum->floats = 0;
658 /* This marks the last argument. We don't need to pass this through
660 if (type == void_type_node)
666 && ! MUST_PASS_IN_STACK (mode, type))
668 /* Look for float, double, or long double argument. */
669 if (mode == QFmode || mode == HFmode)
671 if (cum->floats < cum->maxfloats)
672 reg = c4x_fp_reglist[cum->floats];
674 /* Look for integer, enumeral, boolean, char, or pointer argument. */
675 else if (mode == QImode || mode == Pmode)
677 if (cum->ints < cum->maxints)
678 reg = c4x_int_reglist[cum->maxfloats][cum->ints];
681 else if (! TARGET_MEMPARM && ! type)
683 /* We could use a different argument calling model for libcalls,
684 since we're only calling functions in libgcc. Thus we could
685 pass arguments for long longs in registers rather than on the
686 stack. In the meantime, use the odd TI format. We make the
687 assumption that we won't have more than two floating point
688 args, six integer args, and that all the arguments are of the
690 if (mode == QFmode || mode == HFmode)
691 reg = c4x_fp_reglist[cum->floats];
692 else if (mode == QImode || mode == Pmode)
693 reg = c4x_int_reglist[0][cum->ints];
698 fprintf (stderr, "c4x_function_arg(mode=%s, named=%d",
699 GET_MODE_NAME (mode), named);
701 fprintf (stderr, ", reg=%s", reg_names[reg]);
703 fprintf (stderr, ", stack");
704 fprintf (stderr, ")\n");
707 return gen_rtx_REG (mode, reg);
712 /* C[34]x arguments grow in weird ways (downwards) that the standard
713 varargs stuff can't handle.. */
715 c4x_va_arg (tree valist, tree type)
719 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
720 build_int_2 (int_size_in_bytes (type), 0));
721 TREE_SIDE_EFFECTS (t) = 1;
723 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
728 c4x_isr_reg_used_p (unsigned int regno)
730 /* Don't save/restore FP or ST, we handle them separately. */
731 if (regno == FRAME_POINTER_REGNUM
732 || IS_ST_REGNO (regno))
735 /* We could be a little smarter abut saving/restoring DP.
736 We'll only save if for the big memory model or if
737 we're paranoid. ;-) */
738 if (IS_DP_REGNO (regno))
739 return ! TARGET_SMALL || TARGET_PARANOID;
741 /* Only save/restore regs in leaf function that are used. */
742 if (c4x_leaf_function)
743 return regs_ever_live[regno] && fixed_regs[regno] == 0;
745 /* Only save/restore regs that are used by the ISR and regs
746 that are likely to be used by functions the ISR calls
747 if they are not fixed. */
748 return IS_EXT_REGNO (regno)
749 || ((regs_ever_live[regno] || call_used_regs[regno])
750 && fixed_regs[regno] == 0);
755 c4x_leaf_function_p (void)
757 /* A leaf function makes no calls, so we only need
758 to save/restore the registers we actually use.
759 For the global variable leaf_function to be set, we need
760 to define LEAF_REGISTERS and all that it entails.
761 Let's check ourselves... */
763 if (lookup_attribute ("leaf_pretend",
764 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
767 /* Use the leaf_pretend attribute at your own risk. This is a hack
768 to speed up ISRs that call a function infrequently where the
769 overhead of saving and restoring the additional registers is not
770 warranted. You must save and restore the additional registers
771 required by the called function. Caveat emptor. Here's enough
774 if (leaf_function_p ())
782 c4x_naked_function_p (void)
786 type = TREE_TYPE (current_function_decl);
787 return lookup_attribute ("naked", TYPE_ATTRIBUTES (type)) != NULL;
792 c4x_interrupt_function_p (void)
794 const char *cfun_name;
795 if (lookup_attribute ("interrupt",
796 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
799 /* Look for TI style c_intnn. */
800 cfun_name = current_function_name ();
801 return cfun_name[0] == 'c'
802 && cfun_name[1] == '_'
803 && cfun_name[2] == 'i'
804 && cfun_name[3] == 'n'
805 && cfun_name[4] == 't'
806 && ISDIGIT (cfun_name[5])
807 && ISDIGIT (cfun_name[6]);
811 c4x_expand_prologue (void)
814 int size = get_frame_size ();
817 /* In functions where ar3 is not used but frame pointers are still
818 specified, frame pointers are not adjusted (if >= -O2) and this
819 is used so it won't needlessly push the frame pointer. */
822 /* For __naked__ function don't build a prologue. */
823 if (c4x_naked_function_p ())
828 /* For __interrupt__ function build specific prologue. */
829 if (c4x_interrupt_function_p ())
831 c4x_leaf_function = c4x_leaf_function_p ();
833 insn = emit_insn (gen_push_st ());
834 RTX_FRAME_RELATED_P (insn) = 1;
837 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
838 RTX_FRAME_RELATED_P (insn) = 1;
839 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
840 gen_rtx_REG (QImode, SP_REGNO)));
841 RTX_FRAME_RELATED_P (insn) = 1;
842 /* We require that an ISR uses fewer than 32768 words of
843 local variables, otherwise we have to go to lots of
844 effort to save a register, load it with the desired size,
845 adjust the stack pointer, and then restore the modified
846 register. Frankly, I think it is a poor ISR that
847 requires more than 32767 words of local temporary
850 error ("ISR %s requires %d words of local vars, max is 32767",
851 current_function_name (), size);
853 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
854 gen_rtx_REG (QImode, SP_REGNO),
856 RTX_FRAME_RELATED_P (insn) = 1;
858 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
860 if (c4x_isr_reg_used_p (regno))
862 if (regno == DP_REGNO)
864 insn = emit_insn (gen_push_dp ());
865 RTX_FRAME_RELATED_P (insn) = 1;
869 insn = emit_insn (gen_pushqi (gen_rtx_REG (QImode, regno)));
870 RTX_FRAME_RELATED_P (insn) = 1;
871 if (IS_EXT_REGNO (regno))
873 insn = emit_insn (gen_pushqf
874 (gen_rtx_REG (QFmode, regno)));
875 RTX_FRAME_RELATED_P (insn) = 1;
880 /* We need to clear the repeat mode flag if the ISR is
881 going to use a RPTB instruction or uses the RC, RS, or RE
883 if (regs_ever_live[RC_REGNO]
884 || regs_ever_live[RS_REGNO]
885 || regs_ever_live[RE_REGNO])
887 insn = emit_insn (gen_andn_st (GEN_INT(~0x100)));
888 RTX_FRAME_RELATED_P (insn) = 1;
891 /* Reload DP reg if we are paranoid about some turkey
892 violating small memory model rules. */
893 if (TARGET_SMALL && TARGET_PARANOID)
895 insn = emit_insn (gen_set_ldp_prologue
896 (gen_rtx_REG (QImode, DP_REGNO),
897 gen_rtx_SYMBOL_REF (QImode, "data_sec")));
898 RTX_FRAME_RELATED_P (insn) = 1;
903 if (frame_pointer_needed)
906 || (current_function_args_size != 0)
909 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
910 RTX_FRAME_RELATED_P (insn) = 1;
911 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
912 gen_rtx_REG (QImode, SP_REGNO)));
913 RTX_FRAME_RELATED_P (insn) = 1;
918 /* Since ar3 is not used, we don't need to push it. */
924 /* If we use ar3, we need to push it. */
926 if ((size != 0) || (current_function_args_size != 0))
928 /* If we are omitting the frame pointer, we still have
929 to make space for it so the offsets are correct
930 unless we don't use anything on the stack at all. */
937 /* Local vars are too big, it will take multiple operations
941 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
942 GEN_INT(size >> 16)));
943 RTX_FRAME_RELATED_P (insn) = 1;
944 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R1_REGNO),
945 gen_rtx_REG (QImode, R1_REGNO),
947 RTX_FRAME_RELATED_P (insn) = 1;
951 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
952 GEN_INT(size & ~0xffff)));
953 RTX_FRAME_RELATED_P (insn) = 1;
955 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R1_REGNO),
956 gen_rtx_REG (QImode, R1_REGNO),
957 GEN_INT(size & 0xffff)));
958 RTX_FRAME_RELATED_P (insn) = 1;
959 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
960 gen_rtx_REG (QImode, SP_REGNO),
961 gen_rtx_REG (QImode, R1_REGNO)));
962 RTX_FRAME_RELATED_P (insn) = 1;
966 /* Local vars take up less than 32767 words, so we can directly
968 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
969 gen_rtx_REG (QImode, SP_REGNO),
971 RTX_FRAME_RELATED_P (insn) = 1;
974 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
976 if (regs_ever_live[regno] && ! call_used_regs[regno])
978 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
980 if (TARGET_PRESERVE_FLOAT)
982 insn = emit_insn (gen_pushqi
983 (gen_rtx_REG (QImode, regno)));
984 RTX_FRAME_RELATED_P (insn) = 1;
986 insn = emit_insn (gen_pushqf (gen_rtx_REG (QFmode, regno)));
987 RTX_FRAME_RELATED_P (insn) = 1;
989 else if ((! dont_push_ar3) || (regno != AR3_REGNO))
991 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, regno)));
992 RTX_FRAME_RELATED_P (insn) = 1;
1001 c4x_expand_epilogue(void)
1007 int size = get_frame_size ();
1009 /* For __naked__ function build no epilogue. */
1010 if (c4x_naked_function_p ())
1012 insn = emit_jump_insn (gen_return_from_epilogue ());
1013 RTX_FRAME_RELATED_P (insn) = 1;
1017 /* For __interrupt__ function build specific epilogue. */
1018 if (c4x_interrupt_function_p ())
1020 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
1022 if (! c4x_isr_reg_used_p (regno))
1024 if (regno == DP_REGNO)
1026 insn = emit_insn (gen_pop_dp ());
1027 RTX_FRAME_RELATED_P (insn) = 1;
1031 /* We have to use unspec because the compiler will delete insns
1032 that are not call-saved. */
1033 if (IS_EXT_REGNO (regno))
1035 insn = emit_insn (gen_popqf_unspec
1036 (gen_rtx_REG (QFmode, regno)));
1037 RTX_FRAME_RELATED_P (insn) = 1;
1039 insn = emit_insn (gen_popqi_unspec (gen_rtx_REG (QImode, regno)));
1040 RTX_FRAME_RELATED_P (insn) = 1;
1045 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1046 gen_rtx_REG (QImode, SP_REGNO),
1048 RTX_FRAME_RELATED_P (insn) = 1;
1049 insn = emit_insn (gen_popqi
1050 (gen_rtx_REG (QImode, AR3_REGNO)));
1051 RTX_FRAME_RELATED_P (insn) = 1;
1053 insn = emit_insn (gen_pop_st ());
1054 RTX_FRAME_RELATED_P (insn) = 1;
1055 insn = emit_jump_insn (gen_return_from_interrupt_epilogue ());
1056 RTX_FRAME_RELATED_P (insn) = 1;
1060 if (frame_pointer_needed)
1063 || (current_function_args_size != 0)
1067 (gen_movqi (gen_rtx_REG (QImode, R2_REGNO),
1068 gen_rtx_MEM (QImode,
1070 (QImode, gen_rtx_REG (QImode,
1073 RTX_FRAME_RELATED_P (insn) = 1;
1075 /* We already have the return value and the fp,
1076 so we need to add those to the stack. */
1083 /* Since ar3 is not used for anything, we don't need to
1090 dont_pop_ar3 = 0; /* If we use ar3, we need to pop it. */
1091 if (size || current_function_args_size)
1093 /* If we are omitting the frame pointer, we still have
1094 to make space for it so the offsets are correct
1095 unless we don't use anything on the stack at all. */
1100 /* Now restore the saved registers, putting in the delayed branch
1102 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1104 if (regs_ever_live[regno] && ! call_used_regs[regno])
1106 if (regno == AR3_REGNO && dont_pop_ar3)
1109 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
1111 insn = emit_insn (gen_popqf_unspec
1112 (gen_rtx_REG (QFmode, regno)));
1113 RTX_FRAME_RELATED_P (insn) = 1;
1114 if (TARGET_PRESERVE_FLOAT)
1116 insn = emit_insn (gen_popqi_unspec
1117 (gen_rtx_REG (QImode, regno)));
1118 RTX_FRAME_RELATED_P (insn) = 1;
1123 insn = emit_insn (gen_popqi (gen_rtx_REG (QImode, regno)));
1124 RTX_FRAME_RELATED_P (insn) = 1;
1129 if (frame_pointer_needed)
1132 || (current_function_args_size != 0)
1135 /* Restore the old FP. */
1138 (gen_rtx_REG (QImode, AR3_REGNO),
1139 gen_rtx_MEM (QImode, gen_rtx_REG (QImode, AR3_REGNO))));
1141 RTX_FRAME_RELATED_P (insn) = 1;
1147 /* Local vars are too big, it will take multiple operations
1151 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1152 GEN_INT(size >> 16)));
1153 RTX_FRAME_RELATED_P (insn) = 1;
1154 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R3_REGNO),
1155 gen_rtx_REG (QImode, R3_REGNO),
1157 RTX_FRAME_RELATED_P (insn) = 1;
1161 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1162 GEN_INT(size & ~0xffff)));
1163 RTX_FRAME_RELATED_P (insn) = 1;
1165 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R3_REGNO),
1166 gen_rtx_REG (QImode, R3_REGNO),
1167 GEN_INT(size & 0xffff)));
1168 RTX_FRAME_RELATED_P (insn) = 1;
1169 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1170 gen_rtx_REG (QImode, SP_REGNO),
1171 gen_rtx_REG (QImode, R3_REGNO)));
1172 RTX_FRAME_RELATED_P (insn) = 1;
1176 /* Local vars take up less than 32768 words, so we can directly
1177 subtract the number. */
1178 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1179 gen_rtx_REG (QImode, SP_REGNO),
1181 RTX_FRAME_RELATED_P (insn) = 1;
1186 insn = emit_jump_insn (gen_return_indirect_internal
1187 (gen_rtx_REG (QImode, R2_REGNO)));
1188 RTX_FRAME_RELATED_P (insn) = 1;
1192 insn = emit_jump_insn (gen_return_from_epilogue ());
1193 RTX_FRAME_RELATED_P (insn) = 1;
1200 c4x_null_epilogue_p (void)
1204 if (reload_completed
1205 && ! c4x_naked_function_p ()
1206 && ! c4x_interrupt_function_p ()
1207 && ! current_function_calls_alloca
1208 && ! current_function_args_size
1210 && ! get_frame_size ())
1212 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1213 if (regs_ever_live[regno] && ! call_used_regs[regno]
1214 && (regno != AR3_REGNO))
1223 c4x_emit_move_sequence (rtx *operands, enum machine_mode mode)
1225 rtx op0 = operands[0];
1226 rtx op1 = operands[1];
1228 if (! reload_in_progress
1231 && ! (stik_const_operand (op1, mode) && ! push_operand (op0, mode)))
1232 op1 = force_reg (mode, op1);
1234 if (GET_CODE (op1) == LO_SUM
1235 && GET_MODE (op1) == Pmode
1236 && dp_reg_operand (XEXP (op1, 0), mode))
1238 /* expand_increment will sometimes create a LO_SUM immediate
1240 op1 = XEXP (op1, 1);
1242 else if (symbolic_address_operand (op1, mode))
1244 if (TARGET_LOAD_ADDRESS)
1246 /* Alias analysis seems to do a better job if we force
1247 constant addresses to memory after reload. */
1248 emit_insn (gen_load_immed_address (op0, op1));
1253 /* Stick symbol or label address into the constant pool. */
1254 op1 = force_const_mem (Pmode, op1);
1257 else if (mode == HFmode && CONSTANT_P (op1) && ! LEGITIMATE_CONSTANT_P (op1))
1259 /* We could be a lot smarter about loading some of these
1261 op1 = force_const_mem (mode, op1);
1264 /* Convert (MEM (SYMREF)) to a (MEM (LO_SUM (REG) (SYMREF)))
1265 and emit associated (HIGH (SYMREF)) if large memory model.
1266 c4x_legitimize_address could be used to do this,
1267 perhaps by calling validize_address. */
1268 if (TARGET_EXPOSE_LDP
1269 && ! (reload_in_progress || reload_completed)
1270 && GET_CODE (op1) == MEM
1271 && symbolic_address_operand (XEXP (op1, 0), Pmode))
1273 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1275 emit_insn (gen_set_ldp (dp_reg, XEXP (op1, 0)));
1276 op1 = change_address (op1, mode,
1277 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op1, 0)));
1280 if (TARGET_EXPOSE_LDP
1281 && ! (reload_in_progress || reload_completed)
1282 && GET_CODE (op0) == MEM
1283 && symbolic_address_operand (XEXP (op0, 0), Pmode))
1285 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1287 emit_insn (gen_set_ldp (dp_reg, XEXP (op0, 0)));
1288 op0 = change_address (op0, mode,
1289 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op0, 0)));
1292 if (GET_CODE (op0) == SUBREG
1293 && mixed_subreg_operand (op0, mode))
1295 /* We should only generate these mixed mode patterns
1296 during RTL generation. If we need do it later on
1297 then we'll have to emit patterns that won't clobber CC. */
1298 if (reload_in_progress || reload_completed)
1300 if (GET_MODE (SUBREG_REG (op0)) == QImode)
1301 op0 = SUBREG_REG (op0);
1302 else if (GET_MODE (SUBREG_REG (op0)) == HImode)
1304 op0 = copy_rtx (op0);
1305 PUT_MODE (op0, QImode);
1311 emit_insn (gen_storeqf_int_clobber (op0, op1));
1317 if (GET_CODE (op1) == SUBREG
1318 && mixed_subreg_operand (op1, mode))
1320 /* We should only generate these mixed mode patterns
1321 during RTL generation. If we need do it later on
1322 then we'll have to emit patterns that won't clobber CC. */
1323 if (reload_in_progress || reload_completed)
1325 if (GET_MODE (SUBREG_REG (op1)) == QImode)
1326 op1 = SUBREG_REG (op1);
1327 else if (GET_MODE (SUBREG_REG (op1)) == HImode)
1329 op1 = copy_rtx (op1);
1330 PUT_MODE (op1, QImode);
1336 emit_insn (gen_loadqf_int_clobber (op0, op1));
1343 && reg_operand (op0, mode)
1344 && const_int_operand (op1, mode)
1345 && ! IS_INT16_CONST (INTVAL (op1))
1346 && ! IS_HIGH_CONST (INTVAL (op1)))
1348 emit_insn (gen_loadqi_big_constant (op0, op1));
1353 && reg_operand (op0, mode)
1354 && const_int_operand (op1, mode))
1356 emit_insn (gen_loadhi_big_constant (op0, op1));
1360 /* Adjust operands in case we have modified them. */
1364 /* Emit normal pattern. */
1370 c4x_emit_libcall (rtx libcall, enum rtx_code code,
1371 enum machine_mode dmode, enum machine_mode smode,
1372 int noperands, rtx *operands)
1382 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 1,
1383 operands[1], smode);
1384 equiv = gen_rtx (code, dmode, operands[1]);
1388 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 2,
1389 operands[1], smode, operands[2], smode);
1390 equiv = gen_rtx (code, dmode, operands[1], operands[2]);
1397 insns = get_insns ();
1399 emit_libcall_block (insns, operands[0], ret, equiv);
1404 c4x_emit_libcall3 (rtx libcall, enum rtx_code code,
1405 enum machine_mode mode, rtx *operands)
1407 c4x_emit_libcall (libcall, code, mode, mode, 3, operands);
1412 c4x_emit_libcall_mulhi (rtx libcall, enum rtx_code code,
1413 enum machine_mode mode, rtx *operands)
1420 ret = emit_library_call_value (libcall, NULL_RTX, 1, mode, 2,
1421 operands[1], mode, operands[2], mode);
1422 equiv = gen_rtx_TRUNCATE (mode,
1423 gen_rtx_LSHIFTRT (HImode,
1424 gen_rtx_MULT (HImode,
1425 gen_rtx (code, HImode, operands[1]),
1426 gen_rtx (code, HImode, operands[2])),
1428 insns = get_insns ();
1430 emit_libcall_block (insns, operands[0], ret, equiv);
1435 c4x_legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
1437 rtx base = NULL_RTX; /* Base register (AR0-AR7). */
1438 rtx indx = NULL_RTX; /* Index register (IR0,IR1). */
1439 rtx disp = NULL_RTX; /* Displacement. */
1442 code = GET_CODE (addr);
1445 /* Register indirect with auto increment/decrement. We don't
1446 allow SP here---push_operand should recognize an operand
1447 being pushed on the stack. */
1452 if (mode != QImode && mode != QFmode)
1456 base = XEXP (addr, 0);
1464 rtx op0 = XEXP (addr, 0);
1465 rtx op1 = XEXP (addr, 1);
1467 if (mode != QImode && mode != QFmode)
1471 || (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS))
1473 base = XEXP (op1, 0);
1476 if (REGNO (base) != REGNO (op0))
1478 if (REG_P (XEXP (op1, 1)))
1479 indx = XEXP (op1, 1);
1481 disp = XEXP (op1, 1);
1485 /* Register indirect. */
1490 /* Register indirect with displacement or index. */
1493 rtx op0 = XEXP (addr, 0);
1494 rtx op1 = XEXP (addr, 1);
1495 enum rtx_code code0 = GET_CODE (op0);
1502 base = op0; /* Base + index. */
1504 if (IS_INDEX_REG (base) || IS_ADDR_REG (indx))
1512 base = op0; /* Base + displacement. */
1523 /* Direct addressing with DP register. */
1526 rtx op0 = XEXP (addr, 0);
1527 rtx op1 = XEXP (addr, 1);
1529 /* HImode and HFmode direct memory references aren't truly
1530 offsettable (consider case at end of data page). We
1531 probably get better code by loading a pointer and using an
1532 indirect memory reference. */
1533 if (mode == HImode || mode == HFmode)
1536 if (!REG_P (op0) || REGNO (op0) != DP_REGNO)
1539 if ((GET_CODE (op1) == SYMBOL_REF || GET_CODE (op1) == LABEL_REF))
1542 if (GET_CODE (op1) == CONST)
1548 /* Direct addressing with some work for the assembler... */
1550 /* Direct addressing. */
1553 if (! TARGET_EXPOSE_LDP && ! strict && mode != HFmode && mode != HImode)
1555 /* These need to be converted to a LO_SUM (...).
1556 LEGITIMIZE_RELOAD_ADDRESS will do this during reload. */
1559 /* Do not allow direct memory access to absolute addresses.
1560 This is more pain than it's worth, especially for the
1561 small memory model where we can't guarantee that
1562 this address is within the data page---we don't want
1563 to modify the DP register in the small memory model,
1564 even temporarily, since an interrupt can sneak in.... */
1568 /* Indirect indirect addressing. */
1573 fatal_insn ("using CONST_DOUBLE for address", addr);
1579 /* Validate the base register. */
1582 /* Check that the address is offsettable for HImode and HFmode. */
1583 if (indx && (mode == HImode || mode == HFmode))
1586 /* Handle DP based stuff. */
1587 if (REGNO (base) == DP_REGNO)
1589 if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
1591 else if (! strict && ! IS_ADDR_OR_PSEUDO_REG (base))
1595 /* Now validate the index register. */
1598 if (GET_CODE (indx) != REG)
1600 if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
1602 else if (! strict && ! IS_INDEX_OR_PSEUDO_REG (indx))
1606 /* Validate displacement. */
1609 if (GET_CODE (disp) != CONST_INT)
1611 if (mode == HImode || mode == HFmode)
1613 /* The offset displacement must be legitimate. */
1614 if (! IS_DISP8_OFF_CONST (INTVAL (disp)))
1619 if (! IS_DISP8_CONST (INTVAL (disp)))
1622 /* Can't add an index with a disp. */
1631 c4x_legitimize_address (rtx orig ATTRIBUTE_UNUSED,
1632 enum machine_mode mode ATTRIBUTE_UNUSED)
1634 if (GET_CODE (orig) == SYMBOL_REF
1635 || GET_CODE (orig) == LABEL_REF)
1637 if (mode == HImode || mode == HFmode)
1639 /* We need to force the address into
1640 a register so that it is offsettable. */
1641 rtx addr_reg = gen_reg_rtx (Pmode);
1642 emit_move_insn (addr_reg, orig);
1647 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1650 emit_insn (gen_set_ldp (dp_reg, orig));
1652 return gen_rtx_LO_SUM (Pmode, dp_reg, orig);
1660 /* Provide the costs of an addressing mode that contains ADDR.
1661 If ADDR is not a valid address, its cost is irrelevant.
1662 This is used in cse and loop optimization to determine
1663 if it is worthwhile storing a common address into a register.
1664 Unfortunately, the C4x address cost depends on other operands. */
1667 c4x_address_cost (rtx addr)
1669 switch (GET_CODE (addr))
1680 /* These shouldn't be directly generated. */
1688 rtx op1 = XEXP (addr, 1);
1690 if (GET_CODE (op1) == LABEL_REF || GET_CODE (op1) == SYMBOL_REF)
1691 return TARGET_SMALL ? 3 : 4;
1693 if (GET_CODE (op1) == CONST)
1695 rtx offset = const0_rtx;
1697 op1 = eliminate_constant_term (op1, &offset);
1699 /* ??? These costs need rethinking... */
1700 if (GET_CODE (op1) == LABEL_REF)
1703 if (GET_CODE (op1) != SYMBOL_REF)
1706 if (INTVAL (offset) == 0)
1711 fatal_insn ("c4x_address_cost: Invalid addressing mode", addr);
1717 register rtx op0 = XEXP (addr, 0);
1718 register rtx op1 = XEXP (addr, 1);
1720 if (GET_CODE (op0) != REG)
1723 switch (GET_CODE (op1))
1729 /* This cost for REG+REG must be greater than the cost
1730 for REG if we want autoincrement addressing modes. */
1734 /* The following tries to improve GIV combination
1735 in strength reduce but appears not to help. */
1736 if (TARGET_DEVEL && IS_UINT5_CONST (INTVAL (op1)))
1739 if (IS_DISP1_CONST (INTVAL (op1)))
1742 if (! TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
1757 c4x_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
1759 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1762 if (mode == CC_NOOVmode
1763 && (code == LE || code == GE || code == LT || code == GT))
1766 cc_reg = gen_rtx_REG (mode, ST_REGNO);
1767 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1768 gen_rtx_COMPARE (mode, x, y)));
1773 c4x_output_cbranch (const char *form, rtx seq)
1780 static char str[100];
1784 delay = XVECEXP (final_sequence, 0, 1);
1785 delayed = ! INSN_ANNULLED_BRANCH_P (seq);
1786 annultrue = INSN_ANNULLED_BRANCH_P (seq) && ! INSN_FROM_TARGET_P (delay);
1787 annulfalse = INSN_ANNULLED_BRANCH_P (seq) && INSN_FROM_TARGET_P (delay);
1790 cp = &str [strlen (str)];
1815 c4x_print_operand (FILE *file, rtx op, int letter)
1822 case '#': /* Delayed. */
1824 fprintf (file, "d");
1828 code = GET_CODE (op);
1831 case 'A': /* Direct address. */
1832 if (code == CONST_INT || code == SYMBOL_REF || code == CONST)
1833 fprintf (file, "@");
1836 case 'H': /* Sethi. */
1837 output_addr_const (file, op);
1840 case 'I': /* Reversed condition. */
1841 code = reverse_condition (code);
1844 case 'L': /* Log 2 of constant. */
1845 if (code != CONST_INT)
1846 fatal_insn ("c4x_print_operand: %%L inconsistency", op);
1847 fprintf (file, "%d", exact_log2 (INTVAL (op)));
1850 case 'N': /* Ones complement of small constant. */
1851 if (code != CONST_INT)
1852 fatal_insn ("c4x_print_operand: %%N inconsistency", op);
1853 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (op));
1856 case 'K': /* Generate ldp(k) if direct address. */
1859 && GET_CODE (XEXP (op, 0)) == LO_SUM
1860 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
1861 && REGNO (XEXP (XEXP (op, 0), 0)) == DP_REGNO)
1863 op1 = XEXP (XEXP (op, 0), 1);
1864 if (GET_CODE(op1) == CONST_INT || GET_CODE(op1) == SYMBOL_REF)
1866 fprintf (file, "\t%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1867 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1868 fprintf (file, "\n");
1873 case 'M': /* Generate ldp(k) if direct address. */
1874 if (! TARGET_SMALL /* Only used in asm statements. */
1876 && (GET_CODE (XEXP (op, 0)) == CONST
1877 || GET_CODE (XEXP (op, 0)) == SYMBOL_REF))
1879 fprintf (file, "%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1880 output_address (XEXP (op, 0));
1881 fprintf (file, "\n\t");
1885 case 'O': /* Offset address. */
1886 if (code == MEM && c4x_autoinc_operand (op, Pmode))
1888 else if (code == MEM)
1889 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1890 else if (code == REG)
1891 fprintf (file, "%s", reg_names[REGNO (op) + 1]);
1893 fatal_insn ("c4x_print_operand: %%O inconsistency", op);
1896 case 'C': /* Call. */
1899 case 'U': /* Call/callu. */
1900 if (code != SYMBOL_REF)
1901 fprintf (file, "u");
1911 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
1913 fprintf (file, "%s", float_reg_names[REGNO (op)]);
1915 fprintf (file, "%s", reg_names[REGNO (op)]);
1919 output_address (XEXP (op, 0));
1926 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (op),
1927 sizeof (str), 0, 1);
1928 fprintf (file, "%s", str);
1933 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
1937 fprintf (file, "ne");
1941 fprintf (file, "eq");
1945 fprintf (file, "ge");
1949 fprintf (file, "gt");
1953 fprintf (file, "le");
1957 fprintf (file, "lt");
1961 fprintf (file, "hs");
1965 fprintf (file, "hi");
1969 fprintf (file, "ls");
1973 fprintf (file, "lo");
1977 output_addr_const (file, op);
1981 output_addr_const (file, XEXP (op, 0));
1988 fatal_insn ("c4x_print_operand: Bad operand case", op);
1995 c4x_print_operand_address (FILE *file, rtx addr)
1997 switch (GET_CODE (addr))
2000 fprintf (file, "*%s", reg_names[REGNO (addr)]);
2004 fprintf (file, "*--%s", reg_names[REGNO (XEXP (addr, 0))]);
2008 fprintf (file, "*%s++", reg_names[REGNO (XEXP (addr, 0))]);
2013 rtx op0 = XEXP (XEXP (addr, 1), 0);
2014 rtx op1 = XEXP (XEXP (addr, 1), 1);
2016 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2017 fprintf (file, "*%s++(%s)", reg_names[REGNO (op0)],
2018 reg_names[REGNO (op1)]);
2019 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2020 fprintf (file, "*%s++(" HOST_WIDE_INT_PRINT_DEC ")",
2021 reg_names[REGNO (op0)], INTVAL (op1));
2022 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2023 fprintf (file, "*%s--(" HOST_WIDE_INT_PRINT_DEC ")",
2024 reg_names[REGNO (op0)], -INTVAL (op1));
2025 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2026 fprintf (file, "*%s--(%s)", reg_names[REGNO (op0)],
2027 reg_names[REGNO (op1)]);
2029 fatal_insn ("c4x_print_operand_address: Bad post_modify", addr);
2035 rtx op0 = XEXP (XEXP (addr, 1), 0);
2036 rtx op1 = XEXP (XEXP (addr, 1), 1);
2038 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2039 fprintf (file, "*++%s(%s)", reg_names[REGNO (op0)],
2040 reg_names[REGNO (op1)]);
2041 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2042 fprintf (file, "*++%s(" HOST_WIDE_INT_PRINT_DEC ")",
2043 reg_names[REGNO (op0)], INTVAL (op1));
2044 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2045 fprintf (file, "*--%s(" HOST_WIDE_INT_PRINT_DEC ")",
2046 reg_names[REGNO (op0)], -INTVAL (op1));
2047 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2048 fprintf (file, "*--%s(%s)", reg_names[REGNO (op0)],
2049 reg_names[REGNO (op1)]);
2051 fatal_insn ("c4x_print_operand_address: Bad pre_modify", addr);
2056 fprintf (file, "*++%s", reg_names[REGNO (XEXP (addr, 0))]);
2060 fprintf (file, "*%s--", reg_names[REGNO (XEXP (addr, 0))]);
2063 case PLUS: /* Indirect with displacement. */
2065 rtx op0 = XEXP (addr, 0);
2066 rtx op1 = XEXP (addr, 1);
2072 if (IS_INDEX_REG (op0))
2074 fprintf (file, "*+%s(%s)",
2075 reg_names[REGNO (op1)],
2076 reg_names[REGNO (op0)]); /* Index + base. */
2080 fprintf (file, "*+%s(%s)",
2081 reg_names[REGNO (op0)],
2082 reg_names[REGNO (op1)]); /* Base + index. */
2085 else if (INTVAL (op1) < 0)
2087 fprintf (file, "*-%s(" HOST_WIDE_INT_PRINT_DEC ")",
2088 reg_names[REGNO (op0)],
2089 -INTVAL (op1)); /* Base - displacement. */
2093 fprintf (file, "*+%s(" HOST_WIDE_INT_PRINT_DEC ")",
2094 reg_names[REGNO (op0)],
2095 INTVAL (op1)); /* Base + displacement. */
2099 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2105 rtx op0 = XEXP (addr, 0);
2106 rtx op1 = XEXP (addr, 1);
2108 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
2109 c4x_print_operand_address (file, op1);
2111 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2118 fprintf (file, "@");
2119 output_addr_const (file, addr);
2122 /* We shouldn't access CONST_INT addresses. */
2126 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2132 /* Return nonzero if the floating point operand will fit
2133 in the immediate field. */
2136 c4x_immed_float_p (rtx op)
2142 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2143 if (GET_MODE (op) == HFmode)
2144 REAL_VALUE_TO_TARGET_DOUBLE (r, convval);
2147 REAL_VALUE_TO_TARGET_SINGLE (r, convval[0]);
2151 /* Sign extend exponent. */
2152 exponent = (((convval[0] >> 24) & 0xff) ^ 0x80) - 0x80;
2153 if (exponent == -128)
2155 if ((convval[0] & 0x00000fff) != 0 || convval[1] != 0)
2156 return 0; /* Precision doesn't fit. */
2157 return (exponent <= 7) /* Positive exp. */
2158 && (exponent >= -7); /* Negative exp. */
2162 /* The last instruction in a repeat block cannot be a Bcond, DBcound,
2163 CALL, CALLCond, TRAPcond, RETIcond, RETScond, IDLE, RPTB or RPTS.
2165 None of the last four instructions from the bottom of the block can
2166 be a BcondD, BRD, DBcondD, RPTBD, LAJ, LAJcond, LATcond, BcondAF,
2167 BcondAT or RETIcondD.
2169 This routine scans the four previous insns for a jump insn, and if
2170 one is found, returns 1 so that we bung in a nop instruction.
2171 This simple minded strategy will add a nop, when it may not
2172 be required. Say when there is a JUMP_INSN near the end of the
2173 block that doesn't get converted into a delayed branch.
2175 Note that we cannot have a call insn, since we don't generate
2176 repeat loops with calls in them (although I suppose we could, but
2177 there's no benefit.)
2179 !!! FIXME. The rptb_top insn may be sucked into a SEQUENCE. */
2182 c4x_rptb_nop_p (rtx insn)
2187 /* Extract the start label from the jump pattern (rptb_end). */
2188 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2190 /* If there is a label at the end of the loop we must insert
2193 insn = previous_insn (insn);
2194 } while (GET_CODE (insn) == NOTE
2195 || GET_CODE (insn) == USE
2196 || GET_CODE (insn) == CLOBBER);
2197 if (GET_CODE (insn) == CODE_LABEL)
2200 for (i = 0; i < 4; i++)
2202 /* Search back for prev non-note and non-label insn. */
2203 while (GET_CODE (insn) == NOTE || GET_CODE (insn) == CODE_LABEL
2204 || GET_CODE (insn) == USE || GET_CODE (insn) == CLOBBER)
2206 if (insn == start_label)
2209 insn = previous_insn (insn);
2212 /* If we have a jump instruction we should insert a NOP. If we
2213 hit repeat block top we should only insert a NOP if the loop
2215 if (GET_CODE (insn) == JUMP_INSN)
2217 insn = previous_insn (insn);
2223 /* The C4x looping instruction needs to be emitted at the top of the
2224 loop. Emitting the true RTL for a looping instruction at the top of
2225 the loop can cause problems with flow analysis. So instead, a dummy
2226 doloop insn is emitted at the end of the loop. This routine checks
2227 for the presence of this doloop insn and then searches back to the
2228 top of the loop, where it inserts the true looping insn (provided
2229 there are no instructions in the loop which would cause problems).
2230 Any additional labels can be emitted at this point. In addition, if
2231 the desired loop count register was not allocated, this routine does
2234 Before we can create a repeat block looping instruction we have to
2235 verify that there are no jumps outside the loop and no jumps outside
2236 the loop go into this loop. This can happen in the basic blocks reorder
2237 pass. The C4x cpu can not handle this. */
2240 c4x_label_ref_used_p (rtx x, rtx code_label)
2249 code = GET_CODE (x);
2250 if (code == LABEL_REF)
2251 return INSN_UID (XEXP (x,0)) == INSN_UID (code_label);
2253 fmt = GET_RTX_FORMAT (code);
2254 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2258 if (c4x_label_ref_used_p (XEXP (x, i), code_label))
2261 else if (fmt[i] == 'E')
2262 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2263 if (c4x_label_ref_used_p (XVECEXP (x, i, j), code_label))
2271 c4x_rptb_valid_p (rtx insn, rtx start_label)
2277 /* Find the start label. */
2278 for (; insn; insn = PREV_INSN (insn))
2279 if (insn == start_label)
2282 /* Note found then we can not use a rptb or rpts. The label was
2283 probably moved by the basic block reorder pass. */
2288 /* If any jump jumps inside this block then we must fail. */
2289 for (insn = PREV_INSN (start); insn; insn = PREV_INSN (insn))
2291 if (GET_CODE (insn) == CODE_LABEL)
2293 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2294 if (GET_CODE (tmp) == JUMP_INSN
2295 && c4x_label_ref_used_p (tmp, insn))
2299 for (insn = NEXT_INSN (end); insn; insn = NEXT_INSN (insn))
2301 if (GET_CODE (insn) == CODE_LABEL)
2303 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2304 if (GET_CODE (tmp) == JUMP_INSN
2305 && c4x_label_ref_used_p (tmp, insn))
2309 /* If any jump jumps outside this block then we must fail. */
2310 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
2312 if (GET_CODE (insn) == CODE_LABEL)
2314 for (tmp = NEXT_INSN (end); tmp; tmp = NEXT_INSN(tmp))
2315 if (GET_CODE (tmp) == JUMP_INSN
2316 && c4x_label_ref_used_p (tmp, insn))
2318 for (tmp = PREV_INSN (start); tmp; tmp = PREV_INSN(tmp))
2319 if (GET_CODE (tmp) == JUMP_INSN
2320 && c4x_label_ref_used_p (tmp, insn))
2325 /* All checks OK. */
2331 c4x_rptb_insert (rtx insn)
2335 rtx new_start_label;
2338 /* If the count register has not been allocated to RC, say if
2339 there is a movstr pattern in the loop, then do not insert a
2340 RPTB instruction. Instead we emit a decrement and branch
2341 at the end of the loop. */
2342 count_reg = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0), 0);
2343 if (REGNO (count_reg) != RC_REGNO)
2346 /* Extract the start label from the jump pattern (rptb_end). */
2347 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2349 if (! c4x_rptb_valid_p (insn, start_label))
2351 /* We can not use the rptb insn. Replace it so reorg can use
2352 the delay slots of the jump insn. */
2353 emit_insn_before (gen_addqi3 (count_reg, count_reg, GEN_INT (-1)), insn);
2354 emit_insn_before (gen_cmpqi (count_reg, GEN_INT (0)), insn);
2355 emit_insn_before (gen_bge (start_label), insn);
2356 LABEL_NUSES (start_label)++;
2361 end_label = gen_label_rtx ();
2362 LABEL_NUSES (end_label)++;
2363 emit_label_after (end_label, insn);
2365 new_start_label = gen_label_rtx ();
2366 LABEL_NUSES (new_start_label)++;
2368 for (; insn; insn = PREV_INSN (insn))
2370 if (insn == start_label)
2372 if (GET_CODE (insn) == JUMP_INSN &&
2373 JUMP_LABEL (insn) == start_label)
2374 redirect_jump (insn, new_start_label, 0);
2377 fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
2379 emit_label_after (new_start_label, insn);
2381 if (TARGET_RPTS && c4x_rptb_rpts_p (PREV_INSN (insn), 0))
2382 emit_insn_after (gen_rpts_top (new_start_label, end_label), insn);
2384 emit_insn_after (gen_rptb_top (new_start_label, end_label), insn);
2385 if (LABEL_NUSES (start_label) == 0)
2386 delete_insn (start_label);
2390 /* We need to use direct addressing for large constants and addresses
2391 that cannot fit within an instruction. We must check for these
2392 after after the final jump optimization pass, since this may
2393 introduce a local_move insn for a SYMBOL_REF. This pass
2394 must come before delayed branch slot filling since it can generate
2395 additional instructions.
2397 This function also fixes up RTPB style loops that didn't get RC
2398 allocated as the loop counter. */
2405 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2407 /* Look for insn. */
2410 int insn_code_number;
2413 insn_code_number = recog_memoized (insn);
2415 if (insn_code_number < 0)
2418 /* Insert the RTX for RPTB at the top of the loop
2419 and a label at the end of the loop. */
2420 if (insn_code_number == CODE_FOR_rptb_end)
2421 c4x_rptb_insert(insn);
2423 /* We need to split the insn here. Otherwise the calls to
2424 force_const_mem will not work for load_immed_address. */
2427 /* Don't split the insn if it has been deleted. */
2428 if (! INSN_DELETED_P (old))
2429 insn = try_split (PATTERN(old), old, 1);
2431 /* When not optimizing, the old insn will be still left around
2432 with only the 'deleted' bit set. Transform it into a note
2433 to avoid confusion of subsequent processing. */
2434 if (INSN_DELETED_P (old))
2436 PUT_CODE (old, NOTE);
2437 NOTE_LINE_NUMBER (old) = NOTE_INSN_DELETED;
2438 NOTE_SOURCE_FILE (old) = 0;
2446 c4x_a_register (rtx op)
2448 return REG_P (op) && IS_ADDR_OR_PSEUDO_REG (op);
2453 c4x_x_register (rtx op)
2455 return REG_P (op) && IS_INDEX_OR_PSEUDO_REG (op);
2460 c4x_immed_int_constant (rtx op)
2462 if (GET_CODE (op) != CONST_INT)
2465 return GET_MODE (op) == VOIDmode
2466 || GET_MODE_CLASS (GET_MODE (op)) == MODE_INT
2467 || GET_MODE_CLASS (GET_MODE (op)) == MODE_PARTIAL_INT;
2472 c4x_immed_float_constant (rtx op)
2474 if (GET_CODE (op) != CONST_DOUBLE)
2477 /* Do not check if the CONST_DOUBLE is in memory. If there is a MEM
2478 present this only means that a MEM rtx has been generated. It does
2479 not mean the rtx is really in memory. */
2481 return GET_MODE (op) == QFmode || GET_MODE (op) == HFmode;
2486 c4x_shiftable_constant (rtx op)
2490 int val = INTVAL (op);
2492 for (i = 0; i < 16; i++)
2497 mask = ((0xffff >> i) << 16) | 0xffff;
2498 if (IS_INT16_CONST (val & (1 << 31) ? (val >> i) | ~mask
2499 : (val >> i) & mask))
2506 c4x_H_constant (rtx op)
2508 return c4x_immed_float_constant (op) && c4x_immed_float_p (op);
2513 c4x_I_constant (rtx op)
2515 return c4x_immed_int_constant (op) && IS_INT16_CONST (INTVAL (op));
2520 c4x_J_constant (rtx op)
2524 return c4x_immed_int_constant (op) && IS_INT8_CONST (INTVAL (op));
2529 c4x_K_constant (rtx op)
2531 if (TARGET_C3X || ! c4x_immed_int_constant (op))
2533 return IS_INT5_CONST (INTVAL (op));
2538 c4x_L_constant (rtx op)
2540 return c4x_immed_int_constant (op) && IS_UINT16_CONST (INTVAL (op));
2545 c4x_N_constant (rtx op)
2547 return c4x_immed_int_constant (op) && IS_NOT_UINT16_CONST (INTVAL (op));
2552 c4x_O_constant (rtx op)
2554 return c4x_immed_int_constant (op) && IS_HIGH_CONST (INTVAL (op));
2558 /* The constraints do not have to check the register class,
2559 except when needed to discriminate between the constraints.
2560 The operand has been checked by the predicates to be valid. */
2562 /* ARx + 9-bit signed const or IRn
2563 *ARx, *+ARx(n), *-ARx(n), *+ARx(IRn), *-Arx(IRn) for -256 < n < 256
2564 We don't include the pre/post inc/dec forms here since
2565 they are handled by the <> constraints. */
2568 c4x_Q_constraint (rtx op)
2570 enum machine_mode mode = GET_MODE (op);
2572 if (GET_CODE (op) != MEM)
2575 switch (GET_CODE (op))
2582 rtx op0 = XEXP (op, 0);
2583 rtx op1 = XEXP (op, 1);
2591 if (GET_CODE (op1) != CONST_INT)
2594 /* HImode and HFmode must be offsettable. */
2595 if (mode == HImode || mode == HFmode)
2596 return IS_DISP8_OFF_CONST (INTVAL (op1));
2598 return IS_DISP8_CONST (INTVAL (op1));
2609 /* ARx + 5-bit unsigned const
2610 *ARx, *+ARx(n) for n < 32. */
2613 c4x_R_constraint (rtx op)
2615 enum machine_mode mode = GET_MODE (op);
2619 if (GET_CODE (op) != MEM)
2622 switch (GET_CODE (op))
2629 rtx op0 = XEXP (op, 0);
2630 rtx op1 = XEXP (op, 1);
2635 if (GET_CODE (op1) != CONST_INT)
2638 /* HImode and HFmode must be offsettable. */
2639 if (mode == HImode || mode == HFmode)
2640 return IS_UINT5_CONST (INTVAL (op1) + 1);
2642 return IS_UINT5_CONST (INTVAL (op1));
2654 c4x_R_indirect (rtx op)
2656 enum machine_mode mode = GET_MODE (op);
2658 if (TARGET_C3X || GET_CODE (op) != MEM)
2662 switch (GET_CODE (op))
2665 return IS_ADDR_OR_PSEUDO_REG (op);
2669 rtx op0 = XEXP (op, 0);
2670 rtx op1 = XEXP (op, 1);
2672 /* HImode and HFmode must be offsettable. */
2673 if (mode == HImode || mode == HFmode)
2674 return IS_ADDR_OR_PSEUDO_REG (op0)
2675 && GET_CODE (op1) == CONST_INT
2676 && IS_UINT5_CONST (INTVAL (op1) + 1);
2679 && IS_ADDR_OR_PSEUDO_REG (op0)
2680 && GET_CODE (op1) == CONST_INT
2681 && IS_UINT5_CONST (INTVAL (op1));
2692 /* ARx + 1-bit unsigned const or IRn
2693 *ARx, *+ARx(1), *-ARx(1), *+ARx(IRn), *-Arx(IRn)
2694 We don't include the pre/post inc/dec forms here since
2695 they are handled by the <> constraints. */
2698 c4x_S_constraint (rtx op)
2700 enum machine_mode mode = GET_MODE (op);
2701 if (GET_CODE (op) != MEM)
2704 switch (GET_CODE (op))
2712 rtx op0 = XEXP (op, 0);
2713 rtx op1 = XEXP (op, 1);
2715 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2716 || (op0 != XEXP (op1, 0)))
2719 op0 = XEXP (op1, 0);
2720 op1 = XEXP (op1, 1);
2721 return REG_P (op0) && REG_P (op1);
2722 /* Pre or post_modify with a displacement of 0 or 1
2723 should not be generated. */
2729 rtx op0 = XEXP (op, 0);
2730 rtx op1 = XEXP (op, 1);
2738 if (GET_CODE (op1) != CONST_INT)
2741 /* HImode and HFmode must be offsettable. */
2742 if (mode == HImode || mode == HFmode)
2743 return IS_DISP1_OFF_CONST (INTVAL (op1));
2745 return IS_DISP1_CONST (INTVAL (op1));
2757 c4x_S_indirect (rtx op)
2759 enum machine_mode mode = GET_MODE (op);
2760 if (GET_CODE (op) != MEM)
2764 switch (GET_CODE (op))
2768 if (mode != QImode && mode != QFmode)
2775 return IS_ADDR_OR_PSEUDO_REG (op);
2780 rtx op0 = XEXP (op, 0);
2781 rtx op1 = XEXP (op, 1);
2783 if (mode != QImode && mode != QFmode)
2786 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2787 || (op0 != XEXP (op1, 0)))
2790 op0 = XEXP (op1, 0);
2791 op1 = XEXP (op1, 1);
2792 return REG_P (op0) && IS_ADDR_OR_PSEUDO_REG (op0)
2793 && REG_P (op1) && IS_INDEX_OR_PSEUDO_REG (op1);
2794 /* Pre or post_modify with a displacement of 0 or 1
2795 should not be generated. */
2800 rtx op0 = XEXP (op, 0);
2801 rtx op1 = XEXP (op, 1);
2805 /* HImode and HFmode must be offsettable. */
2806 if (mode == HImode || mode == HFmode)
2807 return IS_ADDR_OR_PSEUDO_REG (op0)
2808 && GET_CODE (op1) == CONST_INT
2809 && IS_DISP1_OFF_CONST (INTVAL (op1));
2812 return (IS_INDEX_OR_PSEUDO_REG (op1)
2813 && IS_ADDR_OR_PSEUDO_REG (op0))
2814 || (IS_ADDR_OR_PSEUDO_REG (op1)
2815 && IS_INDEX_OR_PSEUDO_REG (op0));
2817 return IS_ADDR_OR_PSEUDO_REG (op0)
2818 && GET_CODE (op1) == CONST_INT
2819 && IS_DISP1_CONST (INTVAL (op1));
2831 /* Direct memory operand. */
2834 c4x_T_constraint (rtx op)
2836 if (GET_CODE (op) != MEM)
2840 if (GET_CODE (op) != LO_SUM)
2842 /* Allow call operands. */
2843 return GET_CODE (op) == SYMBOL_REF
2844 && GET_MODE (op) == Pmode
2845 && SYMBOL_REF_FUNCTION_P (op);
2848 /* HImode and HFmode are not offsettable. */
2849 if (GET_MODE (op) == HImode || GET_CODE (op) == HFmode)
2852 if ((GET_CODE (XEXP (op, 0)) == REG)
2853 && (REGNO (XEXP (op, 0)) == DP_REGNO))
2854 return c4x_U_constraint (XEXP (op, 1));
2860 /* Symbolic operand. */
2863 c4x_U_constraint (rtx op)
2865 /* Don't allow direct addressing to an arbitrary constant. */
2866 return GET_CODE (op) == CONST
2867 || GET_CODE (op) == SYMBOL_REF
2868 || GET_CODE (op) == LABEL_REF;
2873 c4x_autoinc_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2875 if (GET_CODE (op) == MEM)
2877 enum rtx_code code = GET_CODE (XEXP (op, 0));
2883 || code == PRE_MODIFY
2884 || code == POST_MODIFY
2892 /* Match any operand. */
2895 any_operand (register rtx op ATTRIBUTE_UNUSED,
2896 enum machine_mode mode ATTRIBUTE_UNUSED)
2902 /* Nonzero if OP is a floating point value with value 0.0. */
2905 fp_zero_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2909 if (GET_CODE (op) != CONST_DOUBLE)
2911 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2912 return REAL_VALUES_EQUAL (r, dconst0);
2917 const_operand (register rtx op, register enum machine_mode mode)
2923 if (GET_CODE (op) != CONST_DOUBLE
2924 || GET_MODE (op) != mode
2925 || GET_MODE_CLASS (mode) != MODE_FLOAT)
2928 return c4x_immed_float_p (op);
2934 if (GET_CODE (op) == CONSTANT_P_RTX)
2937 if (GET_CODE (op) != CONST_INT
2938 || (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
2939 || GET_MODE_CLASS (mode) != MODE_INT)
2942 return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
2954 stik_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2956 return c4x_K_constant (op);
2961 not_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2963 return c4x_N_constant (op);
2968 reg_operand (rtx op, enum machine_mode mode)
2970 if (GET_CODE (op) == SUBREG
2971 && GET_MODE (op) == QFmode)
2973 return register_operand (op, mode);
2978 mixed_subreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2980 /* Allow (subreg:HF (reg:HI)) that be generated for a union of an
2981 int and a long double. */
2982 if (GET_CODE (op) == SUBREG
2983 && (GET_MODE (op) == QFmode)
2984 && (GET_MODE (SUBREG_REG (op)) == QImode
2985 || GET_MODE (SUBREG_REG (op)) == HImode))
2992 reg_imm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2994 if (REG_P (op) || CONSTANT_P (op))
3001 not_modify_reg (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3003 if (REG_P (op) || CONSTANT_P (op))
3005 if (GET_CODE (op) != MEM)
3008 switch (GET_CODE (op))
3015 rtx op0 = XEXP (op, 0);
3016 rtx op1 = XEXP (op, 1);
3021 if (REG_P (op1) || GET_CODE (op1) == CONST_INT)
3027 rtx op0 = XEXP (op, 0);
3029 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
3047 not_rc_reg (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3049 if (REG_P (op) && REGNO (op) == RC_REGNO)
3055 /* Extended precision register R0-R1. */
3058 r0r1_reg_operand (rtx op, enum machine_mode mode)
3060 if (! reg_operand (op, mode))
3062 if (GET_CODE (op) == SUBREG)
3063 op = SUBREG_REG (op);
3064 return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
3068 /* Extended precision register R2-R3. */
3071 r2r3_reg_operand (rtx op, enum machine_mode mode)
3073 if (! reg_operand (op, mode))
3075 if (GET_CODE (op) == SUBREG)
3076 op = SUBREG_REG (op);
3077 return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
3081 /* Low extended precision register R0-R7. */
3084 ext_low_reg_operand (rtx op, enum machine_mode mode)
3086 if (! reg_operand (op, mode))
3088 if (GET_CODE (op) == SUBREG)
3089 op = SUBREG_REG (op);
3090 return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
3094 /* Extended precision register. */
3097 ext_reg_operand (rtx op, enum machine_mode mode)
3099 if (! reg_operand (op, mode))
3101 if (GET_CODE (op) == SUBREG)
3102 op = SUBREG_REG (op);
3105 return IS_EXT_OR_PSEUDO_REG (op);
3109 /* Standard precision register. */
3112 std_reg_operand (rtx op, enum machine_mode mode)
3114 if (! reg_operand (op, mode))
3116 if (GET_CODE (op) == SUBREG)
3117 op = SUBREG_REG (op);
3118 return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
3121 /* Standard precision or normal register. */
3124 std_or_reg_operand (rtx op, enum machine_mode mode)
3126 if (reload_in_progress)
3127 return std_reg_operand (op, mode);
3128 return reg_operand (op, mode);
3131 /* Address register. */
3134 addr_reg_operand (rtx op, enum machine_mode mode)
3136 if (! reg_operand (op, mode))
3138 return c4x_a_register (op);
3142 /* Index register. */
3145 index_reg_operand (rtx op, enum machine_mode mode)
3147 if (! reg_operand (op, mode))
3149 if (GET_CODE (op) == SUBREG)
3150 op = SUBREG_REG (op);
3151 return c4x_x_register (op);
3158 dp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3160 return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
3167 sp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3169 return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
3176 st_reg_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3178 return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
3185 rc_reg_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3187 return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
3192 call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3194 return (REG_P (op) || symbolic_address_operand (op, mode));
3198 /* Symbolic address operand. */
3201 symbolic_address_operand (register rtx op,
3202 enum machine_mode mode ATTRIBUTE_UNUSED)
3204 switch (GET_CODE (op))
3216 /* Check dst operand of a move instruction. */
3219 dst_operand (rtx op, enum machine_mode mode)
3221 if (GET_CODE (op) == SUBREG
3222 && mixed_subreg_operand (op, mode))
3226 return reg_operand (op, mode);
3228 return nonimmediate_operand (op, mode);
3232 /* Check src operand of two operand arithmetic instructions. */
3235 src_operand (rtx op, enum machine_mode mode)
3237 if (GET_CODE (op) == SUBREG
3238 && mixed_subreg_operand (op, mode))
3242 return reg_operand (op, mode);
3244 if (mode == VOIDmode)
3245 mode = GET_MODE (op);
3247 if (GET_CODE (op) == CONST_INT)
3248 return (mode == QImode || mode == Pmode || mode == HImode)
3249 && c4x_I_constant (op);
3251 /* We don't like CONST_DOUBLE integers. */
3252 if (GET_CODE (op) == CONST_DOUBLE)
3253 return c4x_H_constant (op);
3255 /* Disallow symbolic addresses. Only the predicate
3256 symbolic_address_operand will match these. */
3257 if (GET_CODE (op) == SYMBOL_REF
3258 || GET_CODE (op) == LABEL_REF
3259 || GET_CODE (op) == CONST)
3262 /* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
3263 access to symbolic addresses. These operands will get forced
3264 into a register and the movqi expander will generate a
3265 HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
3266 if (GET_CODE (op) == MEM
3267 && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3268 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3269 || GET_CODE (XEXP (op, 0)) == CONST)))
3270 return ! TARGET_LOAD_DIRECT_MEMS && GET_MODE (op) == mode;
3272 return general_operand (op, mode);
3277 src_hi_operand (rtx op, enum machine_mode mode)
3279 if (c4x_O_constant (op))
3281 return src_operand (op, mode);
3285 /* Check src operand of two operand logical instructions. */
3288 lsrc_operand (rtx op, enum machine_mode mode)
3290 if (mode == VOIDmode)
3291 mode = GET_MODE (op);
3293 if (mode != QImode && mode != Pmode)
3294 fatal_insn ("mode not QImode", op);
3296 if (GET_CODE (op) == CONST_INT)
3297 return c4x_L_constant (op) || c4x_J_constant (op);
3299 return src_operand (op, mode);
3303 /* Check src operand of two operand tricky instructions. */
3306 tsrc_operand (rtx op, enum machine_mode mode)
3308 if (mode == VOIDmode)
3309 mode = GET_MODE (op);
3311 if (mode != QImode && mode != Pmode)
3312 fatal_insn ("mode not QImode", op);
3314 if (GET_CODE (op) == CONST_INT)
3315 return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
3317 return src_operand (op, mode);
3321 /* Check src operand of two operand non immedidate instructions. */
3324 nonimmediate_src_operand (rtx op, enum machine_mode mode)
3326 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3329 return src_operand (op, mode);
3333 /* Check logical src operand of two operand non immedidate instructions. */
3336 nonimmediate_lsrc_operand (rtx op, enum machine_mode mode)
3338 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3341 return lsrc_operand (op, mode);
3346 reg_or_const_operand (rtx op, enum machine_mode mode)
3348 return reg_operand (op, mode) || const_operand (op, mode);
3352 /* Check for indirect operands allowable in parallel instruction. */
3355 par_ind_operand (rtx op, enum machine_mode mode)
3357 if (mode != VOIDmode && mode != GET_MODE (op))
3360 return c4x_S_indirect (op);
3364 /* Check for operands allowable in parallel instruction. */
3367 parallel_operand (rtx op, enum machine_mode mode)
3369 return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
3374 c4x_S_address_parse (rtx op, int *base, int *incdec, int *index, int *disp)
3381 if (GET_CODE (op) != MEM)
3382 fatal_insn ("invalid indirect memory address", op);
3385 switch (GET_CODE (op))
3388 *base = REGNO (XEXP (op, 0));
3394 *base = REGNO (XEXP (op, 0));
3400 *base = REGNO (XEXP (op, 0));
3406 *base = REGNO (XEXP (op, 0));
3412 *base = REGNO (XEXP (op, 0));
3413 if (REG_P (XEXP (XEXP (op, 1), 1)))
3415 *index = REGNO (XEXP (XEXP (op, 1), 1));
3416 *disp = 0; /* ??? */
3419 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3424 *base = REGNO (XEXP (op, 0));
3425 if (REG_P (XEXP (XEXP (op, 1), 1)))
3427 *index = REGNO (XEXP (XEXP (op, 1), 1));
3428 *disp = 1; /* ??? */
3431 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3442 rtx op0 = XEXP (op, 0);
3443 rtx op1 = XEXP (op, 1);
3445 if (c4x_a_register (op0))
3447 if (c4x_x_register (op1))
3449 *base = REGNO (op0);
3450 *index = REGNO (op1);
3453 else if ((GET_CODE (op1) == CONST_INT
3454 && IS_DISP1_CONST (INTVAL (op1))))
3456 *base = REGNO (op0);
3457 *disp = INTVAL (op1);
3461 else if (c4x_x_register (op0) && c4x_a_register (op1))
3463 *base = REGNO (op1);
3464 *index = REGNO (op0);
3471 fatal_insn ("invalid indirect (S) memory address", op);
3477 c4x_address_conflict (rtx op0, rtx op1, int store0, int store1)
3488 if (MEM_VOLATILE_P (op0) && MEM_VOLATILE_P (op1))
3491 c4x_S_address_parse (op0, &base0, &incdec0, &index0, &disp0);
3492 c4x_S_address_parse (op1, &base1, &incdec1, &index1, &disp1);
3494 if (store0 && store1)
3496 /* If we have two stores in parallel to the same address, then
3497 the C4x only executes one of the stores. This is unlikely to
3498 cause problems except when writing to a hardware device such
3499 as a FIFO since the second write will be lost. The user
3500 should flag the hardware location as being volatile so that
3501 we don't do this optimization. While it is unlikely that we
3502 have an aliased address if both locations are not marked
3503 volatile, it is probably safer to flag a potential conflict
3504 if either location is volatile. */
3505 if (! flag_argument_noalias)
3507 if (MEM_VOLATILE_P (op0) || MEM_VOLATILE_P (op1))
3512 /* If have a parallel load and a store to the same address, the load
3513 is performed first, so there is no conflict. Similarly, there is
3514 no conflict if have parallel loads from the same address. */
3516 /* Cannot use auto increment or auto decrement twice for same
3518 if (base0 == base1 && incdec0 && incdec0)
3521 /* It might be too confusing for GCC if we have use a base register
3522 with a side effect and a memory reference using the same register
3524 if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
3527 /* We can not optimize the case where op1 and op2 refer to the same
3529 if (base0 == base1 && disp0 == disp1 && index0 == index1)
3537 /* Check for while loop inside a decrement and branch loop. */
3540 c4x_label_conflict (rtx insn, rtx jump, rtx db)
3544 if (GET_CODE (insn) == CODE_LABEL)
3546 if (CODE_LABEL_NUMBER (jump) == CODE_LABEL_NUMBER (insn))
3548 if (CODE_LABEL_NUMBER (db) == CODE_LABEL_NUMBER (insn))
3551 insn = PREV_INSN (insn);
3557 /* Validate combination of operands for parallel load/store instructions. */
3560 valid_parallel_load_store (rtx *operands,
3561 enum machine_mode mode ATTRIBUTE_UNUSED)
3563 rtx op0 = operands[0];
3564 rtx op1 = operands[1];
3565 rtx op2 = operands[2];
3566 rtx op3 = operands[3];
3568 if (GET_CODE (op0) == SUBREG)
3569 op0 = SUBREG_REG (op0);
3570 if (GET_CODE (op1) == SUBREG)
3571 op1 = SUBREG_REG (op1);
3572 if (GET_CODE (op2) == SUBREG)
3573 op2 = SUBREG_REG (op2);
3574 if (GET_CODE (op3) == SUBREG)
3575 op3 = SUBREG_REG (op3);
3577 /* The patterns should only allow ext_low_reg_operand() or
3578 par_ind_operand() operands. Thus of the 4 operands, only 2
3579 should be REGs and the other 2 should be MEMs. */
3581 /* This test prevents the multipack pass from using this pattern if
3582 op0 is used as an index or base register in op2 or op3, since
3583 this combination will require reloading. */
3584 if (GET_CODE (op0) == REG
3585 && ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
3586 || (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
3590 if (GET_CODE (op0) == REG && GET_CODE (op2) == REG)
3591 return (REGNO (op0) != REGNO (op2))
3592 && GET_CODE (op1) == MEM && GET_CODE (op3) == MEM
3593 && ! c4x_address_conflict (op1, op3, 0, 0);
3596 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG)
3597 return GET_CODE (op0) == MEM && GET_CODE (op2) == MEM
3598 && ! c4x_address_conflict (op0, op2, 1, 1);
3601 if (GET_CODE (op0) == REG && GET_CODE (op3) == REG)
3602 return GET_CODE (op1) == MEM && GET_CODE (op2) == MEM
3603 && ! c4x_address_conflict (op1, op2, 0, 1);
3606 if (GET_CODE (op1) == REG && GET_CODE (op2) == REG)
3607 return GET_CODE (op0) == MEM && GET_CODE (op3) == MEM
3608 && ! c4x_address_conflict (op0, op3, 1, 0);
3615 valid_parallel_operands_4 (rtx *operands,
3616 enum machine_mode mode ATTRIBUTE_UNUSED)
3618 rtx op0 = operands[0];
3619 rtx op2 = operands[2];
3621 if (GET_CODE (op0) == SUBREG)
3622 op0 = SUBREG_REG (op0);
3623 if (GET_CODE (op2) == SUBREG)
3624 op2 = SUBREG_REG (op2);
3626 /* This test prevents the multipack pass from using this pattern if
3627 op0 is used as an index or base register in op2, since this combination
3628 will require reloading. */
3629 if (GET_CODE (op0) == REG
3630 && GET_CODE (op2) == MEM
3631 && reg_mentioned_p (op0, XEXP (op2, 0)))
3639 valid_parallel_operands_5 (rtx *operands,
3640 enum machine_mode mode ATTRIBUTE_UNUSED)
3643 rtx op0 = operands[0];
3644 rtx op1 = operands[1];
3645 rtx op2 = operands[2];
3646 rtx op3 = operands[3];
3648 if (GET_CODE (op0) == SUBREG)
3649 op0 = SUBREG_REG (op0);
3650 if (GET_CODE (op1) == SUBREG)
3651 op1 = SUBREG_REG (op1);
3652 if (GET_CODE (op2) == SUBREG)
3653 op2 = SUBREG_REG (op2);
3655 /* The patterns should only allow ext_low_reg_operand() or
3656 par_ind_operand() operands. Operands 1 and 2 may be commutative
3657 but only one of them can be a register. */
3658 if (GET_CODE (op1) == REG)
3660 if (GET_CODE (op2) == REG)
3666 /* This test prevents the multipack pass from using this pattern if
3667 op0 is used as an index or base register in op3, since this combination
3668 will require reloading. */
3669 if (GET_CODE (op0) == REG
3670 && GET_CODE (op3) == MEM
3671 && reg_mentioned_p (op0, XEXP (op3, 0)))
3679 valid_parallel_operands_6 (rtx *operands,
3680 enum machine_mode mode ATTRIBUTE_UNUSED)
3683 rtx op0 = operands[0];
3684 rtx op1 = operands[1];
3685 rtx op2 = operands[2];
3686 rtx op4 = operands[4];
3687 rtx op5 = operands[5];
3689 if (GET_CODE (op1) == SUBREG)
3690 op1 = SUBREG_REG (op1);
3691 if (GET_CODE (op2) == SUBREG)
3692 op2 = SUBREG_REG (op2);
3693 if (GET_CODE (op4) == SUBREG)
3694 op4 = SUBREG_REG (op4);
3695 if (GET_CODE (op5) == SUBREG)
3696 op5 = SUBREG_REG (op5);
3698 /* The patterns should only allow ext_low_reg_operand() or
3699 par_ind_operand() operands. Thus of the 4 input operands, only 2
3700 should be REGs and the other 2 should be MEMs. */
3702 if (GET_CODE (op1) == REG)
3704 if (GET_CODE (op2) == REG)
3706 if (GET_CODE (op4) == REG)
3708 if (GET_CODE (op5) == REG)
3711 /* The new C30/C40 silicon dies allow 3 regs of the 4 input operands.
3712 Perhaps we should count the MEMs as well? */
3716 /* This test prevents the multipack pass from using this pattern if
3717 op0 is used as an index or base register in op4 or op5, since
3718 this combination will require reloading. */
3719 if (GET_CODE (op0) == REG
3720 && ((GET_CODE (op4) == MEM && reg_mentioned_p (op0, XEXP (op4, 0)))
3721 || (GET_CODE (op5) == MEM && reg_mentioned_p (op0, XEXP (op5, 0)))))
3728 /* Validate combination of src operands. Note that the operands have
3729 been screened by the src_operand predicate. We just have to check
3730 that the combination of operands is valid. If FORCE is set, ensure
3731 that the destination regno is valid if we have a 2 operand insn. */
3734 c4x_valid_operands (enum rtx_code code, rtx *operands,
3735 enum machine_mode mode ATTRIBUTE_UNUSED,
3741 enum rtx_code code1;
3742 enum rtx_code code2;
3745 /* FIXME, why can't we tighten the operands for IF_THEN_ELSE? */
3746 if (code == IF_THEN_ELSE)
3747 return 1 || (operands[0] == operands[2] || operands[0] == operands[3]);
3749 if (code == COMPARE)
3762 if (GET_CODE (op0) == SUBREG)
3763 op0 = SUBREG_REG (op0);
3764 if (GET_CODE (op1) == SUBREG)
3765 op1 = SUBREG_REG (op1);
3766 if (GET_CODE (op2) == SUBREG)
3767 op2 = SUBREG_REG (op2);
3769 code1 = GET_CODE (op1);
3770 code2 = GET_CODE (op2);
3773 if (code1 == REG && code2 == REG)
3776 if (code1 == MEM && code2 == MEM)
3778 if (c4x_S_indirect (op1) && c4x_S_indirect (op2))
3780 return c4x_R_indirect (op1) && c4x_R_indirect (op2);
3783 /* We cannot handle two MEMs or two CONSTS, etc. */
3792 if (c4x_J_constant (op2) && c4x_R_indirect (op1))
3797 if (! c4x_H_constant (op2))
3801 /* Any valid memory operand screened by src_operand is OK. */
3805 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3806 into a stack slot memory address comprising a PLUS and a
3812 fatal_insn ("c4x_valid_operands: Internal error", op2);
3816 if (GET_CODE (op0) == SCRATCH)
3822 /* Check that we have a valid destination register for a two operand
3824 return ! force || code == COMPARE || REGNO (op1) == REGNO (op0);
3828 /* Check non-commutative operators. */
3829 if (code == ASHIFTRT || code == LSHIFTRT
3830 || code == ASHIFT || code == COMPARE)
3832 && (c4x_S_indirect (op1) || c4x_R_indirect (op1));
3835 /* Assume MINUS is commutative since the subtract patterns
3836 also support the reverse subtract instructions. Since op1
3837 is not a register, and op2 is a register, op1 can only
3838 be a restricted memory operand for a shift instruction. */
3847 if (! c4x_H_constant (op1))
3851 /* Any valid memory operand screened by src_operand is OK. */
3855 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3856 into a stack slot memory address comprising a PLUS and a
3866 if (GET_CODE (op0) == SCRATCH)
3872 /* Check that we have a valid destination register for a two operand
3874 return ! force || REGNO (op1) == REGNO (op0);
3877 if (c4x_J_constant (op1) && c4x_R_indirect (op2))
3884 int valid_operands (enum rtx_code code, rtx *operands, enum machine_mode mode)
3887 /* If we are not optimizing then we have to let anything go and let
3888 reload fix things up. instantiate_decl in function.c can produce
3889 invalid insns by changing the offset of a memory operand from a
3890 valid one into an invalid one, when the second operand is also a
3891 memory operand. The alternative is not to allow two memory
3892 operands for an insn when not optimizing. The problem only rarely
3893 occurs, for example with the C-torture program DFcmp.c. */
3895 return ! optimize || c4x_valid_operands (code, operands, mode, 0);
3900 legitimize_operands (enum rtx_code code, rtx *operands, enum machine_mode mode)
3902 /* Compare only has 2 operands. */
3903 if (code == COMPARE)
3905 /* During RTL generation, force constants into pseudos so that
3906 they can get hoisted out of loops. This will tie up an extra
3907 register but can save an extra cycle. Only do this if loop
3908 optimization enabled. (We cannot pull this trick for add and
3909 sub instructions since the flow pass won't find
3910 autoincrements etc.) This allows us to generate compare
3911 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
3912 of LDI *AR0++, R0; CMPI 42, R0.
3914 Note that expand_binops will try to load an expensive constant
3915 into a register if it is used within a loop. Unfortunately,
3916 the cost mechanism doesn't allow us to look at the other
3917 operand to decide whether the constant is expensive. */
3919 if (! reload_in_progress
3922 && GET_CODE (operands[1]) == CONST_INT
3923 && preserve_subexpressions_p ()
3924 && rtx_cost (operands[1], code) > 1)
3925 operands[1] = force_reg (mode, operands[1]);
3927 if (! reload_in_progress
3928 && ! c4x_valid_operands (code, operands, mode, 0))
3929 operands[0] = force_reg (mode, operands[0]);
3933 /* We cannot do this for ADDI/SUBI insns since we will
3934 defeat the flow pass from finding autoincrement addressing
3936 if (! reload_in_progress
3937 && ! ((code == PLUS || code == MINUS) && mode == Pmode)
3940 && GET_CODE (operands[2]) == CONST_INT
3941 && preserve_subexpressions_p ()
3942 && rtx_cost (operands[2], code) > 1)
3943 operands[2] = force_reg (mode, operands[2]);
3945 /* We can get better code on a C30 if we force constant shift counts
3946 into a register. This way they can get hoisted out of loops,
3947 tying up a register, but saving an instruction. The downside is
3948 that they may get allocated to an address or index register, and
3949 thus we will get a pipeline conflict if there is a nearby
3950 indirect address using an address register.
3952 Note that expand_binops will not try to load an expensive constant
3953 into a register if it is used within a loop for a shift insn. */
3955 if (! reload_in_progress
3956 && ! c4x_valid_operands (code, operands, mode, TARGET_FORCE))
3958 /* If the operand combination is invalid, we force operand1 into a
3959 register, preventing reload from having doing to do this at a
3961 operands[1] = force_reg (mode, operands[1]);
3964 emit_move_insn (operands[0], operands[1]);
3965 operands[1] = copy_rtx (operands[0]);
3969 /* Just in case... */
3970 if (! c4x_valid_operands (code, operands, mode, 0))
3971 operands[2] = force_reg (mode, operands[2]);
3975 /* Right shifts require a negative shift count, but GCC expects
3976 a positive count, so we emit a NEG. */
3977 if ((code == ASHIFTRT || code == LSHIFTRT)
3978 && (GET_CODE (operands[2]) != CONST_INT))
3979 operands[2] = gen_rtx_NEG (mode, negate_rtx (mode, operands[2]));
3985 /* The following predicates are used for instruction scheduling. */
3988 group1_reg_operand (rtx op, enum machine_mode mode)
3990 if (mode != VOIDmode && mode != GET_MODE (op))
3992 if (GET_CODE (op) == SUBREG)
3993 op = SUBREG_REG (op);
3994 return REG_P (op) && (! reload_completed || IS_GROUP1_REG (op));
3999 group1_mem_operand (rtx op, enum machine_mode mode)
4001 if (mode != VOIDmode && mode != GET_MODE (op))
4004 if (GET_CODE (op) == MEM)
4007 if (GET_CODE (op) == PLUS)
4009 rtx op0 = XEXP (op, 0);
4010 rtx op1 = XEXP (op, 1);
4012 if ((REG_P (op0) && (! reload_completed || IS_GROUP1_REG (op0)))
4013 || (REG_P (op1) && (! reload_completed || IS_GROUP1_REG (op1))))
4016 else if ((REG_P (op)) && (! reload_completed || IS_GROUP1_REG (op)))
4024 /* Return true if any one of the address registers. */
4027 arx_reg_operand (rtx op, enum machine_mode mode)
4029 if (mode != VOIDmode && mode != GET_MODE (op))
4031 if (GET_CODE (op) == SUBREG)
4032 op = SUBREG_REG (op);
4033 return REG_P (op) && (! reload_completed || IS_ADDR_REG (op));
4038 c4x_arn_reg_operand (rtx op, enum machine_mode mode, unsigned int regno)
4040 if (mode != VOIDmode && mode != GET_MODE (op))
4042 if (GET_CODE (op) == SUBREG)
4043 op = SUBREG_REG (op);
4044 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4049 c4x_arn_mem_operand (rtx op, enum machine_mode mode, unsigned int regno)
4051 if (mode != VOIDmode && mode != GET_MODE (op))
4054 if (GET_CODE (op) == MEM)
4057 switch (GET_CODE (op))
4066 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4070 if (REG_P (XEXP (op, 0)) && (! reload_completed
4071 || (REGNO (XEXP (op, 0)) == regno)))
4073 if (REG_P (XEXP (XEXP (op, 1), 1))
4074 && (! reload_completed
4075 || (REGNO (XEXP (XEXP (op, 1), 1)) == regno)))
4081 rtx op0 = XEXP (op, 0);
4082 rtx op1 = XEXP (op, 1);
4084 if ((REG_P (op0) && (! reload_completed
4085 || (REGNO (op0) == regno)))
4086 || (REG_P (op1) && (! reload_completed
4087 || (REGNO (op1) == regno))))
4101 ar0_reg_operand (rtx op, enum machine_mode mode)
4103 return c4x_arn_reg_operand (op, mode, AR0_REGNO);
4108 ar0_mem_operand (rtx op, enum machine_mode mode)
4110 return c4x_arn_mem_operand (op, mode, AR0_REGNO);
4115 ar1_reg_operand (rtx op, enum machine_mode mode)
4117 return c4x_arn_reg_operand (op, mode, AR1_REGNO);
4122 ar1_mem_operand (rtx op, enum machine_mode mode)
4124 return c4x_arn_mem_operand (op, mode, AR1_REGNO);
4129 ar2_reg_operand (rtx op, enum machine_mode mode)
4131 return c4x_arn_reg_operand (op, mode, AR2_REGNO);
4136 ar2_mem_operand (rtx op, enum machine_mode mode)
4138 return c4x_arn_mem_operand (op, mode, AR2_REGNO);
4143 ar3_reg_operand (rtx op, enum machine_mode mode)
4145 return c4x_arn_reg_operand (op, mode, AR3_REGNO);
4150 ar3_mem_operand (rtx op, enum machine_mode mode)
4152 return c4x_arn_mem_operand (op, mode, AR3_REGNO);
4157 ar4_reg_operand (rtx op, enum machine_mode mode)
4159 return c4x_arn_reg_operand (op, mode, AR4_REGNO);
4164 ar4_mem_operand (rtx op, enum machine_mode mode)
4166 return c4x_arn_mem_operand (op, mode, AR4_REGNO);
4171 ar5_reg_operand (rtx op, enum machine_mode mode)
4173 return c4x_arn_reg_operand (op, mode, AR5_REGNO);
4178 ar5_mem_operand (rtx op, enum machine_mode mode)
4180 return c4x_arn_mem_operand (op, mode, AR5_REGNO);
4185 ar6_reg_operand (rtx op, enum machine_mode mode)
4187 return c4x_arn_reg_operand (op, mode, AR6_REGNO);
4192 ar6_mem_operand (rtx op, enum machine_mode mode)
4194 return c4x_arn_mem_operand (op, mode, AR6_REGNO);
4199 ar7_reg_operand (rtx op, enum machine_mode mode)
4201 return c4x_arn_reg_operand (op, mode, AR7_REGNO);
4206 ar7_mem_operand (rtx op, enum machine_mode mode)
4208 return c4x_arn_mem_operand (op, mode, AR7_REGNO);
4213 ir0_reg_operand (rtx op, enum machine_mode mode)
4215 return c4x_arn_reg_operand (op, mode, IR0_REGNO);
4220 ir0_mem_operand (rtx op, enum machine_mode mode)
4222 return c4x_arn_mem_operand (op, mode, IR0_REGNO);
4227 ir1_reg_operand (rtx op, enum machine_mode mode)
4229 return c4x_arn_reg_operand (op, mode, IR1_REGNO);
4234 ir1_mem_operand (rtx op, enum machine_mode mode)
4236 return c4x_arn_mem_operand (op, mode, IR1_REGNO);
4240 /* This is similar to operand_subword but allows autoincrement
4244 c4x_operand_subword (rtx op, int i, int validate_address,
4245 enum machine_mode mode)
4247 if (mode != HImode && mode != HFmode)
4248 fatal_insn ("c4x_operand_subword: invalid mode", op);
4250 if (mode == HFmode && REG_P (op))
4251 fatal_insn ("c4x_operand_subword: invalid operand", op);
4253 if (GET_CODE (op) == MEM)
4255 enum rtx_code code = GET_CODE (XEXP (op, 0));
4256 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4257 enum machine_mode submode;
4262 else if (mode == HFmode)
4269 return gen_rtx_MEM (submode, XEXP (op, 0));
4275 /* We could handle these with some difficulty.
4276 e.g., *p-- => *(p-=2); *(p+1). */
4277 fatal_insn ("c4x_operand_subword: invalid autoincrement", op);
4283 fatal_insn ("c4x_operand_subword: invalid address", op);
4285 /* Even though offsettable_address_p considers (MEM
4286 (LO_SUM)) to be offsettable, it is not safe if the
4287 address is at the end of the data page since we also have
4288 to fix up the associated high PART. In this case where
4289 we are trying to split a HImode or HFmode memory
4290 reference, we would have to emit another insn to reload a
4291 new HIGH value. It's easier to disable LO_SUM memory references
4292 in HImode or HFmode and we probably get better code. */
4294 fatal_insn ("c4x_operand_subword: address not offsettable", op);
4301 return operand_subword (op, i, validate_address, mode);
4306 struct name_list *next;
4310 static struct name_list *global_head;
4311 static struct name_list *extern_head;
4314 /* Add NAME to list of global symbols and remove from external list if
4315 present on external list. */
4318 c4x_global_label (const char *name)
4320 struct name_list *p, *last;
4322 /* Do not insert duplicate names, so linearly search through list of
4327 if (strcmp (p->name, name) == 0)
4331 p = (struct name_list *) xmalloc (sizeof *p);
4332 p->next = global_head;
4336 /* Remove this name from ref list if present. */
4341 if (strcmp (p->name, name) == 0)
4344 last->next = p->next;
4346 extern_head = p->next;
4355 /* Add NAME to list of external symbols. */
4358 c4x_external_ref (const char *name)
4360 struct name_list *p;
4362 /* Do not insert duplicate names. */
4366 if (strcmp (p->name, name) == 0)
4371 /* Do not insert ref if global found. */
4375 if (strcmp (p->name, name) == 0)
4379 p = (struct name_list *) xmalloc (sizeof *p);
4380 p->next = extern_head;
4385 /* We need to have a data section we can identify so that we can set
4386 the DP register back to a data pointer in the small memory model.
4387 This is only required for ISRs if we are paranoid that someone
4388 may have quietly changed this register on the sly. */
4390 c4x_file_start (void)
4393 if (TARGET_C30) dspversion = 30;
4394 if (TARGET_C31) dspversion = 31;
4395 if (TARGET_C32) dspversion = 32;
4396 if (TARGET_C33) dspversion = 33;
4397 if (TARGET_C40) dspversion = 40;
4398 if (TARGET_C44) dspversion = 44;
4400 default_file_start ();
4401 fprintf (asm_out_file, "\t.version\t%d\n", dspversion);
4402 fputs ("\n\t.data\ndata_sec:\n", asm_out_file);
4409 struct name_list *p;
4411 /* Output all external names that are not global. */
4415 fprintf (asm_out_file, "\t.ref\t");
4416 assemble_name (asm_out_file, p->name);
4417 fprintf (asm_out_file, "\n");
4420 fprintf (asm_out_file, "\t.end\n");
4425 c4x_check_attribute (const char *attrib, tree list, tree decl, tree *attributes)
4427 while (list != NULL_TREE
4428 && IDENTIFIER_POINTER (TREE_PURPOSE (list))
4429 != IDENTIFIER_POINTER (DECL_NAME (decl)))
4430 list = TREE_CHAIN (list);
4432 *attributes = tree_cons (get_identifier (attrib), TREE_VALUE (list),
4438 c4x_insert_attributes (tree decl, tree *attributes)
4440 switch (TREE_CODE (decl))
4443 c4x_check_attribute ("section", code_tree, decl, attributes);
4444 c4x_check_attribute ("const", pure_tree, decl, attributes);
4445 c4x_check_attribute ("noreturn", noreturn_tree, decl, attributes);
4446 c4x_check_attribute ("interrupt", interrupt_tree, decl, attributes);
4447 c4x_check_attribute ("naked", naked_tree, decl, attributes);
4451 c4x_check_attribute ("section", data_tree, decl, attributes);
4459 /* Table of valid machine attributes. */
4460 const struct attribute_spec c4x_attribute_table[] =
4462 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4463 { "interrupt", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4464 { "naked", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4465 { "leaf_pretend", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4466 { NULL, 0, 0, false, false, false, NULL }
4469 /* Handle an attribute requiring a FUNCTION_TYPE;
4470 arguments as in struct attribute_spec.handler. */
4472 c4x_handle_fntype_attribute (tree *node, tree name,
4473 tree args ATTRIBUTE_UNUSED,
4474 int flags ATTRIBUTE_UNUSED,
4477 if (TREE_CODE (*node) != FUNCTION_TYPE)
4479 warning ("`%s' attribute only applies to functions",
4480 IDENTIFIER_POINTER (name));
4481 *no_add_attrs = true;
4488 /* !!! FIXME to emit RPTS correctly. */
4491 c4x_rptb_rpts_p (rtx insn, rtx op)
4493 /* The next insn should be our label marking where the
4494 repeat block starts. */
4495 insn = NEXT_INSN (insn);
4496 if (GET_CODE (insn) != CODE_LABEL)
4498 /* Some insns may have been shifted between the RPTB insn
4499 and the top label... They were probably destined to
4500 be moved out of the loop. For now, let's leave them
4501 where they are and print a warning. We should
4502 probably move these insns before the repeat block insn. */
4504 fatal_insn("c4x_rptb_rpts_p: Repeat block top label moved\n",
4509 /* Skip any notes. */
4510 insn = next_nonnote_insn (insn);
4512 /* This should be our first insn in the loop. */
4513 if (! INSN_P (insn))
4516 /* Skip any notes. */
4517 insn = next_nonnote_insn (insn);
4519 if (! INSN_P (insn))
4522 if (recog_memoized (insn) != CODE_FOR_rptb_end)
4528 return (GET_CODE (op) == CONST_INT) && TARGET_RPTS_CYCLES (INTVAL (op));
4532 /* Check if register r11 is used as the destination of an insn. */
4535 c4x_r11_set_p(rtx x)
4544 if (INSN_P (x) && GET_CODE (PATTERN (x)) == SEQUENCE)
4545 x = XVECEXP (PATTERN (x), 0, XVECLEN (PATTERN (x), 0) - 1);
4547 if (INSN_P (x) && (set = single_set (x)))
4550 if (GET_CODE (x) == REG && REGNO (x) == R11_REGNO)
4553 fmt = GET_RTX_FORMAT (GET_CODE (x));
4554 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4558 if (c4x_r11_set_p (XEXP (x, i)))
4561 else if (fmt[i] == 'E')
4562 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4563 if (c4x_r11_set_p (XVECEXP (x, i, j)))
4570 /* The c4x sometimes has a problem when the insn before the laj insn
4571 sets the r11 register. Check for this situation. */
4574 c4x_check_laj_p (rtx insn)
4576 insn = prev_nonnote_insn (insn);
4578 /* If this is the start of the function no nop is needed. */
4582 /* If the previous insn is a code label we have to insert a nop. This
4583 could be a jump or table jump. We can find the normal jumps by
4584 scanning the function but this will not find table jumps. */
4585 if (GET_CODE (insn) == CODE_LABEL)
4588 /* If the previous insn sets register r11 we have to insert a nop. */
4589 if (c4x_r11_set_p (insn))
4592 /* No nop needed. */
4597 /* Adjust the cost of a scheduling dependency. Return the new cost of
4598 a dependency LINK or INSN on DEP_INSN. COST is the current cost.
4599 A set of an address register followed by a use occurs a 2 cycle
4600 stall (reduced to a single cycle on the c40 using LDA), while
4601 a read of an address register followed by a use occurs a single cycle. */
4603 #define SET_USE_COST 3
4604 #define SETLDA_USE_COST 2
4605 #define READ_USE_COST 2
4608 c4x_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4610 /* Don't worry about this until we know what registers have been
4612 if (flag_schedule_insns == 0 && ! reload_completed)
4615 /* How do we handle dependencies where a read followed by another
4616 read causes a pipeline stall? For example, a read of ar0 followed
4617 by the use of ar0 for a memory reference. It looks like we
4618 need to extend the scheduler to handle this case. */
4620 /* Reload sometimes generates a CLOBBER of a stack slot, e.g.,
4621 (clobber (mem:QI (plus:QI (reg:QI 11 ar3) (const_int 261)))),
4622 so only deal with insns we know about. */
4623 if (recog_memoized (dep_insn) < 0)
4626 if (REG_NOTE_KIND (link) == 0)
4630 /* Data dependency; DEP_INSN writes a register that INSN reads some
4634 if (get_attr_setgroup1 (dep_insn) && get_attr_usegroup1 (insn))
4635 max = SET_USE_COST > max ? SET_USE_COST : max;
4636 if (get_attr_readarx (dep_insn) && get_attr_usegroup1 (insn))
4637 max = READ_USE_COST > max ? READ_USE_COST : max;
4641 /* This could be significantly optimized. We should look
4642 to see if dep_insn sets ar0-ar7 or ir0-ir1 and if
4643 insn uses ar0-ar7. We then test if the same register
4644 is used. The tricky bit is that some operands will
4645 use several registers... */
4646 if (get_attr_setar0 (dep_insn) && get_attr_usear0 (insn))
4647 max = SET_USE_COST > max ? SET_USE_COST : max;
4648 if (get_attr_setlda_ar0 (dep_insn) && get_attr_usear0 (insn))
4649 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4650 if (get_attr_readar0 (dep_insn) && get_attr_usear0 (insn))
4651 max = READ_USE_COST > max ? READ_USE_COST : max;
4653 if (get_attr_setar1 (dep_insn) && get_attr_usear1 (insn))
4654 max = SET_USE_COST > max ? SET_USE_COST : max;
4655 if (get_attr_setlda_ar1 (dep_insn) && get_attr_usear1 (insn))
4656 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4657 if (get_attr_readar1 (dep_insn) && get_attr_usear1 (insn))
4658 max = READ_USE_COST > max ? READ_USE_COST : max;
4660 if (get_attr_setar2 (dep_insn) && get_attr_usear2 (insn))
4661 max = SET_USE_COST > max ? SET_USE_COST : max;
4662 if (get_attr_setlda_ar2 (dep_insn) && get_attr_usear2 (insn))
4663 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4664 if (get_attr_readar2 (dep_insn) && get_attr_usear2 (insn))
4665 max = READ_USE_COST > max ? READ_USE_COST : max;
4667 if (get_attr_setar3 (dep_insn) && get_attr_usear3 (insn))
4668 max = SET_USE_COST > max ? SET_USE_COST : max;
4669 if (get_attr_setlda_ar3 (dep_insn) && get_attr_usear3 (insn))
4670 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4671 if (get_attr_readar3 (dep_insn) && get_attr_usear3 (insn))
4672 max = READ_USE_COST > max ? READ_USE_COST : max;
4674 if (get_attr_setar4 (dep_insn) && get_attr_usear4 (insn))
4675 max = SET_USE_COST > max ? SET_USE_COST : max;
4676 if (get_attr_setlda_ar4 (dep_insn) && get_attr_usear4 (insn))
4677 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4678 if (get_attr_readar4 (dep_insn) && get_attr_usear4 (insn))
4679 max = READ_USE_COST > max ? READ_USE_COST : max;
4681 if (get_attr_setar5 (dep_insn) && get_attr_usear5 (insn))
4682 max = SET_USE_COST > max ? SET_USE_COST : max;
4683 if (get_attr_setlda_ar5 (dep_insn) && get_attr_usear5 (insn))
4684 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4685 if (get_attr_readar5 (dep_insn) && get_attr_usear5 (insn))
4686 max = READ_USE_COST > max ? READ_USE_COST : max;
4688 if (get_attr_setar6 (dep_insn) && get_attr_usear6 (insn))
4689 max = SET_USE_COST > max ? SET_USE_COST : max;
4690 if (get_attr_setlda_ar6 (dep_insn) && get_attr_usear6 (insn))
4691 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4692 if (get_attr_readar6 (dep_insn) && get_attr_usear6 (insn))
4693 max = READ_USE_COST > max ? READ_USE_COST : max;
4695 if (get_attr_setar7 (dep_insn) && get_attr_usear7 (insn))
4696 max = SET_USE_COST > max ? SET_USE_COST : max;
4697 if (get_attr_setlda_ar7 (dep_insn) && get_attr_usear7 (insn))
4698 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4699 if (get_attr_readar7 (dep_insn) && get_attr_usear7 (insn))
4700 max = READ_USE_COST > max ? READ_USE_COST : max;
4702 if (get_attr_setir0 (dep_insn) && get_attr_useir0 (insn))
4703 max = SET_USE_COST > max ? SET_USE_COST : max;
4704 if (get_attr_setlda_ir0 (dep_insn) && get_attr_useir0 (insn))
4705 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4707 if (get_attr_setir1 (dep_insn) && get_attr_useir1 (insn))
4708 max = SET_USE_COST > max ? SET_USE_COST : max;
4709 if (get_attr_setlda_ir1 (dep_insn) && get_attr_useir1 (insn))
4710 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4716 /* For other data dependencies, the default cost specified in the
4720 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4722 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4725 /* For c4x anti dependencies, the cost is 0. */
4728 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4730 /* Output dependency; DEP_INSN writes a register that INSN writes some
4733 /* For c4x output dependencies, the cost is 0. */
4741 c4x_init_builtins (void)
4743 tree endlink = void_list_node;
4745 builtin_function ("fast_ftoi",
4748 tree_cons (NULL_TREE, double_type_node, endlink)),
4749 C4X_BUILTIN_FIX, BUILT_IN_MD, NULL, NULL_TREE);
4750 builtin_function ("ansi_ftoi",
4753 tree_cons (NULL_TREE, double_type_node, endlink)),
4754 C4X_BUILTIN_FIX_ANSI, BUILT_IN_MD, NULL, NULL_TREE);
4756 builtin_function ("fast_imult",
4759 tree_cons (NULL_TREE, integer_type_node,
4760 tree_cons (NULL_TREE,
4761 integer_type_node, endlink))),
4762 C4X_BUILTIN_MPYI, BUILT_IN_MD, NULL, NULL_TREE);
4765 builtin_function ("toieee",
4768 tree_cons (NULL_TREE, double_type_node, endlink)),
4769 C4X_BUILTIN_TOIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4770 builtin_function ("frieee",
4773 tree_cons (NULL_TREE, double_type_node, endlink)),
4774 C4X_BUILTIN_FRIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4775 builtin_function ("fast_invf",
4778 tree_cons (NULL_TREE, double_type_node, endlink)),
4779 C4X_BUILTIN_RCPF, BUILT_IN_MD, NULL, NULL_TREE);
4785 c4x_expand_builtin (tree exp, rtx target,
4786 rtx subtarget ATTRIBUTE_UNUSED,
4787 enum machine_mode mode ATTRIBUTE_UNUSED,
4788 int ignore ATTRIBUTE_UNUSED)
4790 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4791 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4792 tree arglist = TREE_OPERAND (exp, 1);
4798 case C4X_BUILTIN_FIX:
4799 arg0 = TREE_VALUE (arglist);
4800 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4801 r0 = protect_from_queue (r0, 0);
4802 if (! target || ! register_operand (target, QImode))
4803 target = gen_reg_rtx (QImode);
4804 emit_insn (gen_fixqfqi_clobber (target, r0));
4807 case C4X_BUILTIN_FIX_ANSI:
4808 arg0 = TREE_VALUE (arglist);
4809 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4810 r0 = protect_from_queue (r0, 0);
4811 if (! target || ! register_operand (target, QImode))
4812 target = gen_reg_rtx (QImode);
4813 emit_insn (gen_fix_truncqfqi2 (target, r0));
4816 case C4X_BUILTIN_MPYI:
4819 arg0 = TREE_VALUE (arglist);
4820 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4821 r0 = expand_expr (arg0, NULL_RTX, QImode, 0);
4822 r1 = expand_expr (arg1, NULL_RTX, QImode, 0);
4823 r0 = protect_from_queue (r0, 0);
4824 r1 = protect_from_queue (r1, 0);
4825 if (! target || ! register_operand (target, QImode))
4826 target = gen_reg_rtx (QImode);
4827 emit_insn (gen_mulqi3_24_clobber (target, r0, r1));
4830 case C4X_BUILTIN_TOIEEE:
4833 arg0 = TREE_VALUE (arglist);
4834 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4835 r0 = protect_from_queue (r0, 0);
4836 if (! target || ! register_operand (target, QFmode))
4837 target = gen_reg_rtx (QFmode);
4838 emit_insn (gen_toieee (target, r0));
4841 case C4X_BUILTIN_FRIEEE:
4844 arg0 = TREE_VALUE (arglist);
4845 if (TREE_CODE (arg0) == VAR_DECL || TREE_CODE (arg0) == PARM_DECL)
4846 put_var_into_stack (arg0, /*rescan=*/true);
4847 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4848 r0 = protect_from_queue (r0, 0);
4849 if (register_operand (r0, QFmode))
4851 r1 = assign_stack_local (QFmode, GET_MODE_SIZE (QFmode), 0);
4852 emit_move_insn (r1, r0);
4855 if (! target || ! register_operand (target, QFmode))
4856 target = gen_reg_rtx (QFmode);
4857 emit_insn (gen_frieee (target, r0));
4860 case C4X_BUILTIN_RCPF:
4863 arg0 = TREE_VALUE (arglist);
4864 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4865 r0 = protect_from_queue (r0, 0);
4866 if (! target || ! register_operand (target, QFmode))
4867 target = gen_reg_rtx (QFmode);
4868 emit_insn (gen_rcpfqf_clobber (target, r0));
4875 c4x_init_libfuncs (void)
4877 set_optab_libfunc (smul_optab, QImode, "__mulqi3");
4878 set_optab_libfunc (sdiv_optab, QImode, "__divqi3");
4879 set_optab_libfunc (udiv_optab, QImode, "__udivqi3");
4880 set_optab_libfunc (smod_optab, QImode, "__modqi3");
4881 set_optab_libfunc (umod_optab, QImode, "__umodqi3");
4882 set_optab_libfunc (sdiv_optab, QFmode, "__divqf3");
4883 set_optab_libfunc (smul_optab, HFmode, "__mulhf3");
4884 set_optab_libfunc (sdiv_optab, HFmode, "__divhf3");
4885 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4886 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4887 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4888 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4889 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4890 set_optab_libfunc (ffs_optab, QImode, "__ffs");
4891 smulhi3_libfunc = init_one_libfunc ("__smulhi3_high");
4892 umulhi3_libfunc = init_one_libfunc ("__umulhi3_high");
4893 fix_truncqfhi2_libfunc = init_one_libfunc ("__fix_truncqfhi2");
4894 fixuns_truncqfhi2_libfunc = init_one_libfunc ("__ufix_truncqfhi2");
4895 fix_trunchfhi2_libfunc = init_one_libfunc ("__fix_trunchfhi2");
4896 fixuns_trunchfhi2_libfunc = init_one_libfunc ("__ufix_trunchfhi2");
4897 floathiqf2_libfunc = init_one_libfunc ("__floathiqf2");
4898 floatunshiqf2_libfunc = init_one_libfunc ("__ufloathiqf2");
4899 floathihf2_libfunc = init_one_libfunc ("__floathihf2");
4900 floatunshihf2_libfunc = init_one_libfunc ("__ufloathihf2");
4904 c4x_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4906 fprintf (asm_out_file, "\t.sect\t\"%s\"\n", name);
4910 c4x_globalize_label (FILE *stream, const char *name)
4912 default_globalize_label (stream, name);
4913 c4x_global_label (name);
4916 #define SHIFT_CODE_P(C) \
4917 ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
4918 #define LOGICAL_CODE_P(C) \
4919 ((C) == NOT || (C) == AND || (C) == IOR || (C) == XOR)
4921 /* Compute a (partial) cost for rtx X. Return true if the complete
4922 cost has been computed, and false if subexpressions should be
4923 scanned. In either case, *TOTAL contains the cost result. */
4926 c4x_rtx_costs (rtx x, int code, int outer_code, int *total)
4932 /* Some small integers are effectively free for the C40. We should
4933 also consider if we are using the small memory model. With
4934 the big memory model we require an extra insn for a constant
4935 loaded from memory. */
4939 if (c4x_J_constant (x))
4941 else if (! TARGET_C3X
4942 && outer_code == AND
4943 && (val == 255 || val == 65535))
4945 else if (! TARGET_C3X
4946 && (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
4947 && (val == 16 || val == 24))
4949 else if (TARGET_C3X && SHIFT_CODE_P (outer_code))
4951 else if (LOGICAL_CODE_P (outer_code)
4952 ? c4x_L_constant (x) : c4x_I_constant (x))
4965 if (c4x_H_constant (x))
4967 else if (GET_MODE (x) == QFmode)
4973 /* ??? Note that we return true, rather than false so that rtx_cost
4974 doesn't include the constant costs. Otherwise expand_mult will
4975 think that it is cheaper to synthesize a multiply rather than to
4976 use a multiply instruction. I think this is because the algorithm
4977 synth_mult doesn't take into account the loading of the operands,
4978 whereas the calculation of mult_cost does. */
4987 *total = COSTS_N_INSNS (1);
4991 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
4992 || TARGET_MPYI ? 1 : 14);
4999 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT