1 /* Subroutines for assembler code output on the TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004
3 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Some output-actions in c4x.md need these. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "basic-block.h"
36 #include "insn-config.h"
37 #include "insn-attr.h"
38 #include "conditions.h"
52 #include "target-def.h"
56 rtx fix_truncqfhi2_libfunc;
57 rtx fixuns_truncqfhi2_libfunc;
58 rtx fix_trunchfhi2_libfunc;
59 rtx fixuns_trunchfhi2_libfunc;
60 rtx floathiqf2_libfunc;
61 rtx floatunshiqf2_libfunc;
62 rtx floathihf2_libfunc;
63 rtx floatunshihf2_libfunc;
65 static int c4x_leaf_function;
67 static const char *const float_reg_names[] = FLOAT_REGISTER_NAMES;
69 /* Array of the smallest class containing reg number REGNO, indexed by
70 REGNO. Used by REGNO_REG_CLASS in c4x.h. We assume that all these
71 registers are available and set the class to NO_REGS for registers
72 that the target switches say are unavailable. */
74 enum reg_class c4x_regclass_map[FIRST_PSEUDO_REGISTER] =
76 /* Reg Modes Saved. */
77 R0R1_REGS, /* R0 QI, QF, HF No. */
78 R0R1_REGS, /* R1 QI, QF, HF No. */
79 R2R3_REGS, /* R2 QI, QF, HF No. */
80 R2R3_REGS, /* R3 QI, QF, HF No. */
81 EXT_LOW_REGS, /* R4 QI, QF, HF QI. */
82 EXT_LOW_REGS, /* R5 QI, QF, HF QI. */
83 EXT_LOW_REGS, /* R6 QI, QF, HF QF. */
84 EXT_LOW_REGS, /* R7 QI, QF, HF QF. */
85 ADDR_REGS, /* AR0 QI No. */
86 ADDR_REGS, /* AR1 QI No. */
87 ADDR_REGS, /* AR2 QI No. */
88 ADDR_REGS, /* AR3 QI QI. */
89 ADDR_REGS, /* AR4 QI QI. */
90 ADDR_REGS, /* AR5 QI QI. */
91 ADDR_REGS, /* AR6 QI QI. */
92 ADDR_REGS, /* AR7 QI QI. */
93 DP_REG, /* DP QI No. */
94 INDEX_REGS, /* IR0 QI No. */
95 INDEX_REGS, /* IR1 QI No. */
96 BK_REG, /* BK QI QI. */
97 SP_REG, /* SP QI No. */
98 ST_REG, /* ST CC No. */
99 NO_REGS, /* DIE/IE No. */
100 NO_REGS, /* IIE/IF No. */
101 NO_REGS, /* IIF/IOF No. */
102 INT_REGS, /* RS QI No. */
103 INT_REGS, /* RE QI No. */
104 RC_REG, /* RC QI No. */
105 EXT_REGS, /* R8 QI, QF, HF QI. */
106 EXT_REGS, /* R9 QI, QF, HF No. */
107 EXT_REGS, /* R10 QI, QF, HF No. */
108 EXT_REGS, /* R11 QI, QF, HF No. */
111 enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
113 /* Reg Modes Saved. */
114 HFmode, /* R0 QI, QF, HF No. */
115 HFmode, /* R1 QI, QF, HF No. */
116 HFmode, /* R2 QI, QF, HF No. */
117 HFmode, /* R3 QI, QF, HF No. */
118 QFmode, /* R4 QI, QF, HF QI. */
119 QFmode, /* R5 QI, QF, HF QI. */
120 QImode, /* R6 QI, QF, HF QF. */
121 QImode, /* R7 QI, QF, HF QF. */
122 QImode, /* AR0 QI No. */
123 QImode, /* AR1 QI No. */
124 QImode, /* AR2 QI No. */
125 QImode, /* AR3 QI QI. */
126 QImode, /* AR4 QI QI. */
127 QImode, /* AR5 QI QI. */
128 QImode, /* AR6 QI QI. */
129 QImode, /* AR7 QI QI. */
130 VOIDmode, /* DP QI No. */
131 QImode, /* IR0 QI No. */
132 QImode, /* IR1 QI No. */
133 QImode, /* BK QI QI. */
134 VOIDmode, /* SP QI No. */
135 VOIDmode, /* ST CC No. */
136 VOIDmode, /* DIE/IE No. */
137 VOIDmode, /* IIE/IF No. */
138 VOIDmode, /* IIF/IOF No. */
139 QImode, /* RS QI No. */
140 QImode, /* RE QI No. */
141 VOIDmode, /* RC QI No. */
142 QFmode, /* R8 QI, QF, HF QI. */
143 HFmode, /* R9 QI, QF, HF No. */
144 HFmode, /* R10 QI, QF, HF No. */
145 HFmode, /* R11 QI, QF, HF No. */
149 /* Test and compare insns in c4x.md store the information needed to
150 generate branch and scc insns here. */
155 const char *c4x_rpts_cycles_string;
156 int c4x_rpts_cycles = 0; /* Max. cycles for RPTS. */
157 const char *c4x_cpu_version_string;
158 int c4x_cpu_version = 40; /* CPU version C30/31/32/33/40/44. */
160 /* Pragma definitions. */
162 tree code_tree = NULL_TREE;
163 tree data_tree = NULL_TREE;
164 tree pure_tree = NULL_TREE;
165 tree noreturn_tree = NULL_TREE;
166 tree interrupt_tree = NULL_TREE;
167 tree naked_tree = NULL_TREE;
169 /* Forward declarations */
170 static int c4x_isr_reg_used_p (unsigned int);
171 static int c4x_leaf_function_p (void);
172 static int c4x_naked_function_p (void);
173 static int c4x_immed_float_p (rtx);
174 static int c4x_a_register (rtx);
175 static int c4x_x_register (rtx);
176 static int c4x_immed_int_constant (rtx);
177 static int c4x_immed_float_constant (rtx);
178 static int c4x_K_constant (rtx);
179 static int c4x_N_constant (rtx);
180 static int c4x_O_constant (rtx);
181 static int c4x_R_indirect (rtx);
182 static int c4x_S_indirect (rtx);
183 static void c4x_S_address_parse (rtx , int *, int *, int *, int *);
184 static int c4x_valid_operands (enum rtx_code, rtx *, enum machine_mode, int);
185 static int c4x_arn_reg_operand (rtx, enum machine_mode, unsigned int);
186 static int c4x_arn_mem_operand (rtx, enum machine_mode, unsigned int);
187 static void c4x_file_start (void);
188 static void c4x_file_end (void);
189 static void c4x_check_attribute (const char *, tree, tree, tree *);
190 static int c4x_r11_set_p (rtx);
191 static int c4x_rptb_valid_p (rtx, rtx);
192 static void c4x_reorg (void);
193 static int c4x_label_ref_used_p (rtx, rtx);
194 static tree c4x_handle_fntype_attribute (tree *, tree, tree, int, bool *);
195 const struct attribute_spec c4x_attribute_table[];
196 static void c4x_insert_attributes (tree, tree *);
197 static void c4x_asm_named_section (const char *, unsigned int);
198 static int c4x_adjust_cost (rtx, rtx, rtx, int);
199 static void c4x_globalize_label (FILE *, const char *);
200 static bool c4x_rtx_costs (rtx, int, int, int *);
201 static int c4x_address_cost (rtx);
202 static void c4x_init_libfuncs (void);
203 static void c4x_external_libcall (rtx);
204 static rtx c4x_struct_value_rtx (tree, int);
206 /* Initialize the GCC target structure. */
207 #undef TARGET_ASM_BYTE_OP
208 #define TARGET_ASM_BYTE_OP "\t.word\t"
209 #undef TARGET_ASM_ALIGNED_HI_OP
210 #define TARGET_ASM_ALIGNED_HI_OP NULL
211 #undef TARGET_ASM_ALIGNED_SI_OP
212 #define TARGET_ASM_ALIGNED_SI_OP NULL
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START c4x_file_start
215 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
216 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
217 #undef TARGET_ASM_FILE_END
218 #define TARGET_ASM_FILE_END c4x_file_end
220 #undef TARGET_ASM_EXTERNAL_LIBCALL
221 #define TARGET_ASM_EXTERNAL_LIBCALL c4x_external_libcall
223 #undef TARGET_ATTRIBUTE_TABLE
224 #define TARGET_ATTRIBUTE_TABLE c4x_attribute_table
226 #undef TARGET_INSERT_ATTRIBUTES
227 #define TARGET_INSERT_ATTRIBUTES c4x_insert_attributes
229 #undef TARGET_INIT_BUILTINS
230 #define TARGET_INIT_BUILTINS c4x_init_builtins
232 #undef TARGET_EXPAND_BUILTIN
233 #define TARGET_EXPAND_BUILTIN c4x_expand_builtin
235 #undef TARGET_SCHED_ADJUST_COST
236 #define TARGET_SCHED_ADJUST_COST c4x_adjust_cost
238 #undef TARGET_ASM_GLOBALIZE_LABEL
239 #define TARGET_ASM_GLOBALIZE_LABEL c4x_globalize_label
241 #undef TARGET_RTX_COSTS
242 #define TARGET_RTX_COSTS c4x_rtx_costs
243 #undef TARGET_ADDRESS_COST
244 #define TARGET_ADDRESS_COST c4x_address_cost
246 #undef TARGET_MACHINE_DEPENDENT_REORG
247 #define TARGET_MACHINE_DEPENDENT_REORG c4x_reorg
249 #undef TARGET_INIT_LIBFUNCS
250 #define TARGET_INIT_LIBFUNCS c4x_init_libfuncs
252 #undef TARGET_STRUCT_VALUE_RTX
253 #define TARGET_STRUCT_VALUE_RTX c4x_struct_value_rtx
255 struct gcc_target targetm = TARGET_INITIALIZER;
257 /* Override command line options.
258 Called once after all options have been parsed.
259 Mostly we process the processor
260 type and sometimes adjust other TARGET_ options. */
263 c4x_override_options (void)
265 if (c4x_rpts_cycles_string)
266 c4x_rpts_cycles = atoi (c4x_rpts_cycles_string);
271 c4x_cpu_version = 30;
273 c4x_cpu_version = 31;
275 c4x_cpu_version = 32;
277 c4x_cpu_version = 33;
279 c4x_cpu_version = 40;
281 c4x_cpu_version = 44;
283 c4x_cpu_version = 40;
285 /* -mcpu=xx overrides -m40 etc. */
286 if (c4x_cpu_version_string)
288 const char *p = c4x_cpu_version_string;
290 /* Also allow -mcpu=c30 etc. */
291 if (*p == 'c' || *p == 'C')
293 c4x_cpu_version = atoi (p);
296 target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG |
297 C40_FLAG | C44_FLAG);
299 switch (c4x_cpu_version)
301 case 30: target_flags |= C30_FLAG; break;
302 case 31: target_flags |= C31_FLAG; break;
303 case 32: target_flags |= C32_FLAG; break;
304 case 33: target_flags |= C33_FLAG; break;
305 case 40: target_flags |= C40_FLAG; break;
306 case 44: target_flags |= C44_FLAG; break;
308 warning ("unknown CPU version %d, using 40.\n", c4x_cpu_version);
309 c4x_cpu_version = 40;
310 target_flags |= C40_FLAG;
313 if (TARGET_C30 || TARGET_C31 || TARGET_C32 || TARGET_C33)
314 target_flags |= C3X_FLAG;
316 target_flags &= ~C3X_FLAG;
318 /* Convert foo / 8.0 into foo * 0.125, etc. */
319 set_fast_math_flags (1);
321 /* We should phase out the following at some stage.
322 This provides compatibility with the old -mno-aliases option. */
323 if (! TARGET_ALIASES && ! flag_argument_noalias)
324 flag_argument_noalias = 1;
328 /* This is called before c4x_override_options. */
331 c4x_optimization_options (int level ATTRIBUTE_UNUSED,
332 int size ATTRIBUTE_UNUSED)
334 /* Scheduling before register allocation can screw up global
335 register allocation, especially for functions that use MPY||ADD
336 instructions. The benefit we gain we get by scheduling before
337 register allocation is probably marginal anyhow. */
338 flag_schedule_insns = 0;
342 /* Write an ASCII string. */
344 #define C4X_ASCII_LIMIT 40
347 c4x_output_ascii (FILE *stream, const char *ptr, int len)
349 char sbuf[C4X_ASCII_LIMIT + 1];
350 int s, l, special, first = 1, onlys;
353 fprintf (stream, "\t.byte\t");
355 for (s = l = 0; len > 0; --len, ++ptr)
359 /* Escape " and \ with a \". */
360 special = *ptr == '\"' || *ptr == '\\';
362 /* If printable - add to buff. */
363 if ((! TARGET_TI || ! special) && *ptr >= 0x20 && *ptr < 0x7f)
368 if (s < C4X_ASCII_LIMIT - 1)
383 fprintf (stream, "\"%s\"", sbuf);
385 if (TARGET_TI && l >= 80 && len > 1)
387 fprintf (stream, "\n\t.byte\t");
405 fprintf (stream, "%d", *ptr);
407 if (TARGET_TI && l >= 80 && len > 1)
409 fprintf (stream, "\n\t.byte\t");
420 fprintf (stream, "\"%s\"", sbuf);
423 fputc ('\n', stream);
428 c4x_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
433 case Pmode: /* Pointer (24/32 bits). */
435 case QImode: /* Integer (32 bits). */
436 return IS_INT_REGNO (regno);
438 case QFmode: /* Float, Double (32 bits). */
439 case HFmode: /* Long Double (40 bits). */
440 return IS_EXT_REGNO (regno);
442 case CCmode: /* Condition Codes. */
443 case CC_NOOVmode: /* Condition Codes. */
444 return IS_ST_REGNO (regno);
446 case HImode: /* Long Long (64 bits). */
447 /* We need two registers to store long longs. Note that
448 it is much easier to constrain the first register
449 to start on an even boundary. */
450 return IS_INT_REGNO (regno)
451 && IS_INT_REGNO (regno + 1)
455 return 0; /* We don't support these modes. */
461 /* Return nonzero if REGNO1 can be renamed to REGNO2. */
463 c4x_hard_regno_rename_ok (unsigned int regno1, unsigned int regno2)
465 /* We can not copy call saved registers from mode QI into QF or from
467 if (IS_FLOAT_CALL_SAVED_REGNO (regno1) && IS_INT_CALL_SAVED_REGNO (regno2))
469 if (IS_INT_CALL_SAVED_REGNO (regno1) && IS_FLOAT_CALL_SAVED_REGNO (regno2))
471 /* We cannot copy from an extended (40 bit) register to a standard
472 (32 bit) register because we only set the condition codes for
473 extended registers. */
474 if (IS_EXT_REGNO (regno1) && ! IS_EXT_REGNO (regno2))
476 if (IS_EXT_REGNO (regno2) && ! IS_EXT_REGNO (regno1))
481 /* The TI C3x C compiler register argument runtime model uses 6 registers,
482 AR2, R2, R3, RC, RS, RE.
484 The first two floating point arguments (float, double, long double)
485 that are found scanning from left to right are assigned to R2 and R3.
487 The remaining integer (char, short, int, long) or pointer arguments
488 are assigned to the remaining registers in the order AR2, R2, R3,
489 RC, RS, RE when scanning left to right, except for the last named
490 argument prior to an ellipsis denoting variable number of
491 arguments. We don't have to worry about the latter condition since
492 function.c treats the last named argument as anonymous (unnamed).
494 All arguments that cannot be passed in registers are pushed onto
495 the stack in reverse order (right to left). GCC handles that for us.
497 c4x_init_cumulative_args() is called at the start, so we can parse
498 the args to see how many floating point arguments and how many
499 integer (or pointer) arguments there are. c4x_function_arg() is
500 then called (sometimes repeatedly) for each argument (parsed left
501 to right) to obtain the register to pass the argument in, or zero
502 if the argument is to be passed on the stack. Once the compiler is
503 happy, c4x_function_arg_advance() is called.
505 Don't use R0 to pass arguments in, we use 0 to indicate a stack
508 static const int c4x_int_reglist[3][6] =
510 {AR2_REGNO, R2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO},
511 {AR2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0},
512 {AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
515 static const int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
518 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
519 function whose data type is FNTYPE.
520 For a library call, FNTYPE is 0. */
523 c4x_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname)
525 tree param, next_param;
527 cum->floats = cum->ints = 0;
534 fprintf (stderr, "\nc4x_init_cumulative_args (");
537 tree ret_type = TREE_TYPE (fntype);
539 fprintf (stderr, "fntype code = %s, ret code = %s",
540 tree_code_name[(int) TREE_CODE (fntype)],
541 tree_code_name[(int) TREE_CODE (ret_type)]);
544 fprintf (stderr, "no fntype");
547 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
550 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
552 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
553 param; param = next_param)
557 next_param = TREE_CHAIN (param);
559 type = TREE_VALUE (param);
560 if (type && type != void_type_node)
562 enum machine_mode mode;
564 /* If the last arg doesn't have void type then we have
565 variable arguments. */
569 if ((mode = TYPE_MODE (type)))
571 if (! MUST_PASS_IN_STACK (mode, type))
573 /* Look for float, double, or long double argument. */
574 if (mode == QFmode || mode == HFmode)
576 /* Look for integer, enumeral, boolean, char, or pointer
578 else if (mode == QImode || mode == Pmode)
587 fprintf (stderr, "%s%s, args = %d)\n",
588 cum->prototype ? ", prototype" : "",
589 cum->var ? ", variable args" : "",
594 /* Update the data in CUM to advance over an argument
595 of mode MODE and data type TYPE.
596 (TYPE is null for libcalls where that information may not be available.) */
599 c4x_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
600 tree type, int named)
603 fprintf (stderr, "c4x_function_adv(mode=%s, named=%d)\n\n",
604 GET_MODE_NAME (mode), named);
608 && ! MUST_PASS_IN_STACK (mode, type))
610 /* Look for float, double, or long double argument. */
611 if (mode == QFmode || mode == HFmode)
613 /* Look for integer, enumeral, boolean, char, or pointer argument. */
614 else if (mode == QImode || mode == Pmode)
617 else if (! TARGET_MEMPARM && ! type)
619 /* Handle libcall arguments. */
620 if (mode == QFmode || mode == HFmode)
622 else if (mode == QImode || mode == Pmode)
629 /* Define where to put the arguments to a function. Value is zero to
630 push the argument on the stack, or a hard register in which to
633 MODE is the argument's machine mode.
634 TYPE is the data type of the argument (as a tree).
635 This is null for libcalls where that information may
637 CUM is a variable of type CUMULATIVE_ARGS which gives info about
638 the preceding args and about the function being called.
639 NAMED is nonzero if this argument is a named parameter
640 (otherwise it is an extra parameter matching an ellipsis). */
643 c4x_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
644 tree type, int named)
646 int reg = 0; /* Default to passing argument on stack. */
650 /* We can handle at most 2 floats in R2, R3. */
651 cum->maxfloats = (cum->floats > 2) ? 2 : cum->floats;
653 /* We can handle at most 6 integers minus number of floats passed
655 cum->maxints = (cum->ints > 6 - cum->maxfloats) ?
656 6 - cum->maxfloats : cum->ints;
658 /* If there is no prototype, assume all the arguments are integers. */
659 if (! cum->prototype)
662 cum->ints = cum->floats = 0;
666 /* This marks the last argument. We don't need to pass this through
668 if (type == void_type_node)
674 && ! MUST_PASS_IN_STACK (mode, type))
676 /* Look for float, double, or long double argument. */
677 if (mode == QFmode || mode == HFmode)
679 if (cum->floats < cum->maxfloats)
680 reg = c4x_fp_reglist[cum->floats];
682 /* Look for integer, enumeral, boolean, char, or pointer argument. */
683 else if (mode == QImode || mode == Pmode)
685 if (cum->ints < cum->maxints)
686 reg = c4x_int_reglist[cum->maxfloats][cum->ints];
689 else if (! TARGET_MEMPARM && ! type)
691 /* We could use a different argument calling model for libcalls,
692 since we're only calling functions in libgcc. Thus we could
693 pass arguments for long longs in registers rather than on the
694 stack. In the meantime, use the odd TI format. We make the
695 assumption that we won't have more than two floating point
696 args, six integer args, and that all the arguments are of the
698 if (mode == QFmode || mode == HFmode)
699 reg = c4x_fp_reglist[cum->floats];
700 else if (mode == QImode || mode == Pmode)
701 reg = c4x_int_reglist[0][cum->ints];
706 fprintf (stderr, "c4x_function_arg(mode=%s, named=%d",
707 GET_MODE_NAME (mode), named);
709 fprintf (stderr, ", reg=%s", reg_names[reg]);
711 fprintf (stderr, ", stack");
712 fprintf (stderr, ")\n");
715 return gen_rtx_REG (mode, reg);
720 /* C[34]x arguments grow in weird ways (downwards) that the standard
721 varargs stuff can't handle.. */
723 c4x_va_arg (tree valist, tree type)
727 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
728 build_int_2 (int_size_in_bytes (type), 0));
729 TREE_SIDE_EFFECTS (t) = 1;
731 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
736 c4x_isr_reg_used_p (unsigned int regno)
738 /* Don't save/restore FP or ST, we handle them separately. */
739 if (regno == FRAME_POINTER_REGNUM
740 || IS_ST_REGNO (regno))
743 /* We could be a little smarter abut saving/restoring DP.
744 We'll only save if for the big memory model or if
745 we're paranoid. ;-) */
746 if (IS_DP_REGNO (regno))
747 return ! TARGET_SMALL || TARGET_PARANOID;
749 /* Only save/restore regs in leaf function that are used. */
750 if (c4x_leaf_function)
751 return regs_ever_live[regno] && fixed_regs[regno] == 0;
753 /* Only save/restore regs that are used by the ISR and regs
754 that are likely to be used by functions the ISR calls
755 if they are not fixed. */
756 return IS_EXT_REGNO (regno)
757 || ((regs_ever_live[regno] || call_used_regs[regno])
758 && fixed_regs[regno] == 0);
763 c4x_leaf_function_p (void)
765 /* A leaf function makes no calls, so we only need
766 to save/restore the registers we actually use.
767 For the global variable leaf_function to be set, we need
768 to define LEAF_REGISTERS and all that it entails.
769 Let's check ourselves... */
771 if (lookup_attribute ("leaf_pretend",
772 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
775 /* Use the leaf_pretend attribute at your own risk. This is a hack
776 to speed up ISRs that call a function infrequently where the
777 overhead of saving and restoring the additional registers is not
778 warranted. You must save and restore the additional registers
779 required by the called function. Caveat emptor. Here's enough
782 if (leaf_function_p ())
790 c4x_naked_function_p (void)
794 type = TREE_TYPE (current_function_decl);
795 return lookup_attribute ("naked", TYPE_ATTRIBUTES (type)) != NULL;
800 c4x_interrupt_function_p (void)
802 const char *cfun_name;
803 if (lookup_attribute ("interrupt",
804 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
807 /* Look for TI style c_intnn. */
808 cfun_name = current_function_name ();
809 return cfun_name[0] == 'c'
810 && cfun_name[1] == '_'
811 && cfun_name[2] == 'i'
812 && cfun_name[3] == 'n'
813 && cfun_name[4] == 't'
814 && ISDIGIT (cfun_name[5])
815 && ISDIGIT (cfun_name[6]);
819 c4x_expand_prologue (void)
822 int size = get_frame_size ();
825 /* In functions where ar3 is not used but frame pointers are still
826 specified, frame pointers are not adjusted (if >= -O2) and this
827 is used so it won't needlessly push the frame pointer. */
830 /* For __naked__ function don't build a prologue. */
831 if (c4x_naked_function_p ())
836 /* For __interrupt__ function build specific prologue. */
837 if (c4x_interrupt_function_p ())
839 c4x_leaf_function = c4x_leaf_function_p ();
841 insn = emit_insn (gen_push_st ());
842 RTX_FRAME_RELATED_P (insn) = 1;
845 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
846 RTX_FRAME_RELATED_P (insn) = 1;
847 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
848 gen_rtx_REG (QImode, SP_REGNO)));
849 RTX_FRAME_RELATED_P (insn) = 1;
850 /* We require that an ISR uses fewer than 32768 words of
851 local variables, otherwise we have to go to lots of
852 effort to save a register, load it with the desired size,
853 adjust the stack pointer, and then restore the modified
854 register. Frankly, I think it is a poor ISR that
855 requires more than 32767 words of local temporary
858 error ("ISR %s requires %d words of local vars, max is 32767",
859 current_function_name (), size);
861 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
862 gen_rtx_REG (QImode, SP_REGNO),
864 RTX_FRAME_RELATED_P (insn) = 1;
866 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
868 if (c4x_isr_reg_used_p (regno))
870 if (regno == DP_REGNO)
872 insn = emit_insn (gen_push_dp ());
873 RTX_FRAME_RELATED_P (insn) = 1;
877 insn = emit_insn (gen_pushqi (gen_rtx_REG (QImode, regno)));
878 RTX_FRAME_RELATED_P (insn) = 1;
879 if (IS_EXT_REGNO (regno))
881 insn = emit_insn (gen_pushqf
882 (gen_rtx_REG (QFmode, regno)));
883 RTX_FRAME_RELATED_P (insn) = 1;
888 /* We need to clear the repeat mode flag if the ISR is
889 going to use a RPTB instruction or uses the RC, RS, or RE
891 if (regs_ever_live[RC_REGNO]
892 || regs_ever_live[RS_REGNO]
893 || regs_ever_live[RE_REGNO])
895 insn = emit_insn (gen_andn_st (GEN_INT(~0x100)));
896 RTX_FRAME_RELATED_P (insn) = 1;
899 /* Reload DP reg if we are paranoid about some turkey
900 violating small memory model rules. */
901 if (TARGET_SMALL && TARGET_PARANOID)
903 insn = emit_insn (gen_set_ldp_prologue
904 (gen_rtx_REG (QImode, DP_REGNO),
905 gen_rtx_SYMBOL_REF (QImode, "data_sec")));
906 RTX_FRAME_RELATED_P (insn) = 1;
911 if (frame_pointer_needed)
914 || (current_function_args_size != 0)
917 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, AR3_REGNO)));
918 RTX_FRAME_RELATED_P (insn) = 1;
919 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, AR3_REGNO),
920 gen_rtx_REG (QImode, SP_REGNO)));
921 RTX_FRAME_RELATED_P (insn) = 1;
926 /* Since ar3 is not used, we don't need to push it. */
932 /* If we use ar3, we need to push it. */
934 if ((size != 0) || (current_function_args_size != 0))
936 /* If we are omitting the frame pointer, we still have
937 to make space for it so the offsets are correct
938 unless we don't use anything on the stack at all. */
945 /* Local vars are too big, it will take multiple operations
949 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
950 GEN_INT(size >> 16)));
951 RTX_FRAME_RELATED_P (insn) = 1;
952 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R1_REGNO),
953 gen_rtx_REG (QImode, R1_REGNO),
955 RTX_FRAME_RELATED_P (insn) = 1;
959 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R1_REGNO),
960 GEN_INT(size & ~0xffff)));
961 RTX_FRAME_RELATED_P (insn) = 1;
963 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R1_REGNO),
964 gen_rtx_REG (QImode, R1_REGNO),
965 GEN_INT(size & 0xffff)));
966 RTX_FRAME_RELATED_P (insn) = 1;
967 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
968 gen_rtx_REG (QImode, SP_REGNO),
969 gen_rtx_REG (QImode, R1_REGNO)));
970 RTX_FRAME_RELATED_P (insn) = 1;
974 /* Local vars take up less than 32767 words, so we can directly
976 insn = emit_insn (gen_addqi3 (gen_rtx_REG (QImode, SP_REGNO),
977 gen_rtx_REG (QImode, SP_REGNO),
979 RTX_FRAME_RELATED_P (insn) = 1;
982 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
984 if (regs_ever_live[regno] && ! call_used_regs[regno])
986 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
988 if (TARGET_PRESERVE_FLOAT)
990 insn = emit_insn (gen_pushqi
991 (gen_rtx_REG (QImode, regno)));
992 RTX_FRAME_RELATED_P (insn) = 1;
994 insn = emit_insn (gen_pushqf (gen_rtx_REG (QFmode, regno)));
995 RTX_FRAME_RELATED_P (insn) = 1;
997 else if ((! dont_push_ar3) || (regno != AR3_REGNO))
999 insn = emit_insn (gen_pushqi ( gen_rtx_REG (QImode, regno)));
1000 RTX_FRAME_RELATED_P (insn) = 1;
1009 c4x_expand_epilogue(void)
1015 int size = get_frame_size ();
1017 /* For __naked__ function build no epilogue. */
1018 if (c4x_naked_function_p ())
1020 insn = emit_jump_insn (gen_return_from_epilogue ());
1021 RTX_FRAME_RELATED_P (insn) = 1;
1025 /* For __interrupt__ function build specific epilogue. */
1026 if (c4x_interrupt_function_p ())
1028 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
1030 if (! c4x_isr_reg_used_p (regno))
1032 if (regno == DP_REGNO)
1034 insn = emit_insn (gen_pop_dp ());
1035 RTX_FRAME_RELATED_P (insn) = 1;
1039 /* We have to use unspec because the compiler will delete insns
1040 that are not call-saved. */
1041 if (IS_EXT_REGNO (regno))
1043 insn = emit_insn (gen_popqf_unspec
1044 (gen_rtx_REG (QFmode, regno)));
1045 RTX_FRAME_RELATED_P (insn) = 1;
1047 insn = emit_insn (gen_popqi_unspec (gen_rtx_REG (QImode, regno)));
1048 RTX_FRAME_RELATED_P (insn) = 1;
1053 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1054 gen_rtx_REG (QImode, SP_REGNO),
1056 RTX_FRAME_RELATED_P (insn) = 1;
1057 insn = emit_insn (gen_popqi
1058 (gen_rtx_REG (QImode, AR3_REGNO)));
1059 RTX_FRAME_RELATED_P (insn) = 1;
1061 insn = emit_insn (gen_pop_st ());
1062 RTX_FRAME_RELATED_P (insn) = 1;
1063 insn = emit_jump_insn (gen_return_from_interrupt_epilogue ());
1064 RTX_FRAME_RELATED_P (insn) = 1;
1068 if (frame_pointer_needed)
1071 || (current_function_args_size != 0)
1075 (gen_movqi (gen_rtx_REG (QImode, R2_REGNO),
1076 gen_rtx_MEM (QImode,
1078 (QImode, gen_rtx_REG (QImode,
1081 RTX_FRAME_RELATED_P (insn) = 1;
1083 /* We already have the return value and the fp,
1084 so we need to add those to the stack. */
1091 /* Since ar3 is not used for anything, we don't need to
1098 dont_pop_ar3 = 0; /* If we use ar3, we need to pop it. */
1099 if (size || current_function_args_size)
1101 /* If we are omitting the frame pointer, we still have
1102 to make space for it so the offsets are correct
1103 unless we don't use anything on the stack at all. */
1108 /* Now restore the saved registers, putting in the delayed branch
1110 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1112 if (regs_ever_live[regno] && ! call_used_regs[regno])
1114 if (regno == AR3_REGNO && dont_pop_ar3)
1117 if (IS_FLOAT_CALL_SAVED_REGNO (regno))
1119 insn = emit_insn (gen_popqf_unspec
1120 (gen_rtx_REG (QFmode, regno)));
1121 RTX_FRAME_RELATED_P (insn) = 1;
1122 if (TARGET_PRESERVE_FLOAT)
1124 insn = emit_insn (gen_popqi_unspec
1125 (gen_rtx_REG (QImode, regno)));
1126 RTX_FRAME_RELATED_P (insn) = 1;
1131 insn = emit_insn (gen_popqi (gen_rtx_REG (QImode, regno)));
1132 RTX_FRAME_RELATED_P (insn) = 1;
1137 if (frame_pointer_needed)
1140 || (current_function_args_size != 0)
1143 /* Restore the old FP. */
1146 (gen_rtx_REG (QImode, AR3_REGNO),
1147 gen_rtx_MEM (QImode, gen_rtx_REG (QImode, AR3_REGNO))));
1149 RTX_FRAME_RELATED_P (insn) = 1;
1155 /* Local vars are too big, it will take multiple operations
1159 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1160 GEN_INT(size >> 16)));
1161 RTX_FRAME_RELATED_P (insn) = 1;
1162 insn = emit_insn (gen_lshrqi3 (gen_rtx_REG (QImode, R3_REGNO),
1163 gen_rtx_REG (QImode, R3_REGNO),
1165 RTX_FRAME_RELATED_P (insn) = 1;
1169 insn = emit_insn (gen_movqi (gen_rtx_REG (QImode, R3_REGNO),
1170 GEN_INT(size & ~0xffff)));
1171 RTX_FRAME_RELATED_P (insn) = 1;
1173 insn = emit_insn (gen_iorqi3 (gen_rtx_REG (QImode, R3_REGNO),
1174 gen_rtx_REG (QImode, R3_REGNO),
1175 GEN_INT(size & 0xffff)));
1176 RTX_FRAME_RELATED_P (insn) = 1;
1177 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1178 gen_rtx_REG (QImode, SP_REGNO),
1179 gen_rtx_REG (QImode, R3_REGNO)));
1180 RTX_FRAME_RELATED_P (insn) = 1;
1184 /* Local vars take up less than 32768 words, so we can directly
1185 subtract the number. */
1186 insn = emit_insn (gen_subqi3 (gen_rtx_REG (QImode, SP_REGNO),
1187 gen_rtx_REG (QImode, SP_REGNO),
1189 RTX_FRAME_RELATED_P (insn) = 1;
1194 insn = emit_jump_insn (gen_return_indirect_internal
1195 (gen_rtx_REG (QImode, R2_REGNO)));
1196 RTX_FRAME_RELATED_P (insn) = 1;
1200 insn = emit_jump_insn (gen_return_from_epilogue ());
1201 RTX_FRAME_RELATED_P (insn) = 1;
1208 c4x_null_epilogue_p (void)
1212 if (reload_completed
1213 && ! c4x_naked_function_p ()
1214 && ! c4x_interrupt_function_p ()
1215 && ! current_function_calls_alloca
1216 && ! current_function_args_size
1218 && ! get_frame_size ())
1220 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1221 if (regs_ever_live[regno] && ! call_used_regs[regno]
1222 && (regno != AR3_REGNO))
1231 c4x_emit_move_sequence (rtx *operands, enum machine_mode mode)
1233 rtx op0 = operands[0];
1234 rtx op1 = operands[1];
1236 if (! reload_in_progress
1239 && ! (stik_const_operand (op1, mode) && ! push_operand (op0, mode)))
1240 op1 = force_reg (mode, op1);
1242 if (GET_CODE (op1) == LO_SUM
1243 && GET_MODE (op1) == Pmode
1244 && dp_reg_operand (XEXP (op1, 0), mode))
1246 /* expand_increment will sometimes create a LO_SUM immediate
1247 address. Undo this sillyness. */
1248 op1 = XEXP (op1, 1);
1251 if (symbolic_address_operand (op1, mode))
1253 if (TARGET_LOAD_ADDRESS)
1255 /* Alias analysis seems to do a better job if we force
1256 constant addresses to memory after reload. */
1257 emit_insn (gen_load_immed_address (op0, op1));
1262 /* Stick symbol or label address into the constant pool. */
1263 op1 = force_const_mem (Pmode, op1);
1266 else if (mode == HFmode && CONSTANT_P (op1) && ! LEGITIMATE_CONSTANT_P (op1))
1268 /* We could be a lot smarter about loading some of these
1270 op1 = force_const_mem (mode, op1);
1273 /* Convert (MEM (SYMREF)) to a (MEM (LO_SUM (REG) (SYMREF)))
1274 and emit associated (HIGH (SYMREF)) if large memory model.
1275 c4x_legitimize_address could be used to do this,
1276 perhaps by calling validize_address. */
1277 if (TARGET_EXPOSE_LDP
1278 && ! (reload_in_progress || reload_completed)
1279 && GET_CODE (op1) == MEM
1280 && symbolic_address_operand (XEXP (op1, 0), Pmode))
1282 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1284 emit_insn (gen_set_ldp (dp_reg, XEXP (op1, 0)));
1285 op1 = change_address (op1, mode,
1286 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op1, 0)));
1289 if (TARGET_EXPOSE_LDP
1290 && ! (reload_in_progress || reload_completed)
1291 && GET_CODE (op0) == MEM
1292 && symbolic_address_operand (XEXP (op0, 0), Pmode))
1294 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1296 emit_insn (gen_set_ldp (dp_reg, XEXP (op0, 0)));
1297 op0 = change_address (op0, mode,
1298 gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op0, 0)));
1301 if (GET_CODE (op0) == SUBREG
1302 && mixed_subreg_operand (op0, mode))
1304 /* We should only generate these mixed mode patterns
1305 during RTL generation. If we need do it later on
1306 then we'll have to emit patterns that won't clobber CC. */
1307 if (reload_in_progress || reload_completed)
1309 if (GET_MODE (SUBREG_REG (op0)) == QImode)
1310 op0 = SUBREG_REG (op0);
1311 else if (GET_MODE (SUBREG_REG (op0)) == HImode)
1313 op0 = copy_rtx (op0);
1314 PUT_MODE (op0, QImode);
1320 emit_insn (gen_storeqf_int_clobber (op0, op1));
1326 if (GET_CODE (op1) == SUBREG
1327 && mixed_subreg_operand (op1, mode))
1329 /* We should only generate these mixed mode patterns
1330 during RTL generation. If we need do it later on
1331 then we'll have to emit patterns that won't clobber CC. */
1332 if (reload_in_progress || reload_completed)
1334 if (GET_MODE (SUBREG_REG (op1)) == QImode)
1335 op1 = SUBREG_REG (op1);
1336 else if (GET_MODE (SUBREG_REG (op1)) == HImode)
1338 op1 = copy_rtx (op1);
1339 PUT_MODE (op1, QImode);
1345 emit_insn (gen_loadqf_int_clobber (op0, op1));
1352 && reg_operand (op0, mode)
1353 && const_int_operand (op1, mode)
1354 && ! IS_INT16_CONST (INTVAL (op1))
1355 && ! IS_HIGH_CONST (INTVAL (op1)))
1357 emit_insn (gen_loadqi_big_constant (op0, op1));
1362 && reg_operand (op0, mode)
1363 && const_int_operand (op1, mode))
1365 emit_insn (gen_loadhi_big_constant (op0, op1));
1369 /* Adjust operands in case we have modified them. */
1373 /* Emit normal pattern. */
1379 c4x_emit_libcall (rtx libcall, enum rtx_code code,
1380 enum machine_mode dmode, enum machine_mode smode,
1381 int noperands, rtx *operands)
1391 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 1,
1392 operands[1], smode);
1393 equiv = gen_rtx_fmt_e (code, dmode, operands[1]);
1397 ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 2,
1398 operands[1], smode, operands[2], smode);
1399 equiv = gen_rtx_fmt_ee (code, dmode, operands[1], operands[2]);
1406 insns = get_insns ();
1408 emit_libcall_block (insns, operands[0], ret, equiv);
1413 c4x_emit_libcall3 (rtx libcall, enum rtx_code code,
1414 enum machine_mode mode, rtx *operands)
1416 c4x_emit_libcall (libcall, code, mode, mode, 3, operands);
1421 c4x_emit_libcall_mulhi (rtx libcall, enum rtx_code code,
1422 enum machine_mode mode, rtx *operands)
1429 ret = emit_library_call_value (libcall, NULL_RTX, 1, mode, 2,
1430 operands[1], mode, operands[2], mode);
1431 equiv = gen_rtx_TRUNCATE (mode,
1432 gen_rtx_LSHIFTRT (HImode,
1433 gen_rtx_MULT (HImode,
1434 gen_rtx_fmt_e (code, HImode, operands[1]),
1435 gen_rtx_fmt_e (code, HImode, operands[2])),
1437 insns = get_insns ();
1439 emit_libcall_block (insns, operands[0], ret, equiv);
1444 c4x_legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
1446 rtx base = NULL_RTX; /* Base register (AR0-AR7). */
1447 rtx indx = NULL_RTX; /* Index register (IR0,IR1). */
1448 rtx disp = NULL_RTX; /* Displacement. */
1451 code = GET_CODE (addr);
1454 /* Register indirect with auto increment/decrement. We don't
1455 allow SP here---push_operand should recognize an operand
1456 being pushed on the stack. */
1461 if (mode != QImode && mode != QFmode)
1465 base = XEXP (addr, 0);
1473 rtx op0 = XEXP (addr, 0);
1474 rtx op1 = XEXP (addr, 1);
1476 if (mode != QImode && mode != QFmode)
1480 || (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS))
1482 base = XEXP (op1, 0);
1485 if (REGNO (base) != REGNO (op0))
1487 if (REG_P (XEXP (op1, 1)))
1488 indx = XEXP (op1, 1);
1490 disp = XEXP (op1, 1);
1494 /* Register indirect. */
1499 /* Register indirect with displacement or index. */
1502 rtx op0 = XEXP (addr, 0);
1503 rtx op1 = XEXP (addr, 1);
1504 enum rtx_code code0 = GET_CODE (op0);
1511 base = op0; /* Base + index. */
1513 if (IS_INDEX_REG (base) || IS_ADDR_REG (indx))
1521 base = op0; /* Base + displacement. */
1532 /* Direct addressing with DP register. */
1535 rtx op0 = XEXP (addr, 0);
1536 rtx op1 = XEXP (addr, 1);
1538 /* HImode and HFmode direct memory references aren't truly
1539 offsettable (consider case at end of data page). We
1540 probably get better code by loading a pointer and using an
1541 indirect memory reference. */
1542 if (mode == HImode || mode == HFmode)
1545 if (!REG_P (op0) || REGNO (op0) != DP_REGNO)
1548 if ((GET_CODE (op1) == SYMBOL_REF || GET_CODE (op1) == LABEL_REF))
1551 if (GET_CODE (op1) == CONST)
1557 /* Direct addressing with some work for the assembler... */
1559 /* Direct addressing. */
1562 if (! TARGET_EXPOSE_LDP && ! strict && mode != HFmode && mode != HImode)
1564 /* These need to be converted to a LO_SUM (...).
1565 LEGITIMIZE_RELOAD_ADDRESS will do this during reload. */
1568 /* Do not allow direct memory access to absolute addresses.
1569 This is more pain than it's worth, especially for the
1570 small memory model where we can't guarantee that
1571 this address is within the data page---we don't want
1572 to modify the DP register in the small memory model,
1573 even temporarily, since an interrupt can sneak in.... */
1577 /* Indirect indirect addressing. */
1582 fatal_insn ("using CONST_DOUBLE for address", addr);
1588 /* Validate the base register. */
1591 /* Check that the address is offsettable for HImode and HFmode. */
1592 if (indx && (mode == HImode || mode == HFmode))
1595 /* Handle DP based stuff. */
1596 if (REGNO (base) == DP_REGNO)
1598 if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
1600 else if (! strict && ! IS_ADDR_OR_PSEUDO_REG (base))
1604 /* Now validate the index register. */
1607 if (GET_CODE (indx) != REG)
1609 if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
1611 else if (! strict && ! IS_INDEX_OR_PSEUDO_REG (indx))
1615 /* Validate displacement. */
1618 if (GET_CODE (disp) != CONST_INT)
1620 if (mode == HImode || mode == HFmode)
1622 /* The offset displacement must be legitimate. */
1623 if (! IS_DISP8_OFF_CONST (INTVAL (disp)))
1628 if (! IS_DISP8_CONST (INTVAL (disp)))
1631 /* Can't add an index with a disp. */
1640 c4x_legitimize_address (rtx orig ATTRIBUTE_UNUSED,
1641 enum machine_mode mode ATTRIBUTE_UNUSED)
1643 if (GET_CODE (orig) == SYMBOL_REF
1644 || GET_CODE (orig) == LABEL_REF)
1646 if (mode == HImode || mode == HFmode)
1648 /* We need to force the address into
1649 a register so that it is offsettable. */
1650 rtx addr_reg = gen_reg_rtx (Pmode);
1651 emit_move_insn (addr_reg, orig);
1656 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1659 emit_insn (gen_set_ldp (dp_reg, orig));
1661 return gen_rtx_LO_SUM (Pmode, dp_reg, orig);
1669 /* Provide the costs of an addressing mode that contains ADDR.
1670 If ADDR is not a valid address, its cost is irrelevant.
1671 This is used in cse and loop optimization to determine
1672 if it is worthwhile storing a common address into a register.
1673 Unfortunately, the C4x address cost depends on other operands. */
1676 c4x_address_cost (rtx addr)
1678 switch (GET_CODE (addr))
1689 /* These shouldn't be directly generated. */
1697 rtx op1 = XEXP (addr, 1);
1699 if (GET_CODE (op1) == LABEL_REF || GET_CODE (op1) == SYMBOL_REF)
1700 return TARGET_SMALL ? 3 : 4;
1702 if (GET_CODE (op1) == CONST)
1704 rtx offset = const0_rtx;
1706 op1 = eliminate_constant_term (op1, &offset);
1708 /* ??? These costs need rethinking... */
1709 if (GET_CODE (op1) == LABEL_REF)
1712 if (GET_CODE (op1) != SYMBOL_REF)
1715 if (INTVAL (offset) == 0)
1720 fatal_insn ("c4x_address_cost: Invalid addressing mode", addr);
1726 register rtx op0 = XEXP (addr, 0);
1727 register rtx op1 = XEXP (addr, 1);
1729 if (GET_CODE (op0) != REG)
1732 switch (GET_CODE (op1))
1738 /* This cost for REG+REG must be greater than the cost
1739 for REG if we want autoincrement addressing modes. */
1743 /* The following tries to improve GIV combination
1744 in strength reduce but appears not to help. */
1745 if (TARGET_DEVEL && IS_UINT5_CONST (INTVAL (op1)))
1748 if (IS_DISP1_CONST (INTVAL (op1)))
1751 if (! TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
1766 c4x_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
1768 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1771 if (mode == CC_NOOVmode
1772 && (code == LE || code == GE || code == LT || code == GT))
1775 cc_reg = gen_rtx_REG (mode, ST_REGNO);
1776 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
1777 gen_rtx_COMPARE (mode, x, y)));
1782 c4x_output_cbranch (const char *form, rtx seq)
1789 static char str[100];
1793 delay = XVECEXP (final_sequence, 0, 1);
1794 delayed = ! INSN_ANNULLED_BRANCH_P (seq);
1795 annultrue = INSN_ANNULLED_BRANCH_P (seq) && ! INSN_FROM_TARGET_P (delay);
1796 annulfalse = INSN_ANNULLED_BRANCH_P (seq) && INSN_FROM_TARGET_P (delay);
1799 cp = &str [strlen (str)];
1824 c4x_print_operand (FILE *file, rtx op, int letter)
1831 case '#': /* Delayed. */
1833 fprintf (file, "d");
1837 code = GET_CODE (op);
1840 case 'A': /* Direct address. */
1841 if (code == CONST_INT || code == SYMBOL_REF || code == CONST)
1842 fprintf (file, "@");
1845 case 'H': /* Sethi. */
1846 output_addr_const (file, op);
1849 case 'I': /* Reversed condition. */
1850 code = reverse_condition (code);
1853 case 'L': /* Log 2 of constant. */
1854 if (code != CONST_INT)
1855 fatal_insn ("c4x_print_operand: %%L inconsistency", op);
1856 fprintf (file, "%d", exact_log2 (INTVAL (op)));
1859 case 'N': /* Ones complement of small constant. */
1860 if (code != CONST_INT)
1861 fatal_insn ("c4x_print_operand: %%N inconsistency", op);
1862 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (op));
1865 case 'K': /* Generate ldp(k) if direct address. */
1868 && GET_CODE (XEXP (op, 0)) == LO_SUM
1869 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
1870 && REGNO (XEXP (XEXP (op, 0), 0)) == DP_REGNO)
1872 op1 = XEXP (XEXP (op, 0), 1);
1873 if (GET_CODE(op1) == CONST_INT || GET_CODE(op1) == SYMBOL_REF)
1875 fprintf (file, "\t%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1876 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1877 fprintf (file, "\n");
1882 case 'M': /* Generate ldp(k) if direct address. */
1883 if (! TARGET_SMALL /* Only used in asm statements. */
1885 && (GET_CODE (XEXP (op, 0)) == CONST
1886 || GET_CODE (XEXP (op, 0)) == SYMBOL_REF))
1888 fprintf (file, "%s\t@", TARGET_C3X ? "ldp" : "ldpk");
1889 output_address (XEXP (op, 0));
1890 fprintf (file, "\n\t");
1894 case 'O': /* Offset address. */
1895 if (code == MEM && c4x_autoinc_operand (op, Pmode))
1897 else if (code == MEM)
1898 output_address (XEXP (adjust_address (op, VOIDmode, 1), 0));
1899 else if (code == REG)
1900 fprintf (file, "%s", reg_names[REGNO (op) + 1]);
1902 fatal_insn ("c4x_print_operand: %%O inconsistency", op);
1905 case 'C': /* Call. */
1908 case 'U': /* Call/callu. */
1909 if (code != SYMBOL_REF)
1910 fprintf (file, "u");
1920 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
1922 fprintf (file, "%s", float_reg_names[REGNO (op)]);
1924 fprintf (file, "%s", reg_names[REGNO (op)]);
1928 output_address (XEXP (op, 0));
1935 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (op),
1936 sizeof (str), 0, 1);
1937 fprintf (file, "%s", str);
1942 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
1946 fprintf (file, "ne");
1950 fprintf (file, "eq");
1954 fprintf (file, "ge");
1958 fprintf (file, "gt");
1962 fprintf (file, "le");
1966 fprintf (file, "lt");
1970 fprintf (file, "hs");
1974 fprintf (file, "hi");
1978 fprintf (file, "ls");
1982 fprintf (file, "lo");
1986 output_addr_const (file, op);
1990 output_addr_const (file, XEXP (op, 0));
1997 fatal_insn ("c4x_print_operand: Bad operand case", op);
2004 c4x_print_operand_address (FILE *file, rtx addr)
2006 switch (GET_CODE (addr))
2009 fprintf (file, "*%s", reg_names[REGNO (addr)]);
2013 fprintf (file, "*--%s", reg_names[REGNO (XEXP (addr, 0))]);
2017 fprintf (file, "*%s++", reg_names[REGNO (XEXP (addr, 0))]);
2022 rtx op0 = XEXP (XEXP (addr, 1), 0);
2023 rtx op1 = XEXP (XEXP (addr, 1), 1);
2025 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2026 fprintf (file, "*%s++(%s)", reg_names[REGNO (op0)],
2027 reg_names[REGNO (op1)]);
2028 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2029 fprintf (file, "*%s++(" HOST_WIDE_INT_PRINT_DEC ")",
2030 reg_names[REGNO (op0)], INTVAL (op1));
2031 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2032 fprintf (file, "*%s--(" HOST_WIDE_INT_PRINT_DEC ")",
2033 reg_names[REGNO (op0)], -INTVAL (op1));
2034 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2035 fprintf (file, "*%s--(%s)", reg_names[REGNO (op0)],
2036 reg_names[REGNO (op1)]);
2038 fatal_insn ("c4x_print_operand_address: Bad post_modify", addr);
2044 rtx op0 = XEXP (XEXP (addr, 1), 0);
2045 rtx op1 = XEXP (XEXP (addr, 1), 1);
2047 if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
2048 fprintf (file, "*++%s(%s)", reg_names[REGNO (op0)],
2049 reg_names[REGNO (op1)]);
2050 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
2051 fprintf (file, "*++%s(" HOST_WIDE_INT_PRINT_DEC ")",
2052 reg_names[REGNO (op0)], INTVAL (op1));
2053 else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
2054 fprintf (file, "*--%s(" HOST_WIDE_INT_PRINT_DEC ")",
2055 reg_names[REGNO (op0)], -INTVAL (op1));
2056 else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
2057 fprintf (file, "*--%s(%s)", reg_names[REGNO (op0)],
2058 reg_names[REGNO (op1)]);
2060 fatal_insn ("c4x_print_operand_address: Bad pre_modify", addr);
2065 fprintf (file, "*++%s", reg_names[REGNO (XEXP (addr, 0))]);
2069 fprintf (file, "*%s--", reg_names[REGNO (XEXP (addr, 0))]);
2072 case PLUS: /* Indirect with displacement. */
2074 rtx op0 = XEXP (addr, 0);
2075 rtx op1 = XEXP (addr, 1);
2081 if (IS_INDEX_REG (op0))
2083 fprintf (file, "*+%s(%s)",
2084 reg_names[REGNO (op1)],
2085 reg_names[REGNO (op0)]); /* Index + base. */
2089 fprintf (file, "*+%s(%s)",
2090 reg_names[REGNO (op0)],
2091 reg_names[REGNO (op1)]); /* Base + index. */
2094 else if (INTVAL (op1) < 0)
2096 fprintf (file, "*-%s(" HOST_WIDE_INT_PRINT_DEC ")",
2097 reg_names[REGNO (op0)],
2098 -INTVAL (op1)); /* Base - displacement. */
2102 fprintf (file, "*+%s(" HOST_WIDE_INT_PRINT_DEC ")",
2103 reg_names[REGNO (op0)],
2104 INTVAL (op1)); /* Base + displacement. */
2108 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2114 rtx op0 = XEXP (addr, 0);
2115 rtx op1 = XEXP (addr, 1);
2117 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
2118 c4x_print_operand_address (file, op1);
2120 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2127 fprintf (file, "@");
2128 output_addr_const (file, addr);
2131 /* We shouldn't access CONST_INT addresses. */
2135 fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
2141 /* Return nonzero if the floating point operand will fit
2142 in the immediate field. */
2145 c4x_immed_float_p (rtx op)
2151 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2152 if (GET_MODE (op) == HFmode)
2153 REAL_VALUE_TO_TARGET_DOUBLE (r, convval);
2156 REAL_VALUE_TO_TARGET_SINGLE (r, convval[0]);
2160 /* Sign extend exponent. */
2161 exponent = (((convval[0] >> 24) & 0xff) ^ 0x80) - 0x80;
2162 if (exponent == -128)
2164 if ((convval[0] & 0x00000fff) != 0 || convval[1] != 0)
2165 return 0; /* Precision doesn't fit. */
2166 return (exponent <= 7) /* Positive exp. */
2167 && (exponent >= -7); /* Negative exp. */
2171 /* The last instruction in a repeat block cannot be a Bcond, DBcound,
2172 CALL, CALLCond, TRAPcond, RETIcond, RETScond, IDLE, RPTB or RPTS.
2174 None of the last four instructions from the bottom of the block can
2175 be a BcondD, BRD, DBcondD, RPTBD, LAJ, LAJcond, LATcond, BcondAF,
2176 BcondAT or RETIcondD.
2178 This routine scans the four previous insns for a jump insn, and if
2179 one is found, returns 1 so that we bung in a nop instruction.
2180 This simple minded strategy will add a nop, when it may not
2181 be required. Say when there is a JUMP_INSN near the end of the
2182 block that doesn't get converted into a delayed branch.
2184 Note that we cannot have a call insn, since we don't generate
2185 repeat loops with calls in them (although I suppose we could, but
2186 there's no benefit.)
2188 !!! FIXME. The rptb_top insn may be sucked into a SEQUENCE. */
2191 c4x_rptb_nop_p (rtx insn)
2196 /* Extract the start label from the jump pattern (rptb_end). */
2197 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2199 /* If there is a label at the end of the loop we must insert
2202 insn = previous_insn (insn);
2203 } while (GET_CODE (insn) == NOTE
2204 || GET_CODE (insn) == USE
2205 || GET_CODE (insn) == CLOBBER);
2206 if (GET_CODE (insn) == CODE_LABEL)
2209 for (i = 0; i < 4; i++)
2211 /* Search back for prev non-note and non-label insn. */
2212 while (GET_CODE (insn) == NOTE || GET_CODE (insn) == CODE_LABEL
2213 || GET_CODE (insn) == USE || GET_CODE (insn) == CLOBBER)
2215 if (insn == start_label)
2218 insn = previous_insn (insn);
2221 /* If we have a jump instruction we should insert a NOP. If we
2222 hit repeat block top we should only insert a NOP if the loop
2224 if (GET_CODE (insn) == JUMP_INSN)
2226 insn = previous_insn (insn);
2232 /* The C4x looping instruction needs to be emitted at the top of the
2233 loop. Emitting the true RTL for a looping instruction at the top of
2234 the loop can cause problems with flow analysis. So instead, a dummy
2235 doloop insn is emitted at the end of the loop. This routine checks
2236 for the presence of this doloop insn and then searches back to the
2237 top of the loop, where it inserts the true looping insn (provided
2238 there are no instructions in the loop which would cause problems).
2239 Any additional labels can be emitted at this point. In addition, if
2240 the desired loop count register was not allocated, this routine does
2243 Before we can create a repeat block looping instruction we have to
2244 verify that there are no jumps outside the loop and no jumps outside
2245 the loop go into this loop. This can happen in the basic blocks reorder
2246 pass. The C4x cpu can not handle this. */
2249 c4x_label_ref_used_p (rtx x, rtx code_label)
2258 code = GET_CODE (x);
2259 if (code == LABEL_REF)
2260 return INSN_UID (XEXP (x,0)) == INSN_UID (code_label);
2262 fmt = GET_RTX_FORMAT (code);
2263 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2267 if (c4x_label_ref_used_p (XEXP (x, i), code_label))
2270 else if (fmt[i] == 'E')
2271 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2272 if (c4x_label_ref_used_p (XVECEXP (x, i, j), code_label))
2280 c4x_rptb_valid_p (rtx insn, rtx start_label)
2286 /* Find the start label. */
2287 for (; insn; insn = PREV_INSN (insn))
2288 if (insn == start_label)
2291 /* Note found then we can not use a rptb or rpts. The label was
2292 probably moved by the basic block reorder pass. */
2297 /* If any jump jumps inside this block then we must fail. */
2298 for (insn = PREV_INSN (start); insn; insn = PREV_INSN (insn))
2300 if (GET_CODE (insn) == CODE_LABEL)
2302 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2303 if (GET_CODE (tmp) == JUMP_INSN
2304 && c4x_label_ref_used_p (tmp, insn))
2308 for (insn = NEXT_INSN (end); insn; insn = NEXT_INSN (insn))
2310 if (GET_CODE (insn) == CODE_LABEL)
2312 for (tmp = NEXT_INSN (start); tmp != end; tmp = NEXT_INSN(tmp))
2313 if (GET_CODE (tmp) == JUMP_INSN
2314 && c4x_label_ref_used_p (tmp, insn))
2318 /* If any jump jumps outside this block then we must fail. */
2319 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
2321 if (GET_CODE (insn) == CODE_LABEL)
2323 for (tmp = NEXT_INSN (end); tmp; tmp = NEXT_INSN(tmp))
2324 if (GET_CODE (tmp) == JUMP_INSN
2325 && c4x_label_ref_used_p (tmp, insn))
2327 for (tmp = PREV_INSN (start); tmp; tmp = PREV_INSN(tmp))
2328 if (GET_CODE (tmp) == JUMP_INSN
2329 && c4x_label_ref_used_p (tmp, insn))
2334 /* All checks OK. */
2340 c4x_rptb_insert (rtx insn)
2344 rtx new_start_label;
2347 /* If the count register has not been allocated to RC, say if
2348 there is a movstr pattern in the loop, then do not insert a
2349 RPTB instruction. Instead we emit a decrement and branch
2350 at the end of the loop. */
2351 count_reg = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0), 0);
2352 if (REGNO (count_reg) != RC_REGNO)
2355 /* Extract the start label from the jump pattern (rptb_end). */
2356 start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
2358 if (! c4x_rptb_valid_p (insn, start_label))
2360 /* We can not use the rptb insn. Replace it so reorg can use
2361 the delay slots of the jump insn. */
2362 emit_insn_before (gen_addqi3 (count_reg, count_reg, constm1_rtx), insn);
2363 emit_insn_before (gen_cmpqi (count_reg, const0_rtx), insn);
2364 emit_insn_before (gen_bge (start_label), insn);
2365 LABEL_NUSES (start_label)++;
2370 end_label = gen_label_rtx ();
2371 LABEL_NUSES (end_label)++;
2372 emit_label_after (end_label, insn);
2374 new_start_label = gen_label_rtx ();
2375 LABEL_NUSES (new_start_label)++;
2377 for (; insn; insn = PREV_INSN (insn))
2379 if (insn == start_label)
2381 if (GET_CODE (insn) == JUMP_INSN &&
2382 JUMP_LABEL (insn) == start_label)
2383 redirect_jump (insn, new_start_label, 0);
2386 fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
2388 emit_label_after (new_start_label, insn);
2390 if (TARGET_RPTS && c4x_rptb_rpts_p (PREV_INSN (insn), 0))
2391 emit_insn_after (gen_rpts_top (new_start_label, end_label), insn);
2393 emit_insn_after (gen_rptb_top (new_start_label, end_label), insn);
2394 if (LABEL_NUSES (start_label) == 0)
2395 delete_insn (start_label);
2399 /* We need to use direct addressing for large constants and addresses
2400 that cannot fit within an instruction. We must check for these
2401 after after the final jump optimization pass, since this may
2402 introduce a local_move insn for a SYMBOL_REF. This pass
2403 must come before delayed branch slot filling since it can generate
2404 additional instructions.
2406 This function also fixes up RTPB style loops that didn't get RC
2407 allocated as the loop counter. */
2414 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2416 /* Look for insn. */
2419 int insn_code_number;
2422 insn_code_number = recog_memoized (insn);
2424 if (insn_code_number < 0)
2427 /* Insert the RTX for RPTB at the top of the loop
2428 and a label at the end of the loop. */
2429 if (insn_code_number == CODE_FOR_rptb_end)
2430 c4x_rptb_insert(insn);
2432 /* We need to split the insn here. Otherwise the calls to
2433 force_const_mem will not work for load_immed_address. */
2436 /* Don't split the insn if it has been deleted. */
2437 if (! INSN_DELETED_P (old))
2438 insn = try_split (PATTERN(old), old, 1);
2440 /* When not optimizing, the old insn will be still left around
2441 with only the 'deleted' bit set. Transform it into a note
2442 to avoid confusion of subsequent processing. */
2443 if (INSN_DELETED_P (old))
2445 PUT_CODE (old, NOTE);
2446 NOTE_LINE_NUMBER (old) = NOTE_INSN_DELETED;
2447 NOTE_SOURCE_FILE (old) = 0;
2455 c4x_a_register (rtx op)
2457 return REG_P (op) && IS_ADDR_OR_PSEUDO_REG (op);
2462 c4x_x_register (rtx op)
2464 return REG_P (op) && IS_INDEX_OR_PSEUDO_REG (op);
2469 c4x_immed_int_constant (rtx op)
2471 if (GET_CODE (op) != CONST_INT)
2474 return GET_MODE (op) == VOIDmode
2475 || GET_MODE_CLASS (GET_MODE (op)) == MODE_INT
2476 || GET_MODE_CLASS (GET_MODE (op)) == MODE_PARTIAL_INT;
2481 c4x_immed_float_constant (rtx op)
2483 if (GET_CODE (op) != CONST_DOUBLE)
2486 /* Do not check if the CONST_DOUBLE is in memory. If there is a MEM
2487 present this only means that a MEM rtx has been generated. It does
2488 not mean the rtx is really in memory. */
2490 return GET_MODE (op) == QFmode || GET_MODE (op) == HFmode;
2495 c4x_shiftable_constant (rtx op)
2499 int val = INTVAL (op);
2501 for (i = 0; i < 16; i++)
2506 mask = ((0xffff >> i) << 16) | 0xffff;
2507 if (IS_INT16_CONST (val & (1 << 31) ? (val >> i) | ~mask
2508 : (val >> i) & mask))
2515 c4x_H_constant (rtx op)
2517 return c4x_immed_float_constant (op) && c4x_immed_float_p (op);
2522 c4x_I_constant (rtx op)
2524 return c4x_immed_int_constant (op) && IS_INT16_CONST (INTVAL (op));
2529 c4x_J_constant (rtx op)
2533 return c4x_immed_int_constant (op) && IS_INT8_CONST (INTVAL (op));
2538 c4x_K_constant (rtx op)
2540 if (TARGET_C3X || ! c4x_immed_int_constant (op))
2542 return IS_INT5_CONST (INTVAL (op));
2547 c4x_L_constant (rtx op)
2549 return c4x_immed_int_constant (op) && IS_UINT16_CONST (INTVAL (op));
2554 c4x_N_constant (rtx op)
2556 return c4x_immed_int_constant (op) && IS_NOT_UINT16_CONST (INTVAL (op));
2561 c4x_O_constant (rtx op)
2563 return c4x_immed_int_constant (op) && IS_HIGH_CONST (INTVAL (op));
2567 /* The constraints do not have to check the register class,
2568 except when needed to discriminate between the constraints.
2569 The operand has been checked by the predicates to be valid. */
2571 /* ARx + 9-bit signed const or IRn
2572 *ARx, *+ARx(n), *-ARx(n), *+ARx(IRn), *-Arx(IRn) for -256 < n < 256
2573 We don't include the pre/post inc/dec forms here since
2574 they are handled by the <> constraints. */
2577 c4x_Q_constraint (rtx op)
2579 enum machine_mode mode = GET_MODE (op);
2581 if (GET_CODE (op) != MEM)
2584 switch (GET_CODE (op))
2591 rtx op0 = XEXP (op, 0);
2592 rtx op1 = XEXP (op, 1);
2600 if (GET_CODE (op1) != CONST_INT)
2603 /* HImode and HFmode must be offsettable. */
2604 if (mode == HImode || mode == HFmode)
2605 return IS_DISP8_OFF_CONST (INTVAL (op1));
2607 return IS_DISP8_CONST (INTVAL (op1));
2618 /* ARx + 5-bit unsigned const
2619 *ARx, *+ARx(n) for n < 32. */
2622 c4x_R_constraint (rtx op)
2624 enum machine_mode mode = GET_MODE (op);
2628 if (GET_CODE (op) != MEM)
2631 switch (GET_CODE (op))
2638 rtx op0 = XEXP (op, 0);
2639 rtx op1 = XEXP (op, 1);
2644 if (GET_CODE (op1) != CONST_INT)
2647 /* HImode and HFmode must be offsettable. */
2648 if (mode == HImode || mode == HFmode)
2649 return IS_UINT5_CONST (INTVAL (op1) + 1);
2651 return IS_UINT5_CONST (INTVAL (op1));
2663 c4x_R_indirect (rtx op)
2665 enum machine_mode mode = GET_MODE (op);
2667 if (TARGET_C3X || GET_CODE (op) != MEM)
2671 switch (GET_CODE (op))
2674 return IS_ADDR_OR_PSEUDO_REG (op);
2678 rtx op0 = XEXP (op, 0);
2679 rtx op1 = XEXP (op, 1);
2681 /* HImode and HFmode must be offsettable. */
2682 if (mode == HImode || mode == HFmode)
2683 return IS_ADDR_OR_PSEUDO_REG (op0)
2684 && GET_CODE (op1) == CONST_INT
2685 && IS_UINT5_CONST (INTVAL (op1) + 1);
2688 && IS_ADDR_OR_PSEUDO_REG (op0)
2689 && GET_CODE (op1) == CONST_INT
2690 && IS_UINT5_CONST (INTVAL (op1));
2701 /* ARx + 1-bit unsigned const or IRn
2702 *ARx, *+ARx(1), *-ARx(1), *+ARx(IRn), *-Arx(IRn)
2703 We don't include the pre/post inc/dec forms here since
2704 they are handled by the <> constraints. */
2707 c4x_S_constraint (rtx op)
2709 enum machine_mode mode = GET_MODE (op);
2710 if (GET_CODE (op) != MEM)
2713 switch (GET_CODE (op))
2721 rtx op0 = XEXP (op, 0);
2722 rtx op1 = XEXP (op, 1);
2724 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2725 || (op0 != XEXP (op1, 0)))
2728 op0 = XEXP (op1, 0);
2729 op1 = XEXP (op1, 1);
2730 return REG_P (op0) && REG_P (op1);
2731 /* Pre or post_modify with a displacement of 0 or 1
2732 should not be generated. */
2738 rtx op0 = XEXP (op, 0);
2739 rtx op1 = XEXP (op, 1);
2747 if (GET_CODE (op1) != CONST_INT)
2750 /* HImode and HFmode must be offsettable. */
2751 if (mode == HImode || mode == HFmode)
2752 return IS_DISP1_OFF_CONST (INTVAL (op1));
2754 return IS_DISP1_CONST (INTVAL (op1));
2766 c4x_S_indirect (rtx op)
2768 enum machine_mode mode = GET_MODE (op);
2769 if (GET_CODE (op) != MEM)
2773 switch (GET_CODE (op))
2777 if (mode != QImode && mode != QFmode)
2784 return IS_ADDR_OR_PSEUDO_REG (op);
2789 rtx op0 = XEXP (op, 0);
2790 rtx op1 = XEXP (op, 1);
2792 if (mode != QImode && mode != QFmode)
2795 if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
2796 || (op0 != XEXP (op1, 0)))
2799 op0 = XEXP (op1, 0);
2800 op1 = XEXP (op1, 1);
2801 return REG_P (op0) && IS_ADDR_OR_PSEUDO_REG (op0)
2802 && REG_P (op1) && IS_INDEX_OR_PSEUDO_REG (op1);
2803 /* Pre or post_modify with a displacement of 0 or 1
2804 should not be generated. */
2809 rtx op0 = XEXP (op, 0);
2810 rtx op1 = XEXP (op, 1);
2814 /* HImode and HFmode must be offsettable. */
2815 if (mode == HImode || mode == HFmode)
2816 return IS_ADDR_OR_PSEUDO_REG (op0)
2817 && GET_CODE (op1) == CONST_INT
2818 && IS_DISP1_OFF_CONST (INTVAL (op1));
2821 return (IS_INDEX_OR_PSEUDO_REG (op1)
2822 && IS_ADDR_OR_PSEUDO_REG (op0))
2823 || (IS_ADDR_OR_PSEUDO_REG (op1)
2824 && IS_INDEX_OR_PSEUDO_REG (op0));
2826 return IS_ADDR_OR_PSEUDO_REG (op0)
2827 && GET_CODE (op1) == CONST_INT
2828 && IS_DISP1_CONST (INTVAL (op1));
2840 /* Direct memory operand. */
2843 c4x_T_constraint (rtx op)
2845 if (GET_CODE (op) != MEM)
2849 if (GET_CODE (op) != LO_SUM)
2851 /* Allow call operands. */
2852 return GET_CODE (op) == SYMBOL_REF
2853 && GET_MODE (op) == Pmode
2854 && SYMBOL_REF_FUNCTION_P (op);
2857 /* HImode and HFmode are not offsettable. */
2858 if (GET_MODE (op) == HImode || GET_CODE (op) == HFmode)
2861 if ((GET_CODE (XEXP (op, 0)) == REG)
2862 && (REGNO (XEXP (op, 0)) == DP_REGNO))
2863 return c4x_U_constraint (XEXP (op, 1));
2869 /* Symbolic operand. */
2872 c4x_U_constraint (rtx op)
2874 /* Don't allow direct addressing to an arbitrary constant. */
2875 return GET_CODE (op) == CONST
2876 || GET_CODE (op) == SYMBOL_REF
2877 || GET_CODE (op) == LABEL_REF;
2882 c4x_autoinc_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2884 if (GET_CODE (op) == MEM)
2886 enum rtx_code code = GET_CODE (XEXP (op, 0));
2892 || code == PRE_MODIFY
2893 || code == POST_MODIFY
2901 /* Match any operand. */
2904 any_operand (register rtx op ATTRIBUTE_UNUSED,
2905 enum machine_mode mode ATTRIBUTE_UNUSED)
2911 /* Nonzero if OP is a floating point value with value 0.0. */
2914 fp_zero_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2918 if (GET_CODE (op) != CONST_DOUBLE)
2920 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2921 return REAL_VALUES_EQUAL (r, dconst0);
2926 const_operand (register rtx op, register enum machine_mode mode)
2932 if (GET_CODE (op) != CONST_DOUBLE
2933 || GET_MODE (op) != mode
2934 || GET_MODE_CLASS (mode) != MODE_FLOAT)
2937 return c4x_immed_float_p (op);
2943 if (GET_CODE (op) == CONSTANT_P_RTX)
2946 if (GET_CODE (op) != CONST_INT
2947 || (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
2948 || GET_MODE_CLASS (mode) != MODE_INT)
2951 return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
2963 stik_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2965 return c4x_K_constant (op);
2970 not_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2972 return c4x_N_constant (op);
2977 reg_operand (rtx op, enum machine_mode mode)
2979 if (GET_CODE (op) == SUBREG
2980 && GET_MODE (op) == QFmode)
2982 return register_operand (op, mode);
2987 mixed_subreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2989 /* Allow (subreg:HF (reg:HI)) that be generated for a union of an
2990 int and a long double. */
2991 if (GET_CODE (op) == SUBREG
2992 && (GET_MODE (op) == QFmode)
2993 && (GET_MODE (SUBREG_REG (op)) == QImode
2994 || GET_MODE (SUBREG_REG (op)) == HImode))
3001 reg_imm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3003 if (REG_P (op) || CONSTANT_P (op))
3010 not_modify_reg (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3012 if (REG_P (op) || CONSTANT_P (op))
3014 if (GET_CODE (op) != MEM)
3017 switch (GET_CODE (op))
3024 rtx op0 = XEXP (op, 0);
3025 rtx op1 = XEXP (op, 1);
3030 if (REG_P (op1) || GET_CODE (op1) == CONST_INT)
3036 rtx op0 = XEXP (op, 0);
3038 if (REG_P (op0) && REGNO (op0) == DP_REGNO)
3056 not_rc_reg (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3058 if (REG_P (op) && REGNO (op) == RC_REGNO)
3064 /* Extended precision register R0-R1. */
3067 r0r1_reg_operand (rtx op, enum machine_mode mode)
3069 if (! reg_operand (op, mode))
3071 if (GET_CODE (op) == SUBREG)
3072 op = SUBREG_REG (op);
3073 return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
3077 /* Extended precision register R2-R3. */
3080 r2r3_reg_operand (rtx op, enum machine_mode mode)
3082 if (! reg_operand (op, mode))
3084 if (GET_CODE (op) == SUBREG)
3085 op = SUBREG_REG (op);
3086 return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
3090 /* Low extended precision register R0-R7. */
3093 ext_low_reg_operand (rtx op, enum machine_mode mode)
3095 if (! reg_operand (op, mode))
3097 if (GET_CODE (op) == SUBREG)
3098 op = SUBREG_REG (op);
3099 return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
3103 /* Extended precision register. */
3106 ext_reg_operand (rtx op, enum machine_mode mode)
3108 if (! reg_operand (op, mode))
3110 if (GET_CODE (op) == SUBREG)
3111 op = SUBREG_REG (op);
3114 return IS_EXT_OR_PSEUDO_REG (op);
3118 /* Standard precision register. */
3121 std_reg_operand (rtx op, enum machine_mode mode)
3123 if (! reg_operand (op, mode))
3125 if (GET_CODE (op) == SUBREG)
3126 op = SUBREG_REG (op);
3127 return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
3130 /* Standard precision or normal register. */
3133 std_or_reg_operand (rtx op, enum machine_mode mode)
3135 if (reload_in_progress)
3136 return std_reg_operand (op, mode);
3137 return reg_operand (op, mode);
3140 /* Address register. */
3143 addr_reg_operand (rtx op, enum machine_mode mode)
3145 if (! reg_operand (op, mode))
3147 return c4x_a_register (op);
3151 /* Index register. */
3154 index_reg_operand (rtx op, enum machine_mode mode)
3156 if (! reg_operand (op, mode))
3158 if (GET_CODE (op) == SUBREG)
3159 op = SUBREG_REG (op);
3160 return c4x_x_register (op);
3167 dp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3169 return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
3176 sp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3178 return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
3185 st_reg_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3187 return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
3194 rc_reg_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3196 return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
3201 call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3203 return (REG_P (op) || symbolic_address_operand (op, mode));
3207 /* Symbolic address operand. */
3210 symbolic_address_operand (register rtx op,
3211 enum machine_mode mode ATTRIBUTE_UNUSED)
3213 switch (GET_CODE (op))
3225 /* Check dst operand of a move instruction. */
3228 dst_operand (rtx op, enum machine_mode mode)
3230 if (GET_CODE (op) == SUBREG
3231 && mixed_subreg_operand (op, mode))
3235 return reg_operand (op, mode);
3237 return nonimmediate_operand (op, mode);
3241 /* Check src operand of two operand arithmetic instructions. */
3244 src_operand (rtx op, enum machine_mode mode)
3246 if (GET_CODE (op) == SUBREG
3247 && mixed_subreg_operand (op, mode))
3251 return reg_operand (op, mode);
3253 if (mode == VOIDmode)
3254 mode = GET_MODE (op);
3256 if (GET_CODE (op) == CONST_INT)
3257 return (mode == QImode || mode == Pmode || mode == HImode)
3258 && c4x_I_constant (op);
3260 /* We don't like CONST_DOUBLE integers. */
3261 if (GET_CODE (op) == CONST_DOUBLE)
3262 return c4x_H_constant (op);
3264 /* Disallow symbolic addresses. Only the predicate
3265 symbolic_address_operand will match these. */
3266 if (GET_CODE (op) == SYMBOL_REF
3267 || GET_CODE (op) == LABEL_REF
3268 || GET_CODE (op) == CONST)
3271 /* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
3272 access to symbolic addresses. These operands will get forced
3273 into a register and the movqi expander will generate a
3274 HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
3275 if (GET_CODE (op) == MEM
3276 && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3277 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3278 || GET_CODE (XEXP (op, 0)) == CONST)))
3279 return !TARGET_EXPOSE_LDP &&
3280 ! TARGET_LOAD_DIRECT_MEMS && GET_MODE (op) == mode;
3282 return general_operand (op, mode);
3287 src_hi_operand (rtx op, enum machine_mode mode)
3289 if (c4x_O_constant (op))
3291 return src_operand (op, mode);
3295 /* Check src operand of two operand logical instructions. */
3298 lsrc_operand (rtx op, enum machine_mode mode)
3300 if (mode == VOIDmode)
3301 mode = GET_MODE (op);
3303 if (mode != QImode && mode != Pmode)
3304 fatal_insn ("mode not QImode", op);
3306 if (GET_CODE (op) == CONST_INT)
3307 return c4x_L_constant (op) || c4x_J_constant (op);
3309 return src_operand (op, mode);
3313 /* Check src operand of two operand tricky instructions. */
3316 tsrc_operand (rtx op, enum machine_mode mode)
3318 if (mode == VOIDmode)
3319 mode = GET_MODE (op);
3321 if (mode != QImode && mode != Pmode)
3322 fatal_insn ("mode not QImode", op);
3324 if (GET_CODE (op) == CONST_INT)
3325 return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
3327 return src_operand (op, mode);
3331 /* Check src operand of two operand non immedidate instructions. */
3334 nonimmediate_src_operand (rtx op, enum machine_mode mode)
3336 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3339 return src_operand (op, mode);
3343 /* Check logical src operand of two operand non immedidate instructions. */
3346 nonimmediate_lsrc_operand (rtx op, enum machine_mode mode)
3348 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
3351 return lsrc_operand (op, mode);
3356 reg_or_const_operand (rtx op, enum machine_mode mode)
3358 return reg_operand (op, mode) || const_operand (op, mode);
3362 /* Check for indirect operands allowable in parallel instruction. */
3365 par_ind_operand (rtx op, enum machine_mode mode)
3367 if (mode != VOIDmode && mode != GET_MODE (op))
3370 return c4x_S_indirect (op);
3374 /* Check for operands allowable in parallel instruction. */
3377 parallel_operand (rtx op, enum machine_mode mode)
3379 return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
3384 c4x_S_address_parse (rtx op, int *base, int *incdec, int *index, int *disp)
3391 if (GET_CODE (op) != MEM)
3392 fatal_insn ("invalid indirect memory address", op);
3395 switch (GET_CODE (op))
3398 *base = REGNO (XEXP (op, 0));
3404 *base = REGNO (XEXP (op, 0));
3410 *base = REGNO (XEXP (op, 0));
3416 *base = REGNO (XEXP (op, 0));
3422 *base = REGNO (XEXP (op, 0));
3423 if (REG_P (XEXP (XEXP (op, 1), 1)))
3425 *index = REGNO (XEXP (XEXP (op, 1), 1));
3426 *disp = 0; /* ??? */
3429 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3434 *base = REGNO (XEXP (op, 0));
3435 if (REG_P (XEXP (XEXP (op, 1), 1)))
3437 *index = REGNO (XEXP (XEXP (op, 1), 1));
3438 *disp = 1; /* ??? */
3441 *disp = INTVAL (XEXP (XEXP (op, 1), 1));
3452 rtx op0 = XEXP (op, 0);
3453 rtx op1 = XEXP (op, 1);
3455 if (c4x_a_register (op0))
3457 if (c4x_x_register (op1))
3459 *base = REGNO (op0);
3460 *index = REGNO (op1);
3463 else if ((GET_CODE (op1) == CONST_INT
3464 && IS_DISP1_CONST (INTVAL (op1))))
3466 *base = REGNO (op0);
3467 *disp = INTVAL (op1);
3471 else if (c4x_x_register (op0) && c4x_a_register (op1))
3473 *base = REGNO (op1);
3474 *index = REGNO (op0);
3481 fatal_insn ("invalid indirect (S) memory address", op);
3487 c4x_address_conflict (rtx op0, rtx op1, int store0, int store1)
3498 if (MEM_VOLATILE_P (op0) && MEM_VOLATILE_P (op1))
3501 c4x_S_address_parse (op0, &base0, &incdec0, &index0, &disp0);
3502 c4x_S_address_parse (op1, &base1, &incdec1, &index1, &disp1);
3504 if (store0 && store1)
3506 /* If we have two stores in parallel to the same address, then
3507 the C4x only executes one of the stores. This is unlikely to
3508 cause problems except when writing to a hardware device such
3509 as a FIFO since the second write will be lost. The user
3510 should flag the hardware location as being volatile so that
3511 we don't do this optimization. While it is unlikely that we
3512 have an aliased address if both locations are not marked
3513 volatile, it is probably safer to flag a potential conflict
3514 if either location is volatile. */
3515 if (! flag_argument_noalias)
3517 if (MEM_VOLATILE_P (op0) || MEM_VOLATILE_P (op1))
3522 /* If have a parallel load and a store to the same address, the load
3523 is performed first, so there is no conflict. Similarly, there is
3524 no conflict if have parallel loads from the same address. */
3526 /* Cannot use auto increment or auto decrement twice for same
3528 if (base0 == base1 && incdec0 && incdec0)
3531 /* It might be too confusing for GCC if we have use a base register
3532 with a side effect and a memory reference using the same register
3534 if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
3537 /* We can not optimize the case where op1 and op2 refer to the same
3539 if (base0 == base1 && disp0 == disp1 && index0 == index1)
3547 /* Check for while loop inside a decrement and branch loop. */
3550 c4x_label_conflict (rtx insn, rtx jump, rtx db)
3554 if (GET_CODE (insn) == CODE_LABEL)
3556 if (CODE_LABEL_NUMBER (jump) == CODE_LABEL_NUMBER (insn))
3558 if (CODE_LABEL_NUMBER (db) == CODE_LABEL_NUMBER (insn))
3561 insn = PREV_INSN (insn);
3567 /* Validate combination of operands for parallel load/store instructions. */
3570 valid_parallel_load_store (rtx *operands,
3571 enum machine_mode mode ATTRIBUTE_UNUSED)
3573 rtx op0 = operands[0];
3574 rtx op1 = operands[1];
3575 rtx op2 = operands[2];
3576 rtx op3 = operands[3];
3578 if (GET_CODE (op0) == SUBREG)
3579 op0 = SUBREG_REG (op0);
3580 if (GET_CODE (op1) == SUBREG)
3581 op1 = SUBREG_REG (op1);
3582 if (GET_CODE (op2) == SUBREG)
3583 op2 = SUBREG_REG (op2);
3584 if (GET_CODE (op3) == SUBREG)
3585 op3 = SUBREG_REG (op3);
3587 /* The patterns should only allow ext_low_reg_operand() or
3588 par_ind_operand() operands. Thus of the 4 operands, only 2
3589 should be REGs and the other 2 should be MEMs. */
3591 /* This test prevents the multipack pass from using this pattern if
3592 op0 is used as an index or base register in op2 or op3, since
3593 this combination will require reloading. */
3594 if (GET_CODE (op0) == REG
3595 && ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
3596 || (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
3600 if (GET_CODE (op0) == REG && GET_CODE (op2) == REG)
3601 return (REGNO (op0) != REGNO (op2))
3602 && GET_CODE (op1) == MEM && GET_CODE (op3) == MEM
3603 && ! c4x_address_conflict (op1, op3, 0, 0);
3606 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG)
3607 return GET_CODE (op0) == MEM && GET_CODE (op2) == MEM
3608 && ! c4x_address_conflict (op0, op2, 1, 1);
3611 if (GET_CODE (op0) == REG && GET_CODE (op3) == REG)
3612 return GET_CODE (op1) == MEM && GET_CODE (op2) == MEM
3613 && ! c4x_address_conflict (op1, op2, 0, 1);
3616 if (GET_CODE (op1) == REG && GET_CODE (op2) == REG)
3617 return GET_CODE (op0) == MEM && GET_CODE (op3) == MEM
3618 && ! c4x_address_conflict (op0, op3, 1, 0);
3625 valid_parallel_operands_4 (rtx *operands,
3626 enum machine_mode mode ATTRIBUTE_UNUSED)
3628 rtx op0 = operands[0];
3629 rtx op2 = operands[2];
3631 if (GET_CODE (op0) == SUBREG)
3632 op0 = SUBREG_REG (op0);
3633 if (GET_CODE (op2) == SUBREG)
3634 op2 = SUBREG_REG (op2);
3636 /* This test prevents the multipack pass from using this pattern if
3637 op0 is used as an index or base register in op2, since this combination
3638 will require reloading. */
3639 if (GET_CODE (op0) == REG
3640 && GET_CODE (op2) == MEM
3641 && reg_mentioned_p (op0, XEXP (op2, 0)))
3649 valid_parallel_operands_5 (rtx *operands,
3650 enum machine_mode mode ATTRIBUTE_UNUSED)
3653 rtx op0 = operands[0];
3654 rtx op1 = operands[1];
3655 rtx op2 = operands[2];
3656 rtx op3 = operands[3];
3658 if (GET_CODE (op0) == SUBREG)
3659 op0 = SUBREG_REG (op0);
3660 if (GET_CODE (op1) == SUBREG)
3661 op1 = SUBREG_REG (op1);
3662 if (GET_CODE (op2) == SUBREG)
3663 op2 = SUBREG_REG (op2);
3665 /* The patterns should only allow ext_low_reg_operand() or
3666 par_ind_operand() operands. Operands 1 and 2 may be commutative
3667 but only one of them can be a register. */
3668 if (GET_CODE (op1) == REG)
3670 if (GET_CODE (op2) == REG)
3676 /* This test prevents the multipack pass from using this pattern if
3677 op0 is used as an index or base register in op3, since this combination
3678 will require reloading. */
3679 if (GET_CODE (op0) == REG
3680 && GET_CODE (op3) == MEM
3681 && reg_mentioned_p (op0, XEXP (op3, 0)))
3689 valid_parallel_operands_6 (rtx *operands,
3690 enum machine_mode mode ATTRIBUTE_UNUSED)
3693 rtx op0 = operands[0];
3694 rtx op1 = operands[1];
3695 rtx op2 = operands[2];
3696 rtx op4 = operands[4];
3697 rtx op5 = operands[5];
3699 if (GET_CODE (op1) == SUBREG)
3700 op1 = SUBREG_REG (op1);
3701 if (GET_CODE (op2) == SUBREG)
3702 op2 = SUBREG_REG (op2);
3703 if (GET_CODE (op4) == SUBREG)
3704 op4 = SUBREG_REG (op4);
3705 if (GET_CODE (op5) == SUBREG)
3706 op5 = SUBREG_REG (op5);
3708 /* The patterns should only allow ext_low_reg_operand() or
3709 par_ind_operand() operands. Thus of the 4 input operands, only 2
3710 should be REGs and the other 2 should be MEMs. */
3712 if (GET_CODE (op1) == REG)
3714 if (GET_CODE (op2) == REG)
3716 if (GET_CODE (op4) == REG)
3718 if (GET_CODE (op5) == REG)
3721 /* The new C30/C40 silicon dies allow 3 regs of the 4 input operands.
3722 Perhaps we should count the MEMs as well? */
3726 /* This test prevents the multipack pass from using this pattern if
3727 op0 is used as an index or base register in op4 or op5, since
3728 this combination will require reloading. */
3729 if (GET_CODE (op0) == REG
3730 && ((GET_CODE (op4) == MEM && reg_mentioned_p (op0, XEXP (op4, 0)))
3731 || (GET_CODE (op5) == MEM && reg_mentioned_p (op0, XEXP (op5, 0)))))
3738 /* Validate combination of src operands. Note that the operands have
3739 been screened by the src_operand predicate. We just have to check
3740 that the combination of operands is valid. If FORCE is set, ensure
3741 that the destination regno is valid if we have a 2 operand insn. */
3744 c4x_valid_operands (enum rtx_code code, rtx *operands,
3745 enum machine_mode mode ATTRIBUTE_UNUSED,
3751 enum rtx_code code1;
3752 enum rtx_code code2;
3755 /* FIXME, why can't we tighten the operands for IF_THEN_ELSE? */
3756 if (code == IF_THEN_ELSE)
3757 return 1 || (operands[0] == operands[2] || operands[0] == operands[3]);
3759 if (code == COMPARE)
3772 if (GET_CODE (op0) == SUBREG)
3773 op0 = SUBREG_REG (op0);
3774 if (GET_CODE (op1) == SUBREG)
3775 op1 = SUBREG_REG (op1);
3776 if (GET_CODE (op2) == SUBREG)
3777 op2 = SUBREG_REG (op2);
3779 code1 = GET_CODE (op1);
3780 code2 = GET_CODE (op2);
3783 if (code1 == REG && code2 == REG)
3786 if (code1 == MEM && code2 == MEM)
3788 if (c4x_S_indirect (op1) && c4x_S_indirect (op2))
3790 return c4x_R_indirect (op1) && c4x_R_indirect (op2);
3793 /* We cannot handle two MEMs or two CONSTS, etc. */
3802 if (c4x_J_constant (op2) && c4x_R_indirect (op1))
3807 if (! c4x_H_constant (op2))
3811 /* Any valid memory operand screened by src_operand is OK. */
3815 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3816 into a stack slot memory address comprising a PLUS and a
3822 fatal_insn ("c4x_valid_operands: Internal error", op2);
3826 if (GET_CODE (op0) == SCRATCH)
3832 /* Check that we have a valid destination register for a two operand
3834 return ! force || code == COMPARE || REGNO (op1) == REGNO (op0);
3838 /* Check non-commutative operators. */
3839 if (code == ASHIFTRT || code == LSHIFTRT
3840 || code == ASHIFT || code == COMPARE)
3842 && (c4x_S_indirect (op1) || c4x_R_indirect (op1));
3845 /* Assume MINUS is commutative since the subtract patterns
3846 also support the reverse subtract instructions. Since op1
3847 is not a register, and op2 is a register, op1 can only
3848 be a restricted memory operand for a shift instruction. */
3857 if (! c4x_H_constant (op1))
3861 /* Any valid memory operand screened by src_operand is OK. */
3865 /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
3866 into a stack slot memory address comprising a PLUS and a
3876 if (GET_CODE (op0) == SCRATCH)
3882 /* Check that we have a valid destination register for a two operand
3884 return ! force || REGNO (op1) == REGNO (op0);
3887 if (c4x_J_constant (op1) && c4x_R_indirect (op2))
3894 int valid_operands (enum rtx_code code, rtx *operands, enum machine_mode mode)
3897 /* If we are not optimizing then we have to let anything go and let
3898 reload fix things up. instantiate_decl in function.c can produce
3899 invalid insns by changing the offset of a memory operand from a
3900 valid one into an invalid one, when the second operand is also a
3901 memory operand. The alternative is not to allow two memory
3902 operands for an insn when not optimizing. The problem only rarely
3903 occurs, for example with the C-torture program DFcmp.c. */
3905 return ! optimize || c4x_valid_operands (code, operands, mode, 0);
3910 legitimize_operands (enum rtx_code code, rtx *operands, enum machine_mode mode)
3912 /* Compare only has 2 operands. */
3913 if (code == COMPARE)
3915 /* During RTL generation, force constants into pseudos so that
3916 they can get hoisted out of loops. This will tie up an extra
3917 register but can save an extra cycle. Only do this if loop
3918 optimization enabled. (We cannot pull this trick for add and
3919 sub instructions since the flow pass won't find
3920 autoincrements etc.) This allows us to generate compare
3921 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
3922 of LDI *AR0++, R0; CMPI 42, R0.
3924 Note that expand_binops will try to load an expensive constant
3925 into a register if it is used within a loop. Unfortunately,
3926 the cost mechanism doesn't allow us to look at the other
3927 operand to decide whether the constant is expensive. */
3929 if (! reload_in_progress
3932 && GET_CODE (operands[1]) == CONST_INT
3933 && preserve_subexpressions_p ()
3934 && rtx_cost (operands[1], code) > 1)
3935 operands[1] = force_reg (mode, operands[1]);
3937 if (! reload_in_progress
3938 && ! c4x_valid_operands (code, operands, mode, 0))
3939 operands[0] = force_reg (mode, operands[0]);
3943 /* We cannot do this for ADDI/SUBI insns since we will
3944 defeat the flow pass from finding autoincrement addressing
3946 if (! reload_in_progress
3947 && ! ((code == PLUS || code == MINUS) && mode == Pmode)
3950 && GET_CODE (operands[2]) == CONST_INT
3951 && preserve_subexpressions_p ()
3952 && rtx_cost (operands[2], code) > 1)
3953 operands[2] = force_reg (mode, operands[2]);
3955 /* We can get better code on a C30 if we force constant shift counts
3956 into a register. This way they can get hoisted out of loops,
3957 tying up a register but saving an instruction. The downside is
3958 that they may get allocated to an address or index register, and
3959 thus we will get a pipeline conflict if there is a nearby
3960 indirect address using an address register.
3962 Note that expand_binops will not try to load an expensive constant
3963 into a register if it is used within a loop for a shift insn. */
3965 if (! reload_in_progress
3966 && ! c4x_valid_operands (code, operands, mode, TARGET_FORCE))
3968 /* If the operand combination is invalid, we force operand1 into a
3969 register, preventing reload from having doing to do this at a
3971 operands[1] = force_reg (mode, operands[1]);
3974 emit_move_insn (operands[0], operands[1]);
3975 operands[1] = copy_rtx (operands[0]);
3979 /* Just in case... */
3980 if (! c4x_valid_operands (code, operands, mode, 0))
3981 operands[2] = force_reg (mode, operands[2]);
3985 /* Right shifts require a negative shift count, but GCC expects
3986 a positive count, so we emit a NEG. */
3987 if ((code == ASHIFTRT || code == LSHIFTRT)
3988 && (GET_CODE (operands[2]) != CONST_INT))
3989 operands[2] = gen_rtx_NEG (mode, negate_rtx (mode, operands[2]));
3992 /* When the shift count is greater than 32 then the result
3993 can be implementation dependent. We truncate the result to
3994 fit in 5 bits so that we do not emit invalid code when
3995 optimising---such as trying to generate lhu2 with 20021124-1.c. */
3996 if (((code == ASHIFTRT || code == LSHIFTRT || code == ASHIFT)
3997 && (GET_CODE (operands[2]) == CONST_INT))
3998 && INTVAL (operands[2]) > (GET_MODE_BITSIZE (mode) - 1))
4000 = GEN_INT (INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode) - 1));
4006 /* The following predicates are used for instruction scheduling. */
4009 group1_reg_operand (rtx op, enum machine_mode mode)
4011 if (mode != VOIDmode && mode != GET_MODE (op))
4013 if (GET_CODE (op) == SUBREG)
4014 op = SUBREG_REG (op);
4015 return REG_P (op) && (! reload_completed || IS_GROUP1_REG (op));
4020 group1_mem_operand (rtx op, enum machine_mode mode)
4022 if (mode != VOIDmode && mode != GET_MODE (op))
4025 if (GET_CODE (op) == MEM)
4028 if (GET_CODE (op) == PLUS)
4030 rtx op0 = XEXP (op, 0);
4031 rtx op1 = XEXP (op, 1);
4033 if ((REG_P (op0) && (! reload_completed || IS_GROUP1_REG (op0)))
4034 || (REG_P (op1) && (! reload_completed || IS_GROUP1_REG (op1))))
4037 else if ((REG_P (op)) && (! reload_completed || IS_GROUP1_REG (op)))
4045 /* Return true if any one of the address registers. */
4048 arx_reg_operand (rtx op, enum machine_mode mode)
4050 if (mode != VOIDmode && mode != GET_MODE (op))
4052 if (GET_CODE (op) == SUBREG)
4053 op = SUBREG_REG (op);
4054 return REG_P (op) && (! reload_completed || IS_ADDR_REG (op));
4059 c4x_arn_reg_operand (rtx op, enum machine_mode mode, unsigned int regno)
4061 if (mode != VOIDmode && mode != GET_MODE (op))
4063 if (GET_CODE (op) == SUBREG)
4064 op = SUBREG_REG (op);
4065 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4070 c4x_arn_mem_operand (rtx op, enum machine_mode mode, unsigned int regno)
4072 if (mode != VOIDmode && mode != GET_MODE (op))
4075 if (GET_CODE (op) == MEM)
4078 switch (GET_CODE (op))
4087 return REG_P (op) && (! reload_completed || (REGNO (op) == regno));
4091 if (REG_P (XEXP (op, 0)) && (! reload_completed
4092 || (REGNO (XEXP (op, 0)) == regno)))
4094 if (REG_P (XEXP (XEXP (op, 1), 1))
4095 && (! reload_completed
4096 || (REGNO (XEXP (XEXP (op, 1), 1)) == regno)))
4102 rtx op0 = XEXP (op, 0);
4103 rtx op1 = XEXP (op, 1);
4105 if ((REG_P (op0) && (! reload_completed
4106 || (REGNO (op0) == regno)))
4107 || (REG_P (op1) && (! reload_completed
4108 || (REGNO (op1) == regno))))
4122 ar0_reg_operand (rtx op, enum machine_mode mode)
4124 return c4x_arn_reg_operand (op, mode, AR0_REGNO);
4129 ar0_mem_operand (rtx op, enum machine_mode mode)
4131 return c4x_arn_mem_operand (op, mode, AR0_REGNO);
4136 ar1_reg_operand (rtx op, enum machine_mode mode)
4138 return c4x_arn_reg_operand (op, mode, AR1_REGNO);
4143 ar1_mem_operand (rtx op, enum machine_mode mode)
4145 return c4x_arn_mem_operand (op, mode, AR1_REGNO);
4150 ar2_reg_operand (rtx op, enum machine_mode mode)
4152 return c4x_arn_reg_operand (op, mode, AR2_REGNO);
4157 ar2_mem_operand (rtx op, enum machine_mode mode)
4159 return c4x_arn_mem_operand (op, mode, AR2_REGNO);
4164 ar3_reg_operand (rtx op, enum machine_mode mode)
4166 return c4x_arn_reg_operand (op, mode, AR3_REGNO);
4171 ar3_mem_operand (rtx op, enum machine_mode mode)
4173 return c4x_arn_mem_operand (op, mode, AR3_REGNO);
4178 ar4_reg_operand (rtx op, enum machine_mode mode)
4180 return c4x_arn_reg_operand (op, mode, AR4_REGNO);
4185 ar4_mem_operand (rtx op, enum machine_mode mode)
4187 return c4x_arn_mem_operand (op, mode, AR4_REGNO);
4192 ar5_reg_operand (rtx op, enum machine_mode mode)
4194 return c4x_arn_reg_operand (op, mode, AR5_REGNO);
4199 ar5_mem_operand (rtx op, enum machine_mode mode)
4201 return c4x_arn_mem_operand (op, mode, AR5_REGNO);
4206 ar6_reg_operand (rtx op, enum machine_mode mode)
4208 return c4x_arn_reg_operand (op, mode, AR6_REGNO);
4213 ar6_mem_operand (rtx op, enum machine_mode mode)
4215 return c4x_arn_mem_operand (op, mode, AR6_REGNO);
4220 ar7_reg_operand (rtx op, enum machine_mode mode)
4222 return c4x_arn_reg_operand (op, mode, AR7_REGNO);
4227 ar7_mem_operand (rtx op, enum machine_mode mode)
4229 return c4x_arn_mem_operand (op, mode, AR7_REGNO);
4234 ir0_reg_operand (rtx op, enum machine_mode mode)
4236 return c4x_arn_reg_operand (op, mode, IR0_REGNO);
4241 ir0_mem_operand (rtx op, enum machine_mode mode)
4243 return c4x_arn_mem_operand (op, mode, IR0_REGNO);
4248 ir1_reg_operand (rtx op, enum machine_mode mode)
4250 return c4x_arn_reg_operand (op, mode, IR1_REGNO);
4255 ir1_mem_operand (rtx op, enum machine_mode mode)
4257 return c4x_arn_mem_operand (op, mode, IR1_REGNO);
4261 /* This is similar to operand_subword but allows autoincrement
4265 c4x_operand_subword (rtx op, int i, int validate_address,
4266 enum machine_mode mode)
4268 if (mode != HImode && mode != HFmode)
4269 fatal_insn ("c4x_operand_subword: invalid mode", op);
4271 if (mode == HFmode && REG_P (op))
4272 fatal_insn ("c4x_operand_subword: invalid operand", op);
4274 if (GET_CODE (op) == MEM)
4276 enum rtx_code code = GET_CODE (XEXP (op, 0));
4277 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4278 enum machine_mode submode;
4283 else if (mode == HFmode)
4290 return gen_rtx_MEM (submode, XEXP (op, 0));
4296 /* We could handle these with some difficulty.
4297 e.g., *p-- => *(p-=2); *(p+1). */
4298 fatal_insn ("c4x_operand_subword: invalid autoincrement", op);
4304 fatal_insn ("c4x_operand_subword: invalid address", op);
4306 /* Even though offsettable_address_p considers (MEM
4307 (LO_SUM)) to be offsettable, it is not safe if the
4308 address is at the end of the data page since we also have
4309 to fix up the associated high PART. In this case where
4310 we are trying to split a HImode or HFmode memory
4311 reference, we would have to emit another insn to reload a
4312 new HIGH value. It's easier to disable LO_SUM memory references
4313 in HImode or HFmode and we probably get better code. */
4315 fatal_insn ("c4x_operand_subword: address not offsettable", op);
4322 return operand_subword (op, i, validate_address, mode);
4327 struct name_list *next;
4331 static struct name_list *global_head;
4332 static struct name_list *extern_head;
4335 /* Add NAME to list of global symbols and remove from external list if
4336 present on external list. */
4339 c4x_global_label (const char *name)
4341 struct name_list *p, *last;
4343 /* Do not insert duplicate names, so linearly search through list of
4348 if (strcmp (p->name, name) == 0)
4352 p = (struct name_list *) xmalloc (sizeof *p);
4353 p->next = global_head;
4357 /* Remove this name from ref list if present. */
4362 if (strcmp (p->name, name) == 0)
4365 last->next = p->next;
4367 extern_head = p->next;
4376 /* Add NAME to list of external symbols. */
4379 c4x_external_ref (const char *name)
4381 struct name_list *p;
4383 /* Do not insert duplicate names. */
4387 if (strcmp (p->name, name) == 0)
4392 /* Do not insert ref if global found. */
4396 if (strcmp (p->name, name) == 0)
4400 p = (struct name_list *) xmalloc (sizeof *p);
4401 p->next = extern_head;
4406 /* We need to have a data section we can identify so that we can set
4407 the DP register back to a data pointer in the small memory model.
4408 This is only required for ISRs if we are paranoid that someone
4409 may have quietly changed this register on the sly. */
4411 c4x_file_start (void)
4414 if (TARGET_C30) dspversion = 30;
4415 if (TARGET_C31) dspversion = 31;
4416 if (TARGET_C32) dspversion = 32;
4417 if (TARGET_C33) dspversion = 33;
4418 if (TARGET_C40) dspversion = 40;
4419 if (TARGET_C44) dspversion = 44;
4421 default_file_start ();
4422 fprintf (asm_out_file, "\t.version\t%d\n", dspversion);
4423 fputs ("\n\t.data\ndata_sec:\n", asm_out_file);
4430 struct name_list *p;
4432 /* Output all external names that are not global. */
4436 fprintf (asm_out_file, "\t.ref\t");
4437 assemble_name (asm_out_file, p->name);
4438 fprintf (asm_out_file, "\n");
4441 fprintf (asm_out_file, "\t.end\n");
4446 c4x_check_attribute (const char *attrib, tree list, tree decl, tree *attributes)
4448 while (list != NULL_TREE
4449 && IDENTIFIER_POINTER (TREE_PURPOSE (list))
4450 != IDENTIFIER_POINTER (DECL_NAME (decl)))
4451 list = TREE_CHAIN (list);
4453 *attributes = tree_cons (get_identifier (attrib), TREE_VALUE (list),
4459 c4x_insert_attributes (tree decl, tree *attributes)
4461 switch (TREE_CODE (decl))
4464 c4x_check_attribute ("section", code_tree, decl, attributes);
4465 c4x_check_attribute ("const", pure_tree, decl, attributes);
4466 c4x_check_attribute ("noreturn", noreturn_tree, decl, attributes);
4467 c4x_check_attribute ("interrupt", interrupt_tree, decl, attributes);
4468 c4x_check_attribute ("naked", naked_tree, decl, attributes);
4472 c4x_check_attribute ("section", data_tree, decl, attributes);
4480 /* Table of valid machine attributes. */
4481 const struct attribute_spec c4x_attribute_table[] =
4483 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4484 { "interrupt", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4485 { "naked", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4486 { "leaf_pretend", 0, 0, false, true, true, c4x_handle_fntype_attribute },
4487 { NULL, 0, 0, false, false, false, NULL }
4490 /* Handle an attribute requiring a FUNCTION_TYPE;
4491 arguments as in struct attribute_spec.handler. */
4493 c4x_handle_fntype_attribute (tree *node, tree name,
4494 tree args ATTRIBUTE_UNUSED,
4495 int flags ATTRIBUTE_UNUSED,
4498 if (TREE_CODE (*node) != FUNCTION_TYPE)
4500 warning ("`%s' attribute only applies to functions",
4501 IDENTIFIER_POINTER (name));
4502 *no_add_attrs = true;
4509 /* !!! FIXME to emit RPTS correctly. */
4512 c4x_rptb_rpts_p (rtx insn, rtx op)
4514 /* The next insn should be our label marking where the
4515 repeat block starts. */
4516 insn = NEXT_INSN (insn);
4517 if (GET_CODE (insn) != CODE_LABEL)
4519 /* Some insns may have been shifted between the RPTB insn
4520 and the top label... They were probably destined to
4521 be moved out of the loop. For now, let's leave them
4522 where they are and print a warning. We should
4523 probably move these insns before the repeat block insn. */
4525 fatal_insn("c4x_rptb_rpts_p: Repeat block top label moved\n",
4530 /* Skip any notes. */
4531 insn = next_nonnote_insn (insn);
4533 /* This should be our first insn in the loop. */
4534 if (! INSN_P (insn))
4537 /* Skip any notes. */
4538 insn = next_nonnote_insn (insn);
4540 if (! INSN_P (insn))
4543 if (recog_memoized (insn) != CODE_FOR_rptb_end)
4549 return (GET_CODE (op) == CONST_INT) && TARGET_RPTS_CYCLES (INTVAL (op));
4553 /* Check if register r11 is used as the destination of an insn. */
4556 c4x_r11_set_p(rtx x)
4565 if (INSN_P (x) && GET_CODE (PATTERN (x)) == SEQUENCE)
4566 x = XVECEXP (PATTERN (x), 0, XVECLEN (PATTERN (x), 0) - 1);
4568 if (INSN_P (x) && (set = single_set (x)))
4571 if (GET_CODE (x) == REG && REGNO (x) == R11_REGNO)
4574 fmt = GET_RTX_FORMAT (GET_CODE (x));
4575 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4579 if (c4x_r11_set_p (XEXP (x, i)))
4582 else if (fmt[i] == 'E')
4583 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4584 if (c4x_r11_set_p (XVECEXP (x, i, j)))
4591 /* The c4x sometimes has a problem when the insn before the laj insn
4592 sets the r11 register. Check for this situation. */
4595 c4x_check_laj_p (rtx insn)
4597 insn = prev_nonnote_insn (insn);
4599 /* If this is the start of the function no nop is needed. */
4603 /* If the previous insn is a code label we have to insert a nop. This
4604 could be a jump or table jump. We can find the normal jumps by
4605 scanning the function but this will not find table jumps. */
4606 if (GET_CODE (insn) == CODE_LABEL)
4609 /* If the previous insn sets register r11 we have to insert a nop. */
4610 if (c4x_r11_set_p (insn))
4613 /* No nop needed. */
4618 /* Adjust the cost of a scheduling dependency. Return the new cost of
4619 a dependency LINK or INSN on DEP_INSN. COST is the current cost.
4620 A set of an address register followed by a use occurs a 2 cycle
4621 stall (reduced to a single cycle on the c40 using LDA), while
4622 a read of an address register followed by a use occurs a single cycle. */
4624 #define SET_USE_COST 3
4625 #define SETLDA_USE_COST 2
4626 #define READ_USE_COST 2
4629 c4x_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4631 /* Don't worry about this until we know what registers have been
4633 if (flag_schedule_insns == 0 && ! reload_completed)
4636 /* How do we handle dependencies where a read followed by another
4637 read causes a pipeline stall? For example, a read of ar0 followed
4638 by the use of ar0 for a memory reference. It looks like we
4639 need to extend the scheduler to handle this case. */
4641 /* Reload sometimes generates a CLOBBER of a stack slot, e.g.,
4642 (clobber (mem:QI (plus:QI (reg:QI 11 ar3) (const_int 261)))),
4643 so only deal with insns we know about. */
4644 if (recog_memoized (dep_insn) < 0)
4647 if (REG_NOTE_KIND (link) == 0)
4651 /* Data dependency; DEP_INSN writes a register that INSN reads some
4655 if (get_attr_setgroup1 (dep_insn) && get_attr_usegroup1 (insn))
4656 max = SET_USE_COST > max ? SET_USE_COST : max;
4657 if (get_attr_readarx (dep_insn) && get_attr_usegroup1 (insn))
4658 max = READ_USE_COST > max ? READ_USE_COST : max;
4662 /* This could be significantly optimized. We should look
4663 to see if dep_insn sets ar0-ar7 or ir0-ir1 and if
4664 insn uses ar0-ar7. We then test if the same register
4665 is used. The tricky bit is that some operands will
4666 use several registers... */
4667 if (get_attr_setar0 (dep_insn) && get_attr_usear0 (insn))
4668 max = SET_USE_COST > max ? SET_USE_COST : max;
4669 if (get_attr_setlda_ar0 (dep_insn) && get_attr_usear0 (insn))
4670 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4671 if (get_attr_readar0 (dep_insn) && get_attr_usear0 (insn))
4672 max = READ_USE_COST > max ? READ_USE_COST : max;
4674 if (get_attr_setar1 (dep_insn) && get_attr_usear1 (insn))
4675 max = SET_USE_COST > max ? SET_USE_COST : max;
4676 if (get_attr_setlda_ar1 (dep_insn) && get_attr_usear1 (insn))
4677 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4678 if (get_attr_readar1 (dep_insn) && get_attr_usear1 (insn))
4679 max = READ_USE_COST > max ? READ_USE_COST : max;
4681 if (get_attr_setar2 (dep_insn) && get_attr_usear2 (insn))
4682 max = SET_USE_COST > max ? SET_USE_COST : max;
4683 if (get_attr_setlda_ar2 (dep_insn) && get_attr_usear2 (insn))
4684 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4685 if (get_attr_readar2 (dep_insn) && get_attr_usear2 (insn))
4686 max = READ_USE_COST > max ? READ_USE_COST : max;
4688 if (get_attr_setar3 (dep_insn) && get_attr_usear3 (insn))
4689 max = SET_USE_COST > max ? SET_USE_COST : max;
4690 if (get_attr_setlda_ar3 (dep_insn) && get_attr_usear3 (insn))
4691 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4692 if (get_attr_readar3 (dep_insn) && get_attr_usear3 (insn))
4693 max = READ_USE_COST > max ? READ_USE_COST : max;
4695 if (get_attr_setar4 (dep_insn) && get_attr_usear4 (insn))
4696 max = SET_USE_COST > max ? SET_USE_COST : max;
4697 if (get_attr_setlda_ar4 (dep_insn) && get_attr_usear4 (insn))
4698 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4699 if (get_attr_readar4 (dep_insn) && get_attr_usear4 (insn))
4700 max = READ_USE_COST > max ? READ_USE_COST : max;
4702 if (get_attr_setar5 (dep_insn) && get_attr_usear5 (insn))
4703 max = SET_USE_COST > max ? SET_USE_COST : max;
4704 if (get_attr_setlda_ar5 (dep_insn) && get_attr_usear5 (insn))
4705 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4706 if (get_attr_readar5 (dep_insn) && get_attr_usear5 (insn))
4707 max = READ_USE_COST > max ? READ_USE_COST : max;
4709 if (get_attr_setar6 (dep_insn) && get_attr_usear6 (insn))
4710 max = SET_USE_COST > max ? SET_USE_COST : max;
4711 if (get_attr_setlda_ar6 (dep_insn) && get_attr_usear6 (insn))
4712 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4713 if (get_attr_readar6 (dep_insn) && get_attr_usear6 (insn))
4714 max = READ_USE_COST > max ? READ_USE_COST : max;
4716 if (get_attr_setar7 (dep_insn) && get_attr_usear7 (insn))
4717 max = SET_USE_COST > max ? SET_USE_COST : max;
4718 if (get_attr_setlda_ar7 (dep_insn) && get_attr_usear7 (insn))
4719 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4720 if (get_attr_readar7 (dep_insn) && get_attr_usear7 (insn))
4721 max = READ_USE_COST > max ? READ_USE_COST : max;
4723 if (get_attr_setir0 (dep_insn) && get_attr_useir0 (insn))
4724 max = SET_USE_COST > max ? SET_USE_COST : max;
4725 if (get_attr_setlda_ir0 (dep_insn) && get_attr_useir0 (insn))
4726 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4728 if (get_attr_setir1 (dep_insn) && get_attr_useir1 (insn))
4729 max = SET_USE_COST > max ? SET_USE_COST : max;
4730 if (get_attr_setlda_ir1 (dep_insn) && get_attr_useir1 (insn))
4731 max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
4737 /* For other data dependencies, the default cost specified in the
4741 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4743 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4746 /* For c4x anti dependencies, the cost is 0. */
4749 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4751 /* Output dependency; DEP_INSN writes a register that INSN writes some
4754 /* For c4x output dependencies, the cost is 0. */
4762 c4x_init_builtins (void)
4764 tree endlink = void_list_node;
4766 builtin_function ("fast_ftoi",
4769 tree_cons (NULL_TREE, double_type_node, endlink)),
4770 C4X_BUILTIN_FIX, BUILT_IN_MD, NULL, NULL_TREE);
4771 builtin_function ("ansi_ftoi",
4774 tree_cons (NULL_TREE, double_type_node, endlink)),
4775 C4X_BUILTIN_FIX_ANSI, BUILT_IN_MD, NULL, NULL_TREE);
4777 builtin_function ("fast_imult",
4780 tree_cons (NULL_TREE, integer_type_node,
4781 tree_cons (NULL_TREE,
4782 integer_type_node, endlink))),
4783 C4X_BUILTIN_MPYI, BUILT_IN_MD, NULL, NULL_TREE);
4786 builtin_function ("toieee",
4789 tree_cons (NULL_TREE, double_type_node, endlink)),
4790 C4X_BUILTIN_TOIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4791 builtin_function ("frieee",
4794 tree_cons (NULL_TREE, double_type_node, endlink)),
4795 C4X_BUILTIN_FRIEEE, BUILT_IN_MD, NULL, NULL_TREE);
4796 builtin_function ("fast_invf",
4799 tree_cons (NULL_TREE, double_type_node, endlink)),
4800 C4X_BUILTIN_RCPF, BUILT_IN_MD, NULL, NULL_TREE);
4806 c4x_expand_builtin (tree exp, rtx target,
4807 rtx subtarget ATTRIBUTE_UNUSED,
4808 enum machine_mode mode ATTRIBUTE_UNUSED,
4809 int ignore ATTRIBUTE_UNUSED)
4811 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4812 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4813 tree arglist = TREE_OPERAND (exp, 1);
4819 case C4X_BUILTIN_FIX:
4820 arg0 = TREE_VALUE (arglist);
4821 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4822 r0 = protect_from_queue (r0, 0);
4823 if (! target || ! register_operand (target, QImode))
4824 target = gen_reg_rtx (QImode);
4825 emit_insn (gen_fixqfqi_clobber (target, r0));
4828 case C4X_BUILTIN_FIX_ANSI:
4829 arg0 = TREE_VALUE (arglist);
4830 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4831 r0 = protect_from_queue (r0, 0);
4832 if (! target || ! register_operand (target, QImode))
4833 target = gen_reg_rtx (QImode);
4834 emit_insn (gen_fix_truncqfqi2 (target, r0));
4837 case C4X_BUILTIN_MPYI:
4840 arg0 = TREE_VALUE (arglist);
4841 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4842 r0 = expand_expr (arg0, NULL_RTX, QImode, 0);
4843 r1 = expand_expr (arg1, NULL_RTX, QImode, 0);
4844 r0 = protect_from_queue (r0, 0);
4845 r1 = protect_from_queue (r1, 0);
4846 if (! target || ! register_operand (target, QImode))
4847 target = gen_reg_rtx (QImode);
4848 emit_insn (gen_mulqi3_24_clobber (target, r0, r1));
4851 case C4X_BUILTIN_TOIEEE:
4854 arg0 = TREE_VALUE (arglist);
4855 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4856 r0 = protect_from_queue (r0, 0);
4857 if (! target || ! register_operand (target, QFmode))
4858 target = gen_reg_rtx (QFmode);
4859 emit_insn (gen_toieee (target, r0));
4862 case C4X_BUILTIN_FRIEEE:
4865 arg0 = TREE_VALUE (arglist);
4866 if (TREE_CODE (arg0) == VAR_DECL || TREE_CODE (arg0) == PARM_DECL)
4867 put_var_into_stack (arg0, /*rescan=*/true);
4868 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4869 r0 = protect_from_queue (r0, 0);
4870 if (register_operand (r0, QFmode))
4872 r1 = assign_stack_local (QFmode, GET_MODE_SIZE (QFmode), 0);
4873 emit_move_insn (r1, r0);
4876 if (! target || ! register_operand (target, QFmode))
4877 target = gen_reg_rtx (QFmode);
4878 emit_insn (gen_frieee (target, r0));
4881 case C4X_BUILTIN_RCPF:
4884 arg0 = TREE_VALUE (arglist);
4885 r0 = expand_expr (arg0, NULL_RTX, QFmode, 0);
4886 r0 = protect_from_queue (r0, 0);
4887 if (! target || ! register_operand (target, QFmode))
4888 target = gen_reg_rtx (QFmode);
4889 emit_insn (gen_rcpfqf_clobber (target, r0));
4896 c4x_init_libfuncs (void)
4898 set_optab_libfunc (smul_optab, QImode, "__mulqi3");
4899 set_optab_libfunc (sdiv_optab, QImode, "__divqi3");
4900 set_optab_libfunc (udiv_optab, QImode, "__udivqi3");
4901 set_optab_libfunc (smod_optab, QImode, "__modqi3");
4902 set_optab_libfunc (umod_optab, QImode, "__umodqi3");
4903 set_optab_libfunc (sdiv_optab, QFmode, "__divqf3");
4904 set_optab_libfunc (smul_optab, HFmode, "__mulhf3");
4905 set_optab_libfunc (sdiv_optab, HFmode, "__divhf3");
4906 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4907 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4908 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4909 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4910 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4911 set_optab_libfunc (ffs_optab, QImode, "__ffs");
4912 smulhi3_libfunc = init_one_libfunc ("__smulhi3_high");
4913 umulhi3_libfunc = init_one_libfunc ("__umulhi3_high");
4914 fix_truncqfhi2_libfunc = init_one_libfunc ("__fix_truncqfhi2");
4915 fixuns_truncqfhi2_libfunc = init_one_libfunc ("__ufix_truncqfhi2");
4916 fix_trunchfhi2_libfunc = init_one_libfunc ("__fix_trunchfhi2");
4917 fixuns_trunchfhi2_libfunc = init_one_libfunc ("__ufix_trunchfhi2");
4918 floathiqf2_libfunc = init_one_libfunc ("__floathiqf2");
4919 floatunshiqf2_libfunc = init_one_libfunc ("__ufloathiqf2");
4920 floathihf2_libfunc = init_one_libfunc ("__floathihf2");
4921 floatunshihf2_libfunc = init_one_libfunc ("__ufloathihf2");
4925 c4x_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4927 fprintf (asm_out_file, "\t.sect\t\"%s\"\n", name);
4931 c4x_globalize_label (FILE *stream, const char *name)
4933 default_globalize_label (stream, name);
4934 c4x_global_label (name);
4937 #define SHIFT_CODE_P(C) \
4938 ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
4939 #define LOGICAL_CODE_P(C) \
4940 ((C) == NOT || (C) == AND || (C) == IOR || (C) == XOR)
4942 /* Compute a (partial) cost for rtx X. Return true if the complete
4943 cost has been computed, and false if subexpressions should be
4944 scanned. In either case, *TOTAL contains the cost result. */
4947 c4x_rtx_costs (rtx x, int code, int outer_code, int *total)
4953 /* Some small integers are effectively free for the C40. We should
4954 also consider if we are using the small memory model. With
4955 the big memory model we require an extra insn for a constant
4956 loaded from memory. */
4960 if (c4x_J_constant (x))
4962 else if (! TARGET_C3X
4963 && outer_code == AND
4964 && (val == 255 || val == 65535))
4966 else if (! TARGET_C3X
4967 && (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
4968 && (val == 16 || val == 24))
4970 else if (TARGET_C3X && SHIFT_CODE_P (outer_code))
4972 else if (LOGICAL_CODE_P (outer_code)
4973 ? c4x_L_constant (x) : c4x_I_constant (x))
4986 if (c4x_H_constant (x))
4988 else if (GET_MODE (x) == QFmode)
4994 /* ??? Note that we return true, rather than false so that rtx_cost
4995 doesn't include the constant costs. Otherwise expand_mult will
4996 think that it is cheaper to synthesize a multiply rather than to
4997 use a multiply instruction. I think this is because the algorithm
4998 synth_mult doesn't take into account the loading of the operands,
4999 whereas the calculation of mult_cost does. */
5008 *total = COSTS_N_INSNS (1);
5012 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
5013 || TARGET_MPYI ? 1 : 14);
5020 *total = COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
5029 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
5032 c4x_external_libcall (rtx fun)
5034 /* This is only needed to keep asm30 happy for ___divqf3 etc. */
5035 c4x_external_ref (XSTR (fun, 0));
5038 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5041 c4x_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
5042 int incoming ATTRIBUTE_UNUSED)
5044 return gen_rtx_REG (Pmode, AR0_REGNO);