1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ; operand punctuation marks:
24 ; X -- integer value printed as log2
25 ; Y -- integer value printed as log2(~value) - for bitclear
26 ; h -- print half word register, low part
27 ; d -- print half word register, high part
28 ; D -- print operand as dregs pairs
29 ; w -- print operand as accumulator register word (a0w, a1w)
30 ; H -- high part of double mode operand
31 ; T -- byte register representation Oct. 02 2001
33 ; constant operand classes
35 ; J 2**N 5bit imm scaled
36 ; Ks7 -64 .. 63 signed 7bit imm
37 ; Ku5 0..31 unsigned 5bit imm
38 ; Ks4 -8 .. 7 signed 4bit imm
39 ; Ks3 -4 .. 3 signed 3bit imm
40 ; Ku3 0 .. 7 unsigned 3bit imm
41 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
50 ; c (i0..i3,m0..m3) CIRCREGS
57 ;; Define constants for hard registers.
124 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
127 [(UNSPEC_CBRANCH_TAKEN 0)
128 (UNSPEC_CBRANCH_NOPS 1)
131 (UNSPEC_LIBRARY_OFFSET 4)
132 (UNSPEC_PUSH_MULTIPLE 5)
133 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
134 (UNSPEC_MUL_WITH_FLAG 6)
135 (UNSPEC_MAC_WITH_FLAG 7)
136 (UNSPEC_MOVE_FDPIC 8)
137 (UNSPEC_FUNCDESC_GOT17M4 9)
138 (UNSPEC_LSETUP_END 10)
139 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
143 [(UNSPEC_VOLATILE_EH_RETURN 0)
144 (UNSPEC_VOLATILE_CSYNC 1)
145 (UNSPEC_VOLATILE_SSYNC 2)
146 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)])
163 "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
164 (const_string "misc"))
166 (define_attr "addrtype" "32bit,preg,ireg"
167 (cond [(and (eq_attr "type" "mcld")
168 (and (match_operand 0 "d_register_operand" "")
169 (match_operand 1 "mem_p_address_operand" "")))
170 (const_string "preg")
171 (and (eq_attr "type" "mcld")
172 (and (match_operand 0 "d_register_operand" "")
173 (match_operand 1 "mem_i_address_operand" "")))
174 (const_string "ireg")
175 (and (eq_attr "type" "mcst")
176 (and (match_operand 1 "d_register_operand" "")
177 (match_operand 0 "mem_p_address_operand" "")))
178 (const_string "preg")
179 (and (eq_attr "type" "mcst")
180 (and (match_operand 1 "d_register_operand" "")
181 (match_operand 0 "mem_i_address_operand" "")))
182 (const_string "ireg")]
183 (const_string "32bit")))
185 ;; Scheduling definitions
187 (define_automaton "bfin")
189 (define_cpu_unit "slot0" "bfin")
190 (define_cpu_unit "slot1" "bfin")
191 (define_cpu_unit "slot2" "bfin")
193 ;; Three units used to enforce parallel issue restrictions:
194 ;; only one of the 16-bit slots can use a P register in an address,
195 ;; and only one them can be a store.
196 (define_cpu_unit "store" "bfin")
197 (define_cpu_unit "pregs" "bfin")
199 (define_reservation "core" "slot0+slot1+slot2")
201 (define_insn_reservation "alu" 1
202 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
205 (define_insn_reservation "imul" 3
206 (eq_attr "type" "mult")
209 (define_insn_reservation "dsp32" 1
210 (eq_attr "type" "dsp32")
213 (define_insn_reservation "load32" 1
214 (and (not (eq_attr "seq_insns" "multi"))
215 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
218 (define_insn_reservation "loadp" 1
219 (and (not (eq_attr "seq_insns" "multi"))
220 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
221 "(slot1|slot2)+pregs")
223 (define_insn_reservation "loadi" 1
224 (and (not (eq_attr "seq_insns" "multi"))
225 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
228 (define_insn_reservation "store32" 1
229 (and (not (eq_attr "seq_insns" "multi"))
230 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
233 (define_insn_reservation "storep" 1
234 (and (not (eq_attr "seq_insns" "multi"))
235 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg")))
236 "(slot1|slot2)+pregs+store")
238 (define_insn_reservation "storei" 1
239 (and (not (eq_attr "seq_insns" "multi"))
240 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
241 "(slot1|slot2)+store")
243 (define_insn_reservation "multi" 2
244 (eq_attr "seq_insns" "multi")
247 (absence_set "slot0" "slot1,slot2")
248 (absence_set "slot1" "slot2")
250 ;; Make sure genautomata knows about the maximum latency that can be produced
251 ;; by the adjust_cost function.
252 (define_insn_reservation "dummy" 5
253 (eq_attr "type" "dummy")
256 ;; Operand and operator predicates
258 (include "predicates.md")
261 ;;; FRIO branches have been optimized for code density
262 ;;; this comes at a slight cost of complexity when
263 ;;; a compiler needs to generate branches in the general
264 ;;; case. In order to generate the correct branching
265 ;;; mechanisms the compiler needs keep track of instruction
266 ;;; lengths. The follow table describes how to count instructions
267 ;;; for the FRIO architecture.
269 ;;; unconditional br are 12-bit imm pcrelative branches *2
270 ;;; conditional br are 10-bit imm pcrelative branches *2
272 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
274 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
275 ;;; NOTE : For brcc we generate instructions such as
276 ;;; if cc jmp; jump.[sl] offset
277 ;;; offset of jump.[sl] is from the jump instruction but
278 ;;; gcc calculates length from the if cc jmp instruction
279 ;;; furthermore gcc takes the end address of the branch instruction
280 ;;; as (pc) for a forward branch
281 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
283 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
284 ;;; for backward branches it's the address of the current instruction,
285 ;;; for forward branches it's the previously known address of the following
286 ;;; instruction - we have to take this into account by reducing the range
287 ;;; for a forward branch.
289 ;; Lengths for type "mvi" insns are always defined by the instructions
291 (define_attr "length" ""
292 (cond [(eq_attr "type" "mcld")
293 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
294 (const_int 4) (const_int 2))
296 (eq_attr "type" "mcst")
297 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
298 (const_int 4) (const_int 2))
300 (eq_attr "type" "move") (const_int 2)
302 (eq_attr "type" "dsp32") (const_int 4)
303 (eq_attr "type" "call") (const_int 4)
305 (eq_attr "type" "br")
307 (le (minus (match_dup 0) (pc)) (const_int 4092))
308 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
312 (eq_attr "type" "brcc")
314 (le (minus (match_dup 3) (pc)) (const_int 1020))
315 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
318 (le (minus (match_dup 3) (pc)) (const_int 4092))
319 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
326 ;; Classify the insns into those that are one instruction and those that
327 ;; are more than one in sequence.
328 (define_attr "seq_insns" "single,multi"
329 (const_string "single"))
333 (define_expand "movsicc"
334 [(set (match_operand:SI 0 "register_operand" "")
335 (if_then_else:SI (match_operand 1 "comparison_operator" "")
336 (match_operand:SI 2 "register_operand" "")
337 (match_operand:SI 3 "register_operand" "")))]
340 operands[1] = bfin_gen_compare (operands[1], SImode);
343 (define_insn "*movsicc_insn1"
344 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
346 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
348 (match_operand:SI 1 "register_operand" "da,0,da")
349 (match_operand:SI 2 "register_operand" "0,da,da")))]
352 if !cc %0 =%1; /* movsicc-1a */
353 if cc %0 =%2; /* movsicc-1b */
354 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
355 [(set_attr "length" "2,2,4")
356 (set_attr "type" "movcc")
357 (set_attr "seq_insns" "*,*,multi")])
359 (define_insn "*movsicc_insn2"
360 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
362 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
364 (match_operand:SI 1 "register_operand" "0,da,da")
365 (match_operand:SI 2 "register_operand" "da,0,da")))]
368 if !cc %0 =%2; /* movsicc-2b */
369 if cc %0 =%1; /* movsicc-2a */
370 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
371 [(set_attr "length" "2,2,4")
372 (set_attr "type" "movcc")
373 (set_attr "seq_insns" "*,*,multi")])
375 ;; Insns to load HIGH and LO_SUM
377 (define_insn "movsi_high"
378 [(set (match_operand:SI 0 "register_operand" "=x")
379 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
382 [(set_attr "type" "mvi")
383 (set_attr "length" "4")])
385 (define_insn "movstricthi_high"
386 [(set (match_operand:SI 0 "register_operand" "+x")
387 (ior:SI (and:SI (match_dup 0) (const_int 65535))
388 (match_operand:SI 1 "immediate_operand" "i")))]
391 [(set_attr "type" "mvi")
392 (set_attr "length" "4")])
394 (define_insn "movsi_low"
395 [(set (match_operand:SI 0 "register_operand" "=x")
396 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
397 (match_operand:SI 2 "immediate_operand" "i")))]
400 [(set_attr "type" "mvi")
401 (set_attr "length" "4")])
403 (define_insn "movsi_high_pic"
404 [(set (match_operand:SI 0 "register_operand" "=x")
405 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
409 [(set_attr "type" "mvi")
410 (set_attr "length" "4")])
412 (define_insn "movsi_low_pic"
413 [(set (match_operand:SI 0 "register_operand" "=x")
414 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
415 (unspec:SI [(match_operand:SI 2 "" "")]
418 "%h0 = %h2@GOT_HIGH;"
419 [(set_attr "type" "mvi")
420 (set_attr "length" "4")])
422 ;;; Move instructions
424 (define_insn_and_split "movdi_insn"
425 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
426 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
427 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
430 [(set (match_dup 2) (match_dup 3))
431 (set (match_dup 4) (match_dup 5))]
433 rtx lo_half[2], hi_half[2];
434 split_di (operands, 2, lo_half, hi_half);
436 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
438 operands[2] = hi_half[0];
439 operands[3] = hi_half[1];
440 operands[4] = lo_half[0];
441 operands[5] = lo_half[1];
445 operands[2] = lo_half[0];
446 operands[3] = lo_half[1];
447 operands[4] = hi_half[0];
448 operands[5] = hi_half[1];
453 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
454 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
464 R0 = R0 | R0; CC = AC0;"
465 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
466 (set_attr "length" "2,2,*,*,2,2,4")
467 (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
469 (define_insn "movpdi"
470 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
471 (match_operand:PDI 1 "general_operand" " e,e,>"))]
477 [(set_attr "type" "move,mcst,mcld")
478 (set_attr "seq_insns" "*,multi,multi")])
480 (define_insn "load_accumulator"
481 [(set (match_operand:PDI 0 "register_operand" "=e")
482 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
485 [(set_attr "type" "move")])
487 (define_insn_and_split "load_accumulator_pair"
488 [(set (match_operand:V2PDI 0 "register_operand" "=e")
489 (sign_extend:V2PDI (vec_concat:V2SI
490 (match_operand:SI 1 "register_operand" "d")
491 (match_operand:SI 2 "register_operand" "d"))))]
495 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
496 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
498 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
499 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
502 (define_insn "*pushsi_insn"
503 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
504 (match_operand:SI 0 "register_operand" "xy"))]
507 [(set_attr "type" "mcst")
508 (set_attr "addrtype" "32bit")
509 (set_attr "length" "2")])
511 (define_insn "*popsi_insn"
512 [(set (match_operand:SI 0 "register_operand" "=d,xy")
513 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
516 [(set_attr "type" "mcld")
517 (set_attr "addrtype" "preg,32bit")
518 (set_attr "length" "2")])
520 ;; The first alternative is used to make reload choose a limited register
521 ;; class when faced with a movsi_insn that had its input operand replaced
522 ;; with a PLUS. We generally require fewer secondary reloads this way.
524 (define_insn "*movsi_insn"
525 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr")
526 (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))]
527 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
539 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
540 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
542 (define_insn "*movsi_insn32"
543 [(set (match_operand:SI 0 "register_operand" "=d,d")
544 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
549 [(set_attr "type" "dsp32")])
552 [(set (match_operand:SI 0 "d_register_operand" "")
554 "splitting_for_sched && !optimize_size"
555 [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
558 [(set (match_operand:SI 0 "d_register_operand" "")
559 (match_operand:SI 1 "d_register_operand" ""))]
560 "splitting_for_sched && !optimize_size"
561 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
563 (define_insn_and_split "*movv2hi_insn"
564 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
565 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
567 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
573 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
574 [(set (match_dup 0) (high:SI (match_dup 2)))
575 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
577 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
578 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
580 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
581 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
583 [(set_attr "type" "move,move,mcld,mcst")
584 (set_attr "length" "2,2,*,*")])
586 (define_insn "*movhi_insn"
587 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
588 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
589 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
591 static const char *templates[] = {
600 int alt = which_alternative;
601 rtx mem = (MEM_P (operands[0]) ? operands[0]
602 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
603 if (mem && bfin_dsp_memref_p (mem))
605 return templates[alt];
607 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
608 (set_attr "length" "2,2,4,*,*")])
610 (define_insn "*movqi_insn"
611 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
612 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
613 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
620 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
621 (set_attr "length" "2,2,4,*,*")])
623 (define_insn "*movsf_insn"
624 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
625 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
626 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
632 [(set_attr "type" "move,*,mcld,mcst")])
634 (define_insn_and_split "movdf_insn"
635 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
636 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
637 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
640 [(set (match_dup 2) (match_dup 3))
641 (set (match_dup 4) (match_dup 5))]
643 rtx lo_half[2], hi_half[2];
644 split_di (operands, 2, lo_half, hi_half);
646 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
648 operands[2] = hi_half[0];
649 operands[3] = hi_half[1];
650 operands[4] = lo_half[0];
651 operands[5] = lo_half[1];
655 operands[2] = lo_half[0];
656 operands[3] = lo_half[1];
657 operands[4] = hi_half[0];
658 operands[5] = hi_half[1];
662 ;; Storing halfwords.
663 (define_insn "*movsi_insv"
664 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
667 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
672 [(set_attr "type" "dsp32,mvi")])
674 (define_expand "insv"
675 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
676 (match_operand:SI 1 "immediate_operand" "")
677 (match_operand:SI 2 "immediate_operand" ""))
678 (match_operand:SI 3 "nonmemory_operand" ""))]
681 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
684 /* From mips.md: insert_bit_field doesn't verify that our source
685 matches the predicate, so check it again here. */
686 if (! register_operand (operands[0], VOIDmode))
690 ;; This is the main "hook" for PIC code. When generating
691 ;; PIC, movsi is responsible for determining when the source address
692 ;; needs PIC relocation and appropriately calling legitimize_pic_address
693 ;; to perform the actual relocation.
695 (define_expand "movsi"
696 [(set (match_operand:SI 0 "nonimmediate_operand" "")
697 (match_operand:SI 1 "general_operand" ""))]
700 if (expand_move (operands, SImode))
704 (define_expand "movv2hi"
705 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
706 (match_operand:V2HI 1 "general_operand" ""))]
708 "expand_move (operands, V2HImode);")
710 (define_expand "movdi"
711 [(set (match_operand:DI 0 "nonimmediate_operand" "")
712 (match_operand:DI 1 "general_operand" ""))]
714 "expand_move (operands, DImode);")
716 (define_expand "movsf"
717 [(set (match_operand:SF 0 "nonimmediate_operand" "")
718 (match_operand:SF 1 "general_operand" ""))]
720 "expand_move (operands, SFmode);")
722 (define_expand "movdf"
723 [(set (match_operand:DF 0 "nonimmediate_operand" "")
724 (match_operand:DF 1 "general_operand" ""))]
726 "expand_move (operands, DFmode);")
728 (define_expand "movhi"
729 [(set (match_operand:HI 0 "nonimmediate_operand" "")
730 (match_operand:HI 1 "general_operand" ""))]
732 "expand_move (operands, HImode);")
734 (define_expand "movqi"
735 [(set (match_operand:QI 0 "nonimmediate_operand" "")
736 (match_operand:QI 1 "general_operand" ""))]
738 " expand_move (operands, QImode); ")
740 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
743 [(set (match_operand:SI 0 "register_operand" "")
744 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
746 /* Always split symbolic operands; split integer constants that are
747 too large for a single instruction. */
748 && (GET_CODE (operands[1]) != CONST_INT
749 || (INTVAL (operands[1]) < -32768
750 || INTVAL (operands[1]) >= 65536
751 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
752 [(set (match_dup 0) (high:SI (match_dup 1)))
753 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
755 if (GET_CODE (operands[1]) == CONST_INT
756 && split_load_immediate (operands))
758 /* ??? Do something about TARGET_LOW_64K. */
762 [(set (match_operand:SF 0 "register_operand" "")
763 (match_operand:SF 1 "immediate_operand" ""))]
765 [(set (match_dup 2) (high:SI (match_dup 3)))
766 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
769 REAL_VALUE_TYPE value;
771 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
773 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
774 REAL_VALUE_TO_TARGET_SINGLE (value, values);
776 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
777 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
778 if (values >= -32768 && values < 65536)
780 emit_move_insn (operands[2], operands[3]);
783 if (split_load_immediate (operands + 2))
787 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
788 ;; expects to be able to use registers for operand 1.
789 ;; Note that the asm instruction is defined by the manual to take an unsigned
790 ;; constant, but it doesn't matter to the assembler, and the compiler only
791 ;; deals with sign-extended constants. Hence "Ksh".
792 (define_insn "movstricthi_1"
793 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
794 (match_operand:HI 1 "immediate_operand" "Ksh"))]
797 [(set_attr "type" "mvi")
798 (set_attr "length" "4")])
800 ;; Sign and zero extensions
802 (define_insn_and_split "extendhisi2"
803 [(set (match_operand:SI 0 "register_operand" "=d, d")
804 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
809 "reload_completed && bfin_dsp_memref_p (operands[1])"
810 [(set (match_dup 2) (match_dup 1))
811 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
813 operands[2] = gen_lowpart (HImode, operands[0]);
815 [(set_attr "type" "alu0,mcld")])
817 (define_insn_and_split "zero_extendhisi2"
818 [(set (match_operand:SI 0 "register_operand" "=d, d")
819 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
824 "reload_completed && bfin_dsp_memref_p (operands[1])"
825 [(set (match_dup 2) (match_dup 1))
826 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
828 operands[2] = gen_lowpart (HImode, operands[0]);
830 [(set_attr "type" "alu0,mcld")])
832 (define_insn "zero_extendbisi2"
833 [(set (match_operand:SI 0 "register_operand" "=d")
834 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
837 [(set_attr "type" "compare")])
839 (define_insn "extendqihi2"
840 [(set (match_operand:HI 0 "register_operand" "=d, d")
841 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
846 [(set_attr "type" "mcld,alu0")])
848 (define_insn "extendqisi2"
849 [(set (match_operand:SI 0 "register_operand" "=d, d")
850 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
855 [(set_attr "type" "mcld,alu0")])
858 (define_insn "zero_extendqihi2"
859 [(set (match_operand:HI 0 "register_operand" "=d, d")
860 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
865 [(set_attr "type" "mcld,alu0")])
868 (define_insn "zero_extendqisi2"
869 [(set (match_operand:SI 0 "register_operand" "=d, d")
870 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
875 [(set_attr "type" "mcld,alu0")])
877 ;; DImode logical operations
879 (define_code_macro any_logical [and ior xor])
880 (define_code_attr optab [(and "and")
883 (define_code_attr op [(and "&")
886 (define_code_attr high_result [(and "0")
890 (define_insn "<optab>di3"
891 [(set (match_operand:DI 0 "register_operand" "=d")
892 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
893 (match_operand:DI 2 "register_operand" "d")))]
895 "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
896 [(set_attr "length" "4")
897 (set_attr "seq_insns" "multi")])
899 (define_insn "*<optab>di_zesidi_di"
900 [(set (match_operand:DI 0 "register_operand" "=d")
901 (any_logical:DI (zero_extend:DI
902 (match_operand:SI 2 "register_operand" "d"))
903 (match_operand:DI 1 "register_operand" "d")))]
905 "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;"
906 [(set_attr "length" "4")
907 (set_attr "seq_insns" "multi")])
909 (define_insn "*<optab>di_sesdi_di"
910 [(set (match_operand:DI 0 "register_operand" "=d")
911 (any_logical:DI (sign_extend:DI
912 (match_operand:SI 2 "register_operand" "d"))
913 (match_operand:DI 1 "register_operand" "0")))
914 (clobber (match_scratch:SI 3 "=&d"))]
916 "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
917 [(set_attr "length" "8")
918 (set_attr "seq_insns" "multi")])
920 (define_insn "negdi2"
921 [(set (match_operand:DI 0 "register_operand" "=d")
922 (neg:DI (match_operand:DI 1 "register_operand" "d")))
923 (clobber (match_scratch:SI 2 "=&d"))
924 (clobber (reg:CC REG_CC))]
926 "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
927 [(set_attr "length" "16")
928 (set_attr "seq_insns" "multi")])
930 (define_insn "one_cmpldi2"
931 [(set (match_operand:DI 0 "register_operand" "=d")
932 (not:DI (match_operand:DI 1 "register_operand" "d")))]
934 "%0 = ~%1;\\n\\t%H0 = ~%H1;"
935 [(set_attr "length" "4")
936 (set_attr "seq_insns" "multi")])
938 ;; DImode zero and sign extend patterns
940 (define_insn_and_split "zero_extendsidi2"
941 [(set (match_operand:DI 0 "register_operand" "=d")
942 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
946 [(set (match_dup 3) (const_int 0))]
948 split_di (operands, 1, operands + 2, operands + 3);
949 if (REGNO (operands[0]) != REGNO (operands[1]))
950 emit_move_insn (operands[2], operands[1]);
953 (define_insn "zero_extendqidi2"
954 [(set (match_operand:DI 0 "register_operand" "=d")
955 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
957 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
958 [(set_attr "length" "4")
959 (set_attr "seq_insns" "multi")])
961 (define_insn "zero_extendhidi2"
962 [(set (match_operand:DI 0 "register_operand" "=d")
963 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
965 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
966 [(set_attr "length" "4")
967 (set_attr "seq_insns" "multi")])
969 (define_insn_and_split "extendsidi2"
970 [(set (match_operand:DI 0 "register_operand" "=d")
971 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
975 [(set (match_dup 3) (match_dup 1))
976 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
978 split_di (operands, 1, operands + 2, operands + 3);
979 if (REGNO (operands[0]) != REGNO (operands[1]))
980 emit_move_insn (operands[2], operands[1]);
983 (define_insn_and_split "extendqidi2"
984 [(set (match_operand:DI 0 "register_operand" "=d")
985 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
989 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
990 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
991 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
993 split_di (operands, 1, operands + 2, operands + 3);
996 (define_insn_and_split "extendhidi2"
997 [(set (match_operand:DI 0 "register_operand" "=d")
998 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
1002 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1003 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1004 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1006 split_di (operands, 1, operands + 2, operands + 3);
1009 ;; DImode arithmetic operations
1011 (define_insn "add_with_carry"
1012 [(set (match_operand:SI 0 "register_operand" "=d,d")
1013 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1014 (match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
1015 (set (match_operand:SI 3 "register_operand" "=d,d")
1017 (lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1))
1018 (zero_extend:DI (match_dup 2)))
1020 (clobber (reg:CC 34))]
1023 %0 += %2; cc = ac0; %3 = cc;
1024 %0 = %0 + %2; cc = ac0; %3 = cc;"
1025 [(set_attr "type" "alu0")
1026 (set_attr "length" "6")
1027 (set_attr "seq_insns" "multi")])
1029 (define_insn "adddi3"
1030 [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
1031 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
1032 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
1033 (clobber (match_scratch:SI 3 "=&d,&d,&d"))
1034 (clobber (reg:CC 34))]
1037 %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
1038 %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
1039 %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
1040 [(set_attr "type" "alu0")
1041 (set_attr "length" "10,8,10")
1042 (set_attr "seq_insns" "multi,multi,multi")])
1044 (define_insn "subdi3"
1045 [(set (match_operand:DI 0 "register_operand" "=&d")
1046 (minus:DI (match_operand:DI 1 "register_operand" "0")
1047 (match_operand:DI 2 "register_operand" "d")))
1048 (clobber (reg:CC 34))]
1050 "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1051 [(set_attr "length" "10")
1052 (set_attr "seq_insns" "multi")])
1054 (define_insn "*subdi_di_zesidi"
1055 [(set (match_operand:DI 0 "register_operand" "=d")
1056 (minus:DI (match_operand:DI 1 "register_operand" "0")
1058 (match_operand:SI 2 "register_operand" "d"))))
1059 (clobber (match_scratch:SI 3 "=&d"))
1060 (clobber (reg:CC 34))]
1062 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
1063 [(set_attr "length" "10")
1064 (set_attr "seq_insns" "multi")])
1066 (define_insn "*subdi_zesidi_di"
1067 [(set (match_operand:DI 0 "register_operand" "=d")
1068 (minus:DI (zero_extend:DI
1069 (match_operand:SI 2 "register_operand" "d"))
1070 (match_operand:DI 1 "register_operand" "0")))
1071 (clobber (match_scratch:SI 3 "=&d"))
1072 (clobber (reg:CC 34))]
1074 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
1075 [(set_attr "length" "12")
1076 (set_attr "seq_insns" "multi")])
1078 (define_insn "*subdi_di_sesidi"
1079 [(set (match_operand:DI 0 "register_operand" "=d")
1080 (minus:DI (match_operand:DI 1 "register_operand" "0")
1082 (match_operand:SI 2 "register_operand" "d"))))
1083 (clobber (match_scratch:SI 3 "=&d"))
1084 (clobber (reg:CC 34))]
1086 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1087 [(set_attr "length" "14")
1088 (set_attr "seq_insns" "multi")])
1090 (define_insn "*subdi_sesidi_di"
1091 [(set (match_operand:DI 0 "register_operand" "=d")
1092 (minus:DI (sign_extend:DI
1093 (match_operand:SI 2 "register_operand" "d"))
1094 (match_operand:DI 1 "register_operand" "0")))
1095 (clobber (match_scratch:SI 3 "=&d"))
1096 (clobber (reg:CC 34))]
1098 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1099 [(set_attr "length" "14")
1100 (set_attr "seq_insns" "multi")])
1102 ;; Combined shift/add instructions
1105 [(set (match_operand:SI 0 "register_operand" "=a,d")
1106 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1107 (match_operand:SI 2 "register_operand" "a,d"))
1108 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
1110 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
1111 [(set_attr "type" "alu0")])
1114 [(set (match_operand:SI 0 "register_operand" "=a")
1115 (plus:SI (match_operand:SI 1 "register_operand" "a")
1116 (mult:SI (match_operand:SI 2 "register_operand" "a")
1117 (match_operand:SI 3 "scale_by_operand" "i"))))]
1119 "%0 = %1 + (%2 << %X3);"
1120 [(set_attr "type" "alu0")])
1123 [(set (match_operand:SI 0 "register_operand" "=a")
1124 (plus:SI (match_operand:SI 1 "register_operand" "a")
1125 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1126 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1128 "%0 = %1 + (%2 << %3);"
1129 [(set_attr "type" "alu0")])
1132 [(set (match_operand:SI 0 "register_operand" "=a")
1133 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1134 (match_operand:SI 2 "scale_by_operand" "i"))
1135 (match_operand:SI 3 "register_operand" "a")))]
1137 "%0 = %3 + (%1 << %X2);"
1138 [(set_attr "type" "alu0")])
1141 [(set (match_operand:SI 0 "register_operand" "=a")
1142 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1143 (match_operand:SI 2 "pos_scale_operand" "i"))
1144 (match_operand:SI 3 "register_operand" "a")))]
1146 "%0 = %3 + (%1 << %2);"
1147 [(set_attr "type" "alu0")])
1149 (define_insn "mulhisi3"
1150 [(set (match_operand:SI 0 "register_operand" "=d")
1151 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1152 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1154 "%0 = %h1 * %h2 (IS)%!"
1155 [(set_attr "type" "dsp32")])
1157 (define_insn "umulhisi3"
1158 [(set (match_operand:SI 0 "register_operand" "=d")
1159 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1160 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1162 "%0 = %h1 * %h2 (FU)%!"
1163 [(set_attr "type" "dsp32")])
1165 (define_insn "usmulhisi3"
1166 [(set (match_operand:SI 0 "register_operand" "=W")
1167 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1168 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1170 "%0 = %h2 * %h1 (IS,M)%!"
1171 [(set_attr "type" "dsp32")])
1173 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1174 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1175 ;; The same applies to the add/subtract constant versions involving
1178 (define_insn "addsi3"
1179 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1180 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1181 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1187 [(set_attr "type" "alu0")
1188 (set_attr "length" "2,2,2")])
1190 (define_insn "ssaddsi3"
1191 [(set (match_operand:SI 0 "register_operand" "=d")
1192 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1193 (match_operand:SI 2 "register_operand" "d")))]
1195 "%0 = %1 + %2 (S)%!"
1196 [(set_attr "type" "dsp32")])
1198 (define_insn "subsi3"
1199 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1200 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1201 (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
1204 static const char *const strings_subsi3[] = {
1210 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1211 rtx tmp_op = operands[2];
1212 operands[2] = GEN_INT (-INTVAL (operands[2]));
1213 output_asm_insn ("%0 += %2;", operands);
1214 operands[2] = tmp_op;
1218 return strings_subsi3[which_alternative];
1220 [(set_attr "type" "alu0")])
1222 (define_insn "sssubsi3"
1223 [(set (match_operand:SI 0 "register_operand" "=d")
1224 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1225 (match_operand:SI 2 "register_operand" "d")))]
1227 "%0 = %1 - %2 (S)%!"
1228 [(set_attr "type" "dsp32")])
1230 ;; Accumulator addition
1232 (define_insn "sum_of_accumulators"
1233 [(set (match_operand:SI 0 "register_operand" "=d")
1235 (ss_plus:PDI (match_operand:PDI 2 "register_operand" "1")
1236 (match_operand:PDI 3 "register_operand" "B"))))
1237 (set (match_operand:PDI 1 "register_operand" "=A")
1238 (ss_plus:PDI (match_dup 2) (match_dup 3)))]
1241 [(set_attr "type" "dsp32")])
1243 ;; Bit test instructions
1245 (define_insn "*not_bittst"
1246 [(set (match_operand:BI 0 "register_operand" "=C")
1247 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1249 (match_operand:SI 2 "immediate_operand" "Ku5"))
1252 "cc = !BITTST (%1,%2);"
1253 [(set_attr "type" "alu0")])
1255 (define_insn "*bittst"
1256 [(set (match_operand:BI 0 "register_operand" "=C")
1257 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1259 (match_operand:SI 2 "immediate_operand" "Ku5"))
1262 "cc = BITTST (%1,%2);"
1263 [(set_attr "type" "alu0")])
1265 (define_insn_and_split "*bit_extract"
1266 [(set (match_operand:SI 0 "register_operand" "=d")
1267 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1269 (match_operand:SI 2 "immediate_operand" "Ku5")))
1270 (clobber (reg:BI REG_CC))]
1274 [(set (reg:BI REG_CC)
1275 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1278 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1280 (define_insn_and_split "*not_bit_extract"
1281 [(set (match_operand:SI 0 "register_operand" "=d")
1282 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1284 (match_operand:SI 2 "immediate_operand" "Ku5")))
1285 (clobber (reg:BI REG_CC))]
1289 [(set (reg:BI REG_CC)
1290 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1293 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1295 (define_insn "*andsi_insn"
1296 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1297 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1298 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1305 [(set_attr "type" "alu0")])
1307 (define_expand "andsi3"
1308 [(set (match_operand:SI 0 "register_operand" "")
1309 (and:SI (match_operand:SI 1 "register_operand" "")
1310 (match_operand:SI 2 "general_operand" "")))]
1313 if (highbits_operand (operands[2], SImode))
1315 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1316 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1317 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1320 if (! rhs_andsi3_operand (operands[2], SImode))
1321 operands[2] = force_reg (SImode, operands[2]);
1324 (define_insn "iorsi3"
1325 [(set (match_operand:SI 0 "register_operand" "=d,d")
1326 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1327 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1332 [(set_attr "type" "alu0")])
1334 (define_insn "xorsi3"
1335 [(set (match_operand:SI 0 "register_operand" "=d,d")
1336 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1337 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1342 [(set_attr "type" "alu0")])
1344 (define_insn "smaxsi3"
1345 [(set (match_operand:SI 0 "register_operand" "=d")
1346 (smax:SI (match_operand:SI 1 "register_operand" "d")
1347 (match_operand:SI 2 "register_operand" "d")))]
1350 [(set_attr "type" "dsp32")])
1352 (define_insn "sminsi3"
1353 [(set (match_operand:SI 0 "register_operand" "=d")
1354 (smin:SI (match_operand:SI 1 "register_operand" "d")
1355 (match_operand:SI 2 "register_operand" "d")))]
1358 [(set_attr "type" "dsp32")])
1360 (define_insn "abssi2"
1361 [(set (match_operand:SI 0 "register_operand" "=d")
1362 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1365 [(set_attr "type" "dsp32")])
1367 (define_insn "negsi2"
1368 [(set (match_operand:SI 0 "register_operand" "=d")
1369 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1372 [(set_attr "type" "alu0")])
1374 (define_insn "ssnegsi2"
1375 [(set (match_operand:SI 0 "register_operand" "=d")
1376 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1379 [(set_attr "type" "dsp32")])
1381 (define_insn "one_cmplsi2"
1382 [(set (match_operand:SI 0 "register_operand" "=d")
1383 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1386 [(set_attr "type" "alu0")])
1388 (define_insn "signbitssi2"
1389 [(set (match_operand:HI 0 "register_operand" "=d")
1391 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1392 (clz:HI (not:SI (match_dup 1)))
1393 (clz:HI (match_dup 1))))]
1395 "%h0 = signbits %1%!"
1396 [(set_attr "type" "dsp32")])
1398 (define_insn "smaxhi3"
1399 [(set (match_operand:HI 0 "register_operand" "=d")
1400 (smax:HI (match_operand:HI 1 "register_operand" "d")
1401 (match_operand:HI 2 "register_operand" "d")))]
1403 "%0 = max(%1,%2) (V)%!"
1404 [(set_attr "type" "dsp32")])
1406 (define_insn "sminhi3"
1407 [(set (match_operand:HI 0 "register_operand" "=d")
1408 (smin:HI (match_operand:HI 1 "register_operand" "d")
1409 (match_operand:HI 2 "register_operand" "d")))]
1411 "%0 = min(%1,%2) (V)%!"
1412 [(set_attr "type" "dsp32")])
1414 (define_insn "abshi2"
1415 [(set (match_operand:HI 0 "register_operand" "=d")
1416 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1419 [(set_attr "type" "dsp32")])
1421 (define_insn "neghi2"
1422 [(set (match_operand:HI 0 "register_operand" "=d")
1423 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1426 [(set_attr "type" "alu0")])
1428 (define_insn "ssneghi2"
1429 [(set (match_operand:HI 0 "register_operand" "=d")
1430 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1433 [(set_attr "type" "dsp32")])
1435 (define_insn "signbitshi2"
1436 [(set (match_operand:HI 0 "register_operand" "=d")
1438 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1439 (clz:HI (not:HI (match_dup 1)))
1440 (clz:HI (match_dup 1))))]
1442 "%h0 = signbits %h1%!"
1443 [(set_attr "type" "dsp32")])
1445 (define_insn "mulsi3"
1446 [(set (match_operand:SI 0 "register_operand" "=d")
1447 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1448 (match_operand:SI 2 "register_operand" "d")))]
1451 [(set_attr "type" "mult")])
1453 (define_expand "umulsi3_highpart"
1455 [(set (match_operand:SI 0 "register_operand" "")
1458 (mult:DI (zero_extend:DI
1459 (match_operand:SI 1 "nonimmediate_operand" ""))
1461 (match_operand:SI 2 "register_operand" "")))
1463 (clobber (reg:PDI REG_A0))
1464 (clobber (reg:PDI REG_A1))])]
1469 rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
1470 rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
1471 emit_insn (gen_flag_macinit1hi (a1reg,
1472 gen_lowpart (HImode, operands[1]),
1473 gen_lowpart (HImode, operands[2]),
1474 GEN_INT (MACFLAG_FU)));
1475 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1476 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
1477 gen_lowpart (V2HImode, operands[1]),
1478 gen_lowpart (V2HImode, operands[2]),
1479 const1_rtx, const1_rtx,
1480 const1_rtx, const0_rtx, a1reg,
1481 const0_rtx, GEN_INT (MACFLAG_FU),
1482 GEN_INT (MACFLAG_FU)));
1483 emit_insn (gen_flag_machi_parts_acconly (a1reg,
1484 gen_lowpart (V2HImode, operands[2]),
1485 gen_lowpart (V2HImode, operands[1]),
1486 const1_rtx, const0_rtx,
1487 a1reg, const0_rtx, GEN_INT (MACFLAG_FU)));
1488 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1489 emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg));
1493 rtx umulsi3_highpart_libfunc
1494 = init_one_libfunc ("__umulsi3_highpart");
1496 emit_library_call_value (umulsi3_highpart_libfunc,
1497 operands[0], LCT_NORMAL, SImode,
1498 2, operands[1], SImode, operands[2], SImode);
1503 (define_expand "smulsi3_highpart"
1505 [(set (match_operand:SI 0 "register_operand" "")
1508 (mult:DI (sign_extend:DI
1509 (match_operand:SI 1 "nonimmediate_operand" ""))
1511 (match_operand:SI 2 "register_operand" "")))
1513 (clobber (reg:PDI REG_A0))
1514 (clobber (reg:PDI REG_A1))])]
1519 rtx a1reg = gen_rtx_REG (PDImode, REG_A1);
1520 rtx a0reg = gen_rtx_REG (PDImode, REG_A0);
1521 emit_insn (gen_flag_macinit1hi (a1reg,
1522 gen_lowpart (HImode, operands[1]),
1523 gen_lowpart (HImode, operands[2]),
1524 GEN_INT (MACFLAG_FU)));
1525 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
1526 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg,
1527 gen_lowpart (V2HImode, operands[1]),
1528 gen_lowpart (V2HImode, operands[2]),
1529 const1_rtx, const1_rtx,
1530 const1_rtx, const0_rtx, a1reg,
1531 const0_rtx, GEN_INT (MACFLAG_IS),
1532 GEN_INT (MACFLAG_IS_M)));
1533 emit_insn (gen_flag_machi_parts_acconly (a1reg,
1534 gen_lowpart (V2HImode, operands[2]),
1535 gen_lowpart (V2HImode, operands[1]),
1536 const1_rtx, const0_rtx,
1537 a1reg, const0_rtx, GEN_INT (MACFLAG_IS_M)));
1538 emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (16)));
1539 emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg));
1543 rtx smulsi3_highpart_libfunc
1544 = init_one_libfunc ("__smulsi3_highpart");
1546 emit_library_call_value (smulsi3_highpart_libfunc,
1547 operands[0], LCT_NORMAL, SImode,
1548 2, operands[1], SImode, operands[2], SImode);
1553 (define_expand "ashlsi3"
1554 [(set (match_operand:SI 0 "register_operand" "")
1555 (ashift:SI (match_operand:SI 1 "register_operand" "")
1556 (match_operand:SI 2 "nonmemory_operand" "")))]
1559 if (GET_CODE (operands[2]) == CONST_INT
1560 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1562 emit_insn (gen_movsi (operands[0], const0_rtx));
1567 (define_insn_and_split "*ashlsi3_insn"
1568 [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
1569 (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
1570 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
1578 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1579 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1580 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1581 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1582 [(set_attr "type" "shft,dsp32,shft,shft,*")])
1584 (define_insn "ashrsi3"
1585 [(set (match_operand:SI 0 "register_operand" "=d,d")
1586 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1587 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1592 [(set_attr "type" "shft,dsp32")])
1594 (define_insn "rotl16"
1595 [(set (match_operand:SI 0 "register_operand" "=d")
1596 (rotate:SI (match_operand:SI 1 "register_operand" "d")
1599 "%0 = PACK (%h1, %d1)%!"
1600 [(set_attr "type" "dsp32")])
1602 (define_expand "rotlsi3"
1603 [(set (match_operand:SI 0 "register_operand" "")
1604 (rotate:SI (match_operand:SI 1 "register_operand" "")
1605 (match_operand:SI 2 "immediate_operand" "")))]
1608 if (INTVAL (operands[2]) != 16)
1612 (define_expand "rotrsi3"
1613 [(set (match_operand:SI 0 "register_operand" "")
1614 (rotatert:SI (match_operand:SI 1 "register_operand" "")
1615 (match_operand:SI 2 "immediate_operand" "")))]
1618 if (INTVAL (operands[2]) != 16)
1620 emit_insn (gen_rotl16 (operands[0], operands[1]));
1625 (define_insn "ror_one"
1626 [(set (match_operand:SI 0 "register_operand" "=d")
1627 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1628 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1629 (set (reg:BI REG_CC)
1630 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1632 "%0 = ROT %1 BY -1%!"
1633 [(set_attr "type" "dsp32")])
1635 (define_insn "rol_one"
1636 [(set (match_operand:SI 0 "register_operand" "+d")
1637 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1638 (zero_extend:SI (reg:BI REG_CC))))
1639 (set (reg:BI REG_CC)
1640 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1642 "%0 = ROT %1 BY 1%!"
1643 [(set_attr "type" "dsp32")])
1645 (define_expand "lshrdi3"
1646 [(set (match_operand:DI 0 "register_operand" "")
1647 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1648 (match_operand:DI 2 "general_operand" "")))]
1651 rtx lo_half[2], hi_half[2];
1653 if (operands[2] != const1_rtx)
1655 if (! rtx_equal_p (operands[0], operands[1]))
1656 emit_move_insn (operands[0], operands[1]);
1658 split_di (operands, 2, lo_half, hi_half);
1660 emit_move_insn (bfin_cc_rtx, const0_rtx);
1661 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1662 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1666 (define_expand "ashrdi3"
1667 [(set (match_operand:DI 0 "register_operand" "")
1668 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1669 (match_operand:DI 2 "general_operand" "")))]
1672 rtx lo_half[2], hi_half[2];
1674 if (operands[2] != const1_rtx)
1676 if (! rtx_equal_p (operands[0], operands[1]))
1677 emit_move_insn (operands[0], operands[1]);
1679 split_di (operands, 2, lo_half, hi_half);
1681 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1682 hi_half[1], const0_rtx));
1683 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1684 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1688 (define_expand "ashldi3"
1689 [(set (match_operand:DI 0 "register_operand" "")
1690 (ashift:DI (match_operand:DI 1 "register_operand" "")
1691 (match_operand:DI 2 "general_operand" "")))]
1694 rtx lo_half[2], hi_half[2];
1696 if (operands[2] != const1_rtx)
1698 if (! rtx_equal_p (operands[0], operands[1]))
1699 emit_move_insn (operands[0], operands[1]);
1701 split_di (operands, 2, lo_half, hi_half);
1703 emit_move_insn (bfin_cc_rtx, const0_rtx);
1704 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1705 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1709 (define_insn "lshrsi3"
1710 [(set (match_operand:SI 0 "register_operand" "=d,d,a")
1711 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
1712 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
1718 [(set_attr "type" "shft,dsp32,shft")])
1720 (define_insn "lshrpdi3"
1721 [(set (match_operand:PDI 0 "register_operand" "=e")
1722 (lshiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1723 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1726 [(set_attr "type" "dsp32")])
1728 (define_insn "ashrpdi3"
1729 [(set (match_operand:PDI 0 "register_operand" "=e")
1730 (ashiftrt:PDI (match_operand:PDI 1 "register_operand" "0")
1731 (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
1734 [(set_attr "type" "dsp32")])
1736 ;; A pattern to reload the equivalent of
1737 ;; (set (Dreg) (plus (FP) (large_constant)))
1739 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1740 ;; using a scratch register
1741 (define_expand "reload_insi"
1742 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1743 (match_operand:SI 1 "fp_plus_const_operand" ""))
1744 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1747 rtx fp_op = XEXP (operands[1], 0);
1748 rtx const_op = XEXP (operands[1], 1);
1749 rtx primary = operands[0];
1750 rtx scratch = operands[2];
1752 emit_move_insn (scratch, const_op);
1753 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1754 emit_move_insn (primary, scratch);
1758 ;; Jump instructions
1762 (label_ref (match_operand 0 "" "")))]
1765 if (get_attr_length (insn) == 2)
1766 return "jump.s %0;";
1768 return "jump.l %0;";
1770 [(set_attr "type" "br")])
1772 (define_insn "indirect_jump"
1774 (match_operand:SI 0 "register_operand" "a"))]
1777 [(set_attr "type" "misc")])
1779 (define_expand "tablejump"
1780 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1781 (use (label_ref (match_operand 1 "" "")))])]
1784 /* In PIC mode, the table entries are stored PC relative.
1785 Convert the relative address to an absolute address. */
1788 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1790 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1791 op1, NULL_RTX, 0, OPTAB_DIRECT);
1795 (define_insn "*tablejump_internal"
1796 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1797 (use (label_ref (match_operand 1 "" "")))]
1800 [(set_attr "type" "misc")])
1804 ; operand 0 is the loop count pseudo register
1805 ; operand 1 is the number of loop iterations or 0 if it is unknown
1806 ; operand 2 is the maximum number of loop iterations
1807 ; operand 3 is the number of levels of enclosed loops
1808 ; operand 4 is the label to jump to at the top of the loop
1809 (define_expand "doloop_end"
1810 [(parallel [(set (pc) (if_then_else
1811 (ne (match_operand:SI 0 "" "")
1813 (label_ref (match_operand 4 "" ""))
1816 (plus:SI (match_dup 0)
1818 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1819 (clobber (match_scratch:SI 5 ""))])]
1822 /* The loop optimizer doesn't check the predicates... */
1823 if (GET_MODE (operands[0]) != SImode)
1825 /* Due to limitations in the hardware (an initial loop count of 0
1826 does not loop 2^32 times) we must avoid to generate a hardware
1827 loops when we cannot rule out this case. */
1828 if (!flag_unsafe_loop_optimizations
1829 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF)
1831 bfin_hardware_loop ();
1834 (define_insn "loop_end"
1836 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m")
1838 (label_ref (match_operand 1 "" ""))
1843 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1844 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1847 /* loop end %0 %l1 */
1850 [(set_attr "length" "6,10,14")])
1854 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1856 (label_ref (match_operand 1 "" ""))
1861 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1862 (clobber (match_scratch:SI 2 "=&r"))]
1864 [(set (match_dup 2) (match_dup 0))
1865 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1866 (set (match_dup 0) (match_dup 2))
1867 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1869 (if_then_else (eq (reg:BI REG_CC)
1871 (label_ref (match_dup 1))
1875 (define_insn "lsetup_with_autoinit"
1876 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1877 (label_ref (match_operand 1 "" "")))
1878 (set (match_operand:SI 2 "lb_register_operand" "=u")
1879 (label_ref (match_operand 3 "" "")))
1880 (set (match_operand:SI 4 "lc_register_operand" "=k")
1881 (match_operand:SI 5 "register_operand" "a"))]
1883 "LSETUP (%1, %3) %4 = %5;"
1884 [(set_attr "length" "4")])
1886 (define_insn "lsetup_without_autoinit"
1887 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1888 (label_ref (match_operand 1 "" "")))
1889 (set (match_operand:SI 2 "lb_register_operand" "=u")
1890 (label_ref (match_operand 3 "" "")))
1891 (use (match_operand:SI 4 "lc_register_operand" "k"))]
1893 "LSETUP (%1, %3) %4;"
1894 [(set_attr "length" "4")])
1896 ;; Call instructions..
1898 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
1899 ;; the load before a branch after a NULL test, or before a store that
1900 ;; initializes a function descriptor.
1902 (define_insn_and_split "load_funcdescsi"
1903 [(set (match_operand:SI 0 "register_operand" "=a")
1904 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
1905 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
1909 [(set (match_dup 0) (mem:SI (match_dup 1)))])
1911 (define_expand "call"
1912 [(parallel [(call (match_operand:SI 0 "" "")
1913 (match_operand 1 "" ""))
1914 (use (match_operand 2 "" ""))])]
1917 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
1921 (define_expand "sibcall"
1922 [(parallel [(call (match_operand:SI 0 "" "")
1923 (match_operand 1 "" ""))
1924 (use (match_operand 2 "" ""))
1928 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
1932 (define_expand "call_value"
1933 [(parallel [(set (match_operand 0 "register_operand" "")
1934 (call (match_operand:SI 1 "" "")
1935 (match_operand 2 "" "")))
1936 (use (match_operand 3 "" ""))])]
1939 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
1943 (define_expand "sibcall_value"
1944 [(parallel [(set (match_operand 0 "register_operand" "")
1945 (call (match_operand:SI 1 "" "")
1946 (match_operand 2 "" "")))
1947 (use (match_operand 3 "" ""))
1951 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
1955 (define_insn "*call_symbol_fdpic"
1956 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1957 (match_operand 1 "general_operand" "g"))
1958 (use (match_operand:SI 2 "register_operand" "Z"))
1959 (use (match_operand 3 "" ""))]
1960 "! SIBLING_CALL_P (insn)
1961 && GET_CODE (operands[0]) == SYMBOL_REF
1962 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1964 [(set_attr "type" "call")
1965 (set_attr "length" "4")])
1967 (define_insn "*sibcall_symbol_fdpic"
1968 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1969 (match_operand 1 "general_operand" "g"))
1970 (use (match_operand:SI 2 "register_operand" "Z"))
1971 (use (match_operand 3 "" ""))
1973 "SIBLING_CALL_P (insn)
1974 && GET_CODE (operands[0]) == SYMBOL_REF
1975 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1977 [(set_attr "type" "br")
1978 (set_attr "length" "4")])
1980 (define_insn "*call_value_symbol_fdpic"
1981 [(set (match_operand 0 "register_operand" "=d")
1982 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1983 (match_operand 2 "general_operand" "g")))
1984 (use (match_operand:SI 3 "register_operand" "Z"))
1985 (use (match_operand 4 "" ""))]
1986 "! SIBLING_CALL_P (insn)
1987 && GET_CODE (operands[1]) == SYMBOL_REF
1988 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1990 [(set_attr "type" "call")
1991 (set_attr "length" "4")])
1993 (define_insn "*sibcall_value_symbol_fdpic"
1994 [(set (match_operand 0 "register_operand" "=d")
1995 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1996 (match_operand 2 "general_operand" "g")))
1997 (use (match_operand:SI 3 "register_operand" "Z"))
1998 (use (match_operand 4 "" ""))
2000 "SIBLING_CALL_P (insn)
2001 && GET_CODE (operands[1]) == SYMBOL_REF
2002 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
2004 [(set_attr "type" "br")
2005 (set_attr "length" "4")])
2007 (define_insn "*call_insn_fdpic"
2008 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
2009 (match_operand 1 "general_operand" "g"))
2010 (use (match_operand:SI 2 "register_operand" "Z"))
2011 (use (match_operand 3 "" ""))]
2012 "! SIBLING_CALL_P (insn)"
2014 [(set_attr "type" "call")
2015 (set_attr "length" "2")])
2017 (define_insn "*sibcall_insn_fdpic"
2018 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
2019 (match_operand 1 "general_operand" "g"))
2020 (use (match_operand:SI 2 "register_operand" "Z"))
2021 (use (match_operand 3 "" ""))
2023 "SIBLING_CALL_P (insn)"
2025 [(set_attr "type" "br")
2026 (set_attr "length" "2")])
2028 (define_insn "*call_value_insn_fdpic"
2029 [(set (match_operand 0 "register_operand" "=d")
2030 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
2031 (match_operand 2 "general_operand" "g")))
2032 (use (match_operand:SI 3 "register_operand" "Z"))
2033 (use (match_operand 4 "" ""))]
2034 "! SIBLING_CALL_P (insn)"
2036 [(set_attr "type" "call")
2037 (set_attr "length" "2")])
2039 (define_insn "*sibcall_value_insn_fdpic"
2040 [(set (match_operand 0 "register_operand" "=d")
2041 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
2042 (match_operand 2 "general_operand" "g")))
2043 (use (match_operand:SI 3 "register_operand" "Z"))
2044 (use (match_operand 4 "" ""))
2046 "SIBLING_CALL_P (insn)"
2048 [(set_attr "type" "br")
2049 (set_attr "length" "2")])
2051 (define_insn "*call_symbol"
2052 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2053 (match_operand 1 "general_operand" "g"))
2054 (use (match_operand 2 "" ""))]
2055 "! SIBLING_CALL_P (insn)
2056 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2057 && GET_CODE (operands[0]) == SYMBOL_REF
2058 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2060 [(set_attr "type" "call")
2061 (set_attr "length" "4")])
2063 (define_insn "*sibcall_symbol"
2064 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
2065 (match_operand 1 "general_operand" "g"))
2066 (use (match_operand 2 "" ""))
2068 "SIBLING_CALL_P (insn)
2069 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2070 && GET_CODE (operands[0]) == SYMBOL_REF
2071 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
2073 [(set_attr "type" "br")
2074 (set_attr "length" "4")])
2076 (define_insn "*call_value_symbol"
2077 [(set (match_operand 0 "register_operand" "=d")
2078 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2079 (match_operand 2 "general_operand" "g")))
2080 (use (match_operand 3 "" ""))]
2081 "! SIBLING_CALL_P (insn)
2082 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2083 && GET_CODE (operands[1]) == SYMBOL_REF
2084 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2086 [(set_attr "type" "call")
2087 (set_attr "length" "4")])
2089 (define_insn "*sibcall_value_symbol"
2090 [(set (match_operand 0 "register_operand" "=d")
2091 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
2092 (match_operand 2 "general_operand" "g")))
2093 (use (match_operand 3 "" ""))
2095 "SIBLING_CALL_P (insn)
2096 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
2097 && GET_CODE (operands[1]) == SYMBOL_REF
2098 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
2100 [(set_attr "type" "br")
2101 (set_attr "length" "4")])
2103 (define_insn "*call_insn"
2104 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
2105 (match_operand 1 "general_operand" "g"))
2106 (use (match_operand 2 "" ""))]
2107 "! SIBLING_CALL_P (insn)"
2109 [(set_attr "type" "call")
2110 (set_attr "length" "2")])
2112 (define_insn "*sibcall_insn"
2113 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
2114 (match_operand 1 "general_operand" "g"))
2115 (use (match_operand 2 "" ""))
2117 "SIBLING_CALL_P (insn)"
2119 [(set_attr "type" "br")
2120 (set_attr "length" "2")])
2122 (define_insn "*call_value_insn"
2123 [(set (match_operand 0 "register_operand" "=d")
2124 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
2125 (match_operand 2 "general_operand" "g")))
2126 (use (match_operand 3 "" ""))]
2127 "! SIBLING_CALL_P (insn)"
2129 [(set_attr "type" "call")
2130 (set_attr "length" "2")])
2132 (define_insn "*sibcall_value_insn"
2133 [(set (match_operand 0 "register_operand" "=d")
2134 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
2135 (match_operand 2 "general_operand" "g")))
2136 (use (match_operand 3 "" ""))
2138 "SIBLING_CALL_P (insn)"
2140 [(set_attr "type" "br")
2141 (set_attr "length" "2")])
2143 ;; Block move patterns
2145 ;; We cheat. This copies one more word than operand 2 indicates.
2147 (define_insn "rep_movsi"
2148 [(set (match_operand:SI 0 "register_operand" "=&a")
2149 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2150 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2153 (set (match_operand:SI 1 "register_operand" "=&b")
2154 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2155 (ashift:SI (match_dup 2) (const_int 2)))
2157 (set (mem:BLK (match_dup 3))
2158 (mem:BLK (match_dup 4)))
2160 (clobber (match_scratch:HI 5 "=&d"))
2161 (clobber (reg:SI REG_LT1))
2162 (clobber (reg:SI REG_LC1))
2163 (clobber (reg:SI REG_LB1))]
2165 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
2166 [(set_attr "type" "misc")
2167 (set_attr "length" "16")
2168 (set_attr "seq_insns" "multi")])
2170 (define_insn "rep_movhi"
2171 [(set (match_operand:SI 0 "register_operand" "=&a")
2172 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
2173 (ashift:SI (match_operand:SI 2 "register_operand" "a")
2176 (set (match_operand:SI 1 "register_operand" "=&b")
2177 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
2178 (ashift:SI (match_dup 2) (const_int 1)))
2180 (set (mem:BLK (match_dup 3))
2181 (mem:BLK (match_dup 4)))
2183 (clobber (match_scratch:HI 5 "=&d"))
2184 (clobber (reg:SI REG_LT1))
2185 (clobber (reg:SI REG_LC1))
2186 (clobber (reg:SI REG_LB1))]
2188 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
2189 [(set_attr "type" "misc")
2190 (set_attr "length" "16")
2191 (set_attr "seq_insns" "multi")])
2193 (define_expand "movmemsi"
2194 [(match_operand:BLK 0 "general_operand" "")
2195 (match_operand:BLK 1 "general_operand" "")
2196 (match_operand:SI 2 "const_int_operand" "")
2197 (match_operand:SI 3 "const_int_operand" "")]
2200 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
2205 ;; Conditional branch patterns
2206 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2208 ;; The only outcome of this pattern is that global variables
2209 ;; bfin_compare_op[01] are set for use in bcond patterns.
2211 (define_expand "cmpbi"
2212 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
2213 (match_operand:BI 1 "immediate_operand" "")))]
2216 bfin_compare_op0 = operands[0];
2217 bfin_compare_op1 = operands[1];
2221 (define_expand "cmpsi"
2222 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2223 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
2226 bfin_compare_op0 = operands[0];
2227 bfin_compare_op1 = operands[1];
2231 (define_insn "compare_eq"
2232 [(set (match_operand:BI 0 "register_operand" "=C,C")
2233 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2234 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2237 [(set_attr "type" "compare")])
2239 (define_insn "compare_ne"
2240 [(set (match_operand:BI 0 "register_operand" "=C,C")
2241 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
2242 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2245 [(set_attr "type" "compare")])
2247 (define_insn "compare_lt"
2248 [(set (match_operand:BI 0 "register_operand" "=C,C")
2249 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
2250 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2253 [(set_attr "type" "compare")])
2255 (define_insn "compare_le"
2256 [(set (match_operand:BI 0 "register_operand" "=C,C")
2257 (le:BI (match_operand:SI 1 "register_operand" "d,a")
2258 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2261 [(set_attr "type" "compare")])
2263 (define_insn "compare_leu"
2264 [(set (match_operand:BI 0 "register_operand" "=C,C")
2265 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
2266 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2269 [(set_attr "type" "compare")])
2271 (define_insn "compare_ltu"
2272 [(set (match_operand:BI 0 "register_operand" "=C,C")
2273 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2274 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2277 [(set_attr "type" "compare")])
2279 (define_expand "beq"
2280 [(set (match_dup 1) (match_dup 2))
2282 (if_then_else (match_dup 3)
2283 (label_ref (match_operand 0 "" ""))
2287 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2288 operands[1] = bfin_cc_rtx; /* hard register: CC */
2289 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2290 /* If we have a BImode input, then we already have a compare result, and
2291 do not need to emit another comparison. */
2292 if (GET_MODE (bfin_compare_op0) == BImode)
2294 gcc_assert (bfin_compare_op1 == const0_rtx);
2295 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2299 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2302 (define_expand "bne"
2303 [(set (match_dup 1) (match_dup 2))
2305 (if_then_else (match_dup 3)
2306 (label_ref (match_operand 0 "" ""))
2310 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2311 /* If we have a BImode input, then we already have a compare result, and
2312 do not need to emit another comparison. */
2313 if (GET_MODE (bfin_compare_op0) == BImode)
2315 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2317 gcc_assert (bfin_compare_op1 == const0_rtx);
2318 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2322 operands[1] = bfin_cc_rtx; /* hard register: CC */
2323 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2324 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2327 (define_expand "bgt"
2328 [(set (match_dup 1) (match_dup 2))
2330 (if_then_else (match_dup 3)
2331 (label_ref (match_operand 0 "" ""))
2335 operands[1] = bfin_cc_rtx;
2336 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2337 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2340 (define_expand "bgtu"
2341 [(set (match_dup 1) (match_dup 2))
2343 (if_then_else (match_dup 3)
2344 (label_ref (match_operand 0 "" ""))
2348 operands[1] = bfin_cc_rtx;
2349 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2350 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2353 (define_expand "blt"
2354 [(set (match_dup 1) (match_dup 2))
2356 (if_then_else (match_dup 3)
2357 (label_ref (match_operand 0 "" ""))
2361 operands[1] = bfin_cc_rtx;
2362 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2363 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2366 (define_expand "bltu"
2367 [(set (match_dup 1) (match_dup 2))
2369 (if_then_else (match_dup 3)
2370 (label_ref (match_operand 0 "" ""))
2374 operands[1] = bfin_cc_rtx;
2375 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2376 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2380 (define_expand "bge"
2381 [(set (match_dup 1) (match_dup 2))
2383 (if_then_else (match_dup 3)
2384 (label_ref (match_operand 0 "" ""))
2388 operands[1] = bfin_cc_rtx;
2389 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2390 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2393 (define_expand "bgeu"
2394 [(set (match_dup 1) (match_dup 2))
2396 (if_then_else (match_dup 3)
2397 (label_ref (match_operand 0 "" ""))
2401 operands[1] = bfin_cc_rtx;
2402 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2403 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2406 (define_expand "ble"
2407 [(set (match_dup 1) (match_dup 2))
2409 (if_then_else (match_dup 3)
2410 (label_ref (match_operand 0 "" ""))
2414 operands[1] = bfin_cc_rtx;
2415 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2416 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2419 (define_expand "bleu"
2420 [(set (match_dup 1) (match_dup 2))
2422 (if_then_else (match_dup 3)
2423 (label_ref (match_operand 0 "" ""))
2428 operands[1] = bfin_cc_rtx;
2429 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2430 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2433 (define_insn "cbranchbi4"
2436 (match_operator 0 "bfin_cbranch_operator"
2437 [(match_operand:BI 1 "register_operand" "C")
2438 (match_operand:BI 2 "immediate_operand" "P0")])
2439 (label_ref (match_operand 3 "" ""))
2443 asm_conditional_branch (insn, operands, 0, 0);
2446 [(set_attr "type" "brcc")])
2448 ;; Special cbranch patterns to deal with the speculative load problem - see
2449 ;; bfin_reorg for details.
2451 (define_insn "cbranch_predicted_taken"
2454 (match_operator 0 "bfin_cbranch_operator"
2455 [(match_operand:BI 1 "register_operand" "C")
2456 (match_operand:BI 2 "immediate_operand" "P0")])
2457 (label_ref (match_operand 3 "" ""))
2459 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2462 asm_conditional_branch (insn, operands, 0, 1);
2465 [(set_attr "type" "brcc")])
2467 (define_insn "cbranch_with_nops"
2470 (match_operator 0 "bfin_cbranch_operator"
2471 [(match_operand:BI 1 "register_operand" "C")
2472 (match_operand:BI 2 "immediate_operand" "P0")])
2473 (label_ref (match_operand 3 "" ""))
2475 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2478 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2481 [(set_attr "type" "brcc")
2482 (set_attr "length" "6")])
2485 (define_expand "seq"
2486 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
2487 (set (match_operand:SI 0 "register_operand" "")
2488 (ne:SI (match_dup 1) (const_int 0)))]
2491 operands[2] = bfin_compare_op0;
2492 operands[3] = bfin_compare_op1;
2493 operands[1] = bfin_cc_rtx;
2496 (define_expand "slt"
2497 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
2498 (set (match_operand:SI 0 "register_operand" "")
2499 (ne:SI (match_dup 1) (const_int 0)))]
2502 operands[2] = bfin_compare_op0;
2503 operands[3] = bfin_compare_op1;
2504 operands[1] = bfin_cc_rtx;
2507 (define_expand "sle"
2508 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
2509 (set (match_operand:SI 0 "register_operand" "")
2510 (ne:SI (match_dup 1) (const_int 0)))]
2513 operands[2] = bfin_compare_op0;
2514 operands[3] = bfin_compare_op1;
2515 operands[1] = bfin_cc_rtx;
2518 (define_expand "sltu"
2519 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
2520 (set (match_operand:SI 0 "register_operand" "")
2521 (ne:SI (match_dup 1) (const_int 0)))]
2524 operands[2] = bfin_compare_op0;
2525 operands[3] = bfin_compare_op1;
2526 operands[1] = bfin_cc_rtx;
2529 (define_expand "sleu"
2530 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2531 (set (match_operand:SI 0 "register_operand" "")
2532 (ne:SI (match_dup 1) (const_int 0)))]
2535 operands[2] = bfin_compare_op0;
2536 operands[3] = bfin_compare_op1;
2537 operands[1] = bfin_cc_rtx;
2546 [(unspec [(const_int 0)] UNSPEC_32BIT)]
2549 [(set_attr "type" "dsp32")])
2551 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2552 (define_insn "movsibi"
2553 [(set (match_operand:BI 0 "register_operand" "=C")
2554 (ne:BI (match_operand:SI 1 "register_operand" "d")
2558 [(set_attr "length" "2")])
2560 (define_insn "movbisi"
2561 [(set (match_operand:SI 0 "register_operand" "=d")
2562 (ne:SI (match_operand:BI 1 "register_operand" "C")
2566 [(set_attr "length" "2")])
2569 [(set (match_operand:BI 0 "register_operand" "=C")
2570 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2573 "%0 = ! %0;" /* NOT CC;" */
2574 [(set_attr "type" "compare")])
2576 ;; Vector and DSP insns
2579 [(set (match_operand:SI 0 "register_operand" "=d")
2580 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2582 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2585 "%0 = ALIGN8(%1, %2)%!"
2586 [(set_attr "type" "dsp32")])
2589 [(set (match_operand:SI 0 "register_operand" "=d")
2590 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2592 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2595 "%0 = ALIGN16(%1, %2)%!"
2596 [(set_attr "type" "dsp32")])
2599 [(set (match_operand:SI 0 "register_operand" "=d")
2600 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2602 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2605 "%0 = ALIGN24(%1, %2)%!"
2606 [(set_attr "type" "dsp32")])
2608 ;; Prologue and epilogue.
2610 (define_expand "prologue"
2613 "bfin_expand_prologue (); DONE;")
2615 (define_expand "epilogue"
2618 "bfin_expand_epilogue (1, 0); DONE;")
2620 (define_expand "sibcall_epilogue"
2623 "bfin_expand_epilogue (0, 0); DONE;")
2625 (define_expand "eh_return"
2626 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")]
2627 UNSPEC_VOLATILE_EH_RETURN)]
2630 emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
2631 emit_jump_insn (gen_eh_return_internal ());
2636 (define_insn_and_split "eh_return_internal"
2638 (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))]
2643 "bfin_expand_epilogue (1, 1); DONE;")
2646 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2647 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2648 (set (reg:SI REG_FP)
2649 (plus:SI (reg:SI REG_SP) (const_int -8)))
2650 (set (reg:SI REG_SP)
2651 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2654 [(set_attr "length" "4")])
2656 (define_insn "unlink"
2657 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2658 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2659 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2662 [(set_attr "length" "4")])
2664 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2665 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2666 ;; where on the stack, since it goes through all elements of the parallel in
2668 (define_insn "push_multiple"
2669 [(match_parallel 0 "push_multiple_operation"
2670 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2673 output_push_multiple (insn, operands);
2677 (define_insn "pop_multiple"
2678 [(match_parallel 0 "pop_multiple_operation"
2679 [(set (reg:SI REG_SP)
2680 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2683 output_pop_multiple (insn, operands);
2687 (define_insn "return_internal"
2689 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
2692 switch (INTVAL (operands[0]))
2698 case INTERRUPT_HANDLER:
2706 (define_insn "csync"
2707 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2710 [(set_attr "type" "sync")])
2712 (define_insn "ssync"
2713 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2716 [(set_attr "type" "sync")])
2719 [(trap_if (const_int 1) (const_int 3))]
2722 [(set_attr "type" "misc")
2723 (set_attr "length" "2")])
2725 (define_insn "trapifcc"
2726 [(trap_if (reg:BI REG_CC) (const_int 3))]
2728 "if !cc jump 4 (bp); excpt 3;"
2729 [(set_attr "type" "misc")
2730 (set_attr "length" "4")
2731 (set_attr "seq_insns" "multi")])
2733 ;;; Vector instructions
2735 ;; First, all sorts of move variants
2737 (define_insn "movhi_low2high"
2738 [(set (match_operand:V2HI 0 "register_operand" "=d")
2740 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2741 (parallel [(const_int 0)]))
2742 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2743 (parallel [(const_int 0)]))))]
2746 [(set_attr "type" "dsp32")])
2748 (define_insn "movhi_high2high"
2749 [(set (match_operand:V2HI 0 "register_operand" "=d")
2751 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2752 (parallel [(const_int 0)]))
2753 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2754 (parallel [(const_int 1)]))))]
2757 [(set_attr "type" "dsp32")])
2759 (define_insn "movhi_low2low"
2760 [(set (match_operand:V2HI 0 "register_operand" "=d")
2762 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2763 (parallel [(const_int 0)]))
2764 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2765 (parallel [(const_int 1)]))))]
2768 [(set_attr "type" "dsp32")])
2770 (define_insn "movhi_high2low"
2771 [(set (match_operand:V2HI 0 "register_operand" "=d")
2773 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2774 (parallel [(const_int 1)]))
2775 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2776 (parallel [(const_int 1)]))))]
2779 [(set_attr "type" "dsp32")])
2781 (define_insn "movhiv2hi_low"
2782 [(set (match_operand:V2HI 0 "register_operand" "=d")
2784 (match_operand:HI 2 "register_operand" "d")
2785 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2786 (parallel [(const_int 1)]))))]
2789 [(set_attr "type" "dsp32")])
2791 (define_insn "movhiv2hi_high"
2792 [(set (match_operand:V2HI 0 "register_operand" "=d")
2794 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2795 (parallel [(const_int 0)]))
2796 (match_operand:HI 2 "register_operand" "d")))]
2799 [(set_attr "type" "dsp32")])
2801 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2802 ;; The order of operands is intentional to match the VDSP builtin (high word
2803 ;; is passed first).
2804 (define_insn_and_split "composev2hi"
2805 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2806 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2807 (match_operand:HI 1 "register_operand" "d,d")))]
2815 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2820 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2822 [(set_attr "type" "dsp32")])
2824 ; Like composev2hi, but operating on elements of V2HI vectors.
2825 ; Useful on its own, and as a combiner bridge for the multiply and
2827 (define_insn "packv2hi"
2828 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d")
2829 (vec_concat:V2HI (vec_select:HI
2830 (match_operand:V2HI 1 "register_operand" "d,d,d,d")
2831 (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")]))
2833 (match_operand:V2HI 2 "register_operand" "d,d,d,d")
2834 (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))]
2837 %0 = PACK (%h2,%h1)%!
2838 %0 = PACK (%h2,%d1)%!
2839 %0 = PACK (%d2,%h1)%!
2840 %0 = PACK (%d2,%d1)%!"
2841 [(set_attr "type" "dsp32")])
2843 (define_insn "movv2hi_hi"
2844 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2845 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2846 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2852 [(set_attr "type" "dsp32")])
2854 (define_expand "movv2hi_hi_low"
2855 [(set (match_operand:HI 0 "register_operand" "")
2856 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2857 (parallel [(const_int 0)])))]
2861 (define_expand "movv2hi_hi_high"
2862 [(set (match_operand:HI 0 "register_operand" "")
2863 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2864 (parallel [(const_int 1)])))]
2868 ;; Unusual arithmetic operations on 16-bit registers.
2870 (define_insn "ssaddhi3"
2871 [(set (match_operand:HI 0 "register_operand" "=d")
2872 (ss_plus:HI (match_operand:HI 1 "register_operand" "d")
2873 (match_operand:HI 2 "register_operand" "d")))]
2875 "%h0 = %h1 + %h2 (S)%!"
2876 [(set_attr "type" "dsp32")])
2878 (define_insn "sssubhi3"
2879 [(set (match_operand:HI 0 "register_operand" "=d")
2880 (ss_minus:HI (match_operand:HI 1 "register_operand" "d")
2881 (match_operand:HI 2 "register_operand" "d")))]
2883 "%h0 = %h1 - %h2 (S)%!"
2884 [(set_attr "type" "dsp32")])
2886 ;; V2HI vector insns
2888 (define_insn "addv2hi3"
2889 [(set (match_operand:V2HI 0 "register_operand" "=d")
2890 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2891 (match_operand:V2HI 2 "register_operand" "d")))]
2894 [(set_attr "type" "dsp32")])
2896 (define_insn "ssaddv2hi3"
2897 [(set (match_operand:V2HI 0 "register_operand" "=d")
2898 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2899 (match_operand:V2HI 2 "register_operand" "d")))]
2901 "%0 = %1 +|+ %2 (S)%!"
2902 [(set_attr "type" "dsp32")])
2904 (define_insn "subv2hi3"
2905 [(set (match_operand:V2HI 0 "register_operand" "=d")
2906 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2907 (match_operand:V2HI 2 "register_operand" "d")))]
2910 [(set_attr "type" "dsp32")])
2912 (define_insn "sssubv2hi3"
2913 [(set (match_operand:V2HI 0 "register_operand" "=d")
2914 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2915 (match_operand:V2HI 2 "register_operand" "d")))]
2917 "%0 = %1 -|- %2 (S)%!"
2918 [(set_attr "type" "dsp32")])
2920 (define_insn "addsubv2hi3"
2921 [(set (match_operand:V2HI 0 "register_operand" "=d")
2923 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2924 (parallel [(const_int 0)]))
2925 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2926 (parallel [(const_int 0)])))
2927 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2928 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2931 [(set_attr "type" "dsp32")])
2933 (define_insn "subaddv2hi3"
2934 [(set (match_operand:V2HI 0 "register_operand" "=d")
2936 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2937 (parallel [(const_int 0)]))
2938 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2939 (parallel [(const_int 0)])))
2940 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2941 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2944 [(set_attr "type" "dsp32")])
2946 (define_insn "ssaddsubv2hi3"
2947 [(set (match_operand:V2HI 0 "register_operand" "=d")
2949 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2950 (parallel [(const_int 0)]))
2951 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2952 (parallel [(const_int 0)])))
2953 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2954 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2956 "%0 = %1 +|- %2 (S)%!"
2957 [(set_attr "type" "dsp32")])
2959 (define_insn "sssubaddv2hi3"
2960 [(set (match_operand:V2HI 0 "register_operand" "=d")
2962 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2963 (parallel [(const_int 0)]))
2964 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2965 (parallel [(const_int 0)])))
2966 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2967 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2969 "%0 = %1 -|+ %2 (S)%!"
2970 [(set_attr "type" "dsp32")])
2972 (define_insn "sublohiv2hi3"
2973 [(set (match_operand:HI 0 "register_operand" "=d")
2974 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2975 (parallel [(const_int 1)]))
2976 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2977 (parallel [(const_int 0)]))))]
2980 [(set_attr "type" "dsp32")])
2982 (define_insn "subhilov2hi3"
2983 [(set (match_operand:HI 0 "register_operand" "=d")
2984 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2985 (parallel [(const_int 0)]))
2986 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2987 (parallel [(const_int 1)]))))]
2990 [(set_attr "type" "dsp32")])
2992 (define_insn "sssublohiv2hi3"
2993 [(set (match_operand:HI 0 "register_operand" "=d")
2994 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2995 (parallel [(const_int 1)]))
2996 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2997 (parallel [(const_int 0)]))))]
2999 "%h0 = %d1 - %h2 (S)%!"
3000 [(set_attr "type" "dsp32")])
3002 (define_insn "sssubhilov2hi3"
3003 [(set (match_operand:HI 0 "register_operand" "=d")
3004 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3005 (parallel [(const_int 0)]))
3006 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3007 (parallel [(const_int 1)]))))]
3009 "%h0 = %h1 - %d2 (S)%!"
3010 [(set_attr "type" "dsp32")])
3012 (define_insn "addlohiv2hi3"
3013 [(set (match_operand:HI 0 "register_operand" "=d")
3014 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3015 (parallel [(const_int 1)]))
3016 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3017 (parallel [(const_int 0)]))))]
3020 [(set_attr "type" "dsp32")])
3022 (define_insn "addhilov2hi3"
3023 [(set (match_operand:HI 0 "register_operand" "=d")
3024 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3025 (parallel [(const_int 0)]))
3026 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3027 (parallel [(const_int 1)]))))]
3030 [(set_attr "type" "dsp32")])
3032 (define_insn "ssaddlohiv2hi3"
3033 [(set (match_operand:HI 0 "register_operand" "=d")
3034 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3035 (parallel [(const_int 1)]))
3036 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3037 (parallel [(const_int 0)]))))]
3039 "%h0 = %d1 + %h2 (S)%!"
3040 [(set_attr "type" "dsp32")])
3042 (define_insn "ssaddhilov2hi3"
3043 [(set (match_operand:HI 0 "register_operand" "=d")
3044 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3045 (parallel [(const_int 0)]))
3046 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3047 (parallel [(const_int 1)]))))]
3049 "%h0 = %h1 + %d2 (S)%!"
3050 [(set_attr "type" "dsp32")])
3052 (define_insn "sminv2hi3"
3053 [(set (match_operand:V2HI 0 "register_operand" "=d")
3054 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
3055 (match_operand:V2HI 2 "register_operand" "d")))]
3057 "%0 = MIN (%1, %2) (V)%!"
3058 [(set_attr "type" "dsp32")])
3060 (define_insn "smaxv2hi3"
3061 [(set (match_operand:V2HI 0 "register_operand" "=d")
3062 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
3063 (match_operand:V2HI 2 "register_operand" "d")))]
3065 "%0 = MAX (%1, %2) (V)%!"
3066 [(set_attr "type" "dsp32")])
3070 ;; The Blackfin allows a lot of different options, and we need many patterns to
3071 ;; cover most of the hardware's abilities.
3072 ;; There are a few simple patterns using MULT rtx codes, but most of them use
3073 ;; an unspec with a const_int operand that determines which flag to use in the
3075 ;; There are variants for single and parallel multiplications.
3076 ;; There are variants which just use 16-bit lowparts as inputs, and variants
3077 ;; which allow the user to choose just which halves to use as input values.
3078 ;; There are variants which set D registers, variants which set accumulators,
3079 ;; variants which set both, some of them optionally using the accumulators as
3080 ;; inputs for multiply-accumulate operations.
3082 (define_insn "flag_mulhi"
3083 [(set (match_operand:HI 0 "register_operand" "=d")
3084 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
3085 (match_operand:HI 2 "register_operand" "d")
3086 (match_operand 3 "const_int_operand" "n")]
3087 UNSPEC_MUL_WITH_FLAG))]
3089 "%h0 = %h1 * %h2 %M3%!"
3090 [(set_attr "type" "dsp32")])
3092 (define_insn "flag_mulhisi"
3093 [(set (match_operand:SI 0 "register_operand" "=d")
3094 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
3095 (match_operand:HI 2 "register_operand" "d")
3096 (match_operand 3 "const_int_operand" "n")]
3097 UNSPEC_MUL_WITH_FLAG))]
3099 "%0 = %h1 * %h2 %M3%!"
3100 [(set_attr "type" "dsp32")])
3102 (define_insn "flag_mulhisi_parts"
3103 [(set (match_operand:SI 0 "register_operand" "=d")
3104 (unspec:SI [(vec_select:HI
3105 (match_operand:V2HI 1 "register_operand" "d")
3106 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3108 (match_operand:V2HI 2 "register_operand" "d")
3109 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
3110 (match_operand 5 "const_int_operand" "n")]
3111 UNSPEC_MUL_WITH_FLAG))]
3114 const char *templates[] = {
3115 "%0 = %h1 * %h2 %M5%!",
3116 "%0 = %d1 * %h2 %M5%!",
3117 "%0 = %h1 * %d2 %M5%!",
3118 "%0 = %d1 * %d2 %M5%!" };
3119 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3120 return templates[alt];
3122 [(set_attr "type" "dsp32")])
3124 ;; Three alternatives here to cover all possible allocations:
3125 ;; 0. mac flag is usable only for accumulator 1 - use A1 and odd DREG
3126 ;; 1. mac flag is usable for accumulator 0 - use A0 and even DREG
3127 ;; 2. mac flag is usable in any accumulator - use A1 and odd DREG
3128 ;; Other patterns which don't have a DREG destination can collapse cases
3129 ;; 1 and 2 into one.
3130 (define_insn "flag_machi"
3131 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3132 (unspec:HI [(match_operand:HI 2 "register_operand" "d,d,d")
3133 (match_operand:HI 3 "register_operand" "d,d,d")
3134 (match_operand 4 "register_operand" "1,1,1")
3135 (match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")
3136 (match_operand 6 "const_int_operand" "PB,PA,PA")]
3137 UNSPEC_MAC_WITH_FLAG))
3138 (set (match_operand:PDI 1 "register_operand" "=B,A,B")
3139 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
3140 (match_dup 4) (match_dup 5)]
3141 UNSPEC_MAC_WITH_FLAG))]
3143 "%h0 = (%1 %b5 %h2 * %h3) %M6%!"
3144 [(set_attr "type" "dsp32")])
3146 (define_insn "flag_machi_acconly"
3147 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3148 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3149 (match_operand:HI 2 "register_operand" "d,d")
3150 (match_operand 3 "register_operand" "0,0")
3151 (match_operand 4 "const01_operand" "P0P1,P0P1")
3152 (match_operand 5 "const_int_operand" "PB,PA")]
3153 UNSPEC_MAC_WITH_FLAG))]
3155 "%0 %b4 %h1 * %h2 %M5%!"
3156 [(set_attr "type" "dsp32")])
3158 (define_insn "flag_machi_parts_acconly"
3159 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3160 (unspec:PDI [(vec_select:HI
3161 (match_operand:V2HI 1 "register_operand" "d,d")
3162 (parallel [(match_operand 3 "const01_operand" "P0P1,P0P1")]))
3164 (match_operand:V2HI 2 "register_operand" "d,d")
3165 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1")]))
3166 (match_operand:PDI 5 "register_operand" "0,0")
3167 (match_operand 6 "const01_operand" "P0P1,P0P1")
3168 (match_operand 7 "const_int_operand" "PB,PA")]
3169 UNSPEC_MAC_WITH_FLAG))]
3172 const char *templates[] = {
3173 "%0 %b6 %h1 * %h2 %M7%!",
3174 "%0 %b6 %d1 * %h2 %M7%!",
3175 "%0 %b6 %h1 * %d2 %M7%!",
3176 "%0 %b6 %d1 * %d2 %M7%!"
3178 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
3179 return templates[alt];
3181 [(set_attr "type" "dsp32")])
3183 (define_insn "flag_macinithi"
3184 [(set (match_operand:HI 0 "register_operand" "=W,D,W")
3185 (unspec:HI [(match_operand:HI 1 "register_operand" "d,d,d")
3186 (match_operand:HI 2 "register_operand" "d,d,d")
3187 (match_operand 3 "const_int_operand" "PB,PA,PA")]
3188 UNSPEC_MAC_WITH_FLAG))
3189 (set (match_operand:PDI 4 "register_operand" "=B,A,B")
3190 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
3191 UNSPEC_MAC_WITH_FLAG))]
3193 "%h0 = (%4 = %h1 * %h2) %M3%!"
3194 [(set_attr "type" "dsp32")])
3196 (define_insn "flag_macinit1hi"
3197 [(set (match_operand:PDI 0 "register_operand" "=B,e")
3198 (unspec:PDI [(match_operand:HI 1 "register_operand" "d,d")
3199 (match_operand:HI 2 "register_operand" "d,d")
3200 (match_operand 3 "const_int_operand" "PB,PA")]
3201 UNSPEC_MAC_WITH_FLAG))]
3203 "%0 = %h1 * %h2 %M3%!"
3204 [(set_attr "type" "dsp32")])
3206 (define_insn "mulv2hi3"
3207 [(set (match_operand:V2HI 0 "register_operand" "=d")
3208 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
3209 (match_operand:V2HI 2 "register_operand" "d")))]
3211 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
3212 [(set_attr "type" "dsp32")])
3214 (define_insn "flag_mulv2hi"
3215 [(set (match_operand:V2HI 0 "register_operand" "=d")
3216 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
3217 (match_operand:V2HI 2 "register_operand" "d")
3218 (match_operand 3 "const_int_operand" "n")]
3219 UNSPEC_MUL_WITH_FLAG))]
3221 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
3222 [(set_attr "type" "dsp32")])
3224 (define_insn "flag_mulv2hi_parts"
3225 [(set (match_operand:V2HI 0 "register_operand" "=d")
3226 (unspec:V2HI [(vec_concat:V2HI
3228 (match_operand:V2HI 1 "register_operand" "d")
3229 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3232 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3234 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3235 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3236 (vec_select:HI (match_dup 2)
3237 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3238 (match_operand 7 "const_int_operand" "n")]
3239 UNSPEC_MUL_WITH_FLAG))]
3242 const char *templates[] = {
3243 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
3244 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
3245 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
3246 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
3247 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
3248 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
3249 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
3250 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
3251 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
3252 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
3253 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
3254 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
3255 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
3256 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
3257 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
3258 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
3259 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3260 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3261 return templates[alt];
3263 [(set_attr "type" "dsp32")])
3265 ;; A slightly complicated pattern.
3266 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
3267 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
3268 ;; parts of these 2x16 bit registers to use.
3269 ;; Operand 7 is the accumulator input.
3270 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
3271 ;; Operand 10 is the macflag to be used.
3272 (define_insn "flag_macv2hi_parts"
3273 [(set (match_operand:V2HI 0 "register_operand" "=d")
3274 (unspec:V2HI [(vec_concat:V2HI
3276 (match_operand:V2HI 1 "register_operand" "d")
3277 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3280 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3282 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3283 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3284 (vec_select:HI (match_dup 2)
3285 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3286 (match_operand:V2PDI 7 "register_operand" "e")
3287 (match_operand 8 "const01_operand" "P0P1")
3288 (match_operand 9 "const01_operand" "P0P1")
3289 (match_operand 10 "const_int_operand" "n")]
3290 UNSPEC_MAC_WITH_FLAG))
3291 (set (match_operand:V2PDI 11 "register_operand" "=e")
3292 (unspec:V2PDI [(vec_concat:V2HI
3293 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3294 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3296 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3297 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3298 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
3299 UNSPEC_MAC_WITH_FLAG))]
3302 const char *templates[] = {
3303 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3304 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3305 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3306 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3307 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3308 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3309 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3310 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3311 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3312 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3313 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3314 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3315 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3316 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3317 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3318 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
3319 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3320 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3321 return templates[alt];
3323 [(set_attr "type" "dsp32")])
3325 (define_insn "flag_macv2hi_parts_acconly"
3326 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3327 (unspec:V2PDI [(vec_concat:V2HI
3329 (match_operand:V2HI 1 "register_operand" "d")
3330 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3333 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3335 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3336 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3337 (vec_select:HI (match_dup 2)
3338 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3339 (match_operand:V2PDI 7 "register_operand" "e")
3340 (match_operand 8 "const01_operand" "P0P1")
3341 (match_operand 9 "const01_operand" "P0P1")
3342 (match_operand 10 "const_int_operand" "n")]
3343 UNSPEC_MAC_WITH_FLAG))]
3346 const char *templates[] = {
3347 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3348 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3349 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3350 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3351 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3352 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3353 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3354 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3355 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3356 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3357 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3358 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3359 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3360 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3361 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
3362 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
3363 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3364 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3365 return templates[alt];
3367 [(set_attr "type" "dsp32")])
3369 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3370 ;; necessary operands.
3371 (define_insn "flag_macinitv2hi_parts"
3372 [(set (match_operand:V2HI 0 "register_operand" "=d")
3373 (unspec:V2HI [(vec_concat:V2HI
3375 (match_operand:V2HI 1 "register_operand" "d")
3376 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3379 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3381 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3382 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3383 (vec_select:HI (match_dup 2)
3384 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3385 (match_operand 7 "const_int_operand" "n")]
3386 UNSPEC_MAC_WITH_FLAG))
3387 (set (match_operand:V2PDI 8 "register_operand" "=e")
3388 (unspec:V2PDI [(vec_concat:V2HI
3389 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3390 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3392 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3393 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3395 UNSPEC_MAC_WITH_FLAG))]
3398 const char *templates[] = {
3399 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3400 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3401 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3402 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3403 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3404 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3405 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3406 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3407 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3408 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3409 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3410 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3411 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3412 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3413 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
3414 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
3415 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3416 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3417 return templates[alt];
3419 [(set_attr "type" "dsp32")])
3421 (define_insn "flag_macinit1v2hi_parts"
3422 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3423 (unspec:V2PDI [(vec_concat:V2HI
3425 (match_operand:V2HI 1 "register_operand" "d")
3426 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3429 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3431 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3432 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3433 (vec_select:HI (match_dup 2)
3434 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3435 (match_operand 7 "const_int_operand" "n")]
3436 UNSPEC_MAC_WITH_FLAG))]
3439 const char *templates[] = {
3440 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
3441 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
3442 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
3443 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
3444 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
3445 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
3446 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
3447 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
3448 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
3449 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
3450 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
3451 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
3452 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
3453 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
3454 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
3455 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
3456 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3457 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3458 return templates[alt];
3460 [(set_attr "type" "dsp32")])
3462 ;; A mixture of multiply and multiply-accumulate for when we only want to
3463 ;; initialize one part.
3464 (define_insn "flag_mul_macv2hi_parts_acconly"
3465 [(set (match_operand:PDI 0 "register_operand" "=B,e,e")
3466 (unspec:PDI [(vec_select:HI
3467 (match_operand:V2HI 2 "register_operand" "d,d,d")
3468 (parallel [(match_operand 4 "const01_operand" "P0P1,P0P1,P0P1")]))
3470 (match_operand:V2HI 3 "register_operand" "d,d,d")
3471 (parallel [(match_operand 6 "const01_operand" "P0P1,P0P1,P0P1")]))
3472 (match_operand 10 "const_int_operand" "PB,PA,PA")]
3473 UNSPEC_MUL_WITH_FLAG))
3474 (set (match_operand:PDI 1 "register_operand" "=B,e,e")
3475 (unspec:PDI [(vec_select:HI
3477 (parallel [(match_operand 5 "const01_operand" "P0P1,P0P1,P0P1")]))
3480 (parallel [(match_operand 7 "const01_operand" "P0P1,P0P1,P0P1")]))
3481 (match_operand:PDI 8 "register_operand" "1,1,1")
3482 (match_operand 9 "const01_operand" "P0P1,P0P1,P0P1")
3483 (match_operand 11 "const_int_operand" "PA,PB,PA")]
3484 UNSPEC_MAC_WITH_FLAG))]
3485 "MACFLAGS_MATCH_P (INTVAL (operands[10]), INTVAL (operands[11]))"
3488 const char *templates[] = {
3489 "%0 = %h2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3490 "%0 = %d2 * %h3, %1 %b4 %h2 * %h3 %M5%!",
3491 "%0 = %h2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3492 "%0 = %d2 * %h3, %1 %b4 %d2 * %h3 %M5%!",
3493 "%0 = %h2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3494 "%0 = %d2 * %d3, %1 %b4 %h2 * %h3 %M5%!",
3495 "%0 = %h2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3496 "%0 = %d2 * %d3, %1 %b4 %d2 * %h3 %M5%!",
3497 "%0 = %h2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3498 "%0 = %d2 * %h3, %1 %b4 %h2 * %d3 %M5%!",
3499 "%0 = %h2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3500 "%0 = %d2 * %h3, %1 %b4 %d2 * %d3 %M5%!",
3501 "%0 = %h2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3502 "%0 = %d2 * %d3, %1 %b4 %h2 * %d3 %M5%!",
3503 "%0 = %h2 * %d3, %1 %b4 %d2 * %d3 %M5%!",
3504 "%0 = %d2 * %d3, %1 %b4 %d2 * %d3 %M5%!" };
3505 int alt = (INTVAL (operands[4]) + (INTVAL (operands[5]) << 1)
3506 + (INTVAL (operands[6]) << 2) + (INTVAL (operands[7]) << 3));
3507 xops[0] = operands[0];
3508 xops[1] = operands[1];
3509 xops[2] = operands[2];
3510 xops[3] = operands[3];
3511 xops[4] = operands[9];
3512 xops[5] = which_alternative == 0 ? operands[10] : operands[11];
3513 output_asm_insn (templates[alt], xops);
3516 [(set_attr "type" "dsp32")])
3519 (define_code_macro s_or_u [sign_extend zero_extend])
3520 (define_code_attr su_optab [(sign_extend "mul")
3521 (zero_extend "umul")])
3522 (define_code_attr su_modifier [(sign_extend "IS")
3523 (zero_extend "FU")])
3525 (define_insn "<su_optab>hisi_ll"
3526 [(set (match_operand:SI 0 "register_operand" "=d")
3528 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3529 (parallel [(const_int 0)])))
3531 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3532 (parallel [(const_int 0)])))))]
3534 "%0 = %h1 * %h2 (<su_modifier>)%!"
3535 [(set_attr "type" "dsp32")])
3537 (define_insn "<su_optab>hisi_lh"
3538 [(set (match_operand:SI 0 "register_operand" "=d")
3540 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3541 (parallel [(const_int 0)])))
3543 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3544 (parallel [(const_int 1)])))))]
3546 "%0 = %h1 * %d2 (<su_modifier>)%!"
3547 [(set_attr "type" "dsp32")])
3549 (define_insn "<su_optab>hisi_hl"
3550 [(set (match_operand:SI 0 "register_operand" "=d")
3552 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3553 (parallel [(const_int 1)])))
3555 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3556 (parallel [(const_int 0)])))))]
3558 "%0 = %d1 * %h2 (<su_modifier>)%!"
3559 [(set_attr "type" "dsp32")])
3561 (define_insn "<su_optab>hisi_hh"
3562 [(set (match_operand:SI 0 "register_operand" "=d")
3564 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3565 (parallel [(const_int 1)])))
3567 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3568 (parallel [(const_int 1)])))))]
3570 "%0 = %d1 * %d2 (<su_modifier>)%!"
3571 [(set_attr "type" "dsp32")])
3573 ;; Additional variants for signed * unsigned multiply.
3575 (define_insn "usmulhisi_ull"
3576 [(set (match_operand:SI 0 "register_operand" "=W")
3577 (mult:SI (zero_extend:SI
3578 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3579 (parallel [(const_int 0)])))
3581 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3582 (parallel [(const_int 0)])))))]
3584 "%0 = %h2 * %h1 (IS,M)%!"
3585 [(set_attr "type" "dsp32")])
3587 (define_insn "usmulhisi_ulh"
3588 [(set (match_operand:SI 0 "register_operand" "=W")
3589 (mult:SI (zero_extend:SI
3590 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3591 (parallel [(const_int 0)])))
3593 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3594 (parallel [(const_int 1)])))))]
3596 "%0 = %d2 * %h1 (IS,M)%!"
3597 [(set_attr "type" "dsp32")])
3599 (define_insn "usmulhisi_uhl"
3600 [(set (match_operand:SI 0 "register_operand" "=W")
3601 (mult:SI (zero_extend:SI
3602 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
3603 (parallel [(const_int 1)])))
3605 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3606 (parallel [(const_int 0)])))))]
3608 "%0 = %h2 * %d1 (IS,M)%!"
3609 [(set_attr "type" "dsp32")])
3611 (define_insn "usmulhisi_uhh"
3612 [(set (match_operand:SI 0 "register_operand" "=W")
3613 (mult:SI (zero_extend:SI
3614 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3615 (parallel [(const_int 1)])))
3617 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3618 (parallel [(const_int 1)])))))]
3620 "%0 = %d2 * %d1 (IS,M)%!"
3621 [(set_attr "type" "dsp32")])
3623 ;; Parallel versions of these operations. First, normal signed or unsigned
3626 (define_insn "<su_optab>hisi_ll_lh"
3627 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3629 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3630 (parallel [(const_int 0)])))
3632 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3633 (parallel [(const_int 0)])))))
3634 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3636 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3638 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3640 "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
3641 [(set_attr "type" "dsp32")])
3643 (define_insn "<su_optab>hisi_ll_hl"
3644 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3646 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3647 (parallel [(const_int 0)])))
3649 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3650 (parallel [(const_int 0)])))))
3651 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3653 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3655 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3657 "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
3658 [(set_attr "type" "dsp32")])
3660 (define_insn "<su_optab>hisi_ll_hh"
3661 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3663 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3664 (parallel [(const_int 0)])))
3666 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3667 (parallel [(const_int 0)])))))
3668 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3670 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3672 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3674 "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3675 [(set_attr "type" "dsp32")])
3677 (define_insn "<su_optab>hisi_lh_hl"
3678 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3680 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3681 (parallel [(const_int 0)])))
3683 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3684 (parallel [(const_int 1)])))))
3685 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3687 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3689 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3691 "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
3692 [(set_attr "type" "dsp32")])
3694 (define_insn "<su_optab>hisi_lh_hh"
3695 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3697 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3698 (parallel [(const_int 0)])))
3700 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3701 (parallel [(const_int 1)])))))
3702 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3704 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3706 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3708 "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
3709 [(set_attr "type" "dsp32")])
3711 (define_insn "<su_optab>hisi_hl_hh"
3712 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3714 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3715 (parallel [(const_int 1)])))
3717 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3718 (parallel [(const_int 0)])))))
3719 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3721 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3723 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3725 "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
3726 [(set_attr "type" "dsp32")])
3728 ;; Special signed * unsigned variants.
3730 (define_insn "usmulhisi_ll_lul"
3731 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3732 (mult:SI (sign_extend:SI
3733 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3734 (parallel [(const_int 0)])))
3736 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3737 (parallel [(const_int 0)])))))
3738 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3739 (mult:SI (sign_extend:SI
3740 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3742 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3744 "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3745 [(set_attr "type" "dsp32")])
3747 (define_insn "usmulhisi_ll_luh"
3748 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3749 (mult:SI (sign_extend:SI
3750 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3751 (parallel [(const_int 0)])))
3753 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3754 (parallel [(const_int 0)])))))
3755 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3756 (mult:SI (sign_extend:SI
3757 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3759 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3761 "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3762 [(set_attr "type" "dsp32")])
3764 (define_insn "usmulhisi_ll_hul"
3765 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3766 (mult:SI (sign_extend:SI
3767 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3768 (parallel [(const_int 0)])))
3770 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3771 (parallel [(const_int 0)])))))
3772 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3773 (mult:SI (sign_extend:SI
3774 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3776 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3778 "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3779 [(set_attr "type" "dsp32")])
3781 (define_insn "usmulhisi_ll_huh"
3782 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3783 (mult:SI (sign_extend:SI
3784 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3785 (parallel [(const_int 0)])))
3787 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3788 (parallel [(const_int 0)])))))
3789 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3790 (mult:SI (sign_extend:SI
3791 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3793 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3795 "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3796 [(set_attr "type" "dsp32")])
3798 (define_insn "usmulhisi_lh_lul"
3799 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3800 (mult:SI (sign_extend:SI
3801 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3802 (parallel [(const_int 0)])))
3804 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3805 (parallel [(const_int 1)])))))
3806 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3807 (mult:SI (sign_extend:SI
3808 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3810 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3812 "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3813 [(set_attr "type" "dsp32")])
3815 (define_insn "usmulhisi_lh_luh"
3816 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3817 (mult:SI (sign_extend:SI
3818 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3819 (parallel [(const_int 0)])))
3821 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3822 (parallel [(const_int 1)])))))
3823 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3824 (mult:SI (sign_extend:SI
3825 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3827 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3829 "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3830 [(set_attr "type" "dsp32")])
3832 (define_insn "usmulhisi_lh_hul"
3833 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3834 (mult:SI (sign_extend:SI
3835 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3836 (parallel [(const_int 0)])))
3838 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3839 (parallel [(const_int 1)])))))
3840 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3841 (mult:SI (sign_extend:SI
3842 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3844 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3846 "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3847 [(set_attr "type" "dsp32")])
3849 (define_insn "usmulhisi_lh_huh"
3850 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3851 (mult:SI (sign_extend:SI
3852 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3853 (parallel [(const_int 0)])))
3855 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3856 (parallel [(const_int 1)])))))
3857 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3858 (mult:SI (sign_extend:SI
3859 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3861 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3863 "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
3864 [(set_attr "type" "dsp32")])
3866 (define_insn "usmulhisi_hl_lul"
3867 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3868 (mult:SI (sign_extend:SI
3869 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3870 (parallel [(const_int 1)])))
3872 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3873 (parallel [(const_int 0)])))))
3874 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3875 (mult:SI (sign_extend:SI
3876 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3878 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3880 "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
3881 [(set_attr "type" "dsp32")])
3883 (define_insn "usmulhisi_hl_luh"
3884 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3885 (mult:SI (sign_extend:SI
3886 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3887 (parallel [(const_int 1)])))
3889 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3890 (parallel [(const_int 0)])))))
3891 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3892 (mult:SI (sign_extend:SI
3893 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3895 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3897 "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
3898 [(set_attr "type" "dsp32")])
3900 (define_insn "usmulhisi_hl_hul"
3901 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3902 (mult:SI (sign_extend:SI
3903 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3904 (parallel [(const_int 1)])))
3906 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3907 (parallel [(const_int 0)])))))
3908 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3909 (mult:SI (sign_extend:SI
3910 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3912 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3914 "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
3915 [(set_attr "type" "dsp32")])
3917 (define_insn "usmulhisi_hl_huh"
3918 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3919 (mult:SI (sign_extend:SI
3920 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3921 (parallel [(const_int 1)])))
3923 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3924 (parallel [(const_int 0)])))))
3925 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3926 (mult:SI (sign_extend:SI
3927 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3929 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3931 "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
3932 [(set_attr "type" "dsp32")])
3934 (define_insn "usmulhisi_hh_lul"
3935 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3936 (mult:SI (sign_extend:SI
3937 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3938 (parallel [(const_int 1)])))
3940 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3941 (parallel [(const_int 1)])))))
3942 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3943 (mult:SI (sign_extend:SI
3944 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3946 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3948 "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
3949 [(set_attr "type" "dsp32")])
3951 (define_insn "usmulhisi_hh_luh"
3952 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3953 (mult:SI (sign_extend:SI
3954 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3955 (parallel [(const_int 1)])))
3957 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3958 (parallel [(const_int 1)])))))
3959 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3960 (mult:SI (sign_extend:SI
3961 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
3963 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3965 "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
3966 [(set_attr "type" "dsp32")])
3968 (define_insn "usmulhisi_hh_hul"
3969 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3970 (mult:SI (sign_extend:SI
3971 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3972 (parallel [(const_int 1)])))
3974 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3975 (parallel [(const_int 1)])))))
3976 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3977 (mult:SI (sign_extend:SI
3978 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3980 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
3982 "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
3983 [(set_attr "type" "dsp32")])
3985 (define_insn "usmulhisi_hh_huh"
3986 [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
3987 (mult:SI (sign_extend:SI
3988 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
3989 (parallel [(const_int 1)])))
3991 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
3992 (parallel [(const_int 1)])))))
3993 (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
3994 (mult:SI (sign_extend:SI
3995 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3997 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
3999 "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
4000 [(set_attr "type" "dsp32")])
4004 (define_insn "ssnegv2hi2"
4005 [(set (match_operand:V2HI 0 "register_operand" "=d")
4006 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
4009 [(set_attr "type" "dsp32")])
4011 (define_insn "absv2hi2"
4012 [(set (match_operand:V2HI 0 "register_operand" "=d")
4013 (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
4016 [(set_attr "type" "dsp32")])
4020 (define_insn "ssashiftv2hi3"
4021 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
4023 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4024 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
4026 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
4029 %0 = ASHIFT %1 BY %h2 (V, S)%!
4030 %0 = %1 << %2 (V,S)%!
4031 %0 = %1 >>> %N2 (V,S)%!"
4032 [(set_attr "type" "dsp32")])
4034 (define_insn "ssashifthi3"
4035 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4037 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4038 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
4040 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
4043 %0 = ASHIFT %1 BY %h2 (V, S)%!
4044 %0 = %1 << %2 (V,S)%!
4045 %0 = %1 >>> %N2 (V,S)%!"
4046 [(set_attr "type" "dsp32")])
4048 (define_insn "lshiftv2hi3"
4049 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
4051 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4052 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
4054 (ashift:V2HI (match_dup 1) (match_dup 2))))]
4057 %0 = LSHIFT %1 BY %h2 (V)%!
4059 %0 = %1 >> %N2 (V)%!"
4060 [(set_attr "type" "dsp32")])
4062 (define_insn "lshifthi3"
4063 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
4065 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
4066 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
4068 (ashift:HI (match_dup 1) (match_dup 2))))]
4071 %0 = LSHIFT %1 BY %h2 (V)%!
4073 %0 = %1 >> %N2 (V)%!"
4074 [(set_attr "type" "dsp32")])