1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
25 #define OBJECT_FORMAT_ELF
30 /* Print subsidiary information on the compiler version in use. */
31 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
33 /* Run-time compilation parameters selecting different hardware subsets. */
35 extern int target_flags;
37 /* Predefinition in the preprocessor for this target machine */
38 #ifndef TARGET_CPU_CPP_BUILTINS
39 #define TARGET_CPU_CPP_BUILTINS() \
42 builtin_define_std ("bfin"); \
43 builtin_define_std ("BFIN"); \
44 builtin_define ("__ADSPBLACKFIN__"); \
46 builtin_define ("__BFIN_FDPIC__"); \
47 if (TARGET_ID_SHARED_LIBRARY) \
48 builtin_define ("__ID_SHARED_LIB__"); \
53 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
54 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
55 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
56 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
58 #ifndef SUBTARGET_DRIVER_SELF_SPECS
59 # define SUBTARGET_DRIVER_SELF_SPECS
62 #define LINK_GCC_C_SEQUENCE_SPEC \
63 "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \
66 /* A C string constant that tells the GCC driver program options to pass to
67 the assembler. It can also specify how to translate options you give to GNU
68 CC into options for GCC to pass to the assembler. See the file `sun3.h'
69 for an example of this.
71 Do not define this macro if it does not need to do anything.
76 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
77 %{mno-fdpic:-mnopic} %{mfdpic}"
82 %{mfdpic:-melf32bfinfd -z text} \
83 %{static:-dn -Bstatic} \
84 %{shared:-G -Bdynamic} \
85 %{symbolic:-Bsymbolic} \
89 -init __init -fini __fini "
91 /* Generate DSP instructions, like DSP halfword loads */
92 #define TARGET_DSP (1)
94 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
96 /* Maximum number of library ids we permit */
97 #define MAX_LIBRARY_ID 255
99 extern const char *bfin_library_id_string;
101 /* Sometimes certain combinations of command options do not make
102 sense on a particular target machine. You can define a macro
103 `OVERRIDE_OPTIONS' to take account of this. This macro, if
104 defined, is executed once just after all the command options have
107 Don't use this macro to turn on various extra optimizations for
108 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
110 #define OVERRIDE_OPTIONS override_options ()
112 #define FUNCTION_MODE SImode
115 /* store-condition-codes instructions store 0 for false
116 This is the value stored for true. */
117 #define STORE_FLAG_VALUE 1
119 /* Define this if pushing a word on the stack
120 makes the stack pointer a smaller address. */
121 #define STACK_GROWS_DOWNWARD
123 #define STACK_PUSH_CODE PRE_DEC
125 /* Define this to nonzero if the nominal address of the stack frame
126 is at the high-address end of the local variables;
127 that is, each additional local variable allocated
128 goes at a more negative offset in the frame. */
129 #define FRAME_GROWS_DOWNWARD 1
131 /* We define a dummy ARGP register; the parameters start at offset 0 from
133 #define FIRST_PARM_OFFSET(DECL) 0
135 /* Offset within stack frame to start allocating local variables at.
136 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
137 first local allocated. Otherwise, it is the offset to the BEGINNING
138 of the first local allocated. */
139 #define STARTING_FRAME_OFFSET 0
141 /* Register to use for pushing function arguments. */
142 #define STACK_POINTER_REGNUM REG_P6
144 /* Base register for access to local variables of the function. */
145 #define FRAME_POINTER_REGNUM REG_P7
147 /* A dummy register that will be eliminated to either FP or SP. */
148 #define ARG_POINTER_REGNUM REG_ARGP
150 /* `PIC_OFFSET_TABLE_REGNUM'
151 The register number of the register used to address a table of
152 static data addresses in memory. In some cases this register is
153 defined by a processor's "application binary interface" (ABI).
154 When this macro is defined, RTL is generated for this register
155 once, as with the stack pointer and frame pointer registers. If
156 this macro is not defined, it is up to the machine-dependent files
157 to allocate such a register (if necessary). */
158 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
160 #define FDPIC_FPTR_REGNO REG_P1
161 #define FDPIC_REGNO REG_P3
162 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
164 /* A static chain register for nested functions. We need to use a
165 call-clobbered register for this. */
166 #define STATIC_CHAIN_REGNUM REG_P2
168 /* Define this if functions should assume that stack space has been
169 allocated for arguments even when their values are passed in
172 The value of this macro is the size, in bytes, of the area reserved for
173 arguments passed in registers.
175 This space can either be allocated by the caller or be a part of the
176 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
178 #define FIXED_STACK_AREA 12
179 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
181 /* Define this if the above stack space is to be considered part of the
182 * space allocated by the caller. */
183 #define OUTGOING_REG_PARM_STACK_SPACE
185 /* Define this if the maximum size of all the outgoing args is to be
186 accumulated and pushed during the prologue. The amount can be
187 found in the variable current_function_outgoing_args_size. */
188 #define ACCUMULATE_OUTGOING_ARGS 1
190 /* Value should be nonzero if functions must have frame pointers.
191 Zero means the frame pointer need not be set up (and parms
192 may be accessed via the stack pointer) in functions that seem suitable.
193 This is computed in `reload', in reload1.c.
195 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
197 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
199 /* Make strings word-aligned so strcpy from constants will be faster. */
200 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
201 (TREE_CODE (EXP) == STRING_CST \
202 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
204 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
205 #define TRAMPOLINE_TEMPLATE(FILE) \
208 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
209 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
210 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
211 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
212 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
213 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
214 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
215 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
216 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
220 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
221 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
222 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
223 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
224 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
227 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
228 initialize_trampoline (TRAMP, FNADDR, CXT)
230 /* Definitions for register eliminations.
232 This is an array of structures. Each structure initializes one pair
233 of eliminable registers. The "from" register number is given first,
234 followed by "to". Eliminations of the same "from" register are listed
235 in order of preference.
237 There are two registers that can always be eliminated on the i386.
238 The frame pointer and the arg pointer can be replaced by either the
239 hard frame pointer or to the stack pointer, depending upon the
240 circumstances. The hard frame pointer is not used before reload and
241 so it is not eligible for elimination. */
243 #define ELIMINABLE_REGS \
244 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
245 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
246 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
248 /* Given FROM and TO register numbers, say whether this elimination is
249 allowed. Frame pointer elimination is automatically handled.
251 All other eliminations are valid. */
253 #define CAN_ELIMINATE(FROM, TO) \
254 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
256 /* Define the offset between two registers, one to be eliminated, and the other
257 its replacement, at the start of a routine. */
259 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
260 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
262 /* This processor has
263 8 data register for doing arithmetic
264 8 pointer register for doing addressing, including
267 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
268 1 condition code flag register CC
269 5 return address registers RETS/I/X/N/E
270 1 arithmetic status register (ASTAT). */
272 #define FIRST_PSEUDO_REGISTER 50
274 #define D_REGNO_P(X) ((X) <= REG_R7)
275 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
276 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
277 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
278 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
279 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
280 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
281 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
282 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
284 #define REGISTER_NAMES { \
285 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
286 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
287 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
288 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
291 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
293 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
296 #define SHORT_REGISTER_NAMES { \
297 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
298 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
299 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
300 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
302 #define HIGH_REGISTER_NAMES { \
303 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
304 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
305 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
306 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
308 #define DREGS_PAIR_NAMES { \
309 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
311 #define BYTE_REGISTER_NAMES { \
312 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
315 /* 1 for registers that have pervasive standard uses
316 and are not available for the register allocator. */
318 #define FIXED_REGISTERS \
319 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
320 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
321 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
322 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
323 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
324 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
329 /* 1 for registers not available across function calls.
330 These must include the FIXED_REGISTERS and also any
331 registers that can be used without being saved.
332 The latter must include the registers where values are returned
333 and the register where structure-value addresses are passed.
334 Aside from that, you can include as many other registers as you like. */
336 #define CALL_USED_REGISTERS \
337 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
338 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
339 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
340 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
341 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
342 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
347 /* Order in which to allocate registers. Each register must be
348 listed once, even those in FIXED_REGISTERS. List frame pointer
349 late and fixed registers last. Note that, in general, we prefer
350 registers listed in CALL_USED_REGISTERS, keeping the others
351 available for storage of persistent values. */
353 #define REG_ALLOC_ORDER \
354 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
355 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
357 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
358 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
359 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
360 REG_ASTAT, REG_SEQSTAT, REG_USP, \
362 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
365 /* Macro to conditionally modify fixed_regs/call_used_regs. */
366 #define CONDITIONAL_REGISTER_USAGE \
368 conditional_register_usage(); \
370 call_used_regs[FDPIC_REGNO] = 1; \
371 if (!TARGET_FDPIC && flag_pic) \
373 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
374 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
378 /* Define the classes of registers for register constraints in the
379 machine description. Also define ranges of constants.
381 One of the classes must always be named ALL_REGS and include all hard regs.
382 If there is more than one class, another class must be named NO_REGS
383 and contain no registers.
385 The name GENERAL_REGS must be the name of a class (or an alias for
386 another name such as ALL_REGS). This is the class of registers
387 that is allowed by "g" or "r" in a register constraint.
388 Also, registers outside this class are allocated only when
389 instructions express preferences for them.
391 The classes must be numbered in nondecreasing order; that is,
392 a larger-numbered class must never be contained completely
393 in a smaller-numbered class.
395 For any two classes, it is very desirable that there be another
396 class that represents their union. */
406 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
427 ALL_REGS, LIM_REG_CLASSES
430 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
432 #define GENERAL_REGS DPREGS
434 /* Give names of register classes as strings for dump file. */
436 #define REG_CLASS_NAMES \
465 /* An initializer containing the contents of the register classes, as integers
466 which are bit masks. The Nth integer specifies the contents of class N.
467 The way the integer MASK is interpreted is that register R is in the class
468 if `MASK & (1 << R)' is 1.
470 When the machine has more than 32 registers, an integer does not suffice.
471 Then the integers are replaced by sub-initializers, braced groupings
472 containing several integers. Each sub-initializer must be suitable as an
473 initializer for the type `HARD_REG_SET' which is defined in
476 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
477 MOST_REGS as the union of DPREGS and DAGREGS. */
479 #define REG_CLASS_CONTENTS \
481 { { 0x00000000, 0 }, /* NO_REGS */ \
482 { 0x000f0000, 0 }, /* IREGS */ \
483 { 0x00f00000, 0 }, /* BREGS */ \
484 { 0x0f000000, 0 }, /* LREGS */ \
485 { 0xf0000000, 0 }, /* MREGS */ \
486 { 0x0fff0000, 0 }, /* CIRCREGS */ \
487 { 0xffff0000, 0 }, /* DAGREGS */ \
488 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
489 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
490 { 0x00000000, 0x3 }, /* AREGS */ \
491 { 0x00000000, 0x4 }, /* CCREGS */ \
492 { 0x00000055, 0 }, /* EVEN_DREGS */ \
493 { 0x000000aa, 0 }, /* ODD_DREGS */ \
494 { 0x000000ff, 0 }, /* DREGS */ \
495 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
496 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
497 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
498 { 0x0000ff00, 0x800 }, /* PREGS */ \
499 { 0x000fff00, 0x800 }, /* IPREGS */ \
500 { 0x0000ffff, 0x800 }, /* DPREGS */ \
501 { 0xffffffff, 0x800 }, /* MOST_REGS */\
502 { 0x00000000, 0x3000 }, /* LT_REGS */\
503 { 0x00000000, 0xc000 }, /* LC_REGS */\
504 { 0x00000000, 0x30000 }, /* LB_REGS */\
505 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
506 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
507 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
509 #define IREG_POSSIBLE_P(OUTER) \
510 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
511 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
512 || (OUTER) == MEM || (OUTER) == ADDRESS)
514 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
515 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
517 #define INDEX_REG_CLASS PREGS
519 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
520 (P_REGNO_P (X) || (X) == REG_ARGP \
521 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
524 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
525 ((X) >= FIRST_PSEUDO_REGISTER \
526 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
529 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
530 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
532 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
533 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
536 #define REGNO_OK_FOR_INDEX_P(X) 0
538 /* Get reg_class from a letter such as appears in the machine description. */
540 #define REG_CLASS_FROM_LETTER(LETTER) \
541 ((LETTER) == 'a' ? PREGS : \
542 (LETTER) == 'Z' ? FDPIC_REGS : \
543 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
544 (LETTER) == 'd' ? DREGS : \
545 (LETTER) == 'z' ? PREGS_CLOBBERED : \
546 (LETTER) == 'D' ? EVEN_DREGS : \
547 (LETTER) == 'W' ? ODD_DREGS : \
548 (LETTER) == 'e' ? AREGS : \
549 (LETTER) == 'A' ? EVEN_AREGS : \
550 (LETTER) == 'B' ? ODD_AREGS : \
551 (LETTER) == 'b' ? IREGS : \
552 (LETTER) == 'v' ? BREGS : \
553 (LETTER) == 'f' ? MREGS : \
554 (LETTER) == 'c' ? CIRCREGS : \
555 (LETTER) == 'C' ? CCREGS : \
556 (LETTER) == 't' ? LT_REGS : \
557 (LETTER) == 'k' ? LC_REGS : \
558 (LETTER) == 'u' ? LB_REGS : \
559 (LETTER) == 'x' ? MOST_REGS : \
560 (LETTER) == 'y' ? PROLOGUE_REGS : \
561 (LETTER) == 'w' ? NON_A_CC_REGS : \
564 /* The same information, inverted:
565 Return the class number of the smallest class containing
566 reg number REGNO. This could be a conditional expression
567 or could index an array. */
569 #define REGNO_REG_CLASS(REGNO) \
570 ((REGNO) < REG_P0 ? DREGS \
571 : (REGNO) < REG_I0 ? PREGS \
572 : (REGNO) == REG_ARGP ? PREGS \
573 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
574 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
575 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
576 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
577 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
578 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
579 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
580 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
581 : (REGNO) == REG_CC ? CCREGS \
582 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
585 /* When defined, the compiler allows registers explicitly used in the
586 rtl to be used as spill registers but prevents the compiler from
587 extending the lifetime of these registers. */
588 #define SMALL_REGISTER_CLASSES 1
590 #define CLASS_LIKELY_SPILLED_P(CLASS) \
591 ((CLASS) == PREGS_CLOBBERED \
592 || (CLASS) == PROLOGUE_REGS \
593 || (CLASS) == CCREGS)
595 /* Do not allow to store a value in REG_CC for any mode */
596 /* Do not allow to store value in pregs if mode is not SI*/
597 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
599 /* Return the maximum number of consecutive registers
600 needed to represent mode MODE in a register of class CLASS. */
601 #define CLASS_MAX_NREGS(CLASS, MODE) \
602 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
603 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
605 #define HARD_REGNO_NREGS(REGNO, MODE) \
606 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
607 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
608 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
610 /* A C expression that is nonzero if hard register TO can be
611 considered for use as a rename register for FROM register */
612 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
614 /* A C expression that is nonzero if it is desirable to choose
615 register allocation so as to avoid move instructions between a
616 value of mode MODE1 and a value of mode MODE2.
618 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
619 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
620 MODE2)' must be zero. */
621 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
623 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
624 A C expression that places additional restrictions on the register
625 class to use when it is necessary to copy value X into a register
626 in class CLASS. The value is a register class; perhaps CLASS, or
627 perhaps another, smaller class. */
628 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
630 /* Function Calling Conventions. */
632 /* The type of the current function; normal functions are of type
635 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
638 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
640 /* Flags for the call/call_value rtl operations set up by function_arg */
641 #define CALL_NORMAL 0x00000000 /* no special processing */
642 #define CALL_LONG 0x00000001 /* always call indirect */
643 #define CALL_SHORT 0x00000002 /* always call by symbol */
646 int words; /* # words passed so far */
647 int nregs; /* # registers available for passing */
648 int *arg_regs; /* array of register -1 terminated */
649 int call_cookie; /* Do special things for this call */
652 /* Define where to put the arguments to a function.
653 Value is zero to push the argument on the stack,
654 or a hard register in which to store the argument.
656 MODE is the argument's machine mode.
657 TYPE is the data type of the argument (as a tree).
658 This is null for libcalls where that information may
660 CUM is a variable of type CUMULATIVE_ARGS which gives info about
661 the preceding args and about the function being called.
662 NAMED is nonzero if this argument is a named parameter
663 (otherwise it is an extra parameter matching an ellipsis). */
665 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
666 (function_arg (&CUM, MODE, TYPE, NAMED))
668 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
671 /* Initialize a variable CUM of type CUMULATIVE_ARGS
672 for a call to a function whose data type is FNTYPE.
673 For a library call, FNTYPE is 0. */
674 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
675 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
677 /* Update the data in CUM to advance over an argument
678 of mode MODE and data type TYPE.
679 (TYPE is null for libcalls where that information may not be available.) */
680 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
681 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
683 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
685 /* Define how to find the value returned by a function.
686 VALTYPE is the data type of the value (as a tree).
687 If the precise function being called is known, FUNC is its FUNCTION_DECL;
688 otherwise, FUNC is 0.
691 #define VALUE_REGNO(MODE) (REG_R0)
693 #define FUNCTION_VALUE(VALTYPE, FUNC) \
694 gen_rtx_REG (TYPE_MODE (VALTYPE), \
695 VALUE_REGNO(TYPE_MODE(VALTYPE)))
697 /* Define how to find the value returned by a library function
698 assuming the value has mode MODE. */
700 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
702 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
704 #define DEFAULT_PCC_STRUCT_RETURN 0
705 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
707 /* Before the prologue, the return address is in the RETS register. */
708 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
710 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
712 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
714 /* Call instructions don't modify the stack pointer on the Blackfin. */
715 #define INCOMING_FRAME_SP_OFFSET 0
717 /* Describe how we implement __builtin_eh_return. */
718 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
719 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
720 #define EH_RETURN_HANDLER_RTX \
721 gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
723 /* Addressing Modes */
725 /* Recognize any constant value that is a valid address. */
726 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
728 /* Nonzero if the constant value X is a legitimate general operand.
729 symbol_ref are not legitimate and will be put into constant pool.
730 See force_const_mem().
731 If -mno-pool, all constants are legitimate.
733 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
735 /* A number, the maximum number of registers that can appear in a
736 valid memory address. Note that it is up to you to specify a
737 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
738 would ever accept. */
739 #define MAX_REGS_PER_ADDRESS 1
741 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
742 that is a valid memory address for an instruction.
743 The MODE argument is the machine mode for the MEM expression
744 that wants to use this address.
746 Blackfin addressing modes are as follows:
752 W [ Preg + uimm16m2 ]
760 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
761 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
764 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
766 if (bfin_legitimate_address_p (MODE, X, 1)) \
770 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
772 if (bfin_legitimate_address_p (MODE, X, 0)) \
777 /* Try machine-dependent ways of modifying an illegitimate address
778 to be legitimate. If we find one, return the new, valid address.
779 This macro is used in only one place: `memory_address' in explow.c.
781 OLDX is the address as it was before break_out_memory_refs was called.
782 In some cases it is useful to look at this to decide what needs to be done.
784 MODE and WIN are passed so that this macro can use
785 GO_IF_LEGITIMATE_ADDRESS.
787 It is always safe for this macro to do nothing. It exists to recognize
788 opportunities to optimize the output.
790 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
792 rtx _q = legitimize_address(X, OLDX, MODE); \
793 if (_q) { X = _q; goto WIN; } \
796 #define HAVE_POST_INCREMENT 1
797 #define HAVE_POST_DECREMENT 1
798 #define HAVE_PRE_DECREMENT 1
800 /* `LEGITIMATE_PIC_OPERAND_P (X)'
801 A C expression that is nonzero if X is a legitimate immediate
802 operand on the target machine when generating position independent
803 code. You can assume that X satisfies `CONSTANT_P', so you need
804 not check this. You can also assume FLAG_PIC is true, so you need
805 not check it either. You need not define this macro if all
806 constants (including `SYMBOL_REF') can be immediate operands when
807 generating position independent code. */
808 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
810 #define SYMBOLIC_CONST(X) \
811 (GET_CODE (X) == SYMBOL_REF \
812 || GET_CODE (X) == LABEL_REF \
813 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
816 A C statement or compound statement with a conditional `goto
817 LABEL;' executed if memory address X (an RTX) can have different
818 meanings depending on the machine mode of the memory reference it
819 is used for or if the address is valid for some modes but not
822 Autoincrement and autodecrement addresses typically have
823 mode-dependent effects because the amount of the increment or
824 decrement is the size of the operand being addressed. Some
825 machines have other mode-dependent addresses. Many RISC machines
826 have no mode-dependent addresses.
828 You may assume that ADDR is a valid address for the machine.
830 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
832 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
834 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
835 is done just by pretending it is already truncated. */
836 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
838 /* Max number of bytes we can move from memory to memory
839 in one reasonably fast instruction. */
840 #define MOVE_MAX UNITS_PER_WORD
843 /* STORAGE LAYOUT: target machine storage layout
844 Define this macro as a C expression which is nonzero if accessing
845 less than a word of memory (i.e. a `char' or a `short') is no
846 faster than accessing a word of memory, i.e., if such access
847 require more than one instruction or if there is no difference in
848 cost between byte and (aligned) word loads.
850 When this macro is not defined, the compiler will access a field by
851 finding the smallest containing object; when it is defined, a
852 fullword load will be used if alignment permits. Unless bytes
853 accesses are faster than word accesses, using word accesses is
854 preferable since it may eliminate subsequent memory access if
855 subsequent accesses occur to other fields in the same word of the
856 structure, but to different bytes. */
857 #define SLOW_BYTE_ACCESS 0
858 #define SLOW_SHORT_ACCESS 0
860 /* Define this if most significant bit is lowest numbered
861 in instructions that operate on numbered bit-fields. */
862 #define BITS_BIG_ENDIAN 0
864 /* Define this if most significant byte of a word is the lowest numbered.
865 We can't access bytes but if we could we would in the Big Endian order. */
866 #define BYTES_BIG_ENDIAN 0
868 /* Define this if most significant word of a multiword number is numbered. */
869 #define WORDS_BIG_ENDIAN 0
871 /* number of bits in an addressable storage unit */
872 #define BITS_PER_UNIT 8
874 /* Width in bits of a "word", which is the contents of a machine register.
875 Note that this is not necessarily the width of data type `int';
876 if using 16-bit ints on a 68000, this would still be 32.
877 But on a machine with 16-bit registers, this would be 16. */
878 #define BITS_PER_WORD 32
880 /* Width of a word, in units (bytes). */
881 #define UNITS_PER_WORD 4
883 /* Width in bits of a pointer.
884 See also the macro `Pmode1' defined below. */
885 #define POINTER_SIZE 32
887 /* Allocation boundary (in *bits*) for storing pointers in memory. */
888 #define POINTER_BOUNDARY 32
890 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
891 #define PARM_BOUNDARY 32
893 /* Boundary (in *bits*) on which stack pointer should be aligned. */
894 #define STACK_BOUNDARY 32
896 /* Allocation boundary (in *bits*) for the code of a function. */
897 #define FUNCTION_BOUNDARY 32
899 /* Alignment of field after `int : 0' in a structure. */
900 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
902 /* No data type wants to be aligned rounder than this. */
903 #define BIGGEST_ALIGNMENT 32
905 /* Define this if move instructions will actually fail to work
906 when given unaligned data. */
907 #define STRICT_ALIGNMENT 1
909 /* (shell-command "rm c-decl.o stor-layout.o")
910 * never define PCC_BITFIELD_TYPE_MATTERS
911 * really cause some alignment problem
914 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
917 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
921 /* what is the 'type' of size_t */
922 #define SIZE_TYPE "long unsigned int"
924 /* Define this as 1 if `char' should by default be signed; else as 0. */
925 #define DEFAULT_SIGNED_CHAR 1
926 #define FLOAT_TYPE_SIZE BITS_PER_WORD
927 #define SHORT_TYPE_SIZE 16
928 #define CHAR_TYPE_SIZE 8
929 #define INT_TYPE_SIZE 32
930 #define LONG_TYPE_SIZE 32
931 #define LONG_LONG_TYPE_SIZE 64
933 /* Note: Fix this to depend on target switch. -- lev */
935 /* Note: Try to implement double and force long double. -- tonyko
936 * #define __DOUBLES_ARE_FLOATS__
937 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
938 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
939 * #define DOUBLES_ARE_FLOATS 1
942 #define DOUBLE_TYPE_SIZE 64
943 #define LONG_DOUBLE_TYPE_SIZE 64
945 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
946 A macro to update M and UNSIGNEDP when an object whose type is
947 TYPE and which has the specified mode and signedness is to be
948 stored in a register. This macro is only called when TYPE is a
951 On most RISC machines, which only have operations that operate on
952 a full register, define this macro to set M to `word_mode' if M is
953 an integer mode narrower than `BITS_PER_WORD'. In most cases,
954 only integer modes should be widened because wider-precision
955 floating-point operations are usually more expensive than their
956 narrower counterparts.
958 For most machines, the macro definition does not change UNSIGNEDP.
959 However, some machines, have instructions that preferentially
960 handle either signed or unsigned quantities of certain modes. For
961 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
962 instructions sign-extend the result to 64 bits. On such machines,
963 set UNSIGNEDP according to which kind of extension is more
966 Do not define this macro if it would never modify M.*/
968 #define BFIN_PROMOTE_MODE_P(MODE) \
969 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
970 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
972 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
973 if (BFIN_PROMOTE_MODE_P(MODE)) \
975 if (MODE == QImode) \
977 else if (MODE == HImode) \
982 /* Describing Relative Costs of Operations */
984 /* Do not put function addr into constant pool */
985 #define NO_FUNCTION_CSE 1
987 /* A C expression for the cost of moving data from a register in class FROM to
988 one in class TO. The classes are expressed using the enumeration values
989 such as `GENERAL_REGS'. A value of 2 is the default; other values are
990 interpreted relative to that.
992 It is not required that the cost always equal 2 when FROM is the same as TO;
993 on some machines it is expensive to move between registers if they are not
994 general registers. */
996 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
997 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
999 /* A C expression for the cost of moving data of mode M between a
1000 register and memory. A value of 2 is the default; this cost is
1001 relative to those in `REGISTER_MOVE_COST'.
1003 If moving between registers and memory is more expensive than
1004 between two registers, you should define this macro to express the
1007 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1008 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1010 /* Specify the machine mode that this machine uses
1011 for the index in the tablejump instruction. */
1012 #define CASE_VECTOR_MODE SImode
1014 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1016 /* Define if operations between registers always perform the operation
1017 on the full register even if a narrower mode is specified.
1018 #define WORD_REGISTER_OPERATIONS
1021 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
1022 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
1023 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
1024 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
1025 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
1026 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
1027 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
1028 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
1029 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
1030 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
1032 #define CONSTRAINT_LEN(C, STR) \
1033 ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
1035 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1037 #define CONST_OK_FOR_P(VALUE, STR) \
1038 ((STR)[1] == '0' ? (VALUE) == 0 \
1039 : (STR)[1] == '1' ? (VALUE) == 1 \
1040 : (STR)[1] == '2' ? (VALUE) == 2 \
1041 : (STR)[1] == '3' ? (VALUE) == 3 \
1042 : (STR)[1] == '4' ? (VALUE) == 4 \
1045 #define CONST_OK_FOR_K(VALUE, STR) \
1047 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
1048 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
1049 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
1050 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
1053 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
1054 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
1055 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
1056 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
1059 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
1062 ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \
1066 #define CONST_OK_FOR_M(VALUE, STR) \
1067 ((STR)[1] == '1' ? (VALUE) == 255 \
1068 : (STR)[1] == '2' ? (VALUE) == 65535 \
1071 /* The letters I, J, K, L and M in a register constraint string
1072 can be used to stand for particular ranges of immediate operands.
1073 This macro defines what the ranges are.
1074 C is the letter, and VALUE is a constant value.
1075 Return 1 if VALUE is in the range specified by C.
1077 bfin constant operands are as follows
1079 J 2**N 5bit imm scaled
1080 Ks7 -64 .. 63 signed 7bit imm
1081 Ku5 0..31 unsigned 5bit imm
1082 Ks4 -8 .. 7 signed 4bit imm
1083 Ks3 -4 .. 3 signed 3bit imm
1084 Ku3 0 .. 7 unsigned 3bit imm
1085 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
1087 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1088 ((C) == 'J' ? (log2constp (VALUE)) \
1089 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
1090 : (C) == 'L' ? log2constp (~(VALUE)) \
1091 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
1092 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
1095 /*Constant Output Formats */
1096 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1097 ((C) == 'H' ? 1 : 0)
1099 #define EXTRA_CONSTRAINT(VALUE, D) \
1100 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1102 /* Switch into a generic section. */
1103 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1105 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1106 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1108 typedef enum sections {
1114 typedef enum directives {
1123 #define TEXT_SECTION_ASM_OP ".text;"
1124 #define DATA_SECTION_ASM_OP ".data;"
1126 #define ASM_APP_ON ""
1127 #define ASM_APP_OFF ""
1129 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1130 do { fputs (".global ", FILE); \
1131 assemble_name (FILE, NAME); \
1133 fputc ('\n',FILE); \
1136 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1138 fputs (".type ", FILE); \
1139 assemble_name (FILE, NAME); \
1140 fputs (", STT_FUNC", FILE); \
1142 fputc ('\n',FILE); \
1143 ASM_OUTPUT_LABEL(FILE, NAME); \
1146 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1147 do { assemble_name (FILE, NAME); \
1148 fputs (":\n",FILE); \
1151 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1152 do { fprintf (FILE, "_%s", NAME); \
1155 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1156 do { char __buf[256]; \
1157 fprintf (FILE, "\t.dd\t"); \
1158 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1159 assemble_name (FILE, __buf); \
1160 fputc (';', FILE); \
1161 fputc ('\n', FILE); \
1164 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1165 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1167 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1170 fprintf (FILE, "\t.dd\t"); \
1171 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1172 assemble_name (FILE, __buf); \
1173 fputs (" - ", FILE); \
1174 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1175 assemble_name (FILE, __buf); \
1176 fputc (';', FILE); \
1177 fputc ('\n', FILE); \
1180 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1183 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1186 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1188 asm_output_skip (FILE, SIZE); \
1191 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1193 switch_to_section (data_section); \
1194 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1195 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1196 ASM_OUTPUT_LABEL (FILE, NAME); \
1197 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1198 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1201 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1203 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1204 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1206 #define ASM_COMMENT_START "//"
1208 #define FUNCTION_PROFILER(FILE, LABELNO) \
1210 fprintf (FILE, "\tCALL __mcount;\n"); \
1213 #undef NO_PROFILE_COUNTERS
1214 #define NO_PROFILE_COUNTERS 1
1216 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1217 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1219 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1220 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1222 /* This works for GAS and some other assemblers. */
1223 #define SET_ASM_OP ".set "
1225 /* DBX register number for a given compiler register number */
1226 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1228 #define SIZE_ASM_OP "\t.size\t"
1230 extern int splitting_for_sched;
1232 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1234 #endif /* _BFIN_CONFIG */