1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
29 /* Print subsidiary information on the compiler version in use. */
30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32 /* Run-time compilation parameters selecting different hardware subsets. */
34 extern int target_flags;
36 /* Predefinition in the preprocessor for this target machine */
37 #ifndef TARGET_CPU_CPP_BUILTINS
38 #define TARGET_CPU_CPP_BUILTINS() \
41 builtin_define_std ("bfin"); \
42 builtin_define_std ("BFIN"); \
43 builtin_define ("__ADSPBLACKFIN__"); \
44 builtin_define ("__ADSPLPBLACKFIN__"); \
46 switch (bfin_cpu_type) \
48 case BFIN_CPU_BF512: \
49 builtin_define ("__ADSPBF512__"); \
50 builtin_define ("__ADSPBF51x__"); \
52 case BFIN_CPU_BF514: \
53 builtin_define ("__ADSPBF514__"); \
54 builtin_define ("__ADSPBF51x__"); \
56 case BFIN_CPU_BF516: \
57 builtin_define ("__ADSPBF516__"); \
58 builtin_define ("__ADSPBF51x__"); \
60 case BFIN_CPU_BF518: \
61 builtin_define ("__ADSPBF518__"); \
62 builtin_define ("__ADSPBF51x__"); \
64 case BFIN_CPU_BF522: \
65 builtin_define ("__ADSPBF522__"); \
66 builtin_define ("__ADSPBF52x__"); \
68 case BFIN_CPU_BF523: \
69 builtin_define ("__ADSPBF523__"); \
70 builtin_define ("__ADSPBF52x__"); \
72 case BFIN_CPU_BF524: \
73 builtin_define ("__ADSPBF524__"); \
74 builtin_define ("__ADSPBF52x__"); \
76 case BFIN_CPU_BF525: \
77 builtin_define ("__ADSPBF525__"); \
78 builtin_define ("__ADSPBF52x__"); \
80 case BFIN_CPU_BF526: \
81 builtin_define ("__ADSPBF526__"); \
82 builtin_define ("__ADSPBF52x__"); \
84 case BFIN_CPU_BF527: \
85 builtin_define ("__ADSPBF527__"); \
86 builtin_define ("__ADSPBF52x__"); \
88 case BFIN_CPU_BF531: \
89 builtin_define ("__ADSPBF531__"); \
91 case BFIN_CPU_BF532: \
92 builtin_define ("__ADSPBF532__"); \
94 case BFIN_CPU_BF533: \
95 builtin_define ("__ADSPBF533__"); \
97 case BFIN_CPU_BF534: \
98 builtin_define ("__ADSPBF534__"); \
100 case BFIN_CPU_BF536: \
101 builtin_define ("__ADSPBF536__"); \
103 case BFIN_CPU_BF537: \
104 builtin_define ("__ADSPBF537__"); \
106 case BFIN_CPU_BF538: \
107 builtin_define ("__ADSPBF538__"); \
109 case BFIN_CPU_BF539: \
110 builtin_define ("__ADSPBF539__"); \
112 case BFIN_CPU_BF542: \
113 builtin_define ("__ADSPBF542__"); \
114 builtin_define ("__ADSPBF54x__"); \
116 case BFIN_CPU_BF544: \
117 builtin_define ("__ADSPBF544__"); \
118 builtin_define ("__ADSPBF54x__"); \
120 case BFIN_CPU_BF548: \
121 builtin_define ("__ADSPBF548__"); \
122 builtin_define ("__ADSPBF54x__"); \
124 case BFIN_CPU_BF547: \
125 builtin_define ("__ADSPBF547__"); \
126 builtin_define ("__ADSPBF54x__"); \
128 case BFIN_CPU_BF549: \
129 builtin_define ("__ADSPBF549__"); \
130 builtin_define ("__ADSPBF54x__"); \
132 case BFIN_CPU_BF561: \
133 builtin_define ("__ADSPBF561__"); \
137 if (bfin_si_revision != -1) \
139 /* space of 0xnnnn and a NUL */ \
140 char *buf = XALLOCAVEC (char, 7); \
142 sprintf (buf, "0x%04x", bfin_si_revision); \
143 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
146 if (bfin_workarounds) \
147 builtin_define ("__WORKAROUNDS_ENABLED"); \
148 if (ENABLE_WA_SPECULATIVE_LOADS) \
149 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
150 if (ENABLE_WA_SPECULATIVE_SYNCS) \
151 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
152 if (ENABLE_WA_INDIRECT_CALLS) \
153 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
154 if (ENABLE_WA_RETS) \
155 builtin_define ("__WORKAROUND_RETS"); \
159 builtin_define ("__BFIN_FDPIC__"); \
160 builtin_define ("__FDPIC__"); \
162 if (TARGET_ID_SHARED_LIBRARY \
163 && !TARGET_SEP_DATA) \
164 builtin_define ("__ID_SHARED_LIB__"); \
165 if (flag_no_builtin) \
166 builtin_define ("__NO_BUILTIN"); \
167 if (TARGET_MULTICORE) \
168 builtin_define ("__BFIN_MULTICORE"); \
170 builtin_define ("__BFIN_COREA"); \
172 builtin_define ("__BFIN_COREB"); \
174 builtin_define ("__BFIN_SDRAM"); \
179 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
180 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
181 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
182 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
184 #ifndef SUBTARGET_DRIVER_SELF_SPECS
185 # define SUBTARGET_DRIVER_SELF_SPECS
188 #define LINK_GCC_C_SEQUENCE_SPEC "\
189 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
192 /* A C string constant that tells the GCC driver program options to pass to
193 the assembler. It can also specify how to translate options you give to GNU
194 CC into options for GCC to pass to the assembler. See the file `sun3.h'
195 for an example of this.
197 Do not define this macro if it does not need to do anything.
199 Defined in svr4.h. */
202 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
203 %{mno-fdpic:-mnopic} %{mfdpic}"
208 %{mfdpic:-melf32bfinfd -z text} \
209 %{static:-dn -Bstatic} \
210 %{shared:-G -Bdynamic} \
211 %{symbolic:-Bsymbolic} \
215 -init __init -fini __fini "
217 /* Generate DSP instructions, like DSP halfword loads */
218 #define TARGET_DSP (1)
220 #define TARGET_DEFAULT 0
222 /* Maximum number of library ids we permit */
223 #define MAX_LIBRARY_ID 255
225 extern const char *bfin_library_id_string;
227 /* Sometimes certain combinations of command options do not make
228 sense on a particular target machine. You can define a macro
229 `OVERRIDE_OPTIONS' to take account of this. This macro, if
230 defined, is executed once just after all the command options have
233 Don't use this macro to turn on various extra optimizations for
234 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
236 #define OVERRIDE_OPTIONS override_options ()
238 #define FUNCTION_MODE SImode
241 /* store-condition-codes instructions store 0 for false
242 This is the value stored for true. */
243 #define STORE_FLAG_VALUE 1
245 /* Define this if pushing a word on the stack
246 makes the stack pointer a smaller address. */
247 #define STACK_GROWS_DOWNWARD
249 #define STACK_PUSH_CODE PRE_DEC
251 /* Define this to nonzero if the nominal address of the stack frame
252 is at the high-address end of the local variables;
253 that is, each additional local variable allocated
254 goes at a more negative offset in the frame. */
255 #define FRAME_GROWS_DOWNWARD 1
257 /* We define a dummy ARGP register; the parameters start at offset 0 from
259 #define FIRST_PARM_OFFSET(DECL) 0
261 /* Offset within stack frame to start allocating local variables at.
262 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
263 first local allocated. Otherwise, it is the offset to the BEGINNING
264 of the first local allocated. */
265 #define STARTING_FRAME_OFFSET 0
267 /* Register to use for pushing function arguments. */
268 #define STACK_POINTER_REGNUM REG_P6
270 /* Base register for access to local variables of the function. */
271 #define FRAME_POINTER_REGNUM REG_P7
273 /* A dummy register that will be eliminated to either FP or SP. */
274 #define ARG_POINTER_REGNUM REG_ARGP
276 /* `PIC_OFFSET_TABLE_REGNUM'
277 The register number of the register used to address a table of
278 static data addresses in memory. In some cases this register is
279 defined by a processor's "application binary interface" (ABI).
280 When this macro is defined, RTL is generated for this register
281 once, as with the stack pointer and frame pointer registers. If
282 this macro is not defined, it is up to the machine-dependent files
283 to allocate such a register (if necessary). */
284 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
286 #define FDPIC_FPTR_REGNO REG_P1
287 #define FDPIC_REGNO REG_P3
288 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
290 /* A static chain register for nested functions. We need to use a
291 call-clobbered register for this. */
292 #define STATIC_CHAIN_REGNUM REG_P2
294 /* Define this if functions should assume that stack space has been
295 allocated for arguments even when their values are passed in
298 The value of this macro is the size, in bytes, of the area reserved for
299 arguments passed in registers.
301 This space can either be allocated by the caller or be a part of the
302 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
304 #define FIXED_STACK_AREA 12
305 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
307 /* Define this if the above stack space is to be considered part of the
308 * space allocated by the caller. */
309 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
311 /* Define this if the maximum size of all the outgoing args is to be
312 accumulated and pushed during the prologue. The amount can be
313 found in the variable crtl->outgoing_args_size. */
314 #define ACCUMULATE_OUTGOING_ARGS 1
316 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
318 /* If defined, a C expression to compute the alignment for a local
319 variable. TYPE is the data type, and ALIGN is the alignment that
320 the object would ordinarily have. The value of this macro is used
321 instead of that alignment to align the object.
323 If this macro is not defined, then ALIGN is used.
325 One use of this macro is to increase alignment of medium-size
326 data to make it all fit in fewer cache lines. */
328 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
330 /* Make strings word-aligned so strcpy from constants will be faster. */
331 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
332 (TREE_CODE (EXP) == STRING_CST \
333 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
335 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
336 #define TRAMPOLINE_TEMPLATE(FILE) \
339 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
340 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
341 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
342 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
343 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
344 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
345 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
346 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
347 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
351 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
352 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
353 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
354 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
355 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
358 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
359 initialize_trampoline (TRAMP, FNADDR, CXT)
361 /* Definitions for register eliminations.
363 This is an array of structures. Each structure initializes one pair
364 of eliminable registers. The "from" register number is given first,
365 followed by "to". Eliminations of the same "from" register are listed
366 in order of preference.
368 There are two registers that can always be eliminated on the i386.
369 The frame pointer and the arg pointer can be replaced by either the
370 hard frame pointer or to the stack pointer, depending upon the
371 circumstances. The hard frame pointer is not used before reload and
372 so it is not eligible for elimination. */
374 #define ELIMINABLE_REGS \
375 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
376 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
377 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
379 /* Given FROM and TO register numbers, say whether this elimination is
380 allowed. Frame pointer elimination is automatically handled.
382 All other eliminations are valid. */
384 #define CAN_ELIMINATE(FROM, TO) \
385 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
387 /* Define the offset between two registers, one to be eliminated, and the other
388 its replacement, at the start of a routine. */
390 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
391 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
393 /* This processor has
394 8 data register for doing arithmetic
395 8 pointer register for doing addressing, including
398 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
399 1 condition code flag register CC
400 5 return address registers RETS/I/X/N/E
401 1 arithmetic status register (ASTAT). */
403 #define FIRST_PSEUDO_REGISTER 50
405 #define D_REGNO_P(X) ((X) <= REG_R7)
406 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
407 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
408 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
409 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
410 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
411 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
412 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
413 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
415 #define REGISTER_NAMES { \
416 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
417 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
418 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
419 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
422 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
424 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
427 #define SHORT_REGISTER_NAMES { \
428 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
429 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
430 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
431 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
433 #define HIGH_REGISTER_NAMES { \
434 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
435 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
436 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
437 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
439 #define DREGS_PAIR_NAMES { \
440 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
442 #define BYTE_REGISTER_NAMES { \
443 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
446 /* 1 for registers that have pervasive standard uses
447 and are not available for the register allocator. */
449 #define FIXED_REGISTERS \
450 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
451 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
452 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
453 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
454 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
455 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
460 /* 1 for registers not available across function calls.
461 These must include the FIXED_REGISTERS and also any
462 registers that can be used without being saved.
463 The latter must include the registers where values are returned
464 and the register where structure-value addresses are passed.
465 Aside from that, you can include as many other registers as you like. */
467 #define CALL_USED_REGISTERS \
468 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
469 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
470 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
471 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
472 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
478 /* Order in which to allocate registers. Each register must be
479 listed once, even those in FIXED_REGISTERS. List frame pointer
480 late and fixed registers last. Note that, in general, we prefer
481 registers listed in CALL_USED_REGISTERS, keeping the others
482 available for storage of persistent values. */
484 #define REG_ALLOC_ORDER \
485 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
486 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
488 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
489 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
490 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
491 REG_ASTAT, REG_SEQSTAT, REG_USP, \
493 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
496 /* Macro to conditionally modify fixed_regs/call_used_regs. */
497 #define CONDITIONAL_REGISTER_USAGE \
499 conditional_register_usage(); \
501 call_used_regs[FDPIC_REGNO] = 1; \
502 if (!TARGET_FDPIC && flag_pic) \
504 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
505 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
509 /* Define the classes of registers for register constraints in the
510 machine description. Also define ranges of constants.
512 One of the classes must always be named ALL_REGS and include all hard regs.
513 If there is more than one class, another class must be named NO_REGS
514 and contain no registers.
516 The name GENERAL_REGS must be the name of a class (or an alias for
517 another name such as ALL_REGS). This is the class of registers
518 that is allowed by "g" or "r" in a register constraint.
519 Also, registers outside this class are allocated only when
520 instructions express preferences for them.
522 The classes must be numbered in nondecreasing order; that is,
523 a larger-numbered class must never be contained completely
524 in a smaller-numbered class.
526 For any two classes, it is very desirable that there be another
527 class that represents their union. */
537 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
567 ALL_REGS, LIM_REG_CLASSES
570 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
572 #define GENERAL_REGS DPREGS
574 /* Give names of register classes as strings for dump file. */
576 #define REG_CLASS_NAMES \
614 /* An initializer containing the contents of the register classes, as integers
615 which are bit masks. The Nth integer specifies the contents of class N.
616 The way the integer MASK is interpreted is that register R is in the class
617 if `MASK & (1 << R)' is 1.
619 When the machine has more than 32 registers, an integer does not suffice.
620 Then the integers are replaced by sub-initializers, braced groupings
621 containing several integers. Each sub-initializer must be suitable as an
622 initializer for the type `HARD_REG_SET' which is defined in
625 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
626 MOST_REGS as the union of DPREGS and DAGREGS. */
628 #define REG_CLASS_CONTENTS \
630 { { 0x00000000, 0 }, /* NO_REGS */ \
631 { 0x000f0000, 0 }, /* IREGS */ \
632 { 0x00f00000, 0 }, /* BREGS */ \
633 { 0x0f000000, 0 }, /* LREGS */ \
634 { 0xf0000000, 0 }, /* MREGS */ \
635 { 0x0fff0000, 0 }, /* CIRCREGS */ \
636 { 0xffff0000, 0 }, /* DAGREGS */ \
637 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
638 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
639 { 0x00000000, 0x3 }, /* AREGS */ \
640 { 0x00000000, 0x4 }, /* CCREGS */ \
641 { 0x00000055, 0 }, /* EVEN_DREGS */ \
642 { 0x000000aa, 0 }, /* ODD_DREGS */ \
643 { 0x00000001, 0 }, /* D0REGS */ \
644 { 0x00000002, 0 }, /* D1REGS */ \
645 { 0x00000004, 0 }, /* D2REGS */ \
646 { 0x00000008, 0 }, /* D3REGS */ \
647 { 0x00000010, 0 }, /* D4REGS */ \
648 { 0x00000020, 0 }, /* D5REGS */ \
649 { 0x00000040, 0 }, /* D6REGS */ \
650 { 0x00000080, 0 }, /* D7REGS */ \
651 { 0x000000ff, 0 }, /* DREGS */ \
652 { 0x00000100, 0x000 }, /* P0REGS */ \
653 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
654 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
655 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
656 { 0x0000ff00, 0x800 }, /* PREGS */ \
657 { 0x000fff00, 0x800 }, /* IPREGS */ \
658 { 0x0000ffff, 0x800 }, /* DPREGS */ \
659 { 0xffffffff, 0x800 }, /* MOST_REGS */\
660 { 0x00000000, 0x3000 }, /* LT_REGS */\
661 { 0x00000000, 0xc000 }, /* LC_REGS */\
662 { 0x00000000, 0x30000 }, /* LB_REGS */\
663 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
664 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
665 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
667 #define IREG_POSSIBLE_P(OUTER) \
668 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
669 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
670 || (OUTER) == MEM || (OUTER) == ADDRESS)
672 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
673 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
675 #define INDEX_REG_CLASS PREGS
677 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
678 (P_REGNO_P (X) || (X) == REG_ARGP \
679 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
682 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
683 ((X) >= FIRST_PSEUDO_REGISTER \
684 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
687 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
688 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
690 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
691 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
694 #define REGNO_OK_FOR_INDEX_P(X) 0
696 /* The same information, inverted:
697 Return the class number of the smallest class containing
698 reg number REGNO. This could be a conditional expression
699 or could index an array. */
701 #define REGNO_REG_CLASS(REGNO) \
702 ((REGNO) == REG_R0 ? D0REGS \
703 : (REGNO) == REG_R1 ? D1REGS \
704 : (REGNO) == REG_R2 ? D2REGS \
705 : (REGNO) == REG_R3 ? D3REGS \
706 : (REGNO) == REG_R4 ? D4REGS \
707 : (REGNO) == REG_R5 ? D5REGS \
708 : (REGNO) == REG_R6 ? D6REGS \
709 : (REGNO) == REG_R7 ? D7REGS \
710 : (REGNO) == REG_P0 ? P0REGS \
711 : (REGNO) < REG_I0 ? PREGS \
712 : (REGNO) == REG_ARGP ? PREGS \
713 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
714 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
715 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
716 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
717 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
718 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
719 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
720 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
721 : (REGNO) == REG_CC ? CCREGS \
722 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
725 /* The following macro defines cover classes for Integrated Register
726 Allocator. Cover classes is a set of non-intersected register
727 classes covering all hard registers used for register allocation
728 purpose. Any move between two registers of a cover class should be
729 cheaper than load or store of the registers. The macro value is
730 array of register classes with LIM_REG_CLASSES used as the end
733 #define IRA_COVER_CLASSES \
735 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
738 /* When defined, the compiler allows registers explicitly used in the
739 rtl to be used as spill registers but prevents the compiler from
740 extending the lifetime of these registers. */
741 #define SMALL_REGISTER_CLASSES 1
743 #define CLASS_LIKELY_SPILLED_P(CLASS) \
744 ((CLASS) == PREGS_CLOBBERED \
745 || (CLASS) == PROLOGUE_REGS \
746 || (CLASS) == P0REGS \
747 || (CLASS) == D0REGS \
748 || (CLASS) == D1REGS \
749 || (CLASS) == D2REGS \
750 || (CLASS) == CCREGS)
752 /* Do not allow to store a value in REG_CC for any mode */
753 /* Do not allow to store value in pregs if mode is not SI*/
754 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
756 /* Return the maximum number of consecutive registers
757 needed to represent mode MODE in a register of class CLASS. */
758 #define CLASS_MAX_NREGS(CLASS, MODE) \
759 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
760 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
762 #define HARD_REGNO_NREGS(REGNO, MODE) \
763 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
764 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
765 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
767 /* A C expression that is nonzero if hard register TO can be
768 considered for use as a rename register for FROM register */
769 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
771 /* A C expression that is nonzero if it is desirable to choose
772 register allocation so as to avoid move instructions between a
773 value of mode MODE1 and a value of mode MODE2.
775 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
776 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
777 MODE2)' must be zero. */
778 #define MODES_TIEABLE_P(MODE1, MODE2) \
779 ((MODE1) == (MODE2) \
780 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
781 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
782 && (GET_MODE_CLASS (MODE2) == MODE_INT \
783 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
784 && (MODE1) != BImode && (MODE2) != BImode \
785 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
786 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
788 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
789 A C expression that places additional restrictions on the register
790 class to use when it is necessary to copy value X into a register
791 in class CLASS. The value is a register class; perhaps CLASS, or
792 perhaps another, smaller class. */
793 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
794 (GET_CODE (X) == POST_INC \
795 || GET_CODE (X) == POST_DEC \
796 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
798 /* Function Calling Conventions. */
800 /* The type of the current function; normal functions are of type
803 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
806 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
808 /* Flags for the call/call_value rtl operations set up by function_arg */
809 #define CALL_NORMAL 0x00000000 /* no special processing */
810 #define CALL_LONG 0x00000001 /* always call indirect */
811 #define CALL_SHORT 0x00000002 /* always call by symbol */
814 int words; /* # words passed so far */
815 int nregs; /* # registers available for passing */
816 int *arg_regs; /* array of register -1 terminated */
817 int call_cookie; /* Do special things for this call */
820 /* Define where to put the arguments to a function.
821 Value is zero to push the argument on the stack,
822 or a hard register in which to store the argument.
824 MODE is the argument's machine mode.
825 TYPE is the data type of the argument (as a tree).
826 This is null for libcalls where that information may
828 CUM is a variable of type CUMULATIVE_ARGS which gives info about
829 the preceding args and about the function being called.
830 NAMED is nonzero if this argument is a named parameter
831 (otherwise it is an extra parameter matching an ellipsis). */
833 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
834 (function_arg (&CUM, MODE, TYPE, NAMED))
836 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
839 /* Initialize a variable CUM of type CUMULATIVE_ARGS
840 for a call to a function whose data type is FNTYPE.
841 For a library call, FNTYPE is 0. */
842 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
843 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
845 /* Update the data in CUM to advance over an argument
846 of mode MODE and data type TYPE.
847 (TYPE is null for libcalls where that information may not be available.) */
848 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
849 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
851 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
853 /* Define how to find the value returned by a function.
854 VALTYPE is the data type of the value (as a tree).
855 If the precise function being called is known, FUNC is its FUNCTION_DECL;
856 otherwise, FUNC is 0.
859 #define VALUE_REGNO(MODE) (REG_R0)
861 #define FUNCTION_VALUE(VALTYPE, FUNC) \
862 gen_rtx_REG (TYPE_MODE (VALTYPE), \
863 VALUE_REGNO(TYPE_MODE(VALTYPE)))
865 /* Define how to find the value returned by a library function
866 assuming the value has mode MODE. */
868 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
870 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
872 #define DEFAULT_PCC_STRUCT_RETURN 0
874 /* Before the prologue, the return address is in the RETS register. */
875 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
877 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
879 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
881 /* Call instructions don't modify the stack pointer on the Blackfin. */
882 #define INCOMING_FRAME_SP_OFFSET 0
884 /* Describe how we implement __builtin_eh_return. */
885 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
886 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
887 #define EH_RETURN_HANDLER_RTX \
888 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
890 /* Addressing Modes */
892 /* Recognize any constant value that is a valid address. */
893 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
895 /* Nonzero if the constant value X is a legitimate general operand.
896 symbol_ref are not legitimate and will be put into constant pool.
897 See force_const_mem().
898 If -mno-pool, all constants are legitimate.
900 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
902 /* A number, the maximum number of registers that can appear in a
903 valid memory address. Note that it is up to you to specify a
904 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
905 would ever accept. */
906 #define MAX_REGS_PER_ADDRESS 1
908 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
909 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
911 #define HAVE_POST_INCREMENT 1
912 #define HAVE_POST_DECREMENT 1
913 #define HAVE_PRE_DECREMENT 1
915 /* `LEGITIMATE_PIC_OPERAND_P (X)'
916 A C expression that is nonzero if X is a legitimate immediate
917 operand on the target machine when generating position independent
918 code. You can assume that X satisfies `CONSTANT_P', so you need
919 not check this. You can also assume FLAG_PIC is true, so you need
920 not check it either. You need not define this macro if all
921 constants (including `SYMBOL_REF') can be immediate operands when
922 generating position independent code. */
923 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
925 #define SYMBOLIC_CONST(X) \
926 (GET_CODE (X) == SYMBOL_REF \
927 || GET_CODE (X) == LABEL_REF \
928 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
930 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
932 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
933 is done just by pretending it is already truncated. */
934 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
936 /* Max number of bytes we can move from memory to memory
937 in one reasonably fast instruction. */
938 #define MOVE_MAX UNITS_PER_WORD
940 /* If a memory-to-memory move would take MOVE_RATIO or more simple
941 move-instruction pairs, we will do a movmem or libcall instead. */
943 #define MOVE_RATIO(speed) 5
945 /* STORAGE LAYOUT: target machine storage layout
946 Define this macro as a C expression which is nonzero if accessing
947 less than a word of memory (i.e. a `char' or a `short') is no
948 faster than accessing a word of memory, i.e., if such access
949 require more than one instruction or if there is no difference in
950 cost between byte and (aligned) word loads.
952 When this macro is not defined, the compiler will access a field by
953 finding the smallest containing object; when it is defined, a
954 fullword load will be used if alignment permits. Unless bytes
955 accesses are faster than word accesses, using word accesses is
956 preferable since it may eliminate subsequent memory access if
957 subsequent accesses occur to other fields in the same word of the
958 structure, but to different bytes. */
959 #define SLOW_BYTE_ACCESS 0
960 #define SLOW_SHORT_ACCESS 0
962 /* Define this if most significant bit is lowest numbered
963 in instructions that operate on numbered bit-fields. */
964 #define BITS_BIG_ENDIAN 0
966 /* Define this if most significant byte of a word is the lowest numbered.
967 We can't access bytes but if we could we would in the Big Endian order. */
968 #define BYTES_BIG_ENDIAN 0
970 /* Define this if most significant word of a multiword number is numbered. */
971 #define WORDS_BIG_ENDIAN 0
973 /* number of bits in an addressable storage unit */
974 #define BITS_PER_UNIT 8
976 /* Width in bits of a "word", which is the contents of a machine register.
977 Note that this is not necessarily the width of data type `int';
978 if using 16-bit ints on a 68000, this would still be 32.
979 But on a machine with 16-bit registers, this would be 16. */
980 #define BITS_PER_WORD 32
982 /* Width of a word, in units (bytes). */
983 #define UNITS_PER_WORD 4
985 /* Width in bits of a pointer.
986 See also the macro `Pmode1' defined below. */
987 #define POINTER_SIZE 32
989 /* Allocation boundary (in *bits*) for storing pointers in memory. */
990 #define POINTER_BOUNDARY 32
992 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
993 #define PARM_BOUNDARY 32
995 /* Boundary (in *bits*) on which stack pointer should be aligned. */
996 #define STACK_BOUNDARY 32
998 /* Allocation boundary (in *bits*) for the code of a function. */
999 #define FUNCTION_BOUNDARY 32
1001 /* Alignment of field after `int : 0' in a structure. */
1002 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1004 /* No data type wants to be aligned rounder than this. */
1005 #define BIGGEST_ALIGNMENT 32
1007 /* Define this if move instructions will actually fail to work
1008 when given unaligned data. */
1009 #define STRICT_ALIGNMENT 1
1011 /* (shell-command "rm c-decl.o stor-layout.o")
1012 * never define PCC_BITFIELD_TYPE_MATTERS
1013 * really cause some alignment problem
1016 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1019 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1023 /* what is the 'type' of size_t */
1024 #define SIZE_TYPE "long unsigned int"
1026 /* Define this as 1 if `char' should by default be signed; else as 0. */
1027 #define DEFAULT_SIGNED_CHAR 1
1028 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1029 #define SHORT_TYPE_SIZE 16
1030 #define CHAR_TYPE_SIZE 8
1031 #define INT_TYPE_SIZE 32
1032 #define LONG_TYPE_SIZE 32
1033 #define LONG_LONG_TYPE_SIZE 64
1035 /* Note: Fix this to depend on target switch. -- lev */
1037 /* Note: Try to implement double and force long double. -- tonyko
1038 * #define __DOUBLES_ARE_FLOATS__
1039 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1040 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1041 * #define DOUBLES_ARE_FLOATS 1
1044 #define DOUBLE_TYPE_SIZE 64
1045 #define LONG_DOUBLE_TYPE_SIZE 64
1047 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1048 A macro to update M and UNSIGNEDP when an object whose type is
1049 TYPE and which has the specified mode and signedness is to be
1050 stored in a register. This macro is only called when TYPE is a
1053 On most RISC machines, which only have operations that operate on
1054 a full register, define this macro to set M to `word_mode' if M is
1055 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1056 only integer modes should be widened because wider-precision
1057 floating-point operations are usually more expensive than their
1058 narrower counterparts.
1060 For most machines, the macro definition does not change UNSIGNEDP.
1061 However, some machines, have instructions that preferentially
1062 handle either signed or unsigned quantities of certain modes. For
1063 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1064 instructions sign-extend the result to 64 bits. On such machines,
1065 set UNSIGNEDP according to which kind of extension is more
1068 Do not define this macro if it would never modify M.*/
1070 #define BFIN_PROMOTE_MODE_P(MODE) \
1071 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1072 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1074 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1075 if (BFIN_PROMOTE_MODE_P(MODE)) \
1077 if (MODE == QImode) \
1079 else if (MODE == HImode) \
1084 /* Describing Relative Costs of Operations */
1086 /* Do not put function addr into constant pool */
1087 #define NO_FUNCTION_CSE 1
1089 /* A C expression for the cost of moving data from a register in class FROM to
1090 one in class TO. The classes are expressed using the enumeration values
1091 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1092 interpreted relative to that.
1094 It is not required that the cost always equal 2 when FROM is the same as TO;
1095 on some machines it is expensive to move between registers if they are not
1096 general registers. */
1098 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1099 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1101 /* A C expression for the cost of moving data of mode M between a
1102 register and memory. A value of 2 is the default; this cost is
1103 relative to those in `REGISTER_MOVE_COST'.
1105 If moving between registers and memory is more expensive than
1106 between two registers, you should define this macro to express the
1109 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1110 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1112 /* Specify the machine mode that this machine uses
1113 for the index in the tablejump instruction. */
1114 #define CASE_VECTOR_MODE SImode
1116 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1118 /* Define if operations between registers always perform the operation
1119 on the full register even if a narrower mode is specified.
1120 #define WORD_REGISTER_OPERATIONS
1123 /* Evaluates to true if A and B are mac flags that can be used
1124 together in a single multiply insn. That is the case if they are
1125 both the same flag not involving M, or if one is a combination of
1126 the other with M. */
1127 #define MACFLAGS_MATCH_P(A, B) \
1129 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1130 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1131 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1132 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1134 /* Switch into a generic section. */
1135 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1137 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1138 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1140 typedef enum sections {
1146 typedef enum directives {
1155 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1157 || ((C) == '|' && (STR)[1] == '|'))
1159 #define TEXT_SECTION_ASM_OP ".text;"
1160 #define DATA_SECTION_ASM_OP ".data;"
1162 #define ASM_APP_ON ""
1163 #define ASM_APP_OFF ""
1165 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1166 do { fputs (".global ", FILE); \
1167 assemble_name (FILE, NAME); \
1169 fputc ('\n',FILE); \
1172 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1174 fputs (".type ", FILE); \
1175 assemble_name (FILE, NAME); \
1176 fputs (", STT_FUNC", FILE); \
1178 fputc ('\n',FILE); \
1179 ASM_OUTPUT_LABEL(FILE, NAME); \
1182 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1183 do { assemble_name (FILE, NAME); \
1184 fputs (":\n",FILE); \
1187 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1188 do { fprintf (FILE, "_%s", NAME); \
1191 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1192 do { char __buf[256]; \
1193 fprintf (FILE, "\t.dd\t"); \
1194 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1195 assemble_name (FILE, __buf); \
1196 fputc (';', FILE); \
1197 fputc ('\n', FILE); \
1200 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1201 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1203 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1206 fprintf (FILE, "\t.dd\t"); \
1207 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1208 assemble_name (FILE, __buf); \
1209 fputs (" - ", FILE); \
1210 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1211 assemble_name (FILE, __buf); \
1212 fputc (';', FILE); \
1213 fputc ('\n', FILE); \
1216 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1219 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1222 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1224 asm_output_skip (FILE, SIZE); \
1227 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1229 switch_to_section (data_section); \
1230 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1231 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1232 ASM_OUTPUT_LABEL (FILE, NAME); \
1233 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1234 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1237 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1239 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1240 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1242 #define ASM_COMMENT_START "//"
1244 #define FUNCTION_PROFILER(FILE, LABELNO) \
1246 fprintf (FILE, "\tCALL __mcount;\n"); \
1249 #undef NO_PROFILE_COUNTERS
1250 #define NO_PROFILE_COUNTERS 1
1252 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1253 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1255 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1257 /* This works for GAS and some other assemblers. */
1258 #define SET_ASM_OP ".set "
1260 /* DBX register number for a given compiler register number */
1261 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1263 #define SIZE_ASM_OP "\t.size\t"
1265 extern int splitting_for_sched, splitting_loops;
1267 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1269 #endif /* _BFIN_CONFIG */