1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
29 /* Print subsidiary information on the compiler version in use. */
30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32 /* Run-time compilation parameters selecting different hardware subsets. */
34 extern int target_flags;
36 #ifndef DEFAULT_CPU_TYPE
37 #define DEFAULT_CPU_TYPE BFIN_CPU_BF532
40 /* Predefinition in the preprocessor for this target machine */
41 #ifndef TARGET_CPU_CPP_BUILTINS
42 #define TARGET_CPU_CPP_BUILTINS() \
45 builtin_define_std ("bfin"); \
46 builtin_define_std ("BFIN"); \
47 builtin_define ("__ADSPBLACKFIN__"); \
48 builtin_define ("__ADSPLPBLACKFIN__"); \
50 switch (bfin_cpu_type) \
52 case BFIN_CPU_BF531: \
53 builtin_define ("__ADSPBF531__"); \
55 case BFIN_CPU_BF532: \
56 builtin_define ("__ADSPBF532__"); \
58 case BFIN_CPU_BF533: \
59 builtin_define ("__ADSPBF533__"); \
61 case BFIN_CPU_BF534: \
62 builtin_define ("__ADSPBF534__"); \
64 case BFIN_CPU_BF536: \
65 builtin_define ("__ADSPBF536__"); \
67 case BFIN_CPU_BF537: \
68 builtin_define ("__ADSPBF537__"); \
70 case BFIN_CPU_BF561: \
71 builtin_define ("__ADSPBF561__"); \
76 builtin_define ("__BFIN_FDPIC__"); \
77 if (TARGET_ID_SHARED_LIBRARY) \
78 builtin_define ("__ID_SHARED_LIB__"); \
83 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
84 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
85 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
86 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
88 #ifndef SUBTARGET_DRIVER_SELF_SPECS
89 # define SUBTARGET_DRIVER_SELF_SPECS
92 #define LINK_GCC_C_SEQUENCE_SPEC \
93 "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \
96 /* A C string constant that tells the GCC driver program options to pass to
97 the assembler. It can also specify how to translate options you give to GNU
98 CC into options for GCC to pass to the assembler. See the file `sun3.h'
99 for an example of this.
101 Do not define this macro if it does not need to do anything.
103 Defined in svr4.h. */
106 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
107 %{mno-fdpic:-mnopic} %{mfdpic}"
112 %{mfdpic:-melf32bfinfd -z text} \
113 %{static:-dn -Bstatic} \
114 %{shared:-G -Bdynamic} \
115 %{symbolic:-Bsymbolic} \
119 -init __init -fini __fini "
121 /* Generate DSP instructions, like DSP halfword loads */
122 #define TARGET_DSP (1)
124 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
126 /* Maximum number of library ids we permit */
127 #define MAX_LIBRARY_ID 255
129 extern const char *bfin_library_id_string;
131 /* Sometimes certain combinations of command options do not make
132 sense on a particular target machine. You can define a macro
133 `OVERRIDE_OPTIONS' to take account of this. This macro, if
134 defined, is executed once just after all the command options have
137 Don't use this macro to turn on various extra optimizations for
138 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
140 #define OVERRIDE_OPTIONS override_options ()
142 #define FUNCTION_MODE SImode
145 /* store-condition-codes instructions store 0 for false
146 This is the value stored for true. */
147 #define STORE_FLAG_VALUE 1
149 /* Define this if pushing a word on the stack
150 makes the stack pointer a smaller address. */
151 #define STACK_GROWS_DOWNWARD
153 #define STACK_PUSH_CODE PRE_DEC
155 /* Define this to nonzero if the nominal address of the stack frame
156 is at the high-address end of the local variables;
157 that is, each additional local variable allocated
158 goes at a more negative offset in the frame. */
159 #define FRAME_GROWS_DOWNWARD 1
161 /* We define a dummy ARGP register; the parameters start at offset 0 from
163 #define FIRST_PARM_OFFSET(DECL) 0
165 /* Offset within stack frame to start allocating local variables at.
166 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
167 first local allocated. Otherwise, it is the offset to the BEGINNING
168 of the first local allocated. */
169 #define STARTING_FRAME_OFFSET 0
171 /* Register to use for pushing function arguments. */
172 #define STACK_POINTER_REGNUM REG_P6
174 /* Base register for access to local variables of the function. */
175 #define FRAME_POINTER_REGNUM REG_P7
177 /* A dummy register that will be eliminated to either FP or SP. */
178 #define ARG_POINTER_REGNUM REG_ARGP
180 /* `PIC_OFFSET_TABLE_REGNUM'
181 The register number of the register used to address a table of
182 static data addresses in memory. In some cases this register is
183 defined by a processor's "application binary interface" (ABI).
184 When this macro is defined, RTL is generated for this register
185 once, as with the stack pointer and frame pointer registers. If
186 this macro is not defined, it is up to the machine-dependent files
187 to allocate such a register (if necessary). */
188 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
190 #define FDPIC_FPTR_REGNO REG_P1
191 #define FDPIC_REGNO REG_P3
192 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
194 /* A static chain register for nested functions. We need to use a
195 call-clobbered register for this. */
196 #define STATIC_CHAIN_REGNUM REG_P2
198 /* Define this if functions should assume that stack space has been
199 allocated for arguments even when their values are passed in
202 The value of this macro is the size, in bytes, of the area reserved for
203 arguments passed in registers.
205 This space can either be allocated by the caller or be a part of the
206 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
208 #define FIXED_STACK_AREA 12
209 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
211 /* Define this if the above stack space is to be considered part of the
212 * space allocated by the caller. */
213 #define OUTGOING_REG_PARM_STACK_SPACE 1
215 /* Define this if the maximum size of all the outgoing args is to be
216 accumulated and pushed during the prologue. The amount can be
217 found in the variable current_function_outgoing_args_size. */
218 #define ACCUMULATE_OUTGOING_ARGS 1
220 /* Value should be nonzero if functions must have frame pointers.
221 Zero means the frame pointer need not be set up (and parms
222 may be accessed via the stack pointer) in functions that seem suitable.
223 This is computed in `reload', in reload1.c.
225 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
227 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
229 /* If defined, a C expression to compute the alignment for a local
230 variable. TYPE is the data type, and ALIGN is the alignment that
231 the object would ordinarily have. The value of this macro is used
232 instead of that alignment to align the object.
234 If this macro is not defined, then ALIGN is used.
236 One use of this macro is to increase alignment of medium-size
237 data to make it all fit in fewer cache lines. */
239 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
241 /* Make strings word-aligned so strcpy from constants will be faster. */
242 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
243 (TREE_CODE (EXP) == STRING_CST \
244 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
246 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
247 #define TRAMPOLINE_TEMPLATE(FILE) \
250 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
251 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
252 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
253 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
254 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
255 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
256 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
257 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
258 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
262 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
263 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
264 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
265 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
266 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
269 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
270 initialize_trampoline (TRAMP, FNADDR, CXT)
272 /* Definitions for register eliminations.
274 This is an array of structures. Each structure initializes one pair
275 of eliminable registers. The "from" register number is given first,
276 followed by "to". Eliminations of the same "from" register are listed
277 in order of preference.
279 There are two registers that can always be eliminated on the i386.
280 The frame pointer and the arg pointer can be replaced by either the
281 hard frame pointer or to the stack pointer, depending upon the
282 circumstances. The hard frame pointer is not used before reload and
283 so it is not eligible for elimination. */
285 #define ELIMINABLE_REGS \
286 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
287 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
288 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
290 /* Given FROM and TO register numbers, say whether this elimination is
291 allowed. Frame pointer elimination is automatically handled.
293 All other eliminations are valid. */
295 #define CAN_ELIMINATE(FROM, TO) \
296 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
298 /* Define the offset between two registers, one to be eliminated, and the other
299 its replacement, at the start of a routine. */
301 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
302 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
304 /* This processor has
305 8 data register for doing arithmetic
306 8 pointer register for doing addressing, including
309 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
310 1 condition code flag register CC
311 5 return address registers RETS/I/X/N/E
312 1 arithmetic status register (ASTAT). */
314 #define FIRST_PSEUDO_REGISTER 50
316 #define D_REGNO_P(X) ((X) <= REG_R7)
317 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
318 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
319 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
320 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
321 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
322 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
323 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
324 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
326 #define REGISTER_NAMES { \
327 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
328 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
329 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
330 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
333 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
335 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
338 #define SHORT_REGISTER_NAMES { \
339 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
340 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
341 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
342 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
344 #define HIGH_REGISTER_NAMES { \
345 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
346 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
347 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
348 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
350 #define DREGS_PAIR_NAMES { \
351 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
353 #define BYTE_REGISTER_NAMES { \
354 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
357 /* 1 for registers that have pervasive standard uses
358 and are not available for the register allocator. */
360 #define FIXED_REGISTERS \
361 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
362 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
363 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
364 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
365 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
366 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
371 /* 1 for registers not available across function calls.
372 These must include the FIXED_REGISTERS and also any
373 registers that can be used without being saved.
374 The latter must include the registers where values are returned
375 and the register where structure-value addresses are passed.
376 Aside from that, you can include as many other registers as you like. */
378 #define CALL_USED_REGISTERS \
379 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
380 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
381 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
382 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
383 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
384 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
389 /* Order in which to allocate registers. Each register must be
390 listed once, even those in FIXED_REGISTERS. List frame pointer
391 late and fixed registers last. Note that, in general, we prefer
392 registers listed in CALL_USED_REGISTERS, keeping the others
393 available for storage of persistent values. */
395 #define REG_ALLOC_ORDER \
396 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
397 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
399 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
400 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
401 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
402 REG_ASTAT, REG_SEQSTAT, REG_USP, \
404 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
407 /* Macro to conditionally modify fixed_regs/call_used_regs. */
408 #define CONDITIONAL_REGISTER_USAGE \
410 conditional_register_usage(); \
412 call_used_regs[FDPIC_REGNO] = 1; \
413 if (!TARGET_FDPIC && flag_pic) \
415 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
416 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
420 /* Define the classes of registers for register constraints in the
421 machine description. Also define ranges of constants.
423 One of the classes must always be named ALL_REGS and include all hard regs.
424 If there is more than one class, another class must be named NO_REGS
425 and contain no registers.
427 The name GENERAL_REGS must be the name of a class (or an alias for
428 another name such as ALL_REGS). This is the class of registers
429 that is allowed by "g" or "r" in a register constraint.
430 Also, registers outside this class are allocated only when
431 instructions express preferences for them.
433 The classes must be numbered in nondecreasing order; that is,
434 a larger-numbered class must never be contained completely
435 in a smaller-numbered class.
437 For any two classes, it is very desirable that there be another
438 class that represents their union. */
448 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
477 ALL_REGS, LIM_REG_CLASSES
480 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
482 #define GENERAL_REGS DPREGS
484 /* Give names of register classes as strings for dump file. */
486 #define REG_CLASS_NAMES \
523 /* An initializer containing the contents of the register classes, as integers
524 which are bit masks. The Nth integer specifies the contents of class N.
525 The way the integer MASK is interpreted is that register R is in the class
526 if `MASK & (1 << R)' is 1.
528 When the machine has more than 32 registers, an integer does not suffice.
529 Then the integers are replaced by sub-initializers, braced groupings
530 containing several integers. Each sub-initializer must be suitable as an
531 initializer for the type `HARD_REG_SET' which is defined in
534 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
535 MOST_REGS as the union of DPREGS and DAGREGS. */
537 #define REG_CLASS_CONTENTS \
539 { { 0x00000000, 0 }, /* NO_REGS */ \
540 { 0x000f0000, 0 }, /* IREGS */ \
541 { 0x00f00000, 0 }, /* BREGS */ \
542 { 0x0f000000, 0 }, /* LREGS */ \
543 { 0xf0000000, 0 }, /* MREGS */ \
544 { 0x0fff0000, 0 }, /* CIRCREGS */ \
545 { 0xffff0000, 0 }, /* DAGREGS */ \
546 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
547 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
548 { 0x00000000, 0x3 }, /* AREGS */ \
549 { 0x00000000, 0x4 }, /* CCREGS */ \
550 { 0x00000055, 0 }, /* EVEN_DREGS */ \
551 { 0x000000aa, 0 }, /* ODD_DREGS */ \
552 { 0x00000001, 0 }, /* D0REGS */ \
553 { 0x00000002, 0 }, /* D1REGS */ \
554 { 0x00000004, 0 }, /* D2REGS */ \
555 { 0x00000008, 0 }, /* D3REGS */ \
556 { 0x00000010, 0 }, /* D4REGS */ \
557 { 0x00000020, 0 }, /* D5REGS */ \
558 { 0x00000040, 0 }, /* D6REGS */ \
559 { 0x00000080, 0 }, /* D7REGS */ \
560 { 0x000000ff, 0 }, /* DREGS */ \
561 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
562 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
563 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
564 { 0x0000ff00, 0x800 }, /* PREGS */ \
565 { 0x000fff00, 0x800 }, /* IPREGS */ \
566 { 0x0000ffff, 0x800 }, /* DPREGS */ \
567 { 0xffffffff, 0x800 }, /* MOST_REGS */\
568 { 0x00000000, 0x3000 }, /* LT_REGS */\
569 { 0x00000000, 0xc000 }, /* LC_REGS */\
570 { 0x00000000, 0x30000 }, /* LB_REGS */\
571 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
572 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
573 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
575 #define IREG_POSSIBLE_P(OUTER) \
576 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
577 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
578 || (OUTER) == MEM || (OUTER) == ADDRESS)
580 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
581 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
583 #define INDEX_REG_CLASS PREGS
585 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
586 (P_REGNO_P (X) || (X) == REG_ARGP \
587 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
590 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
591 ((X) >= FIRST_PSEUDO_REGISTER \
592 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
595 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
596 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
598 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
599 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
602 #define REGNO_OK_FOR_INDEX_P(X) 0
604 /* Get reg_class from a letter such as appears in the machine description. */
606 #define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \
607 ((LETTER) == 'a' ? PREGS : \
608 (LETTER) == 'Z' ? FDPIC_REGS : \
609 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
610 (LETTER) == 'd' ? DREGS : \
611 (LETTER) == 'z' ? PREGS_CLOBBERED : \
612 (LETTER) == 'D' ? EVEN_DREGS : \
613 (LETTER) == 'W' ? ODD_DREGS : \
614 (LETTER) == 'e' ? AREGS : \
615 (LETTER) == 'A' ? EVEN_AREGS : \
616 (LETTER) == 'B' ? ODD_AREGS : \
617 (LETTER) == 'b' ? IREGS : \
618 (LETTER) == 'v' ? BREGS : \
619 (LETTER) == 'f' ? MREGS : \
620 (LETTER) == 'c' ? CIRCREGS : \
621 (LETTER) == 'C' ? CCREGS : \
622 (LETTER) == 't' ? LT_REGS : \
623 (LETTER) == 'k' ? LC_REGS : \
624 (LETTER) == 'u' ? LB_REGS : \
625 (LETTER) == 'x' ? MOST_REGS : \
626 (LETTER) == 'y' ? PROLOGUE_REGS : \
627 (LETTER) == 'w' ? NON_A_CC_REGS : \
629 ? ((STR)[1] == '0' ? D0REGS \
630 : (STR)[1] == '1' ? D1REGS \
631 : (STR)[1] == '2' ? D2REGS \
632 : (STR)[1] == '3' ? D3REGS \
633 : (STR)[1] == '4' ? D4REGS \
634 : (STR)[1] == '5' ? D5REGS \
635 : (STR)[1] == '6' ? D6REGS \
636 : (STR)[1] == '7' ? D7REGS \
640 /* The same information, inverted:
641 Return the class number of the smallest class containing
642 reg number REGNO. This could be a conditional expression
643 or could index an array. */
645 #define REGNO_REG_CLASS(REGNO) \
646 ((REGNO) == REG_R0 ? D0REGS \
647 : (REGNO) == REG_R1 ? D1REGS \
648 : (REGNO) == REG_R2 ? D2REGS \
649 : (REGNO) == REG_R3 ? D3REGS \
650 : (REGNO) == REG_R4 ? D4REGS \
651 : (REGNO) == REG_R5 ? D5REGS \
652 : (REGNO) == REG_R6 ? D6REGS \
653 : (REGNO) == REG_R7 ? D7REGS \
654 : (REGNO) < REG_I0 ? PREGS \
655 : (REGNO) == REG_ARGP ? PREGS \
656 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
657 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
658 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
659 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
660 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
661 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
662 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
663 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
664 : (REGNO) == REG_CC ? CCREGS \
665 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
668 /* When defined, the compiler allows registers explicitly used in the
669 rtl to be used as spill registers but prevents the compiler from
670 extending the lifetime of these registers. */
671 #define SMALL_REGISTER_CLASSES 1
673 #define CLASS_LIKELY_SPILLED_P(CLASS) \
674 ((CLASS) == PREGS_CLOBBERED \
675 || (CLASS) == PROLOGUE_REGS \
676 || (CLASS) == D0REGS \
677 || (CLASS) == D1REGS \
678 || (CLASS) == D2REGS \
679 || (CLASS) == CCREGS)
681 /* Do not allow to store a value in REG_CC for any mode */
682 /* Do not allow to store value in pregs if mode is not SI*/
683 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
685 /* Return the maximum number of consecutive registers
686 needed to represent mode MODE in a register of class CLASS. */
687 #define CLASS_MAX_NREGS(CLASS, MODE) \
688 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
689 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
691 #define HARD_REGNO_NREGS(REGNO, MODE) \
692 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
693 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
694 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
696 /* A C expression that is nonzero if hard register TO can be
697 considered for use as a rename register for FROM register */
698 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
700 /* A C expression that is nonzero if it is desirable to choose
701 register allocation so as to avoid move instructions between a
702 value of mode MODE1 and a value of mode MODE2.
704 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
705 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
706 MODE2)' must be zero. */
707 #define MODES_TIEABLE_P(MODE1, MODE2) \
708 ((MODE1) == (MODE2) \
709 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
710 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
711 && (GET_MODE_CLASS (MODE2) == MODE_INT \
712 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
713 && (MODE1) != BImode && (MODE2) != BImode \
714 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
715 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
717 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
718 A C expression that places additional restrictions on the register
719 class to use when it is necessary to copy value X into a register
720 in class CLASS. The value is a register class; perhaps CLASS, or
721 perhaps another, smaller class. */
722 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
724 /* Function Calling Conventions. */
726 /* The type of the current function; normal functions are of type
729 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
732 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
734 /* Flags for the call/call_value rtl operations set up by function_arg */
735 #define CALL_NORMAL 0x00000000 /* no special processing */
736 #define CALL_LONG 0x00000001 /* always call indirect */
737 #define CALL_SHORT 0x00000002 /* always call by symbol */
740 int words; /* # words passed so far */
741 int nregs; /* # registers available for passing */
742 int *arg_regs; /* array of register -1 terminated */
743 int call_cookie; /* Do special things for this call */
746 /* Define where to put the arguments to a function.
747 Value is zero to push the argument on the stack,
748 or a hard register in which to store the argument.
750 MODE is the argument's machine mode.
751 TYPE is the data type of the argument (as a tree).
752 This is null for libcalls where that information may
754 CUM is a variable of type CUMULATIVE_ARGS which gives info about
755 the preceding args and about the function being called.
756 NAMED is nonzero if this argument is a named parameter
757 (otherwise it is an extra parameter matching an ellipsis). */
759 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
760 (function_arg (&CUM, MODE, TYPE, NAMED))
762 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
765 /* Initialize a variable CUM of type CUMULATIVE_ARGS
766 for a call to a function whose data type is FNTYPE.
767 For a library call, FNTYPE is 0. */
768 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
769 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
771 /* Update the data in CUM to advance over an argument
772 of mode MODE and data type TYPE.
773 (TYPE is null for libcalls where that information may not be available.) */
774 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
775 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
777 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
779 /* Define how to find the value returned by a function.
780 VALTYPE is the data type of the value (as a tree).
781 If the precise function being called is known, FUNC is its FUNCTION_DECL;
782 otherwise, FUNC is 0.
785 #define VALUE_REGNO(MODE) (REG_R0)
787 #define FUNCTION_VALUE(VALTYPE, FUNC) \
788 gen_rtx_REG (TYPE_MODE (VALTYPE), \
789 VALUE_REGNO(TYPE_MODE(VALTYPE)))
791 /* Define how to find the value returned by a library function
792 assuming the value has mode MODE. */
794 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
796 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
798 #define DEFAULT_PCC_STRUCT_RETURN 0
799 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
801 /* Before the prologue, the return address is in the RETS register. */
802 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
804 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
806 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
808 /* Call instructions don't modify the stack pointer on the Blackfin. */
809 #define INCOMING_FRAME_SP_OFFSET 0
811 /* Describe how we implement __builtin_eh_return. */
812 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
813 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
814 #define EH_RETURN_HANDLER_RTX \
815 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
817 /* Addressing Modes */
819 /* Recognize any constant value that is a valid address. */
820 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
822 /* Nonzero if the constant value X is a legitimate general operand.
823 symbol_ref are not legitimate and will be put into constant pool.
824 See force_const_mem().
825 If -mno-pool, all constants are legitimate.
827 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
829 /* A number, the maximum number of registers that can appear in a
830 valid memory address. Note that it is up to you to specify a
831 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
832 would ever accept. */
833 #define MAX_REGS_PER_ADDRESS 1
835 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
836 that is a valid memory address for an instruction.
837 The MODE argument is the machine mode for the MEM expression
838 that wants to use this address.
840 Blackfin addressing modes are as follows:
846 W [ Preg + uimm16m2 ]
854 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
855 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
858 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
860 if (bfin_legitimate_address_p (MODE, X, 1)) \
864 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
866 if (bfin_legitimate_address_p (MODE, X, 0)) \
871 /* Try machine-dependent ways of modifying an illegitimate address
872 to be legitimate. If we find one, return the new, valid address.
873 This macro is used in only one place: `memory_address' in explow.c.
875 OLDX is the address as it was before break_out_memory_refs was called.
876 In some cases it is useful to look at this to decide what needs to be done.
878 MODE and WIN are passed so that this macro can use
879 GO_IF_LEGITIMATE_ADDRESS.
881 It is always safe for this macro to do nothing. It exists to recognize
882 opportunities to optimize the output.
884 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
886 rtx _q = legitimize_address(X, OLDX, MODE); \
887 if (_q) { X = _q; goto WIN; } \
890 #define HAVE_POST_INCREMENT 1
891 #define HAVE_POST_DECREMENT 1
892 #define HAVE_PRE_DECREMENT 1
894 /* `LEGITIMATE_PIC_OPERAND_P (X)'
895 A C expression that is nonzero if X is a legitimate immediate
896 operand on the target machine when generating position independent
897 code. You can assume that X satisfies `CONSTANT_P', so you need
898 not check this. You can also assume FLAG_PIC is true, so you need
899 not check it either. You need not define this macro if all
900 constants (including `SYMBOL_REF') can be immediate operands when
901 generating position independent code. */
902 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
904 #define SYMBOLIC_CONST(X) \
905 (GET_CODE (X) == SYMBOL_REF \
906 || GET_CODE (X) == LABEL_REF \
907 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
910 A C statement or compound statement with a conditional `goto
911 LABEL;' executed if memory address X (an RTX) can have different
912 meanings depending on the machine mode of the memory reference it
913 is used for or if the address is valid for some modes but not
916 Autoincrement and autodecrement addresses typically have
917 mode-dependent effects because the amount of the increment or
918 decrement is the size of the operand being addressed. Some
919 machines have other mode-dependent addresses. Many RISC machines
920 have no mode-dependent addresses.
922 You may assume that ADDR is a valid address for the machine.
924 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
926 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
928 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
929 is done just by pretending it is already truncated. */
930 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
932 /* Max number of bytes we can move from memory to memory
933 in one reasonably fast instruction. */
934 #define MOVE_MAX UNITS_PER_WORD
936 /* If a memory-to-memory move would take MOVE_RATIO or more simple
937 move-instruction pairs, we will do a movmem or libcall instead. */
941 /* STORAGE LAYOUT: target machine storage layout
942 Define this macro as a C expression which is nonzero if accessing
943 less than a word of memory (i.e. a `char' or a `short') is no
944 faster than accessing a word of memory, i.e., if such access
945 require more than one instruction or if there is no difference in
946 cost between byte and (aligned) word loads.
948 When this macro is not defined, the compiler will access a field by
949 finding the smallest containing object; when it is defined, a
950 fullword load will be used if alignment permits. Unless bytes
951 accesses are faster than word accesses, using word accesses is
952 preferable since it may eliminate subsequent memory access if
953 subsequent accesses occur to other fields in the same word of the
954 structure, but to different bytes. */
955 #define SLOW_BYTE_ACCESS 0
956 #define SLOW_SHORT_ACCESS 0
958 /* Define this if most significant bit is lowest numbered
959 in instructions that operate on numbered bit-fields. */
960 #define BITS_BIG_ENDIAN 0
962 /* Define this if most significant byte of a word is the lowest numbered.
963 We can't access bytes but if we could we would in the Big Endian order. */
964 #define BYTES_BIG_ENDIAN 0
966 /* Define this if most significant word of a multiword number is numbered. */
967 #define WORDS_BIG_ENDIAN 0
969 /* number of bits in an addressable storage unit */
970 #define BITS_PER_UNIT 8
972 /* Width in bits of a "word", which is the contents of a machine register.
973 Note that this is not necessarily the width of data type `int';
974 if using 16-bit ints on a 68000, this would still be 32.
975 But on a machine with 16-bit registers, this would be 16. */
976 #define BITS_PER_WORD 32
978 /* Width of a word, in units (bytes). */
979 #define UNITS_PER_WORD 4
981 /* Width in bits of a pointer.
982 See also the macro `Pmode1' defined below. */
983 #define POINTER_SIZE 32
985 /* Allocation boundary (in *bits*) for storing pointers in memory. */
986 #define POINTER_BOUNDARY 32
988 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
989 #define PARM_BOUNDARY 32
991 /* Boundary (in *bits*) on which stack pointer should be aligned. */
992 #define STACK_BOUNDARY 32
994 /* Allocation boundary (in *bits*) for the code of a function. */
995 #define FUNCTION_BOUNDARY 32
997 /* Alignment of field after `int : 0' in a structure. */
998 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1000 /* No data type wants to be aligned rounder than this. */
1001 #define BIGGEST_ALIGNMENT 32
1003 /* Define this if move instructions will actually fail to work
1004 when given unaligned data. */
1005 #define STRICT_ALIGNMENT 1
1007 /* (shell-command "rm c-decl.o stor-layout.o")
1008 * never define PCC_BITFIELD_TYPE_MATTERS
1009 * really cause some alignment problem
1012 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1015 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1019 /* what is the 'type' of size_t */
1020 #define SIZE_TYPE "long unsigned int"
1022 /* Define this as 1 if `char' should by default be signed; else as 0. */
1023 #define DEFAULT_SIGNED_CHAR 1
1024 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1025 #define SHORT_TYPE_SIZE 16
1026 #define CHAR_TYPE_SIZE 8
1027 #define INT_TYPE_SIZE 32
1028 #define LONG_TYPE_SIZE 32
1029 #define LONG_LONG_TYPE_SIZE 64
1031 /* Note: Fix this to depend on target switch. -- lev */
1033 /* Note: Try to implement double and force long double. -- tonyko
1034 * #define __DOUBLES_ARE_FLOATS__
1035 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1036 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1037 * #define DOUBLES_ARE_FLOATS 1
1040 #define DOUBLE_TYPE_SIZE 64
1041 #define LONG_DOUBLE_TYPE_SIZE 64
1043 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1044 A macro to update M and UNSIGNEDP when an object whose type is
1045 TYPE and which has the specified mode and signedness is to be
1046 stored in a register. This macro is only called when TYPE is a
1049 On most RISC machines, which only have operations that operate on
1050 a full register, define this macro to set M to `word_mode' if M is
1051 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1052 only integer modes should be widened because wider-precision
1053 floating-point operations are usually more expensive than their
1054 narrower counterparts.
1056 For most machines, the macro definition does not change UNSIGNEDP.
1057 However, some machines, have instructions that preferentially
1058 handle either signed or unsigned quantities of certain modes. For
1059 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1060 instructions sign-extend the result to 64 bits. On such machines,
1061 set UNSIGNEDP according to which kind of extension is more
1064 Do not define this macro if it would never modify M.*/
1066 #define BFIN_PROMOTE_MODE_P(MODE) \
1067 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1068 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1070 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1071 if (BFIN_PROMOTE_MODE_P(MODE)) \
1073 if (MODE == QImode) \
1075 else if (MODE == HImode) \
1080 /* Describing Relative Costs of Operations */
1082 /* Do not put function addr into constant pool */
1083 #define NO_FUNCTION_CSE 1
1085 /* A C expression for the cost of moving data from a register in class FROM to
1086 one in class TO. The classes are expressed using the enumeration values
1087 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1088 interpreted relative to that.
1090 It is not required that the cost always equal 2 when FROM is the same as TO;
1091 on some machines it is expensive to move between registers if they are not
1092 general registers. */
1094 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1095 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1097 /* A C expression for the cost of moving data of mode M between a
1098 register and memory. A value of 2 is the default; this cost is
1099 relative to those in `REGISTER_MOVE_COST'.
1101 If moving between registers and memory is more expensive than
1102 between two registers, you should define this macro to express the
1105 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1106 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1108 /* Specify the machine mode that this machine uses
1109 for the index in the tablejump instruction. */
1110 #define CASE_VECTOR_MODE SImode
1112 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1114 /* Define if operations between registers always perform the operation
1115 on the full register even if a narrower mode is specified.
1116 #define WORD_REGISTER_OPERATIONS
1119 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
1120 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
1121 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
1122 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
1123 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
1124 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
1125 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
1126 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
1127 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
1128 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
1130 #define CONSTRAINT_LEN(C, STR) \
1131 ((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2 \
1133 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1135 #define CONST_OK_FOR_P(VALUE, STR) \
1136 ((STR)[1] == '0' ? (VALUE) == 0 \
1137 : (STR)[1] == '1' ? (VALUE) == 1 \
1138 : (STR)[1] == '2' ? (VALUE) == 2 \
1139 : (STR)[1] == '3' ? (VALUE) == 3 \
1140 : (STR)[1] == '4' ? (VALUE) == 4 \
1141 : (STR)[1] == 'A' ? (VALUE) != MACFLAG_M && (VALUE) != MACFLAG_IS_M \
1142 : (STR)[1] == 'B' ? (VALUE) == MACFLAG_M || (VALUE) == MACFLAG_IS_M \
1145 #define CONST_OK_FOR_K(VALUE, STR) \
1147 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
1148 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
1149 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
1150 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
1153 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
1154 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
1155 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
1156 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
1159 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
1162 ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \
1166 #define CONST_OK_FOR_M(VALUE, STR) \
1167 ((STR)[1] == '1' ? (VALUE) == 255 \
1168 : (STR)[1] == '2' ? (VALUE) == 65535 \
1171 /* The letters I, J, K, L and M in a register constraint string
1172 can be used to stand for particular ranges of immediate operands.
1173 This macro defines what the ranges are.
1174 C is the letter, and VALUE is a constant value.
1175 Return 1 if VALUE is in the range specified by C.
1177 bfin constant operands are as follows
1179 J 2**N 5bit imm scaled
1180 Ks7 -64 .. 63 signed 7bit imm
1181 Ku5 0..31 unsigned 5bit imm
1182 Ks4 -8 .. 7 signed 4bit imm
1183 Ks3 -4 .. 3 signed 3bit imm
1184 Ku3 0 .. 7 unsigned 3bit imm
1185 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
1187 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1188 ((C) == 'J' ? (log2constp (VALUE)) \
1189 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
1190 : (C) == 'L' ? log2constp (~(VALUE)) \
1191 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
1192 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
1195 /*Constant Output Formats */
1196 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1197 ((C) == 'H' ? 1 : 0)
1199 #define EXTRA_CONSTRAINT(VALUE, D) \
1200 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1202 /* Evaluates to true if A and B are mac flags that can be used
1203 together in a single multiply insn. That is the case if they are
1204 both the same flag not involving M, or if one is a combination of
1205 the other with M. */
1206 #define MACFLAGS_MATCH_P(A, B) \
1208 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1209 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1210 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1211 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1213 /* Switch into a generic section. */
1214 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1216 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1217 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1219 typedef enum sections {
1225 typedef enum directives {
1234 #define TEXT_SECTION_ASM_OP ".text;"
1235 #define DATA_SECTION_ASM_OP ".data;"
1237 #define ASM_APP_ON ""
1238 #define ASM_APP_OFF ""
1240 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1241 do { fputs (".global ", FILE); \
1242 assemble_name (FILE, NAME); \
1244 fputc ('\n',FILE); \
1247 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1249 fputs (".type ", FILE); \
1250 assemble_name (FILE, NAME); \
1251 fputs (", STT_FUNC", FILE); \
1253 fputc ('\n',FILE); \
1254 ASM_OUTPUT_LABEL(FILE, NAME); \
1257 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1258 do { assemble_name (FILE, NAME); \
1259 fputs (":\n",FILE); \
1262 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1263 do { fprintf (FILE, "_%s", NAME); \
1266 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1267 do { char __buf[256]; \
1268 fprintf (FILE, "\t.dd\t"); \
1269 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1270 assemble_name (FILE, __buf); \
1271 fputc (';', FILE); \
1272 fputc ('\n', FILE); \
1275 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1276 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1278 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1281 fprintf (FILE, "\t.dd\t"); \
1282 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1283 assemble_name (FILE, __buf); \
1284 fputs (" - ", FILE); \
1285 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1286 assemble_name (FILE, __buf); \
1287 fputc (';', FILE); \
1288 fputc ('\n', FILE); \
1291 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1294 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1297 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1299 asm_output_skip (FILE, SIZE); \
1302 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1304 switch_to_section (data_section); \
1305 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1306 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1307 ASM_OUTPUT_LABEL (FILE, NAME); \
1308 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1309 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1312 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1314 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1315 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1317 #define ASM_COMMENT_START "//"
1319 #define FUNCTION_PROFILER(FILE, LABELNO) \
1321 fprintf (FILE, "\tCALL __mcount;\n"); \
1324 #undef NO_PROFILE_COUNTERS
1325 #define NO_PROFILE_COUNTERS 1
1327 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1328 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1330 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1331 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1333 /* This works for GAS and some other assemblers. */
1334 #define SET_ASM_OP ".set "
1336 /* DBX register number for a given compiler register number */
1337 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1339 #define SIZE_ASM_OP "\t.size\t"
1341 extern int splitting_for_sched;
1343 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1345 #endif /* _BFIN_CONFIG */