1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
30 typedef enum bfin_cpu_type
65 extern bfin_cpu_t bfin_cpu_type;
67 /* Value of -msi-revision= */
68 extern int bfin_si_revision;
70 extern unsigned int bfin_workarounds;
72 /* Print subsidiary information on the compiler version in use. */
73 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
75 /* Predefinition in the preprocessor for this target machine */
76 #ifndef TARGET_CPU_CPP_BUILTINS
77 #define TARGET_CPU_CPP_BUILTINS() \
80 builtin_define_std ("bfin"); \
81 builtin_define_std ("BFIN"); \
82 builtin_define ("__ADSPBLACKFIN__"); \
83 builtin_define ("__ADSPLPBLACKFIN__"); \
85 switch (bfin_cpu_type) \
87 case BFIN_CPU_BF512: \
88 builtin_define ("__ADSPBF512__"); \
89 builtin_define ("__ADSPBF51x__"); \
91 case BFIN_CPU_BF514: \
92 builtin_define ("__ADSPBF514__"); \
93 builtin_define ("__ADSPBF51x__"); \
95 case BFIN_CPU_BF516: \
96 builtin_define ("__ADSPBF516__"); \
97 builtin_define ("__ADSPBF51x__"); \
99 case BFIN_CPU_BF518: \
100 builtin_define ("__ADSPBF518__"); \
101 builtin_define ("__ADSPBF51x__"); \
103 case BFIN_CPU_BF522: \
104 builtin_define ("__ADSPBF522__"); \
105 builtin_define ("__ADSPBF52x__"); \
107 case BFIN_CPU_BF523: \
108 builtin_define ("__ADSPBF523__"); \
109 builtin_define ("__ADSPBF52x__"); \
111 case BFIN_CPU_BF524: \
112 builtin_define ("__ADSPBF524__"); \
113 builtin_define ("__ADSPBF52x__"); \
115 case BFIN_CPU_BF525: \
116 builtin_define ("__ADSPBF525__"); \
117 builtin_define ("__ADSPBF52x__"); \
119 case BFIN_CPU_BF526: \
120 builtin_define ("__ADSPBF526__"); \
121 builtin_define ("__ADSPBF52x__"); \
123 case BFIN_CPU_BF527: \
124 builtin_define ("__ADSPBF527__"); \
125 builtin_define ("__ADSPBF52x__"); \
127 case BFIN_CPU_BF531: \
128 builtin_define ("__ADSPBF531__"); \
130 case BFIN_CPU_BF532: \
131 builtin_define ("__ADSPBF532__"); \
133 case BFIN_CPU_BF533: \
134 builtin_define ("__ADSPBF533__"); \
136 case BFIN_CPU_BF534: \
137 builtin_define ("__ADSPBF534__"); \
139 case BFIN_CPU_BF536: \
140 builtin_define ("__ADSPBF536__"); \
142 case BFIN_CPU_BF537: \
143 builtin_define ("__ADSPBF537__"); \
145 case BFIN_CPU_BF538: \
146 builtin_define ("__ADSPBF538__"); \
148 case BFIN_CPU_BF539: \
149 builtin_define ("__ADSPBF539__"); \
151 case BFIN_CPU_BF542M: \
152 builtin_define ("__ADSPBF542M__"); \
153 case BFIN_CPU_BF542: \
154 builtin_define ("__ADSPBF542__"); \
155 builtin_define ("__ADSPBF54x__"); \
157 case BFIN_CPU_BF544M: \
158 builtin_define ("__ADSPBF544M__"); \
159 case BFIN_CPU_BF544: \
160 builtin_define ("__ADSPBF544__"); \
161 builtin_define ("__ADSPBF54x__"); \
163 case BFIN_CPU_BF547M: \
164 builtin_define ("__ADSPBF547M__"); \
165 case BFIN_CPU_BF547: \
166 builtin_define ("__ADSPBF547__"); \
167 builtin_define ("__ADSPBF54x__"); \
169 case BFIN_CPU_BF548M: \
170 builtin_define ("__ADSPBF548M__"); \
171 case BFIN_CPU_BF548: \
172 builtin_define ("__ADSPBF548__"); \
173 builtin_define ("__ADSPBF54x__"); \
175 case BFIN_CPU_BF549M: \
176 builtin_define ("__ADSPBF549M__"); \
177 case BFIN_CPU_BF549: \
178 builtin_define ("__ADSPBF549__"); \
179 builtin_define ("__ADSPBF54x__"); \
181 case BFIN_CPU_BF561: \
182 builtin_define ("__ADSPBF561__"); \
186 if (bfin_si_revision != -1) \
188 /* space of 0xnnnn and a NUL */ \
189 char *buf = XALLOCAVEC (char, 7); \
191 sprintf (buf, "0x%04x", bfin_si_revision); \
192 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
195 if (bfin_workarounds) \
196 builtin_define ("__WORKAROUNDS_ENABLED"); \
197 if (ENABLE_WA_SPECULATIVE_LOADS) \
198 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
199 if (ENABLE_WA_SPECULATIVE_SYNCS) \
200 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
201 if (ENABLE_WA_INDIRECT_CALLS) \
202 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
203 if (ENABLE_WA_RETS) \
204 builtin_define ("__WORKAROUND_RETS"); \
208 builtin_define ("__BFIN_FDPIC__"); \
209 builtin_define ("__FDPIC__"); \
211 if (TARGET_ID_SHARED_LIBRARY \
212 && !TARGET_SEP_DATA) \
213 builtin_define ("__ID_SHARED_LIB__"); \
214 if (flag_no_builtin) \
215 builtin_define ("__NO_BUILTIN"); \
216 if (TARGET_MULTICORE) \
217 builtin_define ("__BFIN_MULTICORE"); \
219 builtin_define ("__BFIN_COREA"); \
221 builtin_define ("__BFIN_COREB"); \
223 builtin_define ("__BFIN_SDRAM"); \
228 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
229 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
230 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
231 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
233 #ifndef SUBTARGET_DRIVER_SELF_SPECS
234 # define SUBTARGET_DRIVER_SELF_SPECS
237 #define LINK_GCC_C_SEQUENCE_SPEC "\
238 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
241 /* A C string constant that tells the GCC driver program options to pass to
242 the assembler. It can also specify how to translate options you give to GNU
243 CC into options for GCC to pass to the assembler. See the file `sun3.h'
244 for an example of this.
246 Do not define this macro if it does not need to do anything.
248 Defined in svr4.h. */
251 %{v} %{n} %{T} %{Ym,*} %{Yd,*} \
252 %{mno-fdpic:-mnopic} %{mfdpic}"
257 %{mfdpic:-melf32bfinfd -z text} \
258 %{static:-dn -Bstatic} \
259 %{shared:-G -Bdynamic} \
260 %{symbolic:-Bsymbolic} \
263 -init __init -fini __fini "
265 /* Generate DSP instructions, like DSP halfword loads */
266 #define TARGET_DSP (1)
268 #define TARGET_DEFAULT 0
270 /* Maximum number of library ids we permit */
271 #define MAX_LIBRARY_ID 255
273 extern const char *bfin_library_id_string;
275 #define FUNCTION_MODE SImode
278 /* store-condition-codes instructions store 0 for false
279 This is the value stored for true. */
280 #define STORE_FLAG_VALUE 1
282 /* Define this if pushing a word on the stack
283 makes the stack pointer a smaller address. */
284 #define STACK_GROWS_DOWNWARD
286 #define STACK_PUSH_CODE PRE_DEC
288 /* Define this to nonzero if the nominal address of the stack frame
289 is at the high-address end of the local variables;
290 that is, each additional local variable allocated
291 goes at a more negative offset in the frame. */
292 #define FRAME_GROWS_DOWNWARD 1
294 /* We define a dummy ARGP register; the parameters start at offset 0 from
296 #define FIRST_PARM_OFFSET(DECL) 0
298 /* Offset within stack frame to start allocating local variables at.
299 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
300 first local allocated. Otherwise, it is the offset to the BEGINNING
301 of the first local allocated. */
302 #define STARTING_FRAME_OFFSET 0
304 /* Register to use for pushing function arguments. */
305 #define STACK_POINTER_REGNUM REG_P6
307 /* Base register for access to local variables of the function. */
308 #define FRAME_POINTER_REGNUM REG_P7
310 /* A dummy register that will be eliminated to either FP or SP. */
311 #define ARG_POINTER_REGNUM REG_ARGP
313 /* `PIC_OFFSET_TABLE_REGNUM'
314 The register number of the register used to address a table of
315 static data addresses in memory. In some cases this register is
316 defined by a processor's "application binary interface" (ABI).
317 When this macro is defined, RTL is generated for this register
318 once, as with the stack pointer and frame pointer registers. If
319 this macro is not defined, it is up to the machine-dependent files
320 to allocate such a register (if necessary). */
321 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
323 #define FDPIC_FPTR_REGNO REG_P1
324 #define FDPIC_REGNO REG_P3
325 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
327 /* A static chain register for nested functions. We need to use a
328 call-clobbered register for this. */
329 #define STATIC_CHAIN_REGNUM REG_P2
331 /* Define this if functions should assume that stack space has been
332 allocated for arguments even when their values are passed in
335 The value of this macro is the size, in bytes, of the area reserved for
336 arguments passed in registers.
338 This space can either be allocated by the caller or be a part of the
339 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
341 #define FIXED_STACK_AREA 12
342 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
344 /* Define this if the above stack space is to be considered part of the
345 * space allocated by the caller. */
346 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
348 /* Define this if the maximum size of all the outgoing args is to be
349 accumulated and pushed during the prologue. The amount can be
350 found in the variable crtl->outgoing_args_size. */
351 #define ACCUMULATE_OUTGOING_ARGS 1
353 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
355 /* If defined, a C expression to compute the alignment for a local
356 variable. TYPE is the data type, and ALIGN is the alignment that
357 the object would ordinarily have. The value of this macro is used
358 instead of that alignment to align the object.
360 If this macro is not defined, then ALIGN is used.
362 One use of this macro is to increase alignment of medium-size
363 data to make it all fit in fewer cache lines. */
365 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
367 /* Make strings word-aligned so strcpy from constants will be faster. */
368 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
369 (TREE_CODE (EXP) == STRING_CST \
370 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
372 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
374 /* Definitions for register eliminations.
376 This is an array of structures. Each structure initializes one pair
377 of eliminable registers. The "from" register number is given first,
378 followed by "to". Eliminations of the same "from" register are listed
379 in order of preference.
381 There are two registers that can always be eliminated on the i386.
382 The frame pointer and the arg pointer can be replaced by either the
383 hard frame pointer or to the stack pointer, depending upon the
384 circumstances. The hard frame pointer is not used before reload and
385 so it is not eligible for elimination. */
387 #define ELIMINABLE_REGS \
388 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
389 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
390 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
392 /* Define the offset between two registers, one to be eliminated, and the other
393 its replacement, at the start of a routine. */
395 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
396 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
398 /* This processor has
399 8 data register for doing arithmetic
400 8 pointer register for doing addressing, including
403 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
404 1 condition code flag register CC
405 5 return address registers RETS/I/X/N/E
406 1 arithmetic status register (ASTAT). */
408 #define FIRST_PSEUDO_REGISTER 50
410 #define D_REGNO_P(X) ((X) <= REG_R7)
411 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
412 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
413 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
414 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
415 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
416 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
417 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
418 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
420 #define REGISTER_NAMES { \
421 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
422 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
423 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
424 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
427 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
429 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
432 #define SHORT_REGISTER_NAMES { \
433 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
434 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
435 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
436 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
438 #define HIGH_REGISTER_NAMES { \
439 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
440 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
441 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
442 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
444 #define DREGS_PAIR_NAMES { \
445 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
447 #define BYTE_REGISTER_NAMES { \
448 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
451 /* 1 for registers that have pervasive standard uses
452 and are not available for the register allocator. */
454 #define FIXED_REGISTERS \
455 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
456 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
457 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
458 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
459 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
460 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
465 /* 1 for registers not available across function calls.
466 These must include the FIXED_REGISTERS and also any
467 registers that can be used without being saved.
468 The latter must include the registers where values are returned
469 and the register where structure-value addresses are passed.
470 Aside from that, you can include as many other registers as you like. */
472 #define CALL_USED_REGISTERS \
473 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
474 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
475 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
476 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
477 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
483 /* Order in which to allocate registers. Each register must be
484 listed once, even those in FIXED_REGISTERS. List frame pointer
485 late and fixed registers last. Note that, in general, we prefer
486 registers listed in CALL_USED_REGISTERS, keeping the others
487 available for storage of persistent values. */
489 #define REG_ALLOC_ORDER \
490 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
491 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
493 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
494 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
495 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
496 REG_ASTAT, REG_SEQSTAT, REG_USP, \
498 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
501 /* Define the classes of registers for register constraints in the
502 machine description. Also define ranges of constants.
504 One of the classes must always be named ALL_REGS and include all hard regs.
505 If there is more than one class, another class must be named NO_REGS
506 and contain no registers.
508 The name GENERAL_REGS must be the name of a class (or an alias for
509 another name such as ALL_REGS). This is the class of registers
510 that is allowed by "g" or "r" in a register constraint.
511 Also, registers outside this class are allocated only when
512 instructions express preferences for them.
514 The classes must be numbered in nondecreasing order; that is,
515 a larger-numbered class must never be contained completely
516 in a smaller-numbered class.
518 For any two classes, it is very desirable that there be another
519 class that represents their union. */
529 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
559 ALL_REGS, LIM_REG_CLASSES
562 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
564 #define GENERAL_REGS DPREGS
566 /* Give names of register classes as strings for dump file. */
568 #define REG_CLASS_NAMES \
606 /* An initializer containing the contents of the register classes, as integers
607 which are bit masks. The Nth integer specifies the contents of class N.
608 The way the integer MASK is interpreted is that register R is in the class
609 if `MASK & (1 << R)' is 1.
611 When the machine has more than 32 registers, an integer does not suffice.
612 Then the integers are replaced by sub-initializers, braced groupings
613 containing several integers. Each sub-initializer must be suitable as an
614 initializer for the type `HARD_REG_SET' which is defined in
617 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
618 MOST_REGS as the union of DPREGS and DAGREGS. */
620 #define REG_CLASS_CONTENTS \
622 { { 0x00000000, 0 }, /* NO_REGS */ \
623 { 0x000f0000, 0 }, /* IREGS */ \
624 { 0x00f00000, 0 }, /* BREGS */ \
625 { 0x0f000000, 0 }, /* LREGS */ \
626 { 0xf0000000, 0 }, /* MREGS */ \
627 { 0x0fff0000, 0 }, /* CIRCREGS */ \
628 { 0xffff0000, 0 }, /* DAGREGS */ \
629 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
630 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
631 { 0x00000000, 0x3 }, /* AREGS */ \
632 { 0x00000000, 0x4 }, /* CCREGS */ \
633 { 0x00000055, 0 }, /* EVEN_DREGS */ \
634 { 0x000000aa, 0 }, /* ODD_DREGS */ \
635 { 0x00000001, 0 }, /* D0REGS */ \
636 { 0x00000002, 0 }, /* D1REGS */ \
637 { 0x00000004, 0 }, /* D2REGS */ \
638 { 0x00000008, 0 }, /* D3REGS */ \
639 { 0x00000010, 0 }, /* D4REGS */ \
640 { 0x00000020, 0 }, /* D5REGS */ \
641 { 0x00000040, 0 }, /* D6REGS */ \
642 { 0x00000080, 0 }, /* D7REGS */ \
643 { 0x000000ff, 0 }, /* DREGS */ \
644 { 0x00000100, 0x000 }, /* P0REGS */ \
645 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
646 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
647 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
648 { 0x0000ff00, 0x800 }, /* PREGS */ \
649 { 0x000fff00, 0x800 }, /* IPREGS */ \
650 { 0x0000ffff, 0x800 }, /* DPREGS */ \
651 { 0xffffffff, 0x800 }, /* MOST_REGS */\
652 { 0x00000000, 0x3000 }, /* LT_REGS */\
653 { 0x00000000, 0xc000 }, /* LC_REGS */\
654 { 0x00000000, 0x30000 }, /* LB_REGS */\
655 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
656 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
657 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
659 #define IREG_POSSIBLE_P(OUTER) \
660 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
661 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
662 || (OUTER) == MEM || (OUTER) == ADDRESS)
664 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
665 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
667 #define INDEX_REG_CLASS PREGS
669 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
670 (P_REGNO_P (X) || (X) == REG_ARGP \
671 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
674 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
675 ((X) >= FIRST_PSEUDO_REGISTER \
676 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
679 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
680 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
682 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
683 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
686 #define REGNO_OK_FOR_INDEX_P(X) 0
688 /* The same information, inverted:
689 Return the class number of the smallest class containing
690 reg number REGNO. This could be a conditional expression
691 or could index an array. */
693 #define REGNO_REG_CLASS(REGNO) \
694 ((REGNO) == REG_R0 ? D0REGS \
695 : (REGNO) == REG_R1 ? D1REGS \
696 : (REGNO) == REG_R2 ? D2REGS \
697 : (REGNO) == REG_R3 ? D3REGS \
698 : (REGNO) == REG_R4 ? D4REGS \
699 : (REGNO) == REG_R5 ? D5REGS \
700 : (REGNO) == REG_R6 ? D6REGS \
701 : (REGNO) == REG_R7 ? D7REGS \
702 : (REGNO) == REG_P0 ? P0REGS \
703 : (REGNO) < REG_I0 ? PREGS \
704 : (REGNO) == REG_ARGP ? PREGS \
705 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
706 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
707 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
708 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
709 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
710 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
711 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
712 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
713 : (REGNO) == REG_CC ? CCREGS \
714 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
717 /* The following macro defines cover classes for Integrated Register
718 Allocator. Cover classes is a set of non-intersected register
719 classes covering all hard registers used for register allocation
720 purpose. Any move between two registers of a cover class should be
721 cheaper than load or store of the registers. The macro value is
722 array of register classes with LIM_REG_CLASSES used as the end
725 #define IRA_COVER_CLASSES \
727 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
730 /* When this hook returns true for MODE, the compiler allows
731 registers explicitly used in the rtl to be used as spill registers
732 but prevents the compiler from extending the lifetime of these
734 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
736 /* Do not allow to store a value in REG_CC for any mode */
737 /* Do not allow to store value in pregs if mode is not SI*/
738 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
740 /* Return the maximum number of consecutive registers
741 needed to represent mode MODE in a register of class CLASS. */
742 #define CLASS_MAX_NREGS(CLASS, MODE) \
743 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
744 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
746 #define HARD_REGNO_NREGS(REGNO, MODE) \
747 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
748 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
749 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
751 /* A C expression that is nonzero if hard register TO can be
752 considered for use as a rename register for FROM register */
753 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
755 /* A C expression that is nonzero if it is desirable to choose
756 register allocation so as to avoid move instructions between a
757 value of mode MODE1 and a value of mode MODE2.
759 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
760 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
761 MODE2)' must be zero. */
762 #define MODES_TIEABLE_P(MODE1, MODE2) \
763 ((MODE1) == (MODE2) \
764 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
765 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
766 && (GET_MODE_CLASS (MODE2) == MODE_INT \
767 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
768 && (MODE1) != BImode && (MODE2) != BImode \
769 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
770 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
772 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
773 A C expression that places additional restrictions on the register
774 class to use when it is necessary to copy value X into a register
775 in class CLASS. The value is a register class; perhaps CLASS, or
776 perhaps another, smaller class. */
777 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
778 (GET_CODE (X) == POST_INC \
779 || GET_CODE (X) == POST_DEC \
780 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
782 /* Function Calling Conventions. */
784 /* The type of the current function; normal functions are of type
787 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
789 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
791 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
793 /* Flags for the call/call_value rtl operations set up by function_arg */
794 #define CALL_NORMAL 0x00000000 /* no special processing */
795 #define CALL_LONG 0x00000001 /* always call indirect */
796 #define CALL_SHORT 0x00000002 /* always call by symbol */
799 int words; /* # words passed so far */
800 int nregs; /* # registers available for passing */
801 int *arg_regs; /* array of register -1 terminated */
802 int call_cookie; /* Do special things for this call */
805 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
808 /* Initialize a variable CUM of type CUMULATIVE_ARGS
809 for a call to a function whose data type is FNTYPE.
810 For a library call, FNTYPE is 0. */
811 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
812 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
814 /* Define how to find the value returned by a function.
815 VALTYPE is the data type of the value (as a tree).
816 If the precise function being called is known, FUNC is its FUNCTION_DECL;
817 otherwise, FUNC is 0.
820 #define VALUE_REGNO(MODE) (REG_R0)
822 #define FUNCTION_VALUE(VALTYPE, FUNC) \
823 gen_rtx_REG (TYPE_MODE (VALTYPE), \
824 VALUE_REGNO(TYPE_MODE(VALTYPE)))
826 /* Define how to find the value returned by a library function
827 assuming the value has mode MODE. */
829 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
831 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
833 #define DEFAULT_PCC_STRUCT_RETURN 0
835 /* Before the prologue, the return address is in the RETS register. */
836 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
838 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
840 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
842 /* Call instructions don't modify the stack pointer on the Blackfin. */
843 #define INCOMING_FRAME_SP_OFFSET 0
845 /* Describe how we implement __builtin_eh_return. */
846 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
847 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
848 #define EH_RETURN_HANDLER_RTX \
849 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
851 /* Addressing Modes */
853 /* Nonzero if the constant value X is a legitimate general operand.
854 symbol_ref are not legitimate and will be put into constant pool.
855 See force_const_mem().
856 If -mno-pool, all constants are legitimate.
858 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
860 /* A number, the maximum number of registers that can appear in a
861 valid memory address. Note that it is up to you to specify a
862 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
863 would ever accept. */
864 #define MAX_REGS_PER_ADDRESS 1
866 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
867 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
869 #define HAVE_POST_INCREMENT 1
870 #define HAVE_POST_DECREMENT 1
871 #define HAVE_PRE_DECREMENT 1
873 /* `LEGITIMATE_PIC_OPERAND_P (X)'
874 A C expression that is nonzero if X is a legitimate immediate
875 operand on the target machine when generating position independent
876 code. You can assume that X satisfies `CONSTANT_P', so you need
877 not check this. You can also assume FLAG_PIC is true, so you need
878 not check it either. You need not define this macro if all
879 constants (including `SYMBOL_REF') can be immediate operands when
880 generating position independent code. */
881 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
883 #define SYMBOLIC_CONST(X) \
884 (GET_CODE (X) == SYMBOL_REF \
885 || GET_CODE (X) == LABEL_REF \
886 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
888 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
890 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
891 is done just by pretending it is already truncated. */
892 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
894 /* Max number of bytes we can move from memory to memory
895 in one reasonably fast instruction. */
896 #define MOVE_MAX UNITS_PER_WORD
898 /* If a memory-to-memory move would take MOVE_RATIO or more simple
899 move-instruction pairs, we will do a movmem or libcall instead. */
901 #define MOVE_RATIO(speed) 5
903 /* STORAGE LAYOUT: target machine storage layout
904 Define this macro as a C expression which is nonzero if accessing
905 less than a word of memory (i.e. a `char' or a `short') is no
906 faster than accessing a word of memory, i.e., if such access
907 require more than one instruction or if there is no difference in
908 cost between byte and (aligned) word loads.
910 When this macro is not defined, the compiler will access a field by
911 finding the smallest containing object; when it is defined, a
912 fullword load will be used if alignment permits. Unless bytes
913 accesses are faster than word accesses, using word accesses is
914 preferable since it may eliminate subsequent memory access if
915 subsequent accesses occur to other fields in the same word of the
916 structure, but to different bytes. */
917 #define SLOW_BYTE_ACCESS 0
918 #define SLOW_SHORT_ACCESS 0
920 /* Define this if most significant bit is lowest numbered
921 in instructions that operate on numbered bit-fields. */
922 #define BITS_BIG_ENDIAN 0
924 /* Define this if most significant byte of a word is the lowest numbered.
925 We can't access bytes but if we could we would in the Big Endian order. */
926 #define BYTES_BIG_ENDIAN 0
928 /* Define this if most significant word of a multiword number is numbered. */
929 #define WORDS_BIG_ENDIAN 0
931 /* number of bits in an addressable storage unit */
932 #define BITS_PER_UNIT 8
934 /* Width in bits of a "word", which is the contents of a machine register.
935 Note that this is not necessarily the width of data type `int';
936 if using 16-bit ints on a 68000, this would still be 32.
937 But on a machine with 16-bit registers, this would be 16. */
938 #define BITS_PER_WORD 32
940 /* Width of a word, in units (bytes). */
941 #define UNITS_PER_WORD 4
943 /* Width in bits of a pointer.
944 See also the macro `Pmode1' defined below. */
945 #define POINTER_SIZE 32
947 /* Allocation boundary (in *bits*) for storing pointers in memory. */
948 #define POINTER_BOUNDARY 32
950 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
951 #define PARM_BOUNDARY 32
953 /* Boundary (in *bits*) on which stack pointer should be aligned. */
954 #define STACK_BOUNDARY 32
956 /* Allocation boundary (in *bits*) for the code of a function. */
957 #define FUNCTION_BOUNDARY 32
959 /* Alignment of field after `int : 0' in a structure. */
960 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
962 /* No data type wants to be aligned rounder than this. */
963 #define BIGGEST_ALIGNMENT 32
965 /* Define this if move instructions will actually fail to work
966 when given unaligned data. */
967 #define STRICT_ALIGNMENT 1
969 /* (shell-command "rm c-decl.o stor-layout.o")
970 * never define PCC_BITFIELD_TYPE_MATTERS
971 * really cause some alignment problem
974 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
977 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
981 /* what is the 'type' of size_t */
982 #define SIZE_TYPE "long unsigned int"
984 /* Define this as 1 if `char' should by default be signed; else as 0. */
985 #define DEFAULT_SIGNED_CHAR 1
986 #define FLOAT_TYPE_SIZE BITS_PER_WORD
987 #define SHORT_TYPE_SIZE 16
988 #define CHAR_TYPE_SIZE 8
989 #define INT_TYPE_SIZE 32
990 #define LONG_TYPE_SIZE 32
991 #define LONG_LONG_TYPE_SIZE 64
993 /* Note: Fix this to depend on target switch. -- lev */
995 /* Note: Try to implement double and force long double. -- tonyko
996 * #define __DOUBLES_ARE_FLOATS__
997 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
998 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
999 * #define DOUBLES_ARE_FLOATS 1
1002 #define DOUBLE_TYPE_SIZE 64
1003 #define LONG_DOUBLE_TYPE_SIZE 64
1005 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1006 A macro to update M and UNSIGNEDP when an object whose type is
1007 TYPE and which has the specified mode and signedness is to be
1008 stored in a register. This macro is only called when TYPE is a
1011 On most RISC machines, which only have operations that operate on
1012 a full register, define this macro to set M to `word_mode' if M is
1013 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1014 only integer modes should be widened because wider-precision
1015 floating-point operations are usually more expensive than their
1016 narrower counterparts.
1018 For most machines, the macro definition does not change UNSIGNEDP.
1019 However, some machines, have instructions that preferentially
1020 handle either signed or unsigned quantities of certain modes. For
1021 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1022 instructions sign-extend the result to 64 bits. On such machines,
1023 set UNSIGNEDP according to which kind of extension is more
1026 Do not define this macro if it would never modify M.*/
1028 #define BFIN_PROMOTE_MODE_P(MODE) \
1029 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1030 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1032 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1033 if (BFIN_PROMOTE_MODE_P(MODE)) \
1035 if (MODE == QImode) \
1037 else if (MODE == HImode) \
1042 /* Describing Relative Costs of Operations */
1044 /* Do not put function addr into constant pool */
1045 #define NO_FUNCTION_CSE 1
1047 /* A C expression for the cost of moving data from a register in class FROM to
1048 one in class TO. The classes are expressed using the enumeration values
1049 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1050 interpreted relative to that.
1052 It is not required that the cost always equal 2 when FROM is the same as TO;
1053 on some machines it is expensive to move between registers if they are not
1054 general registers. */
1056 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1057 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1059 /* A C expression for the cost of moving data of mode M between a
1060 register and memory. A value of 2 is the default; this cost is
1061 relative to those in `REGISTER_MOVE_COST'.
1063 If moving between registers and memory is more expensive than
1064 between two registers, you should define this macro to express the
1067 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1068 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1070 /* Specify the machine mode that this machine uses
1071 for the index in the tablejump instruction. */
1072 #define CASE_VECTOR_MODE SImode
1074 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1076 /* Define if operations between registers always perform the operation
1077 on the full register even if a narrower mode is specified.
1078 #define WORD_REGISTER_OPERATIONS
1081 /* Evaluates to true if A and B are mac flags that can be used
1082 together in a single multiply insn. That is the case if they are
1083 both the same flag not involving M, or if one is a combination of
1084 the other with M. */
1085 #define MACFLAGS_MATCH_P(A, B) \
1087 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1088 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1089 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1090 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1092 /* Switch into a generic section. */
1093 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1095 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1096 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1098 typedef enum sections {
1104 typedef enum directives {
1113 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1115 || ((C) == '|' && (STR)[1] == '|'))
1117 #define TEXT_SECTION_ASM_OP ".text;"
1118 #define DATA_SECTION_ASM_OP ".data;"
1120 #define ASM_APP_ON ""
1121 #define ASM_APP_OFF ""
1123 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1124 do { fputs (".global ", FILE); \
1125 assemble_name (FILE, NAME); \
1127 fputc ('\n',FILE); \
1130 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1132 fputs (".type ", FILE); \
1133 assemble_name (FILE, NAME); \
1134 fputs (", STT_FUNC", FILE); \
1136 fputc ('\n',FILE); \
1137 ASM_OUTPUT_LABEL(FILE, NAME); \
1140 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1141 do { assemble_name (FILE, NAME); \
1142 fputs (":\n",FILE); \
1145 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1146 do { fprintf (FILE, "_%s", NAME); \
1149 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1150 do { char __buf[256]; \
1151 fprintf (FILE, "\t.dd\t"); \
1152 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1153 assemble_name (FILE, __buf); \
1154 fputc (';', FILE); \
1155 fputc ('\n', FILE); \
1158 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1159 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1161 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1164 fprintf (FILE, "\t.dd\t"); \
1165 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1166 assemble_name (FILE, __buf); \
1167 fputs (" - ", FILE); \
1168 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1169 assemble_name (FILE, __buf); \
1170 fputc (';', FILE); \
1171 fputc ('\n', FILE); \
1174 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1177 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1180 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1182 asm_output_skip (FILE, SIZE); \
1185 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1187 switch_to_section (data_section); \
1188 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1189 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1190 ASM_OUTPUT_LABEL (FILE, NAME); \
1191 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1192 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1195 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1197 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1198 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1200 #define ASM_COMMENT_START "//"
1202 #define FUNCTION_PROFILER(FILE, LABELNO) \
1204 fprintf (FILE, "\tCALL __mcount;\n"); \
1207 #undef NO_PROFILE_COUNTERS
1208 #define NO_PROFILE_COUNTERS 1
1210 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1211 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1213 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1215 /* This works for GAS and some other assemblers. */
1216 #define SET_ASM_OP ".set "
1218 /* DBX register number for a given compiler register number */
1219 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1221 #define SIZE_ASM_OP "\t.size\t"
1223 extern int splitting_for_sched, splitting_loops;
1225 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1227 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1228 #define TARGET_SUPPORTS_SYNC_CALLS 0
1231 #endif /* _BFIN_CONFIG */