1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
30 typedef enum bfin_cpu_type
65 extern bfin_cpu_t bfin_cpu_type;
67 /* Value of -msi-revision= */
68 extern int bfin_si_revision;
70 extern unsigned int bfin_workarounds;
72 /* Print subsidiary information on the compiler version in use. */
73 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
75 /* Predefinition in the preprocessor for this target machine */
76 #ifndef TARGET_CPU_CPP_BUILTINS
77 #define TARGET_CPU_CPP_BUILTINS() \
80 builtin_define_std ("bfin"); \
81 builtin_define_std ("BFIN"); \
82 builtin_define ("__ADSPBLACKFIN__"); \
83 builtin_define ("__ADSPLPBLACKFIN__"); \
85 switch (bfin_cpu_type) \
87 case BFIN_CPU_BF512: \
88 builtin_define ("__ADSPBF512__"); \
89 builtin_define ("__ADSPBF51x__"); \
91 case BFIN_CPU_BF514: \
92 builtin_define ("__ADSPBF514__"); \
93 builtin_define ("__ADSPBF51x__"); \
95 case BFIN_CPU_BF516: \
96 builtin_define ("__ADSPBF516__"); \
97 builtin_define ("__ADSPBF51x__"); \
99 case BFIN_CPU_BF518: \
100 builtin_define ("__ADSPBF518__"); \
101 builtin_define ("__ADSPBF51x__"); \
103 case BFIN_CPU_BF522: \
104 builtin_define ("__ADSPBF522__"); \
105 builtin_define ("__ADSPBF52x__"); \
107 case BFIN_CPU_BF523: \
108 builtin_define ("__ADSPBF523__"); \
109 builtin_define ("__ADSPBF52x__"); \
111 case BFIN_CPU_BF524: \
112 builtin_define ("__ADSPBF524__"); \
113 builtin_define ("__ADSPBF52x__"); \
115 case BFIN_CPU_BF525: \
116 builtin_define ("__ADSPBF525__"); \
117 builtin_define ("__ADSPBF52x__"); \
119 case BFIN_CPU_BF526: \
120 builtin_define ("__ADSPBF526__"); \
121 builtin_define ("__ADSPBF52x__"); \
123 case BFIN_CPU_BF527: \
124 builtin_define ("__ADSPBF527__"); \
125 builtin_define ("__ADSPBF52x__"); \
127 case BFIN_CPU_BF531: \
128 builtin_define ("__ADSPBF531__"); \
130 case BFIN_CPU_BF532: \
131 builtin_define ("__ADSPBF532__"); \
133 case BFIN_CPU_BF533: \
134 builtin_define ("__ADSPBF533__"); \
136 case BFIN_CPU_BF534: \
137 builtin_define ("__ADSPBF534__"); \
139 case BFIN_CPU_BF536: \
140 builtin_define ("__ADSPBF536__"); \
142 case BFIN_CPU_BF537: \
143 builtin_define ("__ADSPBF537__"); \
145 case BFIN_CPU_BF538: \
146 builtin_define ("__ADSPBF538__"); \
148 case BFIN_CPU_BF539: \
149 builtin_define ("__ADSPBF539__"); \
151 case BFIN_CPU_BF542M: \
152 builtin_define ("__ADSPBF542M__"); \
153 case BFIN_CPU_BF542: \
154 builtin_define ("__ADSPBF542__"); \
155 builtin_define ("__ADSPBF54x__"); \
157 case BFIN_CPU_BF544M: \
158 builtin_define ("__ADSPBF544M__"); \
159 case BFIN_CPU_BF544: \
160 builtin_define ("__ADSPBF544__"); \
161 builtin_define ("__ADSPBF54x__"); \
163 case BFIN_CPU_BF547M: \
164 builtin_define ("__ADSPBF547M__"); \
165 case BFIN_CPU_BF547: \
166 builtin_define ("__ADSPBF547__"); \
167 builtin_define ("__ADSPBF54x__"); \
169 case BFIN_CPU_BF548M: \
170 builtin_define ("__ADSPBF548M__"); \
171 case BFIN_CPU_BF548: \
172 builtin_define ("__ADSPBF548__"); \
173 builtin_define ("__ADSPBF54x__"); \
175 case BFIN_CPU_BF549M: \
176 builtin_define ("__ADSPBF549M__"); \
177 case BFIN_CPU_BF549: \
178 builtin_define ("__ADSPBF549__"); \
179 builtin_define ("__ADSPBF54x__"); \
181 case BFIN_CPU_BF561: \
182 builtin_define ("__ADSPBF561__"); \
186 if (bfin_si_revision != -1) \
188 /* space of 0xnnnn and a NUL */ \
189 char *buf = XALLOCAVEC (char, 7); \
191 sprintf (buf, "0x%04x", bfin_si_revision); \
192 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
195 if (bfin_workarounds) \
196 builtin_define ("__WORKAROUNDS_ENABLED"); \
197 if (ENABLE_WA_SPECULATIVE_LOADS) \
198 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
199 if (ENABLE_WA_SPECULATIVE_SYNCS) \
200 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
201 if (ENABLE_WA_INDIRECT_CALLS) \
202 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
203 if (ENABLE_WA_RETS) \
204 builtin_define ("__WORKAROUND_RETS"); \
208 builtin_define ("__BFIN_FDPIC__"); \
209 builtin_define ("__FDPIC__"); \
211 if (TARGET_ID_SHARED_LIBRARY \
212 && !TARGET_SEP_DATA) \
213 builtin_define ("__ID_SHARED_LIB__"); \
214 if (flag_no_builtin) \
215 builtin_define ("__NO_BUILTIN"); \
216 if (TARGET_MULTICORE) \
217 builtin_define ("__BFIN_MULTICORE"); \
219 builtin_define ("__BFIN_COREA"); \
221 builtin_define ("__BFIN_COREB"); \
223 builtin_define ("__BFIN_SDRAM"); \
228 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
229 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
230 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
231 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
233 #ifndef SUBTARGET_DRIVER_SELF_SPECS
234 # define SUBTARGET_DRIVER_SELF_SPECS
237 #define LINK_GCC_C_SEQUENCE_SPEC "\
238 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
241 /* A C string constant that tells the GCC driver program options to pass to
242 the assembler. It can also specify how to translate options you give to GNU
243 CC into options for GCC to pass to the assembler. See the file `sun3.h'
244 for an example of this.
246 Do not define this macro if it does not need to do anything.
248 Defined in svr4.h. */
251 %{v} %{Ym,*} %{Yd,*} \
252 %{mno-fdpic:-mnopic} %{mfdpic}"
256 %{mfdpic:-melf32bfinfd -z text} \
257 %{static:-dn -Bstatic} \
258 %{shared:-G -Bdynamic} \
259 %{symbolic:-Bsymbolic} \
262 -init __init -fini __fini "
264 /* Generate DSP instructions, like DSP halfword loads */
265 #define TARGET_DSP (1)
267 #define TARGET_DEFAULT 0
269 /* Maximum number of library ids we permit */
270 #define MAX_LIBRARY_ID 255
272 extern const char *bfin_library_id_string;
274 #define FUNCTION_MODE SImode
277 /* store-condition-codes instructions store 0 for false
278 This is the value stored for true. */
279 #define STORE_FLAG_VALUE 1
281 /* Define this if pushing a word on the stack
282 makes the stack pointer a smaller address. */
283 #define STACK_GROWS_DOWNWARD
285 #define STACK_PUSH_CODE PRE_DEC
287 /* Define this to nonzero if the nominal address of the stack frame
288 is at the high-address end of the local variables;
289 that is, each additional local variable allocated
290 goes at a more negative offset in the frame. */
291 #define FRAME_GROWS_DOWNWARD 1
293 /* We define a dummy ARGP register; the parameters start at offset 0 from
295 #define FIRST_PARM_OFFSET(DECL) 0
297 /* Offset within stack frame to start allocating local variables at.
298 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
299 first local allocated. Otherwise, it is the offset to the BEGINNING
300 of the first local allocated. */
301 #define STARTING_FRAME_OFFSET 0
303 /* Register to use for pushing function arguments. */
304 #define STACK_POINTER_REGNUM REG_P6
306 /* Base register for access to local variables of the function. */
307 #define FRAME_POINTER_REGNUM REG_P7
309 /* A dummy register that will be eliminated to either FP or SP. */
310 #define ARG_POINTER_REGNUM REG_ARGP
312 /* `PIC_OFFSET_TABLE_REGNUM'
313 The register number of the register used to address a table of
314 static data addresses in memory. In some cases this register is
315 defined by a processor's "application binary interface" (ABI).
316 When this macro is defined, RTL is generated for this register
317 once, as with the stack pointer and frame pointer registers. If
318 this macro is not defined, it is up to the machine-dependent files
319 to allocate such a register (if necessary). */
320 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
322 #define FDPIC_FPTR_REGNO REG_P1
323 #define FDPIC_REGNO REG_P3
324 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
326 /* A static chain register for nested functions. We need to use a
327 call-clobbered register for this. */
328 #define STATIC_CHAIN_REGNUM REG_P2
330 /* Define this if functions should assume that stack space has been
331 allocated for arguments even when their values are passed in
334 The value of this macro is the size, in bytes, of the area reserved for
335 arguments passed in registers.
337 This space can either be allocated by the caller or be a part of the
338 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
340 #define FIXED_STACK_AREA 12
341 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
343 /* Define this if the above stack space is to be considered part of the
344 * space allocated by the caller. */
345 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
347 /* Define this if the maximum size of all the outgoing args is to be
348 accumulated and pushed during the prologue. The amount can be
349 found in the variable crtl->outgoing_args_size. */
350 #define ACCUMULATE_OUTGOING_ARGS 1
352 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
354 /* If defined, a C expression to compute the alignment for a local
355 variable. TYPE is the data type, and ALIGN is the alignment that
356 the object would ordinarily have. The value of this macro is used
357 instead of that alignment to align the object.
359 If this macro is not defined, then ALIGN is used.
361 One use of this macro is to increase alignment of medium-size
362 data to make it all fit in fewer cache lines. */
364 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
366 /* Make strings word-aligned so strcpy from constants will be faster. */
367 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
368 (TREE_CODE (EXP) == STRING_CST \
369 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
371 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
373 /* Definitions for register eliminations.
375 This is an array of structures. Each structure initializes one pair
376 of eliminable registers. The "from" register number is given first,
377 followed by "to". Eliminations of the same "from" register are listed
378 in order of preference.
380 There are two registers that can always be eliminated on the i386.
381 The frame pointer and the arg pointer can be replaced by either the
382 hard frame pointer or to the stack pointer, depending upon the
383 circumstances. The hard frame pointer is not used before reload and
384 so it is not eligible for elimination. */
386 #define ELIMINABLE_REGS \
387 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
388 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
389 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
391 /* Define the offset between two registers, one to be eliminated, and the other
392 its replacement, at the start of a routine. */
394 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
395 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
397 /* This processor has
398 8 data register for doing arithmetic
399 8 pointer register for doing addressing, including
402 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
403 1 condition code flag register CC
404 5 return address registers RETS/I/X/N/E
405 1 arithmetic status register (ASTAT). */
407 #define FIRST_PSEUDO_REGISTER 50
409 #define D_REGNO_P(X) ((X) <= REG_R7)
410 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
411 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
412 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
413 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
414 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
415 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
416 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
417 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
419 #define REGISTER_NAMES { \
420 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
421 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
422 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
423 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
426 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
428 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
431 #define SHORT_REGISTER_NAMES { \
432 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
433 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
434 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
435 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
437 #define HIGH_REGISTER_NAMES { \
438 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
439 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
440 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
441 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
443 #define DREGS_PAIR_NAMES { \
444 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
446 #define BYTE_REGISTER_NAMES { \
447 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
450 /* 1 for registers that have pervasive standard uses
451 and are not available for the register allocator. */
453 #define FIXED_REGISTERS \
454 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
455 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
456 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
457 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
458 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
459 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
464 /* 1 for registers not available across function calls.
465 These must include the FIXED_REGISTERS and also any
466 registers that can be used without being saved.
467 The latter must include the registers where values are returned
468 and the register where structure-value addresses are passed.
469 Aside from that, you can include as many other registers as you like. */
471 #define CALL_USED_REGISTERS \
472 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
473 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
474 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
475 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
476 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
477 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
482 /* Order in which to allocate registers. Each register must be
483 listed once, even those in FIXED_REGISTERS. List frame pointer
484 late and fixed registers last. Note that, in general, we prefer
485 registers listed in CALL_USED_REGISTERS, keeping the others
486 available for storage of persistent values. */
488 #define REG_ALLOC_ORDER \
489 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
490 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
492 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
493 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
494 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
495 REG_ASTAT, REG_SEQSTAT, REG_USP, \
497 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
500 /* Define the classes of registers for register constraints in the
501 machine description. Also define ranges of constants.
503 One of the classes must always be named ALL_REGS and include all hard regs.
504 If there is more than one class, another class must be named NO_REGS
505 and contain no registers.
507 The name GENERAL_REGS must be the name of a class (or an alias for
508 another name such as ALL_REGS). This is the class of registers
509 that is allowed by "g" or "r" in a register constraint.
510 Also, registers outside this class are allocated only when
511 instructions express preferences for them.
513 The classes must be numbered in nondecreasing order; that is,
514 a larger-numbered class must never be contained completely
515 in a smaller-numbered class.
517 For any two classes, it is very desirable that there be another
518 class that represents their union. */
528 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
558 ALL_REGS, LIM_REG_CLASSES
561 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
563 #define GENERAL_REGS DPREGS
565 /* Give names of register classes as strings for dump file. */
567 #define REG_CLASS_NAMES \
605 /* An initializer containing the contents of the register classes, as integers
606 which are bit masks. The Nth integer specifies the contents of class N.
607 The way the integer MASK is interpreted is that register R is in the class
608 if `MASK & (1 << R)' is 1.
610 When the machine has more than 32 registers, an integer does not suffice.
611 Then the integers are replaced by sub-initializers, braced groupings
612 containing several integers. Each sub-initializer must be suitable as an
613 initializer for the type `HARD_REG_SET' which is defined in
616 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
617 MOST_REGS as the union of DPREGS and DAGREGS. */
619 #define REG_CLASS_CONTENTS \
621 { { 0x00000000, 0 }, /* NO_REGS */ \
622 { 0x000f0000, 0 }, /* IREGS */ \
623 { 0x00f00000, 0 }, /* BREGS */ \
624 { 0x0f000000, 0 }, /* LREGS */ \
625 { 0xf0000000, 0 }, /* MREGS */ \
626 { 0x0fff0000, 0 }, /* CIRCREGS */ \
627 { 0xffff0000, 0 }, /* DAGREGS */ \
628 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
629 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
630 { 0x00000000, 0x3 }, /* AREGS */ \
631 { 0x00000000, 0x4 }, /* CCREGS */ \
632 { 0x00000055, 0 }, /* EVEN_DREGS */ \
633 { 0x000000aa, 0 }, /* ODD_DREGS */ \
634 { 0x00000001, 0 }, /* D0REGS */ \
635 { 0x00000002, 0 }, /* D1REGS */ \
636 { 0x00000004, 0 }, /* D2REGS */ \
637 { 0x00000008, 0 }, /* D3REGS */ \
638 { 0x00000010, 0 }, /* D4REGS */ \
639 { 0x00000020, 0 }, /* D5REGS */ \
640 { 0x00000040, 0 }, /* D6REGS */ \
641 { 0x00000080, 0 }, /* D7REGS */ \
642 { 0x000000ff, 0 }, /* DREGS */ \
643 { 0x00000100, 0x000 }, /* P0REGS */ \
644 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
645 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
646 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
647 { 0x0000ff00, 0x800 }, /* PREGS */ \
648 { 0x000fff00, 0x800 }, /* IPREGS */ \
649 { 0x0000ffff, 0x800 }, /* DPREGS */ \
650 { 0xffffffff, 0x800 }, /* MOST_REGS */\
651 { 0x00000000, 0x3000 }, /* LT_REGS */\
652 { 0x00000000, 0xc000 }, /* LC_REGS */\
653 { 0x00000000, 0x30000 }, /* LB_REGS */\
654 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
655 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
656 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
658 #define IREG_POSSIBLE_P(OUTER) \
659 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
660 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
661 || (OUTER) == MEM || (OUTER) == ADDRESS)
663 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
664 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
666 #define INDEX_REG_CLASS PREGS
668 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
669 (P_REGNO_P (X) || (X) == REG_ARGP \
670 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
673 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
674 ((X) >= FIRST_PSEUDO_REGISTER \
675 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
678 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
679 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
681 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
682 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
685 #define REGNO_OK_FOR_INDEX_P(X) 0
687 /* The same information, inverted:
688 Return the class number of the smallest class containing
689 reg number REGNO. This could be a conditional expression
690 or could index an array. */
692 #define REGNO_REG_CLASS(REGNO) \
693 ((REGNO) == REG_R0 ? D0REGS \
694 : (REGNO) == REG_R1 ? D1REGS \
695 : (REGNO) == REG_R2 ? D2REGS \
696 : (REGNO) == REG_R3 ? D3REGS \
697 : (REGNO) == REG_R4 ? D4REGS \
698 : (REGNO) == REG_R5 ? D5REGS \
699 : (REGNO) == REG_R6 ? D6REGS \
700 : (REGNO) == REG_R7 ? D7REGS \
701 : (REGNO) == REG_P0 ? P0REGS \
702 : (REGNO) < REG_I0 ? PREGS \
703 : (REGNO) == REG_ARGP ? PREGS \
704 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
705 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
706 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
707 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
708 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
709 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
710 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
711 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
712 : (REGNO) == REG_CC ? CCREGS \
713 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
716 /* The following macro defines cover classes for Integrated Register
717 Allocator. Cover classes is a set of non-intersected register
718 classes covering all hard registers used for register allocation
719 purpose. Any move between two registers of a cover class should be
720 cheaper than load or store of the registers. The macro value is
721 array of register classes with LIM_REG_CLASSES used as the end
724 #define IRA_COVER_CLASSES \
726 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
729 /* When this hook returns true for MODE, the compiler allows
730 registers explicitly used in the rtl to be used as spill registers
731 but prevents the compiler from extending the lifetime of these
733 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
735 /* Do not allow to store a value in REG_CC for any mode */
736 /* Do not allow to store value in pregs if mode is not SI*/
737 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
739 /* Return the maximum number of consecutive registers
740 needed to represent mode MODE in a register of class CLASS. */
741 #define CLASS_MAX_NREGS(CLASS, MODE) \
742 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
743 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
745 #define HARD_REGNO_NREGS(REGNO, MODE) \
746 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
747 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
748 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
750 /* A C expression that is nonzero if hard register TO can be
751 considered for use as a rename register for FROM register */
752 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
754 /* A C expression that is nonzero if it is desirable to choose
755 register allocation so as to avoid move instructions between a
756 value of mode MODE1 and a value of mode MODE2.
758 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
759 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
760 MODE2)' must be zero. */
761 #define MODES_TIEABLE_P(MODE1, MODE2) \
762 ((MODE1) == (MODE2) \
763 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
764 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
765 && (GET_MODE_CLASS (MODE2) == MODE_INT \
766 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
767 && (MODE1) != BImode && (MODE2) != BImode \
768 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
769 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
771 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
772 A C expression that places additional restrictions on the register
773 class to use when it is necessary to copy value X into a register
774 in class CLASS. The value is a register class; perhaps CLASS, or
775 perhaps another, smaller class. */
776 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
777 (GET_CODE (X) == POST_INC \
778 || GET_CODE (X) == POST_DEC \
779 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
781 /* Function Calling Conventions. */
783 /* The type of the current function; normal functions are of type
786 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
788 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
790 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
792 /* Flags for the call/call_value rtl operations set up by function_arg */
793 #define CALL_NORMAL 0x00000000 /* no special processing */
794 #define CALL_LONG 0x00000001 /* always call indirect */
795 #define CALL_SHORT 0x00000002 /* always call by symbol */
798 int words; /* # words passed so far */
799 int nregs; /* # registers available for passing */
800 int *arg_regs; /* array of register -1 terminated */
801 int call_cookie; /* Do special things for this call */
804 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
807 /* Initialize a variable CUM of type CUMULATIVE_ARGS
808 for a call to a function whose data type is FNTYPE.
809 For a library call, FNTYPE is 0. */
810 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
811 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
813 /* Define how to find the value returned by a function.
814 VALTYPE is the data type of the value (as a tree).
815 If the precise function being called is known, FUNC is its FUNCTION_DECL;
816 otherwise, FUNC is 0.
819 #define VALUE_REGNO(MODE) (REG_R0)
821 #define FUNCTION_VALUE(VALTYPE, FUNC) \
822 gen_rtx_REG (TYPE_MODE (VALTYPE), \
823 VALUE_REGNO(TYPE_MODE(VALTYPE)))
825 /* Define how to find the value returned by a library function
826 assuming the value has mode MODE. */
828 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
830 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
832 #define DEFAULT_PCC_STRUCT_RETURN 0
834 /* Before the prologue, the return address is in the RETS register. */
835 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
837 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
839 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
841 /* Call instructions don't modify the stack pointer on the Blackfin. */
842 #define INCOMING_FRAME_SP_OFFSET 0
844 /* Describe how we implement __builtin_eh_return. */
845 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
846 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
847 #define EH_RETURN_HANDLER_RTX \
848 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
850 /* Addressing Modes */
852 /* Nonzero if the constant value X is a legitimate general operand.
853 symbol_ref are not legitimate and will be put into constant pool.
854 See force_const_mem().
855 If -mno-pool, all constants are legitimate.
857 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
859 /* A number, the maximum number of registers that can appear in a
860 valid memory address. Note that it is up to you to specify a
861 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
862 would ever accept. */
863 #define MAX_REGS_PER_ADDRESS 1
865 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
866 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
868 #define HAVE_POST_INCREMENT 1
869 #define HAVE_POST_DECREMENT 1
870 #define HAVE_PRE_DECREMENT 1
872 /* `LEGITIMATE_PIC_OPERAND_P (X)'
873 A C expression that is nonzero if X is a legitimate immediate
874 operand on the target machine when generating position independent
875 code. You can assume that X satisfies `CONSTANT_P', so you need
876 not check this. You can also assume FLAG_PIC is true, so you need
877 not check it either. You need not define this macro if all
878 constants (including `SYMBOL_REF') can be immediate operands when
879 generating position independent code. */
880 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
882 #define SYMBOLIC_CONST(X) \
883 (GET_CODE (X) == SYMBOL_REF \
884 || GET_CODE (X) == LABEL_REF \
885 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
887 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
889 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
890 is done just by pretending it is already truncated. */
891 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
893 /* Max number of bytes we can move from memory to memory
894 in one reasonably fast instruction. */
895 #define MOVE_MAX UNITS_PER_WORD
897 /* If a memory-to-memory move would take MOVE_RATIO or more simple
898 move-instruction pairs, we will do a movmem or libcall instead. */
900 #define MOVE_RATIO(speed) 5
902 /* STORAGE LAYOUT: target machine storage layout
903 Define this macro as a C expression which is nonzero if accessing
904 less than a word of memory (i.e. a `char' or a `short') is no
905 faster than accessing a word of memory, i.e., if such access
906 require more than one instruction or if there is no difference in
907 cost between byte and (aligned) word loads.
909 When this macro is not defined, the compiler will access a field by
910 finding the smallest containing object; when it is defined, a
911 fullword load will be used if alignment permits. Unless bytes
912 accesses are faster than word accesses, using word accesses is
913 preferable since it may eliminate subsequent memory access if
914 subsequent accesses occur to other fields in the same word of the
915 structure, but to different bytes. */
916 #define SLOW_BYTE_ACCESS 0
917 #define SLOW_SHORT_ACCESS 0
919 /* Define this if most significant bit is lowest numbered
920 in instructions that operate on numbered bit-fields. */
921 #define BITS_BIG_ENDIAN 0
923 /* Define this if most significant byte of a word is the lowest numbered.
924 We can't access bytes but if we could we would in the Big Endian order. */
925 #define BYTES_BIG_ENDIAN 0
927 /* Define this if most significant word of a multiword number is numbered. */
928 #define WORDS_BIG_ENDIAN 0
930 /* number of bits in an addressable storage unit */
931 #define BITS_PER_UNIT 8
933 /* Width in bits of a "word", which is the contents of a machine register.
934 Note that this is not necessarily the width of data type `int';
935 if using 16-bit ints on a 68000, this would still be 32.
936 But on a machine with 16-bit registers, this would be 16. */
937 #define BITS_PER_WORD 32
939 /* Width of a word, in units (bytes). */
940 #define UNITS_PER_WORD 4
942 /* Width in bits of a pointer.
943 See also the macro `Pmode1' defined below. */
944 #define POINTER_SIZE 32
946 /* Allocation boundary (in *bits*) for storing pointers in memory. */
947 #define POINTER_BOUNDARY 32
949 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
950 #define PARM_BOUNDARY 32
952 /* Boundary (in *bits*) on which stack pointer should be aligned. */
953 #define STACK_BOUNDARY 32
955 /* Allocation boundary (in *bits*) for the code of a function. */
956 #define FUNCTION_BOUNDARY 32
958 /* Alignment of field after `int : 0' in a structure. */
959 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
961 /* No data type wants to be aligned rounder than this. */
962 #define BIGGEST_ALIGNMENT 32
964 /* Define this if move instructions will actually fail to work
965 when given unaligned data. */
966 #define STRICT_ALIGNMENT 1
968 /* (shell-command "rm c-decl.o stor-layout.o")
969 * never define PCC_BITFIELD_TYPE_MATTERS
970 * really cause some alignment problem
973 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
976 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
980 /* what is the 'type' of size_t */
981 #define SIZE_TYPE "long unsigned int"
983 /* Define this as 1 if `char' should by default be signed; else as 0. */
984 #define DEFAULT_SIGNED_CHAR 1
985 #define FLOAT_TYPE_SIZE BITS_PER_WORD
986 #define SHORT_TYPE_SIZE 16
987 #define CHAR_TYPE_SIZE 8
988 #define INT_TYPE_SIZE 32
989 #define LONG_TYPE_SIZE 32
990 #define LONG_LONG_TYPE_SIZE 64
992 /* Note: Fix this to depend on target switch. -- lev */
994 /* Note: Try to implement double and force long double. -- tonyko
995 * #define __DOUBLES_ARE_FLOATS__
996 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
997 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
998 * #define DOUBLES_ARE_FLOATS 1
1001 #define DOUBLE_TYPE_SIZE 64
1002 #define LONG_DOUBLE_TYPE_SIZE 64
1004 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1005 A macro to update M and UNSIGNEDP when an object whose type is
1006 TYPE and which has the specified mode and signedness is to be
1007 stored in a register. This macro is only called when TYPE is a
1010 On most RISC machines, which only have operations that operate on
1011 a full register, define this macro to set M to `word_mode' if M is
1012 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1013 only integer modes should be widened because wider-precision
1014 floating-point operations are usually more expensive than their
1015 narrower counterparts.
1017 For most machines, the macro definition does not change UNSIGNEDP.
1018 However, some machines, have instructions that preferentially
1019 handle either signed or unsigned quantities of certain modes. For
1020 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1021 instructions sign-extend the result to 64 bits. On such machines,
1022 set UNSIGNEDP according to which kind of extension is more
1025 Do not define this macro if it would never modify M.*/
1027 #define BFIN_PROMOTE_MODE_P(MODE) \
1028 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1029 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1031 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1032 if (BFIN_PROMOTE_MODE_P(MODE)) \
1034 if (MODE == QImode) \
1036 else if (MODE == HImode) \
1041 /* Describing Relative Costs of Operations */
1043 /* Do not put function addr into constant pool */
1044 #define NO_FUNCTION_CSE 1
1046 /* A C expression for the cost of moving data from a register in class FROM to
1047 one in class TO. The classes are expressed using the enumeration values
1048 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1049 interpreted relative to that.
1051 It is not required that the cost always equal 2 when FROM is the same as TO;
1052 on some machines it is expensive to move between registers if they are not
1053 general registers. */
1055 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1056 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1058 /* A C expression for the cost of moving data of mode M between a
1059 register and memory. A value of 2 is the default; this cost is
1060 relative to those in `REGISTER_MOVE_COST'.
1062 If moving between registers and memory is more expensive than
1063 between two registers, you should define this macro to express the
1066 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1067 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1069 /* Specify the machine mode that this machine uses
1070 for the index in the tablejump instruction. */
1071 #define CASE_VECTOR_MODE SImode
1073 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1075 /* Define if operations between registers always perform the operation
1076 on the full register even if a narrower mode is specified.
1077 #define WORD_REGISTER_OPERATIONS
1080 /* Evaluates to true if A and B are mac flags that can be used
1081 together in a single multiply insn. That is the case if they are
1082 both the same flag not involving M, or if one is a combination of
1083 the other with M. */
1084 #define MACFLAGS_MATCH_P(A, B) \
1086 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1087 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1088 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1089 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1091 /* Switch into a generic section. */
1092 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1094 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1095 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1097 typedef enum sections {
1103 typedef enum directives {
1112 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1114 || ((C) == '|' && (STR)[1] == '|'))
1116 #define TEXT_SECTION_ASM_OP ".text;"
1117 #define DATA_SECTION_ASM_OP ".data;"
1119 #define ASM_APP_ON ""
1120 #define ASM_APP_OFF ""
1122 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1123 do { fputs (".global ", FILE); \
1124 assemble_name (FILE, NAME); \
1126 fputc ('\n',FILE); \
1129 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1131 fputs (".type ", FILE); \
1132 assemble_name (FILE, NAME); \
1133 fputs (", STT_FUNC", FILE); \
1135 fputc ('\n',FILE); \
1136 ASM_OUTPUT_LABEL(FILE, NAME); \
1139 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1140 do { assemble_name (FILE, NAME); \
1141 fputs (":\n",FILE); \
1144 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1145 do { fprintf (FILE, "_%s", NAME); \
1148 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1149 do { char __buf[256]; \
1150 fprintf (FILE, "\t.dd\t"); \
1151 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1152 assemble_name (FILE, __buf); \
1153 fputc (';', FILE); \
1154 fputc ('\n', FILE); \
1157 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1158 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1160 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1163 fprintf (FILE, "\t.dd\t"); \
1164 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1165 assemble_name (FILE, __buf); \
1166 fputs (" - ", FILE); \
1167 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1168 assemble_name (FILE, __buf); \
1169 fputc (';', FILE); \
1170 fputc ('\n', FILE); \
1173 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1176 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1179 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1181 asm_output_skip (FILE, SIZE); \
1184 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1186 switch_to_section (data_section); \
1187 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1188 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1189 ASM_OUTPUT_LABEL (FILE, NAME); \
1190 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1191 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1194 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1196 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1197 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1199 #define ASM_COMMENT_START "//"
1201 #define FUNCTION_PROFILER(FILE, LABELNO) \
1203 fprintf (FILE, "\tCALL __mcount;\n"); \
1206 #undef NO_PROFILE_COUNTERS
1207 #define NO_PROFILE_COUNTERS 1
1209 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1210 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1212 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1214 /* This works for GAS and some other assemblers. */
1215 #define SET_ASM_OP ".set "
1217 /* DBX register number for a given compiler register number */
1218 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1220 #define SIZE_ASM_OP "\t.size\t"
1222 extern int splitting_for_sched, splitting_loops;
1224 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1226 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1227 #define TARGET_SUPPORTS_SYNC_CALLS 0
1230 #endif /* _BFIN_CONFIG */