1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
29 /* Print subsidiary information on the compiler version in use. */
30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32 /* Run-time compilation parameters selecting different hardware subsets. */
34 extern int target_flags;
36 #ifndef DEFAULT_CPU_TYPE
37 #define DEFAULT_CPU_TYPE BFIN_CPU_BF532
40 /* Predefinition in the preprocessor for this target machine */
41 #ifndef TARGET_CPU_CPP_BUILTINS
42 #define TARGET_CPU_CPP_BUILTINS() \
45 builtin_define_std ("bfin"); \
46 builtin_define_std ("BFIN"); \
47 builtin_define ("__ADSPBLACKFIN__"); \
48 builtin_define ("__ADSPLPBLACKFIN__"); \
50 switch (bfin_cpu_type) \
52 case BFIN_CPU_BF531: \
53 builtin_define ("__ADSPBF531__"); \
55 case BFIN_CPU_BF532: \
56 builtin_define ("__ADSPBF532__"); \
58 case BFIN_CPU_BF533: \
59 builtin_define ("__ADSPBF533__"); \
61 case BFIN_CPU_BF534: \
62 builtin_define ("__ADSPBF534__"); \
64 case BFIN_CPU_BF536: \
65 builtin_define ("__ADSPBF536__"); \
67 case BFIN_CPU_BF537: \
68 builtin_define ("__ADSPBF537__"); \
70 case BFIN_CPU_BF561: \
71 builtin_define ("__ADSPBF561__"); \
76 builtin_define ("__BFIN_FDPIC__"); \
77 if (TARGET_ID_SHARED_LIBRARY) \
78 builtin_define ("__ID_SHARED_LIB__"); \
79 if (flag_no_builtin) \
80 builtin_define ("__NO_BUILTIN"); \
85 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
86 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
87 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
88 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
90 #ifndef SUBTARGET_DRIVER_SELF_SPECS
91 # define SUBTARGET_DRIVER_SELF_SPECS
94 #define LINK_GCC_C_SEQUENCE_SPEC "\
95 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
98 /* A C string constant that tells the GCC driver program options to pass to
99 the assembler. It can also specify how to translate options you give to GNU
100 CC into options for GCC to pass to the assembler. See the file `sun3.h'
101 for an example of this.
103 Do not define this macro if it does not need to do anything.
105 Defined in svr4.h. */
108 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
109 %{mno-fdpic:-mnopic} %{mfdpic}"
114 %{mfdpic:-melf32bfinfd -z text} \
115 %{static:-dn -Bstatic} \
116 %{shared:-G -Bdynamic} \
117 %{symbolic:-Bsymbolic} \
121 -init __init -fini __fini "
123 /* Generate DSP instructions, like DSP halfword loads */
124 #define TARGET_DSP (1)
126 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
128 /* Maximum number of library ids we permit */
129 #define MAX_LIBRARY_ID 255
131 extern const char *bfin_library_id_string;
133 /* Sometimes certain combinations of command options do not make
134 sense on a particular target machine. You can define a macro
135 `OVERRIDE_OPTIONS' to take account of this. This macro, if
136 defined, is executed once just after all the command options have
139 Don't use this macro to turn on various extra optimizations for
140 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
142 #define OVERRIDE_OPTIONS override_options ()
144 #define FUNCTION_MODE SImode
147 /* store-condition-codes instructions store 0 for false
148 This is the value stored for true. */
149 #define STORE_FLAG_VALUE 1
151 /* Define this if pushing a word on the stack
152 makes the stack pointer a smaller address. */
153 #define STACK_GROWS_DOWNWARD
155 #define STACK_PUSH_CODE PRE_DEC
157 /* Define this to nonzero if the nominal address of the stack frame
158 is at the high-address end of the local variables;
159 that is, each additional local variable allocated
160 goes at a more negative offset in the frame. */
161 #define FRAME_GROWS_DOWNWARD 1
163 /* We define a dummy ARGP register; the parameters start at offset 0 from
165 #define FIRST_PARM_OFFSET(DECL) 0
167 /* Offset within stack frame to start allocating local variables at.
168 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
169 first local allocated. Otherwise, it is the offset to the BEGINNING
170 of the first local allocated. */
171 #define STARTING_FRAME_OFFSET 0
173 /* Register to use for pushing function arguments. */
174 #define STACK_POINTER_REGNUM REG_P6
176 /* Base register for access to local variables of the function. */
177 #define FRAME_POINTER_REGNUM REG_P7
179 /* A dummy register that will be eliminated to either FP or SP. */
180 #define ARG_POINTER_REGNUM REG_ARGP
182 /* `PIC_OFFSET_TABLE_REGNUM'
183 The register number of the register used to address a table of
184 static data addresses in memory. In some cases this register is
185 defined by a processor's "application binary interface" (ABI).
186 When this macro is defined, RTL is generated for this register
187 once, as with the stack pointer and frame pointer registers. If
188 this macro is not defined, it is up to the machine-dependent files
189 to allocate such a register (if necessary). */
190 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
192 #define FDPIC_FPTR_REGNO REG_P1
193 #define FDPIC_REGNO REG_P3
194 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
196 /* A static chain register for nested functions. We need to use a
197 call-clobbered register for this. */
198 #define STATIC_CHAIN_REGNUM REG_P2
200 /* Define this if functions should assume that stack space has been
201 allocated for arguments even when their values are passed in
204 The value of this macro is the size, in bytes, of the area reserved for
205 arguments passed in registers.
207 This space can either be allocated by the caller or be a part of the
208 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
210 #define FIXED_STACK_AREA 12
211 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
213 /* Define this if the above stack space is to be considered part of the
214 * space allocated by the caller. */
215 #define OUTGOING_REG_PARM_STACK_SPACE 1
217 /* Define this if the maximum size of all the outgoing args is to be
218 accumulated and pushed during the prologue. The amount can be
219 found in the variable current_function_outgoing_args_size. */
220 #define ACCUMULATE_OUTGOING_ARGS 1
222 /* Value should be nonzero if functions must have frame pointers.
223 Zero means the frame pointer need not be set up (and parms
224 may be accessed via the stack pointer) in functions that seem suitable.
225 This is computed in `reload', in reload1.c.
227 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
229 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
231 /* If defined, a C expression to compute the alignment for a local
232 variable. TYPE is the data type, and ALIGN is the alignment that
233 the object would ordinarily have. The value of this macro is used
234 instead of that alignment to align the object.
236 If this macro is not defined, then ALIGN is used.
238 One use of this macro is to increase alignment of medium-size
239 data to make it all fit in fewer cache lines. */
241 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
243 /* Make strings word-aligned so strcpy from constants will be faster. */
244 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
245 (TREE_CODE (EXP) == STRING_CST \
246 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
248 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
249 #define TRAMPOLINE_TEMPLATE(FILE) \
252 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
253 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
254 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
255 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
256 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
257 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
258 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
259 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
260 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
264 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
265 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
266 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
267 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
268 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
271 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
272 initialize_trampoline (TRAMP, FNADDR, CXT)
274 /* Definitions for register eliminations.
276 This is an array of structures. Each structure initializes one pair
277 of eliminable registers. The "from" register number is given first,
278 followed by "to". Eliminations of the same "from" register are listed
279 in order of preference.
281 There are two registers that can always be eliminated on the i386.
282 The frame pointer and the arg pointer can be replaced by either the
283 hard frame pointer or to the stack pointer, depending upon the
284 circumstances. The hard frame pointer is not used before reload and
285 so it is not eligible for elimination. */
287 #define ELIMINABLE_REGS \
288 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
289 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
290 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
292 /* Given FROM and TO register numbers, say whether this elimination is
293 allowed. Frame pointer elimination is automatically handled.
295 All other eliminations are valid. */
297 #define CAN_ELIMINATE(FROM, TO) \
298 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
300 /* Define the offset between two registers, one to be eliminated, and the other
301 its replacement, at the start of a routine. */
303 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
304 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
306 /* This processor has
307 8 data register for doing arithmetic
308 8 pointer register for doing addressing, including
311 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
312 1 condition code flag register CC
313 5 return address registers RETS/I/X/N/E
314 1 arithmetic status register (ASTAT). */
316 #define FIRST_PSEUDO_REGISTER 50
318 #define D_REGNO_P(X) ((X) <= REG_R7)
319 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
320 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
321 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
322 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
323 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
324 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
325 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
326 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
328 #define REGISTER_NAMES { \
329 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
330 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
331 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
332 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
335 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
337 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
340 #define SHORT_REGISTER_NAMES { \
341 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
342 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
343 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
344 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
346 #define HIGH_REGISTER_NAMES { \
347 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
348 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
349 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
350 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
352 #define DREGS_PAIR_NAMES { \
353 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
355 #define BYTE_REGISTER_NAMES { \
356 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
359 /* 1 for registers that have pervasive standard uses
360 and are not available for the register allocator. */
362 #define FIXED_REGISTERS \
363 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
364 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
365 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
366 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
367 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
368 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
373 /* 1 for registers not available across function calls.
374 These must include the FIXED_REGISTERS and also any
375 registers that can be used without being saved.
376 The latter must include the registers where values are returned
377 and the register where structure-value addresses are passed.
378 Aside from that, you can include as many other registers as you like. */
380 #define CALL_USED_REGISTERS \
381 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
382 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
383 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
384 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
385 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
386 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
391 /* Order in which to allocate registers. Each register must be
392 listed once, even those in FIXED_REGISTERS. List frame pointer
393 late and fixed registers last. Note that, in general, we prefer
394 registers listed in CALL_USED_REGISTERS, keeping the others
395 available for storage of persistent values. */
397 #define REG_ALLOC_ORDER \
398 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
399 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
401 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
402 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
403 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
404 REG_ASTAT, REG_SEQSTAT, REG_USP, \
406 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
409 /* Macro to conditionally modify fixed_regs/call_used_regs. */
410 #define CONDITIONAL_REGISTER_USAGE \
412 conditional_register_usage(); \
414 call_used_regs[FDPIC_REGNO] = 1; \
415 if (!TARGET_FDPIC && flag_pic) \
417 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
418 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
422 /* Define the classes of registers for register constraints in the
423 machine description. Also define ranges of constants.
425 One of the classes must always be named ALL_REGS and include all hard regs.
426 If there is more than one class, another class must be named NO_REGS
427 and contain no registers.
429 The name GENERAL_REGS must be the name of a class (or an alias for
430 another name such as ALL_REGS). This is the class of registers
431 that is allowed by "g" or "r" in a register constraint.
432 Also, registers outside this class are allocated only when
433 instructions express preferences for them.
435 The classes must be numbered in nondecreasing order; that is,
436 a larger-numbered class must never be contained completely
437 in a smaller-numbered class.
439 For any two classes, it is very desirable that there be another
440 class that represents their union. */
450 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
479 ALL_REGS, LIM_REG_CLASSES
482 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
484 #define GENERAL_REGS DPREGS
486 /* Give names of register classes as strings for dump file. */
488 #define REG_CLASS_NAMES \
525 /* An initializer containing the contents of the register classes, as integers
526 which are bit masks. The Nth integer specifies the contents of class N.
527 The way the integer MASK is interpreted is that register R is in the class
528 if `MASK & (1 << R)' is 1.
530 When the machine has more than 32 registers, an integer does not suffice.
531 Then the integers are replaced by sub-initializers, braced groupings
532 containing several integers. Each sub-initializer must be suitable as an
533 initializer for the type `HARD_REG_SET' which is defined in
536 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
537 MOST_REGS as the union of DPREGS and DAGREGS. */
539 #define REG_CLASS_CONTENTS \
541 { { 0x00000000, 0 }, /* NO_REGS */ \
542 { 0x000f0000, 0 }, /* IREGS */ \
543 { 0x00f00000, 0 }, /* BREGS */ \
544 { 0x0f000000, 0 }, /* LREGS */ \
545 { 0xf0000000, 0 }, /* MREGS */ \
546 { 0x0fff0000, 0 }, /* CIRCREGS */ \
547 { 0xffff0000, 0 }, /* DAGREGS */ \
548 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
549 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
550 { 0x00000000, 0x3 }, /* AREGS */ \
551 { 0x00000000, 0x4 }, /* CCREGS */ \
552 { 0x00000055, 0 }, /* EVEN_DREGS */ \
553 { 0x000000aa, 0 }, /* ODD_DREGS */ \
554 { 0x00000001, 0 }, /* D0REGS */ \
555 { 0x00000002, 0 }, /* D1REGS */ \
556 { 0x00000004, 0 }, /* D2REGS */ \
557 { 0x00000008, 0 }, /* D3REGS */ \
558 { 0x00000010, 0 }, /* D4REGS */ \
559 { 0x00000020, 0 }, /* D5REGS */ \
560 { 0x00000040, 0 }, /* D6REGS */ \
561 { 0x00000080, 0 }, /* D7REGS */ \
562 { 0x000000ff, 0 }, /* DREGS */ \
563 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
564 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
565 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
566 { 0x0000ff00, 0x800 }, /* PREGS */ \
567 { 0x000fff00, 0x800 }, /* IPREGS */ \
568 { 0x0000ffff, 0x800 }, /* DPREGS */ \
569 { 0xffffffff, 0x800 }, /* MOST_REGS */\
570 { 0x00000000, 0x3000 }, /* LT_REGS */\
571 { 0x00000000, 0xc000 }, /* LC_REGS */\
572 { 0x00000000, 0x30000 }, /* LB_REGS */\
573 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
574 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
575 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
577 #define IREG_POSSIBLE_P(OUTER) \
578 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
579 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
580 || (OUTER) == MEM || (OUTER) == ADDRESS)
582 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
583 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
585 #define INDEX_REG_CLASS PREGS
587 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
588 (P_REGNO_P (X) || (X) == REG_ARGP \
589 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
592 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
593 ((X) >= FIRST_PSEUDO_REGISTER \
594 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
597 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
598 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
600 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
601 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
604 #define REGNO_OK_FOR_INDEX_P(X) 0
606 /* Get reg_class from a letter such as appears in the machine description. */
608 #define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \
609 ((LETTER) == 'a' ? PREGS : \
610 (LETTER) == 'Z' ? FDPIC_REGS : \
611 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
612 (LETTER) == 'd' ? DREGS : \
613 (LETTER) == 'z' ? PREGS_CLOBBERED : \
614 (LETTER) == 'D' ? EVEN_DREGS : \
615 (LETTER) == 'W' ? ODD_DREGS : \
616 (LETTER) == 'e' ? AREGS : \
617 (LETTER) == 'A' ? EVEN_AREGS : \
618 (LETTER) == 'B' ? ODD_AREGS : \
619 (LETTER) == 'b' ? IREGS : \
620 (LETTER) == 'v' ? BREGS : \
621 (LETTER) == 'f' ? MREGS : \
622 (LETTER) == 'c' ? CIRCREGS : \
623 (LETTER) == 'C' ? CCREGS : \
624 (LETTER) == 't' ? LT_REGS : \
625 (LETTER) == 'k' ? LC_REGS : \
626 (LETTER) == 'u' ? LB_REGS : \
627 (LETTER) == 'x' ? MOST_REGS : \
628 (LETTER) == 'y' ? PROLOGUE_REGS : \
629 (LETTER) == 'w' ? NON_A_CC_REGS : \
631 ? ((STR)[1] == '0' ? D0REGS \
632 : (STR)[1] == '1' ? D1REGS \
633 : (STR)[1] == '2' ? D2REGS \
634 : (STR)[1] == '3' ? D3REGS \
635 : (STR)[1] == '4' ? D4REGS \
636 : (STR)[1] == '5' ? D5REGS \
637 : (STR)[1] == '6' ? D6REGS \
638 : (STR)[1] == '7' ? D7REGS \
642 /* The same information, inverted:
643 Return the class number of the smallest class containing
644 reg number REGNO. This could be a conditional expression
645 or could index an array. */
647 #define REGNO_REG_CLASS(REGNO) \
648 ((REGNO) == REG_R0 ? D0REGS \
649 : (REGNO) == REG_R1 ? D1REGS \
650 : (REGNO) == REG_R2 ? D2REGS \
651 : (REGNO) == REG_R3 ? D3REGS \
652 : (REGNO) == REG_R4 ? D4REGS \
653 : (REGNO) == REG_R5 ? D5REGS \
654 : (REGNO) == REG_R6 ? D6REGS \
655 : (REGNO) == REG_R7 ? D7REGS \
656 : (REGNO) < REG_I0 ? PREGS \
657 : (REGNO) == REG_ARGP ? PREGS \
658 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
659 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
660 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
661 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
662 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
663 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
664 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
665 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
666 : (REGNO) == REG_CC ? CCREGS \
667 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
670 /* When defined, the compiler allows registers explicitly used in the
671 rtl to be used as spill registers but prevents the compiler from
672 extending the lifetime of these registers. */
673 #define SMALL_REGISTER_CLASSES 1
675 #define CLASS_LIKELY_SPILLED_P(CLASS) \
676 ((CLASS) == PREGS_CLOBBERED \
677 || (CLASS) == PROLOGUE_REGS \
678 || (CLASS) == D0REGS \
679 || (CLASS) == D1REGS \
680 || (CLASS) == D2REGS \
681 || (CLASS) == CCREGS)
683 /* Do not allow to store a value in REG_CC for any mode */
684 /* Do not allow to store value in pregs if mode is not SI*/
685 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
687 /* Return the maximum number of consecutive registers
688 needed to represent mode MODE in a register of class CLASS. */
689 #define CLASS_MAX_NREGS(CLASS, MODE) \
690 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
691 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
693 #define HARD_REGNO_NREGS(REGNO, MODE) \
694 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
695 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
696 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
698 /* A C expression that is nonzero if hard register TO can be
699 considered for use as a rename register for FROM register */
700 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
702 /* A C expression that is nonzero if it is desirable to choose
703 register allocation so as to avoid move instructions between a
704 value of mode MODE1 and a value of mode MODE2.
706 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
707 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
708 MODE2)' must be zero. */
709 #define MODES_TIEABLE_P(MODE1, MODE2) \
710 ((MODE1) == (MODE2) \
711 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
712 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
713 && (GET_MODE_CLASS (MODE2) == MODE_INT \
714 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
715 && (MODE1) != BImode && (MODE2) != BImode \
716 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
717 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
719 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
720 A C expression that places additional restrictions on the register
721 class to use when it is necessary to copy value X into a register
722 in class CLASS. The value is a register class; perhaps CLASS, or
723 perhaps another, smaller class. */
724 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
725 (GET_CODE (X) == POST_INC \
726 || GET_CODE (X) == POST_DEC \
727 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
729 /* Function Calling Conventions. */
731 /* The type of the current function; normal functions are of type
734 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
737 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
739 /* Flags for the call/call_value rtl operations set up by function_arg */
740 #define CALL_NORMAL 0x00000000 /* no special processing */
741 #define CALL_LONG 0x00000001 /* always call indirect */
742 #define CALL_SHORT 0x00000002 /* always call by symbol */
745 int words; /* # words passed so far */
746 int nregs; /* # registers available for passing */
747 int *arg_regs; /* array of register -1 terminated */
748 int call_cookie; /* Do special things for this call */
751 /* Define where to put the arguments to a function.
752 Value is zero to push the argument on the stack,
753 or a hard register in which to store the argument.
755 MODE is the argument's machine mode.
756 TYPE is the data type of the argument (as a tree).
757 This is null for libcalls where that information may
759 CUM is a variable of type CUMULATIVE_ARGS which gives info about
760 the preceding args and about the function being called.
761 NAMED is nonzero if this argument is a named parameter
762 (otherwise it is an extra parameter matching an ellipsis). */
764 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
765 (function_arg (&CUM, MODE, TYPE, NAMED))
767 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
770 /* Initialize a variable CUM of type CUMULATIVE_ARGS
771 for a call to a function whose data type is FNTYPE.
772 For a library call, FNTYPE is 0. */
773 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
774 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
776 /* Update the data in CUM to advance over an argument
777 of mode MODE and data type TYPE.
778 (TYPE is null for libcalls where that information may not be available.) */
779 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
780 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
782 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
784 /* Define how to find the value returned by a function.
785 VALTYPE is the data type of the value (as a tree).
786 If the precise function being called is known, FUNC is its FUNCTION_DECL;
787 otherwise, FUNC is 0.
790 #define VALUE_REGNO(MODE) (REG_R0)
792 #define FUNCTION_VALUE(VALTYPE, FUNC) \
793 gen_rtx_REG (TYPE_MODE (VALTYPE), \
794 VALUE_REGNO(TYPE_MODE(VALTYPE)))
796 /* Define how to find the value returned by a library function
797 assuming the value has mode MODE. */
799 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
801 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
803 #define DEFAULT_PCC_STRUCT_RETURN 0
804 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
806 /* Before the prologue, the return address is in the RETS register. */
807 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
809 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
811 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
813 /* Call instructions don't modify the stack pointer on the Blackfin. */
814 #define INCOMING_FRAME_SP_OFFSET 0
816 /* Describe how we implement __builtin_eh_return. */
817 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
818 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
819 #define EH_RETURN_HANDLER_RTX \
820 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
822 /* Addressing Modes */
824 /* Recognize any constant value that is a valid address. */
825 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
827 /* Nonzero if the constant value X is a legitimate general operand.
828 symbol_ref are not legitimate and will be put into constant pool.
829 See force_const_mem().
830 If -mno-pool, all constants are legitimate.
832 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
834 /* A number, the maximum number of registers that can appear in a
835 valid memory address. Note that it is up to you to specify a
836 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
837 would ever accept. */
838 #define MAX_REGS_PER_ADDRESS 1
840 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
841 that is a valid memory address for an instruction.
842 The MODE argument is the machine mode for the MEM expression
843 that wants to use this address.
845 Blackfin addressing modes are as follows:
851 W [ Preg + uimm16m2 ]
859 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
860 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
863 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
865 if (bfin_legitimate_address_p (MODE, X, 1)) \
869 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
871 if (bfin_legitimate_address_p (MODE, X, 0)) \
876 /* Try machine-dependent ways of modifying an illegitimate address
877 to be legitimate. If we find one, return the new, valid address.
878 This macro is used in only one place: `memory_address' in explow.c.
880 OLDX is the address as it was before break_out_memory_refs was called.
881 In some cases it is useful to look at this to decide what needs to be done.
883 MODE and WIN are passed so that this macro can use
884 GO_IF_LEGITIMATE_ADDRESS.
886 It is always safe for this macro to do nothing. It exists to recognize
887 opportunities to optimize the output.
889 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
891 rtx _q = legitimize_address(X, OLDX, MODE); \
892 if (_q) { X = _q; goto WIN; } \
895 #define HAVE_POST_INCREMENT 1
896 #define HAVE_POST_DECREMENT 1
897 #define HAVE_PRE_DECREMENT 1
899 /* `LEGITIMATE_PIC_OPERAND_P (X)'
900 A C expression that is nonzero if X is a legitimate immediate
901 operand on the target machine when generating position independent
902 code. You can assume that X satisfies `CONSTANT_P', so you need
903 not check this. You can also assume FLAG_PIC is true, so you need
904 not check it either. You need not define this macro if all
905 constants (including `SYMBOL_REF') can be immediate operands when
906 generating position independent code. */
907 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
909 #define SYMBOLIC_CONST(X) \
910 (GET_CODE (X) == SYMBOL_REF \
911 || GET_CODE (X) == LABEL_REF \
912 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
915 A C statement or compound statement with a conditional `goto
916 LABEL;' executed if memory address X (an RTX) can have different
917 meanings depending on the machine mode of the memory reference it
918 is used for or if the address is valid for some modes but not
921 Autoincrement and autodecrement addresses typically have
922 mode-dependent effects because the amount of the increment or
923 decrement is the size of the operand being addressed. Some
924 machines have other mode-dependent addresses. Many RISC machines
925 have no mode-dependent addresses.
927 You may assume that ADDR is a valid address for the machine.
929 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
931 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
933 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
934 is done just by pretending it is already truncated. */
935 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
937 /* Max number of bytes we can move from memory to memory
938 in one reasonably fast instruction. */
939 #define MOVE_MAX UNITS_PER_WORD
941 /* If a memory-to-memory move would take MOVE_RATIO or more simple
942 move-instruction pairs, we will do a movmem or libcall instead. */
946 /* STORAGE LAYOUT: target machine storage layout
947 Define this macro as a C expression which is nonzero if accessing
948 less than a word of memory (i.e. a `char' or a `short') is no
949 faster than accessing a word of memory, i.e., if such access
950 require more than one instruction or if there is no difference in
951 cost between byte and (aligned) word loads.
953 When this macro is not defined, the compiler will access a field by
954 finding the smallest containing object; when it is defined, a
955 fullword load will be used if alignment permits. Unless bytes
956 accesses are faster than word accesses, using word accesses is
957 preferable since it may eliminate subsequent memory access if
958 subsequent accesses occur to other fields in the same word of the
959 structure, but to different bytes. */
960 #define SLOW_BYTE_ACCESS 0
961 #define SLOW_SHORT_ACCESS 0
963 /* Define this if most significant bit is lowest numbered
964 in instructions that operate on numbered bit-fields. */
965 #define BITS_BIG_ENDIAN 0
967 /* Define this if most significant byte of a word is the lowest numbered.
968 We can't access bytes but if we could we would in the Big Endian order. */
969 #define BYTES_BIG_ENDIAN 0
971 /* Define this if most significant word of a multiword number is numbered. */
972 #define WORDS_BIG_ENDIAN 0
974 /* number of bits in an addressable storage unit */
975 #define BITS_PER_UNIT 8
977 /* Width in bits of a "word", which is the contents of a machine register.
978 Note that this is not necessarily the width of data type `int';
979 if using 16-bit ints on a 68000, this would still be 32.
980 But on a machine with 16-bit registers, this would be 16. */
981 #define BITS_PER_WORD 32
983 /* Width of a word, in units (bytes). */
984 #define UNITS_PER_WORD 4
986 /* Width in bits of a pointer.
987 See also the macro `Pmode1' defined below. */
988 #define POINTER_SIZE 32
990 /* Allocation boundary (in *bits*) for storing pointers in memory. */
991 #define POINTER_BOUNDARY 32
993 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
994 #define PARM_BOUNDARY 32
996 /* Boundary (in *bits*) on which stack pointer should be aligned. */
997 #define STACK_BOUNDARY 32
999 /* Allocation boundary (in *bits*) for the code of a function. */
1000 #define FUNCTION_BOUNDARY 32
1002 /* Alignment of field after `int : 0' in a structure. */
1003 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1005 /* No data type wants to be aligned rounder than this. */
1006 #define BIGGEST_ALIGNMENT 32
1008 /* Define this if move instructions will actually fail to work
1009 when given unaligned data. */
1010 #define STRICT_ALIGNMENT 1
1012 /* (shell-command "rm c-decl.o stor-layout.o")
1013 * never define PCC_BITFIELD_TYPE_MATTERS
1014 * really cause some alignment problem
1017 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1020 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1024 /* what is the 'type' of size_t */
1025 #define SIZE_TYPE "long unsigned int"
1027 /* Define this as 1 if `char' should by default be signed; else as 0. */
1028 #define DEFAULT_SIGNED_CHAR 1
1029 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1030 #define SHORT_TYPE_SIZE 16
1031 #define CHAR_TYPE_SIZE 8
1032 #define INT_TYPE_SIZE 32
1033 #define LONG_TYPE_SIZE 32
1034 #define LONG_LONG_TYPE_SIZE 64
1036 /* Note: Fix this to depend on target switch. -- lev */
1038 /* Note: Try to implement double and force long double. -- tonyko
1039 * #define __DOUBLES_ARE_FLOATS__
1040 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1041 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1042 * #define DOUBLES_ARE_FLOATS 1
1045 #define DOUBLE_TYPE_SIZE 64
1046 #define LONG_DOUBLE_TYPE_SIZE 64
1048 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1049 A macro to update M and UNSIGNEDP when an object whose type is
1050 TYPE and which has the specified mode and signedness is to be
1051 stored in a register. This macro is only called when TYPE is a
1054 On most RISC machines, which only have operations that operate on
1055 a full register, define this macro to set M to `word_mode' if M is
1056 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1057 only integer modes should be widened because wider-precision
1058 floating-point operations are usually more expensive than their
1059 narrower counterparts.
1061 For most machines, the macro definition does not change UNSIGNEDP.
1062 However, some machines, have instructions that preferentially
1063 handle either signed or unsigned quantities of certain modes. For
1064 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1065 instructions sign-extend the result to 64 bits. On such machines,
1066 set UNSIGNEDP according to which kind of extension is more
1069 Do not define this macro if it would never modify M.*/
1071 #define BFIN_PROMOTE_MODE_P(MODE) \
1072 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1073 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1075 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1076 if (BFIN_PROMOTE_MODE_P(MODE)) \
1078 if (MODE == QImode) \
1080 else if (MODE == HImode) \
1085 /* Describing Relative Costs of Operations */
1087 /* Do not put function addr into constant pool */
1088 #define NO_FUNCTION_CSE 1
1090 /* A C expression for the cost of moving data from a register in class FROM to
1091 one in class TO. The classes are expressed using the enumeration values
1092 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1093 interpreted relative to that.
1095 It is not required that the cost always equal 2 when FROM is the same as TO;
1096 on some machines it is expensive to move between registers if they are not
1097 general registers. */
1099 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1100 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1102 /* A C expression for the cost of moving data of mode M between a
1103 register and memory. A value of 2 is the default; this cost is
1104 relative to those in `REGISTER_MOVE_COST'.
1106 If moving between registers and memory is more expensive than
1107 between two registers, you should define this macro to express the
1110 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1111 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1113 /* Specify the machine mode that this machine uses
1114 for the index in the tablejump instruction. */
1115 #define CASE_VECTOR_MODE SImode
1117 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1119 /* Define if operations between registers always perform the operation
1120 on the full register even if a narrower mode is specified.
1121 #define WORD_REGISTER_OPERATIONS
1124 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
1125 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
1126 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
1127 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
1128 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
1129 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
1130 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
1131 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
1132 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
1133 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
1135 #define CONSTRAINT_LEN(C, STR) \
1136 ((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2 \
1138 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1140 #define CONST_OK_FOR_P(VALUE, STR) \
1141 ((STR)[1] == '0' ? (VALUE) == 0 \
1142 : (STR)[1] == '1' ? (VALUE) == 1 \
1143 : (STR)[1] == '2' ? (VALUE) == 2 \
1144 : (STR)[1] == '3' ? (VALUE) == 3 \
1145 : (STR)[1] == '4' ? (VALUE) == 4 \
1146 : (STR)[1] == 'A' ? (VALUE) != MACFLAG_M && (VALUE) != MACFLAG_IS_M \
1147 : (STR)[1] == 'B' ? (VALUE) == MACFLAG_M || (VALUE) == MACFLAG_IS_M \
1150 #define CONST_OK_FOR_K(VALUE, STR) \
1152 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
1153 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
1154 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
1155 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
1158 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
1159 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
1160 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
1161 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
1164 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
1167 ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \
1171 #define CONST_OK_FOR_M(VALUE, STR) \
1172 ((STR)[1] == '1' ? (VALUE) == 255 \
1173 : (STR)[1] == '2' ? (VALUE) == 65535 \
1176 /* The letters I, J, K, L and M in a register constraint string
1177 can be used to stand for particular ranges of immediate operands.
1178 This macro defines what the ranges are.
1179 C is the letter, and VALUE is a constant value.
1180 Return 1 if VALUE is in the range specified by C.
1182 bfin constant operands are as follows
1184 J 2**N 5bit imm scaled
1185 Ks7 -64 .. 63 signed 7bit imm
1186 Ku5 0..31 unsigned 5bit imm
1187 Ks4 -8 .. 7 signed 4bit imm
1188 Ks3 -4 .. 3 signed 3bit imm
1189 Ku3 0 .. 7 unsigned 3bit imm
1190 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
1192 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1193 ((C) == 'J' ? (log2constp (VALUE)) \
1194 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
1195 : (C) == 'L' ? log2constp (~(VALUE)) \
1196 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
1197 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
1200 /*Constant Output Formats */
1201 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1202 ((C) == 'H' ? 1 : 0)
1204 #define EXTRA_CONSTRAINT(VALUE, D) \
1205 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1207 /* Evaluates to true if A and B are mac flags that can be used
1208 together in a single multiply insn. That is the case if they are
1209 both the same flag not involving M, or if one is a combination of
1210 the other with M. */
1211 #define MACFLAGS_MATCH_P(A, B) \
1213 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1214 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1215 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1216 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1218 /* Switch into a generic section. */
1219 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1221 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1222 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1224 typedef enum sections {
1230 typedef enum directives {
1239 #define TEXT_SECTION_ASM_OP ".text;"
1240 #define DATA_SECTION_ASM_OP ".data;"
1242 #define ASM_APP_ON ""
1243 #define ASM_APP_OFF ""
1245 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1246 do { fputs (".global ", FILE); \
1247 assemble_name (FILE, NAME); \
1249 fputc ('\n',FILE); \
1252 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1254 fputs (".type ", FILE); \
1255 assemble_name (FILE, NAME); \
1256 fputs (", STT_FUNC", FILE); \
1258 fputc ('\n',FILE); \
1259 ASM_OUTPUT_LABEL(FILE, NAME); \
1262 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1263 do { assemble_name (FILE, NAME); \
1264 fputs (":\n",FILE); \
1267 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1268 do { fprintf (FILE, "_%s", NAME); \
1271 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1272 do { char __buf[256]; \
1273 fprintf (FILE, "\t.dd\t"); \
1274 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1275 assemble_name (FILE, __buf); \
1276 fputc (';', FILE); \
1277 fputc ('\n', FILE); \
1280 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1281 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1283 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1286 fprintf (FILE, "\t.dd\t"); \
1287 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1288 assemble_name (FILE, __buf); \
1289 fputs (" - ", FILE); \
1290 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1291 assemble_name (FILE, __buf); \
1292 fputc (';', FILE); \
1293 fputc ('\n', FILE); \
1296 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1299 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1302 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1304 asm_output_skip (FILE, SIZE); \
1307 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1309 switch_to_section (data_section); \
1310 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1311 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1312 ASM_OUTPUT_LABEL (FILE, NAME); \
1313 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1314 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1317 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1319 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1320 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1322 #define ASM_COMMENT_START "//"
1324 #define FUNCTION_PROFILER(FILE, LABELNO) \
1326 fprintf (FILE, "\tCALL __mcount;\n"); \
1329 #undef NO_PROFILE_COUNTERS
1330 #define NO_PROFILE_COUNTERS 1
1332 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1333 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1335 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1336 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1338 /* This works for GAS and some other assemblers. */
1339 #define SET_ASM_OP ".set "
1341 /* DBX register number for a given compiler register number */
1342 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1344 #define SIZE_ASM_OP "\t.size\t"
1346 extern int splitting_for_sched;
1348 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1350 #endif /* _BFIN_CONFIG */