1 ;; -*- Mode: Scheme -*-
2 ;; Machine description for GNU compiler,
3 ;; for ATMEL AVR micro controllers.
4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
5 ;; 2009, 2010 Free Software Foundation, Inc.
6 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; Special characters after '%':
25 ;; A No effect (add 0).
26 ;; B Add 1 to REG number, MEM address or CONST_INT.
29 ;; j Branch condition.
30 ;; k Reverse branch condition.
31 ;;..m..Constant Direct Data memory address.
32 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
33 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
34 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
35 ;;..x..Constant Direct Program memory address.
36 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
37 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
40 ;; 0 Length of a string, see "strlenhi".
41 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
49 (TMP_REGNO 0) ; temporary register r0
50 (ZERO_REGNO 1) ; zero register r1
60 (UNSPECV_PROLOGUE_SAVES 0)
61 (UNSPECV_EPILOGUE_RESTORES 1)
62 (UNSPECV_WRITE_SP_IRQ_ON 2)
63 (UNSPECV_WRITE_SP_IRQ_OFF 3)
64 (UNSPECV_GOTO_RECEIVER 4)])
66 (include "predicates.md")
67 (include "constraints.md")
69 ;; Condition code settings.
70 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
71 (const_string "none"))
73 (define_attr "type" "branch,branch1,arith,xcall"
74 (const_string "arith"))
76 (define_attr "mcu_have_movw" "yes,no"
77 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
79 (const_string "no"))))
81 (define_attr "mcu_mega" "yes,no"
82 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
84 (const_string "no"))))
87 ;; The size of instructions in bytes.
88 ;; XXX may depend from "cc"
90 (define_attr "length" ""
91 (cond [(eq_attr "type" "branch")
92 (if_then_else (and (ge (minus (pc) (match_dup 0))
94 (le (minus (pc) (match_dup 0))
97 (if_then_else (and (ge (minus (pc) (match_dup 0))
99 (le (minus (pc) (match_dup 0))
103 (eq_attr "type" "branch1")
104 (if_then_else (and (ge (minus (pc) (match_dup 0))
106 (le (minus (pc) (match_dup 0))
109 (if_then_else (and (ge (minus (pc) (match_dup 0))
111 (le (minus (pc) (match_dup 0))
115 (eq_attr "type" "xcall")
116 (if_then_else (eq_attr "mcu_mega" "no")
121 ;; Define mode iterator
122 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
123 (define_mode_iterator QIDI [(QI "") (HI "") (SI "") (DI "")])
124 (define_mode_iterator HIDI [(HI "") (SI "") (DI "")])
125 (define_mode_iterator HISI [(HI "") (SI "")])
127 ;;========================================================================
128 ;; The following is used by nonlocal_goto and setjmp.
129 ;; The receiver pattern will create no instructions since internally
130 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
131 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
132 ;; The 'null' receiver also avoids problems with optimisation
133 ;; not recognising incoming jmp and removing code that resets frame_pointer.
134 ;; The code derived from builtins.c.
136 (define_expand "nonlocal_goto_receiver"
138 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
141 emit_move_insn (virtual_stack_vars_rtx,
142 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
143 gen_int_mode (STARTING_FRAME_OFFSET,
145 /* This might change the hard frame pointer in ways that aren't
146 apparent to early optimization passes, so force a clobber. */
147 emit_clobber (hard_frame_pointer_rtx);
152 ;; Defining nonlocal_goto_receiver means we must also define this.
153 ;; even though its function is identical to that in builtins.c
155 (define_expand "nonlocal_goto"
157 (use (match_operand 0 "general_operand"))
158 (use (match_operand 1 "general_operand"))
159 (use (match_operand 2 "general_operand"))
160 (use (match_operand 3 "general_operand"))
164 rtx r_label = copy_to_reg (operands[1]);
165 rtx r_fp = operands[3];
166 rtx r_sp = operands[2];
168 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
170 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
172 emit_move_insn (hard_frame_pointer_rtx, r_fp);
173 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
175 emit_use (hard_frame_pointer_rtx);
176 emit_use (stack_pointer_rtx);
178 emit_indirect_jump (r_label);
184 (define_insn "*pushqi"
185 [(set (mem:QI (post_dec (reg:HI REG_SP)))
186 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
191 [(set_attr "length" "1,1")])
194 (define_insn "*pushhi"
195 [(set (mem:HI (post_dec (reg:HI REG_SP)))
196 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
200 push __zero_reg__\;push __zero_reg__"
201 [(set_attr "length" "2,2")])
203 (define_insn "*pushsi"
204 [(set (mem:SI (post_dec (reg:HI REG_SP)))
205 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
208 push %D0\;push %C0\;push %B0\;push %A0
209 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
210 [(set_attr "length" "4,4")])
212 (define_insn "*pushsf"
213 [(set (mem:SF (post_dec (reg:HI REG_SP)))
214 (match_operand:SF 0 "register_operand" "r"))]
220 [(set_attr "length" "4")])
222 ;;========================================================================
224 ;; The last alternative (any immediate constant to any register) is
225 ;; very expensive. It should be optimized by peephole2 if a scratch
226 ;; register is available, but then that register could just as well be
227 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
228 ;; are call-saved registers, and most of LD_REGS are call-used registers,
229 ;; so this may still be a win for registers live across function calls.
231 (define_expand "movqi"
232 [(set (match_operand:QI 0 "nonimmediate_operand" "")
233 (match_operand:QI 1 "general_operand" ""))]
235 "/* One of the ops has to be in a register. */
236 if (!register_operand(operand0, QImode)
237 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
238 operands[1] = copy_to_mode_reg(QImode, operand1);
241 (define_insn "*movqi"
242 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
243 (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))]
244 "(register_operand (operands[0],QImode)
245 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
246 "* return output_movqi (insn, operands, NULL);"
247 [(set_attr "length" "1,1,5,5,1,1,4")
248 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
250 ;; This is used in peephole2 to optimize loading immediate constants
251 ;; if a scratch register from LD_REGS happens to be available.
253 (define_insn "*reload_inqi"
254 [(set (match_operand:QI 0 "register_operand" "=l")
255 (match_operand:QI 1 "immediate_operand" "i"))
256 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
260 [(set_attr "length" "2")
261 (set_attr "cc" "none")])
264 [(match_scratch:QI 2 "d")
265 (set (match_operand:QI 0 "l_register_operand" "")
266 (match_operand:QI 1 "immediate_operand" ""))]
267 "(operands[1] != const0_rtx
268 && operands[1] != const1_rtx
269 && operands[1] != constm1_rtx)"
270 [(parallel [(set (match_dup 0) (match_dup 1))
271 (clobber (match_dup 2))])]
274 ;;============================================================================
275 ;; move word (16 bit)
277 (define_expand "movhi"
278 [(set (match_operand:HI 0 "nonimmediate_operand" "")
279 (match_operand:HI 1 "general_operand" ""))]
283 /* One of the ops has to be in a register. */
284 if (!register_operand(operand0, HImode)
285 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
287 operands[1] = copy_to_mode_reg(HImode, operand1);
291 (define_insn "*movhi_sp"
292 [(set (match_operand:HI 0 "register_operand" "=q,r")
293 (match_operand:HI 1 "register_operand" "r,q"))]
294 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
295 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
296 "* return output_movhi (insn, operands, NULL);"
297 [(set_attr "length" "5,2")
298 (set_attr "cc" "none,none")])
300 (define_insn "movhi_sp_r_irq_off"
301 [(set (match_operand:HI 0 "stack_register_operand" "=q")
302 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
303 UNSPECV_WRITE_SP_IRQ_OFF))]
307 [(set_attr "length" "2")
308 (set_attr "cc" "none")])
310 (define_insn "movhi_sp_r_irq_on"
311 [(set (match_operand:HI 0 "stack_register_operand" "=q")
312 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
313 UNSPECV_WRITE_SP_IRQ_ON))]
319 [(set_attr "length" "4")
320 (set_attr "cc" "none")])
323 [(match_scratch:QI 2 "d")
324 (set (match_operand:HI 0 "l_register_operand" "")
325 (match_operand:HI 1 "immediate_operand" ""))]
326 "(operands[1] != const0_rtx
327 && operands[1] != constm1_rtx)"
328 [(parallel [(set (match_dup 0) (match_dup 1))
329 (clobber (match_dup 2))])]
332 ;; '*' because it is not used in rtl generation, only in above peephole
333 (define_insn "*reload_inhi"
334 [(set (match_operand:HI 0 "register_operand" "=r")
335 (match_operand:HI 1 "immediate_operand" "i"))
336 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
338 "* return output_reload_inhi (insn, operands, NULL);"
339 [(set_attr "length" "4")
340 (set_attr "cc" "none")])
342 (define_insn "*movhi"
343 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
344 (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))]
345 "(register_operand (operands[0],HImode)
346 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
347 "* return output_movhi (insn, operands, NULL);"
348 [(set_attr "length" "2,6,7,2,6,5,2")
349 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
351 (define_peephole2 ; movw
352 [(set (match_operand:QI 0 "even_register_operand" "")
353 (match_operand:QI 1 "even_register_operand" ""))
354 (set (match_operand:QI 2 "odd_register_operand" "")
355 (match_operand:QI 3 "odd_register_operand" ""))]
357 && REGNO (operands[0]) == REGNO (operands[2]) - 1
358 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
359 [(set (match_dup 4) (match_dup 5))]
361 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
362 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
365 (define_peephole2 ; movw_r
366 [(set (match_operand:QI 0 "odd_register_operand" "")
367 (match_operand:QI 1 "odd_register_operand" ""))
368 (set (match_operand:QI 2 "even_register_operand" "")
369 (match_operand:QI 3 "even_register_operand" ""))]
371 && REGNO (operands[2]) == REGNO (operands[0]) - 1
372 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
373 [(set (match_dup 4) (match_dup 5))]
375 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
376 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
379 ;;==========================================================================
380 ;; move double word (32 bit)
382 (define_expand "movsi"
383 [(set (match_operand:SI 0 "nonimmediate_operand" "")
384 (match_operand:SI 1 "general_operand" ""))]
388 /* One of the ops has to be in a register. */
389 if (!register_operand (operand0, SImode)
390 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
392 operands[1] = copy_to_mode_reg (SImode, operand1);
398 (define_peephole2 ; movsi_lreg_const
399 [(match_scratch:QI 2 "d")
400 (set (match_operand:SI 0 "l_register_operand" "")
401 (match_operand:SI 1 "immediate_operand" ""))
403 "(operands[1] != const0_rtx
404 && operands[1] != constm1_rtx)"
405 [(parallel [(set (match_dup 0) (match_dup 1))
406 (clobber (match_dup 2))])]
409 ;; '*' because it is not used in rtl generation.
410 (define_insn "*reload_insi"
411 [(set (match_operand:SI 0 "register_operand" "=r")
412 (match_operand:SI 1 "immediate_operand" "i"))
413 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
415 "* return output_reload_insisf (insn, operands, NULL);"
416 [(set_attr "length" "8")
417 (set_attr "cc" "none")])
420 (define_insn "*movsi"
421 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
422 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
423 "(register_operand (operands[0],SImode)
424 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
425 "* return output_movsisf (insn, operands, NULL);"
426 [(set_attr "length" "4,4,8,9,4,10")
427 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
429 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
430 ;; move floating point numbers (32 bit)
432 (define_expand "movsf"
433 [(set (match_operand:SF 0 "nonimmediate_operand" "")
434 (match_operand:SF 1 "general_operand" ""))]
438 /* One of the ops has to be in a register. */
439 if (!register_operand (operand1, SFmode)
440 && !register_operand (operand0, SFmode))
442 operands[1] = copy_to_mode_reg (SFmode, operand1);
446 (define_insn "*movsf"
447 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
448 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
449 "register_operand (operands[0], SFmode)
450 || register_operand (operands[1], SFmode)"
451 "* return output_movsisf (insn, operands, NULL);"
452 [(set_attr "length" "4,4,8,9,4,10")
453 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
455 ;;=========================================================================
456 ;; move string (like memcpy)
457 ;; implement as RTL loop
459 (define_expand "movmemhi"
460 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
461 (match_operand:BLK 1 "memory_operand" ""))
462 (use (match_operand:HI 2 "const_int_operand" ""))
463 (use (match_operand:HI 3 "const_int_operand" ""))])]
468 enum machine_mode mode;
469 rtx label = gen_label_rtx ();
473 /* Copy pointers into new psuedos - they will be changed. */
474 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
475 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
477 /* Create rtx for tmp register - we use this as scratch. */
478 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
480 if (GET_CODE (operands[2]) != CONST_INT)
483 count = INTVAL (operands[2]);
487 /* Work out branch probability for latter use. */
488 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
490 /* See if constant fit 8 bits. */
491 mode = (count < 0x100) ? QImode : HImode;
492 /* Create loop counter register. */
493 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
495 /* Now create RTL code for move loop. */
496 /* Label at top of loop. */
499 /* Move one byte into scratch and inc pointer. */
500 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
501 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
503 /* Move to mem and inc pointer. */
504 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
505 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
507 /* Decrement count. */
508 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
510 /* Compare with zero and jump if not equal. */
511 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
513 /* Set jump probability based on loop count. */
514 jump = get_last_insn ();
515 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
519 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
520 ;; memset (%0, %2, %1)
522 (define_expand "setmemhi"
523 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
524 (match_operand 2 "const_int_operand" ""))
525 (use (match_operand:HI 1 "const_int_operand" ""))
526 (use (match_operand:HI 3 "const_int_operand" "n"))
527 (clobber (match_scratch:HI 4 ""))
528 (clobber (match_dup 5))])]
533 enum machine_mode mode;
535 /* If value to set is not zero, use the library routine. */
536 if (operands[2] != const0_rtx)
539 if (GET_CODE (operands[1]) != CONST_INT)
542 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
543 mode = cnt8 ? QImode : HImode;
544 operands[5] = gen_rtx_SCRATCH (mode);
545 operands[1] = copy_to_mode_reg (mode,
546 gen_int_mode (INTVAL (operands[1]), mode));
547 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
548 operands[0] = gen_rtx_MEM (BLKmode, addr0);
551 (define_insn "*clrmemqi"
552 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
554 (use (match_operand:QI 1 "register_operand" "r"))
555 (use (match_operand:QI 2 "const_int_operand" "n"))
556 (clobber (match_scratch:HI 3 "=0"))
557 (clobber (match_scratch:QI 4 "=&1"))]
559 "st %a0+,__zero_reg__
562 [(set_attr "length" "3")
563 (set_attr "cc" "clobber")])
565 (define_insn "*clrmemhi"
566 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
568 (use (match_operand:HI 1 "register_operand" "!w,d"))
569 (use (match_operand:HI 2 "const_int_operand" "n,n"))
570 (clobber (match_scratch:HI 3 "=0,0"))
571 (clobber (match_scratch:HI 4 "=&1,&1"))]
574 if (which_alternative==0)
575 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
576 AS2 (sbiw,%A1,1) CR_TAB
579 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
580 AS2 (subi,%A1,1) CR_TAB
581 AS2 (sbci,%B1,0) CR_TAB
584 [(set_attr "length" "3,4")
585 (set_attr "cc" "clobber,clobber")])
587 (define_expand "strlenhi"
589 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
590 (match_operand:QI 2 "const_int_operand" "")
591 (match_operand:HI 3 "immediate_operand" "")]
593 (set (match_dup 4) (plus:HI (match_dup 4)
595 (set (match_operand:HI 0 "register_operand" "")
596 (minus:HI (match_dup 4)
601 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
603 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
604 operands[1] = gen_rtx_MEM (BLKmode, addr);
606 operands[4] = gen_reg_rtx (HImode);
609 (define_insn "*strlenhi"
610 [(set (match_operand:HI 0 "register_operand" "=e")
611 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
613 (match_operand:HI 2 "immediate_operand" "i")]
619 [(set_attr "length" "3")
620 (set_attr "cc" "clobber")])
622 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
625 (define_insn "addqi3"
626 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
627 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
628 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
635 [(set_attr "length" "1,1,1,1")
636 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
639 (define_expand "addhi3"
640 [(set (match_operand:HI 0 "register_operand" "")
641 (plus:HI (match_operand:HI 1 "register_operand" "")
642 (match_operand:HI 2 "nonmemory_operand" "")))]
646 if (GET_CODE (operands[2]) == CONST_INT)
648 short tmp = INTVAL (operands[2]);
649 operands[2] = GEN_INT(tmp);
654 (define_insn "*addhi3_zero_extend"
655 [(set (match_operand:HI 0 "register_operand" "=r")
656 (plus:HI (zero_extend:HI
657 (match_operand:QI 1 "register_operand" "r"))
658 (match_operand:HI 2 "register_operand" "0")))]
661 adc %B0,__zero_reg__"
662 [(set_attr "length" "2")
663 (set_attr "cc" "set_n")])
665 (define_insn "*addhi3_zero_extend1"
666 [(set (match_operand:HI 0 "register_operand" "=r")
667 (plus:HI (match_operand:HI 1 "register_operand" "%0")
669 (match_operand:QI 2 "register_operand" "r"))))]
672 adc %B0,__zero_reg__"
673 [(set_attr "length" "2")
674 (set_attr "cc" "set_n")])
676 (define_insn "*addhi3_sp_R_pc2"
677 [(set (match_operand:HI 1 "stack_register_operand" "=q")
678 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
679 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
682 if (CONST_INT_P (operands[0]))
684 switch(INTVAL (operands[0]))
687 return \"rcall .\" CR_TAB
691 return \"rcall .\" CR_TAB
693 \"push __tmp_reg__\";
695 return \"rcall .\" CR_TAB
698 return \"rcall .\" CR_TAB
699 \"push __tmp_reg__\";
703 return \"push __tmp_reg__\";
707 return \"pop __tmp_reg__\";
709 return \"pop __tmp_reg__\" CR_TAB
712 return \"pop __tmp_reg__\" CR_TAB
713 \"pop __tmp_reg__\" CR_TAB
716 return \"pop __tmp_reg__\" CR_TAB
717 \"pop __tmp_reg__\" CR_TAB
718 \"pop __tmp_reg__\" CR_TAB
721 return \"pop __tmp_reg__\" CR_TAB
722 \"pop __tmp_reg__\" CR_TAB
723 \"pop __tmp_reg__\" CR_TAB
724 \"pop __tmp_reg__\" CR_TAB
730 [(set (attr "length")
731 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
732 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
733 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
734 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
735 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
736 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
737 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
738 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
739 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
740 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
741 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
742 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
745 (define_insn "*addhi3_sp_R_pc3"
746 [(set (match_operand:HI 1 "stack_register_operand" "=q")
747 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
748 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
751 if (CONST_INT_P (operands[0]))
753 switch(INTVAL (operands[0]))
756 return \"rcall .\" CR_TAB
759 return \"rcall .\" CR_TAB
760 \"push __tmp_reg__\" CR_TAB
761 \"push __tmp_reg__\";
763 return \"rcall .\" CR_TAB
764 \"push __tmp_reg__\";
768 return \"push __tmp_reg__\" CR_TAB
769 \"push __tmp_reg__\";
771 return \"push __tmp_reg__\";
775 return \"pop __tmp_reg__\";
777 return \"pop __tmp_reg__\" CR_TAB
780 return \"pop __tmp_reg__\" CR_TAB
781 \"pop __tmp_reg__\" CR_TAB
784 return \"pop __tmp_reg__\" CR_TAB
785 \"pop __tmp_reg__\" CR_TAB
786 \"pop __tmp_reg__\" CR_TAB
789 return \"pop __tmp_reg__\" CR_TAB
790 \"pop __tmp_reg__\" CR_TAB
791 \"pop __tmp_reg__\" CR_TAB
792 \"pop __tmp_reg__\" CR_TAB
798 [(set (attr "length")
799 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
800 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
801 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
802 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
803 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
804 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
805 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
806 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
807 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
808 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
809 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
810 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
813 (define_insn "*addhi3"
814 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
816 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
817 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
820 add %A0,%A2\;adc %B0,%B2
823 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
824 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
825 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
826 [(set_attr "length" "2,1,1,2,3,3")
827 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
829 (define_insn "addsi3"
830 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
832 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
833 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
836 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
837 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
838 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
839 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
840 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
841 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
842 [(set_attr "length" "4,3,3,4,5,5")
843 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
845 (define_insn "*addsi3_zero_extend"
846 [(set (match_operand:SI 0 "register_operand" "=r")
847 (plus:SI (zero_extend:SI
848 (match_operand:QI 1 "register_operand" "r"))
849 (match_operand:SI 2 "register_operand" "0")))]
854 adc %D0,__zero_reg__"
855 [(set_attr "length" "4")
856 (set_attr "cc" "set_n")])
858 ;-----------------------------------------------------------------------------
860 (define_insn "subqi3"
861 [(set (match_operand:QI 0 "register_operand" "=r,d")
862 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
863 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
868 [(set_attr "length" "1,1")
869 (set_attr "cc" "set_czn,set_czn")])
871 (define_insn "subhi3"
872 [(set (match_operand:HI 0 "register_operand" "=r,d")
873 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
874 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
877 sub %A0,%A2\;sbc %B0,%B2
878 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
879 [(set_attr "length" "2,2")
880 (set_attr "cc" "set_czn,set_czn")])
882 (define_insn "*subhi3_zero_extend1"
883 [(set (match_operand:HI 0 "register_operand" "=r")
884 (minus:HI (match_operand:HI 1 "register_operand" "0")
886 (match_operand:QI 2 "register_operand" "r"))))]
889 sbc %B0,__zero_reg__"
890 [(set_attr "length" "2")
891 (set_attr "cc" "set_n")])
893 (define_insn "subsi3"
894 [(set (match_operand:SI 0 "register_operand" "=r,d")
895 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
896 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
899 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
900 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
901 [(set_attr "length" "4,4")
902 (set_attr "cc" "set_czn,set_czn")])
904 (define_insn "*subsi3_zero_extend"
905 [(set (match_operand:SI 0 "register_operand" "=r")
906 (minus:SI (match_operand:SI 1 "register_operand" "0")
908 (match_operand:QI 2 "register_operand" "r"))))]
913 sbc %D0,__zero_reg__"
914 [(set_attr "length" "4")
915 (set_attr "cc" "set_n")])
917 ;******************************************************************************
920 (define_expand "mulqi3"
921 [(set (match_operand:QI 0 "register_operand" "")
922 (mult:QI (match_operand:QI 1 "register_operand" "")
923 (match_operand:QI 2 "register_operand" "")))]
928 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
933 (define_insn "*mulqi3_enh"
934 [(set (match_operand:QI 0 "register_operand" "=r")
935 (mult:QI (match_operand:QI 1 "register_operand" "r")
936 (match_operand:QI 2 "register_operand" "r")))]
941 [(set_attr "length" "3")
942 (set_attr "cc" "clobber")])
944 (define_expand "mulqi3_call"
945 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
946 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
947 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
948 (clobber (reg:QI 22))])
949 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
953 (define_insn "*mulqi3_call"
954 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
955 (clobber (reg:QI 22))]
958 [(set_attr "type" "xcall")
959 (set_attr "cc" "clobber")])
961 (define_insn "mulqihi3"
962 [(set (match_operand:HI 0 "register_operand" "=r")
963 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
964 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
969 [(set_attr "length" "3")
970 (set_attr "cc" "clobber")])
972 (define_insn "umulqihi3"
973 [(set (match_operand:HI 0 "register_operand" "=r")
974 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
975 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
980 [(set_attr "length" "3")
981 (set_attr "cc" "clobber")])
983 (define_expand "mulhi3"
984 [(set (match_operand:HI 0 "register_operand" "")
985 (mult:HI (match_operand:HI 1 "register_operand" "")
986 (match_operand:HI 2 "register_operand" "")))]
992 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
997 (define_insn "*mulhi3_enh"
998 [(set (match_operand:HI 0 "register_operand" "=&r")
999 (mult:HI (match_operand:HI 1 "register_operand" "r")
1000 (match_operand:HI 2 "register_operand" "r")))]
1009 [(set_attr "length" "7")
1010 (set_attr "cc" "clobber")])
1012 (define_expand "mulhi3_call"
1013 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1014 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1015 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1016 (clobber (reg:HI 22))
1017 (clobber (reg:QI 21))])
1018 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
1022 (define_insn "*mulhi3_call"
1023 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1024 (clobber (reg:HI 22))
1025 (clobber (reg:QI 21))]
1028 [(set_attr "type" "xcall")
1029 (set_attr "cc" "clobber")])
1031 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
1032 ;; All call-used registers clobbered otherwise - normal library call.
1033 (define_expand "mulsi3"
1034 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1035 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1036 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1037 (clobber (reg:HI 26))
1038 (clobber (reg:HI 30))])
1039 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
1043 (define_insn "*mulsi3_call"
1044 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1045 (clobber (reg:HI 26))
1046 (clobber (reg:HI 30))]
1049 [(set_attr "type" "xcall")
1050 (set_attr "cc" "clobber")])
1052 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
1055 ;; Generate libgcc.S calls ourselves, because:
1056 ;; - we know exactly which registers are clobbered (for QI and HI
1057 ;; modes, some of the call-used registers are preserved)
1058 ;; - we get both the quotient and the remainder at no extra cost
1059 ;; - we split the patterns only after the first CSE passes because
1060 ;; CSE has problems to operate on hard regs.
1062 (define_insn_and_split "divmodqi4"
1063 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1064 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
1065 (match_operand:QI 2 "pseudo_register_operand" "")))
1066 (set (match_operand:QI 3 "pseudo_register_operand" "")
1067 (mod:QI (match_dup 1) (match_dup 2)))
1068 (clobber (reg:QI 22))
1069 (clobber (reg:QI 23))
1070 (clobber (reg:QI 24))
1071 (clobber (reg:QI 25))])]
1073 "this divmodqi4 pattern should have been splitted;"
1075 [(set (reg:QI 24) (match_dup 1))
1076 (set (reg:QI 22) (match_dup 2))
1077 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1078 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1079 (clobber (reg:QI 22))
1080 (clobber (reg:QI 23))])
1081 (set (match_dup 0) (reg:QI 24))
1082 (set (match_dup 3) (reg:QI 25))]
1085 (define_insn "*divmodqi4_call"
1086 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1087 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1088 (clobber (reg:QI 22))
1089 (clobber (reg:QI 23))]
1091 "%~call __divmodqi4"
1092 [(set_attr "type" "xcall")
1093 (set_attr "cc" "clobber")])
1095 (define_insn_and_split "udivmodqi4"
1096 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1097 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
1098 (match_operand:QI 2 "pseudo_register_operand" "")))
1099 (set (match_operand:QI 3 "pseudo_register_operand" "")
1100 (umod:QI (match_dup 1) (match_dup 2)))
1101 (clobber (reg:QI 22))
1102 (clobber (reg:QI 23))
1103 (clobber (reg:QI 24))
1104 (clobber (reg:QI 25))])]
1106 "this udivmodqi4 pattern should have been splitted;"
1108 [(set (reg:QI 24) (match_dup 1))
1109 (set (reg:QI 22) (match_dup 2))
1110 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1111 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1112 (clobber (reg:QI 23))])
1113 (set (match_dup 0) (reg:QI 24))
1114 (set (match_dup 3) (reg:QI 25))]
1117 (define_insn "*udivmodqi4_call"
1118 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1119 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1120 (clobber (reg:QI 23))]
1122 "%~call __udivmodqi4"
1123 [(set_attr "type" "xcall")
1124 (set_attr "cc" "clobber")])
1126 (define_insn_and_split "divmodhi4"
1127 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1128 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
1129 (match_operand:HI 2 "pseudo_register_operand" "")))
1130 (set (match_operand:HI 3 "pseudo_register_operand" "")
1131 (mod:HI (match_dup 1) (match_dup 2)))
1132 (clobber (reg:QI 21))
1133 (clobber (reg:HI 22))
1134 (clobber (reg:HI 24))
1135 (clobber (reg:HI 26))])]
1137 "this should have been splitted;"
1139 [(set (reg:HI 24) (match_dup 1))
1140 (set (reg:HI 22) (match_dup 2))
1141 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1142 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1143 (clobber (reg:HI 26))
1144 (clobber (reg:QI 21))])
1145 (set (match_dup 0) (reg:HI 22))
1146 (set (match_dup 3) (reg:HI 24))]
1149 (define_insn "*divmodhi4_call"
1150 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1151 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1152 (clobber (reg:HI 26))
1153 (clobber (reg:QI 21))]
1155 "%~call __divmodhi4"
1156 [(set_attr "type" "xcall")
1157 (set_attr "cc" "clobber")])
1159 (define_insn_and_split "udivmodhi4"
1160 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1161 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
1162 (match_operand:HI 2 "pseudo_register_operand" "")))
1163 (set (match_operand:HI 3 "pseudo_register_operand" "")
1164 (umod:HI (match_dup 1) (match_dup 2)))
1165 (clobber (reg:QI 21))
1166 (clobber (reg:HI 22))
1167 (clobber (reg:HI 24))
1168 (clobber (reg:HI 26))])]
1170 "this udivmodhi4 pattern should have been splitted.;"
1172 [(set (reg:HI 24) (match_dup 1))
1173 (set (reg:HI 22) (match_dup 2))
1174 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1175 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1176 (clobber (reg:HI 26))
1177 (clobber (reg:QI 21))])
1178 (set (match_dup 0) (reg:HI 22))
1179 (set (match_dup 3) (reg:HI 24))]
1182 (define_insn "*udivmodhi4_call"
1183 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1184 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1185 (clobber (reg:HI 26))
1186 (clobber (reg:QI 21))]
1188 "%~call __udivmodhi4"
1189 [(set_attr "type" "xcall")
1190 (set_attr "cc" "clobber")])
1192 (define_insn_and_split "divmodsi4"
1193 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1194 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
1195 (match_operand:SI 2 "pseudo_register_operand" "")))
1196 (set (match_operand:SI 3 "pseudo_register_operand" "")
1197 (mod:SI (match_dup 1) (match_dup 2)))
1198 (clobber (reg:SI 18))
1199 (clobber (reg:SI 22))
1200 (clobber (reg:HI 26))
1201 (clobber (reg:HI 30))])]
1203 "this divmodsi4 pattern should have been splitted;"
1205 [(set (reg:SI 22) (match_dup 1))
1206 (set (reg:SI 18) (match_dup 2))
1207 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1208 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1209 (clobber (reg:HI 26))
1210 (clobber (reg:HI 30))])
1211 (set (match_dup 0) (reg:SI 18))
1212 (set (match_dup 3) (reg:SI 22))]
1215 (define_insn "*divmodsi4_call"
1216 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1217 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1218 (clobber (reg:HI 26))
1219 (clobber (reg:HI 30))]
1221 "%~call __divmodsi4"
1222 [(set_attr "type" "xcall")
1223 (set_attr "cc" "clobber")])
1225 (define_insn_and_split "udivmodsi4"
1226 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1227 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
1228 (match_operand:SI 2 "pseudo_register_operand" "")))
1229 (set (match_operand:SI 3 "pseudo_register_operand" "")
1230 (umod:SI (match_dup 1) (match_dup 2)))
1231 (clobber (reg:SI 18))
1232 (clobber (reg:SI 22))
1233 (clobber (reg:HI 26))
1234 (clobber (reg:HI 30))])]
1236 "this udivmodsi4 pattern should have been splitted;"
1238 [(set (reg:SI 22) (match_dup 1))
1239 (set (reg:SI 18) (match_dup 2))
1240 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1241 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1242 (clobber (reg:HI 26))
1243 (clobber (reg:HI 30))])
1244 (set (match_dup 0) (reg:SI 18))
1245 (set (match_dup 3) (reg:SI 22))]
1248 (define_insn "*udivmodsi4_call"
1249 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1250 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1251 (clobber (reg:HI 26))
1252 (clobber (reg:HI 30))]
1254 "%~call __udivmodsi4"
1255 [(set_attr "type" "xcall")
1256 (set_attr "cc" "clobber")])
1258 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
1261 (define_insn "andqi3"
1262 [(set (match_operand:QI 0 "register_operand" "=r,d")
1263 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
1264 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1269 [(set_attr "length" "1,1")
1270 (set_attr "cc" "set_zn,set_zn")])
1272 (define_insn "andhi3"
1273 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1274 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1275 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1276 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1279 if (which_alternative==0)
1280 return ("and %A0,%A2" CR_TAB
1282 else if (which_alternative==1)
1284 if (GET_CODE (operands[2]) == CONST_INT)
1286 int mask = INTVAL (operands[2]);
1287 if ((mask & 0xff) != 0xff)
1288 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1289 if ((mask & 0xff00) != 0xff00)
1290 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1293 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1294 AS2 (andi,%B0,hi8(%2)));
1296 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1300 [(set_attr "length" "2,2,3")
1301 (set_attr "cc" "set_n,clobber,set_n")])
1303 (define_insn "andsi3"
1304 [(set (match_operand:SI 0 "register_operand" "=r,d")
1305 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1306 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1309 if (which_alternative==0)
1310 return ("and %0,%2" CR_TAB
1311 "and %B0,%B2" CR_TAB
1312 "and %C0,%C2" CR_TAB
1314 else if (which_alternative==1)
1316 if (GET_CODE (operands[2]) == CONST_INT)
1318 HOST_WIDE_INT mask = INTVAL (operands[2]);
1319 if ((mask & 0xff) != 0xff)
1320 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1321 if ((mask & 0xff00) != 0xff00)
1322 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1323 if ((mask & 0xff0000L) != 0xff0000L)
1324 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1325 if ((mask & 0xff000000L) != 0xff000000L)
1326 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1329 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1330 AS2 (andi, %B0,hi8(%2)) CR_TAB
1331 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1332 AS2 (andi, %D0,hhi8(%2)));
1336 [(set_attr "length" "4,4")
1337 (set_attr "cc" "set_n,clobber")])
1339 (define_peephole2 ; andi
1340 [(set (match_operand:QI 0 "d_register_operand" "")
1341 (and:QI (match_dup 0)
1342 (match_operand:QI 1 "const_int_operand" "")))
1344 (and:QI (match_dup 0)
1345 (match_operand:QI 2 "const_int_operand" "")))]
1347 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1349 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
1352 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1355 (define_insn "iorqi3"
1356 [(set (match_operand:QI 0 "register_operand" "=r,d")
1357 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1358 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1363 [(set_attr "length" "1,1")
1364 (set_attr "cc" "set_zn,set_zn")])
1366 (define_insn "iorhi3"
1367 [(set (match_operand:HI 0 "register_operand" "=r,d")
1368 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1369 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1372 if (which_alternative==0)
1373 return ("or %A0,%A2" CR_TAB
1375 if (GET_CODE (operands[2]) == CONST_INT)
1377 int mask = INTVAL (operands[2]);
1379 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1381 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1384 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1385 AS2 (ori,%B0,hi8(%2)));
1387 [(set_attr "length" "2,2")
1388 (set_attr "cc" "set_n,clobber")])
1390 (define_insn "*iorhi3_clobber"
1391 [(set (match_operand:HI 0 "register_operand" "=r,r")
1392 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1393 (match_operand:HI 2 "immediate_operand" "M,i")))
1394 (clobber (match_scratch:QI 3 "=&d,&d"))]
1397 ldi %3,lo8(%2)\;or %A0,%3
1398 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1399 [(set_attr "length" "2,4")
1400 (set_attr "cc" "clobber,set_n")])
1402 (define_insn "iorsi3"
1403 [(set (match_operand:SI 0 "register_operand" "=r,d")
1404 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1405 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1408 if (which_alternative==0)
1409 return ("or %0,%2" CR_TAB
1413 if (GET_CODE (operands[2]) == CONST_INT)
1415 HOST_WIDE_INT mask = INTVAL (operands[2]);
1417 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1419 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1420 if (mask & 0xff0000L)
1421 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1422 if (mask & 0xff000000L)
1423 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1426 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1427 AS2 (ori, %B0,hi8(%2)) CR_TAB
1428 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1429 AS2 (ori, %D0,hhi8(%2)));
1431 [(set_attr "length" "4,4")
1432 (set_attr "cc" "set_n,clobber")])
1434 (define_insn "*iorsi3_clobber"
1435 [(set (match_operand:SI 0 "register_operand" "=r,r")
1436 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1437 (match_operand:SI 2 "immediate_operand" "M,i")))
1438 (clobber (match_scratch:QI 3 "=&d,&d"))]
1441 ldi %3,lo8(%2)\;or %A0,%3
1442 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1443 [(set_attr "length" "2,8")
1444 (set_attr "cc" "clobber,set_n")])
1446 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1449 (define_insn "xorqi3"
1450 [(set (match_operand:QI 0 "register_operand" "=r")
1451 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1452 (match_operand:QI 2 "register_operand" "r")))]
1455 [(set_attr "length" "1")
1456 (set_attr "cc" "set_zn")])
1458 (define_insn "xorhi3"
1459 [(set (match_operand:HI 0 "register_operand" "=r")
1460 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1461 (match_operand:HI 2 "register_operand" "r")))]
1465 [(set_attr "length" "2")
1466 (set_attr "cc" "set_n")])
1468 (define_insn "xorsi3"
1469 [(set (match_operand:SI 0 "register_operand" "=r")
1470 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1471 (match_operand:SI 2 "register_operand" "r")))]
1477 [(set_attr "length" "4")
1478 (set_attr "cc" "set_n")])
1480 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
1483 (define_expand "rotlqi3"
1484 [(set (match_operand:QI 0 "register_operand" "")
1485 (rotate:QI (match_operand:QI 1 "register_operand" "")
1486 (match_operand:QI 2 "const_int_operand" "")))]
1490 if (!CONST_INT_P (operands[2]) || (INTVAL (operands[2]) != 4))
1494 (define_insn "*rotlqi3_4"
1495 [(set (match_operand:QI 0 "register_operand" "=r")
1496 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1500 [(set_attr "length" "1")
1501 (set_attr "cc" "none")])
1503 ;; Split all rotates of HI,SI and DImode registers where rotation is by
1504 ;; a whole number of bytes. The split creates the appropriate moves and
1505 ;; considers all overlap situations. DImode is split before reload.
1507 ;; HImode does not need scratch. Use attribute for this constraint.
1508 ;; Use QI scratch for DI mode as this is often split into byte sized operands.
1510 (define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (HI "X,X,X")])
1511 (define_mode_attr rotsmode [(DI "QI") (SI "HI") (HI "QI")])
1513 (define_expand "rotl<mode>3"
1514 [(parallel [(set (match_operand:HIDI 0 "register_operand" "")
1515 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
1516 (match_operand:VOID 2 "const_int_operand" "")))
1517 (clobber (match_operand 3 ""))])]
1521 if (CONST_INT_P (operands[2]) && 0 == (INTVAL (operands[2]) % 8))
1523 if (AVR_HAVE_MOVW && 0 == INTVAL (operands[2]) % 16)
1524 operands[3] = gen_reg_rtx (<rotsmode>mode);
1526 operands[3] = gen_reg_rtx (QImode);
1533 ;; Overlapping non-HImode registers often (but not always) need a scratch.
1534 ;; The best we can do is use early clobber alternative "#&r" so that
1535 ;; completely non-overlapping operands dont get a scratch but # so register
1536 ;; allocation does not prefer non-overlapping.
1539 ; Split word aligned rotates using scratch that is mode dependent.
1540 (define_insn_and_split "*rotw<mode>"
1541 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1542 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1543 (match_operand 2 "immediate_operand" "n,n,n")))
1544 (clobber (match_operand:<rotsmode> 3 "register_operand" "=<rotx>" ))]
1545 "(CONST_INT_P (operands[2]) &&
1546 (0 == (INTVAL (operands[2]) % 16) && AVR_HAVE_MOVW))"
1548 "&& (reload_completed || <MODE>mode == DImode)"
1550 "avr_rotate_bytes (operands);
1555 ; Split byte aligned rotates using scratch that is always QI mode.
1556 (define_insn_and_split "*rotb<mode>"
1557 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1558 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1559 (match_operand 2 "immediate_operand" "n,n,n")))
1560 (clobber (match_operand:QI 3 "register_operand" "=<rotx>" ))]
1561 "(CONST_INT_P (operands[2]) &&
1562 (8 == (INTVAL (operands[2]) % 16)
1563 || (!AVR_HAVE_MOVW && 0 == (INTVAL (operands[2]) % 16))))"
1565 "&& (reload_completed || <MODE>mode == DImode)"
1567 "avr_rotate_bytes (operands);
1572 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1573 ;; arithmetic shift left
1575 (define_expand "ashlqi3"
1576 [(set (match_operand:QI 0 "register_operand" "")
1577 (ashift:QI (match_operand:QI 1 "register_operand" "")
1578 (match_operand:QI 2 "general_operand" "")))]
1582 (define_split ; ashlqi3_const4
1583 [(set (match_operand:QI 0 "d_register_operand" "")
1584 (ashift:QI (match_dup 0)
1587 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1588 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
1591 (define_split ; ashlqi3_const5
1592 [(set (match_operand:QI 0 "d_register_operand" "")
1593 (ashift:QI (match_dup 0)
1596 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1597 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1598 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
1601 (define_split ; ashlqi3_const6
1602 [(set (match_operand:QI 0 "d_register_operand" "")
1603 (ashift:QI (match_dup 0)
1606 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1607 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1608 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
1611 (define_insn "*ashlqi3"
1612 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1613 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1614 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1616 "* return ashlqi3_out (insn, operands, NULL);"
1617 [(set_attr "length" "5,0,1,2,4,6,9")
1618 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1620 (define_insn "ashlhi3"
1621 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1622 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1623 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1625 "* return ashlhi3_out (insn, operands, NULL);"
1626 [(set_attr "length" "6,0,2,2,4,10,10")
1627 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1629 (define_insn "ashlsi3"
1630 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1631 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1632 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1634 "* return ashlsi3_out (insn, operands, NULL);"
1635 [(set_attr "length" "8,0,4,4,8,10,12")
1636 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1638 ;; Optimize if a scratch register from LD_REGS happens to be available.
1640 (define_peephole2 ; ashlqi3_l_const4
1641 [(set (match_operand:QI 0 "l_register_operand" "")
1642 (ashift:QI (match_dup 0)
1644 (match_scratch:QI 1 "d")]
1646 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1647 (set (match_dup 1) (const_int -16))
1648 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1651 (define_peephole2 ; ashlqi3_l_const5
1652 [(set (match_operand:QI 0 "l_register_operand" "")
1653 (ashift:QI (match_dup 0)
1655 (match_scratch:QI 1 "d")]
1657 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1658 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1659 (set (match_dup 1) (const_int -32))
1660 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1663 (define_peephole2 ; ashlqi3_l_const6
1664 [(set (match_operand:QI 0 "l_register_operand" "")
1665 (ashift:QI (match_dup 0)
1667 (match_scratch:QI 1 "d")]
1669 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1670 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1671 (set (match_dup 1) (const_int -64))
1672 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1676 [(match_scratch:QI 3 "d")
1677 (set (match_operand:HI 0 "register_operand" "")
1678 (ashift:HI (match_operand:HI 1 "register_operand" "")
1679 (match_operand:QI 2 "const_int_operand" "")))]
1681 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1682 (clobber (match_dup 3))])]
1685 (define_insn "*ashlhi3_const"
1686 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1687 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1688 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1689 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1691 "* return ashlhi3_out (insn, operands, NULL);"
1692 [(set_attr "length" "0,2,2,4,10")
1693 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
1696 [(match_scratch:QI 3 "d")
1697 (set (match_operand:SI 0 "register_operand" "")
1698 (ashift:SI (match_operand:SI 1 "register_operand" "")
1699 (match_operand:QI 2 "const_int_operand" "")))]
1701 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1702 (clobber (match_dup 3))])]
1705 (define_insn "*ashlsi3_const"
1706 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1707 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1708 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1709 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1711 "* return ashlsi3_out (insn, operands, NULL);"
1712 [(set_attr "length" "0,4,4,10")
1713 (set_attr "cc" "none,set_n,clobber,clobber")])
1715 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1716 ;; arithmetic shift right
1718 (define_insn "ashrqi3"
1719 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1720 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1721 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
1723 "* return ashrqi3_out (insn, operands, NULL);"
1724 [(set_attr "length" "5,0,1,2,5,9")
1725 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
1727 (define_insn "ashrhi3"
1728 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1729 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1730 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1732 "* return ashrhi3_out (insn, operands, NULL);"
1733 [(set_attr "length" "6,0,2,4,4,10,10")
1734 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1736 (define_insn "ashrsi3"
1737 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1738 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1739 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1741 "* return ashrsi3_out (insn, operands, NULL);"
1742 [(set_attr "length" "8,0,4,6,8,10,12")
1743 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1745 ;; Optimize if a scratch register from LD_REGS happens to be available.
1748 [(match_scratch:QI 3 "d")
1749 (set (match_operand:HI 0 "register_operand" "")
1750 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1751 (match_operand:QI 2 "const_int_operand" "")))]
1753 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1754 (clobber (match_dup 3))])]
1757 (define_insn "*ashrhi3_const"
1758 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1759 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1760 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1761 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1763 "* return ashrhi3_out (insn, operands, NULL);"
1764 [(set_attr "length" "0,2,4,4,10")
1765 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
1768 [(match_scratch:QI 3 "d")
1769 (set (match_operand:SI 0 "register_operand" "")
1770 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1771 (match_operand:QI 2 "const_int_operand" "")))]
1773 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1774 (clobber (match_dup 3))])]
1777 (define_insn "*ashrsi3_const"
1778 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1779 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1780 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1781 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1783 "* return ashrsi3_out (insn, operands, NULL);"
1784 [(set_attr "length" "0,4,4,10")
1785 (set_attr "cc" "none,clobber,set_n,clobber")])
1787 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1788 ;; logical shift right
1790 (define_expand "lshrqi3"
1791 [(set (match_operand:QI 0 "register_operand" "")
1792 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1793 (match_operand:QI 2 "general_operand" "")))]
1797 (define_split ; lshrqi3_const4
1798 [(set (match_operand:QI 0 "d_register_operand" "")
1799 (lshiftrt:QI (match_dup 0)
1802 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1803 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
1806 (define_split ; lshrqi3_const5
1807 [(set (match_operand:QI 0 "d_register_operand" "")
1808 (lshiftrt:QI (match_dup 0)
1811 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1812 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1813 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
1816 (define_split ; lshrqi3_const6
1817 [(set (match_operand:QI 0 "d_register_operand" "")
1818 (lshiftrt:QI (match_dup 0)
1821 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1822 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1823 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
1826 (define_insn "*lshrqi3"
1827 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1828 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1829 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1831 "* return lshrqi3_out (insn, operands, NULL);"
1832 [(set_attr "length" "5,0,1,2,4,6,9")
1833 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1835 (define_insn "lshrhi3"
1836 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1837 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1838 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1840 "* return lshrhi3_out (insn, operands, NULL);"
1841 [(set_attr "length" "6,0,2,2,4,10,10")
1842 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1844 (define_insn "lshrsi3"
1845 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1846 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1847 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1849 "* return lshrsi3_out (insn, operands, NULL);"
1850 [(set_attr "length" "8,0,4,4,8,10,12")
1851 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1853 ;; Optimize if a scratch register from LD_REGS happens to be available.
1855 (define_peephole2 ; lshrqi3_l_const4
1856 [(set (match_operand:QI 0 "l_register_operand" "")
1857 (lshiftrt:QI (match_dup 0)
1859 (match_scratch:QI 1 "d")]
1861 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1862 (set (match_dup 1) (const_int 15))
1863 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1866 (define_peephole2 ; lshrqi3_l_const5
1867 [(set (match_operand:QI 0 "l_register_operand" "")
1868 (lshiftrt:QI (match_dup 0)
1870 (match_scratch:QI 1 "d")]
1872 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1873 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1874 (set (match_dup 1) (const_int 7))
1875 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1878 (define_peephole2 ; lshrqi3_l_const6
1879 [(set (match_operand:QI 0 "l_register_operand" "")
1880 (lshiftrt:QI (match_dup 0)
1882 (match_scratch:QI 1 "d")]
1884 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1885 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1886 (set (match_dup 1) (const_int 3))
1887 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1891 [(match_scratch:QI 3 "d")
1892 (set (match_operand:HI 0 "register_operand" "")
1893 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1894 (match_operand:QI 2 "const_int_operand" "")))]
1896 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1897 (clobber (match_dup 3))])]
1900 (define_insn "*lshrhi3_const"
1901 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1902 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1903 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1904 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1906 "* return lshrhi3_out (insn, operands, NULL);"
1907 [(set_attr "length" "0,2,2,4,10")
1908 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
1911 [(match_scratch:QI 3 "d")
1912 (set (match_operand:SI 0 "register_operand" "")
1913 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1914 (match_operand:QI 2 "const_int_operand" "")))]
1916 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1917 (clobber (match_dup 3))])]
1920 (define_insn "*lshrsi3_const"
1921 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1922 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1923 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1924 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1926 "* return lshrsi3_out (insn, operands, NULL);"
1927 [(set_attr "length" "0,4,4,10")
1928 (set_attr "cc" "none,clobber,clobber,clobber")])
1930 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
1933 (define_insn "absqi2"
1934 [(set (match_operand:QI 0 "register_operand" "=r")
1935 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
1939 [(set_attr "length" "2")
1940 (set_attr "cc" "clobber")])
1943 (define_insn "abssf2"
1944 [(set (match_operand:SF 0 "register_operand" "=d,r")
1945 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
1950 [(set_attr "length" "1,2")
1951 (set_attr "cc" "set_n,clobber")])
1953 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
1956 (define_insn "negqi2"
1957 [(set (match_operand:QI 0 "register_operand" "=r")
1958 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1961 [(set_attr "length" "1")
1962 (set_attr "cc" "set_zn")])
1964 (define_insn "neghi2"
1965 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
1966 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
1969 com %B0\;neg %A0\;sbci %B0,lo8(-1)
1970 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
1971 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
1972 [(set_attr "length" "3,4,4")
1973 (set_attr "cc" "set_czn,set_n,set_czn")])
1975 (define_insn "negsi2"
1976 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
1977 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
1980 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
1981 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
1982 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
1983 [(set_attr_alternative "length"
1986 (if_then_else (eq_attr "mcu_have_movw" "yes")
1989 (set_attr "cc" "set_czn,set_n,set_czn")])
1991 (define_insn "negsf2"
1992 [(set (match_operand:SF 0 "register_operand" "=d,r")
1993 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
1997 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
1998 [(set_attr "length" "1,4")
1999 (set_attr "cc" "set_n,set_n")])
2001 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2004 (define_insn "one_cmplqi2"
2005 [(set (match_operand:QI 0 "register_operand" "=r")
2006 (not:QI (match_operand:QI 1 "register_operand" "0")))]
2009 [(set_attr "length" "1")
2010 (set_attr "cc" "set_czn")])
2012 (define_insn "one_cmplhi2"
2013 [(set (match_operand:HI 0 "register_operand" "=r")
2014 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2018 [(set_attr "length" "2")
2019 (set_attr "cc" "set_n")])
2021 (define_insn "one_cmplsi2"
2022 [(set (match_operand:SI 0 "register_operand" "=r")
2023 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2029 [(set_attr "length" "4")
2030 (set_attr "cc" "set_n")])
2032 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2035 (define_insn "extendqihi2"
2036 [(set (match_operand:HI 0 "register_operand" "=r,r")
2037 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
2040 clr %B0\;sbrc %0,7\;com %B0
2041 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
2042 [(set_attr "length" "3,4")
2043 (set_attr "cc" "set_n,set_n")])
2045 (define_insn "extendqisi2"
2046 [(set (match_operand:SI 0 "register_operand" "=r,r")
2047 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
2050 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
2051 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
2052 [(set_attr "length" "5,6")
2053 (set_attr "cc" "set_n,set_n")])
2055 (define_insn "extendhisi2"
2056 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2057 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
2060 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
2061 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
2062 [(set_attr_alternative "length"
2064 (if_then_else (eq_attr "mcu_have_movw" "yes")
2067 (set_attr "cc" "set_n,set_n")])
2069 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2072 (define_insn_and_split "zero_extendqihi2"
2073 [(set (match_operand:HI 0 "register_operand" "=r")
2074 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2078 [(set (match_dup 2) (match_dup 1))
2079 (set (match_dup 3) (const_int 0))]
2080 "unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
2081 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
2083 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
2084 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
2087 (define_insn_and_split "zero_extendqisi2"
2088 [(set (match_operand:SI 0 "register_operand" "=r")
2089 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2093 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
2094 (set (match_dup 3) (const_int 0))]
2095 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2096 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2098 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2099 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2102 (define_insn_and_split "zero_extendhisi2"
2103 [(set (match_operand:SI 0 "register_operand" "=r")
2104 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2108 [(set (match_dup 2) (match_dup 1))
2109 (set (match_dup 3) (const_int 0))]
2110 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2111 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2113 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2114 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2117 (define_insn_and_split "zero_extendqidi2"
2118 [(set (match_operand:DI 0 "register_operand" "=r")
2119 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
2123 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2124 (set (match_dup 3) (const_int 0))]
2125 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2126 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2128 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2129 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2132 (define_insn_and_split "zero_extendhidi2"
2133 [(set (match_operand:DI 0 "register_operand" "=r")
2134 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
2138 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2139 (set (match_dup 3) (const_int 0))]
2140 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2141 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2143 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2144 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2147 (define_insn_and_split "zero_extendsidi2"
2148 [(set (match_operand:DI 0 "register_operand" "=r")
2149 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
2153 [(set (match_dup 2) (match_dup 1))
2154 (set (match_dup 3) (const_int 0))]
2155 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2156 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2158 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2159 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2162 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2165 ; Optimize negated tests into reverse compare if overflow is undefined.
2166 (define_insn "*negated_tstqi"
2168 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
2170 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2171 "cp __zero_reg__,%0"
2172 [(set_attr "cc" "compare")
2173 (set_attr "length" "1")])
2175 (define_insn "*reversed_tstqi"
2177 (compare (const_int 0)
2178 (match_operand:QI 0 "register_operand" "r")))]
2180 "cp __zero_reg__,%0"
2181 [(set_attr "cc" "compare")
2182 (set_attr "length" "2")])
2184 (define_insn "*negated_tsthi"
2186 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
2188 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2189 "cp __zero_reg__,%A0
2190 cpc __zero_reg__,%B0"
2191 [(set_attr "cc" "compare")
2192 (set_attr "length" "2")])
2194 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
2195 ;; though it is unused, because this pattern is synthesized by avr_reorg.
2196 (define_insn "*reversed_tsthi"
2198 (compare (const_int 0)
2199 (match_operand:HI 0 "register_operand" "r")))
2200 (clobber (match_scratch:QI 1 "=X"))]
2202 "cp __zero_reg__,%A0
2203 cpc __zero_reg__,%B0"
2204 [(set_attr "cc" "compare")
2205 (set_attr "length" "2")])
2207 (define_insn "*negated_tstsi"
2209 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
2211 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2212 "cp __zero_reg__,%A0
2213 cpc __zero_reg__,%B0
2214 cpc __zero_reg__,%C0
2215 cpc __zero_reg__,%D0"
2216 [(set_attr "cc" "compare")
2217 (set_attr "length" "4")])
2219 (define_insn "*reversed_tstsi"
2221 (compare (const_int 0)
2222 (match_operand:SI 0 "register_operand" "r")))
2223 (clobber (match_scratch:QI 1 "=X"))]
2225 "cp __zero_reg__,%A0
2226 cpc __zero_reg__,%B0
2227 cpc __zero_reg__,%C0
2228 cpc __zero_reg__,%D0"
2229 [(set_attr "cc" "compare")
2230 (set_attr "length" "4")])
2233 (define_insn "*cmpqi"
2235 (compare (match_operand:QI 0 "register_operand" "r,r,d")
2236 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
2242 [(set_attr "cc" "compare,compare,compare")
2243 (set_attr "length" "1,1,1")])
2245 (define_insn "*cmpqi_sign_extend"
2247 (compare (sign_extend:HI
2248 (match_operand:QI 0 "register_operand" "d"))
2249 (match_operand:HI 1 "const_int_operand" "n")))]
2250 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2252 [(set_attr "cc" "compare")
2253 (set_attr "length" "1")])
2255 (define_insn "*cmphi"
2257 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r")
2258 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i")))
2259 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))]
2262 switch (which_alternative)
2265 return out_tsthi (insn, operands[0], NULL);
2268 return (AS2 (cp,%A0,%A1) CR_TAB
2271 if (reg_unused_after (insn, operands[0])
2272 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2273 && test_hard_reg_class (ADDW_REGS, operands[0]))
2274 return AS2 (sbiw,%0,%1);
2276 return (AS2 (cpi,%0,%1) CR_TAB
2277 AS2 (cpc,%B0,__zero_reg__));
2279 if (reg_unused_after (insn, operands[0]))
2280 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2281 AS2 (sbci,%B0,hi8(%1)));
2283 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2284 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2287 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2288 AS2 (cp, %A0,%2) CR_TAB
2289 AS2 (cpc, %B0,__zero_reg__));
2292 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2293 AS2 (cp, %A0,%2) CR_TAB
2294 AS2 (ldi, %2,hi8(%1)) CR_TAB
2299 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare")
2300 (set_attr "length" "1,2,2,2,3,3,4")])
2303 (define_insn "*cmpsi"
2305 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r")
2306 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i")))
2307 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))]
2310 switch (which_alternative)
2313 return out_tstsi (insn, operands[0], NULL);
2316 return (AS2 (cp,%A0,%A1) CR_TAB
2317 AS2 (cpc,%B0,%B1) CR_TAB
2318 AS2 (cpc,%C0,%C1) CR_TAB
2321 if (reg_unused_after (insn, operands[0])
2322 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2323 && test_hard_reg_class (ADDW_REGS, operands[0]))
2324 return (AS2 (sbiw,%0,%1) CR_TAB
2325 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2326 AS2 (cpc,%D0,__zero_reg__));
2328 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2329 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2330 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2331 AS2 (cpc,%D0,__zero_reg__));
2333 if (reg_unused_after (insn, operands[0]))
2334 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2335 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2336 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2337 AS2 (sbci,%D0,hhi8(%1)));
2339 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
2340 AS2 (ldi, %2,hi8(%1)) CR_TAB
2341 AS2 (cpc, %B0,%2) CR_TAB
2342 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2343 AS2 (cpc, %C0,%2) CR_TAB
2344 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2347 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2348 AS2 (cp,%A0,%2) CR_TAB
2349 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2350 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2351 AS2 (cpc,%D0,__zero_reg__));
2353 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2354 AS2 (cp, %A0,%2) CR_TAB
2355 AS2 (ldi, %2,hi8(%1)) CR_TAB
2356 AS2 (cpc, %B0,%2) CR_TAB
2357 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2358 AS2 (cpc, %C0,%2) CR_TAB
2359 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2364 [(set_attr "cc" "compare,compare,compare,compare,compare,compare")
2365 (set_attr "length" "4,4,4,7,5,8")])
2368 ;; ----------------------------------------------------------------------
2369 ;; JUMP INSTRUCTIONS
2370 ;; ----------------------------------------------------------------------
2371 ;; Conditional jump instructions
2373 (define_expand "cbranchsi4"
2374 [(parallel [(set (cc0)
2375 (compare (match_operand:SI 1 "register_operand" "")
2376 (match_operand:SI 2 "nonmemory_operand" "")))
2377 (clobber (match_scratch:QI 4 ""))])
2380 (match_operator 0 "ordered_comparison_operator" [(cc0)
2382 (label_ref (match_operand 3 "" ""))
2386 (define_expand "cbranchhi4"
2387 [(parallel [(set (cc0)
2388 (compare (match_operand:HI 1 "register_operand" "")
2389 (match_operand:HI 2 "nonmemory_operand" "")))
2390 (clobber (match_scratch:QI 4 ""))])
2393 (match_operator 0 "ordered_comparison_operator" [(cc0)
2395 (label_ref (match_operand 3 "" ""))
2399 (define_expand "cbranchqi4"
2401 (compare (match_operand:QI 1 "register_operand" "")
2402 (match_operand:QI 2 "nonmemory_operand" "")))
2405 (match_operator 0 "ordered_comparison_operator" [(cc0)
2407 (label_ref (match_operand 3 "" ""))
2412 ;; Test a single bit in a QI/HI/SImode register.
2413 ;; Combine will create zero extract patterns for single bit tests.
2414 ;; permit any mode in source pattern by using VOIDmode.
2416 (define_insn "*sbrx_branch<mode>"
2419 (match_operator 0 "eqne_operator"
2421 (match_operand:VOID 1 "register_operand" "r")
2423 (match_operand 2 "const_int_operand" "n"))
2425 (label_ref (match_operand 3 "" ""))
2428 "* return avr_out_sbxx_branch (insn, operands);"
2429 [(set (attr "length")
2430 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2431 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2433 (if_then_else (eq_attr "mcu_mega" "no")
2436 (set_attr "cc" "clobber")])
2438 ;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns.
2439 ;; or for old peepholes.
2440 ;; Fixme - bitwise Mask will not work for DImode
2442 (define_insn "*sbrx_and_branch<mode>"
2445 (match_operator 0 "eqne_operator"
2447 (match_operand:QISI 1 "register_operand" "r")
2448 (match_operand:QISI 2 "single_one_operand" "n"))
2450 (label_ref (match_operand 3 "" ""))
2454 HOST_WIDE_INT bitnumber;
2455 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
2456 operands[2] = GEN_INT (bitnumber);
2457 return avr_out_sbxx_branch (insn, operands);
2459 [(set (attr "length")
2460 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2461 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2463 (if_then_else (eq_attr "mcu_mega" "no")
2466 (set_attr "cc" "clobber")])
2468 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2470 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2472 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2473 (label_ref (match_operand 1 "" ""))
2476 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2480 (label_ref (match_dup 1))
2485 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2487 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2488 (label_ref (match_operand 1 "" ""))
2491 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2495 (label_ref (match_dup 1))
2500 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2502 (clobber (match_operand:HI 2 ""))])
2503 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2504 (label_ref (match_operand 1 "" ""))
2507 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2509 (label_ref (match_dup 1))
2514 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2516 (clobber (match_operand:HI 2 ""))])
2517 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2518 (label_ref (match_operand 1 "" ""))
2521 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2523 (label_ref (match_dup 1))
2528 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2530 (clobber (match_operand:SI 2 ""))])
2531 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2532 (label_ref (match_operand 1 "" ""))
2535 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2537 (label_ref (match_dup 1))
2539 "operands[2] = GEN_INT (-2147483647 - 1);")
2542 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2544 (clobber (match_operand:SI 2 ""))])
2545 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2546 (label_ref (match_operand 1 "" ""))
2549 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2551 (label_ref (match_dup 1))
2553 "operands[2] = GEN_INT (-2147483647 - 1);")
2555 ;; ************************************************************************
2556 ;; Implementation of conditional jumps here.
2557 ;; Compare with 0 (test) jumps
2558 ;; ************************************************************************
2560 (define_insn "branch"
2562 (if_then_else (match_operator 1 "simple_comparison_operator"
2565 (label_ref (match_operand 0 "" ""))
2569 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2570 [(set_attr "type" "branch")
2571 (set_attr "cc" "clobber")])
2573 ;; ****************************************************************
2574 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
2575 ;; Convert them all to proper jumps.
2576 ;; ****************************************************************/
2578 (define_insn "difficult_branch"
2580 (if_then_else (match_operator 1 "difficult_comparison_operator"
2583 (label_ref (match_operand 0 "" ""))
2587 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2588 [(set_attr "type" "branch1")
2589 (set_attr "cc" "clobber")])
2593 (define_insn "rvbranch"
2595 (if_then_else (match_operator 1 "simple_comparison_operator"
2599 (label_ref (match_operand 0 "" ""))))]
2602 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2603 [(set_attr "type" "branch1")
2604 (set_attr "cc" "clobber")])
2606 (define_insn "difficult_rvbranch"
2608 (if_then_else (match_operator 1 "difficult_comparison_operator"
2612 (label_ref (match_operand 0 "" ""))))]
2615 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2616 [(set_attr "type" "branch")
2617 (set_attr "cc" "clobber")])
2619 ;; **************************************************************************
2620 ;; Unconditional and other jump instructions.
2624 (label_ref (match_operand 0 "" "")))]
2627 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2628 return AS1 (jmp,%x0);
2629 return AS1 (rjmp,%x0);
2631 [(set (attr "length")
2632 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2633 (if_then_else (eq_attr "mcu_mega" "no")
2636 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
2637 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2640 (set_attr "cc" "none")])
2644 (define_expand "call"
2645 [(call (match_operand:HI 0 "call_insn_operand" "")
2646 (match_operand:HI 1 "general_operand" ""))]
2647 ;; Operand 1 not used on the AVR.
2653 (define_expand "call_value"
2654 [(set (match_operand 0 "register_operand" "")
2655 (call (match_operand:HI 1 "call_insn_operand" "")
2656 (match_operand:HI 2 "general_operand" "")))]
2657 ;; Operand 2 not used on the AVR.
2661 (define_insn "call_insn"
2662 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
2663 (match_operand:HI 1 "general_operand" "X,X,X,X"))]
2664 ;; We don't need in saving Z register because r30,r31 is a call used registers
2665 ;; Operand 1 not used on the AVR.
2666 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
2668 if (which_alternative==0)
2670 else if (which_alternative==1)
2673 return (AS2 (movw, r30, %0) CR_TAB
2676 return (AS2 (mov, r30, %A0) CR_TAB
2677 AS2 (mov, r31, %B0) CR_TAB
2680 else if (which_alternative==2)
2681 return AS1(%~call,%x0);
2682 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
2683 AS2 (ldi,r31,hi8(%0)) CR_TAB
2686 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2687 (set_attr_alternative "length"
2689 (if_then_else (eq_attr "mcu_have_movw" "yes")
2692 (if_then_else (eq_attr "mcu_mega" "yes")
2697 (define_insn "call_value_insn"
2698 [(set (match_operand 0 "register_operand" "=r,r,r,r")
2699 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
2700 ;; We don't need in saving Z register because r30,r31 is a call used registers
2701 (match_operand:HI 2 "general_operand" "X,X,X,X")))]
2702 ;; Operand 2 not used on the AVR.
2703 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
2705 if (which_alternative==0)
2707 else if (which_alternative==1)
2710 return (AS2 (movw, r30, %1) CR_TAB
2713 return (AS2 (mov, r30, %A1) CR_TAB
2714 AS2 (mov, r31, %B1) CR_TAB
2717 else if (which_alternative==2)
2718 return AS1(%~call,%x1);
2719 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
2720 AS2 (ldi, r31, hi8(%1)) CR_TAB
2723 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2724 (set_attr_alternative "length"
2726 (if_then_else (eq_attr "mcu_have_movw" "yes")
2729 (if_then_else (eq_attr "mcu_mega" "yes")
2738 [(set_attr "cc" "none")
2739 (set_attr "length" "1")])
2743 (define_expand "indirect_jump"
2744 [(set (pc) (match_operand:HI 0 "nonmemory_operand" ""))]
2746 " if ((!AVR_HAVE_JMP_CALL) && !register_operand(operand0, HImode))
2748 operands[0] = copy_to_mode_reg(HImode, operand0);
2753 (define_insn "*jcindirect_jump"
2754 [(set (pc) (match_operand:HI 0 "immediate_operand" "i"))]
2758 [(set_attr "length" "2")
2759 (set_attr "cc" "none")])
2762 (define_insn "*njcindirect_jump"
2763 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2764 "!AVR_HAVE_EIJMP_EICALL"
2767 push %A0\;push %B0\;ret"
2768 [(set_attr "length" "1,3")
2769 (set_attr "cc" "none,none")])
2771 (define_insn "*indirect_jump_avr6"
2772 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
2773 "AVR_HAVE_EIJMP_EICALL"
2775 [(set_attr "length" "1")
2776 (set_attr "cc" "none")])
2780 ;; Table made from "rjmp" instructions for <=8K devices.
2781 (define_insn "*tablejump_rjmp"
2782 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
2784 (use (label_ref (match_operand 1 "" "")))
2785 (clobber (match_dup 0))]
2786 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
2789 push %A0\;push %B0\;ret"
2790 [(set_attr "length" "1,3")
2791 (set_attr "cc" "none,none")])
2793 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2794 (define_insn "*tablejump_lib"
2795 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2797 (use (label_ref (match_operand 1 "" "")))
2798 (clobber (match_dup 0))]
2799 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2800 "%~jmp __tablejump2__"
2801 [(set_attr "length" "2")
2802 (set_attr "cc" "clobber")])
2804 (define_insn "*tablejump_enh"
2805 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2807 (use (label_ref (match_operand 1 "" "")))
2808 (clobber (match_dup 0))]
2809 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
2816 [(set_attr "length" "6")
2817 (set_attr "cc" "clobber")])
2819 (define_insn "*tablejump"
2820 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2822 (use (label_ref (match_operand 1 "" "")))
2823 (clobber (match_dup 0))]
2824 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
2833 [(set_attr "length" "8")
2834 (set_attr "cc" "clobber")])
2836 (define_expand "casesi"
2838 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2839 (match_operand:HI 1 "register_operand" "")))
2840 (parallel [(set (cc0)
2841 (compare (match_dup 6)
2842 (match_operand:HI 2 "register_operand" "")))
2843 (clobber (match_scratch:QI 9 ""))])
2846 (if_then_else (gtu (cc0)
2848 (label_ref (match_operand 4 "" ""))
2852 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2854 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
2855 (use (label_ref (match_dup 3)))
2856 (clobber (match_dup 6))])]
2860 operands[6] = gen_reg_rtx (HImode);
2864 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2865 ;; This instruction sets Z flag
2868 [(set (cc0) (const_int 0))]
2871 [(set_attr "length" "1")
2872 (set_attr "cc" "compare")])
2874 ;; Clear/set/test a single bit in I/O address space.
2877 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2878 (and:QI (mem:QI (match_dup 0))
2879 (match_operand:QI 1 "single_zero_operand" "n")))]
2882 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2883 return AS2 (cbi,%m0-0x20,%2);
2885 [(set_attr "length" "1")
2886 (set_attr "cc" "none")])
2889 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2890 (ior:QI (mem:QI (match_dup 0))
2891 (match_operand:QI 1 "single_one_operand" "n")))]
2894 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2895 return AS2 (sbi,%m0-0x20,%2);
2897 [(set_attr "length" "1")
2898 (set_attr "cc" "none")])
2900 ;; Lower half of the I/O space - use sbic/sbis directly.
2901 (define_insn "*sbix_branch"
2904 (match_operator 0 "eqne_operator"
2906 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
2908 (match_operand 2 "const_int_operand" "n"))
2910 (label_ref (match_operand 3 "" ""))
2913 "* return avr_out_sbxx_branch (insn, operands);"
2914 [(set (attr "length")
2915 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2916 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2918 (if_then_else (eq_attr "mcu_mega" "no")
2921 (set_attr "cc" "clobber")])
2923 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
2924 (define_insn "*sbix_branch_bit7"
2927 (match_operator 0 "gelt_operator"
2928 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
2930 (label_ref (match_operand 2 "" ""))
2934 operands[3] = operands[2];
2935 operands[2] = GEN_INT (7);
2936 return avr_out_sbxx_branch (insn, operands);
2938 [(set (attr "length")
2939 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2940 (le (minus (pc) (match_dup 2)) (const_int 2046)))
2942 (if_then_else (eq_attr "mcu_mega" "no")
2945 (set_attr "cc" "clobber")])
2947 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
2948 (define_insn "*sbix_branch_tmp"
2951 (match_operator 0 "eqne_operator"
2953 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
2955 (match_operand 2 "const_int_operand" "n"))
2957 (label_ref (match_operand 3 "" ""))
2960 "* return avr_out_sbxx_branch (insn, operands);"
2961 [(set (attr "length")
2962 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2963 (le (minus (pc) (match_dup 3)) (const_int 2045)))
2965 (if_then_else (eq_attr "mcu_mega" "no")
2968 (set_attr "cc" "clobber")])
2970 (define_insn "*sbix_branch_tmp_bit7"
2973 (match_operator 0 "gelt_operator"
2974 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
2976 (label_ref (match_operand 2 "" ""))
2980 operands[3] = operands[2];
2981 operands[2] = GEN_INT (7);
2982 return avr_out_sbxx_branch (insn, operands);
2984 [(set (attr "length")
2985 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2986 (le (minus (pc) (match_dup 2)) (const_int 2045)))
2988 (if_then_else (eq_attr "mcu_mega" "no")
2991 (set_attr "cc" "clobber")])
2993 ;; ************************* Peepholes ********************************
2996 [(set (match_operand:SI 0 "d_register_operand" "")
2997 (plus:SI (match_dup 0)
3001 (compare (match_dup 0)
3003 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3005 (if_then_else (ne (cc0) (const_int 0))
3006 (label_ref (match_operand 2 "" ""))
3012 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3013 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
3014 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3015 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3017 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3018 AS2 (sbc,%B0,__zero_reg__) CR_TAB
3019 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3020 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3021 switch (avr_jump_mode (operands[2],insn))
3024 return AS1 (brcc,%2);
3026 return (AS1 (brcs,.+2) CR_TAB
3029 return (AS1 (brcs,.+4) CR_TAB
3034 [(set (match_operand:HI 0 "d_register_operand" "")
3035 (plus:HI (match_dup 0)
3039 (compare (match_dup 0)
3041 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3043 (if_then_else (ne (cc0) (const_int 0))
3044 (label_ref (match_operand 2 "" ""))
3050 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3051 output_asm_insn (AS2 (sbiw,%0,1), operands);
3053 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3054 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
3055 switch (avr_jump_mode (operands[2],insn))
3058 return AS1 (brcc,%2);
3060 return (AS1 (brcs,.+2) CR_TAB
3063 return (AS1 (brcs,.+4) CR_TAB
3068 [(set (match_operand:QI 0 "d_register_operand" "")
3069 (plus:QI (match_dup 0)
3072 (compare (match_dup 0)
3075 (if_then_else (ne (cc0) (const_int 0))
3076 (label_ref (match_operand 1 "" ""))
3082 cc_status.value1 = operands[0];
3083 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
3084 output_asm_insn (AS2 (subi,%A0,1), operands);
3085 switch (avr_jump_mode (operands[1],insn))
3088 return AS1 (brcc,%1);
3090 return (AS1 (brcs,.+2) CR_TAB
3093 return (AS1 (brcs,.+4) CR_TAB
3099 (compare (match_operand:QI 0 "register_operand" "")
3102 (if_then_else (eq (cc0) (const_int 0))
3103 (label_ref (match_operand 1 "" ""))
3105 "jump_over_one_insn_p (insn, operands[1])"
3106 "cpse %0,__zero_reg__")
3110 (compare (match_operand:QI 0 "register_operand" "")
3111 (match_operand:QI 1 "register_operand" "")))
3113 (if_then_else (eq (cc0) (const_int 0))
3114 (label_ref (match_operand 2 "" ""))
3116 "jump_over_one_insn_p (insn, operands[2])"
3119 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
3120 ;;prologue/epilogue support instructions
3122 (define_insn "popqi"
3123 [(set (match_operand:QI 0 "register_operand" "=r")
3124 (mem:QI (post_inc (reg:HI REG_SP))))]
3127 [(set_attr "cc" "none")
3128 (set_attr "length" "1")])
3130 (define_insn "pophi"
3131 [(set (match_operand:HI 0 "register_operand" "=r")
3132 (mem:HI (post_inc (reg:HI REG_SP))))]
3135 [(set_attr "cc" "none")
3136 (set_attr "length" "2")])
3138 ;; Enable Interrupts
3139 (define_insn "enable_interrupt"
3140 [(unspec [(const_int 0)] UNSPEC_SEI)]
3143 [(set_attr "length" "1")
3144 (set_attr "cc" "none")
3147 ;; Disable Interrupts
3148 (define_insn "disable_interrupt"
3149 [(unspec [(const_int 0)] UNSPEC_CLI)]
3152 [(set_attr "length" "1")
3153 (set_attr "cc" "none")
3156 ;; Library prologue saves
3157 (define_insn "call_prologue_saves"
3158 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
3159 (match_operand:HI 0 "immediate_operand" "")
3160 (set (reg:HI REG_SP) (minus:HI
3162 (match_operand:HI 1 "immediate_operand" "")))
3163 (use (reg:HI REG_X))
3164 (clobber (reg:HI REG_Z))]
3166 "ldi r30,lo8(gs(1f))
3168 %~jmp __prologue_saves__+((18 - %0) * 2)
3170 [(set_attr_alternative "length"
3171 [(if_then_else (eq_attr "mcu_mega" "yes")
3174 (set_attr "cc" "clobber")
3177 ; epilogue restores using library
3178 (define_insn "epilogue_restores"
3179 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
3180 (set (reg:HI REG_Y ) (plus:HI
3182 (match_operand:HI 0 "immediate_operand" "")))
3183 (set (reg:HI REG_SP) (reg:HI REG_Y))
3184 (clobber (reg:QI REG_Z))]
3187 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
3188 [(set_attr_alternative "length"
3189 [(if_then_else (eq_attr "mcu_mega" "yes")
3192 (set_attr "cc" "clobber")
3196 (define_insn "return"
3198 "reload_completed && avr_simple_epilogue ()"
3200 [(set_attr "cc" "none")
3201 (set_attr "length" "1")])
3203 (define_insn "return_from_epilogue"
3207 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
3208 && !cfun->machine->is_naked)"
3210 [(set_attr "cc" "none")
3211 (set_attr "length" "1")])
3213 (define_insn "return_from_interrupt_epilogue"
3217 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
3218 && !cfun->machine->is_naked)"
3220 [(set_attr "cc" "none")
3221 (set_attr "length" "1")])
3223 (define_insn "return_from_naked_epilogue"
3227 && cfun->machine->is_naked)"
3229 [(set_attr "cc" "none")
3230 (set_attr "length" "0")])
3232 (define_expand "prologue"
3241 (define_expand "epilogue"