1 /* Subroutines for insn-output.c for ATMEL AVR micro controllers
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov (chertykov@gmail.com)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
37 #include "diagnostic-core.h"
45 #include "target-def.h"
49 /* Maximal allowed offset for an address in the LD command */
50 #define MAX_LD_OFFSET(MODE) (64 - (signed)GET_MODE_SIZE (MODE))
52 static void avr_option_override (void);
53 static int avr_naked_function_p (tree);
54 static int interrupt_function_p (tree);
55 static int signal_function_p (tree);
56 static int avr_OS_task_function_p (tree);
57 static int avr_OS_main_function_p (tree);
58 static int avr_regs_to_save (HARD_REG_SET *);
59 static int get_sequence_length (rtx insns);
60 static int sequent_regs_live (void);
61 static const char *ptrreg_to_str (int);
62 static const char *cond_string (enum rtx_code);
63 static int avr_num_arg_regs (enum machine_mode, const_tree);
65 static RTX_CODE compare_condition (rtx insn);
66 static rtx avr_legitimize_address (rtx, rtx, enum machine_mode);
67 static int compare_sign_p (rtx insn);
68 static tree avr_handle_progmem_attribute (tree *, tree, tree, int, bool *);
69 static tree avr_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
70 static tree avr_handle_fntype_attribute (tree *, tree, tree, int, bool *);
71 static bool avr_assemble_integer (rtx, unsigned int, int);
72 static void avr_file_start (void);
73 static void avr_file_end (void);
74 static bool avr_legitimate_address_p (enum machine_mode, rtx, bool);
75 static void avr_asm_function_end_prologue (FILE *);
76 static void avr_asm_function_begin_epilogue (FILE *);
77 static rtx avr_function_value (const_tree, const_tree, bool);
78 static void avr_insert_attributes (tree, tree *);
79 static void avr_asm_init_sections (void);
80 static unsigned int avr_section_type_flags (tree, const char *, int);
82 static void avr_reorg (void);
83 static void avr_asm_out_ctor (rtx, int);
84 static void avr_asm_out_dtor (rtx, int);
85 static int avr_operand_rtx_cost (rtx, enum machine_mode, enum rtx_code, bool);
86 static bool avr_rtx_costs (rtx, int, int, int *, bool);
87 static int avr_address_cost (rtx, bool);
88 static bool avr_return_in_memory (const_tree, const_tree);
89 static struct machine_function * avr_init_machine_status (void);
90 static rtx avr_builtin_setjmp_frame_value (void);
91 static bool avr_hard_regno_scratch_ok (unsigned int);
92 static unsigned int avr_case_values_threshold (void);
93 static bool avr_frame_pointer_required_p (void);
94 static bool avr_can_eliminate (const int, const int);
95 static bool avr_class_likely_spilled_p (reg_class_t c);
96 static rtx avr_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
98 static void avr_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
101 /* Allocate registers from r25 to r8 for parameters for function calls. */
102 #define FIRST_CUM_REG 26
104 /* Temporary register RTX (gen_rtx_REG (QImode, TMP_REGNO)) */
105 static GTY(()) rtx tmp_reg_rtx;
107 /* Zeroed register RTX (gen_rtx_REG (QImode, ZERO_REGNO)) */
108 static GTY(()) rtx zero_reg_rtx;
110 /* AVR register names {"r0", "r1", ..., "r31"} */
111 static const char *const avr_regnames[] = REGISTER_NAMES;
113 /* Preprocessor macros to define depending on MCU type. */
114 const char *avr_extra_arch_macro;
116 /* Current architecture. */
117 const struct base_arch_s *avr_current_arch;
119 /* Current device. */
120 const struct mcu_type_s *avr_current_device;
122 section *progmem_section;
124 /* AVR attributes. */
125 static const struct attribute_spec avr_attribute_table[] =
127 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
128 { "progmem", 0, 0, false, false, false, avr_handle_progmem_attribute },
129 { "signal", 0, 0, true, false, false, avr_handle_fndecl_attribute },
130 { "interrupt", 0, 0, true, false, false, avr_handle_fndecl_attribute },
131 { "naked", 0, 0, false, true, true, avr_handle_fntype_attribute },
132 { "OS_task", 0, 0, false, true, true, avr_handle_fntype_attribute },
133 { "OS_main", 0, 0, false, true, true, avr_handle_fntype_attribute },
134 { NULL, 0, 0, false, false, false, NULL }
137 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
138 static const struct default_options avr_option_optimization_table[] =
140 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
141 { OPT_LEVELS_NONE, 0, NULL, 0 }
144 /* Initialize the GCC target structure. */
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\t.long\t"
149 #undef TARGET_ASM_UNALIGNED_HI_OP
150 #define TARGET_ASM_UNALIGNED_HI_OP "\t.word\t"
151 #undef TARGET_ASM_UNALIGNED_SI_OP
152 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
153 #undef TARGET_ASM_INTEGER
154 #define TARGET_ASM_INTEGER avr_assemble_integer
155 #undef TARGET_ASM_FILE_START
156 #define TARGET_ASM_FILE_START avr_file_start
157 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
158 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
159 #undef TARGET_ASM_FILE_END
160 #define TARGET_ASM_FILE_END avr_file_end
162 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
163 #define TARGET_ASM_FUNCTION_END_PROLOGUE avr_asm_function_end_prologue
164 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
165 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE avr_asm_function_begin_epilogue
166 #undef TARGET_FUNCTION_VALUE
167 #define TARGET_FUNCTION_VALUE avr_function_value
168 #undef TARGET_ATTRIBUTE_TABLE
169 #define TARGET_ATTRIBUTE_TABLE avr_attribute_table
170 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
171 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
172 #undef TARGET_INSERT_ATTRIBUTES
173 #define TARGET_INSERT_ATTRIBUTES avr_insert_attributes
174 #undef TARGET_SECTION_TYPE_FLAGS
175 #define TARGET_SECTION_TYPE_FLAGS avr_section_type_flags
176 #undef TARGET_RTX_COSTS
177 #define TARGET_RTX_COSTS avr_rtx_costs
178 #undef TARGET_ADDRESS_COST
179 #define TARGET_ADDRESS_COST avr_address_cost
180 #undef TARGET_MACHINE_DEPENDENT_REORG
181 #define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
182 #undef TARGET_FUNCTION_ARG
183 #define TARGET_FUNCTION_ARG avr_function_arg
184 #undef TARGET_FUNCTION_ARG_ADVANCE
185 #define TARGET_FUNCTION_ARG_ADVANCE avr_function_arg_advance
187 #undef TARGET_LEGITIMIZE_ADDRESS
188 #define TARGET_LEGITIMIZE_ADDRESS avr_legitimize_address
190 #undef TARGET_RETURN_IN_MEMORY
191 #define TARGET_RETURN_IN_MEMORY avr_return_in_memory
193 #undef TARGET_STRICT_ARGUMENT_NAMING
194 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
196 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
197 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE avr_builtin_setjmp_frame_value
199 #undef TARGET_HARD_REGNO_SCRATCH_OK
200 #define TARGET_HARD_REGNO_SCRATCH_OK avr_hard_regno_scratch_ok
201 #undef TARGET_CASE_VALUES_THRESHOLD
202 #define TARGET_CASE_VALUES_THRESHOLD avr_case_values_threshold
204 #undef TARGET_LEGITIMATE_ADDRESS_P
205 #define TARGET_LEGITIMATE_ADDRESS_P avr_legitimate_address_p
207 #undef TARGET_FRAME_POINTER_REQUIRED
208 #define TARGET_FRAME_POINTER_REQUIRED avr_frame_pointer_required_p
209 #undef TARGET_CAN_ELIMINATE
210 #define TARGET_CAN_ELIMINATE avr_can_eliminate
212 #undef TARGET_CLASS_LIKELY_SPILLED_P
213 #define TARGET_CLASS_LIKELY_SPILLED_P avr_class_likely_spilled_p
215 #undef TARGET_OPTION_OVERRIDE
216 #define TARGET_OPTION_OVERRIDE avr_option_override
218 #undef TARGET_OPTION_OPTIMIZATION_TABLE
219 #define TARGET_OPTION_OPTIMIZATION_TABLE avr_option_optimization_table
221 struct gcc_target targetm = TARGET_INITIALIZER;
224 avr_option_override (void)
226 const struct mcu_type_s *t;
228 flag_delete_null_pointer_checks = 0;
230 for (t = avr_mcu_types; t->name; t++)
231 if (strcmp (t->name, avr_mcu_name) == 0)
236 fprintf (stderr, "unknown MCU '%s' specified\nKnown MCU names:\n",
238 for (t = avr_mcu_types; t->name; t++)
239 fprintf (stderr," %s\n", t->name);
242 avr_current_device = t;
243 avr_current_arch = &avr_arch_types[avr_current_device->arch];
244 avr_extra_arch_macro = avr_current_device->macro;
246 tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
247 zero_reg_rtx = gen_rtx_REG (QImode, ZERO_REGNO);
249 init_machine_status = avr_init_machine_status;
252 /* return register class from register number. */
254 static const enum reg_class reg_class_tab[]={
255 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
256 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
257 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
258 GENERAL_REGS, /* r0 - r15 */
259 LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,
260 LD_REGS, /* r16 - 23 */
261 ADDW_REGS,ADDW_REGS, /* r24,r25 */
262 POINTER_X_REGS,POINTER_X_REGS, /* r26,27 */
263 POINTER_Y_REGS,POINTER_Y_REGS, /* r28,r29 */
264 POINTER_Z_REGS,POINTER_Z_REGS, /* r30,r31 */
265 STACK_REG,STACK_REG /* SPL,SPH */
268 /* Function to set up the backend function structure. */
270 static struct machine_function *
271 avr_init_machine_status (void)
273 return ggc_alloc_cleared_machine_function ();
276 /* Return register class for register R. */
279 avr_regno_reg_class (int r)
282 return reg_class_tab[r];
286 /* Return nonzero if FUNC is a naked function. */
289 avr_naked_function_p (tree func)
293 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
295 a = lookup_attribute ("naked", TYPE_ATTRIBUTES (TREE_TYPE (func)));
296 return a != NULL_TREE;
299 /* Return nonzero if FUNC is an interrupt function as specified
300 by the "interrupt" attribute. */
303 interrupt_function_p (tree func)
307 if (TREE_CODE (func) != FUNCTION_DECL)
310 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
311 return a != NULL_TREE;
314 /* Return nonzero if FUNC is a signal function as specified
315 by the "signal" attribute. */
318 signal_function_p (tree func)
322 if (TREE_CODE (func) != FUNCTION_DECL)
325 a = lookup_attribute ("signal", DECL_ATTRIBUTES (func));
326 return a != NULL_TREE;
329 /* Return nonzero if FUNC is a OS_task function. */
332 avr_OS_task_function_p (tree func)
336 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
338 a = lookup_attribute ("OS_task", TYPE_ATTRIBUTES (TREE_TYPE (func)));
339 return a != NULL_TREE;
342 /* Return nonzero if FUNC is a OS_main function. */
345 avr_OS_main_function_p (tree func)
349 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
351 a = lookup_attribute ("OS_main", TYPE_ATTRIBUTES (TREE_TYPE (func)));
352 return a != NULL_TREE;
355 /* Return the number of hard registers to push/pop in the prologue/epilogue
356 of the current function, and optionally store these registers in SET. */
359 avr_regs_to_save (HARD_REG_SET *set)
362 int int_or_sig_p = (interrupt_function_p (current_function_decl)
363 || signal_function_p (current_function_decl));
366 CLEAR_HARD_REG_SET (*set);
369 /* No need to save any registers if the function never returns or
370 is have "OS_task" or "OS_main" attribute. */
371 if (TREE_THIS_VOLATILE (current_function_decl)
372 || cfun->machine->is_OS_task
373 || cfun->machine->is_OS_main)
376 for (reg = 0; reg < 32; reg++)
378 /* Do not push/pop __tmp_reg__, __zero_reg__, as well as
379 any global register variables. */
383 if ((int_or_sig_p && !current_function_is_leaf && call_used_regs[reg])
384 || (df_regs_ever_live_p (reg)
385 && (int_or_sig_p || !call_used_regs[reg])
386 && !(frame_pointer_needed
387 && (reg == REG_Y || reg == (REG_Y+1)))))
390 SET_HARD_REG_BIT (*set, reg);
397 /* Return true if register FROM can be eliminated via register TO. */
400 avr_can_eliminate (const int from, const int to)
402 return ((from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
403 || ((from == FRAME_POINTER_REGNUM
404 || from == FRAME_POINTER_REGNUM + 1)
405 && !frame_pointer_needed));
408 /* Compute offset between arg_pointer and frame_pointer. */
411 avr_initial_elimination_offset (int from, int to)
413 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
417 int offset = frame_pointer_needed ? 2 : 0;
418 int avr_pc_size = AVR_HAVE_EIJMP_EICALL ? 3 : 2;
420 offset += avr_regs_to_save (NULL);
421 return get_frame_size () + (avr_pc_size) + 1 + offset;
425 /* Actual start of frame is virtual_stack_vars_rtx this is offset from
426 frame pointer by +STARTING_FRAME_OFFSET.
427 Using saved frame = virtual_stack_vars_rtx - STARTING_FRAME_OFFSET
428 avoids creating add/sub of offset in nonlocal goto and setjmp. */
430 rtx avr_builtin_setjmp_frame_value (void)
432 return gen_rtx_MINUS (Pmode, virtual_stack_vars_rtx,
433 gen_int_mode (STARTING_FRAME_OFFSET, Pmode));
436 /* Return contents of MEM at frame pointer + stack size + 1 (+2 if 3 byte PC).
437 This is return address of function. */
439 avr_return_addr_rtx (int count, rtx tem)
443 /* Can only return this functions return address. Others not supported. */
449 r = gen_rtx_SYMBOL_REF (Pmode, ".L__stack_usage+2");
450 warning (0, "'builtin_return_address' contains only 2 bytes of address");
453 r = gen_rtx_SYMBOL_REF (Pmode, ".L__stack_usage+1");
455 r = gen_rtx_PLUS (Pmode, tem, r);
456 r = gen_frame_mem (Pmode, memory_address (Pmode, r));
457 r = gen_rtx_ROTATE (HImode, r, GEN_INT (8));
461 /* Return 1 if the function epilogue is just a single "ret". */
464 avr_simple_epilogue (void)
466 return (! frame_pointer_needed
467 && get_frame_size () == 0
468 && avr_regs_to_save (NULL) == 0
469 && ! interrupt_function_p (current_function_decl)
470 && ! signal_function_p (current_function_decl)
471 && ! avr_naked_function_p (current_function_decl)
472 && ! TREE_THIS_VOLATILE (current_function_decl));
475 /* This function checks sequence of live registers. */
478 sequent_regs_live (void)
484 for (reg = 0; reg < 18; ++reg)
486 if (!call_used_regs[reg])
488 if (df_regs_ever_live_p (reg))
498 if (!frame_pointer_needed)
500 if (df_regs_ever_live_p (REG_Y))
508 if (df_regs_ever_live_p (REG_Y+1))
521 return (cur_seq == live_seq) ? live_seq : 0;
524 /* Obtain the length sequence of insns. */
527 get_sequence_length (rtx insns)
532 for (insn = insns, length = 0; insn; insn = NEXT_INSN (insn))
533 length += get_attr_length (insn);
538 /* Output function prologue. */
541 expand_prologue (void)
546 HOST_WIDE_INT size = get_frame_size();
547 /* Define templates for push instructions. */
548 rtx pushbyte = gen_rtx_MEM (QImode,
549 gen_rtx_POST_DEC (HImode, stack_pointer_rtx));
550 rtx pushword = gen_rtx_MEM (HImode,
551 gen_rtx_POST_DEC (HImode, stack_pointer_rtx));
554 /* Init cfun->machine. */
555 cfun->machine->is_naked = avr_naked_function_p (current_function_decl);
556 cfun->machine->is_interrupt = interrupt_function_p (current_function_decl);
557 cfun->machine->is_signal = signal_function_p (current_function_decl);
558 cfun->machine->is_OS_task = avr_OS_task_function_p (current_function_decl);
559 cfun->machine->is_OS_main = avr_OS_main_function_p (current_function_decl);
560 cfun->machine->stack_usage = 0;
562 /* Prologue: naked. */
563 if (cfun->machine->is_naked)
568 avr_regs_to_save (&set);
569 live_seq = sequent_regs_live ();
570 minimize = (TARGET_CALL_PROLOGUES
571 && !cfun->machine->is_interrupt
572 && !cfun->machine->is_signal
573 && !cfun->machine->is_OS_task
574 && !cfun->machine->is_OS_main
577 if (cfun->machine->is_interrupt || cfun->machine->is_signal)
579 if (cfun->machine->is_interrupt)
581 /* Enable interrupts. */
582 insn = emit_insn (gen_enable_interrupt ());
583 RTX_FRAME_RELATED_P (insn) = 1;
587 insn = emit_move_insn (pushbyte, zero_reg_rtx);
588 RTX_FRAME_RELATED_P (insn) = 1;
589 cfun->machine->stack_usage++;
592 insn = emit_move_insn (pushbyte, tmp_reg_rtx);
593 RTX_FRAME_RELATED_P (insn) = 1;
594 cfun->machine->stack_usage++;
597 insn = emit_move_insn (tmp_reg_rtx,
598 gen_rtx_MEM (QImode, GEN_INT (SREG_ADDR)));
599 RTX_FRAME_RELATED_P (insn) = 1;
600 insn = emit_move_insn (pushbyte, tmp_reg_rtx);
601 RTX_FRAME_RELATED_P (insn) = 1;
602 cfun->machine->stack_usage++;
606 && (TEST_HARD_REG_BIT (set, REG_Z) && TEST_HARD_REG_BIT (set, REG_Z + 1)))
608 insn = emit_move_insn (tmp_reg_rtx,
609 gen_rtx_MEM (QImode, GEN_INT (RAMPZ_ADDR)));
610 RTX_FRAME_RELATED_P (insn) = 1;
611 insn = emit_move_insn (pushbyte, tmp_reg_rtx);
612 RTX_FRAME_RELATED_P (insn) = 1;
613 cfun->machine->stack_usage++;
616 /* Clear zero reg. */
617 insn = emit_move_insn (zero_reg_rtx, const0_rtx);
618 RTX_FRAME_RELATED_P (insn) = 1;
620 /* Prevent any attempt to delete the setting of ZERO_REG! */
621 emit_use (zero_reg_rtx);
623 if (minimize && (frame_pointer_needed
624 || (AVR_2_BYTE_PC && live_seq > 6)
627 insn = emit_move_insn (gen_rtx_REG (HImode, REG_X),
628 gen_int_mode (size, HImode));
629 RTX_FRAME_RELATED_P (insn) = 1;
632 emit_insn (gen_call_prologue_saves (gen_int_mode (live_seq, HImode),
633 gen_int_mode (size + live_seq, HImode)));
634 RTX_FRAME_RELATED_P (insn) = 1;
635 cfun->machine->stack_usage += size + live_seq;
640 for (reg = 0; reg < 32; ++reg)
642 if (TEST_HARD_REG_BIT (set, reg))
644 /* Emit push of register to save. */
645 insn=emit_move_insn (pushbyte, gen_rtx_REG (QImode, reg));
646 RTX_FRAME_RELATED_P (insn) = 1;
647 cfun->machine->stack_usage++;
650 if (frame_pointer_needed)
652 if (!(cfun->machine->is_OS_task || cfun->machine->is_OS_main))
654 /* Push frame pointer. */
655 insn = emit_move_insn (pushword, frame_pointer_rtx);
656 RTX_FRAME_RELATED_P (insn) = 1;
657 cfun->machine->stack_usage += 2;
662 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
663 RTX_FRAME_RELATED_P (insn) = 1;
667 /* Creating a frame can be done by direct manipulation of the
668 stack or via the frame pointer. These two methods are:
675 the optimum method depends on function type, stack and frame size.
676 To avoid a complex logic, both methods are tested and shortest
680 rtx sp_plus_insns = NULL_RTX;
682 if (AVR_HAVE_8BIT_SP)
684 /* The high byte (r29) doesn't change - prefer 'subi' (1 cycle)
685 over 'sbiw' (2 cycles, same size). */
686 myfp = gen_rtx_REG (QImode, REGNO (frame_pointer_rtx));
690 /* Normal sized addition. */
691 myfp = frame_pointer_rtx;
694 /* Method 1-Adjust frame pointer. */
697 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
698 RTX_FRAME_RELATED_P (insn) = 1;
701 emit_move_insn (myfp,
702 gen_rtx_PLUS (GET_MODE(myfp), myfp,
705 RTX_FRAME_RELATED_P (insn) = 1;
707 /* Copy to stack pointer. */
708 if (AVR_HAVE_8BIT_SP)
710 insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
711 RTX_FRAME_RELATED_P (insn) = 1;
713 else if (TARGET_NO_INTERRUPTS
714 || cfun->machine->is_signal
715 || cfun->machine->is_OS_main)
718 emit_insn (gen_movhi_sp_r_irq_off (stack_pointer_rtx,
720 RTX_FRAME_RELATED_P (insn) = 1;
722 else if (cfun->machine->is_interrupt)
724 insn = emit_insn (gen_movhi_sp_r_irq_on (stack_pointer_rtx,
726 RTX_FRAME_RELATED_P (insn) = 1;
730 insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
731 RTX_FRAME_RELATED_P (insn) = 1;
734 fp_plus_insns = get_insns ();
737 /* Method 2-Adjust Stack pointer. */
743 emit_move_insn (stack_pointer_rtx,
744 gen_rtx_PLUS (HImode,
748 RTX_FRAME_RELATED_P (insn) = 1;
751 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
752 RTX_FRAME_RELATED_P (insn) = 1;
754 sp_plus_insns = get_insns ();
758 /* Use shortest method. */
759 if (size <= 6 && (get_sequence_length (sp_plus_insns)
760 < get_sequence_length (fp_plus_insns)))
761 emit_insn (sp_plus_insns);
763 emit_insn (fp_plus_insns);
764 cfun->machine->stack_usage += size;
769 if (flag_stack_usage)
770 current_function_static_stack_size = cfun->machine->stack_usage;
773 /* Output summary at end of function prologue. */
776 avr_asm_function_end_prologue (FILE *file)
778 if (cfun->machine->is_naked)
780 fputs ("/* prologue: naked */\n", file);
784 if (cfun->machine->is_interrupt)
786 fputs ("/* prologue: Interrupt */\n", file);
788 else if (cfun->machine->is_signal)
790 fputs ("/* prologue: Signal */\n", file);
793 fputs ("/* prologue: function */\n", file);
795 fprintf (file, "/* frame size = " HOST_WIDE_INT_PRINT_DEC " */\n",
797 fprintf (file, "/* stack size = %d */\n",
798 cfun->machine->stack_usage);
799 /* Create symbol stack offset here so all functions have it. Add 1 to stack
800 usage for offset so that SP + .L__stack_offset = return address. */
801 fprintf (file, ".L__stack_usage = %d\n", cfun->machine->stack_usage);
805 /* Implement EPILOGUE_USES. */
808 avr_epilogue_uses (int regno ATTRIBUTE_UNUSED)
812 && (cfun->machine->is_interrupt || cfun->machine->is_signal))
817 /* Output RTL epilogue. */
820 expand_epilogue (void)
826 HOST_WIDE_INT size = get_frame_size();
828 /* epilogue: naked */
829 if (cfun->machine->is_naked)
831 emit_jump_insn (gen_return ());
835 avr_regs_to_save (&set);
836 live_seq = sequent_regs_live ();
837 minimize = (TARGET_CALL_PROLOGUES
838 && !cfun->machine->is_interrupt
839 && !cfun->machine->is_signal
840 && !cfun->machine->is_OS_task
841 && !cfun->machine->is_OS_main
844 if (minimize && (frame_pointer_needed || live_seq > 4))
846 if (frame_pointer_needed)
848 /* Get rid of frame. */
849 emit_move_insn(frame_pointer_rtx,
850 gen_rtx_PLUS (HImode, frame_pointer_rtx,
851 gen_int_mode (size, HImode)));
855 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
858 emit_insn (gen_epilogue_restores (gen_int_mode (live_seq, HImode)));
862 if (frame_pointer_needed)
866 /* Try two methods to adjust stack and select shortest. */
869 rtx sp_plus_insns = NULL_RTX;
871 if (AVR_HAVE_8BIT_SP)
873 /* The high byte (r29) doesn't change - prefer 'subi'
874 (1 cycle) over 'sbiw' (2 cycles, same size). */
875 myfp = gen_rtx_REG (QImode, REGNO (frame_pointer_rtx));
879 /* Normal sized addition. */
880 myfp = frame_pointer_rtx;
883 /* Method 1-Adjust frame pointer. */
886 emit_move_insn (myfp,
887 gen_rtx_PLUS (GET_MODE (myfp), myfp,
891 /* Copy to stack pointer. */
892 if (AVR_HAVE_8BIT_SP)
894 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
896 else if (TARGET_NO_INTERRUPTS
897 || cfun->machine->is_signal)
899 emit_insn (gen_movhi_sp_r_irq_off (stack_pointer_rtx,
902 else if (cfun->machine->is_interrupt)
904 emit_insn (gen_movhi_sp_r_irq_on (stack_pointer_rtx,
909 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
912 fp_plus_insns = get_insns ();
915 /* Method 2-Adjust Stack pointer. */
920 emit_move_insn (stack_pointer_rtx,
921 gen_rtx_PLUS (HImode, stack_pointer_rtx,
925 sp_plus_insns = get_insns ();
929 /* Use shortest method. */
930 if (size <= 5 && (get_sequence_length (sp_plus_insns)
931 < get_sequence_length (fp_plus_insns)))
932 emit_insn (sp_plus_insns);
934 emit_insn (fp_plus_insns);
936 if (!(cfun->machine->is_OS_task || cfun->machine->is_OS_main))
938 /* Restore previous frame_pointer. */
939 emit_insn (gen_pophi (frame_pointer_rtx));
942 /* Restore used registers. */
943 for (reg = 31; reg >= 0; --reg)
945 if (TEST_HARD_REG_BIT (set, reg))
946 emit_insn (gen_popqi (gen_rtx_REG (QImode, reg)));
948 if (cfun->machine->is_interrupt || cfun->machine->is_signal)
950 /* Restore RAMPZ using tmp reg as scratch. */
952 && (TEST_HARD_REG_BIT (set, REG_Z) && TEST_HARD_REG_BIT (set, REG_Z + 1)))
954 emit_insn (gen_popqi (tmp_reg_rtx));
955 emit_move_insn (gen_rtx_MEM(QImode, GEN_INT(RAMPZ_ADDR)),
959 /* Restore SREG using tmp reg as scratch. */
960 emit_insn (gen_popqi (tmp_reg_rtx));
962 emit_move_insn (gen_rtx_MEM(QImode, GEN_INT(SREG_ADDR)),
965 /* Restore tmp REG. */
966 emit_insn (gen_popqi (tmp_reg_rtx));
968 /* Restore zero REG. */
969 emit_insn (gen_popqi (zero_reg_rtx));
972 emit_jump_insn (gen_return ());
976 /* Output summary messages at beginning of function epilogue. */
979 avr_asm_function_begin_epilogue (FILE *file)
981 fprintf (file, "/* epilogue start */\n");
984 /* Return nonzero if X (an RTX) is a legitimate memory address on the target
985 machine for a memory operand of mode MODE. */
988 avr_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
990 enum reg_class r = NO_REGS;
992 if (TARGET_ALL_DEBUG)
994 fprintf (stderr, "mode: (%s) %s %s %s %s:",
996 strict ? "(strict)": "",
997 reload_completed ? "(reload_completed)": "",
998 reload_in_progress ? "(reload_in_progress)": "",
999 reg_renumber ? "(reg_renumber)" : "");
1000 if (GET_CODE (x) == PLUS
1001 && REG_P (XEXP (x, 0))
1002 && GET_CODE (XEXP (x, 1)) == CONST_INT
1003 && INTVAL (XEXP (x, 1)) >= 0
1004 && INTVAL (XEXP (x, 1)) <= MAX_LD_OFFSET (mode)
1007 fprintf (stderr, "(r%d ---> r%d)", REGNO (XEXP (x, 0)),
1008 true_regnum (XEXP (x, 0)));
1011 if (!strict && GET_CODE (x) == SUBREG)
1013 if (REG_P (x) && (strict ? REG_OK_FOR_BASE_STRICT_P (x)
1014 : REG_OK_FOR_BASE_NOSTRICT_P (x)))
1016 else if (CONSTANT_ADDRESS_P (x))
1018 else if (GET_CODE (x) == PLUS
1019 && REG_P (XEXP (x, 0))
1020 && GET_CODE (XEXP (x, 1)) == CONST_INT
1021 && INTVAL (XEXP (x, 1)) >= 0)
1023 int fit = INTVAL (XEXP (x, 1)) <= MAX_LD_OFFSET (mode);
1027 || REGNO (XEXP (x,0)) == REG_X
1028 || REGNO (XEXP (x,0)) == REG_Y
1029 || REGNO (XEXP (x,0)) == REG_Z)
1030 r = BASE_POINTER_REGS;
1031 if (XEXP (x,0) == frame_pointer_rtx
1032 || XEXP (x,0) == arg_pointer_rtx)
1033 r = BASE_POINTER_REGS;
1035 else if (frame_pointer_needed && XEXP (x,0) == frame_pointer_rtx)
1038 else if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1039 && REG_P (XEXP (x, 0))
1040 && (strict ? REG_OK_FOR_BASE_STRICT_P (XEXP (x, 0))
1041 : REG_OK_FOR_BASE_NOSTRICT_P (XEXP (x, 0))))
1045 if (TARGET_ALL_DEBUG)
1047 fprintf (stderr, " ret = %c\n", r + '0');
1049 return r == NO_REGS ? 0 : (int)r;
1052 /* Attempts to replace X with a valid
1053 memory address for an operand of mode MODE */
1056 avr_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
1059 if (TARGET_ALL_DEBUG)
1061 fprintf (stderr, "legitimize_address mode: %s", GET_MODE_NAME(mode));
1065 if (GET_CODE (oldx) == PLUS
1066 && REG_P (XEXP (oldx,0)))
1068 if (REG_P (XEXP (oldx,1)))
1069 x = force_reg (GET_MODE (oldx), oldx);
1070 else if (GET_CODE (XEXP (oldx, 1)) == CONST_INT)
1072 int offs = INTVAL (XEXP (oldx,1));
1073 if (frame_pointer_rtx != XEXP (oldx,0))
1074 if (offs > MAX_LD_OFFSET (mode))
1076 if (TARGET_ALL_DEBUG)
1077 fprintf (stderr, "force_reg (big offset)\n");
1078 x = force_reg (GET_MODE (oldx), oldx);
1086 /* Return a pointer register name as a string. */
1089 ptrreg_to_str (int regno)
1093 case REG_X: return "X";
1094 case REG_Y: return "Y";
1095 case REG_Z: return "Z";
1097 output_operand_lossage ("address operand requires constraint for X, Y, or Z register");
1102 /* Return the condition name as a string.
1103 Used in conditional jump constructing */
1106 cond_string (enum rtx_code code)
1115 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1120 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1133 /* Output ADDR to FILE as address. */
1136 print_operand_address (FILE *file, rtx addr)
1138 switch (GET_CODE (addr))
1141 fprintf (file, ptrreg_to_str (REGNO (addr)));
1145 fprintf (file, "-%s", ptrreg_to_str (REGNO (XEXP (addr, 0))));
1149 fprintf (file, "%s+", ptrreg_to_str (REGNO (XEXP (addr, 0))));
1153 if (CONSTANT_ADDRESS_P (addr)
1154 && text_segment_operand (addr, VOIDmode))
1156 rtx x = XEXP (addr,0);
1157 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x,1)) == CONST_INT)
1159 /* Assembler gs() will implant word address. Make offset
1160 a byte offset inside gs() for assembler. This is
1161 needed because the more logical (constant+gs(sym)) is not
1162 accepted by gas. For 128K and lower devices this is ok. For
1163 large devices it will create a Trampoline to offset from symbol
1164 which may not be what the user really wanted. */
1165 fprintf (file, "gs(");
1166 output_addr_const (file, XEXP (x,0));
1167 fprintf (file,"+" HOST_WIDE_INT_PRINT_DEC ")", 2 * INTVAL (XEXP (x,1)));
1169 if (warning (0, "pointer offset from symbol maybe incorrect"))
1171 output_addr_const (stderr, addr);
1172 fprintf(stderr,"\n");
1177 fprintf (file, "gs(");
1178 output_addr_const (file, addr);
1179 fprintf (file, ")");
1183 output_addr_const (file, addr);
1188 /* Output X as assembler operand to file FILE. */
1191 print_operand (FILE *file, rtx x, int code)
1195 if (code >= 'A' && code <= 'D')
1200 if (!AVR_HAVE_JMP_CALL)
1203 else if (code == '!')
1205 if (AVR_HAVE_EIJMP_EICALL)
1210 if (x == zero_reg_rtx)
1211 fprintf (file, "__zero_reg__");
1213 fprintf (file, reg_names[true_regnum (x) + abcd]);
1215 else if (GET_CODE (x) == CONST_INT)
1216 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) + abcd);
1217 else if (GET_CODE (x) == MEM)
1219 rtx addr = XEXP (x,0);
1222 if (!CONSTANT_P (addr))
1223 fatal_insn ("bad address, not a constant):", addr);
1224 /* Assembler template with m-code is data - not progmem section */
1225 if (text_segment_operand (addr, VOIDmode))
1226 if (warning ( 0, "accessing data memory with program memory address"))
1228 output_addr_const (stderr, addr);
1229 fprintf(stderr,"\n");
1231 output_addr_const (file, addr);
1233 else if (code == 'o')
1235 if (GET_CODE (addr) != PLUS)
1236 fatal_insn ("bad address, not (reg+disp):", addr);
1238 print_operand (file, XEXP (addr, 1), 0);
1240 else if (code == 'p' || code == 'r')
1242 if (GET_CODE (addr) != POST_INC && GET_CODE (addr) != PRE_DEC)
1243 fatal_insn ("bad address, not post_inc or pre_dec:", addr);
1246 print_operand_address (file, XEXP (addr, 0)); /* X, Y, Z */
1248 print_operand (file, XEXP (addr, 0), 0); /* r26, r28, r30 */
1250 else if (GET_CODE (addr) == PLUS)
1252 print_operand_address (file, XEXP (addr,0));
1253 if (REGNO (XEXP (addr, 0)) == REG_X)
1254 fatal_insn ("internal compiler error. Bad address:"
1257 print_operand (file, XEXP (addr,1), code);
1260 print_operand_address (file, addr);
1262 else if (code == 'x')
1264 /* Constant progmem address - like used in jmp or call */
1265 if (0 == text_segment_operand (x, VOIDmode))
1266 if (warning ( 0, "accessing program memory with data memory address"))
1268 output_addr_const (stderr, x);
1269 fprintf(stderr,"\n");
1271 /* Use normal symbol for direct address no linker trampoline needed */
1272 output_addr_const (file, x);
1274 else if (GET_CODE (x) == CONST_DOUBLE)
1278 if (GET_MODE (x) != SFmode)
1279 fatal_insn ("internal compiler error. Unknown mode:", x);
1280 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1281 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1282 fprintf (file, "0x%lx", val);
1284 else if (code == 'j')
1285 fputs (cond_string (GET_CODE (x)), file);
1286 else if (code == 'k')
1287 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1289 print_operand_address (file, x);
1292 /* Update the condition code in the INSN. */
1295 notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
1299 switch (get_attr_cc (insn))
1302 /* Insn does not affect CC at all. */
1310 set = single_set (insn);
1314 cc_status.flags |= CC_NO_OVERFLOW;
1315 cc_status.value1 = SET_DEST (set);
1320 /* Insn sets the Z,N,C flags of CC to recog_operand[0].
1321 The V flag may or may not be known but that's ok because
1322 alter_cond will change tests to use EQ/NE. */
1323 set = single_set (insn);
1327 cc_status.value1 = SET_DEST (set);
1328 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
1333 set = single_set (insn);
1336 cc_status.value1 = SET_SRC (set);
1340 /* Insn doesn't leave CC in a usable state. */
1343 /* Correct CC for the ashrqi3 with the shift count as CONST_INT != 6 */
1344 set = single_set (insn);
1347 rtx src = SET_SRC (set);
1349 if (GET_CODE (src) == ASHIFTRT
1350 && GET_MODE (src) == QImode)
1352 rtx x = XEXP (src, 1);
1354 if (GET_CODE (x) == CONST_INT
1358 cc_status.value1 = SET_DEST (set);
1359 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
1367 /* Return maximum number of consecutive registers of
1368 class CLASS needed to hold a value of mode MODE. */
1371 class_max_nregs (enum reg_class rclass ATTRIBUTE_UNUSED,enum machine_mode mode)
1373 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1376 /* Choose mode for jump insn:
1377 1 - relative jump in range -63 <= x <= 62 ;
1378 2 - relative jump in range -2046 <= x <= 2045 ;
1379 3 - absolute jump (only for ATmega[16]03). */
1382 avr_jump_mode (rtx x, rtx insn)
1384 int dest_addr = INSN_ADDRESSES (INSN_UID (GET_CODE (x) == LABEL_REF
1385 ? XEXP (x, 0) : x));
1386 int cur_addr = INSN_ADDRESSES (INSN_UID (insn));
1387 int jump_distance = cur_addr - dest_addr;
1389 if (-63 <= jump_distance && jump_distance <= 62)
1391 else if (-2046 <= jump_distance && jump_distance <= 2045)
1393 else if (AVR_HAVE_JMP_CALL)
1399 /* return an AVR condition jump commands.
1400 X is a comparison RTX.
1401 LEN is a number returned by avr_jump_mode function.
1402 if REVERSE nonzero then condition code in X must be reversed. */
1405 ret_cond_branch (rtx x, int len, int reverse)
1407 RTX_CODE cond = reverse ? reverse_condition (GET_CODE (x)) : GET_CODE (x);
1412 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1413 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1415 len == 2 ? (AS1 (breq,.+4) CR_TAB
1416 AS1 (brmi,.+2) CR_TAB
1418 (AS1 (breq,.+6) CR_TAB
1419 AS1 (brmi,.+4) CR_TAB
1423 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1425 len == 2 ? (AS1 (breq,.+4) CR_TAB
1426 AS1 (brlt,.+2) CR_TAB
1428 (AS1 (breq,.+6) CR_TAB
1429 AS1 (brlt,.+4) CR_TAB
1432 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1434 len == 2 ? (AS1 (breq,.+4) CR_TAB
1435 AS1 (brlo,.+2) CR_TAB
1437 (AS1 (breq,.+6) CR_TAB
1438 AS1 (brlo,.+4) CR_TAB
1441 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1442 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1444 len == 2 ? (AS1 (breq,.+2) CR_TAB
1445 AS1 (brpl,.+2) CR_TAB
1447 (AS1 (breq,.+2) CR_TAB
1448 AS1 (brpl,.+4) CR_TAB
1451 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1453 len == 2 ? (AS1 (breq,.+2) CR_TAB
1454 AS1 (brge,.+2) CR_TAB
1456 (AS1 (breq,.+2) CR_TAB
1457 AS1 (brge,.+4) CR_TAB
1460 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1462 len == 2 ? (AS1 (breq,.+2) CR_TAB
1463 AS1 (brsh,.+2) CR_TAB
1465 (AS1 (breq,.+2) CR_TAB
1466 AS1 (brsh,.+4) CR_TAB
1474 return AS1 (br%k1,%0);
1476 return (AS1 (br%j1,.+2) CR_TAB
1479 return (AS1 (br%j1,.+4) CR_TAB
1488 return AS1 (br%j1,%0);
1490 return (AS1 (br%k1,.+2) CR_TAB
1493 return (AS1 (br%k1,.+4) CR_TAB
1501 /* Predicate function for immediate operand which fits to byte (8bit) */
1504 byte_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1506 return (GET_CODE (op) == CONST_INT
1507 && INTVAL (op) <= 0xff && INTVAL (op) >= 0);
1510 /* Output insn cost for next insn. */
1513 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1514 int num_operands ATTRIBUTE_UNUSED)
1516 if (TARGET_ALL_DEBUG)
1518 fprintf (asm_out_file, "/* DEBUG: cost = %d. */\n",
1519 rtx_cost (PATTERN (insn), INSN, !optimize_size));
1523 /* Return 0 if undefined, 1 if always true or always false. */
1526 avr_simplify_comparison_p (enum machine_mode mode, RTX_CODE op, rtx x)
1528 unsigned int max = (mode == QImode ? 0xff :
1529 mode == HImode ? 0xffff :
1530 mode == SImode ? 0xffffffff : 0);
1531 if (max && op && GET_CODE (x) == CONST_INT)
1533 if (unsigned_condition (op) != op)
1536 if (max != (INTVAL (x) & max)
1537 && INTVAL (x) != 0xff)
1544 /* Returns nonzero if REGNO is the number of a hard
1545 register in which function arguments are sometimes passed. */
1548 function_arg_regno_p(int r)
1550 return (r >= 8 && r <= 25);
1553 /* Initializing the variable cum for the state at the beginning
1554 of the argument list. */
1557 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname,
1558 tree fndecl ATTRIBUTE_UNUSED)
1561 cum->regno = FIRST_CUM_REG;
1562 if (!libname && stdarg_p (fntype))
1566 /* Returns the number of registers to allocate for a function argument. */
1569 avr_num_arg_regs (enum machine_mode mode, const_tree type)
1573 if (mode == BLKmode)
1574 size = int_size_in_bytes (type);
1576 size = GET_MODE_SIZE (mode);
1578 /* Align all function arguments to start in even-numbered registers.
1579 Odd-sized arguments leave holes above them. */
1581 return (size + 1) & ~1;
1584 /* Controls whether a function argument is passed
1585 in a register, and which register. */
1588 avr_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1589 const_tree type, bool named ATTRIBUTE_UNUSED)
1591 int bytes = avr_num_arg_regs (mode, type);
1593 if (cum->nregs && bytes <= cum->nregs)
1594 return gen_rtx_REG (mode, cum->regno - bytes);
1599 /* Update the summarizer variable CUM to advance past an argument
1600 in the argument list. */
1603 avr_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1604 const_tree type, bool named ATTRIBUTE_UNUSED)
1606 int bytes = avr_num_arg_regs (mode, type);
1608 cum->nregs -= bytes;
1609 cum->regno -= bytes;
1611 if (cum->nregs <= 0)
1614 cum->regno = FIRST_CUM_REG;
1618 /***********************************************************************
1619 Functions for outputting various mov's for a various modes
1620 ************************************************************************/
1622 output_movqi (rtx insn, rtx operands[], int *l)
1625 rtx dest = operands[0];
1626 rtx src = operands[1];
1634 if (register_operand (dest, QImode))
1636 if (register_operand (src, QImode)) /* mov r,r */
1638 if (test_hard_reg_class (STACK_REG, dest))
1639 return AS2 (out,%0,%1);
1640 else if (test_hard_reg_class (STACK_REG, src))
1641 return AS2 (in,%0,%1);
1643 return AS2 (mov,%0,%1);
1645 else if (CONSTANT_P (src))
1647 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
1648 return AS2 (ldi,%0,lo8(%1));
1650 if (GET_CODE (src) == CONST_INT)
1652 if (src == const0_rtx) /* mov r,L */
1653 return AS1 (clr,%0);
1654 else if (src == const1_rtx)
1657 return (AS1 (clr,%0) CR_TAB
1660 else if (src == constm1_rtx)
1662 /* Immediate constants -1 to any register */
1664 return (AS1 (clr,%0) CR_TAB
1669 int bit_nr = exact_log2 (INTVAL (src));
1675 output_asm_insn ((AS1 (clr,%0) CR_TAB
1678 avr_output_bld (operands, bit_nr);
1685 /* Last resort, larger than loading from memory. */
1687 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1688 AS2 (ldi,r31,lo8(%1)) CR_TAB
1689 AS2 (mov,%0,r31) CR_TAB
1690 AS2 (mov,r31,__tmp_reg__));
1692 else if (GET_CODE (src) == MEM)
1693 return out_movqi_r_mr (insn, operands, real_l); /* mov r,m */
1695 else if (GET_CODE (dest) == MEM)
1699 if (src == const0_rtx)
1700 operands[1] = zero_reg_rtx;
1702 templ = out_movqi_mr_r (insn, operands, real_l);
1705 output_asm_insn (templ, operands);
1714 output_movhi (rtx insn, rtx operands[], int *l)
1717 rtx dest = operands[0];
1718 rtx src = operands[1];
1724 if (register_operand (dest, HImode))
1726 if (register_operand (src, HImode)) /* mov r,r */
1728 if (test_hard_reg_class (STACK_REG, dest))
1730 if (AVR_HAVE_8BIT_SP)
1731 return *l = 1, AS2 (out,__SP_L__,%A1);
1732 /* Use simple load of stack pointer if no interrupts are
1734 else if (TARGET_NO_INTERRUPTS)
1735 return *l = 2, (AS2 (out,__SP_H__,%B1) CR_TAB
1736 AS2 (out,__SP_L__,%A1));
1738 return (AS2 (in,__tmp_reg__,__SREG__) CR_TAB
1740 AS2 (out,__SP_H__,%B1) CR_TAB
1741 AS2 (out,__SREG__,__tmp_reg__) CR_TAB
1742 AS2 (out,__SP_L__,%A1));
1744 else if (test_hard_reg_class (STACK_REG, src))
1747 return (AS2 (in,%A0,__SP_L__) CR_TAB
1748 AS2 (in,%B0,__SP_H__));
1754 return (AS2 (movw,%0,%1));
1759 return (AS2 (mov,%A0,%A1) CR_TAB
1763 else if (CONSTANT_P (src))
1765 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
1768 return (AS2 (ldi,%A0,lo8(%1)) CR_TAB
1769 AS2 (ldi,%B0,hi8(%1)));
1772 if (GET_CODE (src) == CONST_INT)
1774 if (src == const0_rtx) /* mov r,L */
1777 return (AS1 (clr,%A0) CR_TAB
1780 else if (src == const1_rtx)
1783 return (AS1 (clr,%A0) CR_TAB
1784 AS1 (clr,%B0) CR_TAB
1787 else if (src == constm1_rtx)
1789 /* Immediate constants -1 to any register */
1791 return (AS1 (clr,%0) CR_TAB
1792 AS1 (dec,%A0) CR_TAB
1797 int bit_nr = exact_log2 (INTVAL (src));
1803 output_asm_insn ((AS1 (clr,%A0) CR_TAB
1804 AS1 (clr,%B0) CR_TAB
1807 avr_output_bld (operands, bit_nr);
1813 if ((INTVAL (src) & 0xff) == 0)
1816 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1817 AS1 (clr,%A0) CR_TAB
1818 AS2 (ldi,r31,hi8(%1)) CR_TAB
1819 AS2 (mov,%B0,r31) CR_TAB
1820 AS2 (mov,r31,__tmp_reg__));
1822 else if ((INTVAL (src) & 0xff00) == 0)
1825 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1826 AS2 (ldi,r31,lo8(%1)) CR_TAB
1827 AS2 (mov,%A0,r31) CR_TAB
1828 AS1 (clr,%B0) CR_TAB
1829 AS2 (mov,r31,__tmp_reg__));
1833 /* Last resort, equal to loading from memory. */
1835 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1836 AS2 (ldi,r31,lo8(%1)) CR_TAB
1837 AS2 (mov,%A0,r31) CR_TAB
1838 AS2 (ldi,r31,hi8(%1)) CR_TAB
1839 AS2 (mov,%B0,r31) CR_TAB
1840 AS2 (mov,r31,__tmp_reg__));
1842 else if (GET_CODE (src) == MEM)
1843 return out_movhi_r_mr (insn, operands, real_l); /* mov r,m */
1845 else if (GET_CODE (dest) == MEM)
1849 if (src == const0_rtx)
1850 operands[1] = zero_reg_rtx;
1852 templ = out_movhi_mr_r (insn, operands, real_l);
1855 output_asm_insn (templ, operands);
1860 fatal_insn ("invalid insn:", insn);
1865 out_movqi_r_mr (rtx insn, rtx op[], int *l)
1869 rtx x = XEXP (src, 0);
1875 if (CONSTANT_ADDRESS_P (x))
1877 if (CONST_INT_P (x) && INTVAL (x) == SREG_ADDR)
1880 return AS2 (in,%0,__SREG__);
1882 if (optimize > 0 && io_address_operand (x, QImode))
1885 return AS2 (in,%0,%m1-0x20);
1888 return AS2 (lds,%0,%m1);
1890 /* memory access by reg+disp */
1891 else if (GET_CODE (x) == PLUS
1892 && REG_P (XEXP (x,0))
1893 && GET_CODE (XEXP (x,1)) == CONST_INT)
1895 if ((INTVAL (XEXP (x,1)) - GET_MODE_SIZE (GET_MODE (src))) >= 63)
1897 int disp = INTVAL (XEXP (x,1));
1898 if (REGNO (XEXP (x,0)) != REG_Y)
1899 fatal_insn ("incorrect insn:",insn);
1901 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
1902 return *l = 3, (AS2 (adiw,r28,%o1-63) CR_TAB
1903 AS2 (ldd,%0,Y+63) CR_TAB
1904 AS2 (sbiw,r28,%o1-63));
1906 return *l = 5, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
1907 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
1908 AS2 (ld,%0,Y) CR_TAB
1909 AS2 (subi,r28,lo8(%o1)) CR_TAB
1910 AS2 (sbci,r29,hi8(%o1)));
1912 else if (REGNO (XEXP (x,0)) == REG_X)
1914 /* This is a paranoid case LEGITIMIZE_RELOAD_ADDRESS must exclude
1915 it but I have this situation with extremal optimizing options. */
1916 if (reg_overlap_mentioned_p (dest, XEXP (x,0))
1917 || reg_unused_after (insn, XEXP (x,0)))
1918 return *l = 2, (AS2 (adiw,r26,%o1) CR_TAB
1921 return *l = 3, (AS2 (adiw,r26,%o1) CR_TAB
1922 AS2 (ld,%0,X) CR_TAB
1923 AS2 (sbiw,r26,%o1));
1926 return AS2 (ldd,%0,%1);
1929 return AS2 (ld,%0,%1);
1933 out_movhi_r_mr (rtx insn, rtx op[], int *l)
1937 rtx base = XEXP (src, 0);
1938 int reg_dest = true_regnum (dest);
1939 int reg_base = true_regnum (base);
1940 /* "volatile" forces reading low byte first, even if less efficient,
1941 for correct operation with 16-bit I/O registers. */
1942 int mem_volatile_p = MEM_VOLATILE_P (src);
1950 if (reg_dest == reg_base) /* R = (R) */
1953 return (AS2 (ld,__tmp_reg__,%1+) CR_TAB
1954 AS2 (ld,%B0,%1) CR_TAB
1955 AS2 (mov,%A0,__tmp_reg__));
1957 else if (reg_base == REG_X) /* (R26) */
1959 if (reg_unused_after (insn, base))
1962 return (AS2 (ld,%A0,X+) CR_TAB
1966 return (AS2 (ld,%A0,X+) CR_TAB
1967 AS2 (ld,%B0,X) CR_TAB
1973 return (AS2 (ld,%A0,%1) CR_TAB
1974 AS2 (ldd,%B0,%1+1));
1977 else if (GET_CODE (base) == PLUS) /* (R + i) */
1979 int disp = INTVAL (XEXP (base, 1));
1980 int reg_base = true_regnum (XEXP (base, 0));
1982 if (disp > MAX_LD_OFFSET (GET_MODE (src)))
1984 if (REGNO (XEXP (base, 0)) != REG_Y)
1985 fatal_insn ("incorrect insn:",insn);
1987 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
1988 return *l = 4, (AS2 (adiw,r28,%o1-62) CR_TAB
1989 AS2 (ldd,%A0,Y+62) CR_TAB
1990 AS2 (ldd,%B0,Y+63) CR_TAB
1991 AS2 (sbiw,r28,%o1-62));
1993 return *l = 6, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
1994 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
1995 AS2 (ld,%A0,Y) CR_TAB
1996 AS2 (ldd,%B0,Y+1) CR_TAB
1997 AS2 (subi,r28,lo8(%o1)) CR_TAB
1998 AS2 (sbci,r29,hi8(%o1)));
2000 if (reg_base == REG_X)
2002 /* This is a paranoid case. LEGITIMIZE_RELOAD_ADDRESS must exclude
2003 it but I have this situation with extremal
2004 optimization options. */
2007 if (reg_base == reg_dest)
2008 return (AS2 (adiw,r26,%o1) CR_TAB
2009 AS2 (ld,__tmp_reg__,X+) CR_TAB
2010 AS2 (ld,%B0,X) CR_TAB
2011 AS2 (mov,%A0,__tmp_reg__));
2013 return (AS2 (adiw,r26,%o1) CR_TAB
2014 AS2 (ld,%A0,X+) CR_TAB
2015 AS2 (ld,%B0,X) CR_TAB
2016 AS2 (sbiw,r26,%o1+1));
2019 if (reg_base == reg_dest)
2022 return (AS2 (ldd,__tmp_reg__,%A1) CR_TAB
2023 AS2 (ldd,%B0,%B1) CR_TAB
2024 AS2 (mov,%A0,__tmp_reg__));
2028 return (AS2 (ldd,%A0,%A1) CR_TAB
2031 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2033 if (reg_overlap_mentioned_p (dest, XEXP (base, 0)))
2034 fatal_insn ("incorrect insn:", insn);
2038 if (REGNO (XEXP (base, 0)) == REG_X)
2041 return (AS2 (sbiw,r26,2) CR_TAB
2042 AS2 (ld,%A0,X+) CR_TAB
2043 AS2 (ld,%B0,X) CR_TAB
2049 return (AS2 (sbiw,%r1,2) CR_TAB
2050 AS2 (ld,%A0,%p1) CR_TAB
2051 AS2 (ldd,%B0,%p1+1));
2056 return (AS2 (ld,%B0,%1) CR_TAB
2059 else if (GET_CODE (base) == POST_INC) /* (R++) */
2061 if (reg_overlap_mentioned_p (dest, XEXP (base, 0)))
2062 fatal_insn ("incorrect insn:", insn);
2065 return (AS2 (ld,%A0,%1) CR_TAB
2068 else if (CONSTANT_ADDRESS_P (base))
2070 if (optimize > 0 && io_address_operand (base, HImode))
2073 return (AS2 (in,%A0,%m1-0x20) CR_TAB
2074 AS2 (in,%B0,%m1+1-0x20));
2077 return (AS2 (lds,%A0,%m1) CR_TAB
2078 AS2 (lds,%B0,%m1+1));
2081 fatal_insn ("unknown move insn:",insn);
2086 out_movsi_r_mr (rtx insn, rtx op[], int *l)
2090 rtx base = XEXP (src, 0);
2091 int reg_dest = true_regnum (dest);
2092 int reg_base = true_regnum (base);
2100 if (reg_base == REG_X) /* (R26) */
2102 if (reg_dest == REG_X)
2103 /* "ld r26,-X" is undefined */
2104 return *l=7, (AS2 (adiw,r26,3) CR_TAB
2105 AS2 (ld,r29,X) CR_TAB
2106 AS2 (ld,r28,-X) CR_TAB
2107 AS2 (ld,__tmp_reg__,-X) CR_TAB
2108 AS2 (sbiw,r26,1) CR_TAB
2109 AS2 (ld,r26,X) CR_TAB
2110 AS2 (mov,r27,__tmp_reg__));
2111 else if (reg_dest == REG_X - 2)
2112 return *l=5, (AS2 (ld,%A0,X+) CR_TAB
2113 AS2 (ld,%B0,X+) CR_TAB
2114 AS2 (ld,__tmp_reg__,X+) CR_TAB
2115 AS2 (ld,%D0,X) CR_TAB
2116 AS2 (mov,%C0,__tmp_reg__));
2117 else if (reg_unused_after (insn, base))
2118 return *l=4, (AS2 (ld,%A0,X+) CR_TAB
2119 AS2 (ld,%B0,X+) CR_TAB
2120 AS2 (ld,%C0,X+) CR_TAB
2123 return *l=5, (AS2 (ld,%A0,X+) CR_TAB
2124 AS2 (ld,%B0,X+) CR_TAB
2125 AS2 (ld,%C0,X+) CR_TAB
2126 AS2 (ld,%D0,X) CR_TAB
2131 if (reg_dest == reg_base)
2132 return *l=5, (AS2 (ldd,%D0,%1+3) CR_TAB
2133 AS2 (ldd,%C0,%1+2) CR_TAB
2134 AS2 (ldd,__tmp_reg__,%1+1) CR_TAB
2135 AS2 (ld,%A0,%1) CR_TAB
2136 AS2 (mov,%B0,__tmp_reg__));
2137 else if (reg_base == reg_dest + 2)
2138 return *l=5, (AS2 (ld ,%A0,%1) CR_TAB
2139 AS2 (ldd,%B0,%1+1) CR_TAB
2140 AS2 (ldd,__tmp_reg__,%1+2) CR_TAB
2141 AS2 (ldd,%D0,%1+3) CR_TAB
2142 AS2 (mov,%C0,__tmp_reg__));
2144 return *l=4, (AS2 (ld ,%A0,%1) CR_TAB
2145 AS2 (ldd,%B0,%1+1) CR_TAB
2146 AS2 (ldd,%C0,%1+2) CR_TAB
2147 AS2 (ldd,%D0,%1+3));
2150 else if (GET_CODE (base) == PLUS) /* (R + i) */
2152 int disp = INTVAL (XEXP (base, 1));
2154 if (disp > MAX_LD_OFFSET (GET_MODE (src)))
2156 if (REGNO (XEXP (base, 0)) != REG_Y)
2157 fatal_insn ("incorrect insn:",insn);
2159 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
2160 return *l = 6, (AS2 (adiw,r28,%o1-60) CR_TAB
2161 AS2 (ldd,%A0,Y+60) CR_TAB
2162 AS2 (ldd,%B0,Y+61) CR_TAB
2163 AS2 (ldd,%C0,Y+62) CR_TAB
2164 AS2 (ldd,%D0,Y+63) CR_TAB
2165 AS2 (sbiw,r28,%o1-60));
2167 return *l = 8, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
2168 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
2169 AS2 (ld,%A0,Y) CR_TAB
2170 AS2 (ldd,%B0,Y+1) CR_TAB
2171 AS2 (ldd,%C0,Y+2) CR_TAB
2172 AS2 (ldd,%D0,Y+3) CR_TAB
2173 AS2 (subi,r28,lo8(%o1)) CR_TAB
2174 AS2 (sbci,r29,hi8(%o1)));
2177 reg_base = true_regnum (XEXP (base, 0));
2178 if (reg_base == REG_X)
2181 if (reg_dest == REG_X)
2184 /* "ld r26,-X" is undefined */
2185 return (AS2 (adiw,r26,%o1+3) CR_TAB
2186 AS2 (ld,r29,X) CR_TAB
2187 AS2 (ld,r28,-X) CR_TAB
2188 AS2 (ld,__tmp_reg__,-X) CR_TAB
2189 AS2 (sbiw,r26,1) CR_TAB
2190 AS2 (ld,r26,X) CR_TAB
2191 AS2 (mov,r27,__tmp_reg__));
2194 if (reg_dest == REG_X - 2)
2195 return (AS2 (adiw,r26,%o1) CR_TAB
2196 AS2 (ld,r24,X+) CR_TAB
2197 AS2 (ld,r25,X+) CR_TAB
2198 AS2 (ld,__tmp_reg__,X+) CR_TAB
2199 AS2 (ld,r27,X) CR_TAB
2200 AS2 (mov,r26,__tmp_reg__));
2202 return (AS2 (adiw,r26,%o1) CR_TAB
2203 AS2 (ld,%A0,X+) CR_TAB
2204 AS2 (ld,%B0,X+) CR_TAB
2205 AS2 (ld,%C0,X+) CR_TAB
2206 AS2 (ld,%D0,X) CR_TAB
2207 AS2 (sbiw,r26,%o1+3));
2209 if (reg_dest == reg_base)
2210 return *l=5, (AS2 (ldd,%D0,%D1) CR_TAB
2211 AS2 (ldd,%C0,%C1) CR_TAB
2212 AS2 (ldd,__tmp_reg__,%B1) CR_TAB
2213 AS2 (ldd,%A0,%A1) CR_TAB
2214 AS2 (mov,%B0,__tmp_reg__));
2215 else if (reg_dest == reg_base - 2)
2216 return *l=5, (AS2 (ldd,%A0,%A1) CR_TAB
2217 AS2 (ldd,%B0,%B1) CR_TAB
2218 AS2 (ldd,__tmp_reg__,%C1) CR_TAB
2219 AS2 (ldd,%D0,%D1) CR_TAB
2220 AS2 (mov,%C0,__tmp_reg__));
2221 return *l=4, (AS2 (ldd,%A0,%A1) CR_TAB
2222 AS2 (ldd,%B0,%B1) CR_TAB
2223 AS2 (ldd,%C0,%C1) CR_TAB
2226 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2227 return *l=4, (AS2 (ld,%D0,%1) CR_TAB
2228 AS2 (ld,%C0,%1) CR_TAB
2229 AS2 (ld,%B0,%1) CR_TAB
2231 else if (GET_CODE (base) == POST_INC) /* (R++) */
2232 return *l=4, (AS2 (ld,%A0,%1) CR_TAB
2233 AS2 (ld,%B0,%1) CR_TAB
2234 AS2 (ld,%C0,%1) CR_TAB
2236 else if (CONSTANT_ADDRESS_P (base))
2237 return *l=8, (AS2 (lds,%A0,%m1) CR_TAB
2238 AS2 (lds,%B0,%m1+1) CR_TAB
2239 AS2 (lds,%C0,%m1+2) CR_TAB
2240 AS2 (lds,%D0,%m1+3));
2242 fatal_insn ("unknown move insn:",insn);
2247 out_movsi_mr_r (rtx insn, rtx op[], int *l)
2251 rtx base = XEXP (dest, 0);
2252 int reg_base = true_regnum (base);
2253 int reg_src = true_regnum (src);
2259 if (CONSTANT_ADDRESS_P (base))
2260 return *l=8,(AS2 (sts,%m0,%A1) CR_TAB
2261 AS2 (sts,%m0+1,%B1) CR_TAB
2262 AS2 (sts,%m0+2,%C1) CR_TAB
2263 AS2 (sts,%m0+3,%D1));
2264 if (reg_base > 0) /* (r) */
2266 if (reg_base == REG_X) /* (R26) */
2268 if (reg_src == REG_X)
2270 /* "st X+,r26" is undefined */
2271 if (reg_unused_after (insn, base))
2272 return *l=6, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2273 AS2 (st,X,r26) CR_TAB
2274 AS2 (adiw,r26,1) CR_TAB
2275 AS2 (st,X+,__tmp_reg__) CR_TAB
2276 AS2 (st,X+,r28) CR_TAB
2279 return *l=7, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2280 AS2 (st,X,r26) CR_TAB
2281 AS2 (adiw,r26,1) CR_TAB
2282 AS2 (st,X+,__tmp_reg__) CR_TAB
2283 AS2 (st,X+,r28) CR_TAB
2284 AS2 (st,X,r29) CR_TAB
2287 else if (reg_base == reg_src + 2)
2289 if (reg_unused_after (insn, base))
2290 return *l=7, (AS2 (mov,__zero_reg__,%C1) CR_TAB
2291 AS2 (mov,__tmp_reg__,%D1) CR_TAB
2292 AS2 (st,%0+,%A1) CR_TAB
2293 AS2 (st,%0+,%B1) CR_TAB
2294 AS2 (st,%0+,__zero_reg__) CR_TAB
2295 AS2 (st,%0,__tmp_reg__) CR_TAB
2296 AS1 (clr,__zero_reg__));
2298 return *l=8, (AS2 (mov,__zero_reg__,%C1) CR_TAB
2299 AS2 (mov,__tmp_reg__,%D1) CR_TAB
2300 AS2 (st,%0+,%A1) CR_TAB
2301 AS2 (st,%0+,%B1) CR_TAB
2302 AS2 (st,%0+,__zero_reg__) CR_TAB
2303 AS2 (st,%0,__tmp_reg__) CR_TAB
2304 AS1 (clr,__zero_reg__) CR_TAB
2307 return *l=5, (AS2 (st,%0+,%A1) CR_TAB
2308 AS2 (st,%0+,%B1) CR_TAB
2309 AS2 (st,%0+,%C1) CR_TAB
2310 AS2 (st,%0,%D1) CR_TAB
2314 return *l=4, (AS2 (st,%0,%A1) CR_TAB
2315 AS2 (std,%0+1,%B1) CR_TAB
2316 AS2 (std,%0+2,%C1) CR_TAB
2317 AS2 (std,%0+3,%D1));
2319 else if (GET_CODE (base) == PLUS) /* (R + i) */
2321 int disp = INTVAL (XEXP (base, 1));
2322 reg_base = REGNO (XEXP (base, 0));
2323 if (disp > MAX_LD_OFFSET (GET_MODE (dest)))
2325 if (reg_base != REG_Y)
2326 fatal_insn ("incorrect insn:",insn);
2328 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2329 return *l = 6, (AS2 (adiw,r28,%o0-60) CR_TAB
2330 AS2 (std,Y+60,%A1) CR_TAB
2331 AS2 (std,Y+61,%B1) CR_TAB
2332 AS2 (std,Y+62,%C1) CR_TAB
2333 AS2 (std,Y+63,%D1) CR_TAB
2334 AS2 (sbiw,r28,%o0-60));
2336 return *l = 8, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2337 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2338 AS2 (st,Y,%A1) CR_TAB
2339 AS2 (std,Y+1,%B1) CR_TAB
2340 AS2 (std,Y+2,%C1) CR_TAB
2341 AS2 (std,Y+3,%D1) CR_TAB
2342 AS2 (subi,r28,lo8(%o0)) CR_TAB
2343 AS2 (sbci,r29,hi8(%o0)));
2345 if (reg_base == REG_X)
2348 if (reg_src == REG_X)
2351 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2352 AS2 (mov,__zero_reg__,r27) CR_TAB
2353 AS2 (adiw,r26,%o0) CR_TAB
2354 AS2 (st,X+,__tmp_reg__) CR_TAB
2355 AS2 (st,X+,__zero_reg__) CR_TAB
2356 AS2 (st,X+,r28) CR_TAB
2357 AS2 (st,X,r29) CR_TAB
2358 AS1 (clr,__zero_reg__) CR_TAB
2359 AS2 (sbiw,r26,%o0+3));
2361 else if (reg_src == REG_X - 2)
2364 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2365 AS2 (mov,__zero_reg__,r27) CR_TAB
2366 AS2 (adiw,r26,%o0) CR_TAB
2367 AS2 (st,X+,r24) CR_TAB
2368 AS2 (st,X+,r25) CR_TAB
2369 AS2 (st,X+,__tmp_reg__) CR_TAB
2370 AS2 (st,X,__zero_reg__) CR_TAB
2371 AS1 (clr,__zero_reg__) CR_TAB
2372 AS2 (sbiw,r26,%o0+3));
2375 return (AS2 (adiw,r26,%o0) CR_TAB
2376 AS2 (st,X+,%A1) CR_TAB
2377 AS2 (st,X+,%B1) CR_TAB
2378 AS2 (st,X+,%C1) CR_TAB
2379 AS2 (st,X,%D1) CR_TAB
2380 AS2 (sbiw,r26,%o0+3));
2382 return *l=4, (AS2 (std,%A0,%A1) CR_TAB
2383 AS2 (std,%B0,%B1) CR_TAB
2384 AS2 (std,%C0,%C1) CR_TAB
2387 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2388 return *l=4, (AS2 (st,%0,%D1) CR_TAB
2389 AS2 (st,%0,%C1) CR_TAB
2390 AS2 (st,%0,%B1) CR_TAB
2392 else if (GET_CODE (base) == POST_INC) /* (R++) */
2393 return *l=4, (AS2 (st,%0,%A1) CR_TAB
2394 AS2 (st,%0,%B1) CR_TAB
2395 AS2 (st,%0,%C1) CR_TAB
2397 fatal_insn ("unknown move insn:",insn);
2402 output_movsisf(rtx insn, rtx operands[], int *l)
2405 rtx dest = operands[0];
2406 rtx src = operands[1];
2412 if (register_operand (dest, VOIDmode))
2414 if (register_operand (src, VOIDmode)) /* mov r,r */
2416 if (true_regnum (dest) > true_regnum (src))
2421 return (AS2 (movw,%C0,%C1) CR_TAB
2422 AS2 (movw,%A0,%A1));
2425 return (AS2 (mov,%D0,%D1) CR_TAB
2426 AS2 (mov,%C0,%C1) CR_TAB
2427 AS2 (mov,%B0,%B1) CR_TAB
2435 return (AS2 (movw,%A0,%A1) CR_TAB
2436 AS2 (movw,%C0,%C1));
2439 return (AS2 (mov,%A0,%A1) CR_TAB
2440 AS2 (mov,%B0,%B1) CR_TAB
2441 AS2 (mov,%C0,%C1) CR_TAB
2445 else if (CONSTANT_P (src))
2447 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
2450 return (AS2 (ldi,%A0,lo8(%1)) CR_TAB
2451 AS2 (ldi,%B0,hi8(%1)) CR_TAB
2452 AS2 (ldi,%C0,hlo8(%1)) CR_TAB
2453 AS2 (ldi,%D0,hhi8(%1)));
2456 if (GET_CODE (src) == CONST_INT)
2458 const char *const clr_op0 =
2459 AVR_HAVE_MOVW ? (AS1 (clr,%A0) CR_TAB
2460 AS1 (clr,%B0) CR_TAB
2462 : (AS1 (clr,%A0) CR_TAB
2463 AS1 (clr,%B0) CR_TAB
2464 AS1 (clr,%C0) CR_TAB
2467 if (src == const0_rtx) /* mov r,L */
2469 *l = AVR_HAVE_MOVW ? 3 : 4;
2472 else if (src == const1_rtx)
2475 output_asm_insn (clr_op0, operands);
2476 *l = AVR_HAVE_MOVW ? 4 : 5;
2477 return AS1 (inc,%A0);
2479 else if (src == constm1_rtx)
2481 /* Immediate constants -1 to any register */
2485 return (AS1 (clr,%A0) CR_TAB
2486 AS1 (dec,%A0) CR_TAB
2487 AS2 (mov,%B0,%A0) CR_TAB
2488 AS2 (movw,%C0,%A0));
2491 return (AS1 (clr,%A0) CR_TAB
2492 AS1 (dec,%A0) CR_TAB
2493 AS2 (mov,%B0,%A0) CR_TAB
2494 AS2 (mov,%C0,%A0) CR_TAB
2499 int bit_nr = exact_log2 (INTVAL (src));
2503 *l = AVR_HAVE_MOVW ? 5 : 6;
2506 output_asm_insn (clr_op0, operands);
2507 output_asm_insn ("set", operands);
2510 avr_output_bld (operands, bit_nr);
2517 /* Last resort, better than loading from memory. */
2519 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
2520 AS2 (ldi,r31,lo8(%1)) CR_TAB
2521 AS2 (mov,%A0,r31) CR_TAB
2522 AS2 (ldi,r31,hi8(%1)) CR_TAB
2523 AS2 (mov,%B0,r31) CR_TAB
2524 AS2 (ldi,r31,hlo8(%1)) CR_TAB
2525 AS2 (mov,%C0,r31) CR_TAB
2526 AS2 (ldi,r31,hhi8(%1)) CR_TAB
2527 AS2 (mov,%D0,r31) CR_TAB
2528 AS2 (mov,r31,__tmp_reg__));
2530 else if (GET_CODE (src) == MEM)
2531 return out_movsi_r_mr (insn, operands, real_l); /* mov r,m */
2533 else if (GET_CODE (dest) == MEM)
2537 if (src == const0_rtx)
2538 operands[1] = zero_reg_rtx;
2540 templ = out_movsi_mr_r (insn, operands, real_l);
2543 output_asm_insn (templ, operands);
2548 fatal_insn ("invalid insn:", insn);
2553 out_movqi_mr_r (rtx insn, rtx op[], int *l)
2557 rtx x = XEXP (dest, 0);
2563 if (CONSTANT_ADDRESS_P (x))
2565 if (CONST_INT_P (x) && INTVAL (x) == SREG_ADDR)
2568 return AS2 (out,__SREG__,%1);
2570 if (optimize > 0 && io_address_operand (x, QImode))
2573 return AS2 (out,%m0-0x20,%1);
2576 return AS2 (sts,%m0,%1);
2578 /* memory access by reg+disp */
2579 else if (GET_CODE (x) == PLUS
2580 && REG_P (XEXP (x,0))
2581 && GET_CODE (XEXP (x,1)) == CONST_INT)
2583 if ((INTVAL (XEXP (x,1)) - GET_MODE_SIZE (GET_MODE (dest))) >= 63)
2585 int disp = INTVAL (XEXP (x,1));
2586 if (REGNO (XEXP (x,0)) != REG_Y)
2587 fatal_insn ("incorrect insn:",insn);
2589 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2590 return *l = 3, (AS2 (adiw,r28,%o0-63) CR_TAB
2591 AS2 (std,Y+63,%1) CR_TAB
2592 AS2 (sbiw,r28,%o0-63));
2594 return *l = 5, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2595 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2596 AS2 (st,Y,%1) CR_TAB
2597 AS2 (subi,r28,lo8(%o0)) CR_TAB
2598 AS2 (sbci,r29,hi8(%o0)));
2600 else if (REGNO (XEXP (x,0)) == REG_X)
2602 if (reg_overlap_mentioned_p (src, XEXP (x, 0)))
2604 if (reg_unused_after (insn, XEXP (x,0)))
2605 return *l = 3, (AS2 (mov,__tmp_reg__,%1) CR_TAB
2606 AS2 (adiw,r26,%o0) CR_TAB
2607 AS2 (st,X,__tmp_reg__));
2609 return *l = 4, (AS2 (mov,__tmp_reg__,%1) CR_TAB
2610 AS2 (adiw,r26,%o0) CR_TAB
2611 AS2 (st,X,__tmp_reg__) CR_TAB
2612 AS2 (sbiw,r26,%o0));
2616 if (reg_unused_after (insn, XEXP (x,0)))
2617 return *l = 2, (AS2 (adiw,r26,%o0) CR_TAB
2620 return *l = 3, (AS2 (adiw,r26,%o0) CR_TAB
2621 AS2 (st,X,%1) CR_TAB
2622 AS2 (sbiw,r26,%o0));
2626 return AS2 (std,%0,%1);
2629 return AS2 (st,%0,%1);
2633 out_movhi_mr_r (rtx insn, rtx op[], int *l)
2637 rtx base = XEXP (dest, 0);
2638 int reg_base = true_regnum (base);
2639 int reg_src = true_regnum (src);
2640 /* "volatile" forces writing high byte first, even if less efficient,
2641 for correct operation with 16-bit I/O registers. */
2642 int mem_volatile_p = MEM_VOLATILE_P (dest);
2647 if (CONSTANT_ADDRESS_P (base))
2649 if (optimize > 0 && io_address_operand (base, HImode))
2652 return (AS2 (out,%m0+1-0x20,%B1) CR_TAB
2653 AS2 (out,%m0-0x20,%A1));
2655 return *l = 4, (AS2 (sts,%m0+1,%B1) CR_TAB
2660 if (reg_base == REG_X)
2662 if (reg_src == REG_X)
2664 /* "st X+,r26" and "st -X,r26" are undefined. */
2665 if (!mem_volatile_p && reg_unused_after (insn, src))
2666 return *l=4, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2667 AS2 (st,X,r26) CR_TAB
2668 AS2 (adiw,r26,1) CR_TAB
2669 AS2 (st,X,__tmp_reg__));
2671 return *l=5, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2672 AS2 (adiw,r26,1) CR_TAB
2673 AS2 (st,X,__tmp_reg__) CR_TAB
2674 AS2 (sbiw,r26,1) CR_TAB
2679 if (!mem_volatile_p && reg_unused_after (insn, base))
2680 return *l=2, (AS2 (st,X+,%A1) CR_TAB
2683 return *l=3, (AS2 (adiw,r26,1) CR_TAB
2684 AS2 (st,X,%B1) CR_TAB
2689 return *l=2, (AS2 (std,%0+1,%B1) CR_TAB
2692 else if (GET_CODE (base) == PLUS)
2694 int disp = INTVAL (XEXP (base, 1));
2695 reg_base = REGNO (XEXP (base, 0));
2696 if (disp > MAX_LD_OFFSET (GET_MODE (dest)))
2698 if (reg_base != REG_Y)
2699 fatal_insn ("incorrect insn:",insn);
2701 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2702 return *l = 4, (AS2 (adiw,r28,%o0-62) CR_TAB
2703 AS2 (std,Y+63,%B1) CR_TAB
2704 AS2 (std,Y+62,%A1) CR_TAB
2705 AS2 (sbiw,r28,%o0-62));
2707 return *l = 6, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2708 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2709 AS2 (std,Y+1,%B1) CR_TAB
2710 AS2 (st,Y,%A1) CR_TAB
2711 AS2 (subi,r28,lo8(%o0)) CR_TAB
2712 AS2 (sbci,r29,hi8(%o0)));
2714 if (reg_base == REG_X)
2717 if (reg_src == REG_X)
2720 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2721 AS2 (mov,__zero_reg__,r27) CR_TAB
2722 AS2 (adiw,r26,%o0+1) CR_TAB
2723 AS2 (st,X,__zero_reg__) CR_TAB
2724 AS2 (st,-X,__tmp_reg__) CR_TAB
2725 AS1 (clr,__zero_reg__) CR_TAB
2726 AS2 (sbiw,r26,%o0));
2729 return (AS2 (adiw,r26,%o0+1) CR_TAB
2730 AS2 (st,X,%B1) CR_TAB
2731 AS2 (st,-X,%A1) CR_TAB
2732 AS2 (sbiw,r26,%o0));
2734 return *l=2, (AS2 (std,%B0,%B1) CR_TAB
2737 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2738 return *l=2, (AS2 (st,%0,%B1) CR_TAB
2740 else if (GET_CODE (base) == POST_INC) /* (R++) */
2744 if (REGNO (XEXP (base, 0)) == REG_X)
2747 return (AS2 (adiw,r26,1) CR_TAB
2748 AS2 (st,X,%B1) CR_TAB
2749 AS2 (st,-X,%A1) CR_TAB
2755 return (AS2 (std,%p0+1,%B1) CR_TAB
2756 AS2 (st,%p0,%A1) CR_TAB
2762 return (AS2 (st,%0,%A1) CR_TAB
2765 fatal_insn ("unknown move insn:",insn);
2769 /* Return 1 if frame pointer for current function required. */
2772 avr_frame_pointer_required_p (void)
2774 return (cfun->calls_alloca
2775 || crtl->args.info.nregs == 0
2776 || get_frame_size () > 0);
2779 /* Returns the condition of compare insn INSN, or UNKNOWN. */
2782 compare_condition (rtx insn)
2784 rtx next = next_real_insn (insn);
2785 RTX_CODE cond = UNKNOWN;
2786 if (next && GET_CODE (next) == JUMP_INSN)
2788 rtx pat = PATTERN (next);
2789 rtx src = SET_SRC (pat);
2790 rtx t = XEXP (src, 0);
2791 cond = GET_CODE (t);
2796 /* Returns nonzero if INSN is a tst insn that only tests the sign. */
2799 compare_sign_p (rtx insn)
2801 RTX_CODE cond = compare_condition (insn);
2802 return (cond == GE || cond == LT);
2805 /* Returns nonzero if the next insn is a JUMP_INSN with a condition
2806 that needs to be swapped (GT, GTU, LE, LEU). */
2809 compare_diff_p (rtx insn)
2811 RTX_CODE cond = compare_condition (insn);
2812 return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0;
2815 /* Returns nonzero if INSN is a compare insn with the EQ or NE condition. */
2818 compare_eq_p (rtx insn)
2820 RTX_CODE cond = compare_condition (insn);
2821 return (cond == EQ || cond == NE);
2825 /* Output test instruction for HImode. */
2828 out_tsthi (rtx insn, rtx op, int *l)
2830 if (compare_sign_p (insn))
2833 return AS1 (tst,%B0);
2835 if (reg_unused_after (insn, op)
2836 && compare_eq_p (insn))
2838 /* Faster than sbiw if we can clobber the operand. */
2840 return "or %A0,%B0";
2842 if (test_hard_reg_class (ADDW_REGS, op))
2845 return AS2 (sbiw,%0,0);
2848 return (AS2 (cp,%A0,__zero_reg__) CR_TAB
2849 AS2 (cpc,%B0,__zero_reg__));
2853 /* Output test instruction for SImode. */
2856 out_tstsi (rtx insn, rtx op, int *l)
2858 if (compare_sign_p (insn))
2861 return AS1 (tst,%D0);
2863 if (test_hard_reg_class (ADDW_REGS, op))
2866 return (AS2 (sbiw,%A0,0) CR_TAB
2867 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2868 AS2 (cpc,%D0,__zero_reg__));
2871 return (AS2 (cp,%A0,__zero_reg__) CR_TAB
2872 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2873 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2874 AS2 (cpc,%D0,__zero_reg__));
2878 /* Generate asm equivalent for various shifts.
2879 Shift count is a CONST_INT, MEM or REG.
2880 This only handles cases that are not already
2881 carefully hand-optimized in ?sh??i3_out. */
2884 out_shift_with_cnt (const char *templ, rtx insn, rtx operands[],
2885 int *len, int t_len)
2889 int second_label = 1;
2890 int saved_in_tmp = 0;
2891 int use_zero_reg = 0;
2893 op[0] = operands[0];
2894 op[1] = operands[1];
2895 op[2] = operands[2];
2896 op[3] = operands[3];
2902 if (GET_CODE (operands[2]) == CONST_INT)
2904 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
2905 int count = INTVAL (operands[2]);
2906 int max_len = 10; /* If larger than this, always use a loop. */
2915 if (count < 8 && !scratch)
2919 max_len = t_len + (scratch ? 3 : (use_zero_reg ? 4 : 5));
2921 if (t_len * count <= max_len)
2923 /* Output shifts inline with no loop - faster. */
2925 *len = t_len * count;
2929 output_asm_insn (templ, op);
2938 strcat (str, AS2 (ldi,%3,%2));
2940 else if (use_zero_reg)
2942 /* Hack to save one word: use __zero_reg__ as loop counter.
2943 Set one bit, then shift in a loop until it is 0 again. */
2945 op[3] = zero_reg_rtx;
2949 strcat (str, ("set" CR_TAB
2950 AS2 (bld,%3,%2-1)));
2954 /* No scratch register available, use one from LD_REGS (saved in
2955 __tmp_reg__) that doesn't overlap with registers to shift. */
2957 op[3] = gen_rtx_REG (QImode,
2958 ((true_regnum (operands[0]) - 1) & 15) + 16);
2959 op[4] = tmp_reg_rtx;
2963 *len = 3; /* Includes "mov %3,%4" after the loop. */
2965 strcat (str, (AS2 (mov,%4,%3) CR_TAB
2971 else if (GET_CODE (operands[2]) == MEM)
2975 op[3] = op_mov[0] = tmp_reg_rtx;
2979 out_movqi_r_mr (insn, op_mov, len);
2981 output_asm_insn (out_movqi_r_mr (insn, op_mov, NULL), op_mov);
2983 else if (register_operand (operands[2], QImode))
2985 if (reg_unused_after (insn, operands[2]))
2989 op[3] = tmp_reg_rtx;
2991 strcat (str, (AS2 (mov,%3,%2) CR_TAB));
2995 fatal_insn ("bad shift insn:", insn);
3002 strcat (str, AS1 (rjmp,2f));
3006 *len += t_len + 2; /* template + dec + brXX */
3009 strcat (str, "\n1:\t");
3010 strcat (str, templ);
3011 strcat (str, second_label ? "\n2:\t" : "\n\t");
3012 strcat (str, use_zero_reg ? AS1 (lsr,%3) : AS1 (dec,%3));
3013 strcat (str, CR_TAB);
3014 strcat (str, second_label ? AS1 (brpl,1b) : AS1 (brne,1b));
3016 strcat (str, (CR_TAB AS2 (mov,%3,%4)));
3017 output_asm_insn (str, op);
3022 /* 8bit shift left ((char)x << i) */
3025 ashlqi3_out (rtx insn, rtx operands[], int *len)
3027 if (GET_CODE (operands[2]) == CONST_INT)
3034 switch (INTVAL (operands[2]))
3037 if (INTVAL (operands[2]) < 8)
3041 return AS1 (clr,%0);
3045 return AS1 (lsl,%0);
3049 return (AS1 (lsl,%0) CR_TAB
3054 return (AS1 (lsl,%0) CR_TAB
3059 if (test_hard_reg_class (LD_REGS, operands[0]))
3062 return (AS1 (swap,%0) CR_TAB
3063 AS2 (andi,%0,0xf0));
3066 return (AS1 (lsl,%0) CR_TAB
3072 if (test_hard_reg_class (LD_REGS, operands[0]))
3075 return (AS1 (swap,%0) CR_TAB
3077 AS2 (andi,%0,0xe0));
3080 return (AS1 (lsl,%0) CR_TAB
3087 if (test_hard_reg_class (LD_REGS, operands[0]))
3090 return (AS1 (swap,%0) CR_TAB
3093 AS2 (andi,%0,0xc0));
3096 return (AS1 (lsl,%0) CR_TAB
3105 return (AS1 (ror,%0) CR_TAB
3110 else if (CONSTANT_P (operands[2]))
3111 fatal_insn ("internal compiler error. Incorrect shift:", insn);
3113 out_shift_with_cnt (AS1 (lsl,%0),
3114 insn, operands, len, 1);
3119 /* 16bit shift left ((short)x << i) */
3122 ashlhi3_out (rtx insn, rtx operands[], int *len)
3124 if (GET_CODE (operands[2]) == CONST_INT)
3126 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
3127 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
3134 switch (INTVAL (operands[2]))
3137 if (INTVAL (operands[2]) < 16)
3141 return (AS1 (clr,%B0) CR_TAB
3145 if (optimize_size && scratch)
3150 return (AS1 (swap,%A0) CR_TAB
3151 AS1 (swap,%B0) CR_TAB
3152 AS2 (andi,%B0,0xf0) CR_TAB
3153 AS2 (eor,%B0,%A0) CR_TAB
3154 AS2 (andi,%A0,0xf0) CR_TAB
3160 return (AS1 (swap,%A0) CR_TAB
3161 AS1 (swap,%B0) CR_TAB
3162 AS2 (ldi,%3,0xf0) CR_TAB
3164 AS2 (eor,%B0,%A0) CR_TAB
3168 break; /* optimize_size ? 6 : 8 */
3172 break; /* scratch ? 5 : 6 */
3176 return (AS1 (lsl,%A0) CR_TAB
3177 AS1 (rol,%B0) CR_TAB
3178 AS1 (swap,%A0) CR_TAB
3179 AS1 (swap,%B0) CR_TAB
3180 AS2 (andi,%B0,0xf0) CR_TAB
3181 AS2 (eor,%B0,%A0) CR_TAB
3182 AS2 (andi,%A0,0xf0) CR_TAB
3188 return (AS1 (lsl,%A0) CR_TAB
3189 AS1 (rol,%B0) CR_TAB
3190 AS1 (swap,%A0) CR_TAB
3191 AS1 (swap,%B0) CR_TAB
3192 AS2 (ldi,%3,0xf0) CR_TAB
3194 AS2 (eor,%B0,%A0) CR_TAB
3202 break; /* scratch ? 5 : 6 */
3204 return (AS1 (clr,__tmp_reg__) CR_TAB
3205 AS1 (lsr,%B0) CR_TAB
3206 AS1 (ror,%A0) CR_TAB
3207 AS1 (ror,__tmp_reg__) CR_TAB
3208 AS1 (lsr,%B0) CR_TAB
3209 AS1 (ror,%A0) CR_TAB
3210 AS1 (ror,__tmp_reg__) CR_TAB
3211 AS2 (mov,%B0,%A0) CR_TAB
3212 AS2 (mov,%A0,__tmp_reg__));
3216 return (AS1 (lsr,%B0) CR_TAB
3217 AS2 (mov,%B0,%A0) CR_TAB
3218 AS1 (clr,%A0) CR_TAB
3219 AS1 (ror,%B0) CR_TAB
3223 return *len = 2, (AS2 (mov,%B0,%A1) CR_TAB
3228 return (AS2 (mov,%B0,%A0) CR_TAB
3229 AS1 (clr,%A0) CR_TAB
3234 return (AS2 (mov,%B0,%A0) CR_TAB
3235 AS1 (clr,%A0) CR_TAB
3236 AS1 (lsl,%B0) CR_TAB
3241 return (AS2 (mov,%B0,%A0) CR_TAB
3242 AS1 (clr,%A0) CR_TAB
3243 AS1 (lsl,%B0) CR_TAB
3244 AS1 (lsl,%B0) CR_TAB
3251 return (AS2 (mov,%B0,%A0) CR_TAB
3252 AS1 (clr,%A0) CR_TAB
3253 AS1 (swap,%B0) CR_TAB
3254 AS2 (andi,%B0,0xf0));
3259 return (AS2 (mov,%B0,%A0) CR_TAB
3260 AS1 (clr,%A0) CR_TAB
3261 AS1 (swap,%B0) CR_TAB
3262 AS2 (ldi,%3,0xf0) CR_TAB
3266 return (AS2 (mov,%B0,%A0) CR_TAB
3267 AS1 (clr,%A0) CR_TAB
3268 AS1 (lsl,%B0) CR_TAB
3269 AS1 (lsl,%B0) CR_TAB
3270 AS1 (lsl,%B0) CR_TAB
3277 return (AS2 (mov,%B0,%A0) CR_TAB
3278 AS1 (clr,%A0) CR_TAB
3279 AS1 (swap,%B0) CR_TAB
3280 AS1 (lsl,%B0) CR_TAB
3281 AS2 (andi,%B0,0xe0));
3283 if (AVR_HAVE_MUL && scratch)
3286 return (AS2 (ldi,%3,0x20) CR_TAB
3287 AS2 (mul,%A0,%3) CR_TAB
3288 AS2 (mov,%B0,r0) CR_TAB
3289 AS1 (clr,%A0) CR_TAB
3290 AS1 (clr,__zero_reg__));
3292 if (optimize_size && scratch)
3297 return (AS2 (mov,%B0,%A0) CR_TAB
3298 AS1 (clr,%A0) CR_TAB
3299 AS1 (swap,%B0) CR_TAB
3300 AS1 (lsl,%B0) CR_TAB
3301 AS2 (ldi,%3,0xe0) CR_TAB
3307 return ("set" CR_TAB
3308 AS2 (bld,r1,5) CR_TAB
3309 AS2 (mul,%A0,r1) CR_TAB
3310 AS2 (mov,%B0,r0) CR_TAB
3311 AS1 (clr,%A0) CR_TAB
3312 AS1 (clr,__zero_reg__));
3315 return (AS2 (mov,%B0,%A0) CR_TAB
3316 AS1 (clr,%A0) CR_TAB
3317 AS1 (lsl,%B0) CR_TAB
3318 AS1 (lsl,%B0) CR_TAB
3319 AS1 (lsl,%B0) CR_TAB
3320 AS1 (lsl,%B0) CR_TAB
3324 if (AVR_HAVE_MUL && ldi_ok)
3327 return (AS2 (ldi,%B0,0x40) CR_TAB
3328 AS2 (mul,%A0,%B0) CR_TAB
3329 AS2 (mov,%B0,r0) CR_TAB
3330 AS1 (clr,%A0) CR_TAB
3331 AS1 (clr,__zero_reg__));
3333 if (AVR_HAVE_MUL && scratch)
3336 return (AS2 (ldi,%3,0x40) CR_TAB
3337 AS2 (mul,%A0,%3) CR_TAB
3338 AS2 (mov,%B0,r0) CR_TAB
3339 AS1 (clr,%A0) CR_TAB
3340 AS1 (clr,__zero_reg__));
3342 if (optimize_size && ldi_ok)
3345 return (AS2 (mov,%B0,%A0) CR_TAB
3346 AS2 (ldi,%A0,6) "\n1:\t"
3347 AS1 (lsl,%B0) CR_TAB
3348 AS1 (dec,%A0) CR_TAB
3351 if (optimize_size && scratch)
3354 return (AS1 (clr,%B0) CR_TAB
3355 AS1 (lsr,%A0) CR_TAB
3356 AS1 (ror,%B0) CR_TAB
3357 AS1 (lsr,%A0) CR_TAB
3358 AS1 (ror,%B0) CR_TAB
3363 return (AS1 (clr,%B0) CR_TAB
3364 AS1 (lsr,%A0) CR_TAB
3365 AS1 (ror,%B0) CR_TAB
3370 out_shift_with_cnt ((AS1 (lsl,%A0) CR_TAB
3372 insn, operands, len, 2);
3377 /* 32bit shift left ((long)x << i) */
3380 ashlsi3_out (rtx insn, rtx operands[], int *len)
3382 if (GET_CODE (operands[2]) == CONST_INT)
3390 switch (INTVAL (operands[2]))
3393 if (INTVAL (operands[2]) < 32)
3397 return *len = 3, (AS1 (clr,%D0) CR_TAB
3398 AS1 (clr,%C0) CR_TAB
3399 AS2 (movw,%A0,%C0));
3401 return (AS1 (clr,%D0) CR_TAB
3402 AS1 (clr,%C0) CR_TAB
3403 AS1 (clr,%B0) CR_TAB
3408 int reg0 = true_regnum (operands[0]);
3409 int reg1 = true_regnum (operands[1]);
3412 return (AS2 (mov,%D0,%C1) CR_TAB
3413 AS2 (mov,%C0,%B1) CR_TAB
3414 AS2 (mov,%B0,%A1) CR_TAB
3417 return (AS1 (clr,%A0) CR_TAB
3418 AS2 (mov,%B0,%A1) CR_TAB
3419 AS2 (mov,%C0,%B1) CR_TAB
3425 int reg0 = true_regnum (operands[0]);
3426 int reg1 = true_regnum (operands[1]);
3427 if (reg0 + 2 == reg1)
3428 return *len = 2, (AS1 (clr,%B0) CR_TAB
3431 return *len = 3, (AS2 (movw,%C0,%A1) CR_TAB
3432 AS1 (clr,%B0) CR_TAB
3435 return *len = 4, (AS2 (mov,%C0,%A1) CR_TAB
3436 AS2 (mov,%D0,%B1) CR_TAB
3437 AS1 (clr,%B0) CR_TAB
3443 return (AS2 (mov,%D0,%A1) CR_TAB
3444 AS1 (clr,%C0) CR_TAB
3445 AS1 (clr,%B0) CR_TAB
3450 return (AS1 (clr,%D0) CR_TAB
3451 AS1 (lsr,%A0) CR_TAB
3452 AS1 (ror,%D0) CR_TAB
3453 AS1 (clr,%C0) CR_TAB
3454 AS1 (clr,%B0) CR_TAB
3459 out_shift_with_cnt ((AS1 (lsl,%A0) CR_TAB
3460 AS1 (rol,%B0) CR_TAB
3461 AS1 (rol,%C0) CR_TAB
3463 insn, operands, len, 4);
3467 /* 8bit arithmetic shift right ((signed char)x >> i) */
3470 ashrqi3_out (rtx insn, rtx operands[], int *len)
3472 if (GET_CODE (operands[2]) == CONST_INT)
3479 switch (INTVAL (operands[2]))
3483 return AS1 (asr,%0);
3487 return (AS1 (asr,%0) CR_TAB
3492 return (AS1 (asr,%0) CR_TAB
3498 return (AS1 (asr,%0) CR_TAB
3505 return (AS1 (asr,%0) CR_TAB
3513 return (AS2 (bst,%0,6) CR_TAB
3515 AS2 (sbc,%0,%0) CR_TAB
3519 if (INTVAL (operands[2]) < 8)
3526 return (AS1 (lsl,%0) CR_TAB
3530 else if (CONSTANT_P (operands[2]))
3531 fatal_insn ("internal compiler error. Incorrect shift:", insn);
3533 out_shift_with_cnt (AS1 (asr,%0),
3534 insn, operands, len, 1);
3539 /* 16bit arithmetic shift right ((signed short)x >> i) */
3542 ashrhi3_out (rtx insn, rtx operands[], int *len)
3544 if (GET_CODE (operands[2]) == CONST_INT)
3546 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
3547 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
3554 switch (INTVAL (operands[2]))
3558 /* XXX try to optimize this too? */
3563 break; /* scratch ? 5 : 6 */
3565 return (AS2 (mov,__tmp_reg__,%A0) CR_TAB
3566 AS2 (mov,%A0,%B0) CR_TAB
3567 AS1 (lsl,__tmp_reg__) CR_TAB
3568 AS1 (rol,%A0) CR_TAB
3569 AS2 (sbc,%B0,%B0) CR_TAB
3570 AS1 (lsl,__tmp_reg__) CR_TAB
3571 AS1 (rol,%A0) CR_TAB
3576 return (AS1 (lsl,%A0) CR_TAB
3577 AS2 (mov,%A0,%B0) CR_TAB
3578 AS1 (rol,%A0) CR_TAB
3583 int reg0 = true_regnum (operands[0]);
3584 int reg1 = true_regnum (operands[1]);
3587 return *len = 3, (AS2 (mov,%A0,%B0) CR_TAB
3588 AS1 (lsl,%B0) CR_TAB
3591 return *len = 4, (AS2 (mov,%A0,%B1) CR_TAB
3592 AS1 (clr,%B0) CR_TAB
3593 AS2 (sbrc,%A0,7) CR_TAB
3599 return (AS2 (mov,%A0,%B0) CR_TAB
3600 AS1 (lsl,%B0) CR_TAB
3601 AS2 (sbc,%B0,%B0) CR_TAB
3606 return (AS2 (mov,%A0,%B0) CR_TAB
3607 AS1 (lsl,%B0) CR_TAB
3608 AS2 (sbc,%B0,%B0) CR_TAB
3609 AS1 (asr,%A0) CR_TAB
3613 if (AVR_HAVE_MUL && ldi_ok)
3616 return (AS2 (ldi,%A0,0x20) CR_TAB
3617 AS2 (muls,%B0,%A0) CR_TAB
3618 AS2 (mov,%A0,r1) CR_TAB
3619 AS2 (sbc,%B0,%B0) CR_TAB
3620 AS1 (clr,__zero_reg__));
3622 if (optimize_size && scratch)
3625 return (AS2 (mov,%A0,%B0) CR_TAB
3626 AS1 (lsl,%B0) CR_TAB
3627 AS2 (sbc,%B0,%B0) CR_TAB
3628 AS1 (asr,%A0) CR_TAB
3629 AS1 (asr,%A0) CR_TAB
3633 if (AVR_HAVE_MUL && ldi_ok)
3636 return (AS2 (ldi,%A0,0x10) CR_TAB
3637 AS2 (muls,%B0,%A0) CR_TAB
3638 AS2 (mov,%A0,r1) CR_TAB
3639 AS2 (sbc,%B0,%B0) CR_TAB
3640 AS1 (clr,__zero_reg__));
3642 if (optimize_size && scratch)
3645 return (AS2 (mov,%A0,%B0) CR_TAB
3646 AS1 (lsl,%B0) CR_TAB
3647 AS2 (sbc,%B0,%B0) CR_TAB
3648 AS1 (asr,%A0) CR_TAB
3649 AS1 (asr,%A0) CR_TAB
3650 AS1 (asr,%A0) CR_TAB
3654 if (AVR_HAVE_MUL && ldi_ok)
3657 return (AS2 (ldi,%A0,0x08) CR_TAB
3658 AS2 (muls,%B0,%A0) CR_TAB
3659 AS2 (mov,%A0,r1) CR_TAB
3660 AS2 (sbc,%B0,%B0) CR_TAB
3661 AS1 (clr,__zero_reg__));
3664 break; /* scratch ? 5 : 7 */
3666 return (AS2 (mov,%A0,%B0) CR_TAB
3667 AS1 (lsl,%B0) CR_TAB
3668 AS2 (sbc,%B0,%B0) CR_TAB
3669 AS1 (asr,%A0) CR_TAB
3670 AS1 (asr,%A0) CR_TAB
3671 AS1 (asr,%A0) CR_TAB
3672 AS1 (asr,%A0) CR_TAB
3677 return (AS1 (lsl,%B0) CR_TAB
3678 AS2 (sbc,%A0,%A0) CR_TAB
3679 AS1 (lsl,%B0) CR_TAB
3680 AS2 (mov,%B0,%A0) CR_TAB
3684 if (INTVAL (operands[2]) < 16)
3690 return *len = 3, (AS1 (lsl,%B0) CR_TAB
3691 AS2 (sbc,%A0,%A0) CR_TAB
3696 out_shift_with_cnt ((AS1 (asr,%B0) CR_TAB
3698 insn, operands, len, 2);
3703 /* 32bit arithmetic shift right ((signed long)x >> i) */
3706 ashrsi3_out (rtx insn, rtx operands[], int *len)
3708 if (GET_CODE (operands[2]) == CONST_INT)
3716 switch (INTVAL (operands[2]))
3720 int reg0 = true_regnum (operands[0]);
3721 int reg1 = true_regnum (operands[1]);
3724 return (AS2 (mov,%A0,%B1) CR_TAB
3725 AS2 (mov,%B0,%C1) CR_TAB
3726 AS2 (mov,%C0,%D1) CR_TAB
3727 AS1 (clr,%D0) CR_TAB
3728 AS2 (sbrc,%C0,7) CR_TAB
3731 return (AS1 (clr,%D0) CR_TAB
3732 AS2 (sbrc,%D1,7) CR_TAB
3733 AS1 (dec,%D0) CR_TAB
3734 AS2 (mov,%C0,%D1) CR_TAB
3735 AS2 (mov,%B0,%C1) CR_TAB
3741 int reg0 = true_regnum (operands[0]);
3742 int reg1 = true_regnum (operands[1]);
3744 if (reg0 == reg1 + 2)
3745 return *len = 4, (AS1 (clr,%D0) CR_TAB
3746 AS2 (sbrc,%B0,7) CR_TAB
3747 AS1 (com,%D0) CR_TAB
3750 return *len = 5, (AS2 (movw,%A0,%C1) CR_TAB
3751 AS1 (clr,%D0) CR_TAB
3752 AS2 (sbrc,%B0,7) CR_TAB
3753 AS1 (com,%D0) CR_TAB
3756 return *len = 6, (AS2 (mov,%B0,%D1) CR_TAB
3757 AS2 (mov,%A0,%C1) CR_TAB
3758 AS1 (clr,%D0) CR_TAB
3759 AS2 (sbrc,%B0,7) CR_TAB
3760 AS1 (com,%D0) CR_TAB
3765 return *len = 6, (AS2 (mov,%A0,%D1) CR_TAB
3766 AS1 (clr,%D0) CR_TAB
3767 AS2 (sbrc,%A0,7) CR_TAB
3768 AS1 (com,%D0) CR_TAB
3769 AS2 (mov,%B0,%D0) CR_TAB
3773 if (INTVAL (operands[2]) < 32)
3780 return *len = 4, (AS1 (lsl,%D0) CR_TAB
3781 AS2 (sbc,%A0,%A0) CR_TAB
3782 AS2 (mov,%B0,%A0) CR_TAB
3783 AS2 (movw,%C0,%A0));
3785 return *len = 5, (AS1 (lsl,%D0) CR_TAB
3786 AS2 (sbc,%A0,%A0) CR_TAB
3787 AS2 (mov,%B0,%A0) CR_TAB
3788 AS2 (mov,%C0,%A0) CR_TAB
3793 out_shift_with_cnt ((AS1 (asr,%D0) CR_TAB
3794 AS1 (ror,%C0) CR_TAB
3795 AS1 (ror,%B0) CR_TAB
3797 insn, operands, len, 4);
3801 /* 8bit logic shift right ((unsigned char)x >> i) */
3804 lshrqi3_out (rtx insn, rtx operands[], int *len)
3806 if (GET_CODE (operands[2]) == CONST_INT)
3813 switch (INTVAL (operands[2]))
3816 if (INTVAL (operands[2]) < 8)
3820 return AS1 (clr,%0);
3824 return AS1 (lsr,%0);
3828 return (AS1 (lsr,%0) CR_TAB
3832 return (AS1 (lsr,%0) CR_TAB
3837 if (test_hard_reg_class (LD_REGS, operands[0]))
3840 return (AS1 (swap,%0) CR_TAB
3841 AS2 (andi,%0,0x0f));
3844 return (AS1 (lsr,%0) CR_TAB
3850 if (test_hard_reg_class (LD_REGS, operands[0]))
3853 return (AS1 (swap,%0) CR_TAB
3858 return (AS1 (lsr,%0) CR_TAB
3865 if (test_hard_reg_class (LD_REGS, operands[0]))
3868 return (AS1 (swap,%0) CR_TAB
3874 return (AS1 (lsr,%0) CR_TAB
3883 return (AS1 (rol,%0) CR_TAB
3888 else if (CONSTANT_P (operands[2]))
3889 fatal_insn ("internal compiler error. Incorrect shift:", insn);
3891 out_shift_with_cnt (AS1 (lsr,%0),
3892 insn, operands, len, 1);
3896 /* 16bit logic shift right ((unsigned short)x >> i) */
3899 lshrhi3_out (rtx insn, rtx operands[], int *len)
3901 if (GET_CODE (operands[2]) == CONST_INT)
3903 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
3904 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
3911 switch (INTVAL (operands[2]))
3914 if (INTVAL (operands[2]) < 16)
3918 return (AS1 (clr,%B0) CR_TAB
3922 if (optimize_size && scratch)
3927 return (AS1 (swap,%B0) CR_TAB
3928 AS1 (swap,%A0) CR_TAB
3929 AS2 (andi,%A0,0x0f) CR_TAB
3930 AS2 (eor,%A0,%B0) CR_TAB
3931 AS2 (andi,%B0,0x0f) CR_TAB
3937 return (AS1 (swap,%B0) CR_TAB
3938 AS1 (swap,%A0) CR_TAB
3939 AS2 (ldi,%3,0x0f) CR_TAB
3941 AS2 (eor,%A0,%B0) CR_TAB
3945 break; /* optimize_size ? 6 : 8 */
3949 break; /* scratch ? 5 : 6 */
3953 return (AS1 (lsr,%B0) CR_TAB
3954 AS1 (ror,%A0) CR_TAB
3955 AS1 (swap,%B0) CR_TAB
3956 AS1 (swap,%A0) CR_TAB
3957 AS2 (andi,%A0,0x0f) CR_TAB
3958 AS2 (eor,%A0,%B0) CR_TAB
3959 AS2 (andi,%B0,0x0f) CR_TAB
3965 return (AS1 (lsr,%B0) CR_TAB
3966 AS1 (ror,%A0) CR_TAB
3967 AS1 (swap,%B0) CR_TAB
3968 AS1 (swap,%A0) CR_TAB
3969 AS2 (ldi,%3,0x0f) CR_TAB
3971 AS2 (eor,%A0,%B0) CR_TAB
3979 break; /* scratch ? 5 : 6 */
3981 return (AS1 (clr,__tmp_reg__) CR_TAB
3982 AS1 (lsl,%A0) CR_TAB
3983 AS1 (rol,%B0) CR_TAB
3984 AS1 (rol,__tmp_reg__) CR_TAB
3985 AS1 (lsl,%A0) CR_TAB
3986 AS1 (rol,%B0) CR_TAB
3987 AS1 (rol,__tmp_reg__) CR_TAB
3988 AS2 (mov,%A0,%B0) CR_TAB
3989 AS2 (mov,%B0,__tmp_reg__));
3993 return (AS1 (lsl,%A0) CR_TAB
3994 AS2 (mov,%A0,%B0) CR_TAB
3995 AS1 (rol,%A0) CR_TAB
3996 AS2 (sbc,%B0,%B0) CR_TAB
4000 return *len = 2, (AS2 (mov,%A0,%B1) CR_TAB
4005 return (AS2 (mov,%A0,%B0) CR_TAB
4006 AS1 (clr,%B0) CR_TAB
4011 return (AS2 (mov,%A0,%B0) CR_TAB
4012 AS1 (clr,%B0) CR_TAB
4013 AS1 (lsr,%A0) CR_TAB
4018 return (AS2 (mov,%A0,%B0) CR_TAB
4019 AS1 (clr,%B0) CR_TAB
4020 AS1 (lsr,%A0) CR_TAB
4021 AS1 (lsr,%A0) CR_TAB
4028 return (AS2 (mov,%A0,%B0) CR_TAB
4029 AS1 (clr,%B0) CR_TAB
4030 AS1 (swap,%A0) CR_TAB
4031 AS2 (andi,%A0,0x0f));
4036 return (AS2 (mov,%A0,%B0) CR_TAB
4037 AS1 (clr,%B0) CR_TAB
4038 AS1 (swap,%A0) CR_TAB
4039 AS2 (ldi,%3,0x0f) CR_TAB
4043 return (AS2 (mov,%A0,%B0) CR_TAB
4044 AS1 (clr,%B0) CR_TAB
4045 AS1 (lsr,%A0) CR_TAB
4046 AS1 (lsr,%A0) CR_TAB
4047 AS1 (lsr,%A0) CR_TAB
4054 return (AS2 (mov,%A0,%B0) CR_TAB
4055 AS1 (clr,%B0) CR_TAB
4056 AS1 (swap,%A0) CR_TAB
4057 AS1 (lsr,%A0) CR_TAB
4058 AS2 (andi,%A0,0x07));
4060 if (AVR_HAVE_MUL && scratch)
4063 return (AS2 (ldi,%3,0x08) CR_TAB
4064 AS2 (mul,%B0,%3) CR_TAB
4065 AS2 (mov,%A0,r1) CR_TAB
4066 AS1 (clr,%B0) CR_TAB
4067 AS1 (clr,__zero_reg__));
4069 if (optimize_size && scratch)
4074 return (AS2 (mov,%A0,%B0) CR_TAB
4075 AS1 (clr,%B0) CR_TAB
4076 AS1 (swap,%A0) CR_TAB
4077 AS1 (lsr,%A0) CR_TAB
4078 AS2 (ldi,%3,0x07) CR_TAB
4084 return ("set" CR_TAB
4085 AS2 (bld,r1,3) CR_TAB
4086 AS2 (mul,%B0,r1) CR_TAB
4087 AS2 (mov,%A0,r1) CR_TAB
4088 AS1 (clr,%B0) CR_TAB
4089 AS1 (clr,__zero_reg__));
4092 return (AS2 (mov,%A0,%B0) CR_TAB
4093 AS1 (clr,%B0) CR_TAB
4094 AS1 (lsr,%A0) CR_TAB
4095 AS1 (lsr,%A0) CR_TAB
4096 AS1 (lsr,%A0) CR_TAB
4097 AS1 (lsr,%A0) CR_TAB
4101 if (AVR_HAVE_MUL && ldi_ok)
4104 return (AS2 (ldi,%A0,0x04) CR_TAB
4105 AS2 (mul,%B0,%A0) CR_TAB
4106 AS2 (mov,%A0,r1) CR_TAB
4107 AS1 (clr,%B0) CR_TAB
4108 AS1 (clr,__zero_reg__));
4110 if (AVR_HAVE_MUL && scratch)
4113 return (AS2 (ldi,%3,0x04) CR_TAB
4114 AS2 (mul,%B0,%3) CR_TAB
4115 AS2 (mov,%A0,r1) CR_TAB
4116 AS1 (clr,%B0) CR_TAB
4117 AS1 (clr,__zero_reg__));
4119 if (optimize_size && ldi_ok)
4122 return (AS2 (mov,%A0,%B0) CR_TAB
4123 AS2 (ldi,%B0,6) "\n1:\t"
4124 AS1 (lsr,%A0) CR_TAB
4125 AS1 (dec,%B0) CR_TAB
4128 if (optimize_size && scratch)
4131 return (AS1 (clr,%A0) CR_TAB
4132 AS1 (lsl,%B0) CR_TAB
4133 AS1 (rol,%A0) CR_TAB
4134 AS1 (lsl,%B0) CR_TAB
4135 AS1 (rol,%A0) CR_TAB
4140 return (AS1 (clr,%A0) CR_TAB
4141 AS1 (lsl,%B0) CR_TAB
4142 AS1 (rol,%A0) CR_TAB
4147 out_shift_with_cnt ((AS1 (lsr,%B0) CR_TAB
4149 insn, operands, len, 2);
4153 /* 32bit logic shift right ((unsigned int)x >> i) */
4156 lshrsi3_out (rtx insn, rtx operands[], int *len)
4158 if (GET_CODE (operands[2]) == CONST_INT)
4166 switch (INTVAL (operands[2]))
4169 if (INTVAL (operands[2]) < 32)
4173 return *len = 3, (AS1 (clr,%D0) CR_TAB
4174 AS1 (clr,%C0) CR_TAB
4175 AS2 (movw,%A0,%C0));
4177 return (AS1 (clr,%D0) CR_TAB
4178 AS1 (clr,%C0) CR_TAB
4179 AS1 (clr,%B0) CR_TAB
4184 int reg0 = true_regnum (operands[0]);
4185 int reg1 = true_regnum (operands[1]);
4188 return (AS2 (mov,%A0,%B1) CR_TAB
4189 AS2 (mov,%B0,%C1) CR_TAB
4190 AS2 (mov,%C0,%D1) CR_TAB
4193 return (AS1 (clr,%D0) CR_TAB
4194 AS2 (mov,%C0,%D1) CR_TAB
4195 AS2 (mov,%B0,%C1) CR_TAB
4201 int reg0 = true_regnum (operands[0]);
4202 int reg1 = true_regnum (operands[1]);
4204 if (reg0 == reg1 + 2)
4205 return *len = 2, (AS1 (clr,%C0) CR_TAB
4208 return *len = 3, (AS2 (movw,%A0,%C1) CR_TAB
4209 AS1 (clr,%C0) CR_TAB
4212 return *len = 4, (AS2 (mov,%B0,%D1) CR_TAB
4213 AS2 (mov,%A0,%C1) CR_TAB
4214 AS1 (clr,%C0) CR_TAB
4219 return *len = 4, (AS2 (mov,%A0,%D1) CR_TAB
4220 AS1 (clr,%B0) CR_TAB
4221 AS1 (clr,%C0) CR_TAB
4226 return (AS1 (clr,%A0) CR_TAB
4227 AS2 (sbrc,%D0,7) CR_TAB
4228 AS1 (inc,%A0) CR_TAB
4229 AS1 (clr,%B0) CR_TAB
4230 AS1 (clr,%C0) CR_TAB
4235 out_shift_with_cnt ((AS1 (lsr,%D0) CR_TAB
4236 AS1 (ror,%C0) CR_TAB
4237 AS1 (ror,%B0) CR_TAB
4239 insn, operands, len, 4);
4243 /* Create RTL split patterns for byte sized rotate expressions. This
4244 produces a series of move instructions and considers overlap situations.
4245 Overlapping non-HImode operands need a scratch register. */
4248 avr_rotate_bytes (rtx operands[])
4251 enum machine_mode mode = GET_MODE (operands[0]);
4252 bool overlapped = reg_overlap_mentioned_p (operands[0], operands[1]);
4253 bool same_reg = rtx_equal_p (operands[0], operands[1]);
4254 int num = INTVAL (operands[2]);
4255 rtx scratch = operands[3];
4256 /* Work out if byte or word move is needed. Odd byte rotates need QImode.
4257 Word move if no scratch is needed, otherwise use size of scratch. */
4258 enum machine_mode move_mode = QImode;
4259 int move_size, offset, size;
4263 else if ((mode == SImode && !same_reg) || !overlapped)
4266 move_mode = GET_MODE (scratch);
4268 /* Force DI rotate to use QI moves since other DI moves are currently split
4269 into QI moves so forward propagation works better. */
4272 /* Make scratch smaller if needed. */
4273 if (GET_MODE (scratch) == HImode && move_mode == QImode)
4274 scratch = simplify_gen_subreg (move_mode, scratch, HImode, 0);
4276 move_size = GET_MODE_SIZE (move_mode);
4277 /* Number of bytes/words to rotate. */
4278 offset = (num >> 3) / move_size;
4279 /* Number of moves needed. */
4280 size = GET_MODE_SIZE (mode) / move_size;
4281 /* Himode byte swap is special case to avoid a scratch register. */
4282 if (mode == HImode && same_reg)
4284 /* HImode byte swap, using xor. This is as quick as using scratch. */
4286 src = simplify_gen_subreg (move_mode, operands[1], mode, 0);
4287 dst = simplify_gen_subreg (move_mode, operands[0], mode, 1);
4288 if (!rtx_equal_p (dst, src))
4290 emit_move_insn (dst, gen_rtx_XOR (QImode, dst, src));
4291 emit_move_insn (src, gen_rtx_XOR (QImode, src, dst));
4292 emit_move_insn (dst, gen_rtx_XOR (QImode, dst, src));
4297 #define MAX_SIZE 8 /* GET_MODE_SIZE (DImode) / GET_MODE_SIZE (QImode) */
4298 /* Create linked list of moves to determine move order. */
4302 } move[MAX_SIZE + 8];
4305 gcc_assert (size <= MAX_SIZE);
4306 /* Generate list of subreg moves. */
4307 for (i = 0; i < size; i++)
4310 int to = (from + offset) % size;
4311 move[i].src = simplify_gen_subreg (move_mode, operands[1],
4312 mode, from * move_size);
4313 move[i].dst = simplify_gen_subreg (move_mode, operands[0],
4314 mode, to * move_size);
4317 /* Mark dependence where a dst of one move is the src of another move.
4318 The first move is a conflict as it must wait until second is
4319 performed. We ignore moves to self - we catch this later. */
4321 for (i = 0; i < size; i++)
4322 if (reg_overlap_mentioned_p (move[i].dst, operands[1]))
4323 for (j = 0; j < size; j++)
4324 if (j != i && rtx_equal_p (move[j].src, move[i].dst))
4326 /* The dst of move i is the src of move j. */
4333 /* Go through move list and perform non-conflicting moves. As each
4334 non-overlapping move is made, it may remove other conflicts
4335 so the process is repeated until no conflicts remain. */
4340 /* Emit move where dst is not also a src or we have used that
4342 for (i = 0; i < size; i++)
4343 if (move[i].src != NULL_RTX)
4345 if (move[i].links == -1
4346 || move[move[i].links].src == NULL_RTX)
4349 /* Ignore NOP moves to self. */
4350 if (!rtx_equal_p (move[i].dst, move[i].src))
4351 emit_move_insn (move[i].dst, move[i].src);
4353 /* Remove conflict from list. */
4354 move[i].src = NULL_RTX;
4360 /* Check for deadlock. This is when no moves occurred and we have
4361 at least one blocked move. */
4362 if (moves == 0 && blocked != -1)
4364 /* Need to use scratch register to break deadlock.
4365 Add move to put dst of blocked move into scratch.
4366 When this move occurs, it will break chain deadlock.
4367 The scratch register is substituted for real move. */
4369 move[size].src = move[blocked].dst;
4370 move[size].dst = scratch;
4371 /* Scratch move is never blocked. */
4372 move[size].links = -1;
4373 /* Make sure we have valid link. */
4374 gcc_assert (move[blocked].links != -1);
4375 /* Replace src of blocking move with scratch reg. */
4376 move[move[blocked].links].src = scratch;
4377 /* Make dependent on scratch move occuring. */
4378 move[blocked].links = size;
4382 while (blocked != -1);
4387 /* Modifies the length assigned to instruction INSN
4388 LEN is the initially computed length of the insn. */
4391 adjust_insn_length (rtx insn, int len)
4393 rtx patt = PATTERN (insn);
4396 if (GET_CODE (patt) == SET)
4399 op[1] = SET_SRC (patt);
4400 op[0] = SET_DEST (patt);
4401 if (general_operand (op[1], VOIDmode)
4402 && general_operand (op[0], VOIDmode))
4404 switch (GET_MODE (op[0]))
4407 output_movqi (insn, op, &len);
4410 output_movhi (insn, op, &len);
4414 output_movsisf (insn, op, &len);
4420 else if (op[0] == cc0_rtx && REG_P (op[1]))
4422 switch (GET_MODE (op[1]))
4424 case HImode: out_tsthi (insn, op[1], &len); break;
4425 case SImode: out_tstsi (insn, op[1], &len); break;
4429 else if (GET_CODE (op[1]) == AND)
4431 if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
4433 HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
4434 if (GET_MODE (op[1]) == SImode)
4435 len = (((mask & 0xff) != 0xff)
4436 + ((mask & 0xff00) != 0xff00)
4437 + ((mask & 0xff0000L) != 0xff0000L)
4438 + ((mask & 0xff000000L) != 0xff000000L));
4439 else if (GET_MODE (op[1]) == HImode)
4440 len = (((mask & 0xff) != 0xff)
4441 + ((mask & 0xff00) != 0xff00));
4444 else if (GET_CODE (op[1]) == IOR)
4446 if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
4448 HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
4449 if (GET_MODE (op[1]) == SImode)
4450 len = (((mask & 0xff) != 0)
4451 + ((mask & 0xff00) != 0)
4452 + ((mask & 0xff0000L) != 0)
4453 + ((mask & 0xff000000L) != 0));
4454 else if (GET_MODE (op[1]) == HImode)
4455 len = (((mask & 0xff) != 0)
4456 + ((mask & 0xff00) != 0));
4460 set = single_set (insn);
4465 op[1] = SET_SRC (set);
4466 op[0] = SET_DEST (set);
4468 if (GET_CODE (patt) == PARALLEL
4469 && general_operand (op[1], VOIDmode)
4470 && general_operand (op[0], VOIDmode))
4472 if (XVECLEN (patt, 0) == 2)
4473 op[2] = XVECEXP (patt, 0, 1);
4475 switch (GET_MODE (op[0]))
4481 output_reload_inhi (insn, op, &len);
4485 output_reload_insisf (insn, op, &len);
4491 else if (GET_CODE (op[1]) == ASHIFT
4492 || GET_CODE (op[1]) == ASHIFTRT
4493 || GET_CODE (op[1]) == LSHIFTRT)
4497 ops[1] = XEXP (op[1],0);
4498 ops[2] = XEXP (op[1],1);
4499 switch (GET_CODE (op[1]))
4502 switch (GET_MODE (op[0]))
4504 case QImode: ashlqi3_out (insn,ops,&len); break;
4505 case HImode: ashlhi3_out (insn,ops,&len); break;
4506 case SImode: ashlsi3_out (insn,ops,&len); break;
4511 switch (GET_MODE (op[0]))
4513 case QImode: ashrqi3_out (insn,ops,&len); break;
4514 case HImode: ashrhi3_out (insn,ops,&len); break;
4515 case SImode: ashrsi3_out (insn,ops,&len); break;
4520 switch (GET_MODE (op[0]))
4522 case QImode: lshrqi3_out (insn,ops,&len); break;
4523 case HImode: lshrhi3_out (insn,ops,&len); break;
4524 case SImode: lshrsi3_out (insn,ops,&len); break;
4536 /* Return nonzero if register REG dead after INSN. */
4539 reg_unused_after (rtx insn, rtx reg)
4541 return (dead_or_set_p (insn, reg)
4542 || (REG_P(reg) && _reg_unused_after (insn, reg)));
4545 /* Return nonzero if REG is not used after INSN.
4546 We assume REG is a reload reg, and therefore does
4547 not live past labels. It may live past calls or jumps though. */
4550 _reg_unused_after (rtx insn, rtx reg)
4555 /* If the reg is set by this instruction, then it is safe for our
4556 case. Disregard the case where this is a store to memory, since
4557 we are checking a register used in the store address. */
4558 set = single_set (insn);
4559 if (set && GET_CODE (SET_DEST (set)) != MEM
4560 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4563 while ((insn = NEXT_INSN (insn)))
4566 code = GET_CODE (insn);
4569 /* If this is a label that existed before reload, then the register
4570 if dead here. However, if this is a label added by reorg, then
4571 the register may still be live here. We can't tell the difference,
4572 so we just ignore labels completely. */
4573 if (code == CODE_LABEL)
4581 if (code == JUMP_INSN)
4584 /* If this is a sequence, we must handle them all at once.
4585 We could have for instance a call that sets the target register,
4586 and an insn in a delay slot that uses the register. In this case,
4587 we must return 0. */
4588 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4593 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
4595 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
4596 rtx set = single_set (this_insn);
4598 if (GET_CODE (this_insn) == CALL_INSN)
4600 else if (GET_CODE (this_insn) == JUMP_INSN)
4602 if (INSN_ANNULLED_BRANCH_P (this_insn))
4607 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4609 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4611 if (GET_CODE (SET_DEST (set)) != MEM)
4617 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
4622 else if (code == JUMP_INSN)
4626 if (code == CALL_INSN)
4629 for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1))
4630 if (GET_CODE (XEXP (tem, 0)) == USE
4631 && REG_P (XEXP (XEXP (tem, 0), 0))
4632 && reg_overlap_mentioned_p (reg, XEXP (XEXP (tem, 0), 0)))
4634 if (call_used_regs[REGNO (reg)])
4638 set = single_set (insn);
4640 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4642 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4643 return GET_CODE (SET_DEST (set)) != MEM;
4644 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
4650 /* Target hook for assembling integer objects. The AVR version needs
4651 special handling for references to certain labels. */
4654 avr_assemble_integer (rtx x, unsigned int size, int aligned_p)
4656 if (size == POINTER_SIZE / BITS_PER_UNIT && aligned_p
4657 && text_segment_operand (x, VOIDmode) )
4659 fputs ("\t.word\tgs(", asm_out_file);
4660 output_addr_const (asm_out_file, x);
4661 fputs (")\n", asm_out_file);
4664 return default_assemble_integer (x, size, aligned_p);
4667 /* Worker function for ASM_DECLARE_FUNCTION_NAME. */
4670 avr_asm_declare_function_name (FILE *file, const char *name, tree decl)
4673 /* If the function has the 'signal' or 'interrupt' attribute, test to
4674 make sure that the name of the function is "__vector_NN" so as to
4675 catch when the user misspells the interrupt vector name. */
4677 if (cfun->machine->is_interrupt)
4679 if (strncmp (name, "__vector", strlen ("__vector")) != 0)
4681 warning_at (DECL_SOURCE_LOCATION (decl), 0,
4682 "%qs appears to be a misspelled interrupt handler",
4686 else if (cfun->machine->is_signal)
4688 if (strncmp (name, "__vector", strlen ("__vector")) != 0)
4690 warning_at (DECL_SOURCE_LOCATION (decl), 0,
4691 "%qs appears to be a misspelled signal handler",
4696 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4697 ASM_OUTPUT_LABEL (file, name);
4700 /* The routine used to output NUL terminated strings. We use a special
4701 version of this for most svr4 targets because doing so makes the
4702 generated assembly code more compact (and thus faster to assemble)
4703 as well as more readable, especially for targets like the i386
4704 (where the only alternative is to output character sequences as
4705 comma separated lists of numbers). */
4708 gas_output_limited_string(FILE *file, const char *str)
4710 const unsigned char *_limited_str = (const unsigned char *) str;
4712 fprintf (file, "%s\"", STRING_ASM_OP);
4713 for (; (ch = *_limited_str); _limited_str++)
4716 switch (escape = ESCAPES[ch])
4722 fprintf (file, "\\%03o", ch);
4726 putc (escape, file);
4730 fprintf (file, "\"\n");
4733 /* The routine used to output sequences of byte values. We use a special
4734 version of this for most svr4 targets because doing so makes the
4735 generated assembly code more compact (and thus faster to assemble)
4736 as well as more readable. Note that if we find subparts of the
4737 character sequence which end with NUL (and which are shorter than
4738 STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */
4741 gas_output_ascii(FILE *file, const char *str, size_t length)
4743 const unsigned char *_ascii_bytes = (const unsigned char *) str;
4744 const unsigned char *limit = _ascii_bytes + length;
4745 unsigned bytes_in_chunk = 0;
4746 for (; _ascii_bytes < limit; _ascii_bytes++)
4748 const unsigned char *p;
4749 if (bytes_in_chunk >= 60)
4751 fprintf (file, "\"\n");
4754 for (p = _ascii_bytes; p < limit && *p != '\0'; p++)
4756 if (p < limit && (p - _ascii_bytes) <= (signed)STRING_LIMIT)
4758 if (bytes_in_chunk > 0)
4760 fprintf (file, "\"\n");
4763 gas_output_limited_string (file, (const char*)_ascii_bytes);
4770 if (bytes_in_chunk == 0)
4771 fprintf (file, "\t.ascii\t\"");
4772 switch (escape = ESCAPES[ch = *_ascii_bytes])
4779 fprintf (file, "\\%03o", ch);
4780 bytes_in_chunk += 4;
4784 putc (escape, file);
4785 bytes_in_chunk += 2;
4790 if (bytes_in_chunk > 0)
4791 fprintf (file, "\"\n");
4794 /* Return value is nonzero if pseudos that have been
4795 assigned to registers of class CLASS would likely be spilled
4796 because registers of CLASS are needed for spill registers. */
4799 avr_class_likely_spilled_p (reg_class_t c)
4801 return (c != ALL_REGS && c != ADDW_REGS);
4804 /* Valid attributes:
4805 progmem - put data to program memory;
4806 signal - make a function to be hardware interrupt. After function
4807 prologue interrupts are disabled;
4808 interrupt - make a function to be hardware interrupt. After function
4809 prologue interrupts are enabled;
4810 naked - don't generate function prologue/epilogue and `ret' command.
4812 Only `progmem' attribute valid for type. */
4814 /* Handle a "progmem" attribute; arguments as in
4815 struct attribute_spec.handler. */
4817 avr_handle_progmem_attribute (tree *node, tree name,
4818 tree args ATTRIBUTE_UNUSED,
4819 int flags ATTRIBUTE_UNUSED,
4824 if (TREE_CODE (*node) == TYPE_DECL)
4826 /* This is really a decl attribute, not a type attribute,
4827 but try to handle it for GCC 3.0 backwards compatibility. */
4829 tree type = TREE_TYPE (*node);
4830 tree attr = tree_cons (name, args, TYPE_ATTRIBUTES (type));
4831 tree newtype = build_type_attribute_variant (type, attr);
4833 TYPE_MAIN_VARIANT (newtype) = TYPE_MAIN_VARIANT (type);
4834 TREE_TYPE (*node) = newtype;
4835 *no_add_attrs = true;
4837 else if (TREE_STATIC (*node) || DECL_EXTERNAL (*node))
4839 if (DECL_INITIAL (*node) == NULL_TREE && !DECL_EXTERNAL (*node))
4841 warning (0, "only initialized variables can be placed into "
4842 "program memory area");
4843 *no_add_attrs = true;
4848 warning (OPT_Wattributes, "%qE attribute ignored",
4850 *no_add_attrs = true;
4857 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4858 struct attribute_spec.handler. */
4861 avr_handle_fndecl_attribute (tree *node, tree name,
4862 tree args ATTRIBUTE_UNUSED,
4863 int flags ATTRIBUTE_UNUSED,
4866 if (TREE_CODE (*node) != FUNCTION_DECL)
4868 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4870 *no_add_attrs = true;
4877 avr_handle_fntype_attribute (tree *node, tree name,
4878 tree args ATTRIBUTE_UNUSED,
4879 int flags ATTRIBUTE_UNUSED,
4882 if (TREE_CODE (*node) != FUNCTION_TYPE)
4884 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4886 *no_add_attrs = true;
4892 /* Look for attribute `progmem' in DECL
4893 if found return 1, otherwise 0. */
4896 avr_progmem_p (tree decl, tree attributes)
4900 if (TREE_CODE (decl) != VAR_DECL)
4904 != lookup_attribute ("progmem", attributes))
4910 while (TREE_CODE (a) == ARRAY_TYPE);
4912 if (a == error_mark_node)
4915 if (NULL_TREE != lookup_attribute ("progmem", TYPE_ATTRIBUTES (a)))
4921 /* Add the section attribute if the variable is in progmem. */
4924 avr_insert_attributes (tree node, tree *attributes)
4926 if (TREE_CODE (node) == VAR_DECL
4927 && (TREE_STATIC (node) || DECL_EXTERNAL (node))
4928 && avr_progmem_p (node, *attributes))
4930 static const char dsec[] = ".progmem.data";
4931 *attributes = tree_cons (get_identifier ("section"),
4932 build_tree_list (NULL, build_string (strlen (dsec), dsec)),
4935 /* ??? This seems sketchy. Why can't the user declare the
4936 thing const in the first place? */
4937 TREE_READONLY (node) = 1;
4941 /* A get_unnamed_section callback for switching to progmem_section. */
4944 avr_output_progmem_section_asm_op (const void *arg ATTRIBUTE_UNUSED)
4946 fprintf (asm_out_file,
4947 "\t.section .progmem.gcc_sw_table, \"%s\", @progbits\n",
4948 AVR_HAVE_JMP_CALL ? "a" : "ax");
4949 /* Should already be aligned, this is just to be safe if it isn't. */
4950 fprintf (asm_out_file, "\t.p2align 1\n");
4953 /* Implement TARGET_ASM_INIT_SECTIONS. */
4956 avr_asm_init_sections (void)
4958 progmem_section = get_unnamed_section (AVR_HAVE_JMP_CALL ? 0 : SECTION_CODE,
4959 avr_output_progmem_section_asm_op,
4961 readonly_data_section = data_section;
4965 avr_section_type_flags (tree decl, const char *name, int reloc)
4967 unsigned int flags = default_section_type_flags (decl, name, reloc);
4969 if (strncmp (name, ".noinit", 7) == 0)
4971 if (decl && TREE_CODE (decl) == VAR_DECL
4972 && DECL_INITIAL (decl) == NULL_TREE)
4973 flags |= SECTION_BSS; /* @nobits */
4975 warning (0, "only uninitialized variables can be placed in the "
4982 /* Outputs some appropriate text to go at the start of an assembler
4986 avr_file_start (void)
4988 if (avr_current_arch->asm_only)
4989 error ("MCU %qs supported for assembler only", avr_mcu_name);
4991 default_file_start ();
4993 /* fprintf (asm_out_file, "\t.arch %s\n", avr_mcu_name);*/
4994 fputs ("__SREG__ = 0x3f\n"
4996 "__SP_L__ = 0x3d\n", asm_out_file);
4998 fputs ("__tmp_reg__ = 0\n"
4999 "__zero_reg__ = 1\n", asm_out_file);
5001 /* FIXME: output these only if there is anything in the .data / .bss
5002 sections - some code size could be saved by not linking in the
5003 initialization code from libgcc if one or both sections are empty. */
5004 fputs ("\t.global __do_copy_data\n", asm_out_file);
5005 fputs ("\t.global __do_clear_bss\n", asm_out_file);
5008 /* Outputs to the stdio stream FILE some
5009 appropriate text to go at the end of an assembler file. */
5016 /* Choose the order in which to allocate hard registers for
5017 pseudo-registers local to a basic block.
5019 Store the desired register order in the array `reg_alloc_order'.
5020 Element 0 should be the register to allocate first; element 1, the
5021 next register; and so on. */
5024 order_regs_for_local_alloc (void)
5027 static const int order_0[] = {
5035 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
5039 static const int order_1[] = {
5047 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
5051 static const int order_2[] = {
5060 15,14,13,12,11,10,9,8,7,6,5,4,3,2,
5065 const int *order = (TARGET_ORDER_1 ? order_1 :
5066 TARGET_ORDER_2 ? order_2 :
5068 for (i=0; i < ARRAY_SIZE (order_0); ++i)
5069 reg_alloc_order[i] = order[i];
5073 /* Mutually recursive subroutine of avr_rtx_cost for calculating the
5074 cost of an RTX operand given its context. X is the rtx of the
5075 operand, MODE is its mode, and OUTER is the rtx_code of this
5076 operand's parent operator. */
5079 avr_operand_rtx_cost (rtx x, enum machine_mode mode, enum rtx_code outer,
5082 enum rtx_code code = GET_CODE (x);
5093 return COSTS_N_INSNS (GET_MODE_SIZE (mode));
5100 avr_rtx_costs (x, code, outer, &total, speed);
5104 /* The AVR backend's rtx_cost function. X is rtx expression whose cost
5105 is to be calculated. Return true if the complete cost has been
5106 computed, and false if subexpressions should be scanned. In either
5107 case, *TOTAL contains the cost result. */
5110 avr_rtx_costs (rtx x, int codearg, int outer_code ATTRIBUTE_UNUSED, int *total,
5113 enum rtx_code code = (enum rtx_code) codearg;
5114 enum machine_mode mode = GET_MODE (x);
5121 /* Immediate constants are as cheap as registers. */
5129 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
5137 *total = COSTS_N_INSNS (1);
5141 *total = COSTS_N_INSNS (3);
5145 *total = COSTS_N_INSNS (7);
5151 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5159 *total = COSTS_N_INSNS (1);
5165 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5169 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
5170 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5174 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)
5175 - GET_MODE_SIZE (GET_MODE (XEXP (x, 0))));
5176 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5180 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) + 2
5181 - GET_MODE_SIZE (GET_MODE (XEXP (x, 0))));
5182 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5189 *total = COSTS_N_INSNS (1);
5190 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5191 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5195 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5197 *total = COSTS_N_INSNS (2);
5198 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5200 else if (INTVAL (XEXP (x, 1)) >= -63 && INTVAL (XEXP (x, 1)) <= 63)
5201 *total = COSTS_N_INSNS (1);
5203 *total = COSTS_N_INSNS (2);
5207 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5209 *total = COSTS_N_INSNS (4);
5210 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5212 else if (INTVAL (XEXP (x, 1)) >= -63 && INTVAL (XEXP (x, 1)) <= 63)
5213 *total = COSTS_N_INSNS (1);
5215 *total = COSTS_N_INSNS (4);
5221 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5227 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
5228 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5229 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5230 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5234 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
5235 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5236 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5244 *total = COSTS_N_INSNS (!speed ? 3 : 4);
5246 *total = COSTS_N_INSNS (AVR_HAVE_JMP_CALL ? 2 : 1);
5253 *total = COSTS_N_INSNS (!speed ? 7 : 10);
5255 *total = COSTS_N_INSNS (AVR_HAVE_JMP_CALL ? 2 : 1);
5263 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5264 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5272 *total = COSTS_N_INSNS (AVR_HAVE_JMP_CALL ? 2 : 1);
5275 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5276 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5283 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 4)
5284 *total = COSTS_N_INSNS (1);
5289 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 8)
5290 *total = COSTS_N_INSNS (3);
5295 if (CONST_INT_P (XEXP (x, 1)))
5296 switch (INTVAL (XEXP (x, 1)))
5300 *total = COSTS_N_INSNS (5);
5303 *total = COSTS_N_INSNS (AVR_HAVE_MOVW ? 4 : 6);
5311 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5318 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5320 *total = COSTS_N_INSNS (!speed ? 4 : 17);
5321 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5325 val = INTVAL (XEXP (x, 1));
5327 *total = COSTS_N_INSNS (3);
5328 else if (val >= 0 && val <= 7)
5329 *total = COSTS_N_INSNS (val);
5331 *total = COSTS_N_INSNS (1);
5336 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5338 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5339 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5342 switch (INTVAL (XEXP (x, 1)))
5349 *total = COSTS_N_INSNS (2);
5352 *total = COSTS_N_INSNS (3);
5358 *total = COSTS_N_INSNS (4);
5363 *total = COSTS_N_INSNS (5);
5366 *total = COSTS_N_INSNS (!speed ? 5 : 8);
5369 *total = COSTS_N_INSNS (!speed ? 5 : 9);
5372 *total = COSTS_N_INSNS (!speed ? 5 : 10);
5375 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5376 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5381 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5383 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5384 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5387 switch (INTVAL (XEXP (x, 1)))
5393 *total = COSTS_N_INSNS (3);
5398 *total = COSTS_N_INSNS (4);
5401 *total = COSTS_N_INSNS (6);
5404 *total = COSTS_N_INSNS (!speed ? 7 : 8);
5407 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5408 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5415 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5422 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5424 *total = COSTS_N_INSNS (!speed ? 4 : 17);
5425 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5429 val = INTVAL (XEXP (x, 1));
5431 *total = COSTS_N_INSNS (4);
5433 *total = COSTS_N_INSNS (2);
5434 else if (val >= 0 && val <= 7)
5435 *total = COSTS_N_INSNS (val);
5437 *total = COSTS_N_INSNS (1);
5442 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5444 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5445 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5448 switch (INTVAL (XEXP (x, 1)))
5454 *total = COSTS_N_INSNS (2);
5457 *total = COSTS_N_INSNS (3);
5463 *total = COSTS_N_INSNS (4);
5467 *total = COSTS_N_INSNS (5);
5470 *total = COSTS_N_INSNS (!speed ? 5 : 6);
5473 *total = COSTS_N_INSNS (!speed ? 5 : 7);
5477 *total = COSTS_N_INSNS (!speed ? 5 : 8);
5480 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5481 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5486 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5488 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5489 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5492 switch (INTVAL (XEXP (x, 1)))
5498 *total = COSTS_N_INSNS (4);
5503 *total = COSTS_N_INSNS (6);
5506 *total = COSTS_N_INSNS (!speed ? 7 : 8);
5509 *total = COSTS_N_INSNS (AVR_HAVE_MOVW ? 4 : 5);
5512 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5513 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5520 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5527 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5529 *total = COSTS_N_INSNS (!speed ? 4 : 17);
5530 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5534 val = INTVAL (XEXP (x, 1));
5536 *total = COSTS_N_INSNS (3);
5537 else if (val >= 0 && val <= 7)
5538 *total = COSTS_N_INSNS (val);
5540 *total = COSTS_N_INSNS (1);
5545 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5547 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5548 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5551 switch (INTVAL (XEXP (x, 1)))
5558 *total = COSTS_N_INSNS (2);
5561 *total = COSTS_N_INSNS (3);
5566 *total = COSTS_N_INSNS (4);
5570 *total = COSTS_N_INSNS (5);
5576 *total = COSTS_N_INSNS (!speed ? 5 : 6);
5579 *total = COSTS_N_INSNS (!speed ? 5 : 7);
5583 *total = COSTS_N_INSNS (!speed ? 5 : 9);
5586 *total = COSTS_N_INSNS (!speed ? 5 : 41);
5587 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5592 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5594 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5595 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5598 switch (INTVAL (XEXP (x, 1)))
5604 *total = COSTS_N_INSNS (4);
5607 *total = COSTS_N_INSNS (!speed ? 7 : 8);
5612 *total = COSTS_N_INSNS (4);
5615 *total = COSTS_N_INSNS (6);
5618 *total = COSTS_N_INSNS (!speed ? 7 : 113);
5619 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5626 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5630 switch (GET_MODE (XEXP (x, 0)))
5633 *total = COSTS_N_INSNS (1);
5634 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5635 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5639 *total = COSTS_N_INSNS (2);
5640 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5641 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5642 else if (INTVAL (XEXP (x, 1)) != 0)
5643 *total += COSTS_N_INSNS (1);
5647 *total = COSTS_N_INSNS (4);
5648 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5649 *total += avr_operand_rtx_cost (XEXP (x, 1), mode, code, speed);
5650 else if (INTVAL (XEXP (x, 1)) != 0)
5651 *total += COSTS_N_INSNS (3);
5657 *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, speed);
5666 /* Calculate the cost of a memory address. */
5669 avr_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
5671 if (GET_CODE (x) == PLUS
5672 && GET_CODE (XEXP (x,1)) == CONST_INT
5673 && (REG_P (XEXP (x,0)) || GET_CODE (XEXP (x,0)) == SUBREG)
5674 && INTVAL (XEXP (x,1)) >= 61)
5676 if (CONSTANT_ADDRESS_P (x))
5678 if (optimize > 0 && io_address_operand (x, QImode))
5685 /* Test for extra memory constraint 'Q'.
5686 It's a memory address based on Y or Z pointer with valid displacement. */
5689 extra_constraint_Q (rtx x)
5691 if (GET_CODE (XEXP (x,0)) == PLUS
5692 && REG_P (XEXP (XEXP (x,0), 0))
5693 && GET_CODE (XEXP (XEXP (x,0), 1)) == CONST_INT
5694 && (INTVAL (XEXP (XEXP (x,0), 1))
5695 <= MAX_LD_OFFSET (GET_MODE (x))))
5697 rtx xx = XEXP (XEXP (x,0), 0);
5698 int regno = REGNO (xx);
5699 if (TARGET_ALL_DEBUG)
5701 fprintf (stderr, ("extra_constraint:\n"
5702 "reload_completed: %d\n"
5703 "reload_in_progress: %d\n"),
5704 reload_completed, reload_in_progress);
5707 if (regno >= FIRST_PSEUDO_REGISTER)
5708 return 1; /* allocate pseudos */
5709 else if (regno == REG_Z || regno == REG_Y)
5710 return 1; /* strictly check */
5711 else if (xx == frame_pointer_rtx
5712 || xx == arg_pointer_rtx)
5713 return 1; /* XXX frame & arg pointer checks */
5718 /* Convert condition code CONDITION to the valid AVR condition code. */
5721 avr_normalize_condition (RTX_CODE condition)
5738 /* This function optimizes conditional jumps. */
5745 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5747 if (! (GET_CODE (insn) == INSN
5748 || GET_CODE (insn) == CALL_INSN
5749 || GET_CODE (insn) == JUMP_INSN)
5750 || !single_set (insn))
5753 pattern = PATTERN (insn);
5755 if (GET_CODE (pattern) == PARALLEL)
5756 pattern = XVECEXP (pattern, 0, 0);
5757 if (GET_CODE (pattern) == SET
5758 && SET_DEST (pattern) == cc0_rtx
5759 && compare_diff_p (insn))
5761 if (GET_CODE (SET_SRC (pattern)) == COMPARE)
5763 /* Now we work under compare insn. */
5765 pattern = SET_SRC (pattern);
5766 if (true_regnum (XEXP (pattern,0)) >= 0
5767 && true_regnum (XEXP (pattern,1)) >= 0 )
5769 rtx x = XEXP (pattern,0);
5770 rtx next = next_real_insn (insn);
5771 rtx pat = PATTERN (next);
5772 rtx src = SET_SRC (pat);
5773 rtx t = XEXP (src,0);
5774 PUT_CODE (t, swap_condition (GET_CODE (t)));
5775 XEXP (pattern,0) = XEXP (pattern,1);
5776 XEXP (pattern,1) = x;
5777 INSN_CODE (next) = -1;
5779 else if (true_regnum (XEXP (pattern, 0)) >= 0
5780 && XEXP (pattern, 1) == const0_rtx)
5782 /* This is a tst insn, we can reverse it. */
5783 rtx next = next_real_insn (insn);
5784 rtx pat = PATTERN (next);
5785 rtx src = SET_SRC (pat);
5786 rtx t = XEXP (src,0);
5788 PUT_CODE (t, swap_condition (GET_CODE (t)));
5789 XEXP (pattern, 1) = XEXP (pattern, 0);
5790 XEXP (pattern, 0) = const0_rtx;
5791 INSN_CODE (next) = -1;
5792 INSN_CODE (insn) = -1;
5794 else if (true_regnum (XEXP (pattern,0)) >= 0
5795 && GET_CODE (XEXP (pattern,1)) == CONST_INT)
5797 rtx x = XEXP (pattern,1);
5798 rtx next = next_real_insn (insn);
5799 rtx pat = PATTERN (next);
5800 rtx src = SET_SRC (pat);
5801 rtx t = XEXP (src,0);
5802 enum machine_mode mode = GET_MODE (XEXP (pattern, 0));
5804 if (avr_simplify_comparison_p (mode, GET_CODE (t), x))
5806 XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode);
5807 PUT_CODE (t, avr_normalize_condition (GET_CODE (t)));
5808 INSN_CODE (next) = -1;
5809 INSN_CODE (insn) = -1;
5817 /* Returns register number for function return value.*/
5820 avr_ret_register (void)
5825 /* Create an RTX representing the place where a
5826 library function returns a value of mode MODE. */
5829 avr_libcall_value (enum machine_mode mode)
5831 int offs = GET_MODE_SIZE (mode);
5834 return gen_rtx_REG (mode, RET_REGISTER + 2 - offs);
5837 /* Create an RTX representing the place where a
5838 function returns a value of data type VALTYPE. */
5841 avr_function_value (const_tree type,
5842 const_tree func ATTRIBUTE_UNUSED,
5843 bool outgoing ATTRIBUTE_UNUSED)
5847 if (TYPE_MODE (type) != BLKmode)
5848 return avr_libcall_value (TYPE_MODE (type));
5850 offs = int_size_in_bytes (type);
5853 if (offs > 2 && offs < GET_MODE_SIZE (SImode))
5854 offs = GET_MODE_SIZE (SImode);
5855 else if (offs > GET_MODE_SIZE (SImode) && offs < GET_MODE_SIZE (DImode))
5856 offs = GET_MODE_SIZE (DImode);
5858 return gen_rtx_REG (BLKmode, RET_REGISTER + 2 - offs);
5862 test_hard_reg_class (enum reg_class rclass, rtx x)
5864 int regno = true_regnum (x);
5868 if (TEST_HARD_REG_CLASS (rclass, regno))
5876 jump_over_one_insn_p (rtx insn, rtx dest)
5878 int uid = INSN_UID (GET_CODE (dest) == LABEL_REF
5881 int jump_addr = INSN_ADDRESSES (INSN_UID (insn));
5882 int dest_addr = INSN_ADDRESSES (uid);
5883 return dest_addr - jump_addr == get_attr_length (insn) + 1;
5886 /* Returns 1 if a value of mode MODE can be stored starting with hard
5887 register number REGNO. On the enhanced core, anything larger than
5888 1 byte must start in even numbered register for "movw" to work
5889 (this way we don't have to check for odd registers everywhere). */
5892 avr_hard_regno_mode_ok (int regno, enum machine_mode mode)
5894 /* Disallow QImode in stack pointer regs. */
5895 if ((regno == REG_SP || regno == (REG_SP + 1)) && mode == QImode)
5898 /* The only thing that can go into registers r28:r29 is a Pmode. */
5899 if (regno == REG_Y && mode == Pmode)
5902 /* Otherwise disallow all regno/mode combinations that span r28:r29. */
5903 if (regno <= (REG_Y + 1) && (regno + GET_MODE_SIZE (mode)) >= (REG_Y + 1))
5909 /* Modes larger than QImode occupy consecutive registers. */
5910 if (regno + GET_MODE_SIZE (mode) > FIRST_PSEUDO_REGISTER)
5913 /* All modes larger than QImode should start in an even register. */
5914 return !(regno & 1);
5918 output_reload_inhi (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
5924 if (GET_CODE (operands[1]) == CONST_INT)
5926 int val = INTVAL (operands[1]);
5927 if ((val & 0xff) == 0)
5930 return (AS2 (mov,%A0,__zero_reg__) CR_TAB
5931 AS2 (ldi,%2,hi8(%1)) CR_TAB
5934 else if ((val & 0xff00) == 0)
5937 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5938 AS2 (mov,%A0,%2) CR_TAB
5939 AS2 (mov,%B0,__zero_reg__));
5941 else if ((val & 0xff) == ((val & 0xff00) >> 8))
5944 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5945 AS2 (mov,%A0,%2) CR_TAB
5950 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5951 AS2 (mov,%A0,%2) CR_TAB
5952 AS2 (ldi,%2,hi8(%1)) CR_TAB
5958 output_reload_insisf (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
5960 rtx src = operands[1];
5961 int cnst = (GET_CODE (src) == CONST_INT);
5966 *len = 4 + ((INTVAL (src) & 0xff) != 0)
5967 + ((INTVAL (src) & 0xff00) != 0)
5968 + ((INTVAL (src) & 0xff0000) != 0)
5969 + ((INTVAL (src) & 0xff000000) != 0);
5976 if (cnst && ((INTVAL (src) & 0xff) == 0))
5977 output_asm_insn (AS2 (mov, %A0, __zero_reg__), operands);
5980 output_asm_insn (AS2 (ldi, %2, lo8(%1)), operands);
5981 output_asm_insn (AS2 (mov, %A0, %2), operands);
5983 if (cnst && ((INTVAL (src) & 0xff00) == 0))
5984 output_asm_insn (AS2 (mov, %B0, __zero_reg__), operands);
5987 output_asm_insn (AS2 (ldi, %2, hi8(%1)), operands);
5988 output_asm_insn (AS2 (mov, %B0, %2), operands);
5990 if (cnst && ((INTVAL (src) & 0xff0000) == 0))
5991 output_asm_insn (AS2 (mov, %C0, __zero_reg__), operands);
5994 output_asm_insn (AS2 (ldi, %2, hlo8(%1)), operands);
5995 output_asm_insn (AS2 (mov, %C0, %2), operands);
5997 if (cnst && ((INTVAL (src) & 0xff000000) == 0))
5998 output_asm_insn (AS2 (mov, %D0, __zero_reg__), operands);
6001 output_asm_insn (AS2 (ldi, %2, hhi8(%1)), operands);
6002 output_asm_insn (AS2 (mov, %D0, %2), operands);
6008 avr_output_bld (rtx operands[], int bit_nr)
6010 static char s[] = "bld %A0,0";
6012 s[5] = 'A' + (bit_nr >> 3);
6013 s[8] = '0' + (bit_nr & 7);
6014 output_asm_insn (s, operands);
6018 avr_output_addr_vec_elt (FILE *stream, int value)
6020 switch_to_section (progmem_section);
6021 if (AVR_HAVE_JMP_CALL)
6022 fprintf (stream, "\t.word gs(.L%d)\n", value);
6024 fprintf (stream, "\trjmp .L%d\n", value);
6027 /* Returns true if SCRATCH are safe to be allocated as a scratch
6028 registers (for a define_peephole2) in the current function. */
6031 avr_hard_regno_scratch_ok (unsigned int regno)
6033 /* Interrupt functions can only use registers that have already been saved
6034 by the prologue, even if they would normally be call-clobbered. */
6036 if ((cfun->machine->is_interrupt || cfun->machine->is_signal)
6037 && !df_regs_ever_live_p (regno))
6043 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6046 avr_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
6047 unsigned int new_reg)
6049 /* Interrupt functions can only use registers that have already been
6050 saved by the prologue, even if they would normally be
6053 if ((cfun->machine->is_interrupt || cfun->machine->is_signal)
6054 && !df_regs_ever_live_p (new_reg))
6060 /* Output a branch that tests a single bit of a register (QI, HI, SI or DImode)
6061 or memory location in the I/O space (QImode only).
6063 Operand 0: comparison operator (must be EQ or NE, compare bit to zero).
6064 Operand 1: register operand to test, or CONST_INT memory address.
6065 Operand 2: bit number.
6066 Operand 3: label to jump to if the test is true. */
6069 avr_out_sbxx_branch (rtx insn, rtx operands[])
6071 enum rtx_code comp = GET_CODE (operands[0]);
6072 int long_jump = (get_attr_length (insn) >= 4);
6073 int reverse = long_jump || jump_over_one_insn_p (insn, operands[3]);
6077 else if (comp == LT)
6081 comp = reverse_condition (comp);
6083 if (GET_CODE (operands[1]) == CONST_INT)
6085 if (INTVAL (operands[1]) < 0x40)
6088 output_asm_insn (AS2 (sbis,%m1-0x20,%2), operands);
6090 output_asm_insn (AS2 (sbic,%m1-0x20,%2), operands);
6094 output_asm_insn (AS2 (in,__tmp_reg__,%m1-0x20), operands);
6096 output_asm_insn (AS2 (sbrs,__tmp_reg__,%2), operands);
6098 output_asm_insn (AS2 (sbrc,__tmp_reg__,%2), operands);
6101 else /* GET_CODE (operands[1]) == REG */
6103 if (GET_MODE (operands[1]) == QImode)
6106 output_asm_insn (AS2 (sbrs,%1,%2), operands);
6108 output_asm_insn (AS2 (sbrc,%1,%2), operands);
6110 else /* HImode or SImode */
6112 static char buf[] = "sbrc %A1,0";
6113 int bit_nr = INTVAL (operands[2]);
6114 buf[3] = (comp == EQ) ? 's' : 'c';
6115 buf[6] = 'A' + (bit_nr >> 3);
6116 buf[9] = '0' + (bit_nr & 7);
6117 output_asm_insn (buf, operands);
6122 return (AS1 (rjmp,.+4) CR_TAB
6125 return AS1 (rjmp,%x3);
6129 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
6132 avr_asm_out_ctor (rtx symbol, int priority)
6134 fputs ("\t.global __do_global_ctors\n", asm_out_file);
6135 default_ctor_section_asm_out_constructor (symbol, priority);
6138 /* Worker function for TARGET_ASM_DESTRUCTOR. */
6141 avr_asm_out_dtor (rtx symbol, int priority)
6143 fputs ("\t.global __do_global_dtors\n", asm_out_file);
6144 default_dtor_section_asm_out_destructor (symbol, priority);
6147 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6150 avr_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6152 if (TYPE_MODE (type) == BLKmode)
6154 HOST_WIDE_INT size = int_size_in_bytes (type);
6155 return (size == -1 || size > 8);
6161 /* Worker function for CASE_VALUES_THRESHOLD. */
6163 unsigned int avr_case_values_threshold (void)
6165 return (!AVR_HAVE_JMP_CALL || TARGET_CALL_PROLOGUES) ? 8 : 17;