1 /* Subroutines for insn-output.c for ATMEL AVR micro controllers
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004
3 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov (denisc@overta.ru)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Maximal allowed offset for an address in the LD command */
49 #define MAX_LD_OFFSET(MODE) (64 - (signed)GET_MODE_SIZE (MODE))
51 static int avr_naked_function_p (tree);
52 static int interrupt_function_p (tree);
53 static int signal_function_p (tree);
54 static int avr_regs_to_save (HARD_REG_SET *);
55 static int sequent_regs_live (void);
56 static const char *ptrreg_to_str (int);
57 static const char *cond_string (enum rtx_code);
58 static int avr_num_arg_regs (enum machine_mode, tree);
59 static int out_adj_frame_ptr (FILE *, int);
60 static int out_set_stack_ptr (FILE *, int, int);
61 static RTX_CODE compare_condition (rtx insn);
62 static int compare_sign_p (rtx insn);
63 static tree avr_handle_progmem_attribute (tree *, tree, tree, int, bool *);
64 static tree avr_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
65 const struct attribute_spec avr_attribute_table[];
66 static bool avr_assemble_integer (rtx, unsigned int, int);
67 static void avr_file_start (void);
68 static void avr_file_end (void);
69 static void avr_output_function_prologue (FILE *, HOST_WIDE_INT);
70 static void avr_output_function_epilogue (FILE *, HOST_WIDE_INT);
71 static void avr_unique_section (tree, int);
72 static void avr_insert_attributes (tree, tree *);
73 static unsigned int avr_section_type_flags (tree, const char *, int);
75 static void avr_reorg (void);
76 static void avr_asm_out_ctor (rtx, int);
77 static void avr_asm_out_dtor (rtx, int);
78 static int default_rtx_costs (rtx, enum rtx_code, enum rtx_code);
79 static bool avr_rtx_costs (rtx, int, int, int *);
80 static int avr_address_cost (rtx);
81 static bool avr_return_in_memory (tree, tree);
83 /* Allocate registers from r25 to r8 for parameters for function calls. */
84 #define FIRST_CUM_REG 26
86 /* Temporary register RTX (gen_rtx_REG (QImode, TMP_REGNO)) */
87 static GTY(()) rtx tmp_reg_rtx;
89 /* Zeroed register RTX (gen_rtx_REG (QImode, ZERO_REGNO)) */
90 static GTY(()) rtx zero_reg_rtx;
92 /* AVR register names {"r0", "r1", ..., "r31"} */
93 static const char *const avr_regnames[] = REGISTER_NAMES;
95 /* This holds the last insn address. */
96 static int last_insn_address = 0;
98 /* Commands count in the compiled file */
99 static int commands_in_file;
101 /* Commands in the functions prologues in the compiled file */
102 static int commands_in_prologues;
104 /* Commands in the functions epilogues in the compiled file */
105 static int commands_in_epilogues;
107 /* Prologue/Epilogue size in words */
108 static int prologue_size;
109 static int epilogue_size;
111 /* Size of all jump tables in the current function, in words. */
112 static int jump_tables_size;
114 /* Initial stack value specified by the `-minit-stack=' option */
115 const char *avr_init_stack = "__stack";
117 /* Default MCU name */
118 const char *avr_mcu_name = "avr2";
120 /* Preprocessor macros to define depending on MCU type. */
121 const char *avr_base_arch_macro;
122 const char *avr_extra_arch_macro;
124 /* More than 8K of program memory: use "call" and "jmp". */
127 /* Enhanced core: use "movw", "mul", ... */
128 int avr_enhanced_p = 0;
130 /* Assembler only. */
131 int avr_asm_only_p = 0;
137 const char *const macro;
140 static const struct base_arch_s avr_arch_types[] = {
141 { 1, 0, 0, NULL }, /* unknown device specified */
142 { 1, 0, 0, "__AVR_ARCH__=1" },
143 { 0, 0, 0, "__AVR_ARCH__=2" },
144 { 0, 0, 1, "__AVR_ARCH__=3" },
145 { 0, 1, 0, "__AVR_ARCH__=4" },
146 { 0, 1, 1, "__AVR_ARCH__=5" }
150 const char *const name;
151 int arch; /* index in avr_arch_types[] */
152 /* Must lie outside user's namespace. NULL == no macro. */
153 const char *const macro;
156 /* List of all known AVR MCU types - if updated, it has to be kept
157 in sync in several places (FIXME: is there a better way?):
159 - avr.h (CPP_SPEC, LINK_SPEC, CRT_BINUTILS_SPECS)
160 - t-avr (MULTILIB_MATCHES)
161 - gas/config/tc-avr.c
164 static const struct mcu_type_s avr_mcu_types[] = {
165 /* Classic, <= 8K. */
167 { "at90s2313", 2, "__AVR_AT90S2313__" },
168 { "at90s2323", 2, "__AVR_AT90S2323__" },
169 { "at90s2333", 2, "__AVR_AT90S2333__" },
170 { "at90s2343", 2, "__AVR_AT90S2343__" },
171 { "attiny22", 2, "__AVR_ATtiny22__" },
172 { "attiny26", 2, "__AVR_ATtiny26__" },
173 { "at90s4414", 2, "__AVR_AT90S4414__" },
174 { "at90s4433", 2, "__AVR_AT90S4433__" },
175 { "at90s4434", 2, "__AVR_AT90S4434__" },
176 { "at90s8515", 2, "__AVR_AT90S8515__" },
177 { "at90c8534", 2, "__AVR_AT90C8534__" },
178 { "at90s8535", 2, "__AVR_AT90S8535__" },
179 { "at86rf401", 2, "__AVR_AT86RF401__" },
182 { "atmega103", 3, "__AVR_ATmega103__" },
183 { "atmega603", 3, "__AVR_ATmega603__" },
184 { "at43usb320", 3, "__AVR_AT43USB320__" },
185 { "at43usb355", 3, "__AVR_AT43USB355__" },
186 { "at76c711", 3, "__AVR_AT76C711__" },
187 /* Enhanced, <= 8K. */
189 { "atmega8", 4, "__AVR_ATmega8__" },
190 { "atmega8515", 4, "__AVR_ATmega8515__" },
191 { "atmega8535", 4, "__AVR_ATmega8535__" },
192 /* Enhanced, > 8K. */
194 { "atmega16", 5, "__AVR_ATmega16__" },
195 { "atmega161", 5, "__AVR_ATmega161__" },
196 { "atmega162", 5, "__AVR_ATmega162__" },
197 { "atmega163", 5, "__AVR_ATmega163__" },
198 { "atmega169", 5, "__AVR_ATmega169__" },
199 { "atmega32", 5, "__AVR_ATmega32__" },
200 { "atmega323", 5, "__AVR_ATmega323__" },
201 { "atmega64", 5, "__AVR_ATmega64__" },
202 { "atmega128", 5, "__AVR_ATmega128__" },
203 { "at94k", 5, "__AVR_AT94K__" },
204 /* Assembler only. */
206 { "at90s1200", 1, "__AVR_AT90S1200__" },
207 { "attiny11", 1, "__AVR_ATtiny11__" },
208 { "attiny12", 1, "__AVR_ATtiny12__" },
209 { "attiny15", 1, "__AVR_ATtiny15__" },
210 { "attiny28", 1, "__AVR_ATtiny28__" },
214 int avr_case_values_threshold = 30000;
216 /* Initialize the GCC target structure. */
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
219 #undef TARGET_ASM_INTEGER
220 #define TARGET_ASM_INTEGER avr_assemble_integer
221 #undef TARGET_ASM_FILE_START
222 #define TARGET_ASM_FILE_START avr_file_start
223 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
224 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END avr_file_end
228 #undef TARGET_ASM_FUNCTION_PROLOGUE
229 #define TARGET_ASM_FUNCTION_PROLOGUE avr_output_function_prologue
230 #undef TARGET_ASM_FUNCTION_EPILOGUE
231 #define TARGET_ASM_FUNCTION_EPILOGUE avr_output_function_epilogue
232 #undef TARGET_ATTRIBUTE_TABLE
233 #define TARGET_ATTRIBUTE_TABLE avr_attribute_table
234 #undef TARGET_ASM_UNIQUE_SECTION
235 #define TARGET_ASM_UNIQUE_SECTION avr_unique_section
236 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
237 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
238 #undef TARGET_INSERT_ATTRIBUTES
239 #define TARGET_INSERT_ATTRIBUTES avr_insert_attributes
240 #undef TARGET_SECTION_TYPE_FLAGS
241 #define TARGET_SECTION_TYPE_FLAGS avr_section_type_flags
242 #undef TARGET_RTX_COSTS
243 #define TARGET_RTX_COSTS avr_rtx_costs
244 #undef TARGET_ADDRESS_COST
245 #define TARGET_ADDRESS_COST avr_address_cost
246 #undef TARGET_MACHINE_DEPENDENT_REORG
247 #define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
249 #undef TARGET_RETURN_IN_MEMORY
250 #define TARGET_RETURN_IN_MEMORY avr_return_in_memory
252 #undef TARGET_STRICT_ARGUMENT_NAMING
253 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
255 struct gcc_target targetm = TARGET_INITIALIZER;
258 avr_override_options (void)
260 const struct mcu_type_s *t;
261 const struct base_arch_s *base;
263 for (t = avr_mcu_types; t->name; t++)
264 if (strcmp (t->name, avr_mcu_name) == 0)
269 fprintf (stderr, "unknown MCU `%s' specified\nKnown MCU names:\n",
271 for (t = avr_mcu_types; t->name; t++)
272 fprintf (stderr," %s\n", t->name);
275 base = &avr_arch_types[t->arch];
276 avr_asm_only_p = base->asm_only;
277 avr_enhanced_p = base->enhanced;
278 avr_mega_p = base->mega;
279 avr_base_arch_macro = base->macro;
280 avr_extra_arch_macro = t->macro;
282 if (optimize && !TARGET_NO_TABLEJUMP)
283 avr_case_values_threshold = (!AVR_MEGA || TARGET_CALL_PROLOGUES) ? 8 : 17;
285 tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
286 zero_reg_rtx = gen_rtx_REG (QImode, ZERO_REGNO);
289 /* return register class from register number. */
291 static const int reg_class_tab[]={
292 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
293 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
294 GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,GENERAL_REGS,
295 GENERAL_REGS, /* r0 - r15 */
296 LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,LD_REGS,
297 LD_REGS, /* r16 - 23 */
298 ADDW_REGS,ADDW_REGS, /* r24,r25 */
299 POINTER_X_REGS,POINTER_X_REGS, /* r26,27 */
300 POINTER_Y_REGS,POINTER_Y_REGS, /* r28,r29 */
301 POINTER_Z_REGS,POINTER_Z_REGS, /* r30,r31 */
302 STACK_REG,STACK_REG /* SPL,SPH */
305 /* Return register class for register R. */
308 avr_regno_reg_class (int r)
311 return reg_class_tab[r];
316 /* A C expression which defines the machine-dependent operand
317 constraint letters for register classes. If C is such a
318 letter, the value should be the register class corresponding to
319 it. Otherwise, the value should be `NO_REGS'. The register
320 letter `r', corresponding to class `GENERAL_REGS', will not be
321 passed to this macro; you do not need to handle it. */
324 avr_reg_class_from_letter (int c)
328 case 't' : return R0_REG;
329 case 'b' : return BASE_POINTER_REGS;
330 case 'e' : return POINTER_REGS;
331 case 'w' : return ADDW_REGS;
332 case 'd' : return LD_REGS;
333 case 'l' : return NO_LD_REGS;
334 case 'a' : return SIMPLE_LD_REGS;
335 case 'x' : return POINTER_X_REGS;
336 case 'y' : return POINTER_Y_REGS;
337 case 'z' : return POINTER_Z_REGS;
338 case 'q' : return STACK_REG;
344 /* Return nonzero if FUNC is a naked function. */
347 avr_naked_function_p (tree func)
351 if (TREE_CODE (func) != FUNCTION_DECL)
354 a = lookup_attribute ("naked", DECL_ATTRIBUTES (func));
355 return a != NULL_TREE;
358 /* Return nonzero if FUNC is an interrupt function as specified
359 by the "interrupt" attribute. */
362 interrupt_function_p (tree func)
366 if (TREE_CODE (func) != FUNCTION_DECL)
369 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
370 return a != NULL_TREE;
373 /* Return nonzero if FUNC is a signal function as specified
374 by the "signal" attribute. */
377 signal_function_p (tree func)
381 if (TREE_CODE (func) != FUNCTION_DECL)
384 a = lookup_attribute ("signal", DECL_ATTRIBUTES (func));
385 return a != NULL_TREE;
388 /* Return the number of hard registers to push/pop in the prologue/epilogue
389 of the current function, and optionally store these registers in SET. */
392 avr_regs_to_save (HARD_REG_SET *set)
395 int int_or_sig_p = (interrupt_function_p (current_function_decl)
396 || signal_function_p (current_function_decl));
397 int leaf_func_p = leaf_function_p ();
400 CLEAR_HARD_REG_SET (*set);
403 /* No need to save any registers if the function never returns. */
404 if (TREE_THIS_VOLATILE (current_function_decl))
407 for (reg = 0; reg < 32; reg++)
409 /* Do not push/pop __tmp_reg__, __zero_reg__, as well as
410 any global register variables. */
414 if ((int_or_sig_p && !leaf_func_p && call_used_regs[reg])
415 || (regs_ever_live[reg]
416 && (int_or_sig_p || !call_used_regs[reg])
417 && !(frame_pointer_needed
418 && (reg == REG_Y || reg == (REG_Y+1)))))
421 SET_HARD_REG_BIT (*set, reg);
428 /* Compute offset between arg_pointer and frame_pointer. */
431 initial_elimination_offset (int from, int to)
433 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
437 int offset = frame_pointer_needed ? 2 : 0;
439 offset += avr_regs_to_save (NULL);
440 return get_frame_size () + 2 + 1 + offset;
444 /* Return 1 if the function epilogue is just a single "ret". */
447 avr_simple_epilogue (void)
449 return (! frame_pointer_needed
450 && get_frame_size () == 0
451 && avr_regs_to_save (NULL) == 0
452 && ! interrupt_function_p (current_function_decl)
453 && ! signal_function_p (current_function_decl)
454 && ! avr_naked_function_p (current_function_decl)
455 && ! MAIN_NAME_P (DECL_NAME (current_function_decl))
456 && ! TREE_THIS_VOLATILE (current_function_decl));
459 /* This function checks sequence of live registers. */
462 sequent_regs_live (void)
468 for (reg = 0; reg < 18; ++reg)
470 if (!call_used_regs[reg])
472 if (regs_ever_live[reg])
482 if (!frame_pointer_needed)
484 if (regs_ever_live[REG_Y])
492 if (regs_ever_live[REG_Y+1])
505 return (cur_seq == live_seq) ? live_seq : 0;
509 /* Output to FILE the asm instructions to adjust the frame pointer by
510 ADJ (r29:r28 -= ADJ;) which can be positive (prologue) or negative
511 (epilogue). Returns the number of instructions generated. */
514 out_adj_frame_ptr (FILE *file, int adj)
520 if (TARGET_TINY_STACK)
522 if (adj < -63 || adj > 63)
523 warning ("large frame pointer change (%d) with -mtiny-stack", adj);
525 /* The high byte (r29) doesn't change - prefer "subi" (1 cycle)
526 over "sbiw" (2 cycles, same size). */
528 fprintf (file, (AS2 (subi, r28, %d) CR_TAB), adj);
531 else if (adj < -63 || adj > 63)
533 fprintf (file, (AS2 (subi, r28, lo8(%d)) CR_TAB
534 AS2 (sbci, r29, hi8(%d)) CR_TAB),
540 fprintf (file, (AS2 (adiw, r28, %d) CR_TAB), -adj);
545 fprintf (file, (AS2 (sbiw, r28, %d) CR_TAB), adj);
553 /* Output to FILE the asm instructions to copy r29:r28 to SPH:SPL,
554 handling various cases of interrupt enable flag state BEFORE and AFTER
555 (0=disabled, 1=enabled, -1=unknown/unchanged) and target_flags.
556 Returns the number of instructions generated. */
559 out_set_stack_ptr (FILE *file, int before, int after)
561 int do_sph, do_cli, do_save, do_sei, lock_sph, size;
563 /* The logic here is so that -mno-interrupts actually means
564 "it is safe to write SPH in one instruction, then SPL in the
565 next instruction, without disabling interrupts first".
566 The after != -1 case (interrupt/signal) is not affected. */
568 do_sph = !TARGET_TINY_STACK;
569 lock_sph = do_sph && !TARGET_NO_INTERRUPTS;
570 do_cli = (before != 0 && (after == 0 || lock_sph));
571 do_save = (do_cli && before == -1 && after == -1);
572 do_sei = ((do_cli || before != 1) && after == 1);
577 fprintf (file, AS2 (in, __tmp_reg__, __SREG__) CR_TAB);
583 fprintf (file, "cli" CR_TAB);
587 /* Do SPH first - maybe this will disable interrupts for one instruction
588 someday (a suggestion has been sent to avr@atmel.com for consideration
589 in future devices - that would make -mno-interrupts always safe). */
592 fprintf (file, AS2 (out, __SP_H__, r29) CR_TAB);
596 /* Set/restore the I flag now - interrupts will be really enabled only
597 after the next instruction. This is not clearly documented, but
598 believed to be true for all AVR devices. */
601 fprintf (file, AS2 (out, __SREG__, __tmp_reg__) CR_TAB);
606 fprintf (file, "sei" CR_TAB);
610 fprintf (file, AS2 (out, __SP_L__, r28) "\n");
616 /* Output function prologue. */
619 avr_output_function_prologue (FILE *file, HOST_WIDE_INT size)
622 int interrupt_func_p;
628 last_insn_address = 0;
629 jump_tables_size = 0;
631 fprintf (file, "/* prologue: frame size=" HOST_WIDE_INT_PRINT_DEC " */\n",
634 if (avr_naked_function_p (current_function_decl))
636 fputs ("/* prologue: naked */\n", file);
640 interrupt_func_p = interrupt_function_p (current_function_decl);
641 signal_func_p = signal_function_p (current_function_decl);
642 main_p = MAIN_NAME_P (DECL_NAME (current_function_decl));
643 live_seq = sequent_regs_live ();
644 minimize = (TARGET_CALL_PROLOGUES
645 && !interrupt_func_p && !signal_func_p && live_seq);
647 if (interrupt_func_p)
649 fprintf (file,"\tsei\n");
652 if (interrupt_func_p || signal_func_p)
655 AS1 (push,__zero_reg__) CR_TAB
656 AS1 (push,__tmp_reg__) CR_TAB
657 AS2 (in,__tmp_reg__,__SREG__) CR_TAB
658 AS1 (push,__tmp_reg__) CR_TAB
659 AS1 (clr,__zero_reg__) "\n");
665 AS1 (ldi,r28) ",lo8(%s - " HOST_WIDE_INT_PRINT_DEC ")" CR_TAB
666 AS1 (ldi,r29) ",hi8(%s - " HOST_WIDE_INT_PRINT_DEC ")" CR_TAB
667 AS2 (out,__SP_H__,r29) CR_TAB
668 AS2 (out,__SP_L__,r28) "\n"),
669 avr_init_stack, size, avr_init_stack, size);
673 else if (minimize && (frame_pointer_needed || live_seq > 6))
675 const char *cfun_name = current_function_name ();
677 AS1 (ldi, r26) ",lo8(" HOST_WIDE_INT_PRINT_DEC ")" CR_TAB
678 AS1 (ldi, r27) ",hi8(" HOST_WIDE_INT_PRINT_DEC ")" CR_TAB), size, size);
680 fprintf (file, (AS2 (ldi, r30, pm_lo8(.L_%s_body)) CR_TAB
681 AS2 (ldi, r31, pm_hi8(.L_%s_body)) CR_TAB),
682 cfun_name, cfun_name);
688 fprintf (file, AS1 (jmp,__prologue_saves__+%d) "\n",
689 (18 - live_seq) * 2);
694 fprintf (file, AS1 (rjmp,__prologue_saves__+%d) "\n",
695 (18 - live_seq) * 2);
698 fprintf (file, ".L_%s_body:\n", cfun_name);
704 prologue_size += avr_regs_to_save (&set);
705 for (reg = 0; reg < 32; ++reg)
707 if (TEST_HARD_REG_BIT (set, reg))
709 fprintf (file, "\t" AS1 (push,%s) "\n", avr_regnames[reg]);
712 if (frame_pointer_needed)
715 AS1 (push,r28) CR_TAB
716 AS1 (push,r29) CR_TAB
717 AS2 (in,r28,__SP_L__) CR_TAB
718 AS2 (in,r29,__SP_H__) "\n");
723 prologue_size += out_adj_frame_ptr (file, size);
725 if (interrupt_func_p)
727 prologue_size += out_set_stack_ptr (file, 1, 1);
729 else if (signal_func_p)
731 prologue_size += out_set_stack_ptr (file, 0, 0);
735 prologue_size += out_set_stack_ptr (file, -1, -1);
742 fprintf (file, "/* prologue end (size=%d) */\n", prologue_size);
745 /* Output function epilogue. */
748 avr_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
751 int interrupt_func_p;
757 rtx last = get_last_nonnote_insn ();
759 function_size = jump_tables_size;
762 rtx first = get_first_nonnote_insn ();
763 function_size += (INSN_ADDRESSES (INSN_UID (last)) -
764 INSN_ADDRESSES (INSN_UID (first)));
765 function_size += get_attr_length (last);
768 fprintf (file, "/* epilogue: frame size=" HOST_WIDE_INT_PRINT_DEC " */\n", size);
771 if (avr_naked_function_p (current_function_decl))
773 fputs ("/* epilogue: naked */\n", file);
777 if (last && GET_CODE (last) == BARRIER)
779 fputs ("/* epilogue: noreturn */\n", file);
783 interrupt_func_p = interrupt_function_p (current_function_decl);
784 signal_func_p = signal_function_p (current_function_decl);
785 main_p = MAIN_NAME_P (DECL_NAME (current_function_decl));
786 live_seq = sequent_regs_live ();
787 minimize = (TARGET_CALL_PROLOGUES
788 && !interrupt_func_p && !signal_func_p && live_seq);
792 /* Return value from main() is already in the correct registers
793 (r25:r24) as the exit() argument. */
796 fputs ("\t" AS1 (jmp,exit) "\n", file);
801 fputs ("\t" AS1 (rjmp,exit) "\n", file);
805 else if (minimize && (frame_pointer_needed || live_seq > 4))
807 fprintf (file, ("\t" AS2 (ldi, r30, %d) CR_TAB), live_seq);
809 if (frame_pointer_needed)
811 epilogue_size += out_adj_frame_ptr (file, -size);
815 fprintf (file, (AS2 (in , r28, __SP_L__) CR_TAB
816 AS2 (in , r29, __SP_H__) CR_TAB));
822 fprintf (file, AS1 (jmp,__epilogue_restores__+%d) "\n",
823 (18 - live_seq) * 2);
828 fprintf (file, AS1 (rjmp,__epilogue_restores__+%d) "\n",
829 (18 - live_seq) * 2);
837 if (frame_pointer_needed)
842 epilogue_size += out_adj_frame_ptr (file, -size);
844 if (interrupt_func_p || signal_func_p)
846 epilogue_size += out_set_stack_ptr (file, -1, 0);
850 epilogue_size += out_set_stack_ptr (file, -1, -1);
859 epilogue_size += avr_regs_to_save (&set);
860 for (reg = 31; reg >= 0; --reg)
862 if (TEST_HARD_REG_BIT (set, reg))
864 fprintf (file, "\t" AS1 (pop,%s) "\n", avr_regnames[reg]);
868 if (interrupt_func_p || signal_func_p)
871 AS1 (pop,__tmp_reg__) CR_TAB
872 AS2 (out,__SREG__,__tmp_reg__) CR_TAB
873 AS1 (pop,__tmp_reg__) CR_TAB
874 AS1 (pop,__zero_reg__) "\n");
876 fprintf (file, "\treti\n");
879 fprintf (file, "\tret\n");
884 fprintf (file, "/* epilogue end (size=%d) */\n", epilogue_size);
885 fprintf (file, "/* function %s size %d (%d) */\n", current_function_name (),
886 prologue_size + function_size + epilogue_size, function_size);
887 commands_in_file += prologue_size + function_size + epilogue_size;
888 commands_in_prologues += prologue_size;
889 commands_in_epilogues += epilogue_size;
893 /* Return nonzero if X (an RTX) is a legitimate memory address on the target
894 machine for a memory operand of mode MODE. */
897 legitimate_address_p (enum machine_mode mode, rtx x, int strict)
899 enum reg_class r = NO_REGS;
901 if (TARGET_ALL_DEBUG)
903 fprintf (stderr, "mode: (%s) %s %s %s %s:",
905 strict ? "(strict)": "",
906 reload_completed ? "(reload_completed)": "",
907 reload_in_progress ? "(reload_in_progress)": "",
908 reg_renumber ? "(reg_renumber)" : "");
909 if (GET_CODE (x) == PLUS
910 && REG_P (XEXP (x, 0))
911 && GET_CODE (XEXP (x, 1)) == CONST_INT
912 && INTVAL (XEXP (x, 1)) >= 0
913 && INTVAL (XEXP (x, 1)) <= MAX_LD_OFFSET (mode)
916 fprintf (stderr, "(r%d ---> r%d)", REGNO (XEXP (x, 0)),
917 true_regnum (XEXP (x, 0)));
920 if (REG_P (x) && (strict ? REG_OK_FOR_BASE_STRICT_P (x)
921 : REG_OK_FOR_BASE_NOSTRICT_P (x)))
923 else if (CONSTANT_ADDRESS_P (x))
925 else if (GET_CODE (x) == PLUS
926 && REG_P (XEXP (x, 0))
927 && GET_CODE (XEXP (x, 1)) == CONST_INT
928 && INTVAL (XEXP (x, 1)) >= 0)
930 int fit = INTVAL (XEXP (x, 1)) <= MAX_LD_OFFSET (mode);
934 || REGNO (XEXP (x,0)) == REG_Y
935 || REGNO (XEXP (x,0)) == REG_Z)
936 r = BASE_POINTER_REGS;
937 if (XEXP (x,0) == frame_pointer_rtx
938 || XEXP (x,0) == arg_pointer_rtx)
939 r = BASE_POINTER_REGS;
941 else if (frame_pointer_needed && XEXP (x,0) == frame_pointer_rtx)
944 else if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
945 && REG_P (XEXP (x, 0))
946 && (strict ? REG_OK_FOR_BASE_STRICT_P (XEXP (x, 0))
947 : REG_OK_FOR_BASE_NOSTRICT_P (XEXP (x, 0))))
951 if (TARGET_ALL_DEBUG)
953 fprintf (stderr, " ret = %c\n", r);
955 return r == NO_REGS ? 0 : (int)r;
958 /* Attempts to replace X with a valid
959 memory address for an operand of mode MODE */
962 legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
965 if (TARGET_ALL_DEBUG)
967 fprintf (stderr, "legitimize_address mode: %s", GET_MODE_NAME(mode));
971 if (GET_CODE (oldx) == PLUS
972 && REG_P (XEXP (oldx,0)))
974 if (REG_P (XEXP (oldx,1)))
975 x = force_reg (GET_MODE (oldx), oldx);
976 else if (GET_CODE (XEXP (oldx, 1)) == CONST_INT)
978 int offs = INTVAL (XEXP (oldx,1));
979 if (frame_pointer_rtx != XEXP (oldx,0))
980 if (offs > MAX_LD_OFFSET (mode))
982 if (TARGET_ALL_DEBUG)
983 fprintf (stderr, "force_reg (big offset)\n");
984 x = force_reg (GET_MODE (oldx), oldx);
992 /* Return a pointer register name as a string. */
995 ptrreg_to_str (int regno)
999 case REG_X: return "X";
1000 case REG_Y: return "Y";
1001 case REG_Z: return "Z";
1008 /* Return the condition name as a string.
1009 Used in conditional jump constructing */
1012 cond_string (enum rtx_code code)
1021 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1026 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1039 /* Output ADDR to FILE as address. */
1042 print_operand_address (FILE *file, rtx addr)
1044 switch (GET_CODE (addr))
1047 fprintf (file, ptrreg_to_str (REGNO (addr)));
1051 fprintf (file, "-%s", ptrreg_to_str (REGNO (XEXP (addr, 0))));
1055 fprintf (file, "%s+", ptrreg_to_str (REGNO (XEXP (addr, 0))));
1059 if (CONSTANT_ADDRESS_P (addr)
1060 && ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (addr))
1061 || GET_CODE (addr) == LABEL_REF))
1063 fprintf (file, "pm(");
1064 output_addr_const (file,addr);
1065 fprintf (file ,")");
1068 output_addr_const (file, addr);
1073 /* Output X as assembler operand to file FILE. */
1076 print_operand (FILE *file, rtx x, int code)
1080 if (code >= 'A' && code <= 'D')
1090 if (x == zero_reg_rtx)
1091 fprintf (file, "__zero_reg__");
1093 fprintf (file, reg_names[true_regnum (x) + abcd]);
1095 else if (GET_CODE (x) == CONST_INT)
1096 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) + abcd);
1097 else if (GET_CODE (x) == MEM)
1099 rtx addr = XEXP (x,0);
1101 if (CONSTANT_P (addr) && abcd)
1104 output_address (addr);
1105 fprintf (file, ")+%d", abcd);
1107 else if (code == 'o')
1109 if (GET_CODE (addr) != PLUS)
1110 fatal_insn ("bad address, not (reg+disp):", addr);
1112 print_operand (file, XEXP (addr, 1), 0);
1114 else if (GET_CODE (addr) == PLUS)
1116 print_operand_address (file, XEXP (addr,0));
1117 if (REGNO (XEXP (addr, 0)) == REG_X)
1118 fatal_insn ("internal compiler error. Bad address:"
1121 print_operand (file, XEXP (addr,1), code);
1124 print_operand_address (file, addr);
1126 else if (GET_CODE (x) == CONST_DOUBLE)
1130 if (GET_MODE (x) != SFmode)
1131 fatal_insn ("internal compiler error. Unknown mode:", x);
1132 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1133 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1134 fprintf (file, "0x%lx", val);
1136 else if (code == 'j')
1137 fputs (cond_string (GET_CODE (x)), file);
1138 else if (code == 'k')
1139 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1141 print_operand_address (file, x);
1144 /* Recognize operand OP of mode MODE used in call instructions. */
1147 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1149 if (GET_CODE (op) == MEM)
1151 rtx inside = XEXP (op, 0);
1152 if (register_operand (inside, Pmode))
1154 if (CONSTANT_ADDRESS_P (inside))
1160 /* Update the condition code in the INSN. */
1163 notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
1167 switch (get_attr_cc (insn))
1170 /* Insn does not affect CC at all. */
1178 set = single_set (insn);
1182 cc_status.flags |= CC_NO_OVERFLOW;
1183 cc_status.value1 = SET_DEST (set);
1188 /* Insn sets the Z,N,C flags of CC to recog_operand[0].
1189 The V flag may or may not be known but that's ok because
1190 alter_cond will change tests to use EQ/NE. */
1191 set = single_set (insn);
1195 cc_status.value1 = SET_DEST (set);
1196 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
1201 set = single_set (insn);
1204 cc_status.value1 = SET_SRC (set);
1208 /* Insn doesn't leave CC in a usable state. */
1211 /* Correct CC for the ashrqi3 with the shift count as CONST_INT != 6 */
1212 set = single_set (insn);
1215 rtx src = SET_SRC (set);
1217 if (GET_CODE (src) == ASHIFTRT
1218 && GET_MODE (src) == QImode)
1220 rtx x = XEXP (src, 1);
1222 if (GET_CODE (x) == CONST_INT
1225 cc_status.value1 = SET_DEST (set);
1226 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
1234 /* Return maximum number of consecutive registers of
1235 class CLASS needed to hold a value of mode MODE. */
1238 class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,enum machine_mode mode)
1240 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1243 /* Choose mode for jump insn:
1244 1 - relative jump in range -63 <= x <= 62 ;
1245 2 - relative jump in range -2046 <= x <= 2045 ;
1246 3 - absolute jump (only for ATmega[16]03). */
1249 avr_jump_mode (rtx x, rtx insn)
1251 int dest_addr = INSN_ADDRESSES (INSN_UID (GET_MODE (x) == LABEL_REF
1252 ? XEXP (x, 0) : x));
1253 int cur_addr = INSN_ADDRESSES (INSN_UID (insn));
1254 int jump_distance = cur_addr - dest_addr;
1256 if (-63 <= jump_distance && jump_distance <= 62)
1258 else if (-2046 <= jump_distance && jump_distance <= 2045)
1266 /* return an AVR condition jump commands.
1267 X is a comparison RTX.
1268 LEN is a number returned by avr_jump_mode function.
1269 if REVERSE nonzero then condition code in X must be reversed. */
1272 ret_cond_branch (rtx x, int len, int reverse)
1274 RTX_CODE cond = reverse ? reverse_condition (GET_CODE (x)) : GET_CODE (x);
1279 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1280 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1282 len == 2 ? (AS1 (breq,.+4) CR_TAB
1283 AS1 (brmi,.+2) CR_TAB
1285 (AS1 (breq,.+6) CR_TAB
1286 AS1 (brmi,.+4) CR_TAB
1290 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1292 len == 2 ? (AS1 (breq,.+4) CR_TAB
1293 AS1 (brlt,.+2) CR_TAB
1295 (AS1 (breq,.+6) CR_TAB
1296 AS1 (brlt,.+4) CR_TAB
1299 return (len == 1 ? (AS1 (breq,.+2) CR_TAB
1301 len == 2 ? (AS1 (breq,.+4) CR_TAB
1302 AS1 (brlo,.+2) CR_TAB
1304 (AS1 (breq,.+6) CR_TAB
1305 AS1 (brlo,.+4) CR_TAB
1308 if (cc_prev_status.flags & CC_OVERFLOW_UNUSABLE)
1309 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1311 len == 2 ? (AS1 (breq,.+2) CR_TAB
1312 AS1 (brpl,.+2) CR_TAB
1314 (AS1 (breq,.+2) CR_TAB
1315 AS1 (brpl,.+4) CR_TAB
1318 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1320 len == 2 ? (AS1 (breq,.+2) CR_TAB
1321 AS1 (brge,.+2) CR_TAB
1323 (AS1 (breq,.+2) CR_TAB
1324 AS1 (brge,.+4) CR_TAB
1327 return (len == 1 ? (AS1 (breq,%0) CR_TAB
1329 len == 2 ? (AS1 (breq,.+2) CR_TAB
1330 AS1 (brsh,.+2) CR_TAB
1332 (AS1 (breq,.+2) CR_TAB
1333 AS1 (brsh,.+4) CR_TAB
1341 return AS1 (br%k1,%0);
1343 return (AS1 (br%j1,.+2) CR_TAB
1346 return (AS1 (br%j1,.+4) CR_TAB
1355 return AS1 (br%j1,%0);
1357 return (AS1 (br%k1,.+2) CR_TAB
1360 return (AS1 (br%k1,.+4) CR_TAB
1368 /* Predicate function for immediate operand which fits to byte (8bit) */
1371 byte_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1373 return (GET_CODE (op) == CONST_INT
1374 && INTVAL (op) <= 0xff && INTVAL (op) >= 0);
1377 /* Output all insn addresses and their sizes into the assembly language
1378 output file. This is helpful for debugging whether the length attributes
1379 in the md file are correct.
1380 Output insn cost for next insn. */
1383 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1384 int num_operands ATTRIBUTE_UNUSED)
1386 int uid = INSN_UID (insn);
1388 if (TARGET_INSN_SIZE_DUMP || TARGET_ALL_DEBUG)
1390 fprintf (asm_out_file, "/*DEBUG: 0x%x\t\t%d\t%d */\n",
1391 INSN_ADDRESSES (uid),
1392 INSN_ADDRESSES (uid) - last_insn_address,
1393 rtx_cost (PATTERN (insn), INSN));
1395 last_insn_address = INSN_ADDRESSES (uid);
1398 /* Return 0 if undefined, 1 if always true or always false. */
1401 avr_simplify_comparison_p (enum machine_mode mode, RTX_CODE operator, rtx x)
1403 unsigned int max = (mode == QImode ? 0xff :
1404 mode == HImode ? 0xffff :
1405 mode == SImode ? 0xffffffff : 0);
1406 if (max && operator && GET_CODE (x) == CONST_INT)
1408 if (unsigned_condition (operator) != operator)
1411 if (max != (INTVAL (x) & max)
1412 && INTVAL (x) != 0xff)
1419 /* Returns nonzero if REGNO is the number of a hard
1420 register in which function arguments are sometimes passed. */
1423 function_arg_regno_p(int r)
1425 return (r >= 8 && r <= 25);
1428 /* Initializing the variable cum for the state at the beginning
1429 of the argument list. */
1432 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname,
1433 tree fndecl ATTRIBUTE_UNUSED)
1436 cum->regno = FIRST_CUM_REG;
1437 if (!libname && fntype)
1439 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
1440 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1441 != void_type_node));
1447 /* Returns the number of registers to allocate for a function argument. */
1450 avr_num_arg_regs (enum machine_mode mode, tree type)
1454 if (mode == BLKmode)
1455 size = int_size_in_bytes (type);
1457 size = GET_MODE_SIZE (mode);
1459 /* Align all function arguments to start in even-numbered registers.
1460 Odd-sized arguments leave holes above them. */
1462 return (size + 1) & ~1;
1465 /* Controls whether a function argument is passed
1466 in a register, and which register. */
1469 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1470 int named ATTRIBUTE_UNUSED)
1472 int bytes = avr_num_arg_regs (mode, type);
1474 if (cum->nregs && bytes <= cum->nregs)
1475 return gen_rtx_REG (mode, cum->regno - bytes);
1480 /* Update the summarizer variable CUM to advance past an argument
1481 in the argument list. */
1484 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1485 int named ATTRIBUTE_UNUSED)
1487 int bytes = avr_num_arg_regs (mode, type);
1489 cum->nregs -= bytes;
1490 cum->regno -= bytes;
1492 if (cum->nregs <= 0)
1495 cum->regno = FIRST_CUM_REG;
1499 /***********************************************************************
1500 Functions for outputting various mov's for a various modes
1501 ************************************************************************/
1503 output_movqi (rtx insn, rtx operands[], int *l)
1506 rtx dest = operands[0];
1507 rtx src = operands[1];
1515 if (register_operand (dest, QImode))
1517 if (register_operand (src, QImode)) /* mov r,r */
1519 if (test_hard_reg_class (STACK_REG, dest))
1520 return AS2 (out,%0,%1);
1521 else if (test_hard_reg_class (STACK_REG, src))
1522 return AS2 (in,%0,%1);
1524 return AS2 (mov,%0,%1);
1526 else if (CONSTANT_P (src))
1528 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
1529 return AS2 (ldi,%0,lo8(%1));
1531 if (GET_CODE (src) == CONST_INT)
1533 if (src == const0_rtx) /* mov r,L */
1534 return AS1 (clr,%0);
1535 else if (src == const1_rtx)
1538 return (AS1 (clr,%0) CR_TAB
1541 else if (src == constm1_rtx)
1543 /* Immediate constants -1 to any register */
1545 return (AS1 (clr,%0) CR_TAB
1550 int bit_nr = exact_log2 (INTVAL (src));
1556 output_asm_insn ((AS1 (clr,%0) CR_TAB
1559 avr_output_bld (operands, bit_nr);
1566 /* Last resort, larger than loading from memory. */
1568 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1569 AS2 (ldi,r31,lo8(%1)) CR_TAB
1570 AS2 (mov,%0,r31) CR_TAB
1571 AS2 (mov,r31,__tmp_reg__));
1573 else if (GET_CODE (src) == MEM)
1574 return out_movqi_r_mr (insn, operands, real_l); /* mov r,m */
1576 else if (GET_CODE (dest) == MEM)
1578 const char *template;
1580 if (src == const0_rtx)
1581 operands[1] = zero_reg_rtx;
1583 template = out_movqi_mr_r (insn, operands, real_l);
1586 output_asm_insn (template, operands);
1595 output_movhi (rtx insn, rtx operands[], int *l)
1598 rtx dest = operands[0];
1599 rtx src = operands[1];
1605 if (register_operand (dest, HImode))
1607 if (register_operand (src, HImode)) /* mov r,r */
1609 if (test_hard_reg_class (STACK_REG, dest))
1611 if (TARGET_TINY_STACK)
1614 return AS2 (out,__SP_L__,%A1);
1616 else if (TARGET_NO_INTERRUPTS)
1619 return (AS2 (out,__SP_H__,%B1) CR_TAB
1620 AS2 (out,__SP_L__,%A1));
1624 return (AS2 (in,__tmp_reg__,__SREG__) CR_TAB
1626 AS2 (out,__SP_H__,%B1) CR_TAB
1627 AS2 (out,__SREG__,__tmp_reg__) CR_TAB
1628 AS2 (out,__SP_L__,%A1));
1630 else if (test_hard_reg_class (STACK_REG, src))
1633 return (AS2 (in,%A0,__SP_L__) CR_TAB
1634 AS2 (in,%B0,__SP_H__));
1640 return (AS2 (movw,%0,%1));
1643 if (true_regnum (dest) > true_regnum (src))
1646 return (AS2 (mov,%B0,%B1) CR_TAB
1652 return (AS2 (mov,%A0,%A1) CR_TAB
1656 else if (CONSTANT_P (src))
1658 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
1661 return (AS2 (ldi,%A0,lo8(%1)) CR_TAB
1662 AS2 (ldi,%B0,hi8(%1)));
1665 if (GET_CODE (src) == CONST_INT)
1667 if (src == const0_rtx) /* mov r,L */
1670 return (AS1 (clr,%A0) CR_TAB
1673 else if (src == const1_rtx)
1676 return (AS1 (clr,%A0) CR_TAB
1677 AS1 (clr,%B0) CR_TAB
1680 else if (src == constm1_rtx)
1682 /* Immediate constants -1 to any register */
1684 return (AS1 (clr,%0) CR_TAB
1685 AS1 (dec,%A0) CR_TAB
1690 int bit_nr = exact_log2 (INTVAL (src));
1696 output_asm_insn ((AS1 (clr,%A0) CR_TAB
1697 AS1 (clr,%B0) CR_TAB
1700 avr_output_bld (operands, bit_nr);
1706 if ((INTVAL (src) & 0xff) == 0)
1709 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1710 AS1 (clr,%A0) CR_TAB
1711 AS2 (ldi,r31,hi8(%1)) CR_TAB
1712 AS2 (mov,%B0,r31) CR_TAB
1713 AS2 (mov,r31,__tmp_reg__));
1715 else if ((INTVAL (src) & 0xff00) == 0)
1718 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1719 AS2 (ldi,r31,lo8(%1)) CR_TAB
1720 AS2 (mov,%A0,r31) CR_TAB
1721 AS1 (clr,%B0) CR_TAB
1722 AS2 (mov,r31,__tmp_reg__));
1726 /* Last resort, equal to loading from memory. */
1728 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
1729 AS2 (ldi,r31,lo8(%1)) CR_TAB
1730 AS2 (mov,%A0,r31) CR_TAB
1731 AS2 (ldi,r31,hi8(%1)) CR_TAB
1732 AS2 (mov,%B0,r31) CR_TAB
1733 AS2 (mov,r31,__tmp_reg__));
1735 else if (GET_CODE (src) == MEM)
1736 return out_movhi_r_mr (insn, operands, real_l); /* mov r,m */
1738 else if (GET_CODE (dest) == MEM)
1740 const char *template;
1742 if (src == const0_rtx)
1743 operands[1] = zero_reg_rtx;
1745 template = out_movhi_mr_r (insn, operands, real_l);
1748 output_asm_insn (template, operands);
1753 fatal_insn ("invalid insn:", insn);
1758 out_movqi_r_mr (rtx insn, rtx op[], int *l)
1762 rtx x = XEXP (src, 0);
1768 if (CONSTANT_ADDRESS_P (x))
1770 if (avr_io_address_p (x, 1))
1773 return AS2 (in,%0,%1-0x20);
1776 return AS2 (lds,%0,%1);
1778 /* memory access by reg+disp */
1779 else if (GET_CODE (x) == PLUS
1780 && REG_P (XEXP (x,0))
1781 && GET_CODE (XEXP (x,1)) == CONST_INT)
1783 if ((INTVAL (XEXP (x,1)) - GET_MODE_SIZE (GET_MODE (src))) >= 63)
1785 int disp = INTVAL (XEXP (x,1));
1786 if (REGNO (XEXP (x,0)) != REG_Y)
1787 fatal_insn ("incorrect insn:",insn);
1789 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
1790 return *l = 3, (AS2 (adiw,r28,%o1-63) CR_TAB
1791 AS2 (ldd,%0,Y+63) CR_TAB
1792 AS2 (sbiw,r28,%o1-63));
1794 return *l = 5, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
1795 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
1796 AS2 (ld,%0,Y) CR_TAB
1797 AS2 (subi,r28,lo8(%o1)) CR_TAB
1798 AS2 (sbci,r29,hi8(%o1)));
1800 else if (REGNO (XEXP (x,0)) == REG_X)
1802 /* This is a paranoid case LEGITIMIZE_RELOAD_ADDRESS must exclude
1803 it but I have this situation with extremal optimizing options. */
1804 if (reg_overlap_mentioned_p (dest, XEXP (x,0))
1805 || reg_unused_after (insn, XEXP (x,0)))
1806 return *l = 2, (AS2 (adiw,r26,%o1) CR_TAB
1809 return *l = 3, (AS2 (adiw,r26,%o1) CR_TAB
1810 AS2 (ld,%0,X) CR_TAB
1811 AS2 (sbiw,r26,%o1));
1814 return AS2 (ldd,%0,%1);
1817 return AS2 (ld,%0,%1);
1821 out_movhi_r_mr (rtx insn, rtx op[], int *l)
1825 rtx base = XEXP (src, 0);
1826 int reg_dest = true_regnum (dest);
1827 int reg_base = true_regnum (base);
1835 if (reg_dest == reg_base) /* R = (R) */
1838 return (AS2 (ld,__tmp_reg__,%1+) CR_TAB
1839 AS2 (ld,%B0,%1) CR_TAB
1840 AS2 (mov,%A0,__tmp_reg__));
1842 else if (reg_base == REG_X) /* (R26) */
1844 if (reg_unused_after (insn, base))
1847 return (AS2 (ld,%A0,X+) CR_TAB
1851 return (AS2 (ld,%A0,X+) CR_TAB
1852 AS2 (ld,%B0,X) CR_TAB
1858 return (AS2 (ld,%A0,%1) CR_TAB
1859 AS2 (ldd,%B0,%1+1));
1862 else if (GET_CODE (base) == PLUS) /* (R + i) */
1864 int disp = INTVAL (XEXP (base, 1));
1865 int reg_base = true_regnum (XEXP (base, 0));
1867 if (disp > MAX_LD_OFFSET (GET_MODE (src)))
1869 if (REGNO (XEXP (base, 0)) != REG_Y)
1870 fatal_insn ("incorrect insn:",insn);
1872 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
1873 return *l = 4, (AS2 (adiw,r28,%o1-62) CR_TAB
1874 AS2 (ldd,%A0,Y+62) CR_TAB
1875 AS2 (ldd,%B0,Y+63) CR_TAB
1876 AS2 (sbiw,r28,%o1-62));
1878 return *l = 6, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
1879 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
1880 AS2 (ld,%A0,Y) CR_TAB
1881 AS2 (ldd,%B0,Y+1) CR_TAB
1882 AS2 (subi,r28,lo8(%o1)) CR_TAB
1883 AS2 (sbci,r29,hi8(%o1)));
1885 if (reg_base == REG_X)
1887 /* This is a paranoid case. LEGITIMIZE_RELOAD_ADDRESS must exclude
1888 it but I have this situation with extremal
1889 optimization options. */
1892 if (reg_base == reg_dest)
1893 return (AS2 (adiw,r26,%o1) CR_TAB
1894 AS2 (ld,__tmp_reg__,X+) CR_TAB
1895 AS2 (ld,%B0,X) CR_TAB
1896 AS2 (mov,%A0,__tmp_reg__));
1898 return (AS2 (adiw,r26,%o1) CR_TAB
1899 AS2 (ld,%A0,X+) CR_TAB
1900 AS2 (ld,%B0,X) CR_TAB
1901 AS2 (sbiw,r26,%o1+1));
1904 if (reg_base == reg_dest)
1907 return (AS2 (ldd,__tmp_reg__,%A1) CR_TAB
1908 AS2 (ldd,%B0,%B1) CR_TAB
1909 AS2 (mov,%A0,__tmp_reg__));
1913 return (AS2 (ldd,%A0,%A1) CR_TAB
1916 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
1918 if (reg_overlap_mentioned_p (dest, XEXP (base, 0)))
1919 fatal_insn ("incorrect insn:", insn);
1922 return (AS2 (ld,%B0,%1) CR_TAB
1925 else if (GET_CODE (base) == POST_INC) /* (R++) */
1927 if (reg_overlap_mentioned_p (dest, XEXP (base, 0)))
1928 fatal_insn ("incorrect insn:", insn);
1931 return (AS2 (ld,%A0,%1) CR_TAB
1934 else if (CONSTANT_ADDRESS_P (base))
1936 if (avr_io_address_p (base, 2))
1939 return (AS2 (in,%A0,%A1-0x20) CR_TAB
1940 AS2 (in,%B0,%B1-0x20));
1943 return (AS2 (lds,%A0,%A1) CR_TAB
1947 fatal_insn ("unknown move insn:",insn);
1952 out_movsi_r_mr (rtx insn, rtx op[], int *l)
1956 rtx base = XEXP (src, 0);
1957 int reg_dest = true_regnum (dest);
1958 int reg_base = true_regnum (base);
1966 if (reg_base == REG_X) /* (R26) */
1968 if (reg_dest == REG_X)
1969 /* "ld r26,-X" is undefined */
1970 return *l=7, (AS2 (adiw,r26,3) CR_TAB
1971 AS2 (ld,r29,X) CR_TAB
1972 AS2 (ld,r28,-X) CR_TAB
1973 AS2 (ld,__tmp_reg__,-X) CR_TAB
1974 AS2 (sbiw,r26,1) CR_TAB
1975 AS2 (ld,r26,X) CR_TAB
1976 AS2 (mov,r27,__tmp_reg__));
1977 else if (reg_dest == REG_X - 2)
1978 return *l=5, (AS2 (ld,%A0,X+) CR_TAB
1979 AS2 (ld,%B0,X+) CR_TAB
1980 AS2 (ld,__tmp_reg__,X+) CR_TAB
1981 AS2 (ld,%D0,X) CR_TAB
1982 AS2 (mov,%C0,__tmp_reg__));
1983 else if (reg_unused_after (insn, base))
1984 return *l=4, (AS2 (ld,%A0,X+) CR_TAB
1985 AS2 (ld,%B0,X+) CR_TAB
1986 AS2 (ld,%C0,X+) CR_TAB
1989 return *l=5, (AS2 (ld,%A0,X+) CR_TAB
1990 AS2 (ld,%B0,X+) CR_TAB
1991 AS2 (ld,%C0,X+) CR_TAB
1992 AS2 (ld,%D0,X) CR_TAB
1997 if (reg_dest == reg_base)
1998 return *l=5, (AS2 (ldd,%D0,%1+3) CR_TAB
1999 AS2 (ldd,%C0,%1+2) CR_TAB
2000 AS2 (ldd,__tmp_reg__,%1+1) CR_TAB
2001 AS2 (ld,%A0,%1) CR_TAB
2002 AS2 (mov,%B0,__tmp_reg__));
2003 else if (reg_base == reg_dest + 2)
2004 return *l=5, (AS2 (ld ,%A0,%1) CR_TAB
2005 AS2 (ldd,%B0,%1+1) CR_TAB
2006 AS2 (ldd,__tmp_reg__,%1+2) CR_TAB
2007 AS2 (ldd,%D0,%1+3) CR_TAB
2008 AS2 (mov,%C0,__tmp_reg__));
2010 return *l=4, (AS2 (ld ,%A0,%1) CR_TAB
2011 AS2 (ldd,%B0,%1+1) CR_TAB
2012 AS2 (ldd,%C0,%1+2) CR_TAB
2013 AS2 (ldd,%D0,%1+3));
2016 else if (GET_CODE (base) == PLUS) /* (R + i) */
2018 int disp = INTVAL (XEXP (base, 1));
2020 if (disp > MAX_LD_OFFSET (GET_MODE (src)))
2022 if (REGNO (XEXP (base, 0)) != REG_Y)
2023 fatal_insn ("incorrect insn:",insn);
2025 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (src)))
2026 return *l = 6, (AS2 (adiw,r28,%o1-60) CR_TAB
2027 AS2 (ldd,%A0,Y+60) CR_TAB
2028 AS2 (ldd,%B0,Y+61) CR_TAB
2029 AS2 (ldd,%C0,Y+62) CR_TAB
2030 AS2 (ldd,%D0,Y+63) CR_TAB
2031 AS2 (sbiw,r28,%o1-60));
2033 return *l = 8, (AS2 (subi,r28,lo8(-%o1)) CR_TAB
2034 AS2 (sbci,r29,hi8(-%o1)) CR_TAB
2035 AS2 (ld,%A0,Y) CR_TAB
2036 AS2 (ldd,%B0,Y+1) CR_TAB
2037 AS2 (ldd,%C0,Y+2) CR_TAB
2038 AS2 (ldd,%D0,Y+3) CR_TAB
2039 AS2 (subi,r28,lo8(%o1)) CR_TAB
2040 AS2 (sbci,r29,hi8(%o1)));
2043 reg_base = true_regnum (XEXP (base, 0));
2044 if (reg_base == REG_X)
2047 if (reg_dest == REG_X)
2050 /* "ld r26,-X" is undefined */
2051 return (AS2 (adiw,r26,%o1+3) CR_TAB
2052 AS2 (ld,r29,X) CR_TAB
2053 AS2 (ld,r28,-X) CR_TAB
2054 AS2 (ld,__tmp_reg__,-X) CR_TAB
2055 AS2 (sbiw,r26,1) CR_TAB
2056 AS2 (ld,r26,X) CR_TAB
2057 AS2 (mov,r27,__tmp_reg__));
2060 if (reg_dest == REG_X - 2)
2061 return (AS2 (adiw,r26,%o1) CR_TAB
2062 AS2 (ld,r24,X+) CR_TAB
2063 AS2 (ld,r25,X+) CR_TAB
2064 AS2 (ld,__tmp_reg__,X+) CR_TAB
2065 AS2 (ld,r27,X) CR_TAB
2066 AS2 (mov,r26,__tmp_reg__));
2068 return (AS2 (adiw,r26,%o1) CR_TAB
2069 AS2 (ld,%A0,X+) CR_TAB
2070 AS2 (ld,%B0,X+) CR_TAB
2071 AS2 (ld,%C0,X+) CR_TAB
2072 AS2 (ld,%D0,X) CR_TAB
2073 AS2 (sbiw,r26,%o1+3));
2075 if (reg_dest == reg_base)
2076 return *l=5, (AS2 (ldd,%D0,%D1) CR_TAB
2077 AS2 (ldd,%C0,%C1) CR_TAB
2078 AS2 (ldd,__tmp_reg__,%B1) CR_TAB
2079 AS2 (ldd,%A0,%A1) CR_TAB
2080 AS2 (mov,%B0,__tmp_reg__));
2081 else if (reg_dest == reg_base - 2)
2082 return *l=5, (AS2 (ldd,%A0,%A1) CR_TAB
2083 AS2 (ldd,%B0,%B1) CR_TAB
2084 AS2 (ldd,__tmp_reg__,%C1) CR_TAB
2085 AS2 (ldd,%D0,%D1) CR_TAB
2086 AS2 (mov,%C0,__tmp_reg__));
2087 return *l=4, (AS2 (ldd,%A0,%A1) CR_TAB
2088 AS2 (ldd,%B0,%B1) CR_TAB
2089 AS2 (ldd,%C0,%C1) CR_TAB
2092 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2093 return *l=4, (AS2 (ld,%D0,%1) CR_TAB
2094 AS2 (ld,%C0,%1) CR_TAB
2095 AS2 (ld,%B0,%1) CR_TAB
2097 else if (GET_CODE (base) == POST_INC) /* (R++) */
2098 return *l=4, (AS2 (ld,%A0,%1) CR_TAB
2099 AS2 (ld,%B0,%1) CR_TAB
2100 AS2 (ld,%C0,%1) CR_TAB
2102 else if (CONSTANT_ADDRESS_P (base))
2103 return *l=8, (AS2 (lds,%A0,%A1) CR_TAB
2104 AS2 (lds,%B0,%B1) CR_TAB
2105 AS2 (lds,%C0,%C1) CR_TAB
2108 fatal_insn ("unknown move insn:",insn);
2113 out_movsi_mr_r (rtx insn, rtx op[], int *l)
2117 rtx base = XEXP (dest, 0);
2118 int reg_base = true_regnum (base);
2119 int reg_src = true_regnum (src);
2125 if (CONSTANT_ADDRESS_P (base))
2126 return *l=8,(AS2 (sts,%A0,%A1) CR_TAB
2127 AS2 (sts,%B0,%B1) CR_TAB
2128 AS2 (sts,%C0,%C1) CR_TAB
2130 if (reg_base > 0) /* (r) */
2132 if (reg_base == REG_X) /* (R26) */
2134 if (reg_src == REG_X)
2136 /* "st X+,r26" is undefined */
2137 if (reg_unused_after (insn, base))
2138 return *l=6, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2139 AS2 (st,X,r26) CR_TAB
2140 AS2 (adiw,r26,1) CR_TAB
2141 AS2 (st,X+,__tmp_reg__) CR_TAB
2142 AS2 (st,X+,r28) CR_TAB
2145 return *l=7, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2146 AS2 (st,X,r26) CR_TAB
2147 AS2 (adiw,r26,1) CR_TAB
2148 AS2 (st,X+,__tmp_reg__) CR_TAB
2149 AS2 (st,X+,r28) CR_TAB
2150 AS2 (st,X,r29) CR_TAB
2153 else if (reg_base == reg_src + 2)
2155 if (reg_unused_after (insn, base))
2156 return *l=7, (AS2 (mov,__zero_reg__,%C1) CR_TAB
2157 AS2 (mov,__tmp_reg__,%D1) CR_TAB
2158 AS2 (st,%0+,%A1) CR_TAB
2159 AS2 (st,%0+,%B1) CR_TAB
2160 AS2 (st,%0+,__zero_reg__) CR_TAB
2161 AS2 (st,%0,__tmp_reg__) CR_TAB
2162 AS1 (clr,__zero_reg__));
2164 return *l=8, (AS2 (mov,__zero_reg__,%C1) CR_TAB
2165 AS2 (mov,__tmp_reg__,%D1) CR_TAB
2166 AS2 (st,%0+,%A1) CR_TAB
2167 AS2 (st,%0+,%B1) CR_TAB
2168 AS2 (st,%0+,__zero_reg__) CR_TAB
2169 AS2 (st,%0,__tmp_reg__) CR_TAB
2170 AS1 (clr,__zero_reg__) CR_TAB
2173 return *l=5, (AS2 (st,%0+,%A1) CR_TAB
2174 AS2 (st,%0+,%B1) CR_TAB
2175 AS2 (st,%0+,%C1) CR_TAB
2176 AS2 (st,%0,%D1) CR_TAB
2180 return *l=4, (AS2 (st,%0,%A1) CR_TAB
2181 AS2 (std,%0+1,%B1) CR_TAB
2182 AS2 (std,%0+2,%C1) CR_TAB
2183 AS2 (std,%0+3,%D1));
2185 else if (GET_CODE (base) == PLUS) /* (R + i) */
2187 int disp = INTVAL (XEXP (base, 1));
2188 reg_base = REGNO (XEXP (base, 0));
2189 if (disp > MAX_LD_OFFSET (GET_MODE (dest)))
2191 if (reg_base != REG_Y)
2192 fatal_insn ("incorrect insn:",insn);
2194 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2195 return *l = 6, (AS2 (adiw,r28,%o0-60) CR_TAB
2196 AS2 (std,Y+60,%A1) CR_TAB
2197 AS2 (std,Y+61,%B1) CR_TAB
2198 AS2 (std,Y+62,%C1) CR_TAB
2199 AS2 (std,Y+63,%D1) CR_TAB
2200 AS2 (sbiw,r28,%o0-60));
2202 return *l = 8, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2203 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2204 AS2 (st,Y,%A1) CR_TAB
2205 AS2 (std,Y+1,%B1) CR_TAB
2206 AS2 (std,Y+2,%C1) CR_TAB
2207 AS2 (std,Y+3,%D1) CR_TAB
2208 AS2 (subi,r28,lo8(%o0)) CR_TAB
2209 AS2 (sbci,r29,hi8(%o0)));
2211 if (reg_base == REG_X)
2214 if (reg_src == REG_X)
2217 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2218 AS2 (mov,__zero_reg__,r27) CR_TAB
2219 AS2 (adiw,r26,%o0) CR_TAB
2220 AS2 (st,X+,__tmp_reg__) CR_TAB
2221 AS2 (st,X+,__zero_reg__) CR_TAB
2222 AS2 (st,X+,r28) CR_TAB
2223 AS2 (st,X,r29) CR_TAB
2224 AS1 (clr,__zero_reg__) CR_TAB
2225 AS2 (sbiw,r26,%o0+3));
2227 else if (reg_src == REG_X - 2)
2230 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2231 AS2 (mov,__zero_reg__,r27) CR_TAB
2232 AS2 (adiw,r26,%o0) CR_TAB
2233 AS2 (st,X+,r24) CR_TAB
2234 AS2 (st,X+,r25) CR_TAB
2235 AS2 (st,X+,__tmp_reg__) CR_TAB
2236 AS2 (st,X,__zero_reg__) CR_TAB
2237 AS1 (clr,__zero_reg__) CR_TAB
2238 AS2 (sbiw,r26,%o0+3));
2241 return (AS2 (adiw,r26,%o0) CR_TAB
2242 AS2 (st,X+,%A1) CR_TAB
2243 AS2 (st,X+,%B1) CR_TAB
2244 AS2 (st,X+,%C1) CR_TAB
2245 AS2 (st,X,%D1) CR_TAB
2246 AS2 (sbiw,r26,%o0+3));
2248 return *l=4, (AS2 (std,%A0,%A1) CR_TAB
2249 AS2 (std,%B0,%B1) CR_TAB
2250 AS2 (std,%C0,%C1) CR_TAB
2253 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2254 return *l=4, (AS2 (st,%0,%D1) CR_TAB
2255 AS2 (st,%0,%C1) CR_TAB
2256 AS2 (st,%0,%B1) CR_TAB
2258 else if (GET_CODE (base) == POST_INC) /* (R++) */
2259 return *l=4, (AS2 (st,%0,%A1) CR_TAB
2260 AS2 (st,%0,%B1) CR_TAB
2261 AS2 (st,%0,%C1) CR_TAB
2263 fatal_insn ("unknown move insn:",insn);
2268 output_movsisf(rtx insn, rtx operands[], int *l)
2271 rtx dest = operands[0];
2272 rtx src = operands[1];
2278 if (register_operand (dest, VOIDmode))
2280 if (register_operand (src, VOIDmode)) /* mov r,r */
2282 if (true_regnum (dest) > true_regnum (src))
2287 return (AS2 (movw,%C0,%C1) CR_TAB
2288 AS2 (movw,%A0,%A1));
2291 return (AS2 (mov,%D0,%D1) CR_TAB
2292 AS2 (mov,%C0,%C1) CR_TAB
2293 AS2 (mov,%B0,%B1) CR_TAB
2301 return (AS2 (movw,%A0,%A1) CR_TAB
2302 AS2 (movw,%C0,%C1));
2305 return (AS2 (mov,%A0,%A1) CR_TAB
2306 AS2 (mov,%B0,%B1) CR_TAB
2307 AS2 (mov,%C0,%C1) CR_TAB
2311 else if (CONSTANT_P (src))
2313 if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
2316 return (AS2 (ldi,%A0,lo8(%1)) CR_TAB
2317 AS2 (ldi,%B0,hi8(%1)) CR_TAB
2318 AS2 (ldi,%C0,hlo8(%1)) CR_TAB
2319 AS2 (ldi,%D0,hhi8(%1)));
2322 if (GET_CODE (src) == CONST_INT)
2324 const char *const clr_op0 =
2325 AVR_ENHANCED ? (AS1 (clr,%A0) CR_TAB
2326 AS1 (clr,%B0) CR_TAB
2328 : (AS1 (clr,%A0) CR_TAB
2329 AS1 (clr,%B0) CR_TAB
2330 AS1 (clr,%C0) CR_TAB
2333 if (src == const0_rtx) /* mov r,L */
2335 *l = AVR_ENHANCED ? 3 : 4;
2338 else if (src == const1_rtx)
2341 output_asm_insn (clr_op0, operands);
2342 *l = AVR_ENHANCED ? 4 : 5;
2343 return AS1 (inc,%A0);
2345 else if (src == constm1_rtx)
2347 /* Immediate constants -1 to any register */
2351 return (AS1 (clr,%A0) CR_TAB
2352 AS1 (dec,%A0) CR_TAB
2353 AS2 (mov,%B0,%A0) CR_TAB
2354 AS2 (movw,%C0,%A0));
2357 return (AS1 (clr,%A0) CR_TAB
2358 AS1 (dec,%A0) CR_TAB
2359 AS2 (mov,%B0,%A0) CR_TAB
2360 AS2 (mov,%C0,%A0) CR_TAB
2365 int bit_nr = exact_log2 (INTVAL (src));
2369 *l = AVR_ENHANCED ? 5 : 6;
2372 output_asm_insn (clr_op0, operands);
2373 output_asm_insn ("set", operands);
2376 avr_output_bld (operands, bit_nr);
2383 /* Last resort, better than loading from memory. */
2385 return (AS2 (mov,__tmp_reg__,r31) CR_TAB
2386 AS2 (ldi,r31,lo8(%1)) CR_TAB
2387 AS2 (mov,%A0,r31) CR_TAB
2388 AS2 (ldi,r31,hi8(%1)) CR_TAB
2389 AS2 (mov,%B0,r31) CR_TAB
2390 AS2 (ldi,r31,hlo8(%1)) CR_TAB
2391 AS2 (mov,%C0,r31) CR_TAB
2392 AS2 (ldi,r31,hhi8(%1)) CR_TAB
2393 AS2 (mov,%D0,r31) CR_TAB
2394 AS2 (mov,r31,__tmp_reg__));
2396 else if (GET_CODE (src) == MEM)
2397 return out_movsi_r_mr (insn, operands, real_l); /* mov r,m */
2399 else if (GET_CODE (dest) == MEM)
2401 const char *template;
2403 if (src == const0_rtx)
2404 operands[1] = zero_reg_rtx;
2406 template = out_movsi_mr_r (insn, operands, real_l);
2409 output_asm_insn (template, operands);
2414 fatal_insn ("invalid insn:", insn);
2419 out_movqi_mr_r (rtx insn, rtx op[], int *l)
2423 rtx x = XEXP (dest, 0);
2429 if (CONSTANT_ADDRESS_P (x))
2431 if (avr_io_address_p (x, 1))
2434 return AS2 (out,%0-0x20,%1);
2437 return AS2 (sts,%0,%1);
2439 /* memory access by reg+disp */
2440 else if (GET_CODE (x) == PLUS
2441 && REG_P (XEXP (x,0))
2442 && GET_CODE (XEXP (x,1)) == CONST_INT)
2444 if ((INTVAL (XEXP (x,1)) - GET_MODE_SIZE (GET_MODE (dest))) >= 63)
2446 int disp = INTVAL (XEXP (x,1));
2447 if (REGNO (XEXP (x,0)) != REG_Y)
2448 fatal_insn ("incorrect insn:",insn);
2450 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2451 return *l = 3, (AS2 (adiw,r28,%o0-63) CR_TAB
2452 AS2 (std,Y+63,%1) CR_TAB
2453 AS2 (sbiw,r28,%o0-63));
2455 return *l = 5, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2456 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2457 AS2 (st,Y,%1) CR_TAB
2458 AS2 (subi,r28,lo8(%o0)) CR_TAB
2459 AS2 (sbci,r29,hi8(%o0)));
2461 else if (REGNO (XEXP (x,0)) == REG_X)
2463 if (reg_overlap_mentioned_p (src, XEXP (x, 0)))
2465 if (reg_unused_after (insn, XEXP (x,0)))
2466 return *l = 3, (AS2 (mov,__tmp_reg__,%1) CR_TAB
2467 AS2 (adiw,r26,%o0) CR_TAB
2468 AS2 (st,X,__tmp_reg__));
2470 return *l = 4, (AS2 (mov,__tmp_reg__,%1) CR_TAB
2471 AS2 (adiw,r26,%o0) CR_TAB
2472 AS2 (st,X,__tmp_reg__) CR_TAB
2473 AS2 (sbiw,r26,%o0));
2477 if (reg_unused_after (insn, XEXP (x,0)))
2478 return *l = 2, (AS2 (adiw,r26,%o0) CR_TAB
2481 return *l = 3, (AS2 (adiw,r26,%o0) CR_TAB
2482 AS2 (st,X,%1) CR_TAB
2483 AS2 (sbiw,r26,%o0));
2487 return AS2 (std,%0,%1);
2490 return AS2 (st,%0,%1);
2494 out_movhi_mr_r (rtx insn, rtx op[], int *l)
2498 rtx base = XEXP (dest, 0);
2499 int reg_base = true_regnum (base);
2500 int reg_src = true_regnum (src);
2504 if (CONSTANT_ADDRESS_P (base))
2506 if (avr_io_address_p (base, 2))
2509 return (AS2 (out,%B0-0x20,%B1) CR_TAB
2510 AS2 (out,%A0-0x20,%A1));
2512 return *l = 4, (AS2 (sts,%B0,%B1) CR_TAB
2517 if (reg_base == REG_X)
2519 if (reg_src == REG_X)
2521 /* "st X+,r26" is undefined */
2522 if (reg_unused_after (insn, src))
2523 return *l=4, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2524 AS2 (st,X,r26) CR_TAB
2525 AS2 (adiw,r26,1) CR_TAB
2526 AS2 (st,X,__tmp_reg__));
2528 return *l=5, (AS2 (mov,__tmp_reg__,r27) CR_TAB
2529 AS2 (st,X,r26) CR_TAB
2530 AS2 (adiw,r26,1) CR_TAB
2531 AS2 (st,X,__tmp_reg__) CR_TAB
2536 if (reg_unused_after (insn, base))
2537 return *l=2, (AS2 (st,X+,%A1) CR_TAB
2540 return *l=3, (AS2 (st ,X+,%A1) CR_TAB
2541 AS2 (st ,X,%B1) CR_TAB
2546 return *l=2, (AS2 (st ,%0,%A1) CR_TAB
2547 AS2 (std,%0+1,%B1));
2549 else if (GET_CODE (base) == PLUS)
2551 int disp = INTVAL (XEXP (base, 1));
2552 reg_base = REGNO (XEXP (base, 0));
2553 if (disp > MAX_LD_OFFSET (GET_MODE (dest)))
2555 if (reg_base != REG_Y)
2556 fatal_insn ("incorrect insn:",insn);
2558 if (disp <= 63 + MAX_LD_OFFSET (GET_MODE (dest)))
2559 return *l = 4, (AS2 (adiw,r28,%o0-62) CR_TAB
2560 AS2 (std,Y+62,%A1) CR_TAB
2561 AS2 (std,Y+63,%B1) CR_TAB
2562 AS2 (sbiw,r28,%o0-62));
2564 return *l = 6, (AS2 (subi,r28,lo8(-%o0)) CR_TAB
2565 AS2 (sbci,r29,hi8(-%o0)) CR_TAB
2566 AS2 (st,Y,%A1) CR_TAB
2567 AS2 (std,Y+1,%B1) CR_TAB
2568 AS2 (subi,r28,lo8(%o0)) CR_TAB
2569 AS2 (sbci,r29,hi8(%o0)));
2571 if (reg_base == REG_X)
2574 if (reg_src == REG_X)
2577 return (AS2 (mov,__tmp_reg__,r26) CR_TAB
2578 AS2 (mov,__zero_reg__,r27) CR_TAB
2579 AS2 (adiw,r26,%o0) CR_TAB
2580 AS2 (st,X+,__tmp_reg__) CR_TAB
2581 AS2 (st,X,__zero_reg__) CR_TAB
2582 AS1 (clr,__zero_reg__) CR_TAB
2583 AS2 (sbiw,r26,%o0+1));
2586 return (AS2 (adiw,r26,%o0) CR_TAB
2587 AS2 (st,X+,%A1) CR_TAB
2588 AS2 (st,X,%B1) CR_TAB
2589 AS2 (sbiw,r26,%o0+1));
2591 return *l=2, (AS2 (std,%A0,%A1) CR_TAB
2594 else if (GET_CODE (base) == PRE_DEC) /* (--R) */
2595 return *l=2, (AS2 (st,%0,%B1) CR_TAB
2597 else if (GET_CODE (base) == POST_INC) /* (R++) */
2598 return *l=2, (AS2 (st,%0,%A1) CR_TAB
2600 fatal_insn ("unknown move insn:",insn);
2604 /* Return 1 if frame pointer for current function required. */
2607 frame_pointer_required_p (void)
2609 return (current_function_calls_alloca
2610 || current_function_args_info.nregs == 0
2611 || get_frame_size () > 0);
2614 /* Returns the condition of compare insn INSN, or UNKNOWN. */
2617 compare_condition (rtx insn)
2619 rtx next = next_real_insn (insn);
2620 RTX_CODE cond = UNKNOWN;
2621 if (next && GET_CODE (next) == JUMP_INSN)
2623 rtx pat = PATTERN (next);
2624 rtx src = SET_SRC (pat);
2625 rtx t = XEXP (src, 0);
2626 cond = GET_CODE (t);
2631 /* Returns nonzero if INSN is a tst insn that only tests the sign. */
2634 compare_sign_p (rtx insn)
2636 RTX_CODE cond = compare_condition (insn);
2637 return (cond == GE || cond == LT);
2640 /* Returns nonzero if the next insn is a JUMP_INSN with a condition
2641 that needs to be swapped (GT, GTU, LE, LEU). */
2644 compare_diff_p (rtx insn)
2646 RTX_CODE cond = compare_condition (insn);
2647 return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0;
2650 /* Returns nonzero if INSN is a compare insn with the EQ or NE condition. */
2653 compare_eq_p (rtx insn)
2655 RTX_CODE cond = compare_condition (insn);
2656 return (cond == EQ || cond == NE);
2660 /* Output test instruction for HImode. */
2663 out_tsthi (rtx insn, int *l)
2665 if (compare_sign_p (insn))
2668 return AS1 (tst,%B0);
2670 if (reg_unused_after (insn, SET_SRC (PATTERN (insn)))
2671 && compare_eq_p (insn))
2673 /* Faster than sbiw if we can clobber the operand. */
2675 return AS2 (or,%A0,%B0);
2677 if (test_hard_reg_class (ADDW_REGS, SET_SRC (PATTERN (insn))))
2680 return AS2 (sbiw,%0,0);
2683 return (AS2 (cp,%A0,__zero_reg__) CR_TAB
2684 AS2 (cpc,%B0,__zero_reg__));
2688 /* Output test instruction for SImode. */
2691 out_tstsi (rtx insn, int *l)
2693 if (compare_sign_p (insn))
2696 return AS1 (tst,%D0);
2698 if (test_hard_reg_class (ADDW_REGS, SET_SRC (PATTERN (insn))))
2701 return (AS2 (sbiw,%A0,0) CR_TAB
2702 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2703 AS2 (cpc,%D0,__zero_reg__));
2706 return (AS2 (cp,%A0,__zero_reg__) CR_TAB
2707 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2708 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2709 AS2 (cpc,%D0,__zero_reg__));
2713 /* Generate asm equivalent for various shifts.
2714 Shift count is a CONST_INT, MEM or REG.
2715 This only handles cases that are not already
2716 carefully hand-optimized in ?sh??i3_out. */
2719 out_shift_with_cnt (const char *template, rtx insn, rtx operands[],
2720 int *len, int t_len)
2724 int second_label = 1;
2725 int saved_in_tmp = 0;
2726 int use_zero_reg = 0;
2728 op[0] = operands[0];
2729 op[1] = operands[1];
2730 op[2] = operands[2];
2731 op[3] = operands[3];
2737 if (GET_CODE (operands[2]) == CONST_INT)
2739 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
2740 int count = INTVAL (operands[2]);
2741 int max_len = 10; /* If larger than this, always use a loop. */
2743 if (count < 8 && !scratch)
2747 max_len = t_len + (scratch ? 3 : (use_zero_reg ? 4 : 5));
2749 if (t_len * count <= max_len)
2751 /* Output shifts inline with no loop - faster. */
2753 *len = t_len * count;
2757 output_asm_insn (template, op);
2766 strcat (str, AS2 (ldi,%3,%2));
2768 else if (use_zero_reg)
2770 /* Hack to save one word: use __zero_reg__ as loop counter.
2771 Set one bit, then shift in a loop until it is 0 again. */
2773 op[3] = zero_reg_rtx;
2777 strcat (str, ("set" CR_TAB
2778 AS2 (bld,%3,%2-1)));
2782 /* No scratch register available, use one from LD_REGS (saved in
2783 __tmp_reg__) that doesn't overlap with registers to shift. */
2785 op[3] = gen_rtx_REG (QImode,
2786 ((true_regnum (operands[0]) - 1) & 15) + 16);
2787 op[4] = tmp_reg_rtx;
2791 *len = 3; /* Includes "mov %3,%4" after the loop. */
2793 strcat (str, (AS2 (mov,%4,%3) CR_TAB
2799 else if (GET_CODE (operands[2]) == MEM)
2803 op[3] = op_mov[0] = tmp_reg_rtx;
2807 out_movqi_r_mr (insn, op_mov, len);
2809 output_asm_insn (out_movqi_r_mr (insn, op_mov, NULL), op_mov);
2811 else if (register_operand (operands[2], QImode))
2813 if (reg_unused_after (insn, operands[2]))
2817 op[3] = tmp_reg_rtx;
2819 strcat (str, (AS2 (mov,%3,%2) CR_TAB));
2823 fatal_insn ("bad shift insn:", insn);
2830 strcat (str, AS1 (rjmp,2f));
2834 *len += t_len + 2; /* template + dec + brXX */
2837 strcat (str, "\n1:\t");
2838 strcat (str, template);
2839 strcat (str, second_label ? "\n2:\t" : "\n\t");
2840 strcat (str, use_zero_reg ? AS1 (lsr,%3) : AS1 (dec,%3));
2841 strcat (str, CR_TAB);
2842 strcat (str, second_label ? AS1 (brpl,1b) : AS1 (brne,1b));
2844 strcat (str, (CR_TAB AS2 (mov,%3,%4)));
2845 output_asm_insn (str, op);
2850 /* 8bit shift left ((char)x << i) */
2853 ashlqi3_out (rtx insn, rtx operands[], int *len)
2855 if (GET_CODE (operands[2]) == CONST_INT)
2862 switch (INTVAL (operands[2]))
2866 return AS1 (clr,%0);
2870 return AS1 (lsl,%0);
2874 return (AS1 (lsl,%0) CR_TAB
2879 return (AS1 (lsl,%0) CR_TAB
2884 if (test_hard_reg_class (LD_REGS, operands[0]))
2887 return (AS1 (swap,%0) CR_TAB
2888 AS2 (andi,%0,0xf0));
2891 return (AS1 (lsl,%0) CR_TAB
2897 if (test_hard_reg_class (LD_REGS, operands[0]))
2900 return (AS1 (swap,%0) CR_TAB
2902 AS2 (andi,%0,0xe0));
2905 return (AS1 (lsl,%0) CR_TAB
2912 if (test_hard_reg_class (LD_REGS, operands[0]))
2915 return (AS1 (swap,%0) CR_TAB
2918 AS2 (andi,%0,0xc0));
2921 return (AS1 (lsl,%0) CR_TAB
2930 return (AS1 (ror,%0) CR_TAB
2935 else if (CONSTANT_P (operands[2]))
2936 fatal_insn ("internal compiler error. Incorrect shift:", insn);
2938 out_shift_with_cnt (AS1 (lsl,%0),
2939 insn, operands, len, 1);
2944 /* 16bit shift left ((short)x << i) */
2947 ashlhi3_out (rtx insn, rtx operands[], int *len)
2949 if (GET_CODE (operands[2]) == CONST_INT)
2951 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
2952 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
2959 switch (INTVAL (operands[2]))
2962 if (optimize_size && scratch)
2967 return (AS1 (swap,%A0) CR_TAB
2968 AS1 (swap,%B0) CR_TAB
2969 AS2 (andi,%B0,0xf0) CR_TAB
2970 AS2 (eor,%B0,%A0) CR_TAB
2971 AS2 (andi,%A0,0xf0) CR_TAB
2977 return (AS1 (swap,%A0) CR_TAB
2978 AS1 (swap,%B0) CR_TAB
2979 AS2 (ldi,%3,0xf0) CR_TAB
2980 AS2 (and,%B0,%3) CR_TAB
2981 AS2 (eor,%B0,%A0) CR_TAB
2982 AS2 (and,%A0,%3) CR_TAB
2985 break; /* optimize_size ? 6 : 8 */
2989 break; /* scratch ? 5 : 6 */
2993 return (AS1 (lsl,%A0) CR_TAB
2994 AS1 (rol,%B0) CR_TAB
2995 AS1 (swap,%A0) CR_TAB
2996 AS1 (swap,%B0) CR_TAB
2997 AS2 (andi,%B0,0xf0) CR_TAB
2998 AS2 (eor,%B0,%A0) CR_TAB
2999 AS2 (andi,%A0,0xf0) CR_TAB
3005 return (AS1 (lsl,%A0) CR_TAB
3006 AS1 (rol,%B0) CR_TAB
3007 AS1 (swap,%A0) CR_TAB
3008 AS1 (swap,%B0) CR_TAB
3009 AS2 (ldi,%3,0xf0) CR_TAB
3010 AS2 (and,%B0,%3) CR_TAB
3011 AS2 (eor,%B0,%A0) CR_TAB
3012 AS2 (and,%A0,%3) CR_TAB
3019 break; /* scratch ? 5 : 6 */
3021 return (AS1 (clr,__tmp_reg__) CR_TAB
3022 AS1 (lsr,%B0) CR_TAB
3023 AS1 (ror,%A0) CR_TAB
3024 AS1 (ror,__tmp_reg__) CR_TAB
3025 AS1 (lsr,%B0) CR_TAB
3026 AS1 (ror,%A0) CR_TAB
3027 AS1 (ror,__tmp_reg__) CR_TAB
3028 AS2 (mov,%B0,%A0) CR_TAB
3029 AS2 (mov,%A0,__tmp_reg__));
3033 return (AS1 (lsr,%B0) CR_TAB
3034 AS2 (mov,%B0,%A0) CR_TAB
3035 AS1 (clr,%A0) CR_TAB
3036 AS1 (ror,%B0) CR_TAB
3040 if (true_regnum (operands[0]) + 1 == true_regnum (operands[1]))
3041 return *len = 1, AS1 (clr,%A0);
3043 return *len = 2, (AS2 (mov,%B0,%A1) CR_TAB
3048 return (AS2 (mov,%B0,%A0) CR_TAB
3049 AS1 (clr,%A0) CR_TAB
3054 return (AS2 (mov,%B0,%A0) CR_TAB
3055 AS1 (clr,%A0) CR_TAB
3056 AS1 (lsl,%B0) CR_TAB
3061 return (AS2 (mov,%B0,%A0) CR_TAB
3062 AS1 (clr,%A0) CR_TAB
3063 AS1 (lsl,%B0) CR_TAB
3064 AS1 (lsl,%B0) CR_TAB
3071 return (AS2 (mov,%B0,%A0) CR_TAB
3072 AS1 (clr,%A0) CR_TAB
3073 AS1 (swap,%B0) CR_TAB
3074 AS2 (andi,%B0,0xf0));
3079 return (AS2 (mov,%B0,%A0) CR_TAB
3080 AS1 (clr,%A0) CR_TAB
3081 AS1 (swap,%B0) CR_TAB
3082 AS2 (ldi,%3,0xf0) CR_TAB
3086 return (AS2 (mov,%B0,%A0) CR_TAB
3087 AS1 (clr,%A0) CR_TAB
3088 AS1 (lsl,%B0) CR_TAB
3089 AS1 (lsl,%B0) CR_TAB
3090 AS1 (lsl,%B0) CR_TAB
3097 return (AS2 (mov,%B0,%A0) CR_TAB
3098 AS1 (clr,%A0) CR_TAB
3099 AS1 (swap,%B0) CR_TAB
3100 AS1 (lsl,%B0) CR_TAB
3101 AS2 (andi,%B0,0xe0));
3103 if (AVR_ENHANCED && scratch)
3106 return (AS2 (ldi,%3,0x20) CR_TAB
3107 AS2 (mul,%A0,%3) CR_TAB
3108 AS2 (mov,%B0,r0) CR_TAB
3109 AS1 (clr,%A0) CR_TAB
3110 AS1 (clr,__zero_reg__));
3112 if (optimize_size && scratch)
3117 return (AS2 (mov,%B0,%A0) CR_TAB
3118 AS1 (clr,%A0) CR_TAB
3119 AS1 (swap,%B0) CR_TAB
3120 AS1 (lsl,%B0) CR_TAB
3121 AS2 (ldi,%3,0xe0) CR_TAB
3127 return ("set" CR_TAB
3128 AS2 (bld,r1,5) CR_TAB
3129 AS2 (mul,%A0,r1) CR_TAB
3130 AS2 (mov,%B0,r0) CR_TAB
3131 AS1 (clr,%A0) CR_TAB
3132 AS1 (clr,__zero_reg__));
3135 return (AS2 (mov,%B0,%A0) CR_TAB
3136 AS1 (clr,%A0) CR_TAB
3137 AS1 (lsl,%B0) CR_TAB
3138 AS1 (lsl,%B0) CR_TAB
3139 AS1 (lsl,%B0) CR_TAB
3140 AS1 (lsl,%B0) CR_TAB
3144 if (AVR_ENHANCED && ldi_ok)
3147 return (AS2 (ldi,%B0,0x40) CR_TAB
3148 AS2 (mul,%A0,%B0) CR_TAB
3149 AS2 (mov,%B0,r0) CR_TAB
3150 AS1 (clr,%A0) CR_TAB
3151 AS1 (clr,__zero_reg__));
3153 if (AVR_ENHANCED && scratch)
3156 return (AS2 (ldi,%3,0x40) CR_TAB
3157 AS2 (mul,%A0,%3) CR_TAB
3158 AS2 (mov,%B0,r0) CR_TAB
3159 AS1 (clr,%A0) CR_TAB
3160 AS1 (clr,__zero_reg__));
3162 if (optimize_size && ldi_ok)
3165 return (AS2 (mov,%B0,%A0) CR_TAB
3166 AS2 (ldi,%A0,6) "\n1:\t"
3167 AS1 (lsl,%B0) CR_TAB
3168 AS1 (dec,%A0) CR_TAB
3171 if (optimize_size && scratch)
3174 return (AS1 (clr,%B0) CR_TAB
3175 AS1 (lsr,%A0) CR_TAB
3176 AS1 (ror,%B0) CR_TAB
3177 AS1 (lsr,%A0) CR_TAB
3178 AS1 (ror,%B0) CR_TAB
3183 return (AS1 (clr,%B0) CR_TAB
3184 AS1 (lsr,%A0) CR_TAB
3185 AS1 (ror,%B0) CR_TAB
3190 out_shift_with_cnt ((AS1 (lsl,%A0) CR_TAB
3192 insn, operands, len, 2);
3197 /* 32bit shift left ((long)x << i) */
3200 ashlsi3_out (rtx insn, rtx operands[], int *len)
3202 if (GET_CODE (operands[2]) == CONST_INT)
3210 switch (INTVAL (operands[2]))
3214 int reg0 = true_regnum (operands[0]);
3215 int reg1 = true_regnum (operands[1]);
3218 return (AS2 (mov,%D0,%C1) CR_TAB
3219 AS2 (mov,%C0,%B1) CR_TAB
3220 AS2 (mov,%B0,%A1) CR_TAB
3222 else if (reg0 + 1 == reg1)
3225 return AS1 (clr,%A0);
3228 return (AS1 (clr,%A0) CR_TAB
3229 AS2 (mov,%B0,%A1) CR_TAB
3230 AS2 (mov,%C0,%B1) CR_TAB
3236 int reg0 = true_regnum (operands[0]);
3237 int reg1 = true_regnum (operands[1]);
3239 if (AVR_ENHANCED && (reg0 + 2 != reg1))
3242 return (AS2 (movw,%C0,%A1) CR_TAB
3243 AS1 (clr,%B0) CR_TAB
3246 if (reg0 + 1 >= reg1)
3247 return (AS2 (mov,%D0,%B1) CR_TAB
3248 AS2 (mov,%C0,%A1) CR_TAB
3249 AS1 (clr,%B0) CR_TAB
3251 if (reg0 + 2 == reg1)
3254 return (AS1 (clr,%B0) CR_TAB
3258 return (AS2 (mov,%C0,%A1) CR_TAB
3259 AS2 (mov,%D0,%B1) CR_TAB
3260 AS1 (clr,%B0) CR_TAB
3266 if (true_regnum (operands[0]) + 3 != true_regnum (operands[1]))
3267 return (AS2 (mov,%D0,%A1) CR_TAB
3268 AS1 (clr,%C0) CR_TAB
3269 AS1 (clr,%B0) CR_TAB
3274 return (AS1 (clr,%C0) CR_TAB
3275 AS1 (clr,%B0) CR_TAB
3281 return (AS1 (clr,%D0) CR_TAB
3282 AS1 (lsr,%A0) CR_TAB
3283 AS1 (ror,%D0) CR_TAB
3284 AS1 (clr,%C0) CR_TAB
3285 AS1 (clr,%B0) CR_TAB
3290 out_shift_with_cnt ((AS1 (lsl,%A0) CR_TAB
3291 AS1 (rol,%B0) CR_TAB
3292 AS1 (rol,%C0) CR_TAB
3294 insn, operands, len, 4);
3298 /* 8bit arithmetic shift right ((signed char)x >> i) */
3301 ashrqi3_out (rtx insn, rtx operands[], int *len)
3303 if (GET_CODE (operands[2]) == CONST_INT)
3310 switch (INTVAL (operands[2]))
3314 return AS1 (asr,%0);
3318 return (AS1 (asr,%0) CR_TAB
3323 return (AS1 (asr,%0) CR_TAB
3329 return (AS1 (asr,%0) CR_TAB
3336 return (AS1 (asr,%0) CR_TAB
3344 return (AS2 (bst,%0,6) CR_TAB
3346 AS2 (sbc,%0,%0) CR_TAB
3352 return (AS1 (lsl,%0) CR_TAB
3356 else if (CONSTANT_P (operands[2]))
3357 fatal_insn ("internal compiler error. Incorrect shift:", insn);
3359 out_shift_with_cnt (AS1 (asr,%0),
3360 insn, operands, len, 1);
3365 /* 16bit arithmetic shift right ((signed short)x >> i) */
3368 ashrhi3_out (rtx insn, rtx operands[], int *len)
3370 if (GET_CODE (operands[2]) == CONST_INT)
3372 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
3373 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
3380 switch (INTVAL (operands[2]))
3384 /* XXX try to optimize this too? */
3389 break; /* scratch ? 5 : 6 */
3391 return (AS2 (mov,__tmp_reg__,%A0) CR_TAB
3392 AS2 (mov,%A0,%B0) CR_TAB
3393 AS1 (lsl,__tmp_reg__) CR_TAB
3394 AS1 (rol,%A0) CR_TAB
3395 AS2 (sbc,%B0,%B0) CR_TAB
3396 AS1 (lsl,__tmp_reg__) CR_TAB
3397 AS1 (rol,%A0) CR_TAB
3402 return (AS1 (lsl,%A0) CR_TAB
3403 AS2 (mov,%A0,%B0) CR_TAB
3404 AS1 (rol,%A0) CR_TAB
3409 int reg0 = true_regnum (operands[0]);
3410 int reg1 = true_regnum (operands[1]);
3413 return *len = 3, (AS2 (mov,%A0,%B0) CR_TAB
3414 AS1 (lsl,%B0) CR_TAB
3416 else if (reg0 == reg1 + 1)
3417 return *len = 3, (AS1 (clr,%B0) CR_TAB
3418 AS2 (sbrc,%A0,7) CR_TAB
3421 return *len = 4, (AS2 (mov,%A0,%B1) CR_TAB
3422 AS1 (clr,%B0) CR_TAB
3423 AS2 (sbrc,%A0,7) CR_TAB
3429 return (AS2 (mov,%A0,%B0) CR_TAB
3430 AS1 (lsl,%B0) CR_TAB
3431 AS2 (sbc,%B0,%B0) CR_TAB
3436 return (AS2 (mov,%A0,%B0) CR_TAB
3437 AS1 (lsl,%B0) CR_TAB
3438 AS2 (sbc,%B0,%B0) CR_TAB
3439 AS1 (asr,%A0) CR_TAB
3443 if (AVR_ENHANCED && ldi_ok)
3446 return (AS2 (ldi,%A0,0x20) CR_TAB
3447 AS2 (muls,%B0,%A0) CR_TAB
3448 AS2 (mov,%A0,r1) CR_TAB
3449 AS2 (sbc,%B0,%B0) CR_TAB
3450 AS1 (clr,__zero_reg__));
3452 if (optimize_size && scratch)
3455 return (AS2 (mov,%A0,%B0) CR_TAB
3456 AS1 (lsl,%B0) CR_TAB
3457 AS2 (sbc,%B0,%B0) CR_TAB
3458 AS1 (asr,%A0) CR_TAB
3459 AS1 (asr,%A0) CR_TAB
3463 if (AVR_ENHANCED && ldi_ok)
3466 return (AS2 (ldi,%A0,0x10) CR_TAB
3467 AS2 (muls,%B0,%A0) CR_TAB
3468 AS2 (mov,%A0,r1) CR_TAB
3469 AS2 (sbc,%B0,%B0) CR_TAB
3470 AS1 (clr,__zero_reg__));
3472 if (optimize_size && scratch)
3475 return (AS2 (mov,%A0,%B0) CR_TAB
3476 AS1 (lsl,%B0) CR_TAB
3477 AS2 (sbc,%B0,%B0) CR_TAB
3478 AS1 (asr,%A0) CR_TAB
3479 AS1 (asr,%A0) CR_TAB
3480 AS1 (asr,%A0) CR_TAB
3484 if (AVR_ENHANCED && ldi_ok)
3487 return (AS2 (ldi,%A0,0x08) CR_TAB
3488 AS2 (muls,%B0,%A0) CR_TAB
3489 AS2 (mov,%A0,r1) CR_TAB
3490 AS2 (sbc,%B0,%B0) CR_TAB
3491 AS1 (clr,__zero_reg__));
3494 break; /* scratch ? 5 : 7 */
3496 return (AS2 (mov,%A0,%B0) CR_TAB
3497 AS1 (lsl,%B0) CR_TAB
3498 AS2 (sbc,%B0,%B0) CR_TAB
3499 AS1 (asr,%A0) CR_TAB
3500 AS1 (asr,%A0) CR_TAB
3501 AS1 (asr,%A0) CR_TAB
3502 AS1 (asr,%A0) CR_TAB
3507 return (AS1 (lsl,%B0) CR_TAB
3508 AS2 (sbc,%A0,%A0) CR_TAB
3509 AS1 (lsl,%B0) CR_TAB
3510 AS2 (mov,%B0,%A0) CR_TAB
3514 return *len = 3, (AS1 (lsl,%B0) CR_TAB
3515 AS2 (sbc,%A0,%A0) CR_TAB
3520 out_shift_with_cnt ((AS1 (asr,%B0) CR_TAB
3522 insn, operands, len, 2);
3527 /* 32bit arithmetic shift right ((signed long)x >> i) */
3530 ashrsi3_out (rtx insn, rtx operands[], int *len)
3532 if (GET_CODE (operands[2]) == CONST_INT)
3540 switch (INTVAL (operands[2]))
3544 int reg0 = true_regnum (operands[0]);
3545 int reg1 = true_regnum (operands[1]);
3548 return (AS2 (mov,%A0,%B1) CR_TAB
3549 AS2 (mov,%B0,%C1) CR_TAB
3550 AS2 (mov,%C0,%D1) CR_TAB
3551 AS1 (clr,%D0) CR_TAB
3552 AS2 (sbrc,%C0,7) CR_TAB
3554 else if (reg0 == reg1 + 1)
3557 return (AS1 (clr,%D0) CR_TAB
3558 AS2 (sbrc,%C0,7) CR_TAB
3562 return (AS1 (clr,%D0) CR_TAB
3563 AS2 (sbrc,%D1,7) CR_TAB
3564 AS1 (dec,%D0) CR_TAB
3565 AS2 (mov,%C0,%D1) CR_TAB
3566 AS2 (mov,%B0,%C1) CR_TAB
3572 int reg0 = true_regnum (operands[0]);
3573 int reg1 = true_regnum (operands[1]);
3575 if (AVR_ENHANCED && (reg0 != reg1 + 2))
3578 return (AS2 (movw,%A0,%C1) CR_TAB
3579 AS1 (clr,%D0) CR_TAB
3580 AS2 (sbrc,%B0,7) CR_TAB
3581 AS1 (com,%D0) CR_TAB
3584 if (reg0 <= reg1 + 1)
3585 return (AS2 (mov,%A0,%C1) CR_TAB
3586 AS2 (mov,%B0,%D1) CR_TAB
3587 AS1 (clr,%D0) CR_TAB
3588 AS2 (sbrc,%B0,7) CR_TAB
3589 AS1 (com,%D0) CR_TAB
3591 else if (reg0 == reg1 + 2)
3592 return *len = 4, (AS1 (clr,%D0) CR_TAB
3593 AS2 (sbrc,%B0,7) CR_TAB
3594 AS1 (com,%D0) CR_TAB
3597 return (AS2 (mov,%B0,%D1) CR_TAB
3598 AS2 (mov,%A0,%C1) CR_TAB
3599 AS1 (clr,%D0) CR_TAB
3600 AS2 (sbrc,%B0,7) CR_TAB
3601 AS1 (com,%D0) CR_TAB
3606 if (true_regnum (operands[0]) != true_regnum (operands[1]) + 3)
3607 return *len = 6, (AS2 (mov,%A0,%D1) CR_TAB
3608 AS1 (clr,%D0) CR_TAB
3609 AS2 (sbrc,%A0,7) CR_TAB
3610 AS1 (com,%D0) CR_TAB
3611 AS2 (mov,%B0,%D0) CR_TAB
3614 return *len = 5, (AS1 (clr,%D0) CR_TAB
3615 AS2 (sbrc,%A0,7) CR_TAB
3616 AS1 (com,%D0) CR_TAB
3617 AS2 (mov,%B0,%D0) CR_TAB
3622 return *len = 4, (AS1 (lsl,%D0) CR_TAB
3623 AS2 (sbc,%A0,%A0) CR_TAB
3624 AS2 (mov,%B0,%A0) CR_TAB
3625 AS2 (movw,%C0,%A0));
3627 return *len = 5, (AS1 (lsl,%D0) CR_TAB
3628 AS2 (sbc,%A0,%A0) CR_TAB
3629 AS2 (mov,%B0,%A0) CR_TAB
3630 AS2 (mov,%C0,%A0) CR_TAB
3635 out_shift_with_cnt ((AS1 (asr,%D0) CR_TAB
3636 AS1 (ror,%C0) CR_TAB
3637 AS1 (ror,%B0) CR_TAB
3639 insn, operands, len, 4);
3643 /* 8bit logic shift right ((unsigned char)x >> i) */
3646 lshrqi3_out (rtx insn, rtx operands[], int *len)
3648 if (GET_CODE (operands[2]) == CONST_INT)
3655 switch (INTVAL (operands[2]))
3659 return AS1 (clr,%0);
3663 return AS1 (lsr,%0);
3667 return (AS1 (lsr,%0) CR_TAB
3671 return (AS1 (lsr,%0) CR_TAB
3676 if (test_hard_reg_class (LD_REGS, operands[0]))
3679 return (AS1 (swap,%0) CR_TAB
3680 AS2 (andi,%0,0x0f));
3683 return (AS1 (lsr,%0) CR_TAB
3689 if (test_hard_reg_class (LD_REGS, operands[0]))
3692 return (AS1 (swap,%0) CR_TAB
3697 return (AS1 (lsr,%0) CR_TAB
3704 if (test_hard_reg_class (LD_REGS, operands[0]))
3707 return (AS1 (swap,%0) CR_TAB
3713 return (AS1 (lsr,%0) CR_TAB
3722 return (AS1 (rol,%0) CR_TAB
3727 else if (CONSTANT_P (operands[2]))
3728 fatal_insn ("internal compiler error. Incorrect shift:", insn);
3730 out_shift_with_cnt (AS1 (lsr,%0),
3731 insn, operands, len, 1);
3735 /* 16bit logic shift right ((unsigned short)x >> i) */
3738 lshrhi3_out (rtx insn, rtx operands[], int *len)
3740 if (GET_CODE (operands[2]) == CONST_INT)
3742 int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
3743 int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
3750 switch (INTVAL (operands[2]))
3753 if (optimize_size && scratch)
3758 return (AS1 (swap,%B0) CR_TAB
3759 AS1 (swap,%A0) CR_TAB
3760 AS2 (andi,%A0,0x0f) CR_TAB
3761 AS2 (eor,%A0,%B0) CR_TAB
3762 AS2 (andi,%B0,0x0f) CR_TAB
3768 return (AS1 (swap,%B0) CR_TAB
3769 AS1 (swap,%A0) CR_TAB
3770 AS2 (ldi,%3,0x0f) CR_TAB
3771 AS2 (and,%A0,%3) CR_TAB
3772 AS2 (eor,%A0,%B0) CR_TAB
3773 AS2 (and,%B0,%3) CR_TAB
3776 break; /* optimize_size ? 6 : 8 */
3780 break; /* scratch ? 5 : 6 */
3784 return (AS1 (lsr,%B0) CR_TAB
3785 AS1 (ror,%A0) CR_TAB
3786 AS1 (swap,%B0) CR_TAB
3787 AS1 (swap,%A0) CR_TAB
3788 AS2 (andi,%A0,0x0f) CR_TAB
3789 AS2 (eor,%A0,%B0) CR_TAB
3790 AS2 (andi,%B0,0x0f) CR_TAB
3796 return (AS1 (lsr,%B0) CR_TAB
3797 AS1 (ror,%A0) CR_TAB
3798 AS1 (swap,%B0) CR_TAB
3799 AS1 (swap,%A0) CR_TAB
3800 AS2 (ldi,%3,0x0f) CR_TAB
3801 AS2 (and,%A0,%3) CR_TAB
3802 AS2 (eor,%A0,%B0) CR_TAB
3803 AS2 (and,%B0,%3) CR_TAB
3810 break; /* scratch ? 5 : 6 */
3812 return (AS1 (clr,__tmp_reg__) CR_TAB
3813 AS1 (lsl,%A0) CR_TAB
3814 AS1 (rol,%B0) CR_TAB
3815 AS1 (rol,__tmp_reg__) CR_TAB
3816 AS1 (lsl,%A0) CR_TAB
3817 AS1 (rol,%B0) CR_TAB
3818 AS1 (rol,__tmp_reg__) CR_TAB
3819 AS2 (mov,%A0,%B0) CR_TAB
3820 AS2 (mov,%B0,__tmp_reg__));
3824 return (AS1 (lsl,%A0) CR_TAB
3825 AS2 (mov,%A0,%B0) CR_TAB
3826 AS1 (rol,%A0) CR_TAB
3827 AS2 (sbc,%B0,%B0) CR_TAB
3831 if (true_regnum (operands[0]) != true_regnum (operands[1]) + 1)
3832 return *len = 2, (AS2 (mov,%A0,%B1) CR_TAB
3835 return *len = 1, AS1 (clr,%B0);
3839 return (AS2 (mov,%A0,%B0) CR_TAB
3840 AS1 (clr,%B0) CR_TAB
3845 return (AS2 (mov,%A0,%B0) CR_TAB
3846 AS1 (clr,%B0) CR_TAB
3847 AS1 (lsr,%A0) CR_TAB
3852 return (AS2 (mov,%A0,%B0) CR_TAB
3853 AS1 (clr,%B0) CR_TAB
3854 AS1 (lsr,%A0) CR_TAB
3855 AS1 (lsr,%A0) CR_TAB
3862 return (AS2 (mov,%A0,%B0) CR_TAB
3863 AS1 (clr,%B0) CR_TAB
3864 AS1 (swap,%A0) CR_TAB
3865 AS2 (andi,%A0,0x0f));
3870 return (AS2 (mov,%A0,%B0) CR_TAB
3871 AS1 (clr,%B0) CR_TAB
3872 AS1 (swap,%A0) CR_TAB
3873 AS2 (ldi,%3,0x0f) CR_TAB
3877 return (AS2 (mov,%A0,%B0) CR_TAB
3878 AS1 (clr,%B0) CR_TAB
3879 AS1 (lsr,%A0) CR_TAB
3880 AS1 (lsr,%A0) CR_TAB
3881 AS1 (lsr,%A0) CR_TAB
3888 return (AS2 (mov,%A0,%B0) CR_TAB
3889 AS1 (clr,%B0) CR_TAB
3890 AS1 (swap,%A0) CR_TAB
3891 AS1 (lsr,%A0) CR_TAB
3892 AS2 (andi,%A0,0x07));
3894 if (AVR_ENHANCED && scratch)
3897 return (AS2 (ldi,%3,0x08) CR_TAB
3898 AS2 (mul,%B0,%3) CR_TAB
3899 AS2 (mov,%A0,r1) CR_TAB
3900 AS1 (clr,%B0) CR_TAB
3901 AS1 (clr,__zero_reg__));
3903 if (optimize_size && scratch)
3908 return (AS2 (mov,%A0,%B0) CR_TAB
3909 AS1 (clr,%B0) CR_TAB
3910 AS1 (swap,%A0) CR_TAB
3911 AS1 (lsr,%A0) CR_TAB
3912 AS2 (ldi,%3,0x07) CR_TAB
3918 return ("set" CR_TAB
3919 AS2 (bld,r1,3) CR_TAB
3920 AS2 (mul,%B0,r1) CR_TAB
3921 AS2 (mov,%A0,r1) CR_TAB
3922 AS1 (clr,%B0) CR_TAB
3923 AS1 (clr,__zero_reg__));
3926 return (AS2 (mov,%A0,%B0) CR_TAB
3927 AS1 (clr,%B0) CR_TAB
3928 AS1 (lsr,%A0) CR_TAB
3929 AS1 (lsr,%A0) CR_TAB
3930 AS1 (lsr,%A0) CR_TAB
3931 AS1 (lsr,%A0) CR_TAB
3935 if (AVR_ENHANCED && ldi_ok)
3938 return (AS2 (ldi,%A0,0x04) CR_TAB
3939 AS2 (mul,%B0,%A0) CR_TAB
3940 AS2 (mov,%A0,r1) CR_TAB
3941 AS1 (clr,%B0) CR_TAB
3942 AS1 (clr,__zero_reg__));
3944 if (AVR_ENHANCED && scratch)
3947 return (AS2 (ldi,%3,0x04) CR_TAB
3948 AS2 (mul,%B0,%3) CR_TAB
3949 AS2 (mov,%A0,r1) CR_TAB
3950 AS1 (clr,%B0) CR_TAB
3951 AS1 (clr,__zero_reg__));
3953 if (optimize_size && ldi_ok)
3956 return (AS2 (mov,%A0,%B0) CR_TAB
3957 AS2 (ldi,%B0,6) "\n1:\t"
3958 AS1 (lsr,%A0) CR_TAB
3959 AS1 (dec,%B0) CR_TAB
3962 if (optimize_size && scratch)
3965 return (AS1 (clr,%A0) CR_TAB
3966 AS1 (lsl,%B0) CR_TAB
3967 AS1 (rol,%A0) CR_TAB
3968 AS1 (lsl,%B0) CR_TAB
3969 AS1 (rol,%A0) CR_TAB
3974 return (AS1 (clr,%A0) CR_TAB
3975 AS1 (lsl,%B0) CR_TAB
3976 AS1 (rol,%A0) CR_TAB
3981 out_shift_with_cnt ((AS1 (lsr,%B0) CR_TAB
3983 insn, operands, len, 2);
3987 /* 32bit logic shift right ((unsigned int)x >> i) */
3990 lshrsi3_out (rtx insn, rtx operands[], int *len)
3992 if (GET_CODE (operands[2]) == CONST_INT)
4000 switch (INTVAL (operands[2]))
4004 int reg0 = true_regnum (operands[0]);
4005 int reg1 = true_regnum (operands[1]);
4008 return (AS2 (mov,%A0,%B1) CR_TAB
4009 AS2 (mov,%B0,%C1) CR_TAB
4010 AS2 (mov,%C0,%D1) CR_TAB
4012 else if (reg0 == reg1 + 1)
4013 return *len = 1, AS1 (clr,%D0);
4015 return (AS1 (clr,%D0) CR_TAB
4016 AS2 (mov,%C0,%D1) CR_TAB
4017 AS2 (mov,%B0,%C1) CR_TAB
4023 int reg0 = true_regnum (operands[0]);
4024 int reg1 = true_regnum (operands[1]);
4026 if (AVR_ENHANCED && (reg0 != reg1 + 2))
4029 return (AS2 (movw,%A0,%C1) CR_TAB
4030 AS1 (clr,%C0) CR_TAB
4033 if (reg0 <= reg1 + 1)
4034 return (AS2 (mov,%A0,%C1) CR_TAB
4035 AS2 (mov,%B0,%D1) CR_TAB
4036 AS1 (clr,%C0) CR_TAB
4038 else if (reg0 == reg1 + 2)
4039 return *len = 2, (AS1 (clr,%C0) CR_TAB
4042 return (AS2 (mov,%B0,%D1) CR_TAB
4043 AS2 (mov,%A0,%C1) CR_TAB
4044 AS1 (clr,%C0) CR_TAB
4049 if (true_regnum (operands[0]) != true_regnum (operands[1]) + 3)
4050 return *len = 4, (AS2 (mov,%A0,%D1) CR_TAB
4051 AS1 (clr,%B0) CR_TAB
4052 AS1 (clr,%C0) CR_TAB
4055 return *len = 3, (AS1 (clr,%B0) CR_TAB
4056 AS1 (clr,%C0) CR_TAB
4061 return (AS1 (clr,%A0) CR_TAB
4062 AS2 (sbrc,%D0,7) CR_TAB
4063 AS1 (inc,%A0) CR_TAB
4064 AS1 (clr,%B0) CR_TAB
4065 AS1 (clr,%C0) CR_TAB
4070 out_shift_with_cnt ((AS1 (lsr,%D0) CR_TAB
4071 AS1 (ror,%C0) CR_TAB
4072 AS1 (ror,%B0) CR_TAB
4074 insn, operands, len, 4);
4078 /* Modifies the length assigned to instruction INSN
4079 LEN is the initially computed length of the insn. */
4082 adjust_insn_length (rtx insn, int len)
4084 rtx patt = PATTERN (insn);
4087 if (GET_CODE (patt) == SET)
4090 op[1] = SET_SRC (patt);
4091 op[0] = SET_DEST (patt);
4092 if (general_operand (op[1], VOIDmode)
4093 && general_operand (op[0], VOIDmode))
4095 switch (GET_MODE (op[0]))
4098 output_movqi (insn, op, &len);
4101 output_movhi (insn, op, &len);
4105 output_movsisf (insn, op, &len);
4111 else if (op[0] == cc0_rtx && REG_P (op[1]))
4113 switch (GET_MODE (op[1]))
4115 case HImode: out_tsthi (insn,&len); break;
4116 case SImode: out_tstsi (insn,&len); break;
4120 else if (GET_CODE (op[1]) == AND)
4122 if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
4124 HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
4125 if (GET_MODE (op[1]) == SImode)
4126 len = (((mask & 0xff) != 0xff)
4127 + ((mask & 0xff00) != 0xff00)
4128 + ((mask & 0xff0000L) != 0xff0000L)
4129 + ((mask & 0xff000000L) != 0xff000000L));
4130 else if (GET_MODE (op[1]) == HImode)
4131 len = (((mask & 0xff) != 0xff)
4132 + ((mask & 0xff00) != 0xff00));
4135 else if (GET_CODE (op[1]) == IOR)
4137 if (GET_CODE (XEXP (op[1],1)) == CONST_INT)
4139 HOST_WIDE_INT mask = INTVAL (XEXP (op[1],1));
4140 if (GET_MODE (op[1]) == SImode)
4141 len = (((mask & 0xff) != 0)
4142 + ((mask & 0xff00) != 0)
4143 + ((mask & 0xff0000L) != 0)
4144 + ((mask & 0xff000000L) != 0));
4145 else if (GET_MODE (op[1]) == HImode)
4146 len = (((mask & 0xff) != 0)
4147 + ((mask & 0xff00) != 0));
4151 set = single_set (insn);
4156 op[1] = SET_SRC (set);
4157 op[0] = SET_DEST (set);
4159 if (GET_CODE (patt) == PARALLEL
4160 && general_operand (op[1], VOIDmode)
4161 && general_operand (op[0], VOIDmode))
4163 if (XVECLEN (patt, 0) == 2)
4164 op[2] = XVECEXP (patt, 0, 1);
4166 switch (GET_MODE (op[0]))
4172 output_reload_inhi (insn, op, &len);
4176 output_reload_insisf (insn, op, &len);
4182 else if (GET_CODE (op[1]) == ASHIFT
4183 || GET_CODE (op[1]) == ASHIFTRT
4184 || GET_CODE (op[1]) == LSHIFTRT)
4188 ops[1] = XEXP (op[1],0);
4189 ops[2] = XEXP (op[1],1);
4190 switch (GET_CODE (op[1]))
4193 switch (GET_MODE (op[0]))
4195 case QImode: ashlqi3_out (insn,ops,&len); break;
4196 case HImode: ashlhi3_out (insn,ops,&len); break;
4197 case SImode: ashlsi3_out (insn,ops,&len); break;
4202 switch (GET_MODE (op[0]))
4204 case QImode: ashrqi3_out (insn,ops,&len); break;
4205 case HImode: ashrhi3_out (insn,ops,&len); break;
4206 case SImode: ashrsi3_out (insn,ops,&len); break;
4211 switch (GET_MODE (op[0]))
4213 case QImode: lshrqi3_out (insn,ops,&len); break;
4214 case HImode: lshrhi3_out (insn,ops,&len); break;
4215 case SImode: lshrsi3_out (insn,ops,&len); break;
4227 /* Return nonzero if register REG dead after INSN. */
4230 reg_unused_after (rtx insn, rtx reg)
4232 return (dead_or_set_p (insn, reg)
4233 || (REG_P(reg) && _reg_unused_after (insn, reg)));
4236 /* Return nonzero if REG is not used after INSN.
4237 We assume REG is a reload reg, and therefore does
4238 not live past labels. It may live past calls or jumps though. */
4241 _reg_unused_after (rtx insn, rtx reg)
4246 /* If the reg is set by this instruction, then it is safe for our
4247 case. Disregard the case where this is a store to memory, since
4248 we are checking a register used in the store address. */
4249 set = single_set (insn);
4250 if (set && GET_CODE (SET_DEST (set)) != MEM
4251 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4254 while ((insn = NEXT_INSN (insn)))
4257 code = GET_CODE (insn);
4260 /* If this is a label that existed before reload, then the register
4261 if dead here. However, if this is a label added by reorg, then
4262 the register may still be live here. We can't tell the difference,
4263 so we just ignore labels completely. */
4264 if (code == CODE_LABEL)
4272 if (code == JUMP_INSN)
4275 /* If this is a sequence, we must handle them all at once.
4276 We could have for instance a call that sets the target register,
4277 and an insn in a delay slot that uses the register. In this case,
4278 we must return 0. */
4279 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4284 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
4286 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
4287 rtx set = single_set (this_insn);
4289 if (GET_CODE (this_insn) == CALL_INSN)
4291 else if (GET_CODE (this_insn) == JUMP_INSN)
4293 if (INSN_ANNULLED_BRANCH_P (this_insn))
4298 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4300 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4302 if (GET_CODE (SET_DEST (set)) != MEM)
4308 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
4313 else if (code == JUMP_INSN)
4317 if (code == CALL_INSN)
4320 for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1))
4321 if (GET_CODE (XEXP (tem, 0)) == USE
4322 && REG_P (XEXP (XEXP (tem, 0), 0))
4323 && reg_overlap_mentioned_p (reg, XEXP (XEXP (tem, 0), 0)))
4325 if (call_used_regs[REGNO (reg)])
4329 set = single_set (insn);
4331 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
4333 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
4334 return GET_CODE (SET_DEST (set)) != MEM;
4335 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
4341 /* Target hook for assembling integer objects. The AVR version needs
4342 special handling for references to certain labels. */
4345 avr_assemble_integer (rtx x, unsigned int size, int aligned_p)
4347 if (size == POINTER_SIZE / BITS_PER_UNIT && aligned_p
4348 && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (x))
4349 || GET_CODE (x) == LABEL_REF))
4351 fputs ("\t.word\tpm(", asm_out_file);
4352 output_addr_const (asm_out_file, x);
4353 fputs (")\n", asm_out_file);
4356 return default_assemble_integer (x, size, aligned_p);
4359 /* Sets section name for declaration DECL. */
4362 avr_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
4365 const char *name, *prefix;
4368 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4369 name = (* targetm.strip_name_encoding) (name);
4371 if (TREE_CODE (decl) == FUNCTION_DECL)
4373 if (flag_function_sections)
4381 if (flag_function_sections)
4383 len = strlen (name) + strlen (prefix);
4384 string = alloca (len + 1);
4385 sprintf (string, "%s%s", prefix, name);
4386 DECL_SECTION_NAME (decl) = build_string (len, string);
4391 /* The routine used to output NUL terminated strings. We use a special
4392 version of this for most svr4 targets because doing so makes the
4393 generated assembly code more compact (and thus faster to assemble)
4394 as well as more readable, especially for targets like the i386
4395 (where the only alternative is to output character sequences as
4396 comma separated lists of numbers). */
4399 gas_output_limited_string(FILE *file, const char *str)
4401 const unsigned char *_limited_str = (unsigned char *) str;
4403 fprintf (file, "%s\"", STRING_ASM_OP);
4404 for (; (ch = *_limited_str); _limited_str++)
4407 switch (escape = ESCAPES[ch])
4413 fprintf (file, "\\%03o", ch);
4417 putc (escape, file);
4421 fprintf (file, "\"\n");
4424 /* The routine used to output sequences of byte values. We use a special
4425 version of this for most svr4 targets because doing so makes the
4426 generated assembly code more compact (and thus faster to assemble)
4427 as well as more readable. Note that if we find subparts of the
4428 character sequence which end with NUL (and which are shorter than
4429 STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */
4432 gas_output_ascii(FILE *file, const char *str, size_t length)
4434 const unsigned char *_ascii_bytes = (const unsigned char *) str;
4435 const unsigned char *limit = _ascii_bytes + length;
4436 unsigned bytes_in_chunk = 0;
4437 for (; _ascii_bytes < limit; _ascii_bytes++)
4439 const unsigned char *p;
4440 if (bytes_in_chunk >= 60)
4442 fprintf (file, "\"\n");
4445 for (p = _ascii_bytes; p < limit && *p != '\0'; p++)
4447 if (p < limit && (p - _ascii_bytes) <= (signed)STRING_LIMIT)
4449 if (bytes_in_chunk > 0)
4451 fprintf (file, "\"\n");
4454 gas_output_limited_string (file, (char*)_ascii_bytes);
4461 if (bytes_in_chunk == 0)
4462 fprintf (file, "\t.ascii\t\"");
4463 switch (escape = ESCAPES[ch = *_ascii_bytes])
4470 fprintf (file, "\\%03o", ch);
4471 bytes_in_chunk += 4;
4475 putc (escape, file);
4476 bytes_in_chunk += 2;
4481 if (bytes_in_chunk > 0)
4482 fprintf (file, "\"\n");
4485 /* Return value is nonzero if pseudos that have been
4486 assigned to registers of class CLASS would likely be spilled
4487 because registers of CLASS are needed for spill registers. */
4490 class_likely_spilled_p (int c)
4492 return (c != ALL_REGS && c != ADDW_REGS);
4495 /* Valid attributes:
4496 progmem - put data to program memory;
4497 signal - make a function to be hardware interrupt. After function
4498 prologue interrupts are disabled;
4499 interrupt - make a function to be hardware interrupt. After function
4500 prologue interrupts are enabled;
4501 naked - don't generate function prologue/epilogue and `ret' command.
4503 Only `progmem' attribute valid for type. */
4505 const struct attribute_spec avr_attribute_table[] =
4507 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4508 { "progmem", 0, 0, false, false, false, avr_handle_progmem_attribute },
4509 { "signal", 0, 0, true, false, false, avr_handle_fndecl_attribute },
4510 { "interrupt", 0, 0, true, false, false, avr_handle_fndecl_attribute },
4511 { "naked", 0, 0, true, false, false, avr_handle_fndecl_attribute },
4512 { NULL, 0, 0, false, false, false, NULL }
4515 /* Handle a "progmem" attribute; arguments as in
4516 struct attribute_spec.handler. */
4518 avr_handle_progmem_attribute (tree *node, tree name,
4519 tree args ATTRIBUTE_UNUSED,
4520 int flags ATTRIBUTE_UNUSED,
4525 if (TREE_CODE (*node) == TYPE_DECL)
4527 /* This is really a decl attribute, not a type attribute,
4528 but try to handle it for GCC 3.0 backwards compatibility. */
4530 tree type = TREE_TYPE (*node);
4531 tree attr = tree_cons (name, args, TYPE_ATTRIBUTES (type));
4532 tree newtype = build_type_attribute_variant (type, attr);
4534 TYPE_MAIN_VARIANT (newtype) = TYPE_MAIN_VARIANT (type);
4535 TREE_TYPE (*node) = newtype;
4536 *no_add_attrs = true;
4538 else if (TREE_STATIC (*node) || DECL_EXTERNAL (*node))
4540 if (DECL_INITIAL (*node) == NULL_TREE && !DECL_EXTERNAL (*node))
4542 warning ("only initialized variables can be placed into "
4543 "program memory area");
4544 *no_add_attrs = true;
4549 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4550 *no_add_attrs = true;
4557 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4558 struct attribute_spec.handler. */
4561 avr_handle_fndecl_attribute (tree *node, tree name,
4562 tree args ATTRIBUTE_UNUSED,
4563 int flags ATTRIBUTE_UNUSED,
4566 if (TREE_CODE (*node) != FUNCTION_DECL)
4568 warning ("`%s' attribute only applies to functions",
4569 IDENTIFIER_POINTER (name));
4570 *no_add_attrs = true;
4576 /* Look for attribute `progmem' in DECL
4577 if found return 1, otherwise 0. */
4580 avr_progmem_p (tree decl, tree attributes)
4584 if (TREE_CODE (decl) != VAR_DECL)
4588 != lookup_attribute ("progmem", attributes))
4594 while (TREE_CODE (a) == ARRAY_TYPE);
4596 if (a == error_mark_node)
4599 if (NULL_TREE != lookup_attribute ("progmem", TYPE_ATTRIBUTES (a)))
4605 /* Add the section attribute if the variable is in progmem. */
4608 avr_insert_attributes (tree node, tree *attributes)
4610 if (TREE_CODE (node) == VAR_DECL
4611 && (TREE_STATIC (node) || DECL_EXTERNAL (node))
4612 && avr_progmem_p (node, *attributes))
4614 static const char dsec[] = ".progmem.data";
4615 *attributes = tree_cons (get_identifier ("section"),
4616 build_tree_list (NULL, build_string (strlen (dsec), dsec)),
4619 /* ??? This seems sketchy. Why can't the user declare the
4620 thing const in the first place? */
4621 TREE_READONLY (node) = 1;
4626 avr_section_type_flags (tree decl, const char *name, int reloc)
4628 unsigned int flags = default_section_type_flags (decl, name, reloc);
4630 if (strncmp (name, ".noinit", 7) == 0)
4632 if (decl && TREE_CODE (decl) == VAR_DECL
4633 && DECL_INITIAL (decl) == NULL_TREE)
4634 flags |= SECTION_BSS; /* @nobits */
4636 warning ("only uninitialized variables can be placed in the "
4643 /* Outputs some appropriate text to go at the start of an assembler
4647 avr_file_start (void)
4650 error ("MCU `%s' supported for assembler only", avr_mcu_name);
4652 default_file_start ();
4654 fprintf (asm_out_file, "\t.arch %s\n", avr_mcu_name);
4655 fputs ("__SREG__ = 0x3f\n"
4657 "__SP_L__ = 0x3d\n", asm_out_file);
4659 fputs ("__tmp_reg__ = 0\n"
4660 "__zero_reg__ = 1\n", asm_out_file);
4662 /* FIXME: output these only if there is anything in the .data / .bss
4663 sections - some code size could be saved by not linking in the
4664 initialization code from libgcc if one or both sections are empty. */
4665 fputs ("\t.global __do_copy_data\n", asm_out_file);
4666 fputs ("\t.global __do_clear_bss\n", asm_out_file);
4668 commands_in_file = 0;
4669 commands_in_prologues = 0;
4670 commands_in_epilogues = 0;
4673 /* Outputs to the stdio stream FILE some
4674 appropriate text to go at the end of an assembler file. */
4679 fputs ("/* File ", asm_out_file);
4680 output_quoted_string (asm_out_file, main_input_filename);
4681 fprintf (asm_out_file,
4682 ": code %4d = 0x%04x (%4d), prologues %3d, epilogues %3d */\n",
4685 commands_in_file - commands_in_prologues - commands_in_epilogues,
4686 commands_in_prologues, commands_in_epilogues);
4689 /* Choose the order in which to allocate hard registers for
4690 pseudo-registers local to a basic block.
4692 Store the desired register order in the array `reg_alloc_order'.
4693 Element 0 should be the register to allocate first; element 1, the
4694 next register; and so on. */
4697 order_regs_for_local_alloc (void)
4700 static const int order_0[] = {
4708 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4712 static const int order_1[] = {
4720 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4724 static const int order_2[] = {
4733 15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4738 const int *order = (TARGET_ORDER_1 ? order_1 :
4739 TARGET_ORDER_2 ? order_2 :
4741 for (i=0; i < ARRAY_SIZE (order_0); ++i)
4742 reg_alloc_order[i] = order[i];
4745 /* Calculate the cost of X code of the expression in which it is contained,
4746 found in OUTER_CODE */
4749 default_rtx_costs (rtx X, enum rtx_code code, enum rtx_code outer_code)
4756 cost = 2 * GET_MODE_SIZE (GET_MODE (X));
4759 if (outer_code != SET)
4761 if (GET_CODE (XEXP (X,0)) == SYMBOL_REF)
4762 cost += 2 * GET_MODE_SIZE (GET_MODE (X));
4764 cost += GET_MODE_SIZE (GET_MODE (X));
4770 if (outer_code == SET)
4771 cost = GET_MODE_SIZE (GET_MODE (X));
4773 cost = -GET_MODE_SIZE (GET_MODE (X));
4776 if (outer_code == SET)
4777 cost = GET_MODE_SIZE (GET_MODE (X));
4783 if (outer_code == SET)
4785 if (X == stack_pointer_rtx)
4787 else if (GET_CODE (XEXP (X,1)) == CONST_INT)
4788 cost = (INTVAL (XEXP (X,1)) <= 63 ? 1 :
4789 GET_MODE_SIZE (GET_MODE (X)));
4791 cost = GET_MODE_SIZE (GET_MODE (X));
4795 if (GET_CODE (XEXP (X,1)) == CONST_INT)
4796 cost = GET_MODE_SIZE (GET_MODE (XEXP (X,0)));
4805 avr_rtx_costs (rtx x, int code, int outer_code, int *total)
4812 if (outer_code == PLUS
4813 || outer_code == IOR
4814 || outer_code == AND
4815 || outer_code == MINUS
4816 || outer_code == SET
4822 if (outer_code == COMPARE
4824 && INTVAL (x) <= 255)
4839 cst = default_rtx_costs (x, code, outer_code);
4851 /* Calculate the cost of a memory address. */
4854 avr_address_cost (rtx x)
4856 if (GET_CODE (x) == PLUS
4857 && GET_CODE (XEXP (x,1)) == CONST_INT
4858 && (REG_P (XEXP (x,0)) || GET_CODE (XEXP (x,0)) == SUBREG)
4859 && INTVAL (XEXP (x,1)) >= 61)
4861 if (CONSTANT_ADDRESS_P (x))
4863 if (avr_io_address_p (x, 1))
4870 /* EXTRA_CONSTRAINT helper */
4873 extra_constraint (rtx x, int c)
4876 && GET_CODE (x) == MEM
4877 && GET_CODE (XEXP (x,0)) == PLUS)
4879 if (TARGET_ALL_DEBUG)
4881 fprintf (stderr, ("extra_constraint:\n"
4882 "reload_completed: %d\n"
4883 "reload_in_progress: %d\n"),
4884 reload_completed, reload_in_progress);
4887 if (GET_CODE (x) == MEM
4888 && GET_CODE (XEXP (x,0)) == PLUS
4889 && REG_P (XEXP (XEXP (x,0), 0))
4890 && GET_CODE (XEXP (XEXP (x,0), 1)) == CONST_INT
4891 && (INTVAL (XEXP (XEXP (x,0), 1))
4892 <= MAX_LD_OFFSET (GET_MODE (x))))
4894 rtx xx = XEXP (XEXP (x,0), 0);
4895 int regno = REGNO (xx);
4896 if (TARGET_ALL_DEBUG)
4898 fprintf (stderr, ("extra_constraint:\n"
4899 "reload_completed: %d\n"
4900 "reload_in_progress: %d\n"),
4901 reload_completed, reload_in_progress);
4904 if (regno >= FIRST_PSEUDO_REGISTER)
4905 return 1; /* allocate pseudos */
4906 else if (regno == REG_Z || regno == REG_Y)
4907 return 1; /* strictly check */
4908 else if (xx == frame_pointer_rtx
4909 || xx == arg_pointer_rtx)
4910 return 1; /* XXX frame & arg pointer checks */
4916 /* Convert condition code CONDITION to the valid AVR condition code. */
4919 avr_normalize_condition (RTX_CODE condition)
4936 /* This function optimizes conditional jumps. */
4943 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4945 if (! (GET_CODE (insn) == INSN
4946 || GET_CODE (insn) == CALL_INSN
4947 || GET_CODE (insn) == JUMP_INSN)
4948 || !single_set (insn))
4951 pattern = PATTERN (insn);
4953 if (GET_CODE (pattern) == PARALLEL)
4954 pattern = XVECEXP (pattern, 0, 0);
4955 if (GET_CODE (pattern) == SET
4956 && SET_DEST (pattern) == cc0_rtx
4957 && compare_diff_p (insn))
4959 if (GET_CODE (SET_SRC (pattern)) == COMPARE)
4961 /* Now we work under compare insn. */
4963 pattern = SET_SRC (pattern);
4964 if (true_regnum (XEXP (pattern,0)) >= 0
4965 && true_regnum (XEXP (pattern,1)) >= 0 )
4967 rtx x = XEXP (pattern,0);
4968 rtx next = next_real_insn (insn);
4969 rtx pat = PATTERN (next);
4970 rtx src = SET_SRC (pat);
4971 rtx t = XEXP (src,0);
4972 PUT_CODE (t, swap_condition (GET_CODE (t)));
4973 XEXP (pattern,0) = XEXP (pattern,1);
4974 XEXP (pattern,1) = x;
4975 INSN_CODE (next) = -1;
4977 else if (true_regnum (XEXP (pattern,0)) >= 0
4978 && GET_CODE (XEXP (pattern,1)) == CONST_INT)
4980 rtx x = XEXP (pattern,1);
4981 rtx next = next_real_insn (insn);
4982 rtx pat = PATTERN (next);
4983 rtx src = SET_SRC (pat);
4984 rtx t = XEXP (src,0);
4985 enum machine_mode mode = GET_MODE (XEXP (pattern, 0));
4987 if (avr_simplify_comparison_p (mode, GET_CODE (t), x))
4989 XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode);
4990 PUT_CODE (t, avr_normalize_condition (GET_CODE (t)));
4991 INSN_CODE (next) = -1;
4992 INSN_CODE (insn) = -1;
4996 else if (true_regnum (SET_SRC (pattern)) >= 0)
4998 /* This is a tst insn */
4999 rtx next = next_real_insn (insn);
5000 rtx pat = PATTERN (next);
5001 rtx src = SET_SRC (pat);
5002 rtx t = XEXP (src,0);
5004 PUT_CODE (t, swap_condition (GET_CODE (t)));
5005 SET_SRC (pattern) = gen_rtx_NEG (GET_MODE (SET_SRC (pattern)),
5007 INSN_CODE (next) = -1;
5008 INSN_CODE (insn) = -1;
5014 /* Returns register number for function return value.*/
5017 avr_ret_register (void)
5022 /* Ceate an RTX representing the place where a
5023 library function returns a value of mode MODE. */
5026 avr_libcall_value (enum machine_mode mode)
5028 int offs = GET_MODE_SIZE (mode);
5031 return gen_rtx_REG (mode, RET_REGISTER + 2 - offs);
5034 /* Create an RTX representing the place where a
5035 function returns a value of data type VALTYPE. */
5038 avr_function_value (tree type, tree func ATTRIBUTE_UNUSED)
5042 if (TYPE_MODE (type) != BLKmode)
5043 return avr_libcall_value (TYPE_MODE (type));
5045 offs = int_size_in_bytes (type);
5048 if (offs > 2 && offs < GET_MODE_SIZE (SImode))
5049 offs = GET_MODE_SIZE (SImode);
5050 else if (offs > GET_MODE_SIZE (SImode) && offs < GET_MODE_SIZE (DImode))
5051 offs = GET_MODE_SIZE (DImode);
5053 return gen_rtx_REG (BLKmode, RET_REGISTER + 2 - offs);
5056 /* Returns nonzero if the number MASK has only one bit set. */
5059 mask_one_bit_p (HOST_WIDE_INT mask)
5062 unsigned HOST_WIDE_INT n=mask;
5063 for (i = 0; i < 32; ++i)
5065 if (n & 0x80000000L)
5067 if (n & 0x7fffffffL)
5078 /* Places additional restrictions on the register class to
5079 use when it is necessary to copy value X into a register
5083 preferred_reload_class (rtx x ATTRIBUTE_UNUSED, enum reg_class class)
5089 test_hard_reg_class (enum reg_class class, rtx x)
5091 int regno = true_regnum (x);
5095 if (TEST_HARD_REG_CLASS (class, regno))
5103 jump_over_one_insn_p (rtx insn, rtx dest)
5105 int uid = INSN_UID (GET_CODE (dest) == LABEL_REF
5108 int jump_addr = INSN_ADDRESSES (INSN_UID (insn));
5109 int dest_addr = INSN_ADDRESSES (uid);
5110 return dest_addr - jump_addr == get_attr_length (insn) + 1;
5113 /* Returns 1 if a value of mode MODE can be stored starting with hard
5114 register number REGNO. On the enhanced core, anything larger than
5115 1 byte must start in even numbered register for "movw" to work
5116 (this way we don't have to check for odd registers everywhere). */
5119 avr_hard_regno_mode_ok (int regno, enum machine_mode mode)
5121 /* Bug workaround: recog.c (peep2_find_free_register) and probably
5122 a few other places assume that the frame pointer is a single hard
5123 register, so r29 may be allocated and overwrite the high byte of
5124 the frame pointer. Do not allow any value to start in r29. */
5125 if (regno == REG_Y + 1)
5128 /* Reload can use r28:r29 for reload register and for frame pointer
5129 in one insn. It's wrong. We must disable it. */
5130 if (mode != Pmode && reload_in_progress && frame_pointer_required_p ()
5131 && regno <= REG_Y && (regno + GET_MODE_SIZE (mode)) >= (REG_Y + 1))
5136 /* if (regno < 24 && !AVR_ENHANCED)
5138 return !(regno & 1);
5141 /* Returns 1 if X is a valid address for an I/O register of size SIZE
5142 (1 or 2). Used for lds/sts -> in/out optimization. Add 0x20 to SIZE
5143 to check for the lower half of I/O space (for cbi/sbi/sbic/sbis). */
5146 avr_io_address_p (rtx x, int size)
5148 return (optimize > 0 && GET_CODE (x) == CONST_INT
5149 && INTVAL (x) >= 0x20 && INTVAL (x) <= 0x60 - size);
5152 /* Returns nonzero (bit number + 1) if X, or -X, is a constant power of 2. */
5155 const_int_pow2_p (rtx x)
5157 if (GET_CODE (x) == CONST_INT)
5159 HOST_WIDE_INT d = INTVAL (x);
5160 HOST_WIDE_INT abs_d = (d >= 0) ? d : -d;
5161 return exact_log2 (abs_d) + 1;
5167 output_reload_inhi (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
5173 if (GET_CODE (operands[1]) == CONST_INT)
5175 int val = INTVAL (operands[1]);
5176 if ((val & 0xff) == 0)
5179 return (AS2 (mov,%A0,__zero_reg__) CR_TAB
5180 AS2 (ldi,%2,hi8(%1)) CR_TAB
5183 else if ((val & 0xff00) == 0)
5186 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5187 AS2 (mov,%A0,%2) CR_TAB
5188 AS2 (mov,%B0,__zero_reg__));
5190 else if ((val & 0xff) == ((val & 0xff00) >> 8))
5193 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5194 AS2 (mov,%A0,%2) CR_TAB
5199 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
5200 AS2 (mov,%A0,%2) CR_TAB
5201 AS2 (ldi,%2,hi8(%1)) CR_TAB
5207 output_reload_insisf (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
5209 rtx src = operands[1];
5210 int cnst = (GET_CODE (src) == CONST_INT);
5215 *len = 4 + ((INTVAL (src) & 0xff) != 0)
5216 + ((INTVAL (src) & 0xff00) != 0)
5217 + ((INTVAL (src) & 0xff0000) != 0)
5218 + ((INTVAL (src) & 0xff000000) != 0);
5225 if (cnst && ((INTVAL (src) & 0xff) == 0))
5226 output_asm_insn (AS2 (mov, %A0, __zero_reg__), operands);
5229 output_asm_insn (AS2 (ldi, %2, lo8(%1)), operands);
5230 output_asm_insn (AS2 (mov, %A0, %2), operands);
5232 if (cnst && ((INTVAL (src) & 0xff00) == 0))
5233 output_asm_insn (AS2 (mov, %B0, __zero_reg__), operands);
5236 output_asm_insn (AS2 (ldi, %2, hi8(%1)), operands);
5237 output_asm_insn (AS2 (mov, %B0, %2), operands);
5239 if (cnst && ((INTVAL (src) & 0xff0000) == 0))
5240 output_asm_insn (AS2 (mov, %C0, __zero_reg__), operands);
5243 output_asm_insn (AS2 (ldi, %2, hlo8(%1)), operands);
5244 output_asm_insn (AS2 (mov, %C0, %2), operands);
5246 if (cnst && ((INTVAL (src) & 0xff000000) == 0))
5247 output_asm_insn (AS2 (mov, %D0, __zero_reg__), operands);
5250 output_asm_insn (AS2 (ldi, %2, hhi8(%1)), operands);
5251 output_asm_insn (AS2 (mov, %D0, %2), operands);
5257 avr_output_bld (rtx operands[], int bit_nr)
5259 static char s[] = "bld %A0,0";
5261 s[5] = 'A' + (bit_nr >> 3);
5262 s[8] = '0' + (bit_nr & 7);
5263 output_asm_insn (s, operands);
5267 avr_output_addr_vec_elt (FILE *stream, int value)
5270 fprintf (stream, "\t.word pm(.L%d)\n", value);
5272 fprintf (stream, "\trjmp .L%d\n", value);
5277 /* Returns 1 if SCRATCH are safe to be allocated as a scratch
5278 registers (for a define_peephole2) in the current function. */
5281 avr_peep2_scratch_safe (rtx scratch)
5283 if ((interrupt_function_p (current_function_decl)
5284 || signal_function_p (current_function_decl))
5285 && leaf_function_p ())
5287 int first_reg = true_regnum (scratch);
5288 int last_reg = first_reg + GET_MODE_SIZE (GET_MODE (scratch)) - 1;
5291 for (reg = first_reg; reg <= last_reg; reg++)
5293 if (!regs_ever_live[reg])
5300 /* Output a branch that tests a single bit of a register (QI, HI or SImode)
5301 or memory location in the I/O space (QImode only).
5303 Operand 0: comparison operator (must be EQ or NE, compare bit to zero).
5304 Operand 1: register operand to test, or CONST_INT memory address.
5305 Operand 2: bit number (for QImode operand) or mask (HImode, SImode).
5306 Operand 3: label to jump to if the test is true. */
5309 avr_out_sbxx_branch (rtx insn, rtx operands[])
5311 enum rtx_code comp = GET_CODE (operands[0]);
5312 int long_jump = (get_attr_length (insn) >= 4);
5313 int reverse = long_jump || jump_over_one_insn_p (insn, operands[3]);
5317 else if (comp == LT)
5321 comp = reverse_condition (comp);
5323 if (GET_CODE (operands[1]) == CONST_INT)
5325 if (INTVAL (operands[1]) < 0x40)
5328 output_asm_insn (AS2 (sbis,%1-0x20,%2), operands);
5330 output_asm_insn (AS2 (sbic,%1-0x20,%2), operands);
5334 output_asm_insn (AS2 (in,__tmp_reg__,%1-0x20), operands);
5336 output_asm_insn (AS2 (sbrs,__tmp_reg__,%2), operands);
5338 output_asm_insn (AS2 (sbrc,__tmp_reg__,%2), operands);
5341 else /* GET_CODE (operands[1]) == REG */
5343 if (GET_MODE (operands[1]) == QImode)
5346 output_asm_insn (AS2 (sbrs,%1,%2), operands);
5348 output_asm_insn (AS2 (sbrc,%1,%2), operands);
5350 else /* HImode or SImode */
5352 static char buf[] = "sbrc %A1,0";
5353 int bit_nr = exact_log2 (INTVAL (operands[2])
5354 & GET_MODE_MASK (GET_MODE (operands[1])));
5356 buf[3] = (comp == EQ) ? 's' : 'c';
5357 buf[6] = 'A' + (bit_nr >> 3);
5358 buf[9] = '0' + (bit_nr & 7);
5359 output_asm_insn (buf, operands);
5364 return (AS1 (rjmp,.+4) CR_TAB
5367 return AS1 (rjmp,%3);
5371 /* Worker function for TARGET_ASM_CONSTRUCTOR. */
5374 avr_asm_out_ctor (rtx symbol, int priority)
5376 fputs ("\t.global __do_global_ctors\n", asm_out_file);
5377 default_ctor_section_asm_out_constructor (symbol, priority);
5380 /* Worker function for TARGET_ASM_DESTRUCTOR. */
5383 avr_asm_out_dtor (rtx symbol, int priority)
5385 fputs ("\t.global __do_global_dtors\n", asm_out_file);
5386 default_dtor_section_asm_out_destructor (symbol, priority);
5389 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5392 avr_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5394 if (TYPE_MODE (type) == BLKmode)
5396 HOST_WIDE_INT size = int_size_in_bytes (type);
5397 return (size == -1 || size > 8);