1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 (define_insn "*thumb2_incscc"
28 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
29 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
30 [(match_operand:CC 3 "cc_register" "") (const_int 0)])
31 (match_operand:SI 1 "s_register_operand" "0,?r")))]
34 it\\t%d2\;add%d2\\t%0, %1, #1
35 ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
36 [(set_attr "conds" "use")
37 (set_attr "length" "6,10")]
40 (define_insn "*thumb2_decscc"
41 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
42 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
43 (match_operator:SI 2 "arm_comparison_operator"
44 [(match_operand 3 "cc_register" "") (const_int 0)])))]
47 it\\t%d2\;sub%d2\\t%0, %1, #1
48 ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
49 [(set_attr "conds" "use")
50 (set_attr "length" "6,10")]
53 ;; Thumb-2 only allows shift by constant on data processing instructions
54 (define_insn "*thumb_andsi_not_shiftsi_si"
55 [(set (match_operand:SI 0 "s_register_operand" "=r")
56 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
57 [(match_operand:SI 2 "s_register_operand" "r")
58 (match_operand:SI 3 "const_int_operand" "M")]))
59 (match_operand:SI 1 "s_register_operand" "r")))]
61 "bic%?\\t%0, %1, %2%S4"
62 [(set_attr "predicable" "yes")
63 (set_attr "shift" "2")
64 (set_attr "type" "alu_shift")]
67 (define_insn "*thumb2_smaxsi3"
68 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
69 (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
70 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
71 (clobber (reg:CC CC_REGNUM))]
74 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
75 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
76 cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
77 [(set_attr "conds" "clob")
78 (set_attr "length" "10,10,14")]
81 (define_insn "*thumb2_sminsi3"
82 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
83 (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
84 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
85 (clobber (reg:CC CC_REGNUM))]
88 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
89 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
90 cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
91 [(set_attr "conds" "clob")
92 (set_attr "length" "10,10,14")]
95 (define_insn "*thumb32_umaxsi3"
96 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
97 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
98 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
99 (clobber (reg:CC CC_REGNUM))]
102 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
103 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
104 cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
105 [(set_attr "conds" "clob")
106 (set_attr "length" "10,10,14")]
109 (define_insn "*thumb2_uminsi3"
110 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
111 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
112 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
113 (clobber (reg:CC CC_REGNUM))]
116 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
117 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
118 cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
119 [(set_attr "conds" "clob")
120 (set_attr "length" "10,10,14")]
123 (define_insn "*thumb2_notsi_shiftsi"
124 [(set (match_operand:SI 0 "s_register_operand" "=r")
125 (not:SI (match_operator:SI 3 "shift_operator"
126 [(match_operand:SI 1 "s_register_operand" "r")
127 (match_operand:SI 2 "const_int_operand" "M")])))]
130 [(set_attr "predicable" "yes")
131 (set_attr "shift" "1")
132 (set_attr "type" "alu_shift")]
135 (define_insn "*thumb2_notsi_shiftsi_compare0"
136 [(set (reg:CC_NOOV CC_REGNUM)
137 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
138 [(match_operand:SI 1 "s_register_operand" "r")
139 (match_operand:SI 2 "const_int_operand" "M")]))
141 (set (match_operand:SI 0 "s_register_operand" "=r")
142 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
145 [(set_attr "conds" "set")
146 (set_attr "shift" "1")
147 (set_attr "type" "alu_shift")]
150 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
151 [(set (reg:CC_NOOV CC_REGNUM)
152 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
153 [(match_operand:SI 1 "s_register_operand" "r")
154 (match_operand:SI 2 "const_int_operand" "M")]))
156 (clobber (match_scratch:SI 0 "=r"))]
159 [(set_attr "conds" "set")
160 (set_attr "shift" "1")
161 (set_attr "type" "alu_shift")]
164 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
165 (define_insn "*thumb2_negdi2"
166 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
167 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
168 (clobber (reg:CC CC_REGNUM))]
170 "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
171 [(set_attr "conds" "clob")
172 (set_attr "length" "8")]
175 (define_insn "*thumb2_abssi2"
176 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
177 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
178 (clobber (reg:CC CC_REGNUM))]
181 cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
182 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
183 [(set_attr "conds" "clob,*")
184 (set_attr "shift" "1")
185 ;; predicable can't be set based on the variant, so left as no
186 (set_attr "length" "10,8")]
189 (define_insn "*thumb2_neg_abssi2"
190 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
191 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
192 (clobber (reg:CC CC_REGNUM))]
195 cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
196 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
197 [(set_attr "conds" "clob,*")
198 (set_attr "shift" "1")
199 ;; predicable can't be set based on the variant, so left as no
200 (set_attr "length" "10,8")]
203 (define_insn "*thumb2_movdi"
204 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
205 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
207 && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
210 switch (which_alternative)
217 return output_move_double (operands);
220 [(set_attr "length" "8,12,16,8,8")
221 (set_attr "type" "*,*,*,load2,store2")
222 (set_attr "pool_range" "*,*,*,4096,*")
223 (set_attr "neg_pool_range" "*,*,*,0,*")]
226 (define_insn "*thumb2_movsi_insn"
227 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m")
228 (match_operand:SI 1 "general_operand" "rI,K,N,mi,r"))]
229 "TARGET_THUMB2 && ! TARGET_IWMMXT
230 && !(TARGET_HARD_FLOAT && TARGET_VFP)
231 && ( register_operand (operands[0], SImode)
232 || register_operand (operands[1], SImode))"
239 [(set_attr "type" "*,*,*,load1,store1")
240 (set_attr "predicable" "yes")
241 (set_attr "pool_range" "*,*,*,4096,*")
242 (set_attr "neg_pool_range" "*,*,*,0,*")]
245 ;; ??? We can probably do better with thumb2
246 (define_insn "pic_load_addr_thumb2"
247 [(set (match_operand:SI 0 "s_register_operand" "=r")
248 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
249 "TARGET_THUMB2 && flag_pic"
251 [(set_attr "type" "load1")
252 (set_attr "pool_range" "4096")
253 (set_attr "neg_pool_range" "0")]
256 ;; Set reg to the address of this instruction plus four. The low two
257 ;; bits of the PC are always read as zero, so ensure the instructions is
259 (define_insn "pic_load_dot_plus_four"
260 [(set (match_operand:SI 0 "register_operand" "=r")
261 (unspec:SI [(const (plus:SI (pc) (const_int 4)))
262 (use (match_operand 1 "" ""))]
266 assemble_align(BITS_PER_WORD);
267 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
268 INTVAL (operands[1]));
269 /* We use adr because some buggy gas assemble add r8, pc, #0
270 to add.w r8, pc, #0, not addw r8, pc, #0. */
271 asm_fprintf (asm_out_file, \"\\tadr\\t%r, %LLPIC%d + 4\\n\",
272 REGNO(operands[0]), (int)INTVAL (operands[1]));
275 [(set_attr "length" "6")]
278 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
279 ;; of the messiness associated with the ARM patterns.
280 (define_insn "*thumb2_movhi_insn"
281 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
282 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
285 mov%?\\t%0, %1\\t%@ movhi
286 movw%?\\t%0, %L1\\t%@ movhi
287 str%(h%)\\t%1, %0\\t%@ movhi
288 ldr%(h%)\\t%0, %1\\t%@ movhi"
289 [(set_attr "type" "*,*,store1,load1")
290 (set_attr "predicable" "yes")
291 (set_attr "pool_range" "*,*,*,4096")
292 (set_attr "neg_pool_range" "*,*,*,250")]
295 (define_insn "*thumb2_movsf_soft_insn"
296 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
297 (match_operand:SF 1 "general_operand" "r,mE,r"))]
300 && (GET_CODE (operands[0]) != MEM
301 || register_operand (operands[1], SFmode))"
304 ldr%?\\t%0, %1\\t%@ float
305 str%?\\t%1, %0\\t%@ float"
306 [(set_attr "predicable" "yes")
307 (set_attr "type" "*,load1,store1")
308 (set_attr "pool_range" "*,4096,*")
309 (set_attr "neg_pool_range" "*,0,*")]
312 (define_insn "*thumb2_movdf_soft_insn"
313 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
314 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
315 "TARGET_THUMB2 && TARGET_SOFT_FLOAT
316 && ( register_operand (operands[0], DFmode)
317 || register_operand (operands[1], DFmode))"
319 switch (which_alternative)
326 return output_move_double (operands);
329 [(set_attr "length" "8,12,16,8,8")
330 (set_attr "type" "*,*,*,load2,store2")
331 (set_attr "pool_range" "1020")
332 (set_attr "neg_pool_range" "0")]
335 (define_insn "*thumb2_cmpsi_shiftsi"
336 [(set (reg:CC CC_REGNUM)
337 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
338 (match_operator:SI 3 "shift_operator"
339 [(match_operand:SI 1 "s_register_operand" "r")
340 (match_operand:SI 2 "const_int_operand" "M")])))]
343 [(set_attr "conds" "set")
344 (set_attr "shift" "1")
345 (set_attr "type" "alu_shift")]
348 (define_insn "*thumb2_cmpsi_shiftsi_swp"
349 [(set (reg:CC_SWP CC_REGNUM)
350 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
351 [(match_operand:SI 1 "s_register_operand" "r")
352 (match_operand:SI 2 "const_int_operand" "M")])
353 (match_operand:SI 0 "s_register_operand" "r")))]
356 [(set_attr "conds" "set")
357 (set_attr "shift" "1")
358 (set_attr "type" "alu_shift")]
361 (define_insn "*thumb2_cmpsi_neg_shiftsi"
362 [(set (reg:CC CC_REGNUM)
363 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
364 (neg:SI (match_operator:SI 3 "shift_operator"
365 [(match_operand:SI 1 "s_register_operand" "r")
366 (match_operand:SI 2 "const_int_operand" "M")]))))]
369 [(set_attr "conds" "set")
370 (set_attr "shift" "1")
371 (set_attr "type" "alu_shift")]
374 (define_insn "*thumb2_mov_scc"
375 [(set (match_operand:SI 0 "s_register_operand" "=r")
376 (match_operator:SI 1 "arm_comparison_operator"
377 [(match_operand 2 "cc_register" "") (const_int 0)]))]
379 "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
380 [(set_attr "conds" "use")
381 (set_attr "length" "10")]
384 (define_insn "*thumb2_mov_negscc"
385 [(set (match_operand:SI 0 "s_register_operand" "=r")
386 (neg:SI (match_operator:SI 1 "arm_comparison_operator"
387 [(match_operand 2 "cc_register" "") (const_int 0)])))]
389 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
390 [(set_attr "conds" "use")
391 (set_attr "length" "10")]
394 (define_insn "*thumb2_mov_notscc"
395 [(set (match_operand:SI 0 "s_register_operand" "=r")
396 (not:SI (match_operator:SI 1 "arm_comparison_operator"
397 [(match_operand 2 "cc_register" "") (const_int 0)])))]
399 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
400 [(set_attr "conds" "use")
401 (set_attr "length" "10")]
404 (define_insn "*thumb2_movsicc_insn"
405 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
407 (match_operator 3 "arm_comparison_operator"
408 [(match_operand 4 "cc_register" "") (const_int 0)])
409 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
410 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
413 it\\t%D3\;mov%D3\\t%0, %2
414 it\\t%D3\;mvn%D3\\t%0, #%B2
415 it\\t%d3\;mov%d3\\t%0, %1
416 it\\t%d3\;mvn%d3\\t%0, #%B1
417 ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
418 ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
419 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
420 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
421 [(set_attr "length" "6,6,6,6,10,10,10,10")
422 (set_attr "conds" "use")]
425 (define_insn "*thumb2_movsfcc_soft_insn"
426 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
427 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
428 [(match_operand 4 "cc_register" "") (const_int 0)])
429 (match_operand:SF 1 "s_register_operand" "0,r")
430 (match_operand:SF 2 "s_register_operand" "r,0")))]
431 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
433 it\\t%D3\;mov%D3\\t%0, %2
434 it\\t%d3\;mov%d3\\t%0, %1"
435 [(set_attr "length" "6,6")
436 (set_attr "conds" "use")]
439 (define_insn "*call_reg_thumb2"
440 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
441 (match_operand 1 "" ""))
442 (use (match_operand 2 "" ""))
443 (clobber (reg:SI LR_REGNUM))]
446 [(set_attr "type" "call")]
449 (define_insn "*call_value_reg_thumb2"
450 [(set (match_operand 0 "" "")
451 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
452 (match_operand 2 "" "")))
453 (use (match_operand 3 "" ""))
454 (clobber (reg:SI LR_REGNUM))]
457 [(set_attr "type" "call")]
460 (define_insn "*thumb2_indirect_jump"
462 (match_operand:SI 0 "register_operand" "l*r"))]
465 [(set_attr "conds" "clob")]
467 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
468 ;; addresses will have the thumb bit set correctly.
471 ;; Patterns to allow combination of arithmetic, cond code and shifts
473 (define_insn "*thumb2_arith_shiftsi"
474 [(set (match_operand:SI 0 "s_register_operand" "=r")
475 (match_operator:SI 1 "shiftable_operator"
476 [(match_operator:SI 3 "shift_operator"
477 [(match_operand:SI 4 "s_register_operand" "r")
478 (match_operand:SI 5 "const_int_operand" "M")])
479 (match_operand:SI 2 "s_register_operand" "r")]))]
481 "%i1%?\\t%0, %2, %4%S3"
482 [(set_attr "predicable" "yes")
483 (set_attr "shift" "4")
484 (set_attr "type" "alu_shift")]
487 ;; ??? What does this splitter do? Copied from the ARM version
489 [(set (match_operand:SI 0 "s_register_operand" "")
490 (match_operator:SI 1 "shiftable_operator"
491 [(match_operator:SI 2 "shiftable_operator"
492 [(match_operator:SI 3 "shift_operator"
493 [(match_operand:SI 4 "s_register_operand" "")
494 (match_operand:SI 5 "const_int_operand" "")])
495 (match_operand:SI 6 "s_register_operand" "")])
496 (match_operand:SI 7 "arm_rhs_operand" "")]))
497 (clobber (match_operand:SI 8 "s_register_operand" ""))]
500 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
503 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
506 (define_insn "*thumb2_arith_shiftsi_compare0"
507 [(set (reg:CC_NOOV CC_REGNUM)
508 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
509 [(match_operator:SI 3 "shift_operator"
510 [(match_operand:SI 4 "s_register_operand" "r")
511 (match_operand:SI 5 "const_int_operand" "M")])
512 (match_operand:SI 2 "s_register_operand" "r")])
514 (set (match_operand:SI 0 "s_register_operand" "=r")
515 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
518 "%i1%.\\t%0, %2, %4%S3"
519 [(set_attr "conds" "set")
520 (set_attr "shift" "4")
521 (set_attr "type" "alu_shift")]
524 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
525 [(set (reg:CC_NOOV CC_REGNUM)
526 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
527 [(match_operator:SI 3 "shift_operator"
528 [(match_operand:SI 4 "s_register_operand" "r")
529 (match_operand:SI 5 "const_int_operand" "M")])
530 (match_operand:SI 2 "s_register_operand" "r")])
532 (clobber (match_scratch:SI 0 "=r"))]
534 "%i1%.\\t%0, %2, %4%S3"
535 [(set_attr "conds" "set")
536 (set_attr "shift" "4")
537 (set_attr "type" "alu_shift")]
540 (define_insn "*thumb2_sub_shiftsi"
541 [(set (match_operand:SI 0 "s_register_operand" "=r")
542 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
543 (match_operator:SI 2 "shift_operator"
544 [(match_operand:SI 3 "s_register_operand" "r")
545 (match_operand:SI 4 "const_int_operand" "M")])))]
547 "sub%?\\t%0, %1, %3%S2"
548 [(set_attr "predicable" "yes")
549 (set_attr "shift" "3")
550 (set_attr "type" "alu_shift")]
553 (define_insn "*thumb2_sub_shiftsi_compare0"
554 [(set (reg:CC_NOOV CC_REGNUM)
556 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
557 (match_operator:SI 2 "shift_operator"
558 [(match_operand:SI 3 "s_register_operand" "r")
559 (match_operand:SI 4 "const_int_operand" "M")]))
561 (set (match_operand:SI 0 "s_register_operand" "=r")
562 (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
565 "sub%.\\t%0, %1, %3%S2"
566 [(set_attr "conds" "set")
567 (set_attr "shift" "3")
568 (set_attr "type" "alu_shift")]
571 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
572 [(set (reg:CC_NOOV CC_REGNUM)
574 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
575 (match_operator:SI 2 "shift_operator"
576 [(match_operand:SI 3 "s_register_operand" "r")
577 (match_operand:SI 4 "const_int_operand" "M")]))
579 (clobber (match_scratch:SI 0 "=r"))]
581 "sub%.\\t%0, %1, %3%S2"
582 [(set_attr "conds" "set")
583 (set_attr "shift" "3")
584 (set_attr "type" "alu_shift")]
587 (define_insn "*thumb2_and_scc"
588 [(set (match_operand:SI 0 "s_register_operand" "=r")
589 (and:SI (match_operator:SI 1 "arm_comparison_operator"
590 [(match_operand 3 "cc_register" "") (const_int 0)])
591 (match_operand:SI 2 "s_register_operand" "r")))]
593 "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
594 [(set_attr "conds" "use")
595 (set_attr "length" "10")]
598 (define_insn "*thumb2_ior_scc"
599 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
600 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
601 [(match_operand 3 "cc_register" "") (const_int 0)])
602 (match_operand:SI 1 "s_register_operand" "0,?r")))]
605 it\\t%d2\;orr%d2\\t%0, %1, #1
606 ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
607 [(set_attr "conds" "use")
608 (set_attr "length" "6,10")]
611 (define_insn "*thumb2_compare_scc"
612 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
613 (match_operator:SI 1 "arm_comparison_operator"
614 [(match_operand:SI 2 "s_register_operand" "r,r")
615 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
616 (clobber (reg:CC CC_REGNUM))]
619 if (operands[3] == const0_rtx)
621 if (GET_CODE (operands[1]) == LT)
622 return \"lsr\\t%0, %2, #31\";
624 if (GET_CODE (operands[1]) == GE)
625 return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
627 if (GET_CODE (operands[1]) == EQ)
628 return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
631 if (GET_CODE (operands[1]) == NE)
633 if (which_alternative == 1)
634 return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
635 return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
637 if (which_alternative == 1)
638 output_asm_insn (\"cmn\\t%2, #%n3\", operands);
640 output_asm_insn (\"cmp\\t%2, %3\", operands);
641 return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
643 [(set_attr "conds" "clob")
644 (set_attr "length" "14")]
647 (define_insn "*thumb2_cond_move"
648 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
649 (if_then_else:SI (match_operator 3 "equality_operator"
650 [(match_operator 4 "arm_comparison_operator"
651 [(match_operand 5 "cc_register" "") (const_int 0)])
653 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
654 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
657 if (GET_CODE (operands[3]) == NE)
659 if (which_alternative != 1)
660 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
661 if (which_alternative != 0)
662 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
665 switch (which_alternative)
668 output_asm_insn (\"it\\t%d4\", operands);
671 output_asm_insn (\"it\\t%D4\", operands);
674 output_asm_insn (\"ite\\t%D4\", operands);
679 if (which_alternative != 0)
680 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
681 if (which_alternative != 1)
682 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
685 [(set_attr "conds" "use")
686 (set_attr "length" "6,6,10")]
689 (define_insn "*thumb2_cond_arith"
690 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
691 (match_operator:SI 5 "shiftable_operator"
692 [(match_operator:SI 4 "arm_comparison_operator"
693 [(match_operand:SI 2 "s_register_operand" "r,r")
694 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
695 (match_operand:SI 1 "s_register_operand" "0,?r")]))
696 (clobber (reg:CC CC_REGNUM))]
699 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
700 return \"%i5\\t%0, %1, %2, lsr #31\";
702 output_asm_insn (\"cmp\\t%2, %3\", operands);
703 if (GET_CODE (operands[5]) == AND)
705 output_asm_insn (\"ite\\t%D4\", operands);
706 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
708 else if (GET_CODE (operands[5]) == MINUS)
710 output_asm_insn (\"ite\\t%D4\", operands);
711 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
713 else if (which_alternative != 0)
715 output_asm_insn (\"ite\\t%D4\", operands);
716 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
719 output_asm_insn (\"it\\t%d4\", operands);
720 return \"%i5%d4\\t%0, %1, #1\";
722 [(set_attr "conds" "clob")
723 (set_attr "length" "14")]
726 (define_insn "*thumb2_cond_sub"
727 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
728 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
729 (match_operator:SI 4 "arm_comparison_operator"
730 [(match_operand:SI 2 "s_register_operand" "r,r")
731 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
732 (clobber (reg:CC CC_REGNUM))]
735 output_asm_insn (\"cmp\\t%2, %3\", operands);
736 if (which_alternative != 0)
738 output_asm_insn (\"ite\\t%D4\", operands);
739 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
742 output_asm_insn (\"it\\t%d4\", operands);
743 return \"sub%d4\\t%0, %1, #1\";
745 [(set_attr "conds" "clob")
746 (set_attr "length" "10,14")]
749 (define_insn "*thumb2_negscc"
750 [(set (match_operand:SI 0 "s_register_operand" "=r")
751 (neg:SI (match_operator 3 "arm_comparison_operator"
752 [(match_operand:SI 1 "s_register_operand" "r")
753 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
754 (clobber (reg:CC CC_REGNUM))]
757 if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx)
758 return \"asr\\t%0, %1, #31\";
760 if (GET_CODE (operands[3]) == NE)
761 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
763 if (GET_CODE (operands[3]) == GT)
764 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, %0, asr #31\";
766 output_asm_insn (\"cmp\\t%1, %2\", operands);
767 output_asm_insn (\"ite\\t%D3\", operands);
768 output_asm_insn (\"mov%D3\\t%0, #0\", operands);
769 return \"mvn%d3\\t%0, #0\";
771 [(set_attr "conds" "clob")
772 (set_attr "length" "14")]
775 (define_insn "*thumb2_movcond"
776 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
778 (match_operator 5 "arm_comparison_operator"
779 [(match_operand:SI 3 "s_register_operand" "r,r,r")
780 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
781 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
782 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
783 (clobber (reg:CC CC_REGNUM))]
786 if (GET_CODE (operands[5]) == LT
787 && (operands[4] == const0_rtx))
789 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
791 if (operands[2] == const0_rtx)
792 return \"and\\t%0, %1, %3, asr #31\";
793 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
795 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
797 if (operands[1] == const0_rtx)
798 return \"bic\\t%0, %2, %3, asr #31\";
799 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
801 /* The only case that falls through to here is when both ops 1 & 2
805 if (GET_CODE (operands[5]) == GE
806 && (operands[4] == const0_rtx))
808 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
810 if (operands[2] == const0_rtx)
811 return \"bic\\t%0, %1, %3, asr #31\";
812 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
814 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
816 if (operands[1] == const0_rtx)
817 return \"and\\t%0, %2, %3, asr #31\";
818 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
820 /* The only case that falls through to here is when both ops 1 & 2
823 if (GET_CODE (operands[4]) == CONST_INT
824 && !const_ok_for_arm (INTVAL (operands[4])))
825 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
827 output_asm_insn (\"cmp\\t%3, %4\", operands);
828 switch (which_alternative)
831 output_asm_insn (\"it\\t%D5\", operands);
834 output_asm_insn (\"it\\t%d5\", operands);
837 output_asm_insn (\"ite\\t%d5\", operands);
842 if (which_alternative != 0)
843 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
844 if (which_alternative != 1)
845 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
848 [(set_attr "conds" "clob")
849 (set_attr "length" "10,10,14")]
852 ;; Zero and sign extension instructions.
854 (define_insn "*thumb2_zero_extendsidi2"
855 [(set (match_operand:DI 0 "s_register_operand" "=r")
856 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
859 /* ??? Output both instructions unconditionally, otherwise the conditional
860 execution insn counter gets confused.
861 if (REGNO (operands[1])
862 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
863 output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
864 return \"mov%?\\t%R0, #0\";
866 [(set_attr "length" "8")
867 (set_attr "ce_count" "2")
868 (set_attr "predicable" "yes")]
871 (define_insn "*thumb2_zero_extendqidi2"
872 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
873 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
876 and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
877 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
878 [(set_attr "length" "8")
879 (set_attr "ce_count" "2")
880 (set_attr "predicable" "yes")
881 (set_attr "type" "*,load_byte")
882 (set_attr "pool_range" "*,4092")
883 (set_attr "neg_pool_range" "*,250")]
886 (define_insn "*thumb2_extendsidi2"
887 [(set (match_operand:DI 0 "s_register_operand" "=r")
888 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
891 /* ??? Output both instructions unconditionally, otherwise the conditional
892 execution insn counter gets confused.
893 if (REGNO (operands[1])
894 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
895 output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
896 return \"asr%?\\t%R0, %Q0, #31\";
898 [(set_attr "length" "8")
899 (set_attr "ce_count" "2")
900 (set_attr "shift" "1")
901 (set_attr "predicable" "yes")]
904 ;; All supported Thumb2 implementations are armv6, so only that case is
906 (define_insn "*thumb2_extendqisi_v6"
907 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
908 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
909 "TARGET_THUMB2 && arm_arch6"
913 [(set_attr "type" "alu_shift,load_byte")
914 (set_attr "predicable" "yes")
915 (set_attr "pool_range" "*,4096")
916 (set_attr "neg_pool_range" "*,250")]
919 (define_insn "*thumb2_zero_extendhisi2_v6"
920 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
921 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
922 "TARGET_THUMB2 && arm_arch6"
926 [(set_attr "type" "alu_shift,load_byte")
927 (set_attr "predicable" "yes")
928 (set_attr "pool_range" "*,4096")
929 (set_attr "neg_pool_range" "*,250")]
932 (define_insn "*thumb2_zero_extendqisi2_v6"
933 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
934 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
935 "TARGET_THUMB2 && arm_arch6"
938 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
939 [(set_attr "type" "alu_shift,load_byte")
940 (set_attr "predicable" "yes")
941 (set_attr "pool_range" "*,4096")
942 (set_attr "neg_pool_range" "*,250")]
945 (define_insn "thumb2_casesi_internal"
946 [(parallel [(set (pc)
948 (leu (match_operand:SI 0 "s_register_operand" "r")
949 (match_operand:SI 1 "arm_rhs_operand" "rI"))
950 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
951 (label_ref (match_operand 2 "" ""))))
952 (label_ref (match_operand 3 "" ""))))
953 (clobber (reg:CC CC_REGNUM))
954 (clobber (match_scratch:SI 4 "=r"))
955 (use (label_ref (match_dup 2)))])]
956 "TARGET_THUMB2 && !flag_pic"
957 "* return thumb2_output_casesi(operands);"
958 [(set_attr "conds" "clob")
959 (set_attr "length" "16")]
962 (define_insn "thumb2_casesi_internal_pic"
963 [(parallel [(set (pc)
965 (leu (match_operand:SI 0 "s_register_operand" "r")
966 (match_operand:SI 1 "arm_rhs_operand" "rI"))
967 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
968 (label_ref (match_operand 2 "" ""))))
969 (label_ref (match_operand 3 "" ""))))
970 (clobber (reg:CC CC_REGNUM))
971 (clobber (match_scratch:SI 4 "=r"))
972 (clobber (match_scratch:SI 5 "=r"))
973 (use (label_ref (match_dup 2)))])]
974 "TARGET_THUMB2 && flag_pic"
975 "* return thumb2_output_casesi(operands);"
976 [(set_attr "conds" "clob")
977 (set_attr "length" "20")]
980 (define_insn_and_split "thumb2_eh_return"
981 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
983 (clobber (match_scratch:SI 1 "=&r"))]
986 "&& reload_completed"
990 thumb_set_return_address (operands[0], operands[1]);
995 ;; Peepholes and insns for 16-bit flag clobbering instructions.
996 ;; The conditional forms of these instructions do not clobber CC.
997 ;; However by the time peepholes are run it is probably too late to do
998 ;; anything useful with this information.
1000 [(set (match_operand:SI 0 "low_register_operand" "")
1001 (match_operator:SI 3 "thumb_16bit_operator"
1002 [(match_operand:SI 1 "low_register_operand" "")
1003 (match_operand:SI 2 "low_register_operand" "")]))]
1004 "TARGET_THUMB2 && rtx_equal_p(operands[0], operands[1])
1005 && peep2_regno_dead_p(0, CC_REGNUM)"
1011 (clobber (reg:CC CC_REGNUM))])]
1015 (define_insn "*thumb2_alusi3_short"
1016 [(set (match_operand:SI 0 "s_register_operand" "=l")
1017 (match_operator:SI 3 "thumb_16bit_operator"
1018 [(match_operand:SI 1 "s_register_operand" "0")
1019 (match_operand:SI 2 "s_register_operand" "l")]))
1020 (clobber (reg:CC CC_REGNUM))]
1021 "TARGET_THUMB2 && reload_completed"
1022 "%I3%!\\t%0, %1, %2"
1023 [(set_attr "predicable" "yes")
1024 (set_attr "length" "2")]
1027 ;; Similarly for 16-bit shift instructions
1028 ;; There is no 16-bit rotate by immediate instruction.
1030 [(set (match_operand:SI 0 "low_register_operand" "")
1031 (match_operator:SI 3 "shift_operator"
1032 [(match_operand:SI 1 "low_register_operand" "")
1033 (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1035 && peep2_regno_dead_p(0, CC_REGNUM)
1036 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1037 || REG_P(operands[2]))"
1043 (clobber (reg:CC CC_REGNUM))])]
1047 (define_insn "*thumb2_shiftsi3_short"
1048 [(set (match_operand:SI 0 "low_register_operand" "=l")
1049 (match_operator:SI 3 "shift_operator"
1050 [(match_operand:SI 1 "low_register_operand" "l")
1051 (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1052 (clobber (reg:CC CC_REGNUM))]
1053 "TARGET_THUMB2 && reload_completed
1054 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1055 || REG_P(operands[2]))"
1056 "* return arm_output_shift(operands, 2);"
1057 [(set_attr "predicable" "yes")
1058 (set_attr "shift" "1")
1059 (set_attr "length" "2")
1060 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1061 (const_string "alu_shift")
1062 (const_string "alu_shift_reg")))]
1065 ;; 16-bit load immediate
1067 [(set (match_operand:SI 0 "low_register_operand" "")
1068 (match_operand:SI 1 "const_int_operand" ""))]
1070 && peep2_regno_dead_p(0, CC_REGNUM)
1071 && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1075 (clobber (reg:CC CC_REGNUM))])]
1079 (define_insn "*thumb2_movsi_shortim"
1080 [(set (match_operand:SI 0 "low_register_operand" "=l")
1081 (match_operand:SI 1 "const_int_operand" "I"))
1082 (clobber (reg:CC CC_REGNUM))]
1083 "TARGET_THUMB2 && reload_completed"
1085 [(set_attr "predicable" "yes")
1086 (set_attr "length" "2")]
1089 ;; 16-bit add/sub immediate
1091 [(set (match_operand:SI 0 "low_register_operand" "")
1092 (plus:SI (match_operand:SI 1 "low_register_operand" "")
1093 (match_operand:SI 2 "const_int_operand" "")))]
1095 && peep2_regno_dead_p(0, CC_REGNUM)
1096 && ((rtx_equal_p(operands[0], operands[1])
1097 && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1098 || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1101 (plus:SI (match_dup 1)
1103 (clobber (reg:CC CC_REGNUM))])]
1107 (define_insn "*thumb2_addsi_shortim"
1108 [(set (match_operand:SI 0 "low_register_operand" "=l")
1109 (plus:SI (match_operand:SI 1 "low_register_operand" "l")
1110 (match_operand:SI 2 "const_int_operand" "IL")))
1111 (clobber (reg:CC CC_REGNUM))]
1112 "TARGET_THUMB2 && reload_completed"
1116 val = INTVAL(operands[2]);
1117 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1118 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1119 return \"sub%!\\t%0, %1, #%n2\";
1121 return \"add%!\\t%0, %1, %2\";
1123 [(set_attr "predicable" "yes")
1124 (set_attr "length" "2")]
1127 (define_insn "divsi3"
1128 [(set (match_operand:SI 0 "s_register_operand" "=r")
1129 (div:SI (match_operand:SI 1 "s_register_operand" "r")
1130 (match_operand:SI 2 "s_register_operand" "r")))]
1131 "TARGET_THUMB2 && arm_arch_hwdiv"
1132 "sdiv%?\t%0, %1, %2"
1133 [(set_attr "predicable" "yes")]
1136 (define_insn "udivsi3"
1137 [(set (match_operand:SI 0 "s_register_operand" "=r")
1138 (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
1139 (match_operand:SI 2 "s_register_operand" "r")))]
1140 "TARGET_THUMB2 && arm_arch_hwdiv"
1141 "udiv%?\t%0, %1, %2"
1142 [(set_attr "predicable" "yes")]
1145 (define_insn "*thumb2_cbz"
1146 [(set (pc) (if_then_else
1147 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1149 (label_ref (match_operand 1 "" ""))
1151 (clobber (reg:CC CC_REGNUM))]
1154 if (get_attr_length (insn) == 2 && which_alternative == 0)
1155 return \"cbz\\t%0, %l1\";
1157 return \"cmp\\t%0, #0\;beq\\t%l1\";
1159 [(set (attr "length")
1161 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1162 (le (minus (match_dup 1) (pc)) (const_int 128)))
1167 (define_insn "*thumb2_cbnz"
1168 [(set (pc) (if_then_else
1169 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1171 (label_ref (match_operand 1 "" ""))
1173 (clobber (reg:CC CC_REGNUM))]
1176 if (get_attr_length (insn) == 2 && which_alternative == 0)
1177 return \"cbnz\\t%0, %l1\";
1179 return \"cmp\\t%0, #0\;bne\\t%l1\";
1181 [(set (attr "length")
1183 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1184 (le (minus (match_dup 1) (pc)) (const_int 128)))