1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
29 return (GET_CODE (op) == REG
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
35 (define_predicate "arm_hard_register_operand"
38 return REGNO (op) < FIRST_PSEUDO_REGISTER;
42 (define_predicate "low_register_operand"
43 (and (match_code "reg")
44 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
46 ;; A low register or const_int.
47 (define_predicate "low_reg_or_int_operand"
48 (ior (match_code "const_int")
49 (match_operand 0 "low_register_operand")))
51 ;; Any core register, or any pseudo. */
52 (define_predicate "arm_general_register_operand"
53 (match_code "reg,subreg")
55 if (GET_CODE (op) == SUBREG)
58 return (GET_CODE (op) == REG
59 && (REGNO (op) <= LAST_ARM_REGNUM
60 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
63 (define_predicate "f_register_operand"
64 (match_code "reg,subreg")
66 if (GET_CODE (op) == SUBREG)
69 /* We don't consider registers whose class is NO_REGS
70 to be a register operand. */
71 return (GET_CODE (op) == REG
72 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
73 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
76 (define_predicate "vfp_register_operand"
77 (match_code "reg,subreg")
79 if (GET_CODE (op) == SUBREG)
82 /* We don't consider registers whose class is NO_REGS
83 to be a register operand. */
84 return (GET_CODE (op) == REG
85 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
86 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
87 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
89 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
92 (define_special_predicate "subreg_lowpart_operator"
93 (and (match_code "subreg")
94 (match_test "subreg_lowpart_p (op)")))
96 ;; Reg, subreg(reg) or const_int.
97 (define_predicate "reg_or_int_operand"
98 (ior (match_code "const_int")
99 (match_operand 0 "s_register_operand")))
101 (define_predicate "arm_immediate_operand"
102 (and (match_code "const_int")
103 (match_test "const_ok_for_arm (INTVAL (op))")))
105 ;; A constant value which fits into two instructions, each taking
106 ;; an arithmetic constant operand for one of the words.
107 (define_predicate "arm_immediate_di_operand"
108 (and (match_code "const_int,const_double")
109 (match_test "arm_const_double_by_immediates (op)")))
111 (define_predicate "arm_neg_immediate_operand"
112 (and (match_code "const_int")
113 (match_test "const_ok_for_arm (-INTVAL (op))")))
115 (define_predicate "arm_not_immediate_operand"
116 (and (match_code "const_int")
117 (match_test "const_ok_for_arm (~INTVAL (op))")))
119 (define_predicate "const0_operand"
120 (and (match_code "const_int")
121 (match_test "INTVAL (op) == 0")))
123 ;; Something valid on the RHS of an ARM data-processing instruction
124 (define_predicate "arm_rhs_operand"
125 (ior (match_operand 0 "s_register_operand")
126 (match_operand 0 "arm_immediate_operand")))
128 (define_predicate "arm_rhsm_operand"
129 (ior (match_operand 0 "arm_rhs_operand")
130 (match_operand 0 "memory_operand")))
132 (define_predicate "shift_amount_operand"
133 (ior (and (match_test "TARGET_ARM")
134 (match_operand 0 "s_register_operand"))
135 (match_operand 0 "const_int_operand")))
137 (define_predicate "arm_add_operand"
138 (ior (match_operand 0 "arm_rhs_operand")
139 (match_operand 0 "arm_neg_immediate_operand")))
141 (define_predicate "arm_addimm_operand"
142 (ior (match_operand 0 "arm_immediate_operand")
143 (match_operand 0 "arm_neg_immediate_operand")))
145 (define_predicate "arm_not_operand"
146 (ior (match_operand 0 "arm_rhs_operand")
147 (match_operand 0 "arm_not_immediate_operand")))
149 (define_predicate "arm_di_operand"
150 (ior (match_operand 0 "s_register_operand")
151 (match_operand 0 "arm_immediate_di_operand")))
153 ;; True if the operand is a memory reference which contains an
154 ;; offsettable address.
155 (define_predicate "offsettable_memory_operand"
156 (and (match_code "mem")
158 "offsettable_address_p (reload_completed | reload_in_progress,
159 mode, XEXP (op, 0))")))
161 ;; True if the operand is a memory operand that does not have an
162 ;; automodified base register (and thus will not generate output reloads).
163 (define_predicate "call_memory_operand"
164 (and (match_code "mem")
165 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
167 (match_operand 0 "memory_operand"))))
169 (define_predicate "arm_reload_memory_operand"
170 (and (match_code "mem,reg,subreg")
171 (match_test "(!CONSTANT_P (op)
172 && (true_regnum(op) == -1
173 || (GET_CODE (op) == REG
174 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
176 ;; True for valid operands for the rhs of an floating point insns.
177 ;; Allows regs or certain consts on FPA, just regs for everything else.
178 (define_predicate "arm_float_rhs_operand"
179 (ior (match_operand 0 "s_register_operand")
180 (and (match_code "const_double")
181 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
183 (define_predicate "arm_float_add_operand"
184 (ior (match_operand 0 "arm_float_rhs_operand")
185 (and (match_code "const_double")
186 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
188 (define_predicate "vfp_compare_operand"
189 (ior (match_operand 0 "s_register_operand")
190 (and (match_code "const_double")
191 (match_test "arm_const_double_rtx (op)"))))
193 (define_predicate "arm_float_compare_operand"
194 (if_then_else (match_test "TARGET_VFP")
195 (match_operand 0 "vfp_compare_operand")
196 (match_operand 0 "arm_float_rhs_operand")))
198 ;; True for valid index operands.
199 (define_predicate "index_operand"
200 (ior (match_operand 0 "s_register_operand")
201 (and (match_operand 0 "immediate_operand")
202 (match_test "(GET_CODE (op) != CONST_INT
203 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
205 ;; True for operators that can be combined with a shift in ARM state.
206 (define_special_predicate "shiftable_operator"
207 (and (match_code "plus,minus,ior,xor,and")
208 (match_test "mode == GET_MODE (op)")))
210 ;; True for logical binary operators.
211 (define_special_predicate "logical_binary_operator"
212 (and (match_code "ior,xor,and")
213 (match_test "mode == GET_MODE (op)")))
215 ;; True for commutative operators
216 (define_special_predicate "commutative_binary_operator"
217 (and (match_code "ior,xor,and,plus")
218 (match_test "mode == GET_MODE (op)")))
220 ;; True for shift operators.
221 (define_special_predicate "shift_operator"
222 (and (ior (ior (and (match_code "mult")
223 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
224 (and (match_code "rotate")
225 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
226 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
227 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
228 (match_test "mode == GET_MODE (op)")))
230 ;; True for MULT, to identify which variant of shift_operator is in use.
231 (define_special_predicate "mult_operator"
234 ;; True for operators that have 16-bit thumb variants. */
235 (define_special_predicate "thumb_16bit_operator"
236 (match_code "plus,minus,and,ior,xor"))
239 (define_special_predicate "equality_operator"
240 (match_code "eq,ne"))
242 ;; True for integer comparisons and, if FP is active, for comparisons
243 ;; other than LTGT or UNEQ.
244 (define_special_predicate "arm_comparison_operator"
245 (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
246 (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
247 && (TARGET_FPA || TARGET_VFP)")
248 (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
250 (define_special_predicate "lt_ge_comparison_operator"
251 (match_code "lt,ge"))
253 (define_special_predicate "noov_comparison_operator"
254 (match_code "lt,ge,eq,ne"))
256 (define_special_predicate "minmax_operator"
257 (and (match_code "smin,smax,umin,umax")
258 (match_test "mode == GET_MODE (op)")))
260 (define_special_predicate "cc_register"
261 (and (match_code "reg")
262 (and (match_test "REGNO (op) == CC_REGNUM")
263 (ior (match_test "mode == GET_MODE (op)")
264 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
266 (define_special_predicate "dominant_cc_register"
269 if (mode == VOIDmode)
271 mode = GET_MODE (op);
273 if (GET_MODE_CLASS (mode) != MODE_CC)
277 return (cc_register (op, mode)
278 && (mode == CC_DNEmode
279 || mode == CC_DEQmode
280 || mode == CC_DLEmode
281 || mode == CC_DLTmode
282 || mode == CC_DGEmode
283 || mode == CC_DGTmode
284 || mode == CC_DLEUmode
285 || mode == CC_DLTUmode
286 || mode == CC_DGEUmode
287 || mode == CC_DGTUmode));
290 (define_special_predicate "arm_extendqisi_mem_op"
291 (and (match_operand 0 "memory_operand")
292 (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
295 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
296 (ior (match_operand 0 "arm_extendqisi_mem_op")
297 (match_operand 0 "s_register_operand")))
299 (define_predicate "power_of_two_operand"
300 (match_code "const_int")
302 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
304 return value != 0 && (value & (value - 1)) == 0;
307 (define_predicate "nonimmediate_di_operand"
308 (match_code "reg,subreg,mem")
310 if (s_register_operand (op, mode))
313 if (GET_CODE (op) == SUBREG)
314 op = SUBREG_REG (op);
316 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
319 (define_predicate "di_operand"
320 (ior (match_code "const_int,const_double")
321 (and (match_code "reg,subreg,mem")
322 (match_operand 0 "nonimmediate_di_operand"))))
324 (define_predicate "nonimmediate_soft_df_operand"
325 (match_code "reg,subreg,mem")
327 if (s_register_operand (op, mode))
330 if (GET_CODE (op) == SUBREG)
331 op = SUBREG_REG (op);
333 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
336 (define_predicate "soft_df_operand"
337 (ior (match_code "const_double")
338 (and (match_code "reg,subreg,mem")
339 (match_operand 0 "nonimmediate_soft_df_operand"))))
341 (define_predicate "const_shift_operand"
342 (and (match_code "const_int")
343 (ior (match_operand 0 "power_of_two_operand")
344 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
347 (define_special_predicate "load_multiple_operation"
348 (match_code "parallel")
350 HOST_WIDE_INT count = XVECLEN (op, 0);
353 HOST_WIDE_INT i = 1, base = 0;
354 HOST_WIDE_INT offset = 0;
356 bool addr_reg_loaded = false;
360 || GET_CODE (XVECEXP (op, 0, 0)) != SET
361 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
364 /* Check to see if this might be a write-back. */
365 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
371 /* Now check it more carefully. */
372 if (GET_CODE (SET_DEST (elt)) != REG
373 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
374 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
375 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
379 /* Perform a quick check so we don't blow up below. */
381 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
382 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
383 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
386 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
387 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
388 if (GET_CODE (src_addr) == PLUS)
390 if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
392 offset = INTVAL (XEXP (src_addr, 1));
393 src_addr = XEXP (src_addr, 0);
395 if (!REG_P (src_addr))
398 for (; i < count; i++)
400 elt = XVECEXP (op, 0, i);
402 if (GET_CODE (elt) != SET
403 || GET_CODE (SET_DEST (elt)) != REG
404 || GET_MODE (SET_DEST (elt)) != SImode
405 || REGNO (SET_DEST (elt)) <= dest_regno
406 || GET_CODE (SET_SRC (elt)) != MEM
407 || GET_MODE (SET_SRC (elt)) != SImode
408 || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
409 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
410 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
411 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
412 && (!REG_P (XEXP (SET_SRC (elt), 0))
413 || offset + (i - base) * 4 != 0)))
415 dest_regno = REGNO (SET_DEST (elt));
416 if (dest_regno == REGNO (src_addr))
417 addr_reg_loaded = true;
419 /* For Thumb, we only have updating instructions. If the pattern does
420 not describe an update, it must be because the address register is
421 in the list of loaded registers - on the hardware, this has the effect
422 of overriding the update. */
423 if (update && addr_reg_loaded)
426 return update || addr_reg_loaded;
430 (define_special_predicate "store_multiple_operation"
431 (match_code "parallel")
433 HOST_WIDE_INT count = XVECLEN (op, 0);
436 HOST_WIDE_INT i = 1, base = 0, offset = 0;
440 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
443 /* Check to see if this might be a write-back. */
444 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
449 /* Now check it more carefully. */
450 if (GET_CODE (SET_DEST (elt)) != REG
451 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
452 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
453 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
457 /* Perform a quick check so we don't blow up below. */
459 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
460 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
461 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
464 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
465 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
467 if (GET_CODE (dest_addr) == PLUS)
469 if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
471 offset = INTVAL (XEXP (dest_addr, 1));
472 dest_addr = XEXP (dest_addr, 0);
474 if (!REG_P (dest_addr))
477 for (; i < count; i++)
479 elt = XVECEXP (op, 0, i);
481 if (GET_CODE (elt) != SET
482 || GET_CODE (SET_SRC (elt)) != REG
483 || GET_MODE (SET_SRC (elt)) != SImode
484 || REGNO (SET_SRC (elt)) <= src_regno
485 || GET_CODE (SET_DEST (elt)) != MEM
486 || GET_MODE (SET_DEST (elt)) != SImode
487 || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
488 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
489 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
490 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
491 && (!REG_P (XEXP (SET_DEST (elt), 0))
492 || offset + (i - base) * 4 != 0)))
494 src_regno = REGNO (SET_SRC (elt));
500 (define_special_predicate "multi_register_push"
501 (match_code "parallel")
503 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
504 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
505 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
511 ;;-------------------------------------------------------------------------
516 (define_predicate "thumb1_cmp_operand"
517 (ior (and (match_code "reg,subreg")
518 (match_operand 0 "s_register_operand"))
519 (and (match_code "const_int")
520 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
522 (define_predicate "thumb1_cmpneg_operand"
523 (and (match_code "const_int")
524 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
526 ;; Return TRUE if a result can be stored in OP without clobbering the
527 ;; condition code register. Prior to reload we only accept a
528 ;; register. After reload we have to be able to handle memory as
529 ;; well, since a pseudo may not get a hard reg and reload cannot
530 ;; handle output-reloads on jump insns.
532 ;; We could possibly handle mem before reload as well, but that might
533 ;; complicate things with the need to handle increment
535 (define_predicate "thumb_cbrch_target_operand"
536 (and (match_code "reg,subreg,mem")
537 (ior (match_operand 0 "s_register_operand")
538 (and (match_test "reload_in_progress || reload_completed")
539 (match_operand 0 "memory_operand")))))
541 ;;-------------------------------------------------------------------------
543 ;; MAVERICK predicates
546 (define_predicate "cirrus_register_operand"
547 (match_code "reg,subreg")
549 if (GET_CODE (op) == SUBREG)
550 op = SUBREG_REG (op);
552 return (GET_CODE (op) == REG
553 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
554 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
557 (define_predicate "cirrus_fp_register"
558 (match_code "reg,subreg")
560 if (GET_CODE (op) == SUBREG)
561 op = SUBREG_REG (op);
563 return (GET_CODE (op) == REG
564 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
565 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
568 (define_predicate "cirrus_shift_const"
569 (and (match_code "const_int")
570 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
575 (define_predicate "const_multiple_of_8_operand"
576 (match_code "const_int")
578 unsigned HOST_WIDE_INT val = INTVAL (op);
579 return (val & 7) == 0;
582 (define_predicate "imm_for_neon_mov_operand"
583 (match_code "const_vector")
585 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
588 (define_predicate "imm_for_neon_logic_operand"
589 (match_code "const_vector")
592 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
595 (define_predicate "imm_for_neon_inv_logic_operand"
596 (match_code "const_vector")
599 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
602 (define_predicate "neon_logic_op2"
603 (ior (match_operand 0 "imm_for_neon_logic_operand")
604 (match_operand 0 "s_register_operand")))
606 (define_predicate "neon_inv_logic_op2"
607 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
608 (match_operand 0 "s_register_operand")))
610 ;; TODO: We could check lane numbers more precisely based on the mode.
611 (define_predicate "neon_lane_number"
612 (and (match_code "const_int")
613 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
614 ;; Predicates for named expanders that overlap multiple ISAs.
616 (define_predicate "cmpdi_operand"
617 (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
618 (and (match_test "TARGET_ARM")
619 (match_operand 0 "cirrus_fp_register"))
620 (and (match_test "TARGET_32BIT")
621 (match_operand 0 "arm_di_operand"))))
623 ;; True if the operand is memory reference suitable for a ldrex/strex.
624 (define_predicate "arm_sync_memory_operand"
625 (and (match_operand 0 "memory_operand")
626 (match_code "reg" "0")))
628 ;; Predicates for parallel expanders based on mode.
629 (define_special_predicate "vect_par_constant_high"
630 (match_code "parallel")
632 HOST_WIDE_INT count = XVECLEN (op, 0);
634 int base = GET_MODE_NUNITS (mode);
637 || (count != base/2))
640 if (!VECTOR_MODE_P (mode))
643 for (i = 0; i < count; i++)
645 rtx elt = XVECEXP (op, 0, i);
648 if (GET_CODE (elt) != CONST_INT)
652 if (val != (base/2) + i)
658 (define_special_predicate "vect_par_constant_low"
659 (match_code "parallel")
661 HOST_WIDE_INT count = XVECLEN (op, 0);
663 int base = GET_MODE_NUNITS (mode);
666 || (count != base/2))
669 if (!VECTOR_MODE_P (mode))
672 for (i = 0; i < count; i++)
674 rtx elt = XVECEXP (op, 0, i);
677 if (GET_CODE (elt) != CONST_INT)