1 ;; ARM NEON coprocessor Machine Description
2 ;; Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Constants for unspecs.
23 [(UNSPEC_ASHIFT_SIGNED 65)
24 (UNSPEC_ASHIFT_UNSIGNED 66)
59 (UNSPEC_VLD1_LANE 101)
62 (UNSPEC_VLD2_LANE 104)
67 (UNSPEC_VLD3_LANE 109)
72 (UNSPEC_VLD4_LANE 114)
77 (UNSPEC_VMLA_LANE 119)
78 (UNSPEC_VMLAL_LANE 120)
81 (UNSPEC_VMLS_LANE 123)
82 (UNSPEC_VMLSL_LANE 124)
87 (UNSPEC_VMUL_LANE 129)
88 (UNSPEC_VMULL_LANE 130)
105 (UNSPEC_VQDMLAL_LANE 147)
107 (UNSPEC_VQDMLSL_LANE 149)
109 (UNSPEC_VQDMULH_LANE 151)
111 (UNSPEC_VQDMULL_LANE 153)
117 (UNSPEC_VQSHLU_N 159)
118 (UNSPEC_VQSHRN_N 160)
119 (UNSPEC_VQSHRUN_N 161)
128 (UNSPEC_VSET_LANE 170)
138 (UNSPEC_VST1_LANE 180)
140 (UNSPEC_VST2_LANE 182)
144 (UNSPEC_VST3_LANE 186)
148 (UNSPEC_VST4_LANE 190)
149 (UNSPEC_VSTRUCTDUMMY 191)
164 ;; Double-width vector modes.
165 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
167 ;; Double-width vector modes plus 64-bit elements.
168 (define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
170 ;; Same, without floating-point elements.
171 (define_mode_iterator VDI [V8QI V4HI V2SI])
173 ;; Quad-width vector modes.
174 (define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
176 ;; Quad-width vector modes plus 64-bit elements.
177 (define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
179 ;; Same, without floating-point elements.
180 (define_mode_iterator VQI [V16QI V8HI V4SI])
182 ;; Same, with TImode added, for moves.
183 (define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
185 ;; Opaque structure types wider than TImode.
186 (define_mode_iterator VSTRUCT [EI OI CI XI])
188 ;; Number of instructions needed to load/store struct elements. FIXME!
189 (define_mode_attr V_slen [(EI "2") (OI "2") (CI "3") (XI "4")])
191 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
192 (define_mode_iterator VTAB [TI EI OI])
194 ;; vtbl<n> suffix for above modes.
195 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
198 (define_mode_iterator VW [V8QI V4HI V2SI])
201 (define_mode_iterator VN [V8HI V4SI V2DI])
203 ;; All supported vector modes (except singleton DImode).
204 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
206 ;; All supported vector modes (except those with 64-bit integer elements).
207 (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
209 ;; Supported integer vector modes (not 64 bit elements).
210 (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
212 ;; Supported integer vector modes (not singleton DI)
213 (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
215 ;; Vector modes, including 64-bit integer elements.
216 (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
218 ;; Vector modes including 64-bit integer elements, but no floats.
219 (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
221 ;; Vector modes for float->int conversions.
222 (define_mode_iterator VCVTF [V2SF V4SF])
224 ;; Vector modes form int->float conversions.
225 (define_mode_iterator VCVTI [V2SI V4SI])
227 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
228 (define_mode_iterator VMD [V4HI V2SI V2SF])
230 ;; Vector modes for quadword multiply-accumulate, etc. insns.
231 (define_mode_iterator VMQ [V8HI V4SI V4SF])
233 ;; Above modes combined.
234 (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
236 ;; As VMD, but integer modes only.
237 (define_mode_iterator VMDI [V4HI V2SI])
239 ;; As VMQ, but integer modes only.
240 (define_mode_iterator VMQI [V8HI V4SI])
242 ;; Above modes combined.
243 (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
245 ;; Modes with 8-bit and 16-bit elements.
246 (define_mode_iterator VX [V8QI V4HI V16QI V8HI])
248 ;; Modes with 8-bit elements.
249 (define_mode_iterator VE [V8QI V16QI])
251 ;; Modes with 64-bit elements only.
252 (define_mode_iterator V64 [DI V2DI])
254 ;; Modes with 32-bit elements only.
255 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
257 ;; (Opposite) mode to convert to/from for above conversions.
258 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
259 (V4SI "V4SF") (V4SF "V4SI")])
261 ;; Define element mode for each vector mode.
262 (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
263 (V4HI "HI") (V8HI "HI")
264 (V2SI "SI") (V4SI "SI")
265 (V2SF "SF") (V4SF "SF")
266 (DI "DI") (V2DI "DI")])
268 ;; Element modes for vector extraction, padded up to register size.
270 (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
271 (V4HI "SI") (V8HI "SI")
272 (V2SI "SI") (V4SI "SI")
273 (V2SF "SF") (V4SF "SF")
274 (DI "DI") (V2DI "DI")])
276 ;; Mode of pair of elements for each vector mode, to define transfer
277 ;; size for structure lane/dup loads and stores.
278 (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
279 (V4HI "SI") (V8HI "SI")
280 (V2SI "V2SI") (V4SI "V2SI")
281 (V2SF "V2SF") (V4SF "V2SF")
282 (DI "V2DI") (V2DI "V2DI")])
284 ;; Similar, for three elements.
285 ;; ??? Should we define extra modes so that sizes of all three-element
286 ;; accesses can be accurately represented?
287 (define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
288 (V4HI "V4HI") (V8HI "V4HI")
289 (V2SI "V4SI") (V4SI "V4SI")
290 (V2SF "V4SF") (V4SF "V4SF")
291 (DI "EI") (V2DI "EI")])
293 ;; Similar, for four elements.
294 (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
295 (V4HI "V4HI") (V8HI "V4HI")
296 (V2SI "V4SI") (V4SI "V4SI")
297 (V2SF "V4SF") (V4SF "V4SF")
298 (DI "OI") (V2DI "OI")])
300 ;; Register width from element mode
301 (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
302 (V4HI "P") (V8HI "q")
303 (V2SI "P") (V4SI "q")
304 (V2SF "P") (V4SF "q")
305 (DI "P") (V2DI "q")])
307 ;; Wider modes with the same number of elements.
308 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
310 ;; Narrower modes with the same number of elements.
311 (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
313 ;; Modes with half the number of equal-sized elements.
314 (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
315 (V4SI "V2SI") (V4SF "V2SF")
318 ;; Same, but lower-case.
319 (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
320 (V4SI "v2si") (V4SF "v2sf")
323 ;; Modes with twice the number of equal-sized elements.
324 (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
325 (V2SI "V4SI") (V2SF "V4SF")
328 ;; Same, but lower-case.
329 (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
330 (V2SI "v4si") (V2SF "v4sf")
333 ;; Modes with double-width elements.
334 (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
335 (V4HI "V2SI") (V8HI "V4SI")
336 (V2SI "DI") (V4SI "V2DI")])
338 ;; Mode of result of comparison operations (and bit-select operand 1).
339 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
340 (V4HI "V4HI") (V8HI "V8HI")
341 (V2SI "V2SI") (V4SI "V4SI")
342 (V2SF "V2SI") (V4SF "V4SI")
343 (DI "DI") (V2DI "V2DI")])
345 ;; Get element type from double-width mode, for operations where we don't care
347 (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
348 (V4HI "i16") (V8HI "i16")
349 (V2SI "i32") (V4SI "i32")
350 (DI "i64") (V2DI "i64")
351 (V2SF "f32") (V4SF "f32")])
353 ;; Same, but for operations which work on signed values.
354 (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
355 (V4HI "s16") (V8HI "s16")
356 (V2SI "s32") (V4SI "s32")
357 (DI "s64") (V2DI "s64")
358 (V2SF "f32") (V4SF "f32")])
360 ;; Same, but for operations which work on unsigned values.
361 (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
362 (V4HI "u16") (V8HI "u16")
363 (V2SI "u32") (V4SI "u32")
364 (DI "u64") (V2DI "u64")
365 (V2SF "f32") (V4SF "f32")])
367 ;; Element types for extraction of unsigned scalars.
368 (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
369 (V4HI "u16") (V8HI "u16")
370 (V2SI "32") (V4SI "32")
371 (V2SF "32") (V4SF "32")])
373 (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
374 (V4HI "16") (V8HI "16")
375 (V2SI "32") (V4SI "32")
376 (DI "64") (V2DI "64")
377 (V2SF "32") (V4SF "32")])
379 ;; Element sizes for duplicating ARM registers to all elements of a vector.
380 (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
382 ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
383 (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
384 (V4HI "TI") (V8HI "OI")
385 (V2SI "TI") (V4SI "OI")
386 (V2SF "TI") (V4SF "OI")
387 (DI "TI") (V2DI "OI")])
389 ;; Same, but lower-case.
390 (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
391 (V4HI "ti") (V8HI "oi")
392 (V2SI "ti") (V4SI "oi")
393 (V2SF "ti") (V4SF "oi")
394 (DI "ti") (V2DI "oi")])
396 ;; Operations on two halves of a quadword vector.
397 (define_code_iterator vqh_ops [plus smin smax umin umax])
399 ;; Same, without unsigned variants (for use with *SFmode pattern).
400 (define_code_iterator vqhs_ops [plus smin smax])
402 ;; Assembler mnemonics for above codes.
403 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
404 (umin "vmin") (umax "vmax")])
406 ;; Signs of above, where relevant.
407 (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
410 ;; Extra suffix on some 64-bit insn names (to avoid collision with standard
411 ;; names which we don't want to define).
412 (define_mode_attr V_suf64 [(V8QI "") (V16QI "")
416 (DI "_neon") (V2DI "")])
418 ;; Scalars to be presented to scalar multiplication instructions
419 ;; must satisfy the following constraints.
420 ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
421 ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
422 ;; This mode attribute is used to obtain the correct register constraints.
423 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
424 (V8HI "x") (V4SI "t") (V4SF "t")])
426 ;; Attribute used to permit string comparisons against <VQH_mnem> in
427 ;; neon_type attribute definitions.
428 (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd"))
430 ;; Predicates used for setting neon_type
432 (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
433 (V4HI "false") (V8HI "false")
434 (V2SI "false") (V4SI "false")
435 (V2SF "true") (V4SF "true")
436 (DI "false") (V2DI "false")])
438 (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
439 (V4HI "true") (V8HI "true")
440 (V2SI "false") (V4SI "false")
441 (V2SF "false") (V4SF "false")
442 (DI "false") (V2DI "false")])
445 (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
446 (V4HI "true") (V8HI "false")
447 (V2SI "true") (V4SI "false")
448 (V2SF "true") (V4SF "false")
449 (DI "true") (V2DI "false")])
451 (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
452 (V4HI "4") (V8HI "8")
453 (V2SI "2") (V4SI "4")
454 (V2SF "2") (V4SF "4")
455 (DI "1") (V2DI "2")])
457 (define_insn "*neon_mov<mode>"
458 [(set (match_operand:VD 0 "nonimmediate_operand"
459 "=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
460 (match_operand:VD 1 "general_operand"
461 " w,w, Dn,Uvi, w, r, r, Usi,r"))]
464 if (which_alternative == 2)
467 static char templ[40];
469 is_valid = neon_immediate_valid_for_move (operands[1], <MODE>mode,
470 &operands[1], &width);
472 gcc_assert (is_valid != 0);
475 return "vmov.f32\t%P0, %1 @ <mode>";
477 sprintf (templ, "vmov.i%d\t%%P0, %%1 @ <mode>", width);
482 /* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp
483 below must be changed to output_move_neon (which will use the
484 element/structure loads/stores), and the constraint changed to 'Um' instead
487 switch (which_alternative)
489 case 0: return "vmov\t%P0, %P1 @ <mode>";
490 case 1: case 3: return output_move_vfp (operands);
491 case 2: gcc_unreachable ();
492 case 4: return "vmov\t%Q0, %R0, %P1 @ <mode>";
493 case 5: return "vmov\t%P0, %Q1, %R1 @ <mode>";
494 default: return output_move_double (operands);
497 [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
498 (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu,load2,store2")
499 (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
500 (set_attr "length" "4,4,4,4,4,4,8,8,8")
501 (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*")
502 (set_attr "neg_pool_range" "*,*,*,1008,*,*,*,1008,*")])
504 (define_insn "*neon_mov<mode>"
505 [(set (match_operand:VQXMOV 0 "nonimmediate_operand"
506 "=w,Un,w, w, ?r,?w,?r,?r, ?Us")
507 (match_operand:VQXMOV 1 "general_operand"
508 " w,w, Dn,Uni, w, r, r, Usi, r"))]
511 if (which_alternative == 2)
514 static char templ[40];
516 is_valid = neon_immediate_valid_for_move (operands[1], <MODE>mode,
517 &operands[1], &width);
519 gcc_assert (is_valid != 0);
522 return "vmov.f32\t%q0, %1 @ <mode>";
524 sprintf (templ, "vmov.i%d\t%%q0, %%1 @ <mode>", width);
529 switch (which_alternative)
531 case 0: return "vmov\t%q0, %q1 @ <mode>";
532 case 1: case 3: return output_move_neon (operands);
533 case 2: gcc_unreachable ();
534 case 4: return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
535 case 5: return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
536 default: return output_move_quad (operands);
539 [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
540 neon_mrrc,neon_mcr_2_mcrr,*,*,*")
541 (set_attr "type" "*,*,*,*,*,*,alu,load4,store4")
542 (set_attr "insn" "*,*,*,*,*,*,mov,*,*")
543 (set_attr "length" "4,8,4,8,8,8,16,8,16")
544 (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*")
545 (set_attr "neg_pool_range" "*,*,*,1008,*,*,*,1008,*")])
547 (define_expand "movti"
548 [(set (match_operand:TI 0 "nonimmediate_operand" "")
549 (match_operand:TI 1 "general_operand" ""))]
554 (define_expand "mov<mode>"
555 [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "")
556 (match_operand:VSTRUCT 1 "general_operand" ""))]
561 (define_insn "*neon_mov<mode>"
562 [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w")
563 (match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))]
566 switch (which_alternative)
569 case 1: case 2: return output_move_neon (operands);
570 default: gcc_unreachable ();
573 [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_ldm_2")
574 (set_attr "length" "<V_slen>,<V_slen>,<V_slen>")])
577 [(set (match_operand:EI 0 "s_register_operand" "")
578 (match_operand:EI 1 "s_register_operand" ""))]
579 "TARGET_NEON && reload_completed"
580 [(set (match_dup 0) (match_dup 1))
581 (set (match_dup 2) (match_dup 3))]
583 int rdest = REGNO (operands[0]);
584 int rsrc = REGNO (operands[1]);
587 dest[0] = gen_rtx_REG (TImode, rdest);
588 src[0] = gen_rtx_REG (TImode, rsrc);
589 dest[1] = gen_rtx_REG (DImode, rdest + 4);
590 src[1] = gen_rtx_REG (DImode, rsrc + 4);
592 neon_disambiguate_copy (operands, dest, src, 2);
596 [(set (match_operand:OI 0 "s_register_operand" "")
597 (match_operand:OI 1 "s_register_operand" ""))]
598 "TARGET_NEON && reload_completed"
599 [(set (match_dup 0) (match_dup 1))
600 (set (match_dup 2) (match_dup 3))]
602 int rdest = REGNO (operands[0]);
603 int rsrc = REGNO (operands[1]);
606 dest[0] = gen_rtx_REG (TImode, rdest);
607 src[0] = gen_rtx_REG (TImode, rsrc);
608 dest[1] = gen_rtx_REG (TImode, rdest + 4);
609 src[1] = gen_rtx_REG (TImode, rsrc + 4);
611 neon_disambiguate_copy (operands, dest, src, 2);
615 [(set (match_operand:CI 0 "s_register_operand" "")
616 (match_operand:CI 1 "s_register_operand" ""))]
617 "TARGET_NEON && reload_completed"
618 [(set (match_dup 0) (match_dup 1))
619 (set (match_dup 2) (match_dup 3))
620 (set (match_dup 4) (match_dup 5))]
622 int rdest = REGNO (operands[0]);
623 int rsrc = REGNO (operands[1]);
626 dest[0] = gen_rtx_REG (TImode, rdest);
627 src[0] = gen_rtx_REG (TImode, rsrc);
628 dest[1] = gen_rtx_REG (TImode, rdest + 4);
629 src[1] = gen_rtx_REG (TImode, rsrc + 4);
630 dest[2] = gen_rtx_REG (TImode, rdest + 8);
631 src[2] = gen_rtx_REG (TImode, rsrc + 8);
633 neon_disambiguate_copy (operands, dest, src, 3);
637 [(set (match_operand:XI 0 "s_register_operand" "")
638 (match_operand:XI 1 "s_register_operand" ""))]
639 "TARGET_NEON && reload_completed"
640 [(set (match_dup 0) (match_dup 1))
641 (set (match_dup 2) (match_dup 3))
642 (set (match_dup 4) (match_dup 5))
643 (set (match_dup 6) (match_dup 7))]
645 int rdest = REGNO (operands[0]);
646 int rsrc = REGNO (operands[1]);
649 dest[0] = gen_rtx_REG (TImode, rdest);
650 src[0] = gen_rtx_REG (TImode, rsrc);
651 dest[1] = gen_rtx_REG (TImode, rdest + 4);
652 src[1] = gen_rtx_REG (TImode, rsrc + 4);
653 dest[2] = gen_rtx_REG (TImode, rdest + 8);
654 src[2] = gen_rtx_REG (TImode, rsrc + 8);
655 dest[3] = gen_rtx_REG (TImode, rdest + 12);
656 src[3] = gen_rtx_REG (TImode, rsrc + 12);
658 neon_disambiguate_copy (operands, dest, src, 4);
661 (define_insn "vec_set<mode>_internal"
662 [(set (match_operand:VD 0 "s_register_operand" "=w")
665 (match_operand:<V_elem> 1 "s_register_operand" "r"))
666 (match_operand:VD 3 "s_register_operand" "0")
667 (match_operand:SI 2 "immediate_operand" "i")))]
670 int elt = ffs ((int) INTVAL (operands[2]) - 1);
671 if (BYTES_BIG_ENDIAN)
672 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
673 operands[2] = GEN_INT (elt);
675 return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
677 [(set_attr "predicable" "yes")
678 (set_attr "neon_type" "neon_mcr")])
680 (define_insn "vec_set<mode>_internal"
681 [(set (match_operand:VQ 0 "s_register_operand" "=w")
684 (match_operand:<V_elem> 1 "s_register_operand" "r"))
685 (match_operand:VQ 3 "s_register_operand" "0")
686 (match_operand:SI 2 "immediate_operand" "i")))]
689 HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1;
690 int half_elts = GET_MODE_NUNITS (<MODE>mode) / 2;
691 int elt = elem % half_elts;
692 int hi = (elem / half_elts) * 2;
693 int regno = REGNO (operands[0]);
695 if (BYTES_BIG_ENDIAN)
696 elt = half_elts - 1 - elt;
698 operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
699 operands[2] = GEN_INT (elt);
701 return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
703 [(set_attr "predicable" "yes")
704 (set_attr "neon_type" "neon_mcr")]
707 (define_insn "vec_setv2di_internal"
708 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
711 (match_operand:DI 1 "s_register_operand" "r"))
712 (match_operand:V2DI 3 "s_register_operand" "0")
713 (match_operand:SI 2 "immediate_operand" "i")))]
716 HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1;
717 int regno = REGNO (operands[0]) + 2 * elem;
719 operands[0] = gen_rtx_REG (DImode, regno);
721 return "vmov%?.64\t%P0, %Q1, %R1";
723 [(set_attr "predicable" "yes")
724 (set_attr "neon_type" "neon_mcr_2_mcrr")]
727 (define_expand "vec_set<mode>"
728 [(match_operand:VDQ 0 "s_register_operand" "")
729 (match_operand:<V_elem> 1 "s_register_operand" "")
730 (match_operand:SI 2 "immediate_operand" "")]
733 HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
734 emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
735 GEN_INT (elem), operands[0]));
739 (define_insn "vec_extract<mode>"
740 [(set (match_operand:<V_elem> 0 "s_register_operand" "=r")
742 (match_operand:VD 1 "s_register_operand" "w")
743 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
746 if (BYTES_BIG_ENDIAN)
748 int elt = INTVAL (operands[2]);
749 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
750 operands[2] = GEN_INT (elt);
752 return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
754 [(set_attr "predicable" "yes")
755 (set_attr "neon_type" "neon_bp_simple")]
758 (define_insn "vec_extract<mode>"
759 [(set (match_operand:<V_elem> 0 "s_register_operand" "=r")
761 (match_operand:VQ 1 "s_register_operand" "w")
762 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
765 int half_elts = GET_MODE_NUNITS (<MODE>mode) / 2;
766 int elt = INTVAL (operands[2]) % half_elts;
767 int hi = (INTVAL (operands[2]) / half_elts) * 2;
768 int regno = REGNO (operands[1]);
770 if (BYTES_BIG_ENDIAN)
771 elt = half_elts - 1 - elt;
773 operands[1] = gen_rtx_REG (<V_HALF>mode, regno + hi);
774 operands[2] = GEN_INT (elt);
776 return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
778 [(set_attr "predicable" "yes")
779 (set_attr "neon_type" "neon_bp_simple")]
782 (define_insn "vec_extractv2di"
783 [(set (match_operand:DI 0 "s_register_operand" "=r")
785 (match_operand:V2DI 1 "s_register_operand" "w")
786 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
789 int regno = REGNO (operands[1]) + INTVAL (operands[2]);
791 operands[1] = gen_rtx_REG (DImode, regno);
793 return "vmov%?.64\t%Q0, %R0, %P1";
795 [(set_attr "predicable" "yes")
796 (set_attr "neon_type" "neon_int_1")]
799 (define_expand "vec_init<mode>"
800 [(match_operand:VDQ 0 "s_register_operand" "")
801 (match_operand 1 "" "")]
804 neon_expand_vector_init (operands[0], operands[1]);
808 ;; Doubleword and quadword arithmetic.
810 ;; NOTE: vadd/vsub and some other instructions also support 64-bit integer
811 ;; element size, which we could potentially use for "long long" operations. We
812 ;; don't want to do this at present though, because moving values from the
813 ;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is
814 ;; easy to do with ARM instructions anyway.
816 (define_insn "*add<mode>3_neon"
817 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
818 (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
819 (match_operand:VDQ 2 "s_register_operand" "w")))]
821 "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
822 [(set (attr "neon_type")
823 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
824 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
825 (const_string "neon_fp_vadd_ddd_vabs_dd")
826 (const_string "neon_fp_vadd_qqq_vabs_qq"))
827 (const_string "neon_int_1")))]
830 (define_insn "*sub<mode>3_neon"
831 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
832 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
833 (match_operand:VDQ 2 "s_register_operand" "w")))]
835 "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
836 [(set (attr "neon_type")
837 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
838 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
839 (const_string "neon_fp_vadd_ddd_vabs_dd")
840 (const_string "neon_fp_vadd_qqq_vabs_qq"))
841 (const_string "neon_int_2")))]
844 (define_insn "*mul<mode>3_neon"
845 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
846 (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
847 (match_operand:VDQ 2 "s_register_operand" "w")))]
849 "vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
850 [(set (attr "neon_type")
851 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
852 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
853 (const_string "neon_fp_vadd_ddd_vabs_dd")
854 (const_string "neon_fp_vadd_qqq_vabs_qq"))
855 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
857 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
858 (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
859 (const_string "neon_mul_qqq_8_16_32_ddd_32"))
860 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
861 (const_string "neon_mul_qqq_8_16_32_ddd_32")
862 (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
865 (define_insn "*mul<mode>3add<mode>_neon"
866 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
867 (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
868 (match_operand:VDQ 3 "s_register_operand" "w"))
869 (match_operand:VDQ 1 "s_register_operand" "0")))]
871 "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
872 [(set (attr "neon_type")
873 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
874 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
875 (const_string "neon_fp_vmla_ddd")
876 (const_string "neon_fp_vmla_qqq"))
877 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
879 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
880 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
881 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
882 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
883 (const_string "neon_mla_qqq_8_16")
884 (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
887 (define_insn "*mul<mode>3neg<mode>add<mode>_neon"
888 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
889 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
890 (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
891 (match_operand:VDQ 3 "s_register_operand" "w"))))]
893 "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
894 [(set (attr "neon_type")
895 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
896 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
897 (const_string "neon_fp_vmla_ddd")
898 (const_string "neon_fp_vmla_qqq"))
899 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
901 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
902 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
903 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
904 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
905 (const_string "neon_mla_qqq_8_16")
906 (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
909 (define_insn "ior<mode>3"
910 [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
911 (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
912 (match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))]
915 switch (which_alternative)
917 case 0: return "vorr\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
918 case 1: return neon_output_logic_immediate ("vorr", &operands[2],
919 <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));
920 default: gcc_unreachable ();
923 [(set_attr "neon_type" "neon_int_1")]
926 (define_insn "iordi3_neon"
927 [(set (match_operand:DI 0 "s_register_operand" "=w,w")
928 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
929 (match_operand:DI 2 "neon_logic_op2" "w,Dl")]
933 switch (which_alternative)
935 case 0: return "vorr\t%P0, %P1, %P2";
936 case 1: return neon_output_logic_immediate ("vorr", &operands[2],
937 DImode, 0, VALID_NEON_QREG_MODE (DImode));
938 default: gcc_unreachable ();
941 [(set_attr "neon_type" "neon_int_1")]
944 ;; The concrete forms of the Neon immediate-logic instructions are vbic and
945 ;; vorr. We support the pseudo-instruction vand instead, because that
946 ;; corresponds to the canonical form the middle-end expects to use for
947 ;; immediate bitwise-ANDs.
949 (define_insn "and<mode>3"
950 [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
951 (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
952 (match_operand:VDQ 2 "neon_inv_logic_op2" "w,DL")))]
955 switch (which_alternative)
957 case 0: return "vand\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
958 case 1: return neon_output_logic_immediate ("vand", &operands[2],
959 <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));
960 default: gcc_unreachable ();
963 [(set_attr "neon_type" "neon_int_1")]
966 (define_insn "anddi3_neon"
967 [(set (match_operand:DI 0 "s_register_operand" "=w,w")
968 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
969 (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")]
973 switch (which_alternative)
975 case 0: return "vand\t%P0, %P1, %P2";
976 case 1: return neon_output_logic_immediate ("vand", &operands[2],
977 DImode, 1, VALID_NEON_QREG_MODE (DImode));
978 default: gcc_unreachable ();
981 [(set_attr "neon_type" "neon_int_1")]
984 (define_insn "orn<mode>3_neon"
985 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
986 (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
987 (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
989 "vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
990 [(set_attr "neon_type" "neon_int_1")]
993 (define_insn "orndi3_neon"
994 [(set (match_operand:DI 0 "s_register_operand" "=w")
995 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
996 (match_operand:DI 2 "s_register_operand" "w")]
999 "vorn\t%P0, %P1, %P2"
1000 [(set_attr "neon_type" "neon_int_1")]
1003 (define_insn "bic<mode>3_neon"
1004 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
1005 (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
1006 (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
1008 "vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1009 [(set_attr "neon_type" "neon_int_1")]
1012 (define_insn "bicdi3_neon"
1013 [(set (match_operand:DI 0 "s_register_operand" "=w")
1014 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
1015 (match_operand:DI 2 "s_register_operand" "w")]
1018 "vbic\t%P0, %P1, %P2"
1019 [(set_attr "neon_type" "neon_int_1")]
1022 (define_insn "xor<mode>3"
1023 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
1024 (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
1025 (match_operand:VDQ 2 "s_register_operand" "w")))]
1027 "veor\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1028 [(set_attr "neon_type" "neon_int_1")]
1031 (define_insn "xordi3_neon"
1032 [(set (match_operand:DI 0 "s_register_operand" "=w")
1033 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
1034 (match_operand:DI 2 "s_register_operand" "w")]
1037 "veor\t%P0, %P1, %P2"
1038 [(set_attr "neon_type" "neon_int_1")]
1041 (define_insn "one_cmpl<mode>2"
1042 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
1043 (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))]
1045 "vmvn\t%<V_reg>0, %<V_reg>1"
1046 [(set_attr "neon_type" "neon_int_1")]
1049 (define_insn "abs<mode>2"
1050 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1051 (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
1053 "vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
1054 [(set (attr "neon_type")
1055 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1056 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1057 (const_string "neon_fp_vadd_ddd_vabs_dd")
1058 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1059 (const_string "neon_int_3")))]
1062 (define_insn "neg<mode>2"
1063 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1064 (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
1066 "vneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
1067 [(set (attr "neon_type")
1068 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1069 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1070 (const_string "neon_fp_vadd_ddd_vabs_dd")
1071 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1072 (const_string "neon_int_3")))]
1075 (define_insn "*umin<mode>3_neon"
1076 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1077 (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
1078 (match_operand:VDQIW 2 "s_register_operand" "w")))]
1080 "vmin.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1081 [(set_attr "neon_type" "neon_int_5")]
1084 (define_insn "*umax<mode>3_neon"
1085 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1086 (umax:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
1087 (match_operand:VDQIW 2 "s_register_operand" "w")))]
1089 "vmax.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1090 [(set_attr "neon_type" "neon_int_5")]
1093 (define_insn "*smin<mode>3_neon"
1094 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1095 (smin:VDQW (match_operand:VDQW 1 "s_register_operand" "w")
1096 (match_operand:VDQW 2 "s_register_operand" "w")))]
1098 "vmin.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1099 [(set (attr "neon_type")
1100 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1101 (const_string "neon_fp_vadd_ddd_vabs_dd")
1102 (const_string "neon_int_5")))]
1105 (define_insn "*smax<mode>3_neon"
1106 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1107 (smax:VDQW (match_operand:VDQW 1 "s_register_operand" "w")
1108 (match_operand:VDQW 2 "s_register_operand" "w")))]
1110 "vmax.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1111 [(set (attr "neon_type")
1112 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1113 (const_string "neon_fp_vadd_ddd_vabs_dd")
1114 (const_string "neon_int_5")))]
1117 ; TODO: V2DI shifts are current disabled because there are bugs in the
1118 ; generic vectorizer code. It ends up creating a V2DI constructor with
1121 (define_insn "vashl<mode>3"
1122 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1123 (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
1124 (match_operand:VDQIW 2 "s_register_operand" "w")))]
1126 "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1127 [(set (attr "neon_type")
1128 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1129 (const_string "neon_vshl_ddd")
1130 (const_string "neon_shift_3")))]
1133 ; Used for implementing logical shift-right, which is a left-shift by a negative
1134 ; amount, with signed operands. This is essentially the same as ashl<mode>3
1135 ; above, but using an unspec in case GCC tries anything tricky with negative
1138 (define_insn "ashl<mode>3_signed"
1139 [(set (match_operand:VDQI 0 "s_register_operand" "=w")
1140 (unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w")
1141 (match_operand:VDQI 2 "s_register_operand" "w")]
1142 UNSPEC_ASHIFT_SIGNED))]
1144 "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1145 [(set (attr "neon_type")
1146 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1147 (const_string "neon_vshl_ddd")
1148 (const_string "neon_shift_3")))]
1151 ; Used for implementing logical shift-right, which is a left-shift by a negative
1152 ; amount, with unsigned operands.
1154 (define_insn "ashl<mode>3_unsigned"
1155 [(set (match_operand:VDQI 0 "s_register_operand" "=w")
1156 (unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w")
1157 (match_operand:VDQI 2 "s_register_operand" "w")]
1158 UNSPEC_ASHIFT_UNSIGNED))]
1160 "vshl.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1161 [(set (attr "neon_type")
1162 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1163 (const_string "neon_vshl_ddd")
1164 (const_string "neon_shift_3")))]
1167 (define_expand "vashr<mode>3"
1168 [(set (match_operand:VDQIW 0 "s_register_operand" "")
1169 (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
1170 (match_operand:VDQIW 2 "s_register_operand" "")))]
1173 rtx neg = gen_reg_rtx (<MODE>mode);
1175 emit_insn (gen_neg<mode>2 (neg, operands[2]));
1176 emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
1181 (define_expand "vlshr<mode>3"
1182 [(set (match_operand:VDQIW 0 "s_register_operand" "")
1183 (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
1184 (match_operand:VDQIW 2 "s_register_operand" "")))]
1187 rtx neg = gen_reg_rtx (<MODE>mode);
1189 emit_insn (gen_neg<mode>2 (neg, operands[2]));
1190 emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
1195 ;; Widening operations
1197 (define_insn "widen_ssum<mode>3"
1198 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1199 (plus:<V_widen> (sign_extend:<V_widen>
1200 (match_operand:VW 1 "s_register_operand" "%w"))
1201 (match_operand:<V_widen> 2 "s_register_operand" "w")))]
1203 "vaddw.<V_s_elem>\t%q0, %q2, %P1"
1204 [(set_attr "neon_type" "neon_int_3")]
1207 (define_insn "widen_usum<mode>3"
1208 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1209 (plus:<V_widen> (zero_extend:<V_widen>
1210 (match_operand:VW 1 "s_register_operand" "%w"))
1211 (match_operand:<V_widen> 2 "s_register_operand" "w")))]
1213 "vaddw.<V_u_elem>\t%q0, %q2, %P1"
1214 [(set_attr "neon_type" "neon_int_3")]
1217 ;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit
1218 ;; shift-count granularity. That's good enough for the middle-end's current
1221 (define_expand "vec_shr_<mode>"
1222 [(match_operand:VDQ 0 "s_register_operand" "")
1223 (match_operand:VDQ 1 "s_register_operand" "")
1224 (match_operand:SI 2 "const_multiple_of_8_operand" "")]
1228 HOST_WIDE_INT num_bits = INTVAL (operands[2]);
1229 const int width = GET_MODE_BITSIZE (<MODE>mode);
1230 const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
1231 rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
1232 (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
1234 if (num_bits == width)
1236 emit_move_insn (operands[0], operands[1]);
1240 zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
1241 operands[0] = gen_lowpart (bvecmode, operands[0]);
1242 operands[1] = gen_lowpart (bvecmode, operands[1]);
1244 emit_insn (gen_ext (operands[0], operands[1], zero_reg,
1245 GEN_INT (num_bits / BITS_PER_UNIT)));
1249 (define_expand "vec_shl_<mode>"
1250 [(match_operand:VDQ 0 "s_register_operand" "")
1251 (match_operand:VDQ 1 "s_register_operand" "")
1252 (match_operand:SI 2 "const_multiple_of_8_operand" "")]
1256 HOST_WIDE_INT num_bits = INTVAL (operands[2]);
1257 const int width = GET_MODE_BITSIZE (<MODE>mode);
1258 const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
1259 rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
1260 (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
1264 emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
1268 num_bits = width - num_bits;
1270 zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
1271 operands[0] = gen_lowpart (bvecmode, operands[0]);
1272 operands[1] = gen_lowpart (bvecmode, operands[1]);
1274 emit_insn (gen_ext (operands[0], zero_reg, operands[1],
1275 GEN_INT (num_bits / BITS_PER_UNIT)));
1279 ;; Helpers for quad-word reduction operations
1281 ; Add (or smin, smax...) the low N/2 elements of the N-element vector
1282 ; operand[1] to the high N/2 elements of same. Put the result in operand[0], an
1283 ; N/2-element vector.
1285 (define_insn "quad_halves_<code>v4si"
1286 [(set (match_operand:V2SI 0 "s_register_operand" "=w")
1288 (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
1289 (parallel [(const_int 0) (const_int 1)]))
1290 (vec_select:V2SI (match_dup 1)
1291 (parallel [(const_int 2) (const_int 3)]))))]
1293 "<VQH_mnem>.<VQH_sign>32\t%P0, %e1, %f1"
1294 [(set_attr "vqh_mnem" "<VQH_mnem>")
1295 (set (attr "neon_type")
1296 (if_then_else (eq_attr "vqh_mnem" "vadd")
1297 (const_string "neon_int_1") (const_string "neon_int_5")))]
1300 (define_insn "quad_halves_<code>v4sf"
1301 [(set (match_operand:V2SF 0 "s_register_operand" "=w")
1303 (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
1304 (parallel [(const_int 0) (const_int 1)]))
1305 (vec_select:V2SF (match_dup 1)
1306 (parallel [(const_int 2) (const_int 3)]))))]
1308 "<VQH_mnem>.f32\t%P0, %e1, %f1"
1309 [(set_attr "vqh_mnem" "<VQH_mnem>")
1310 (set (attr "neon_type")
1311 (if_then_else (eq_attr "vqh_mnem" "vadd")
1312 (const_string "neon_int_1") (const_string "neon_int_5")))]
1315 (define_insn "quad_halves_<code>v8hi"
1316 [(set (match_operand:V4HI 0 "s_register_operand" "+w")
1318 (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
1319 (parallel [(const_int 0) (const_int 1)
1320 (const_int 2) (const_int 3)]))
1321 (vec_select:V4HI (match_dup 1)
1322 (parallel [(const_int 4) (const_int 5)
1323 (const_int 6) (const_int 7)]))))]
1325 "<VQH_mnem>.<VQH_sign>16\t%P0, %e1, %f1"
1326 [(set_attr "vqh_mnem" "<VQH_mnem>")
1327 (set (attr "neon_type")
1328 (if_then_else (eq_attr "vqh_mnem" "vadd")
1329 (const_string "neon_int_1") (const_string "neon_int_5")))]
1332 (define_insn "quad_halves_<code>v16qi"
1333 [(set (match_operand:V8QI 0 "s_register_operand" "+w")
1335 (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
1336 (parallel [(const_int 0) (const_int 1)
1337 (const_int 2) (const_int 3)
1338 (const_int 4) (const_int 5)
1339 (const_int 6) (const_int 7)]))
1340 (vec_select:V8QI (match_dup 1)
1341 (parallel [(const_int 8) (const_int 9)
1342 (const_int 10) (const_int 11)
1343 (const_int 12) (const_int 13)
1344 (const_int 14) (const_int 15)]))))]
1346 "<VQH_mnem>.<VQH_sign>8\t%P0, %e1, %f1"
1347 [(set_attr "vqh_mnem" "<VQH_mnem>")
1348 (set (attr "neon_type")
1349 (if_then_else (eq_attr "vqh_mnem" "vadd")
1350 (const_string "neon_int_1") (const_string "neon_int_5")))]
1353 ; FIXME: We wouldn't need the following insns if we could write subregs of
1354 ; vector registers. Make an attempt at removing unnecessary moves, though
1355 ; we're really at the mercy of the register allocator.
1357 (define_insn "move_lo_quad_v4si"
1358 [(set (match_operand:V4SI 0 "s_register_operand" "+w")
1360 (match_operand:V2SI 1 "s_register_operand" "w")
1361 (vec_select:V2SI (match_dup 0)
1362 (parallel [(const_int 2) (const_int 3)]))))]
1365 int dest = REGNO (operands[0]);
1366 int src = REGNO (operands[1]);
1369 return "vmov\t%e0, %P1";
1373 [(set_attr "neon_type" "neon_bp_simple")]
1376 (define_insn "move_lo_quad_v4sf"
1377 [(set (match_operand:V4SF 0 "s_register_operand" "+w")
1379 (match_operand:V2SF 1 "s_register_operand" "w")
1380 (vec_select:V2SF (match_dup 0)
1381 (parallel [(const_int 2) (const_int 3)]))))]
1384 int dest = REGNO (operands[0]);
1385 int src = REGNO (operands[1]);
1388 return "vmov\t%e0, %P1";
1392 [(set_attr "neon_type" "neon_bp_simple")]
1395 (define_insn "move_lo_quad_v8hi"
1396 [(set (match_operand:V8HI 0 "s_register_operand" "+w")
1398 (match_operand:V4HI 1 "s_register_operand" "w")
1399 (vec_select:V4HI (match_dup 0)
1400 (parallel [(const_int 4) (const_int 5)
1401 (const_int 6) (const_int 7)]))))]
1404 int dest = REGNO (operands[0]);
1405 int src = REGNO (operands[1]);
1408 return "vmov\t%e0, %P1";
1412 [(set_attr "neon_type" "neon_bp_simple")]
1415 (define_insn "move_lo_quad_v16qi"
1416 [(set (match_operand:V16QI 0 "s_register_operand" "+w")
1418 (match_operand:V8QI 1 "s_register_operand" "w")
1419 (vec_select:V8QI (match_dup 0)
1420 (parallel [(const_int 8) (const_int 9)
1421 (const_int 10) (const_int 11)
1422 (const_int 12) (const_int 13)
1423 (const_int 14) (const_int 15)]))))]
1426 int dest = REGNO (operands[0]);
1427 int src = REGNO (operands[1]);
1430 return "vmov\t%e0, %P1";
1434 [(set_attr "neon_type" "neon_bp_simple")]
1437 ;; Reduction operations
1439 (define_expand "reduc_splus_<mode>"
1440 [(match_operand:VD 0 "s_register_operand" "")
1441 (match_operand:VD 1 "s_register_operand" "")]
1444 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
1445 &gen_neon_vpadd_internal<mode>);
1449 (define_expand "reduc_splus_<mode>"
1450 [(match_operand:VQ 0 "s_register_operand" "")
1451 (match_operand:VQ 1 "s_register_operand" "")]
1454 rtx step1 = gen_reg_rtx (<V_HALF>mode);
1455 rtx res_d = gen_reg_rtx (<V_HALF>mode);
1457 emit_insn (gen_quad_halves_plus<mode> (step1, operands[1]));
1458 emit_insn (gen_reduc_splus_<V_half> (res_d, step1));
1459 emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
1464 (define_insn "reduc_splus_v2di"
1465 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
1466 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")]
1469 "vadd.i64\t%e0, %e1, %f1"
1470 [(set_attr "neon_type" "neon_int_1")]
1473 ;; NEON does not distinguish between signed and unsigned addition except on
1474 ;; widening operations.
1475 (define_expand "reduc_uplus_<mode>"
1476 [(match_operand:VDQI 0 "s_register_operand" "")
1477 (match_operand:VDQI 1 "s_register_operand" "")]
1480 emit_insn (gen_reduc_splus_<mode> (operands[0], operands[1]));
1484 (define_expand "reduc_smin_<mode>"
1485 [(match_operand:VD 0 "s_register_operand" "")
1486 (match_operand:VD 1 "s_register_operand" "")]
1489 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
1490 &gen_neon_vpsmin<mode>);
1494 (define_expand "reduc_smin_<mode>"
1495 [(match_operand:VQ 0 "s_register_operand" "")
1496 (match_operand:VQ 1 "s_register_operand" "")]
1499 rtx step1 = gen_reg_rtx (<V_HALF>mode);
1500 rtx res_d = gen_reg_rtx (<V_HALF>mode);
1502 emit_insn (gen_quad_halves_smin<mode> (step1, operands[1]));
1503 emit_insn (gen_reduc_smin_<V_half> (res_d, step1));
1504 emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
1509 (define_expand "reduc_smax_<mode>"
1510 [(match_operand:VD 0 "s_register_operand" "")
1511 (match_operand:VD 1 "s_register_operand" "")]
1514 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
1515 &gen_neon_vpsmax<mode>);
1519 (define_expand "reduc_smax_<mode>"
1520 [(match_operand:VQ 0 "s_register_operand" "")
1521 (match_operand:VQ 1 "s_register_operand" "")]
1524 rtx step1 = gen_reg_rtx (<V_HALF>mode);
1525 rtx res_d = gen_reg_rtx (<V_HALF>mode);
1527 emit_insn (gen_quad_halves_smax<mode> (step1, operands[1]));
1528 emit_insn (gen_reduc_smax_<V_half> (res_d, step1));
1529 emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
1534 (define_expand "reduc_umin_<mode>"
1535 [(match_operand:VDI 0 "s_register_operand" "")
1536 (match_operand:VDI 1 "s_register_operand" "")]
1539 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
1540 &gen_neon_vpumin<mode>);
1544 (define_expand "reduc_umin_<mode>"
1545 [(match_operand:VQI 0 "s_register_operand" "")
1546 (match_operand:VQI 1 "s_register_operand" "")]
1549 rtx step1 = gen_reg_rtx (<V_HALF>mode);
1550 rtx res_d = gen_reg_rtx (<V_HALF>mode);
1552 emit_insn (gen_quad_halves_umin<mode> (step1, operands[1]));
1553 emit_insn (gen_reduc_umin_<V_half> (res_d, step1));
1554 emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
1559 (define_expand "reduc_umax_<mode>"
1560 [(match_operand:VDI 0 "s_register_operand" "")
1561 (match_operand:VDI 1 "s_register_operand" "")]
1564 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
1565 &gen_neon_vpumax<mode>);
1569 (define_expand "reduc_umax_<mode>"
1570 [(match_operand:VQI 0 "s_register_operand" "")
1571 (match_operand:VQI 1 "s_register_operand" "")]
1574 rtx step1 = gen_reg_rtx (<V_HALF>mode);
1575 rtx res_d = gen_reg_rtx (<V_HALF>mode);
1577 emit_insn (gen_quad_halves_umax<mode> (step1, operands[1]));
1578 emit_insn (gen_reduc_umax_<V_half> (res_d, step1));
1579 emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
1584 (define_insn "neon_vpadd_internal<mode>"
1585 [(set (match_operand:VD 0 "s_register_operand" "=w")
1586 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
1587 (match_operand:VD 2 "s_register_operand" "w")]
1590 "vpadd.<V_if_elem>\t%P0, %P1, %P2"
1591 ;; Assume this schedules like vadd.
1592 [(set (attr "neon_type")
1593 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1594 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1595 (const_string "neon_fp_vadd_ddd_vabs_dd")
1596 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1597 (const_string "neon_int_1")))]
1600 (define_insn "neon_vpsmin<mode>"
1601 [(set (match_operand:VD 0 "s_register_operand" "=w")
1602 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
1603 (match_operand:VD 2 "s_register_operand" "w")]
1606 "vpmin.<V_s_elem>\t%P0, %P1, %P2"
1607 ;; Assume this schedules like vmin.
1608 [(set (attr "neon_type")
1609 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1610 (const_string "neon_fp_vadd_ddd_vabs_dd")
1611 (const_string "neon_int_5")))]
1614 (define_insn "neon_vpsmax<mode>"
1615 [(set (match_operand:VD 0 "s_register_operand" "=w")
1616 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
1617 (match_operand:VD 2 "s_register_operand" "w")]
1620 "vpmax.<V_s_elem>\t%P0, %P1, %P2"
1621 ;; Assume this schedules like vmax.
1622 [(set (attr "neon_type")
1623 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1624 (const_string "neon_fp_vadd_ddd_vabs_dd")
1625 (const_string "neon_int_5")))]
1628 (define_insn "neon_vpumin<mode>"
1629 [(set (match_operand:VDI 0 "s_register_operand" "=w")
1630 (unspec:VDI [(match_operand:VDI 1 "s_register_operand" "w")
1631 (match_operand:VDI 2 "s_register_operand" "w")]
1634 "vpmin.<V_u_elem>\t%P0, %P1, %P2"
1635 ;; Assume this schedules like umin.
1636 [(set_attr "neon_type" "neon_int_5")]
1639 (define_insn "neon_vpumax<mode>"
1640 [(set (match_operand:VDI 0 "s_register_operand" "=w")
1641 (unspec:VDI [(match_operand:VDI 1 "s_register_operand" "w")
1642 (match_operand:VDI 2 "s_register_operand" "w")]
1645 "vpmax.<V_u_elem>\t%P0, %P1, %P2"
1646 ;; Assume this schedules like umax.
1647 [(set_attr "neon_type" "neon_int_5")]
1650 ;; Saturating arithmetic
1652 ; NOTE: Neon supports many more saturating variants of instructions than the
1653 ; following, but these are all GCC currently understands.
1654 ; FIXME: Actually, GCC doesn't know how to create saturating add/sub by itself
1655 ; yet either, although these patterns may be used by intrinsics when they're
1658 (define_insn "*ss_add<mode>_neon"
1659 [(set (match_operand:VD 0 "s_register_operand" "=w")
1660 (ss_plus:VD (match_operand:VD 1 "s_register_operand" "w")
1661 (match_operand:VD 2 "s_register_operand" "w")))]
1663 "vqadd.<V_s_elem>\t%P0, %P1, %P2"
1664 [(set_attr "neon_type" "neon_int_4")]
1667 (define_insn "*us_add<mode>_neon"
1668 [(set (match_operand:VD 0 "s_register_operand" "=w")
1669 (us_plus:VD (match_operand:VD 1 "s_register_operand" "w")
1670 (match_operand:VD 2 "s_register_operand" "w")))]
1672 "vqadd.<V_u_elem>\t%P0, %P1, %P2"
1673 [(set_attr "neon_type" "neon_int_4")]
1676 (define_insn "*ss_sub<mode>_neon"
1677 [(set (match_operand:VD 0 "s_register_operand" "=w")
1678 (ss_minus:VD (match_operand:VD 1 "s_register_operand" "w")
1679 (match_operand:VD 2 "s_register_operand" "w")))]
1681 "vqsub.<V_s_elem>\t%P0, %P1, %P2"
1682 [(set_attr "neon_type" "neon_int_5")]
1685 (define_insn "*us_sub<mode>_neon"
1686 [(set (match_operand:VD 0 "s_register_operand" "=w")
1687 (us_minus:VD (match_operand:VD 1 "s_register_operand" "w")
1688 (match_operand:VD 2 "s_register_operand" "w")))]
1690 "vqsub.<V_u_elem>\t%P0, %P1, %P2"
1691 [(set_attr "neon_type" "neon_int_5")]
1694 ;; Patterns for builtins.
1696 ; good for plain vadd, vaddq.
1698 (define_insn "neon_vadd<mode>"
1699 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
1700 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
1701 (match_operand:VDQX 2 "s_register_operand" "w")
1702 (match_operand:SI 3 "immediate_operand" "i")]
1705 "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1706 [(set (attr "neon_type")
1707 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1708 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1709 (const_string "neon_fp_vadd_ddd_vabs_dd")
1710 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1711 (const_string "neon_int_1")))]
1714 ; operand 3 represents in bits:
1715 ; bit 0: signed (vs unsigned).
1716 ; bit 1: rounding (vs none).
1718 (define_insn "neon_vaddl<mode>"
1719 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1720 (unspec:<V_widen> [(match_operand:VDI 1 "s_register_operand" "w")
1721 (match_operand:VDI 2 "s_register_operand" "w")
1722 (match_operand:SI 3 "immediate_operand" "i")]
1725 "vaddl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
1726 [(set_attr "neon_type" "neon_int_3")]
1729 (define_insn "neon_vaddw<mode>"
1730 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1731 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "w")
1732 (match_operand:VDI 2 "s_register_operand" "w")
1733 (match_operand:SI 3 "immediate_operand" "i")]
1736 "vaddw.%T3%#<V_sz_elem>\t%q0, %q1, %P2"
1737 [(set_attr "neon_type" "neon_int_2")]
1742 (define_insn "neon_vhadd<mode>"
1743 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1744 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
1745 (match_operand:VDQIW 2 "s_register_operand" "w")
1746 (match_operand:SI 3 "immediate_operand" "i")]
1749 "v%O3hadd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1750 [(set_attr "neon_type" "neon_int_4")]
1753 (define_insn "neon_vqadd<mode>"
1754 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
1755 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
1756 (match_operand:VDQIX 2 "s_register_operand" "w")
1757 (match_operand:SI 3 "immediate_operand" "i")]
1760 "vqadd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1761 [(set_attr "neon_type" "neon_int_4")]
1764 (define_insn "neon_vaddhn<mode>"
1765 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
1766 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
1767 (match_operand:VN 2 "s_register_operand" "w")
1768 (match_operand:SI 3 "immediate_operand" "i")]
1771 "v%O3addhn.<V_if_elem>\t%P0, %q1, %q2"
1772 [(set_attr "neon_type" "neon_int_4")]
1775 (define_insn "neon_vmul<mode>"
1776 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1777 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
1778 (match_operand:VDQW 2 "s_register_operand" "w")
1779 (match_operand:SI 3 "immediate_operand" "i")]
1782 "vmul.%F3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1783 [(set (attr "neon_type")
1784 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1785 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1786 (const_string "neon_fp_vadd_ddd_vabs_dd")
1787 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1788 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1790 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1791 (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
1792 (const_string "neon_mul_qqq_8_16_32_ddd_32"))
1793 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1794 (const_string "neon_mul_qqq_8_16_32_ddd_32")
1795 (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
1798 (define_insn "neon_vmla<mode>"
1799 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1800 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
1801 (match_operand:VDQW 2 "s_register_operand" "w")
1802 (match_operand:VDQW 3 "s_register_operand" "w")
1803 (match_operand:SI 4 "immediate_operand" "i")]
1806 "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
1807 [(set (attr "neon_type")
1808 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1809 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1810 (const_string "neon_fp_vmla_ddd")
1811 (const_string "neon_fp_vmla_qqq"))
1812 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1814 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1815 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1816 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
1817 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1818 (const_string "neon_mla_qqq_8_16")
1819 (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
1822 (define_insn "neon_vmlal<mode>"
1823 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1824 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
1825 (match_operand:VW 2 "s_register_operand" "w")
1826 (match_operand:VW 3 "s_register_operand" "w")
1827 (match_operand:SI 4 "immediate_operand" "i")]
1830 "vmlal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
1831 [(set (attr "neon_type")
1832 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1833 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1834 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
1837 (define_insn "neon_vmls<mode>"
1838 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1839 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
1840 (match_operand:VDQW 2 "s_register_operand" "w")
1841 (match_operand:VDQW 3 "s_register_operand" "w")
1842 (match_operand:SI 4 "immediate_operand" "i")]
1845 "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
1846 [(set (attr "neon_type")
1847 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1848 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1849 (const_string "neon_fp_vmla_ddd")
1850 (const_string "neon_fp_vmla_qqq"))
1851 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1853 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1854 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1855 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
1857 (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1858 (const_string "neon_mla_qqq_8_16")
1859 (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
1862 (define_insn "neon_vmlsl<mode>"
1863 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1864 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
1865 (match_operand:VW 2 "s_register_operand" "w")
1866 (match_operand:VW 3 "s_register_operand" "w")
1867 (match_operand:SI 4 "immediate_operand" "i")]
1870 "vmlsl.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
1871 [(set (attr "neon_type")
1872 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1873 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1874 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
1877 (define_insn "neon_vqdmulh<mode>"
1878 [(set (match_operand:VMDQI 0 "s_register_operand" "=w")
1879 (unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "w")
1880 (match_operand:VMDQI 2 "s_register_operand" "w")
1881 (match_operand:SI 3 "immediate_operand" "i")]
1884 "vq%O3dmulh.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1885 [(set (attr "neon_type")
1886 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1887 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1888 (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
1889 (const_string "neon_mul_qqq_8_16_32_ddd_32"))
1890 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1891 (const_string "neon_mul_qqq_8_16_32_ddd_32")
1892 (const_string "neon_mul_qqq_8_16_32_ddd_32"))))]
1895 (define_insn "neon_vqdmlal<mode>"
1896 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1897 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
1898 (match_operand:VMDI 2 "s_register_operand" "w")
1899 (match_operand:VMDI 3 "s_register_operand" "w")
1900 (match_operand:SI 4 "immediate_operand" "i")]
1903 "vqdmlal.<V_s_elem>\t%q0, %P2, %P3"
1904 [(set (attr "neon_type")
1905 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1906 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1907 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
1910 (define_insn "neon_vqdmlsl<mode>"
1911 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1912 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
1913 (match_operand:VMDI 2 "s_register_operand" "w")
1914 (match_operand:VMDI 3 "s_register_operand" "w")
1915 (match_operand:SI 4 "immediate_operand" "i")]
1918 "vqdmlsl.<V_s_elem>\t%q0, %P2, %P3"
1919 [(set (attr "neon_type")
1920 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1921 (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
1922 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
1925 (define_insn "neon_vmull<mode>"
1926 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1927 (unspec:<V_widen> [(match_operand:VW 1 "s_register_operand" "w")
1928 (match_operand:VW 2 "s_register_operand" "w")
1929 (match_operand:SI 3 "immediate_operand" "i")]
1932 "vmull.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
1933 [(set (attr "neon_type")
1934 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1935 (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
1936 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
1939 (define_insn "neon_vqdmull<mode>"
1940 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1941 (unspec:<V_widen> [(match_operand:VMDI 1 "s_register_operand" "w")
1942 (match_operand:VMDI 2 "s_register_operand" "w")
1943 (match_operand:SI 3 "immediate_operand" "i")]
1946 "vqdmull.<V_s_elem>\t%q0, %P1, %P2"
1947 [(set (attr "neon_type")
1948 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
1949 (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
1950 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
1953 (define_insn "neon_vsub<mode>"
1954 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
1955 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
1956 (match_operand:VDQX 2 "s_register_operand" "w")
1957 (match_operand:SI 3 "immediate_operand" "i")]
1960 "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1961 [(set (attr "neon_type")
1962 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1963 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1964 (const_string "neon_fp_vadd_ddd_vabs_dd")
1965 (const_string "neon_fp_vadd_qqq_vabs_qq"))
1966 (const_string "neon_int_2")))]
1969 (define_insn "neon_vsubl<mode>"
1970 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1971 (unspec:<V_widen> [(match_operand:VDI 1 "s_register_operand" "w")
1972 (match_operand:VDI 2 "s_register_operand" "w")
1973 (match_operand:SI 3 "immediate_operand" "i")]
1976 "vsubl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
1977 [(set_attr "neon_type" "neon_int_2")]
1980 (define_insn "neon_vsubw<mode>"
1981 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1982 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "w")
1983 (match_operand:VDI 2 "s_register_operand" "w")
1984 (match_operand:SI 3 "immediate_operand" "i")]
1987 "vsubw.%T3%#<V_sz_elem>\t%q0, %q1, %P2"
1988 [(set_attr "neon_type" "neon_int_2")]
1991 (define_insn "neon_vqsub<mode>"
1992 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
1993 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
1994 (match_operand:VDQIX 2 "s_register_operand" "w")
1995 (match_operand:SI 3 "immediate_operand" "i")]
1998 "vqsub.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1999 [(set_attr "neon_type" "neon_int_5")]
2002 (define_insn "neon_vhsub<mode>"
2003 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2004 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2005 (match_operand:VDQIW 2 "s_register_operand" "w")
2006 (match_operand:SI 3 "immediate_operand" "i")]
2009 "vhsub.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2010 [(set_attr "neon_type" "neon_int_5")]
2013 (define_insn "neon_vsubhn<mode>"
2014 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
2015 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
2016 (match_operand:VN 2 "s_register_operand" "w")
2017 (match_operand:SI 3 "immediate_operand" "i")]
2020 "v%O3subhn.<V_if_elem>\t%P0, %q1, %q2"
2021 [(set_attr "neon_type" "neon_int_4")]
2024 (define_insn "neon_vceq<mode>"
2025 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
2026 (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
2027 (match_operand:VDQW 2 "s_register_operand" "w")
2028 (match_operand:SI 3 "immediate_operand" "i")]
2031 "vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2032 [(set (attr "neon_type")
2033 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2034 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2035 (const_string "neon_fp_vadd_ddd_vabs_dd")
2036 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2037 (const_string "neon_int_5")))]
2040 (define_insn "neon_vcge<mode>"
2041 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
2042 (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
2043 (match_operand:VDQW 2 "s_register_operand" "w")
2044 (match_operand:SI 3 "immediate_operand" "i")]
2047 "vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2048 [(set (attr "neon_type")
2049 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2050 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2051 (const_string "neon_fp_vadd_ddd_vabs_dd")
2052 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2053 (const_string "neon_int_5")))]
2056 (define_insn "neon_vcgt<mode>"
2057 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
2058 (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w")
2059 (match_operand:VDQW 2 "s_register_operand" "w")
2060 (match_operand:SI 3 "immediate_operand" "i")]
2063 "vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2064 [(set (attr "neon_type")
2065 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2066 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2067 (const_string "neon_fp_vadd_ddd_vabs_dd")
2068 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2069 (const_string "neon_int_5")))]
2072 (define_insn "neon_vcage<mode>"
2073 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
2074 (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
2075 (match_operand:VCVTF 2 "s_register_operand" "w")
2076 (match_operand:SI 3 "immediate_operand" "i")]
2079 "vacge.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2080 [(set (attr "neon_type")
2081 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2082 (const_string "neon_fp_vadd_ddd_vabs_dd")
2083 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2086 (define_insn "neon_vcagt<mode>"
2087 [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
2088 (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
2089 (match_operand:VCVTF 2 "s_register_operand" "w")
2090 (match_operand:SI 3 "immediate_operand" "i")]
2093 "vacgt.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2094 [(set (attr "neon_type")
2095 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2096 (const_string "neon_fp_vadd_ddd_vabs_dd")
2097 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2100 (define_insn "neon_vtst<mode>"
2101 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2102 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2103 (match_operand:VDQIW 2 "s_register_operand" "w")
2104 (match_operand:SI 3 "immediate_operand" "i")]
2107 "vtst.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2108 [(set_attr "neon_type" "neon_int_4")]
2111 (define_insn "neon_vabd<mode>"
2112 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
2113 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
2114 (match_operand:VDQW 2 "s_register_operand" "w")
2115 (match_operand:SI 3 "immediate_operand" "i")]
2118 "vabd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2119 [(set (attr "neon_type")
2120 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2121 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2122 (const_string "neon_fp_vadd_ddd_vabs_dd")
2123 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2124 (const_string "neon_int_5")))]
2127 (define_insn "neon_vabdl<mode>"
2128 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
2129 (unspec:<V_widen> [(match_operand:VW 1 "s_register_operand" "w")
2130 (match_operand:VW 2 "s_register_operand" "w")
2131 (match_operand:SI 3 "immediate_operand" "i")]
2134 "vabdl.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
2135 [(set_attr "neon_type" "neon_int_5")]
2138 (define_insn "neon_vaba<mode>"
2139 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2140 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0")
2141 (match_operand:VDQIW 2 "s_register_operand" "w")
2142 (match_operand:VDQIW 3 "s_register_operand" "w")
2143 (match_operand:SI 4 "immediate_operand" "i")]
2146 "vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
2147 [(set (attr "neon_type")
2148 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2149 (const_string "neon_vaba") (const_string "neon_vaba_qqq")))]
2152 (define_insn "neon_vabal<mode>"
2153 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
2154 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
2155 (match_operand:VW 2 "s_register_operand" "w")
2156 (match_operand:VW 3 "s_register_operand" "w")
2157 (match_operand:SI 4 "immediate_operand" "i")]
2160 "vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
2161 [(set_attr "neon_type" "neon_vaba")]
2164 (define_insn "neon_vmax<mode>"
2165 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
2166 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
2167 (match_operand:VDQW 2 "s_register_operand" "w")
2168 (match_operand:SI 3 "immediate_operand" "i")]
2171 "vmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2172 [(set (attr "neon_type")
2173 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2174 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2175 (const_string "neon_fp_vadd_ddd_vabs_dd")
2176 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2177 (const_string "neon_int_5")))]
2180 (define_insn "neon_vmin<mode>"
2181 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
2182 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
2183 (match_operand:VDQW 2 "s_register_operand" "w")
2184 (match_operand:SI 3 "immediate_operand" "i")]
2187 "vmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2188 [(set (attr "neon_type")
2189 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2190 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2191 (const_string "neon_fp_vadd_ddd_vabs_dd")
2192 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2193 (const_string "neon_int_5")))]
2196 (define_expand "neon_vpadd<mode>"
2197 [(match_operand:VD 0 "s_register_operand" "=w")
2198 (match_operand:VD 1 "s_register_operand" "w")
2199 (match_operand:VD 2 "s_register_operand" "w")
2200 (match_operand:SI 3 "immediate_operand" "i")]
2203 emit_insn (gen_neon_vpadd_internal<mode> (operands[0], operands[1],
2208 (define_insn "neon_vpaddl<mode>"
2209 [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2210 (unspec:<V_double_width> [(match_operand:VDQIW 1 "s_register_operand" "w")
2211 (match_operand:SI 2 "immediate_operand" "i")]
2214 "vpaddl.%T2%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
2215 ;; Assume this schedules like vaddl.
2216 [(set_attr "neon_type" "neon_int_3")]
2219 (define_insn "neon_vpadal<mode>"
2220 [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2221 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2222 (match_operand:VDQIW 2 "s_register_operand" "w")
2223 (match_operand:SI 3 "immediate_operand" "i")]
2226 "vpadal.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
2227 ;; Assume this schedules like vpadd.
2228 [(set_attr "neon_type" "neon_int_1")]
2231 (define_insn "neon_vpmax<mode>"
2232 [(set (match_operand:VD 0 "s_register_operand" "=w")
2233 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
2234 (match_operand:VD 2 "s_register_operand" "w")
2235 (match_operand:SI 3 "immediate_operand" "i")]
2238 "vpmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2239 ;; Assume this schedules like vmax.
2240 [(set (attr "neon_type")
2241 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2242 (const_string "neon_fp_vadd_ddd_vabs_dd")
2243 (const_string "neon_int_5")))]
2246 (define_insn "neon_vpmin<mode>"
2247 [(set (match_operand:VD 0 "s_register_operand" "=w")
2248 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
2249 (match_operand:VD 2 "s_register_operand" "w")
2250 (match_operand:SI 3 "immediate_operand" "i")]
2253 "vpmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2254 ;; Assume this schedules like vmin.
2255 [(set (attr "neon_type")
2256 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2257 (const_string "neon_fp_vadd_ddd_vabs_dd")
2258 (const_string "neon_int_5")))]
2261 (define_insn "neon_vrecps<mode>"
2262 [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
2263 (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
2264 (match_operand:VCVTF 2 "s_register_operand" "w")
2265 (match_operand:SI 3 "immediate_operand" "i")]
2268 "vrecps.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2269 [(set (attr "neon_type")
2270 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2271 (const_string "neon_fp_vrecps_vrsqrts_ddd")
2272 (const_string "neon_fp_vrecps_vrsqrts_qqq")))]
2275 (define_insn "neon_vrsqrts<mode>"
2276 [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
2277 (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
2278 (match_operand:VCVTF 2 "s_register_operand" "w")
2279 (match_operand:SI 3 "immediate_operand" "i")]
2282 "vrsqrts.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
2283 [(set (attr "neon_type")
2284 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2285 (const_string "neon_fp_vrecps_vrsqrts_ddd")
2286 (const_string "neon_fp_vrecps_vrsqrts_qqq")))]
2289 (define_insn "neon_vabs<mode>"
2290 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
2291 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
2292 (match_operand:SI 2 "immediate_operand" "i")]
2295 "vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
2296 [(set (attr "neon_type")
2297 (if_then_else (ior (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2298 (ne (symbol_ref "<Is_float_mode>") (const_int 0)))
2300 (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2301 (const_string "neon_fp_vadd_ddd_vabs_dd")
2302 (const_string "neon_fp_vadd_qqq_vabs_qq"))
2303 (const_string "neon_vqneg_vqabs")))]
2306 (define_insn "neon_vqabs<mode>"
2307 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2308 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2309 (match_operand:SI 2 "immediate_operand" "i")]
2312 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
2313 [(set_attr "neon_type" "neon_vqneg_vqabs")]
2316 (define_expand "neon_vneg<mode>"
2317 [(match_operand:VDQW 0 "s_register_operand" "")
2318 (match_operand:VDQW 1 "s_register_operand" "")
2319 (match_operand:SI 2 "immediate_operand" "")]
2322 emit_insn (gen_neg<mode>2 (operands[0], operands[1]));
2326 (define_insn "neon_vqneg<mode>"
2327 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2328 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2329 (match_operand:SI 2 "immediate_operand" "i")]
2332 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
2333 [(set_attr "neon_type" "neon_vqneg_vqabs")]
2336 (define_insn "neon_vcls<mode>"
2337 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2338 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2339 (match_operand:SI 2 "immediate_operand" "i")]
2342 "vcls.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
2343 [(set_attr "neon_type" "neon_int_1")]
2346 (define_insn "neon_vclz<mode>"
2347 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
2348 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
2349 (match_operand:SI 2 "immediate_operand" "i")]
2352 "vclz.<V_if_elem>\t%<V_reg>0, %<V_reg>1"
2353 [(set_attr "neon_type" "neon_int_1")]
2356 (define_insn "neon_vcnt<mode>"
2357 [(set (match_operand:VE 0 "s_register_operand" "=w")
2358 (unspec:VE [(match_operand:VE 1 "s_register_operand" "w")
2359 (match_operand:SI 2 "immediate_operand" "i")]
2362 "vcnt.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
2363 [(set_attr "neon_type" "neon_int_1")]
2366 (define_insn "neon_vrecpe<mode>"
2367 [(set (match_operand:V32 0 "s_register_operand" "=w")
2368 (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")
2369 (match_operand:SI 2 "immediate_operand" "i")]
2372 "vrecpe.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
2373 [(set (attr "neon_type")
2374 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2375 (const_string "neon_fp_vadd_ddd_vabs_dd")
2376 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2379 (define_insn "neon_vrsqrte<mode>"
2380 [(set (match_operand:V32 0 "s_register_operand" "=w")
2381 (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")
2382 (match_operand:SI 2 "immediate_operand" "i")]
2385 "vrsqrte.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
2386 [(set (attr "neon_type")
2387 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2388 (const_string "neon_fp_vadd_ddd_vabs_dd")
2389 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2392 (define_expand "neon_vmvn<mode>"
2393 [(match_operand:VDQIW 0 "s_register_operand" "")
2394 (match_operand:VDQIW 1 "s_register_operand" "")
2395 (match_operand:SI 2 "immediate_operand" "")]
2398 emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[1]));
2402 (define_insn "neon_vget_lane<mode>_sext_internal"
2403 [(set (match_operand:SI 0 "s_register_operand" "=r")
2405 (vec_select:<V_elem>
2406 (match_operand:VD 1 "s_register_operand" "w")
2407 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
2410 if (BYTES_BIG_ENDIAN)
2412 int elt = INTVAL (operands[2]);
2413 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
2414 operands[2] = GEN_INT (elt);
2416 return "vmov%?.s<V_sz_elem>\t%0, %P1[%c2]";
2418 [(set_attr "predicable" "yes")
2419 (set_attr "neon_type" "neon_bp_simple")]
2422 (define_insn "neon_vget_lane<mode>_zext_internal"
2423 [(set (match_operand:SI 0 "s_register_operand" "=r")
2425 (vec_select:<V_elem>
2426 (match_operand:VD 1 "s_register_operand" "w")
2427 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
2430 if (BYTES_BIG_ENDIAN)
2432 int elt = INTVAL (operands[2]);
2433 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
2434 operands[2] = GEN_INT (elt);
2436 return "vmov%?.u<V_sz_elem>\t%0, %P1[%c2]";
2438 [(set_attr "predicable" "yes")
2439 (set_attr "neon_type" "neon_bp_simple")]
2442 (define_insn "neon_vget_lane<mode>_sext_internal"
2443 [(set (match_operand:SI 0 "s_register_operand" "=r")
2445 (vec_select:<V_elem>
2446 (match_operand:VQ 1 "s_register_operand" "w")
2447 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
2451 int regno = REGNO (operands[1]);
2452 unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
2453 unsigned int elt = INTVAL (operands[2]);
2454 unsigned int elt_adj = elt % halfelts;
2456 if (BYTES_BIG_ENDIAN)
2457 elt_adj = halfelts - 1 - elt_adj;
2459 ops[0] = operands[0];
2460 ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
2461 ops[2] = GEN_INT (elt_adj);
2462 output_asm_insn ("vmov%?.s<V_sz_elem>\t%0, %P1[%c2]", ops);
2466 [(set_attr "predicable" "yes")
2467 (set_attr "neon_type" "neon_bp_simple")]
2470 (define_insn "neon_vget_lane<mode>_zext_internal"
2471 [(set (match_operand:SI 0 "s_register_operand" "=r")
2473 (vec_select:<V_elem>
2474 (match_operand:VQ 1 "s_register_operand" "w")
2475 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
2479 int regno = REGNO (operands[1]);
2480 unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
2481 unsigned int elt = INTVAL (operands[2]);
2482 unsigned int elt_adj = elt % halfelts;
2484 if (BYTES_BIG_ENDIAN)
2485 elt_adj = halfelts - 1 - elt_adj;
2487 ops[0] = operands[0];
2488 ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
2489 ops[2] = GEN_INT (elt_adj);
2490 output_asm_insn ("vmov%?.u<V_sz_elem>\t%0, %P1[%c2]", ops);
2494 [(set_attr "predicable" "yes")
2495 (set_attr "neon_type" "neon_bp_simple")]
2498 (define_expand "neon_vget_lane<mode>"
2499 [(match_operand:<V_ext> 0 "s_register_operand" "")
2500 (match_operand:VDQW 1 "s_register_operand" "")
2501 (match_operand:SI 2 "immediate_operand" "")
2502 (match_operand:SI 3 "immediate_operand" "")]
2505 HOST_WIDE_INT magic = INTVAL (operands[3]);
2508 neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode));
2510 if (BYTES_BIG_ENDIAN)
2512 /* The intrinsics are defined in terms of a model where the
2513 element ordering in memory is vldm order, whereas the generic
2514 RTL is defined in terms of a model where the element ordering
2515 in memory is array order. Convert the lane number to conform
2517 unsigned int elt = INTVAL (operands[2]);
2518 unsigned int reg_nelts
2519 = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
2520 elt ^= reg_nelts - 1;
2521 operands[2] = GEN_INT (elt);
2524 if ((magic & 3) == 3 || GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) == 32)
2525 insn = gen_vec_extract<mode> (operands[0], operands[1], operands[2]);
2528 if ((magic & 1) != 0)
2529 insn = gen_neon_vget_lane<mode>_sext_internal (operands[0], operands[1],
2532 insn = gen_neon_vget_lane<mode>_zext_internal (operands[0], operands[1],
2539 ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit
2542 (define_insn "neon_vget_lanedi"
2543 [(set (match_operand:DI 0 "s_register_operand" "=r")
2544 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
2545 (match_operand:SI 2 "immediate_operand" "i")
2546 (match_operand:SI 3 "immediate_operand" "i")]
2550 neon_lane_bounds (operands[2], 0, 1);
2551 return "vmov%?\t%Q0, %R0, %P1 @ di";
2553 [(set_attr "predicable" "yes")
2554 (set_attr "neon_type" "neon_bp_simple")]
2557 (define_insn "neon_vget_lanev2di"
2558 [(set (match_operand:DI 0 "s_register_operand" "=r")
2559 (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w")
2560 (match_operand:SI 2 "immediate_operand" "i")
2561 (match_operand:SI 3 "immediate_operand" "i")]
2566 unsigned int regno = REGNO (operands[1]);
2567 unsigned int elt = INTVAL (operands[2]);
2569 neon_lane_bounds (operands[2], 0, 2);
2571 ops[0] = operands[0];
2572 ops[1] = gen_rtx_REG (DImode, regno + 2 * elt);
2573 output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops);
2577 [(set_attr "predicable" "yes")
2578 (set_attr "neon_type" "neon_bp_simple")]
2581 (define_insn "neon_vset_lane<mode>"
2582 [(set (match_operand:VD 0 "s_register_operand" "=w")
2583 (unspec:VD [(match_operand:<V_elem> 1 "s_register_operand" "r")
2584 (match_operand:VD 2 "s_register_operand" "0")
2585 (match_operand:SI 3 "immediate_operand" "i")]
2589 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
2590 return "vmov%?.<V_sz_elem>\t%P0[%c3], %1";
2592 [(set_attr "predicable" "yes")
2593 (set_attr "neon_type" "neon_bp_simple")]
2596 ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored.
2598 (define_insn "neon_vset_lanedi"
2599 [(set (match_operand:DI 0 "s_register_operand" "=w")
2600 (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")
2601 (match_operand:DI 2 "s_register_operand" "0")
2602 (match_operand:SI 3 "immediate_operand" "i")]
2606 neon_lane_bounds (operands[3], 0, 1);
2607 return "vmov%?\t%P0, %Q1, %R1 @ di";
2609 [(set_attr "predicable" "yes")
2610 (set_attr "neon_type" "neon_bp_simple")]
2613 (define_insn "neon_vset_lane<mode>"
2614 [(set (match_operand:VQ 0 "s_register_operand" "=w")
2615 (unspec:VQ [(match_operand:<V_elem> 1 "s_register_operand" "r")
2616 (match_operand:VQ 2 "s_register_operand" "0")
2617 (match_operand:SI 3 "immediate_operand" "i")]
2622 unsigned int regno = REGNO (operands[0]);
2623 unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
2624 unsigned int elt = INTVAL (operands[3]);
2626 neon_lane_bounds (operands[3], 0, halfelts * 2);
2628 ops[0] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
2629 ops[1] = operands[1];
2630 ops[2] = GEN_INT (elt % halfelts);
2631 output_asm_insn ("vmov%?.<V_sz_elem>\t%P0[%c2], %1", ops);
2635 [(set_attr "predicable" "yes")
2636 (set_attr "neon_type" "neon_bp_simple")]
2639 (define_insn "neon_vset_lanev2di"
2640 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
2641 (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")
2642 (match_operand:V2DI 2 "s_register_operand" "0")
2643 (match_operand:SI 3 "immediate_operand" "i")]
2648 unsigned int regno = REGNO (operands[0]);
2649 unsigned int elt = INTVAL (operands[3]);
2651 neon_lane_bounds (operands[3], 0, 2);
2653 ops[0] = gen_rtx_REG (DImode, regno + 2 * elt);
2654 ops[1] = operands[1];
2655 output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops);
2659 [(set_attr "predicable" "yes")
2660 (set_attr "neon_type" "neon_bp_simple")]
2663 (define_expand "neon_vcreate<mode>"
2664 [(match_operand:VDX 0 "s_register_operand" "")
2665 (match_operand:DI 1 "general_operand" "")]
2668 rtx src = gen_lowpart (<MODE>mode, operands[1]);
2669 emit_move_insn (operands[0], src);
2673 (define_insn "neon_vdup_n<mode>"
2674 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
2675 (unspec:VDQW [(match_operand:<V_elem> 1 "s_register_operand" "r")]
2678 "vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
2679 ;; Assume this schedules like vmov.
2680 [(set_attr "predicable" "yes")
2681 (set_attr "neon_type" "neon_bp_simple")]
2684 (define_insn "neon_vdup_ndi"
2685 [(set (match_operand:DI 0 "s_register_operand" "=w")
2686 (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
2689 "vmov%?\t%P0, %Q1, %R1"
2690 [(set_attr "predicable" "yes")
2691 (set_attr "neon_type" "neon_bp_simple")]
2694 (define_insn "neon_vdup_nv2di"
2695 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
2696 (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")]
2699 "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1"
2700 [(set_attr "predicable" "yes")
2701 (set_attr "length" "8")
2702 (set_attr "neon_type" "neon_bp_simple")]
2705 (define_insn "neon_vdup_lane<mode>"
2706 [(set (match_operand:VD 0 "s_register_operand" "=w")
2707 (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
2708 (match_operand:SI 2 "immediate_operand" "i")]
2712 neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode));
2713 return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
2715 ;; Assume this schedules like vmov.
2716 [(set_attr "neon_type" "neon_bp_simple")]
2719 (define_insn "neon_vdup_lane<mode>"
2720 [(set (match_operand:VQ 0 "s_register_operand" "=w")
2721 (unspec:VQ [(match_operand:<V_HALF> 1 "s_register_operand" "w")
2722 (match_operand:SI 2 "immediate_operand" "i")]
2726 neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_HALF>mode));
2727 return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
2729 ;; Assume this schedules like vmov.
2730 [(set_attr "neon_type" "neon_bp_simple")]
2733 ; Scalar index is ignored, since only zero is valid here.
2734 (define_expand "neon_vdup_lanedi"
2735 [(set (match_operand:DI 0 "s_register_operand" "=w")
2736 (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
2737 (match_operand:SI 2 "immediate_operand" "i")]
2741 neon_lane_bounds (operands[2], 0, 1);
2742 emit_move_insn (operands[0], operands[1]);
2747 (define_insn "neon_vdup_lanev2di"
2748 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
2749 (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w")
2750 (match_operand:SI 2 "immediate_operand" "i")]
2754 neon_lane_bounds (operands[2], 0, 1);
2755 return "vmov\t%e0, %P1\;vmov\t%f0, %P1";
2757 [(set_attr "length" "8")
2758 (set_attr "neon_type" "neon_bp_simple")]
2761 ;; In this insn, operand 1 should be low, and operand 2 the high part of the
2763 ;; FIXME: A different implementation of this builtin could make it much
2764 ;; more likely that we wouldn't actually need to output anything (we could make
2765 ;; it so that the reg allocator puts things in the right places magically
2766 ;; instead). Lack of subregs for vectors makes that tricky though, I think.
2768 (define_insn "neon_vcombine<mode>"
2769 [(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w")
2770 (unspec:<V_DOUBLE> [(match_operand:VDX 1 "s_register_operand" "w")
2771 (match_operand:VDX 2 "s_register_operand" "w")]
2775 int dest = REGNO (operands[0]);
2776 int src1 = REGNO (operands[1]);
2777 int src2 = REGNO (operands[2]);
2780 if (src1 == dest && src2 == dest + 2)
2782 else if (src2 == dest && src1 == dest + 2)
2783 /* Special case of reversed high/low parts. */
2784 return "vswp\t%P1, %P2";
2786 destlo = gen_rtx_REG (<MODE>mode, dest);
2788 if (!reg_overlap_mentioned_p (operands[2], destlo))
2790 /* Try to avoid unnecessary moves if part of the result is in the right
2793 output_asm_insn ("vmov\t%e0, %P1", operands);
2794 if (src2 != dest + 2)
2795 output_asm_insn ("vmov\t%f0, %P2", operands);
2799 if (src2 != dest + 2)
2800 output_asm_insn ("vmov\t%f0, %P2", operands);
2802 output_asm_insn ("vmov\t%e0, %P1", operands);
2807 ;; We set the neon_type attribute based on the vmov instructions above.
2808 [(set_attr "length" "8")
2809 (set_attr "neon_type" "neon_bp_simple")]
2812 (define_insn "neon_vget_high<mode>"
2813 [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
2814 (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
2818 int dest = REGNO (operands[0]);
2819 int src = REGNO (operands[1]);
2821 if (dest != src + 2)
2822 return "vmov\t%P0, %f1";
2826 [(set_attr "neon_type" "neon_bp_simple")]
2829 (define_insn "neon_vget_low<mode>"
2830 [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
2831 (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
2835 int dest = REGNO (operands[0]);
2836 int src = REGNO (operands[1]);
2839 return "vmov\t%P0, %e1";
2843 [(set_attr "neon_type" "neon_bp_simple")]
2846 (define_insn "neon_vcvt<mode>"
2847 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
2848 (unspec:<V_CVTTO> [(match_operand:VCVTF 1 "s_register_operand" "w")
2849 (match_operand:SI 2 "immediate_operand" "i")]
2852 "vcvt.%T2%#32.f32\t%<V_reg>0, %<V_reg>1"
2853 [(set (attr "neon_type")
2854 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2855 (const_string "neon_fp_vadd_ddd_vabs_dd")
2856 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2859 (define_insn "neon_vcvt<mode>"
2860 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
2861 (unspec:<V_CVTTO> [(match_operand:VCVTI 1 "s_register_operand" "w")
2862 (match_operand:SI 2 "immediate_operand" "i")]
2865 "vcvt.f32.%T2%#32\t%<V_reg>0, %<V_reg>1"
2866 [(set (attr "neon_type")
2867 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2868 (const_string "neon_fp_vadd_ddd_vabs_dd")
2869 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2872 (define_insn "neon_vcvt_n<mode>"
2873 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
2874 (unspec:<V_CVTTO> [(match_operand:VCVTF 1 "s_register_operand" "w")
2875 (match_operand:SI 2 "immediate_operand" "i")
2876 (match_operand:SI 3 "immediate_operand" "i")]
2880 neon_const_bounds (operands[2], 1, 33);
2881 return "vcvt.%T3%#32.f32\t%<V_reg>0, %<V_reg>1, %2";
2883 [(set (attr "neon_type")
2884 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2885 (const_string "neon_fp_vadd_ddd_vabs_dd")
2886 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2889 (define_insn "neon_vcvt_n<mode>"
2890 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
2891 (unspec:<V_CVTTO> [(match_operand:VCVTI 1 "s_register_operand" "w")
2892 (match_operand:SI 2 "immediate_operand" "i")
2893 (match_operand:SI 3 "immediate_operand" "i")]
2897 neon_const_bounds (operands[2], 1, 33);
2898 return "vcvt.f32.%T3%#32\t%<V_reg>0, %<V_reg>1, %2";
2900 [(set (attr "neon_type")
2901 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
2902 (const_string "neon_fp_vadd_ddd_vabs_dd")
2903 (const_string "neon_fp_vadd_qqq_vabs_qq")))]
2906 (define_insn "neon_vmovn<mode>"
2907 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
2908 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
2909 (match_operand:SI 2 "immediate_operand" "i")]
2912 "vmovn.<V_if_elem>\t%P0, %q1"
2913 [(set_attr "neon_type" "neon_bp_simple")]
2916 (define_insn "neon_vqmovn<mode>"
2917 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
2918 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
2919 (match_operand:SI 2 "immediate_operand" "i")]
2922 "vqmovn.%T2%#<V_sz_elem>\t%P0, %q1"
2923 [(set_attr "neon_type" "neon_shift_2")]
2926 (define_insn "neon_vqmovun<mode>"
2927 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
2928 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
2929 (match_operand:SI 2 "immediate_operand" "i")]
2932 "vqmovun.<V_s_elem>\t%P0, %q1"
2933 [(set_attr "neon_type" "neon_shift_2")]
2936 (define_insn "neon_vmovl<mode>"
2937 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
2938 (unspec:<V_widen> [(match_operand:VW 1 "s_register_operand" "w")
2939 (match_operand:SI 2 "immediate_operand" "i")]
2942 "vmovl.%T2%#<V_sz_elem>\t%q0, %P1"
2943 [(set_attr "neon_type" "neon_shift_1")]
2946 (define_insn "neon_vmul_lane<mode>"
2947 [(set (match_operand:VMD 0 "s_register_operand" "=w")
2948 (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "w")
2949 (match_operand:VMD 2 "s_register_operand"
2950 "<scalar_mul_constraint>")
2951 (match_operand:SI 3 "immediate_operand" "i")
2952 (match_operand:SI 4 "immediate_operand" "i")]
2956 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
2957 return "vmul.<V_if_elem>\t%P0, %P1, %P2[%c3]";
2959 [(set (attr "neon_type")
2960 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2961 (const_string "neon_fp_vmul_ddd")
2962 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
2963 (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
2964 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))))]
2967 (define_insn "neon_vmul_lane<mode>"
2968 [(set (match_operand:VMQ 0 "s_register_operand" "=w")
2969 (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "w")
2970 (match_operand:<V_HALF> 2 "s_register_operand"
2971 "<scalar_mul_constraint>")
2972 (match_operand:SI 3 "immediate_operand" "i")
2973 (match_operand:SI 4 "immediate_operand" "i")]
2977 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<V_HALF>mode));
2978 return "vmul.<V_if_elem>\t%q0, %q1, %P2[%c3]";
2980 [(set (attr "neon_type")
2981 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
2982 (const_string "neon_fp_vmul_qqd")
2983 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
2984 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
2985 (const_string "neon_mul_qqd_32_scalar"))))]
2988 (define_insn "neon_vmull_lane<mode>"
2989 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
2990 (unspec:<V_widen> [(match_operand:VMDI 1 "s_register_operand" "w")
2991 (match_operand:VMDI 2 "s_register_operand"
2992 "<scalar_mul_constraint>")
2993 (match_operand:SI 3 "immediate_operand" "i")
2994 (match_operand:SI 4 "immediate_operand" "i")]
2995 UNSPEC_VMULL_LANE))]
2998 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
2999 return "vmull.%T4%#<V_sz_elem>\t%q0, %P1, %P2[%c3]";
3001 [(set (attr "neon_type")
3002 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3003 (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
3004 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
3007 (define_insn "neon_vqdmull_lane<mode>"
3008 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3009 (unspec:<V_widen> [(match_operand:VMDI 1 "s_register_operand" "w")
3010 (match_operand:VMDI 2 "s_register_operand"
3011 "<scalar_mul_constraint>")
3012 (match_operand:SI 3 "immediate_operand" "i")
3013 (match_operand:SI 4 "immediate_operand" "i")]
3014 UNSPEC_VQDMULL_LANE))]
3017 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
3018 return "vqdmull.<V_s_elem>\t%q0, %P1, %P2[%c3]";
3020 [(set (attr "neon_type")
3021 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3022 (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
3023 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
3026 (define_insn "neon_vqdmulh_lane<mode>"
3027 [(set (match_operand:VMQI 0 "s_register_operand" "=w")
3028 (unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "w")
3029 (match_operand:<V_HALF> 2 "s_register_operand"
3030 "<scalar_mul_constraint>")
3031 (match_operand:SI 3 "immediate_operand" "i")
3032 (match_operand:SI 4 "immediate_operand" "i")]
3033 UNSPEC_VQDMULH_LANE))]
3036 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
3037 return "vq%O4dmulh.%T4%#<V_sz_elem>\t%q0, %q1, %P2[%c3]";
3039 [(set (attr "neon_type")
3040 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3041 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
3042 (const_string "neon_mul_qqd_32_scalar")))]
3045 (define_insn "neon_vqdmulh_lane<mode>"
3046 [(set (match_operand:VMDI 0 "s_register_operand" "=w")
3047 (unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "w")
3048 (match_operand:VMDI 2 "s_register_operand"
3049 "<scalar_mul_constraint>")
3050 (match_operand:SI 3 "immediate_operand" "i")
3051 (match_operand:SI 4 "immediate_operand" "i")]
3052 UNSPEC_VQDMULH_LANE))]
3055 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
3056 return "vq%O4dmulh.%T4%#<V_sz_elem>\t%P0, %P1, %P2[%c3]";
3058 [(set (attr "neon_type")
3059 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3060 (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
3061 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
3064 (define_insn "neon_vmla_lane<mode>"
3065 [(set (match_operand:VMD 0 "s_register_operand" "=w")
3066 (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0")
3067 (match_operand:VMD 2 "s_register_operand" "w")
3068 (match_operand:VMD 3 "s_register_operand"
3069 "<scalar_mul_constraint>")
3070 (match_operand:SI 4 "immediate_operand" "i")
3071 (match_operand:SI 5 "immediate_operand" "i")]
3075 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3076 return "vmla.<V_if_elem>\t%P0, %P2, %P3[%c4]";
3078 [(set (attr "neon_type")
3079 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
3080 (const_string "neon_fp_vmla_ddd_scalar")
3081 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3082 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3083 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))))]
3086 (define_insn "neon_vmla_lane<mode>"
3087 [(set (match_operand:VMQ 0 "s_register_operand" "=w")
3088 (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "0")
3089 (match_operand:VMQ 2 "s_register_operand" "w")
3090 (match_operand:<V_HALF> 3 "s_register_operand"
3091 "<scalar_mul_constraint>")
3092 (match_operand:SI 4 "immediate_operand" "i")
3093 (match_operand:SI 5 "immediate_operand" "i")]
3097 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3098 return "vmla.<V_if_elem>\t%q0, %q2, %P3[%c4]";
3100 [(set (attr "neon_type")
3101 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
3102 (const_string "neon_fp_vmla_qqq_scalar")
3103 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3104 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
3105 (const_string "neon_mla_qqq_32_qqd_32_scalar"))))]
3108 (define_insn "neon_vmlal_lane<mode>"
3109 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3110 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
3111 (match_operand:VMDI 2 "s_register_operand" "w")
3112 (match_operand:VMDI 3 "s_register_operand"
3113 "<scalar_mul_constraint>")
3114 (match_operand:SI 4 "immediate_operand" "i")
3115 (match_operand:SI 5 "immediate_operand" "i")]
3116 UNSPEC_VMLAL_LANE))]
3119 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3120 return "vmlal.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
3122 [(set (attr "neon_type")
3123 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3124 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3125 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
3128 (define_insn "neon_vqdmlal_lane<mode>"
3129 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3130 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
3131 (match_operand:VMDI 2 "s_register_operand" "w")
3132 (match_operand:VMDI 3 "s_register_operand"
3133 "<scalar_mul_constraint>")
3134 (match_operand:SI 4 "immediate_operand" "i")
3135 (match_operand:SI 5 "immediate_operand" "i")]
3136 UNSPEC_VQDMLAL_LANE))]
3139 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3140 return "vqdmlal.<V_s_elem>\t%q0, %P2, %P3[%c4]";
3142 [(set (attr "neon_type")
3143 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3144 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3145 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
3148 (define_insn "neon_vmls_lane<mode>"
3149 [(set (match_operand:VMD 0 "s_register_operand" "=w")
3150 (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0")
3151 (match_operand:VMD 2 "s_register_operand" "w")
3152 (match_operand:VMD 3 "s_register_operand"
3153 "<scalar_mul_constraint>")
3154 (match_operand:SI 4 "immediate_operand" "i")
3155 (match_operand:SI 5 "immediate_operand" "i")]
3159 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3160 return "vmls.<V_if_elem>\t%P0, %P2, %P3[%c4]";
3162 [(set (attr "neon_type")
3163 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
3164 (const_string "neon_fp_vmla_ddd_scalar")
3165 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3166 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3167 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))))]
3170 (define_insn "neon_vmls_lane<mode>"
3171 [(set (match_operand:VMQ 0 "s_register_operand" "=w")
3172 (unspec:VMQ [(match_operand:VMQ 1 "s_register_operand" "0")
3173 (match_operand:VMQ 2 "s_register_operand" "w")
3174 (match_operand:<V_HALF> 3 "s_register_operand"
3175 "<scalar_mul_constraint>")
3176 (match_operand:SI 4 "immediate_operand" "i")
3177 (match_operand:SI 5 "immediate_operand" "i")]
3181 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3182 return "vmls.<V_if_elem>\t%q0, %q2, %P3[%c4]";
3184 [(set (attr "neon_type")
3185 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
3186 (const_string "neon_fp_vmla_qqq_scalar")
3187 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3188 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
3189 (const_string "neon_mla_qqq_32_qqd_32_scalar"))))]
3192 (define_insn "neon_vmlsl_lane<mode>"
3193 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3194 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
3195 (match_operand:VMDI 2 "s_register_operand" "w")
3196 (match_operand:VMDI 3 "s_register_operand"
3197 "<scalar_mul_constraint>")
3198 (match_operand:SI 4 "immediate_operand" "i")
3199 (match_operand:SI 5 "immediate_operand" "i")]
3200 UNSPEC_VMLSL_LANE))]
3203 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3204 return "vmlsl.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
3206 [(set (attr "neon_type")
3207 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3208 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3209 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
3212 (define_insn "neon_vqdmlsl_lane<mode>"
3213 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3214 (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
3215 (match_operand:VMDI 2 "s_register_operand" "w")
3216 (match_operand:VMDI 3 "s_register_operand"
3217 "<scalar_mul_constraint>")
3218 (match_operand:SI 4 "immediate_operand" "i")
3219 (match_operand:SI 5 "immediate_operand" "i")]
3220 UNSPEC_VQDMLSL_LANE))]
3223 neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (<MODE>mode));
3224 return "vqdmlsl.<V_s_elem>\t%q0, %P2, %P3[%c4]";
3226 [(set (attr "neon_type")
3227 (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
3228 (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
3229 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
3232 ; FIXME: For the "_n" multiply/multiply-accumulate insns, we copy a value in a
3233 ; core register into a temp register, then use a scalar taken from that. This
3234 ; isn't an optimal solution if e.g. the scalar has just been read from memory
3235 ; or extracted from another vector. The latter case it's currently better to
3236 ; use the "_lane" variant, and the former case can probably be implemented
3237 ; using vld1_lane, but that hasn't been done yet.
3239 (define_expand "neon_vmul_n<mode>"
3240 [(match_operand:VMD 0 "s_register_operand" "")
3241 (match_operand:VMD 1 "s_register_operand" "")
3242 (match_operand:<V_elem> 2 "s_register_operand" "")
3243 (match_operand:SI 3 "immediate_operand" "")]
3246 rtx tmp = gen_reg_rtx (<MODE>mode);
3247 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[2], tmp, const0_rtx));
3248 emit_insn (gen_neon_vmul_lane<mode> (operands[0], operands[1], tmp,
3249 const0_rtx, const0_rtx));
3253 (define_expand "neon_vmul_n<mode>"
3254 [(match_operand:VMQ 0 "s_register_operand" "")
3255 (match_operand:VMQ 1 "s_register_operand" "")
3256 (match_operand:<V_elem> 2 "s_register_operand" "")
3257 (match_operand:SI 3 "immediate_operand" "")]
3260 rtx tmp = gen_reg_rtx (<V_HALF>mode);
3261 emit_insn (gen_neon_vset_lane<V_half> (tmp, operands[2], tmp, const0_rtx));
3262 emit_insn (gen_neon_vmul_lane<mode> (operands[0], operands[1], tmp,
3263 const0_rtx, const0_rtx));
3267 (define_expand "neon_vmull_n<mode>"
3268 [(match_operand:<V_widen> 0 "s_register_operand" "")
3269 (match_operand:VMDI 1 "s_register_operand" "")
3270 (match_operand:<V_elem> 2 "s_register_operand" "")
3271 (match_operand:SI 3 "immediate_operand" "")]
3274 rtx tmp = gen_reg_rtx (<MODE>mode);
3275 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[2], tmp, const0_rtx));
3276 emit_insn (gen_neon_vmull_lane<mode> (operands[0], operands[1], tmp,
3277 const0_rtx, operands[3]));
3281 (define_expand "neon_vqdmull_n<mode>"
3282 [(match_operand:<V_widen> 0 "s_register_operand" "")
3283 (match_operand:VMDI 1 "s_register_operand" "")
3284 (match_operand:<V_elem> 2 "s_register_operand" "")
3285 (match_operand:SI 3 "immediate_operand" "")]
3288 rtx tmp = gen_reg_rtx (<MODE>mode);
3289 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[2], tmp, const0_rtx));
3290 emit_insn (gen_neon_vqdmull_lane<mode> (operands[0], operands[1], tmp,
3291 const0_rtx, const0_rtx));
3295 (define_expand "neon_vqdmulh_n<mode>"
3296 [(match_operand:VMDI 0 "s_register_operand" "")
3297 (match_operand:VMDI 1 "s_register_operand" "")
3298 (match_operand:<V_elem> 2 "s_register_operand" "")
3299 (match_operand:SI 3 "immediate_operand" "")]
3302 rtx tmp = gen_reg_rtx (<MODE>mode);
3303 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[2], tmp, const0_rtx));
3304 emit_insn (gen_neon_vqdmulh_lane<mode> (operands[0], operands[1], tmp,
3305 const0_rtx, operands[3]));
3309 (define_expand "neon_vqdmulh_n<mode>"
3310 [(match_operand:VMQI 0 "s_register_operand" "")
3311 (match_operand:VMQI 1 "s_register_operand" "")
3312 (match_operand:<V_elem> 2 "s_register_operand" "")
3313 (match_operand:SI 3 "immediate_operand" "")]
3316 rtx tmp = gen_reg_rtx (<V_HALF>mode);
3317 emit_insn (gen_neon_vset_lane<V_half> (tmp, operands[2], tmp, const0_rtx));
3318 emit_insn (gen_neon_vqdmulh_lane<mode> (operands[0], operands[1], tmp,
3319 const0_rtx, operands[3]));
3323 (define_expand "neon_vmla_n<mode>"
3324 [(match_operand:VMD 0 "s_register_operand" "")
3325 (match_operand:VMD 1 "s_register_operand" "")
3326 (match_operand:VMD 2 "s_register_operand" "")
3327 (match_operand:<V_elem> 3 "s_register_operand" "")
3328 (match_operand:SI 4 "immediate_operand" "")]
3331 rtx tmp = gen_reg_rtx (<MODE>mode);
3332 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3333 emit_insn (gen_neon_vmla_lane<mode> (operands[0], operands[1], operands[2],
3334 tmp, const0_rtx, operands[4]));
3338 (define_expand "neon_vmla_n<mode>"
3339 [(match_operand:VMQ 0 "s_register_operand" "")
3340 (match_operand:VMQ 1 "s_register_operand" "")
3341 (match_operand:VMQ 2 "s_register_operand" "")
3342 (match_operand:<V_elem> 3 "s_register_operand" "")
3343 (match_operand:SI 4 "immediate_operand" "")]
3346 rtx tmp = gen_reg_rtx (<V_HALF>mode);
3347 emit_insn (gen_neon_vset_lane<V_half> (tmp, operands[3], tmp, const0_rtx));
3348 emit_insn (gen_neon_vmla_lane<mode> (operands[0], operands[1], operands[2],
3349 tmp, const0_rtx, operands[4]));
3353 (define_expand "neon_vmlal_n<mode>"
3354 [(match_operand:<V_widen> 0 "s_register_operand" "")
3355 (match_operand:<V_widen> 1 "s_register_operand" "")
3356 (match_operand:VMDI 2 "s_register_operand" "")
3357 (match_operand:<V_elem> 3 "s_register_operand" "")
3358 (match_operand:SI 4 "immediate_operand" "")]
3361 rtx tmp = gen_reg_rtx (<MODE>mode);
3362 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3363 emit_insn (gen_neon_vmlal_lane<mode> (operands[0], operands[1], operands[2],
3364 tmp, const0_rtx, operands[4]));
3368 (define_expand "neon_vqdmlal_n<mode>"
3369 [(match_operand:<V_widen> 0 "s_register_operand" "")
3370 (match_operand:<V_widen> 1 "s_register_operand" "")
3371 (match_operand:VMDI 2 "s_register_operand" "")
3372 (match_operand:<V_elem> 3 "s_register_operand" "")
3373 (match_operand:SI 4 "immediate_operand" "")]
3376 rtx tmp = gen_reg_rtx (<MODE>mode);
3377 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3378 emit_insn (gen_neon_vqdmlal_lane<mode> (operands[0], operands[1], operands[2],
3379 tmp, const0_rtx, operands[4]));
3383 (define_expand "neon_vmls_n<mode>"
3384 [(match_operand:VMD 0 "s_register_operand" "")
3385 (match_operand:VMD 1 "s_register_operand" "")
3386 (match_operand:VMD 2 "s_register_operand" "")
3387 (match_operand:<V_elem> 3 "s_register_operand" "")
3388 (match_operand:SI 4 "immediate_operand" "")]
3391 rtx tmp = gen_reg_rtx (<MODE>mode);
3392 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3393 emit_insn (gen_neon_vmls_lane<mode> (operands[0], operands[1], operands[2],
3394 tmp, const0_rtx, operands[4]));
3398 (define_expand "neon_vmls_n<mode>"
3399 [(match_operand:VMQ 0 "s_register_operand" "")
3400 (match_operand:VMQ 1 "s_register_operand" "")
3401 (match_operand:VMQ 2 "s_register_operand" "")
3402 (match_operand:<V_elem> 3 "s_register_operand" "")
3403 (match_operand:SI 4 "immediate_operand" "")]
3406 rtx tmp = gen_reg_rtx (<V_HALF>mode);
3407 emit_insn (gen_neon_vset_lane<V_half> (tmp, operands[3], tmp, const0_rtx));
3408 emit_insn (gen_neon_vmls_lane<mode> (operands[0], operands[1], operands[2],
3409 tmp, const0_rtx, operands[4]));
3413 (define_expand "neon_vmlsl_n<mode>"
3414 [(match_operand:<V_widen> 0 "s_register_operand" "")
3415 (match_operand:<V_widen> 1 "s_register_operand" "")
3416 (match_operand:VMDI 2 "s_register_operand" "")
3417 (match_operand:<V_elem> 3 "s_register_operand" "")
3418 (match_operand:SI 4 "immediate_operand" "")]
3421 rtx tmp = gen_reg_rtx (<MODE>mode);
3422 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3423 emit_insn (gen_neon_vmlsl_lane<mode> (operands[0], operands[1], operands[2],
3424 tmp, const0_rtx, operands[4]));
3428 (define_expand "neon_vqdmlsl_n<mode>"
3429 [(match_operand:<V_widen> 0 "s_register_operand" "")
3430 (match_operand:<V_widen> 1 "s_register_operand" "")
3431 (match_operand:VMDI 2 "s_register_operand" "")
3432 (match_operand:<V_elem> 3 "s_register_operand" "")
3433 (match_operand:SI 4 "immediate_operand" "")]
3436 rtx tmp = gen_reg_rtx (<MODE>mode);
3437 emit_insn (gen_neon_vset_lane<mode> (tmp, operands[3], tmp, const0_rtx));
3438 emit_insn (gen_neon_vqdmlsl_lane<mode> (operands[0], operands[1], operands[2],
3439 tmp, const0_rtx, operands[4]));
3443 (define_insn "neon_vext<mode>"
3444 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
3445 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
3446 (match_operand:VDQX 2 "s_register_operand" "w")
3447 (match_operand:SI 3 "immediate_operand" "i")]
3451 neon_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
3452 return "vext.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2, %3";
3454 [(set (attr "neon_type")
3455 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3456 (const_string "neon_bp_simple")
3457 (const_string "neon_bp_2cycle")))]
3460 (define_insn "neon_vrev64<mode>"
3461 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
3462 (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "w")
3463 (match_operand:SI 2 "immediate_operand" "i")]
3466 "vrev64.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
3467 [(set_attr "neon_type" "neon_bp_simple")]
3470 (define_insn "neon_vrev32<mode>"
3471 [(set (match_operand:VX 0 "s_register_operand" "=w")
3472 (unspec:VX [(match_operand:VX 1 "s_register_operand" "w")
3473 (match_operand:SI 2 "immediate_operand" "i")]
3476 "vrev32.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
3477 [(set_attr "neon_type" "neon_bp_simple")]
3480 (define_insn "neon_vrev16<mode>"
3481 [(set (match_operand:VE 0 "s_register_operand" "=w")
3482 (unspec:VE [(match_operand:VE 1 "s_register_operand" "w")
3483 (match_operand:SI 2 "immediate_operand" "i")]
3486 "vrev16.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
3487 [(set_attr "neon_type" "neon_bp_simple")]
3490 ; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register
3491 ; allocation. For an intrinsic of form:
3492 ; rD = vbsl_* (rS, rN, rM)
3493 ; We can use any of:
3494 ; vbsl rS, rN, rM (if D = S)
3495 ; vbit rD, rN, rS (if D = M, so 1-bits in rS choose bits from rN, else rM)
3496 ; vbif rD, rM, rS (if D = N, so 0-bits in rS choose bits from rM, else rN)
3498 (define_insn "neon_vbsl<mode>_internal"
3499 [(set (match_operand:VDQX 0 "s_register_operand" "=w,w,w")
3500 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" " 0,w,w")
3501 (match_operand:VDQX 2 "s_register_operand" " w,w,0")
3502 (match_operand:VDQX 3 "s_register_operand" " w,0,w")]
3506 vbsl\t%<V_reg>0, %<V_reg>2, %<V_reg>3
3507 vbit\t%<V_reg>0, %<V_reg>2, %<V_reg>1
3508 vbif\t%<V_reg>0, %<V_reg>3, %<V_reg>1"
3509 [(set_attr "neon_type" "neon_int_1")]
3512 (define_expand "neon_vbsl<mode>"
3513 [(set (match_operand:VDQX 0 "s_register_operand" "")
3514 (unspec:VDQX [(match_operand:<V_cmp_result> 1 "s_register_operand" "")
3515 (match_operand:VDQX 2 "s_register_operand" "")
3516 (match_operand:VDQX 3 "s_register_operand" "")]
3520 /* We can't alias operands together if they have different modes. */
3521 operands[1] = gen_lowpart (<MODE>mode, operands[1]);
3524 (define_insn "neon_vshl<mode>"
3525 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3526 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3527 (match_operand:VDQIX 2 "s_register_operand" "w")
3528 (match_operand:SI 3 "immediate_operand" "i")]
3531 "v%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
3532 [(set (attr "neon_type")
3533 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3534 (const_string "neon_vshl_ddd")
3535 (const_string "neon_shift_3")))]
3538 (define_insn "neon_vqshl<mode>"
3539 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3540 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3541 (match_operand:VDQIX 2 "s_register_operand" "w")
3542 (match_operand:SI 3 "immediate_operand" "i")]
3545 "vq%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
3546 [(set (attr "neon_type")
3547 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3548 (const_string "neon_shift_2")
3549 (const_string "neon_vqshl_vrshl_vqrshl_qqq")))]
3552 (define_insn "neon_vshr_n<mode>"
3553 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3554 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3555 (match_operand:SI 2 "immediate_operand" "i")
3556 (match_operand:SI 3 "immediate_operand" "i")]
3560 neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
3561 return "v%O3shr.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
3563 [(set_attr "neon_type" "neon_shift_1")]
3566 (define_insn "neon_vshrn_n<mode>"
3567 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
3568 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
3569 (match_operand:SI 2 "immediate_operand" "i")
3570 (match_operand:SI 3 "immediate_operand" "i")]
3574 neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
3575 return "v%O3shrn.<V_if_elem>\t%P0, %q1, %2";
3577 [(set_attr "neon_type" "neon_shift_1")]
3580 (define_insn "neon_vqshrn_n<mode>"
3581 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
3582 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
3583 (match_operand:SI 2 "immediate_operand" "i")
3584 (match_operand:SI 3 "immediate_operand" "i")]
3588 neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
3589 return "vq%O3shrn.%T3%#<V_sz_elem>\t%P0, %q1, %2";
3591 [(set_attr "neon_type" "neon_shift_2")]
3594 (define_insn "neon_vqshrun_n<mode>"
3595 [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
3596 (unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")
3597 (match_operand:SI 2 "immediate_operand" "i")
3598 (match_operand:SI 3 "immediate_operand" "i")]
3602 neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
3603 return "vq%O3shrun.%T3%#<V_sz_elem>\t%P0, %q1, %2";
3605 [(set_attr "neon_type" "neon_shift_2")]
3608 (define_insn "neon_vshl_n<mode>"
3609 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3610 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3611 (match_operand:SI 2 "immediate_operand" "i")
3612 (match_operand:SI 3 "immediate_operand" "i")]
3616 neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
3617 return "vshl.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %2";
3619 [(set_attr "neon_type" "neon_shift_1")]
3622 (define_insn "neon_vqshl_n<mode>"
3623 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3624 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3625 (match_operand:SI 2 "immediate_operand" "i")
3626 (match_operand:SI 3 "immediate_operand" "i")]
3630 neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
3631 return "vqshl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
3633 [(set_attr "neon_type" "neon_shift_2")]
3636 (define_insn "neon_vqshlu_n<mode>"
3637 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3638 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "w")
3639 (match_operand:SI 2 "immediate_operand" "i")
3640 (match_operand:SI 3 "immediate_operand" "i")]
3644 neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
3645 return "vqshlu.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
3647 [(set_attr "neon_type" "neon_shift_2")]
3650 (define_insn "neon_vshll_n<mode>"
3651 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
3652 (unspec:<V_widen> [(match_operand:VW 1 "s_register_operand" "w")
3653 (match_operand:SI 2 "immediate_operand" "i")
3654 (match_operand:SI 3 "immediate_operand" "i")]
3658 /* The boundaries are: 0 < imm <= size. */
3659 neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
3660 return "vshll.%T3%#<V_sz_elem>\t%q0, %P1, %2";
3662 [(set_attr "neon_type" "neon_shift_1")]
3665 (define_insn "neon_vsra_n<mode>"
3666 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3667 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0")
3668 (match_operand:VDQIX 2 "s_register_operand" "w")
3669 (match_operand:SI 3 "immediate_operand" "i")
3670 (match_operand:SI 4 "immediate_operand" "i")]
3674 neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
3675 return "v%O4sra.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
3677 [(set_attr "neon_type" "neon_vsra_vrsra")]
3680 (define_insn "neon_vsri_n<mode>"
3681 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3682 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0")
3683 (match_operand:VDQIX 2 "s_register_operand" "w")
3684 (match_operand:SI 3 "immediate_operand" "i")]
3688 neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
3689 return "vsri.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
3691 [(set (attr "neon_type")
3692 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3693 (const_string "neon_shift_1")
3694 (const_string "neon_shift_3")))]
3697 (define_insn "neon_vsli_n<mode>"
3698 [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
3699 (unspec:VDQIX [(match_operand:VDQIX 1 "s_register_operand" "0")
3700 (match_operand:VDQIX 2 "s_register_operand" "w")
3701 (match_operand:SI 3 "immediate_operand" "i")]
3705 neon_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
3706 return "vsli.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
3708 [(set (attr "neon_type")
3709 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3710 (const_string "neon_shift_1")
3711 (const_string "neon_shift_3")))]
3714 (define_insn "neon_vtbl1v8qi"
3715 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3716 (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "w")
3717 (match_operand:V8QI 2 "s_register_operand" "w")]
3720 "vtbl.8\t%P0, {%P1}, %P2"
3721 [(set_attr "neon_type" "neon_bp_2cycle")]
3724 (define_insn "neon_vtbl2v8qi"
3725 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3726 (unspec:V8QI [(match_operand:TI 1 "s_register_operand" "w")
3727 (match_operand:V8QI 2 "s_register_operand" "w")]
3732 int tabbase = REGNO (operands[1]);
3734 ops[0] = operands[0];
3735 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3736 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3737 ops[3] = operands[2];
3738 output_asm_insn ("vtbl.8\t%P0, {%P1, %P2}, %P3", ops);
3742 [(set_attr "neon_type" "neon_bp_2cycle")]
3745 (define_insn "neon_vtbl3v8qi"
3746 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3747 (unspec:V8QI [(match_operand:EI 1 "s_register_operand" "w")
3748 (match_operand:V8QI 2 "s_register_operand" "w")]
3753 int tabbase = REGNO (operands[1]);
3755 ops[0] = operands[0];
3756 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3757 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3758 ops[3] = gen_rtx_REG (V8QImode, tabbase + 4);
3759 ops[4] = operands[2];
3760 output_asm_insn ("vtbl.8\t%P0, {%P1, %P2, %P3}, %P4", ops);
3764 [(set_attr "neon_type" "neon_bp_3cycle")]
3767 (define_insn "neon_vtbl4v8qi"
3768 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3769 (unspec:V8QI [(match_operand:OI 1 "s_register_operand" "w")
3770 (match_operand:V8QI 2 "s_register_operand" "w")]
3775 int tabbase = REGNO (operands[1]);
3777 ops[0] = operands[0];
3778 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3779 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3780 ops[3] = gen_rtx_REG (V8QImode, tabbase + 4);
3781 ops[4] = gen_rtx_REG (V8QImode, tabbase + 6);
3782 ops[5] = operands[2];
3783 output_asm_insn ("vtbl.8\t%P0, {%P1, %P2, %P3, %P4}, %P5", ops);
3787 [(set_attr "neon_type" "neon_bp_3cycle")]
3790 (define_insn "neon_vtbx1v8qi"
3791 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3792 (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0")
3793 (match_operand:V8QI 2 "s_register_operand" "w")
3794 (match_operand:V8QI 3 "s_register_operand" "w")]
3797 "vtbx.8\t%P0, {%P2}, %P3"
3798 [(set_attr "neon_type" "neon_bp_2cycle")]
3801 (define_insn "neon_vtbx2v8qi"
3802 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3803 (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0")
3804 (match_operand:TI 2 "s_register_operand" "w")
3805 (match_operand:V8QI 3 "s_register_operand" "w")]
3810 int tabbase = REGNO (operands[2]);
3812 ops[0] = operands[0];
3813 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3814 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3815 ops[3] = operands[3];
3816 output_asm_insn ("vtbx.8\t%P0, {%P1, %P2}, %P3", ops);
3820 [(set_attr "neon_type" "neon_bp_2cycle")]
3823 (define_insn "neon_vtbx3v8qi"
3824 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3825 (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0")
3826 (match_operand:EI 2 "s_register_operand" "w")
3827 (match_operand:V8QI 3 "s_register_operand" "w")]
3832 int tabbase = REGNO (operands[2]);
3834 ops[0] = operands[0];
3835 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3836 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3837 ops[3] = gen_rtx_REG (V8QImode, tabbase + 4);
3838 ops[4] = operands[3];
3839 output_asm_insn ("vtbx.8\t%P0, {%P1, %P2, %P3}, %P4", ops);
3843 [(set_attr "neon_type" "neon_bp_3cycle")]
3846 (define_insn "neon_vtbx4v8qi"
3847 [(set (match_operand:V8QI 0 "s_register_operand" "=w")
3848 (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "0")
3849 (match_operand:OI 2 "s_register_operand" "w")
3850 (match_operand:V8QI 3 "s_register_operand" "w")]
3855 int tabbase = REGNO (operands[2]);
3857 ops[0] = operands[0];
3858 ops[1] = gen_rtx_REG (V8QImode, tabbase);
3859 ops[2] = gen_rtx_REG (V8QImode, tabbase + 2);
3860 ops[3] = gen_rtx_REG (V8QImode, tabbase + 4);
3861 ops[4] = gen_rtx_REG (V8QImode, tabbase + 6);
3862 ops[5] = operands[3];
3863 output_asm_insn ("vtbx.8\t%P0, {%P1, %P2, %P3, %P4}, %P5", ops);
3867 [(set_attr "neon_type" "neon_bp_3cycle")]
3870 (define_insn "neon_vtrn<mode>_internal"
3871 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
3872 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
3874 (set (match_operand:VDQW 2 "s_register_operand" "=w")
3875 (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
3878 "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
3879 [(set (attr "neon_type")
3880 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3881 (const_string "neon_bp_simple")
3882 (const_string "neon_bp_3cycle")))]
3885 (define_expand "neon_vtrn<mode>"
3886 [(match_operand:SI 0 "s_register_operand" "r")
3887 (match_operand:VDQW 1 "s_register_operand" "w")
3888 (match_operand:VDQW 2 "s_register_operand" "w")]
3891 neon_emit_pair_result_insn (<MODE>mode, gen_neon_vtrn<mode>_internal,
3892 operands[0], operands[1], operands[2]);
3896 (define_insn "neon_vzip<mode>_internal"
3897 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
3898 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
3900 (set (match_operand:VDQW 2 "s_register_operand" "=w")
3901 (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
3904 "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
3905 [(set (attr "neon_type")
3906 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3907 (const_string "neon_bp_simple")
3908 (const_string "neon_bp_3cycle")))]
3911 (define_expand "neon_vzip<mode>"
3912 [(match_operand:SI 0 "s_register_operand" "r")
3913 (match_operand:VDQW 1 "s_register_operand" "w")
3914 (match_operand:VDQW 2 "s_register_operand" "w")]
3917 neon_emit_pair_result_insn (<MODE>mode, gen_neon_vzip<mode>_internal,
3918 operands[0], operands[1], operands[2]);
3922 (define_insn "neon_vuzp<mode>_internal"
3923 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
3924 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
3926 (set (match_operand:VDQW 2 "s_register_operand" "=w")
3927 (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
3930 "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
3931 [(set (attr "neon_type")
3932 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
3933 (const_string "neon_bp_simple")
3934 (const_string "neon_bp_3cycle")))]
3937 (define_expand "neon_vuzp<mode>"
3938 [(match_operand:SI 0 "s_register_operand" "r")
3939 (match_operand:VDQW 1 "s_register_operand" "w")
3940 (match_operand:VDQW 2 "s_register_operand" "w")]
3943 neon_emit_pair_result_insn (<MODE>mode, gen_neon_vuzp<mode>_internal,
3944 operands[0], operands[1], operands[2]);
3948 (define_expand "neon_vreinterpretv8qi<mode>"
3949 [(match_operand:V8QI 0 "s_register_operand" "")
3950 (match_operand:VDX 1 "s_register_operand" "")]
3953 neon_reinterpret (operands[0], operands[1]);
3957 (define_expand "neon_vreinterpretv4hi<mode>"
3958 [(match_operand:V4HI 0 "s_register_operand" "")
3959 (match_operand:VDX 1 "s_register_operand" "")]
3962 neon_reinterpret (operands[0], operands[1]);
3966 (define_expand "neon_vreinterpretv2si<mode>"
3967 [(match_operand:V2SI 0 "s_register_operand" "")
3968 (match_operand:VDX 1 "s_register_operand" "")]
3971 neon_reinterpret (operands[0], operands[1]);
3975 (define_expand "neon_vreinterpretv2sf<mode>"
3976 [(match_operand:V2SF 0 "s_register_operand" "")
3977 (match_operand:VDX 1 "s_register_operand" "")]
3980 neon_reinterpret (operands[0], operands[1]);
3984 (define_expand "neon_vreinterpretdi<mode>"
3985 [(match_operand:DI 0 "s_register_operand" "")
3986 (match_operand:VDX 1 "s_register_operand" "")]
3989 neon_reinterpret (operands[0], operands[1]);
3993 (define_expand "neon_vreinterpretv16qi<mode>"
3994 [(match_operand:V16QI 0 "s_register_operand" "")
3995 (match_operand:VQX 1 "s_register_operand" "")]
3998 neon_reinterpret (operands[0], operands[1]);
4002 (define_expand "neon_vreinterpretv8hi<mode>"
4003 [(match_operand:V8HI 0 "s_register_operand" "")
4004 (match_operand:VQX 1 "s_register_operand" "")]
4007 neon_reinterpret (operands[0], operands[1]);
4011 (define_expand "neon_vreinterpretv4si<mode>"
4012 [(match_operand:V4SI 0 "s_register_operand" "")
4013 (match_operand:VQX 1 "s_register_operand" "")]
4016 neon_reinterpret (operands[0], operands[1]);
4020 (define_expand "neon_vreinterpretv4sf<mode>"
4021 [(match_operand:V4SF 0 "s_register_operand" "")
4022 (match_operand:VQX 1 "s_register_operand" "")]
4025 neon_reinterpret (operands[0], operands[1]);
4029 (define_expand "neon_vreinterpretv2di<mode>"
4030 [(match_operand:V2DI 0 "s_register_operand" "")
4031 (match_operand:VQX 1 "s_register_operand" "")]
4034 neon_reinterpret (operands[0], operands[1]);
4038 (define_insn "neon_vld1<mode>"
4039 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
4040 (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
4043 "vld1.<V_sz_elem>\t%h0, [%1]"
4044 [(set_attr "neon_type" "neon_vld1_1_2_regs")]
4047 (define_insn "neon_vld1_lane<mode>"
4048 [(set (match_operand:VDX 0 "s_register_operand" "=w")
4049 (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
4050 (match_operand:VDX 2 "s_register_operand" "0")
4051 (match_operand:SI 3 "immediate_operand" "i")]
4055 HOST_WIDE_INT lane = INTVAL (operands[3]);
4056 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4057 if (lane < 0 || lane >= max)
4058 error ("lane out of range");
4060 return "vld1.<V_sz_elem>\t%P0, [%1]";
4062 return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
4064 [(set (attr "neon_type")
4065 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
4066 (const_string "neon_vld1_1_2_regs")
4067 (const_string "neon_vld1_vld2_lane")))]
4070 (define_insn "neon_vld1_lane<mode>"
4071 [(set (match_operand:VQX 0 "s_register_operand" "=w")
4072 (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
4073 (match_operand:VQX 2 "s_register_operand" "0")
4074 (match_operand:SI 3 "immediate_operand" "i")]
4078 HOST_WIDE_INT lane = INTVAL (operands[3]);
4079 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4080 int regno = REGNO (operands[0]);
4081 if (lane < 0 || lane >= max)
4082 error ("lane out of range");
4083 else if (lane >= max / 2)
4087 operands[3] = GEN_INT (lane);
4089 operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
4091 return "vld1.<V_sz_elem>\t%P0, [%1]";
4093 return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
4095 [(set (attr "neon_type")
4096 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
4097 (const_string "neon_vld1_1_2_regs")
4098 (const_string "neon_vld1_vld2_lane")))]
4101 (define_insn "neon_vld1_dup<mode>"
4102 [(set (match_operand:VDX 0 "s_register_operand" "=w")
4103 (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
4107 if (GET_MODE_NUNITS (<MODE>mode) > 1)
4108 return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
4110 return "vld1.<V_sz_elem>\t%h0, [%1]";
4112 [(set (attr "neon_type")
4113 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
4114 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")
4115 (const_string "neon_vld1_1_2_regs")))]
4118 (define_insn "neon_vld1_dup<mode>"
4119 [(set (match_operand:VQX 0 "s_register_operand" "=w")
4120 (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
4124 if (GET_MODE_NUNITS (<MODE>mode) > 2)
4125 return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
4127 return "vld1.<V_sz_elem>\t%h0, [%1]";
4129 [(set (attr "neon_type")
4130 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
4131 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")
4132 (const_string "neon_vld1_1_2_regs")))]
4135 (define_insn "neon_vst1<mode>"
4136 [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
4137 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
4140 "vst1.<V_sz_elem>\t%h1, [%0]"
4141 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
4143 (define_insn "neon_vst1_lane<mode>"
4144 [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
4145 (vec_select:<V_elem>
4146 (match_operand:VDX 1 "s_register_operand" "w")
4147 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
4150 HOST_WIDE_INT lane = INTVAL (operands[2]);
4151 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4152 if (lane < 0 || lane >= max)
4153 error ("lane out of range");
4155 return "vst1.<V_sz_elem>\t{%P1}, [%0]";
4157 return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
4159 [(set (attr "neon_type")
4160 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
4161 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
4162 (const_string "neon_vst1_vst2_lane")))])
4164 (define_insn "neon_vst1_lane<mode>"
4165 [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
4166 (vec_select:<V_elem>
4167 (match_operand:VQX 1 "s_register_operand" "w")
4168 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
4171 HOST_WIDE_INT lane = INTVAL (operands[2]);
4172 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4173 int regno = REGNO (operands[1]);
4174 if (lane < 0 || lane >= max)
4175 error ("lane out of range");
4176 else if (lane >= max / 2)
4180 operands[2] = GEN_INT (lane);
4182 operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
4184 return "vst1.<V_sz_elem>\t{%P1}, [%0]";
4186 return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
4188 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
4191 (define_insn "neon_vld2<mode>"
4192 [(set (match_operand:TI 0 "s_register_operand" "=w")
4193 (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
4194 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4198 if (<V_sz_elem> == 64)
4199 return "vld1.64\t%h0, [%1]";
4201 return "vld2.<V_sz_elem>\t%h0, [%1]";
4203 [(set (attr "neon_type")
4204 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4205 (const_string "neon_vld1_1_2_regs")
4206 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))]
4209 (define_insn "neon_vld2<mode>"
4210 [(set (match_operand:OI 0 "s_register_operand" "=w")
4211 (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
4212 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4215 "vld2.<V_sz_elem>\t%h0, [%1]"
4216 [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
4218 (define_insn "neon_vld2_lane<mode>"
4219 [(set (match_operand:TI 0 "s_register_operand" "=w")
4220 (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
4221 (match_operand:TI 2 "s_register_operand" "0")
4222 (match_operand:SI 3 "immediate_operand" "i")
4223 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4227 HOST_WIDE_INT lane = INTVAL (operands[3]);
4228 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4229 int regno = REGNO (operands[0]);
4231 if (lane < 0 || lane >= max)
4232 error ("lane out of range");
4233 ops[0] = gen_rtx_REG (DImode, regno);
4234 ops[1] = gen_rtx_REG (DImode, regno + 2);
4235 ops[2] = operands[1];
4236 ops[3] = operands[3];
4237 output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
4240 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
4243 (define_insn "neon_vld2_lane<mode>"
4244 [(set (match_operand:OI 0 "s_register_operand" "=w")
4245 (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
4246 (match_operand:OI 2 "s_register_operand" "0")
4247 (match_operand:SI 3 "immediate_operand" "i")
4248 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4252 HOST_WIDE_INT lane = INTVAL (operands[3]);
4253 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4254 int regno = REGNO (operands[0]);
4256 if (lane < 0 || lane >= max)
4257 error ("lane out of range");
4258 else if (lane >= max / 2)
4263 ops[0] = gen_rtx_REG (DImode, regno);
4264 ops[1] = gen_rtx_REG (DImode, regno + 4);
4265 ops[2] = operands[1];
4266 ops[3] = GEN_INT (lane);
4267 output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
4270 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
4273 (define_insn "neon_vld2_dup<mode>"
4274 [(set (match_operand:TI 0 "s_register_operand" "=w")
4275 (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
4276 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4280 if (GET_MODE_NUNITS (<MODE>mode) > 1)
4281 return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
4283 return "vld1.<V_sz_elem>\t%h0, [%1]";
4285 [(set (attr "neon_type")
4286 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
4287 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")
4288 (const_string "neon_vld1_1_2_regs")))]
4291 (define_insn "neon_vst2<mode>"
4292 [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
4293 (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
4294 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4298 if (<V_sz_elem> == 64)
4299 return "vst1.64\t%h1, [%0]";
4301 return "vst2.<V_sz_elem>\t%h1, [%0]";
4303 [(set (attr "neon_type")
4304 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4305 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
4306 (const_string "neon_vst1_1_2_regs_vst2_2_regs")))]
4309 (define_insn "neon_vst2<mode>"
4310 [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
4311 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
4312 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4315 "vst2.<V_sz_elem>\t%h1, [%0]"
4316 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
4319 (define_insn "neon_vst2_lane<mode>"
4320 [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
4321 (unspec:<V_two_elem>
4322 [(match_operand:TI 1 "s_register_operand" "w")
4323 (match_operand:SI 2 "immediate_operand" "i")
4324 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4328 HOST_WIDE_INT lane = INTVAL (operands[2]);
4329 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4330 int regno = REGNO (operands[1]);
4332 if (lane < 0 || lane >= max)
4333 error ("lane out of range");
4334 ops[0] = operands[0];
4335 ops[1] = gen_rtx_REG (DImode, regno);
4336 ops[2] = gen_rtx_REG (DImode, regno + 2);
4337 ops[3] = operands[2];
4338 output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
4341 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
4344 (define_insn "neon_vst2_lane<mode>"
4345 [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
4346 (unspec:<V_two_elem>
4347 [(match_operand:OI 1 "s_register_operand" "w")
4348 (match_operand:SI 2 "immediate_operand" "i")
4349 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4353 HOST_WIDE_INT lane = INTVAL (operands[2]);
4354 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4355 int regno = REGNO (operands[1]);
4357 if (lane < 0 || lane >= max)
4358 error ("lane out of range");
4359 else if (lane >= max / 2)
4364 ops[0] = operands[0];
4365 ops[1] = gen_rtx_REG (DImode, regno);
4366 ops[2] = gen_rtx_REG (DImode, regno + 4);
4367 ops[3] = GEN_INT (lane);
4368 output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
4371 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
4374 (define_insn "neon_vld3<mode>"
4375 [(set (match_operand:EI 0 "s_register_operand" "=w")
4376 (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
4377 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4381 if (<V_sz_elem> == 64)
4382 return "vld1.64\t%h0, [%1]";
4384 return "vld3.<V_sz_elem>\t%h0, [%1]";
4386 [(set (attr "neon_type")
4387 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4388 (const_string "neon_vld1_1_2_regs")
4389 (const_string "neon_vld3_vld4")))]
4392 (define_expand "neon_vld3<mode>"
4393 [(match_operand:CI 0 "s_register_operand" "=w")
4394 (match_operand:SI 1 "s_register_operand" "+r")
4395 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4398 emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
4399 operands[1], operands[1]));
4400 emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
4401 operands[1], operands[1]));
4405 (define_insn "neon_vld3qa<mode>"
4406 [(set (match_operand:CI 0 "s_register_operand" "=w")
4407 (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
4408 (match_operand:CI 1 "s_register_operand" "0")
4409 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4411 (set (match_operand:SI 2 "s_register_operand" "=r")
4412 (plus:SI (match_dup 3)
4416 int regno = REGNO (operands[0]);
4418 ops[0] = gen_rtx_REG (DImode, regno);
4419 ops[1] = gen_rtx_REG (DImode, regno + 4);
4420 ops[2] = gen_rtx_REG (DImode, regno + 8);
4421 ops[3] = operands[2];
4422 output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
4425 [(set_attr "neon_type" "neon_vld3_vld4")]
4428 (define_insn "neon_vld3qb<mode>"
4429 [(set (match_operand:CI 0 "s_register_operand" "=w")
4430 (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
4431 (match_operand:CI 1 "s_register_operand" "0")
4432 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4434 (set (match_operand:SI 2 "s_register_operand" "=r")
4435 (plus:SI (match_dup 3)
4439 int regno = REGNO (operands[0]);
4441 ops[0] = gen_rtx_REG (DImode, regno + 2);
4442 ops[1] = gen_rtx_REG (DImode, regno + 6);
4443 ops[2] = gen_rtx_REG (DImode, regno + 10);
4444 ops[3] = operands[2];
4445 output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
4448 [(set_attr "neon_type" "neon_vld3_vld4")]
4451 (define_insn "neon_vld3_lane<mode>"
4452 [(set (match_operand:EI 0 "s_register_operand" "=w")
4453 (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
4454 (match_operand:EI 2 "s_register_operand" "0")
4455 (match_operand:SI 3 "immediate_operand" "i")
4456 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4460 HOST_WIDE_INT lane = INTVAL (operands[3]);
4461 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4462 int regno = REGNO (operands[0]);
4464 if (lane < 0 || lane >= max)
4465 error ("lane out of range");
4466 ops[0] = gen_rtx_REG (DImode, regno);
4467 ops[1] = gen_rtx_REG (DImode, regno + 2);
4468 ops[2] = gen_rtx_REG (DImode, regno + 4);
4469 ops[3] = operands[1];
4470 ops[4] = operands[3];
4471 output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
4475 [(set_attr "neon_type" "neon_vld3_vld4_lane")]
4478 (define_insn "neon_vld3_lane<mode>"
4479 [(set (match_operand:CI 0 "s_register_operand" "=w")
4480 (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
4481 (match_operand:CI 2 "s_register_operand" "0")
4482 (match_operand:SI 3 "immediate_operand" "i")
4483 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4487 HOST_WIDE_INT lane = INTVAL (operands[3]);
4488 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4489 int regno = REGNO (operands[0]);
4491 if (lane < 0 || lane >= max)
4492 error ("lane out of range");
4493 else if (lane >= max / 2)
4498 ops[0] = gen_rtx_REG (DImode, regno);
4499 ops[1] = gen_rtx_REG (DImode, regno + 4);
4500 ops[2] = gen_rtx_REG (DImode, regno + 8);
4501 ops[3] = operands[1];
4502 ops[4] = GEN_INT (lane);
4503 output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
4507 [(set_attr "neon_type" "neon_vld3_vld4_lane")]
4510 (define_insn "neon_vld3_dup<mode>"
4511 [(set (match_operand:EI 0 "s_register_operand" "=w")
4512 (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
4513 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4517 if (GET_MODE_NUNITS (<MODE>mode) > 1)
4519 int regno = REGNO (operands[0]);
4521 ops[0] = gen_rtx_REG (DImode, regno);
4522 ops[1] = gen_rtx_REG (DImode, regno + 2);
4523 ops[2] = gen_rtx_REG (DImode, regno + 4);
4524 ops[3] = operands[1];
4525 output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
4529 return "vld1.<V_sz_elem>\t%h0, [%1]";
4531 [(set (attr "neon_type")
4532 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
4533 (const_string "neon_vld3_vld4_all_lanes")
4534 (const_string "neon_vld1_1_2_regs")))])
4536 (define_insn "neon_vst3<mode>"
4537 [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
4538 (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
4539 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4543 if (<V_sz_elem> == 64)
4544 return "vst1.64\t%h1, [%0]";
4546 return "vst3.<V_sz_elem>\t%h1, [%0]";
4548 [(set (attr "neon_type")
4549 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4550 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
4551 (const_string "neon_vst2_4_regs_vst3_vst4")))])
4553 (define_expand "neon_vst3<mode>"
4554 [(match_operand:SI 0 "s_register_operand" "+r")
4555 (match_operand:CI 1 "s_register_operand" "w")
4556 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4559 emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
4560 emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
4564 (define_insn "neon_vst3qa<mode>"
4565 [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
4566 (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
4567 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4569 (set (match_operand:SI 0 "s_register_operand" "=r")
4570 (plus:SI (match_dup 1)
4574 int regno = REGNO (operands[2]);
4576 ops[0] = operands[0];
4577 ops[1] = gen_rtx_REG (DImode, regno);
4578 ops[2] = gen_rtx_REG (DImode, regno + 4);
4579 ops[3] = gen_rtx_REG (DImode, regno + 8);
4580 output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
4583 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
4586 (define_insn "neon_vst3qb<mode>"
4587 [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
4588 (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
4589 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4591 (set (match_operand:SI 0 "s_register_operand" "=r")
4592 (plus:SI (match_dup 1)
4596 int regno = REGNO (operands[2]);
4598 ops[0] = operands[0];
4599 ops[1] = gen_rtx_REG (DImode, regno + 2);
4600 ops[2] = gen_rtx_REG (DImode, regno + 6);
4601 ops[3] = gen_rtx_REG (DImode, regno + 10);
4602 output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
4605 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
4608 (define_insn "neon_vst3_lane<mode>"
4609 [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
4610 (unspec:<V_three_elem>
4611 [(match_operand:EI 1 "s_register_operand" "w")
4612 (match_operand:SI 2 "immediate_operand" "i")
4613 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4617 HOST_WIDE_INT lane = INTVAL (operands[2]);
4618 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4619 int regno = REGNO (operands[1]);
4621 if (lane < 0 || lane >= max)
4622 error ("lane out of range");
4623 ops[0] = operands[0];
4624 ops[1] = gen_rtx_REG (DImode, regno);
4625 ops[2] = gen_rtx_REG (DImode, regno + 2);
4626 ops[3] = gen_rtx_REG (DImode, regno + 4);
4627 ops[4] = operands[2];
4628 output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
4632 [(set_attr "neon_type" "neon_vst3_vst4_lane")]
4635 (define_insn "neon_vst3_lane<mode>"
4636 [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
4637 (unspec:<V_three_elem>
4638 [(match_operand:CI 1 "s_register_operand" "w")
4639 (match_operand:SI 2 "immediate_operand" "i")
4640 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4644 HOST_WIDE_INT lane = INTVAL (operands[2]);
4645 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4646 int regno = REGNO (operands[1]);
4648 if (lane < 0 || lane >= max)
4649 error ("lane out of range");
4650 else if (lane >= max / 2)
4655 ops[0] = operands[0];
4656 ops[1] = gen_rtx_REG (DImode, regno);
4657 ops[2] = gen_rtx_REG (DImode, regno + 4);
4658 ops[3] = gen_rtx_REG (DImode, regno + 8);
4659 ops[4] = GEN_INT (lane);
4660 output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
4664 [(set_attr "neon_type" "neon_vst3_vst4_lane")])
4666 (define_insn "neon_vld4<mode>"
4667 [(set (match_operand:OI 0 "s_register_operand" "=w")
4668 (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
4669 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4673 if (<V_sz_elem> == 64)
4674 return "vld1.64\t%h0, [%1]";
4676 return "vld4.<V_sz_elem>\t%h0, [%1]";
4678 [(set (attr "neon_type")
4679 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4680 (const_string "neon_vld1_1_2_regs")
4681 (const_string "neon_vld3_vld4")))]
4684 (define_expand "neon_vld4<mode>"
4685 [(match_operand:XI 0 "s_register_operand" "=w")
4686 (match_operand:SI 1 "s_register_operand" "+r")
4687 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4690 emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
4691 operands[1], operands[1]));
4692 emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
4693 operands[1], operands[1]));
4697 (define_insn "neon_vld4qa<mode>"
4698 [(set (match_operand:XI 0 "s_register_operand" "=w")
4699 (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
4700 (match_operand:XI 1 "s_register_operand" "0")
4701 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4703 (set (match_operand:SI 2 "s_register_operand" "=r")
4704 (plus:SI (match_dup 3)
4708 int regno = REGNO (operands[0]);
4710 ops[0] = gen_rtx_REG (DImode, regno);
4711 ops[1] = gen_rtx_REG (DImode, regno + 4);
4712 ops[2] = gen_rtx_REG (DImode, regno + 8);
4713 ops[3] = gen_rtx_REG (DImode, regno + 12);
4714 ops[4] = operands[2];
4715 output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
4718 [(set_attr "neon_type" "neon_vld3_vld4")]
4721 (define_insn "neon_vld4qb<mode>"
4722 [(set (match_operand:XI 0 "s_register_operand" "=w")
4723 (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
4724 (match_operand:XI 1 "s_register_operand" "0")
4725 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4727 (set (match_operand:SI 2 "s_register_operand" "=r")
4728 (plus:SI (match_dup 3)
4732 int regno = REGNO (operands[0]);
4734 ops[0] = gen_rtx_REG (DImode, regno + 2);
4735 ops[1] = gen_rtx_REG (DImode, regno + 6);
4736 ops[2] = gen_rtx_REG (DImode, regno + 10);
4737 ops[3] = gen_rtx_REG (DImode, regno + 14);
4738 ops[4] = operands[2];
4739 output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
4742 [(set_attr "neon_type" "neon_vld3_vld4")]
4745 (define_insn "neon_vld4_lane<mode>"
4746 [(set (match_operand:OI 0 "s_register_operand" "=w")
4747 (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
4748 (match_operand:OI 2 "s_register_operand" "0")
4749 (match_operand:SI 3 "immediate_operand" "i")
4750 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4754 HOST_WIDE_INT lane = INTVAL (operands[3]);
4755 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4756 int regno = REGNO (operands[0]);
4758 if (lane < 0 || lane >= max)
4759 error ("lane out of range");
4760 ops[0] = gen_rtx_REG (DImode, regno);
4761 ops[1] = gen_rtx_REG (DImode, regno + 2);
4762 ops[2] = gen_rtx_REG (DImode, regno + 4);
4763 ops[3] = gen_rtx_REG (DImode, regno + 6);
4764 ops[4] = operands[1];
4765 ops[5] = operands[3];
4766 output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
4770 [(set_attr "neon_type" "neon_vld3_vld4_lane")]
4773 (define_insn "neon_vld4_lane<mode>"
4774 [(set (match_operand:XI 0 "s_register_operand" "=w")
4775 (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
4776 (match_operand:XI 2 "s_register_operand" "0")
4777 (match_operand:SI 3 "immediate_operand" "i")
4778 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4782 HOST_WIDE_INT lane = INTVAL (operands[3]);
4783 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4784 int regno = REGNO (operands[0]);
4786 if (lane < 0 || lane >= max)
4787 error ("lane out of range");
4788 else if (lane >= max / 2)
4793 ops[0] = gen_rtx_REG (DImode, regno);
4794 ops[1] = gen_rtx_REG (DImode, regno + 4);
4795 ops[2] = gen_rtx_REG (DImode, regno + 8);
4796 ops[3] = gen_rtx_REG (DImode, regno + 12);
4797 ops[4] = operands[1];
4798 ops[5] = GEN_INT (lane);
4799 output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
4803 [(set_attr "neon_type" "neon_vld3_vld4_lane")]
4806 (define_insn "neon_vld4_dup<mode>"
4807 [(set (match_operand:OI 0 "s_register_operand" "=w")
4808 (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
4809 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4813 if (GET_MODE_NUNITS (<MODE>mode) > 1)
4815 int regno = REGNO (operands[0]);
4817 ops[0] = gen_rtx_REG (DImode, regno);
4818 ops[1] = gen_rtx_REG (DImode, regno + 2);
4819 ops[2] = gen_rtx_REG (DImode, regno + 4);
4820 ops[3] = gen_rtx_REG (DImode, regno + 6);
4821 ops[4] = operands[1];
4822 output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
4827 return "vld1.<V_sz_elem>\t%h0, [%1]";
4829 [(set (attr "neon_type")
4830 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
4831 (const_string "neon_vld3_vld4_all_lanes")
4832 (const_string "neon_vld1_1_2_regs")))]
4835 (define_insn "neon_vst4<mode>"
4836 [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
4837 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
4838 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4842 if (<V_sz_elem> == 64)
4843 return "vst1.64\t%h1, [%0]";
4845 return "vst4.<V_sz_elem>\t%h1, [%0]";
4847 [(set (attr "neon_type")
4848 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
4849 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
4850 (const_string "neon_vst2_4_regs_vst3_vst4")))]
4853 (define_expand "neon_vst4<mode>"
4854 [(match_operand:SI 0 "s_register_operand" "+r")
4855 (match_operand:XI 1 "s_register_operand" "w")
4856 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4859 emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
4860 emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
4864 (define_insn "neon_vst4qa<mode>"
4865 [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
4866 (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
4867 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4869 (set (match_operand:SI 0 "s_register_operand" "=r")
4870 (plus:SI (match_dup 1)
4874 int regno = REGNO (operands[2]);
4876 ops[0] = operands[0];
4877 ops[1] = gen_rtx_REG (DImode, regno);
4878 ops[2] = gen_rtx_REG (DImode, regno + 4);
4879 ops[3] = gen_rtx_REG (DImode, regno + 8);
4880 ops[4] = gen_rtx_REG (DImode, regno + 12);
4881 output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
4884 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
4887 (define_insn "neon_vst4qb<mode>"
4888 [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
4889 (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
4890 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4892 (set (match_operand:SI 0 "s_register_operand" "=r")
4893 (plus:SI (match_dup 1)
4897 int regno = REGNO (operands[2]);
4899 ops[0] = operands[0];
4900 ops[1] = gen_rtx_REG (DImode, regno + 2);
4901 ops[2] = gen_rtx_REG (DImode, regno + 6);
4902 ops[3] = gen_rtx_REG (DImode, regno + 10);
4903 ops[4] = gen_rtx_REG (DImode, regno + 14);
4904 output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
4907 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
4910 (define_insn "neon_vst4_lane<mode>"
4911 [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
4912 (unspec:<V_four_elem>
4913 [(match_operand:OI 1 "s_register_operand" "w")
4914 (match_operand:SI 2 "immediate_operand" "i")
4915 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4919 HOST_WIDE_INT lane = INTVAL (operands[2]);
4920 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4921 int regno = REGNO (operands[1]);
4923 if (lane < 0 || lane >= max)
4924 error ("lane out of range");
4925 ops[0] = operands[0];
4926 ops[1] = gen_rtx_REG (DImode, regno);
4927 ops[2] = gen_rtx_REG (DImode, regno + 2);
4928 ops[3] = gen_rtx_REG (DImode, regno + 4);
4929 ops[4] = gen_rtx_REG (DImode, regno + 6);
4930 ops[5] = operands[2];
4931 output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
4935 [(set_attr "neon_type" "neon_vst3_vst4_lane")]
4938 (define_insn "neon_vst4_lane<mode>"
4939 [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
4940 (unspec:<V_four_elem>
4941 [(match_operand:XI 1 "s_register_operand" "w")
4942 (match_operand:SI 2 "immediate_operand" "i")
4943 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
4947 HOST_WIDE_INT lane = INTVAL (operands[2]);
4948 HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
4949 int regno = REGNO (operands[1]);
4951 if (lane < 0 || lane >= max)
4952 error ("lane out of range");
4953 else if (lane >= max / 2)
4958 ops[0] = operands[0];
4959 ops[1] = gen_rtx_REG (DImode, regno);
4960 ops[2] = gen_rtx_REG (DImode, regno + 4);
4961 ops[3] = gen_rtx_REG (DImode, regno + 8);
4962 ops[4] = gen_rtx_REG (DImode, regno + 12);
4963 ops[5] = GEN_INT (lane);
4964 output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
4968 [(set_attr "neon_type" "neon_vst3_vst4_lane")]
4971 (define_expand "neon_vand<mode>"
4972 [(match_operand:VDQX 0 "s_register_operand" "")
4973 (match_operand:VDQX 1 "s_register_operand" "")
4974 (match_operand:VDQX 2 "neon_inv_logic_op2" "")
4975 (match_operand:SI 3 "immediate_operand" "")]
4978 emit_insn (gen_and<mode>3<V_suf64> (operands[0], operands[1], operands[2]));
4982 (define_expand "neon_vorr<mode>"
4983 [(match_operand:VDQX 0 "s_register_operand" "")
4984 (match_operand:VDQX 1 "s_register_operand" "")
4985 (match_operand:VDQX 2 "neon_logic_op2" "")
4986 (match_operand:SI 3 "immediate_operand" "")]
4989 emit_insn (gen_ior<mode>3<V_suf64> (operands[0], operands[1], operands[2]));
4993 (define_expand "neon_veor<mode>"
4994 [(match_operand:VDQX 0 "s_register_operand" "")
4995 (match_operand:VDQX 1 "s_register_operand" "")
4996 (match_operand:VDQX 2 "s_register_operand" "")
4997 (match_operand:SI 3 "immediate_operand" "")]
5000 emit_insn (gen_xor<mode>3<V_suf64> (operands[0], operands[1], operands[2]));
5004 (define_expand "neon_vbic<mode>"
5005 [(match_operand:VDQX 0 "s_register_operand" "")
5006 (match_operand:VDQX 1 "s_register_operand" "")
5007 (match_operand:VDQX 2 "neon_logic_op2" "")
5008 (match_operand:SI 3 "immediate_operand" "")]
5011 emit_insn (gen_bic<mode>3_neon (operands[0], operands[1], operands[2]));
5015 (define_expand "neon_vorn<mode>"
5016 [(match_operand:VDQX 0 "s_register_operand" "")
5017 (match_operand:VDQX 1 "s_register_operand" "")
5018 (match_operand:VDQX 2 "neon_inv_logic_op2" "")
5019 (match_operand:SI 3 "immediate_operand" "")]
5022 emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));