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1 ;; ARM Cortex-A8 NEON scheduling description.
2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery.
4
5 ;; This file is part of GCC.
6
7 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
8 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
10 ;; License for more details.
11
12 ;; You should have received a copy of the GNU General Public License
13 ;; along with GCC; see the file COPYING.  If not, write to
14 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
15 ;; Boston, MA 02110-1301, USA.
16
17 (define_automaton "cortex_a8_neon")
18
19 ;; Only one load, store, permute, MCR or MRC instruction can be issued
20 ;; per cycle.
21 (define_cpu_unit "cortex_a8_neon_issue_perm" "cortex_a8_neon")
22
23 ;; Only one data-processing instruction can be issued per cycle.
24 (define_cpu_unit "cortex_a8_neon_issue_dp" "cortex_a8_neon")
25
26 ;; The VFPLite unit (non-pipelined).
27 (define_cpu_unit "cortex_a8_vfplite" "cortex_a8_neon")
28
29 ;; We need a special mutual exclusion (to be used in addition to
30 ;; cortex_a8_neon_issue_dp) for the case when an instruction such as
31 ;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to
32 ;; E2 of the floating-point add pipeline.  On the cycle previous to that
33 ;; forward we must prevent issue of any instruction to the floating-point
34 ;; add pipeline, but still allow issue of a data-processing instruction
35 ;; to any of the other pipelines.
36 (define_cpu_unit "cortex_a8_neon_issue_fadd" "cortex_a8_neon")
37
38 ;; Patterns of reservation.
39 ;; We model the NEON issue units as running in parallel with the core ones.
40 ;; We assume that multi-cycle NEON instructions get decomposed into
41 ;; micro-ops as they are issued into the NEON pipeline, and not as they
42 ;; are issued into the ARM pipeline.  Dual issue may not occur except
43 ;; upon the first and last cycles of a multi-cycle instruction, but it
44 ;; is unclear whether two multi-cycle instructions can issue together (in
45 ;; this model they cannot).  It is also unclear whether a pair of
46 ;; a multi-cycle and single-cycle instructions, that could potentially
47 ;; issue together, only do so if (say) the single-cycle one precedes
48 ;; the other.
49
50 (define_reservation "cortex_a8_neon_dp"
51                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp")
52 (define_reservation "cortex_a8_neon_dp_2"
53                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp,\
54                      cortex_a8_neon_issue_dp")
55 (define_reservation "cortex_a8_neon_dp_4"
56                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp,\
57                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
58                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
59                      cortex_a8_neon_issue_dp")
60
61 (define_reservation "cortex_a8_neon_fadd"
62                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp+\
63                      cortex_a8_neon_issue_fadd")
64 (define_reservation "cortex_a8_neon_fadd_2"
65                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp+\
66                      cortex_a8_neon_issue_fadd,\
67                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_fadd")
68
69 (define_reservation "cortex_a8_neon_perm"
70                     "(cortex_a8_alu0|cortex_a8_alu1)+\
71                      cortex_a8_neon_issue_perm")
72 (define_reservation "cortex_a8_neon_perm_2"
73                     "(cortex_a8_alu0|cortex_a8_alu1)+\
74                      cortex_a8_neon_issue_perm,\
75                      cortex_a8_neon_issue_perm")
76 (define_reservation "cortex_a8_neon_perm_3"
77                     "(cortex_a8_alu0|cortex_a8_alu1)+\
78                      cortex_a8_neon_issue_perm,\
79                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
80                      cortex_a8_neon_issue_perm")
81
82 (define_reservation "cortex_a8_neon_ls"
83                     "cortex_a8_issue_ls+cortex_a8_neon_issue_perm")
84 (define_reservation "cortex_a8_neon_ls_2"
85                     "cortex_a8_issue_ls+cortex_a8_neon_issue_perm,\
86                      cortex_a8_neon_issue_perm")
87 (define_reservation "cortex_a8_neon_ls_3"
88                     "cortex_a8_issue_ls+cortex_a8_neon_issue_perm,\
89                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
90                      cortex_a8_neon_issue_perm")
91 (define_reservation "cortex_a8_neon_ls_4"
92                     "cortex_a8_issue_ls+cortex_a8_neon_issue_perm,\
93                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
94                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
95                      cortex_a8_neon_issue_perm")
96 (define_reservation "cortex_a8_neon_ls_5"
97                     "cortex_a8_issue_ls+cortex_a8_neon_issue_perm,\
98                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
99                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
100                      cortex_a8_neon_issue_dp+cortex_a8_neon_issue_perm,\
101                      cortex_a8_neon_issue_perm")
102
103 (define_reservation "cortex_a8_neon_fmul_then_fadd"
104                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp,\
105                      nothing*3,\
106                      cortex_a8_neon_issue_fadd")
107 (define_reservation "cortex_a8_neon_fmul_then_fadd_2"
108                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp,\
109                      cortex_a8_neon_issue_dp,\
110                      nothing*2,\
111                      cortex_a8_neon_issue_fadd,\
112                      cortex_a8_neon_issue_fadd")
113
114 ;; VFP instructions can only be single-issued into the NEON pipeline.
115 (define_reservation "cortex_a8_vfp"
116                     "(cortex_a8_alu0|cortex_a8_alu1)+cortex_a8_neon_issue_dp+\
117                      cortex_a8_neon_issue_perm+cortex_a8_vfplite")
118
119 ;; VFP instructions.
120 ;; The VFPLite unit that executes these isn't pipelined; we give the
121 ;; worst-case latencies (and choose the double-precision ones where we
122 ;; do not distinguish on precision).  We assume RunFast mode is not
123 ;; enabled and therefore do not model the possible VFP instruction
124 ;; execution in the NEON floating point pipelines, nor additional
125 ;; latencies for the processing of subnormals.
126 ;;
127 ;; TODO: RunFast mode could potentially be enabled when -ffast-math
128 ;; is specified.
129
130 (define_insn_reservation "cortex_a8_vfp_add_sub" 10
131   (and (eq_attr "tune" "cortexa8")
132        (eq_attr "type" "farith"))
133   "cortex_a8_vfp,cortex_a8_vfplite*9")
134
135 (define_insn_reservation "cortex_a8_vfp_muls" 12
136   (and (eq_attr "tune" "cortexa8")
137        (eq_attr "type" "fmuls"))
138   "cortex_a8_vfp,cortex_a8_vfplite*11")
139
140 (define_insn_reservation "cortex_a8_vfp_muld" 17
141   (and (eq_attr "tune" "cortexa8")
142        (eq_attr "type" "fmuld"))
143   "cortex_a8_vfp,cortex_a8_vfplite*16")
144
145 (define_insn_reservation "cortex_a8_vfp_macs" 21
146   (and (eq_attr "tune" "cortexa8")
147        (eq_attr "type" "fmacs"))
148   "cortex_a8_vfp,cortex_a8_vfplite*20")
149
150 (define_insn_reservation "cortex_a8_vfp_macd" 26
151   (and (eq_attr "tune" "cortexa8")
152        (eq_attr "type" "fmacd"))
153   "cortex_a8_vfp,cortex_a8_vfplite*25")
154
155 (define_insn_reservation "cortex_a8_vfp_divs" 37
156   (and (eq_attr "tune" "cortexa8")
157        (eq_attr "type" "fdivs"))
158   "cortex_a8_vfp,cortex_a8_vfplite*36")
159
160 (define_insn_reservation "cortex_a8_vfp_divd" 65
161   (and (eq_attr "tune" "cortexa8")
162        (eq_attr "type" "fdivd"))
163   "cortex_a8_vfp,cortex_a8_vfplite*64")
164
165 ;; Comparisons can actually take 7 cycles sometimes instead of four,
166 ;; but given all the other instructions lumped into type=ffarith that
167 ;; take four cycles, we pick that latency.
168 (define_insn_reservation "cortex_a8_vfp_farith" 4
169   (and (eq_attr "tune" "cortexa8")
170        (eq_attr "type" "ffarith"))
171   "cortex_a8_vfp,cortex_a8_vfplite*3")
172
173 (define_insn_reservation "cortex_a8_vfp_cvt" 7
174   (and (eq_attr "tune" "cortexa8")
175        (eq_attr "type" "f_cvt"))
176   "cortex_a8_vfp,cortex_a8_vfplite*6")
177
178 ;; NEON -> core transfers.
179
180 (define_insn_reservation "neon_mrc" 20
181   (and (eq_attr "tune" "cortexa8")
182        (eq_attr "neon_type" "neon_mrc"))
183   "cortex_a8_neon_ls")
184
185 (define_insn_reservation "neon_mrrc" 21
186   (and (eq_attr "tune" "cortexa8")
187        (eq_attr "neon_type" "neon_mrrc"))
188   "cortex_a8_neon_ls_2")
189
190 ;; The remainder of this file is auto-generated by neon-schedgen.
191
192 ;; Instructions using this reservation read their source operands at N2, and
193 ;; produce a result at N3.
194 (define_insn_reservation "neon_int_1" 3
195   (and (eq_attr "tune" "cortexa8")
196        (eq_attr "neon_type" "neon_int_1"))
197   "cortex_a8_neon_dp")
198
199 ;; Instructions using this reservation read their (D|Q)m operands at N1,
200 ;; their (D|Q)n operands at N2, and produce a result at N3.
201 (define_insn_reservation "neon_int_2" 3
202   (and (eq_attr "tune" "cortexa8")
203        (eq_attr "neon_type" "neon_int_2"))
204   "cortex_a8_neon_dp")
205
206 ;; Instructions using this reservation read their source operands at N1, and
207 ;; produce a result at N3.
208 (define_insn_reservation "neon_int_3" 3
209   (and (eq_attr "tune" "cortexa8")
210        (eq_attr "neon_type" "neon_int_3"))
211   "cortex_a8_neon_dp")
212
213 ;; Instructions using this reservation read their source operands at N2, and
214 ;; produce a result at N4.
215 (define_insn_reservation "neon_int_4" 4
216   (and (eq_attr "tune" "cortexa8")
217        (eq_attr "neon_type" "neon_int_4"))
218   "cortex_a8_neon_dp")
219
220 ;; Instructions using this reservation read their (D|Q)m operands at N1,
221 ;; their (D|Q)n operands at N2, and produce a result at N4.
222 (define_insn_reservation "neon_int_5" 4
223   (and (eq_attr "tune" "cortexa8")
224        (eq_attr "neon_type" "neon_int_5"))
225   "cortex_a8_neon_dp")
226
227 ;; Instructions using this reservation read their source operands at N1, and
228 ;; produce a result at N4.
229 (define_insn_reservation "neon_vqneg_vqabs" 4
230   (and (eq_attr "tune" "cortexa8")
231        (eq_attr "neon_type" "neon_vqneg_vqabs"))
232   "cortex_a8_neon_dp")
233
234 ;; Instructions using this reservation produce a result at N3.
235 (define_insn_reservation "neon_vmov" 3
236   (and (eq_attr "tune" "cortexa8")
237        (eq_attr "neon_type" "neon_vmov"))
238   "cortex_a8_neon_dp")
239
240 ;; Instructions using this reservation read their (D|Q)n operands at N2,
241 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
242 ;; produce a result at N6.
243 (define_insn_reservation "neon_vaba" 6
244   (and (eq_attr "tune" "cortexa8")
245        (eq_attr "neon_type" "neon_vaba"))
246   "cortex_a8_neon_dp")
247
248 ;; Instructions using this reservation read their (D|Q)n operands at N2,
249 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
250 ;; produce a result at N6 on cycle 2.
251 (define_insn_reservation "neon_vaba_qqq" 7
252   (and (eq_attr "tune" "cortexa8")
253        (eq_attr "neon_type" "neon_vaba_qqq"))
254   "cortex_a8_neon_dp_2")
255
256 ;; Instructions using this reservation read their (D|Q)m operands at N1,
257 ;; their (D|Q)d operands at N3, and produce a result at N6.
258 (define_insn_reservation "neon_vsma" 6
259   (and (eq_attr "tune" "cortexa8")
260        (eq_attr "neon_type" "neon_vsma"))
261   "cortex_a8_neon_dp")
262
263 ;; Instructions using this reservation read their source operands at N2, and
264 ;; produce a result at N6.
265 (define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
266   (and (eq_attr "tune" "cortexa8")
267        (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
268   "cortex_a8_neon_dp")
269
270 ;; Instructions using this reservation read their source operands at N2, and
271 ;; produce a result at N6 on cycle 2.
272 (define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7
273   (and (eq_attr "tune" "cortexa8")
274        (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
275   "cortex_a8_neon_dp_2")
276
277 ;; Instructions using this reservation read their (D|Q)n operands at N2,
278 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
279 (define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
280   (and (eq_attr "tune" "cortexa8")
281        (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
282   "cortex_a8_neon_dp_2")
283
284 ;; Instructions using this reservation read their (D|Q)n operands at N2,
285 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
286 ;; produce a result at N6.
287 (define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
288   (and (eq_attr "tune" "cortexa8")
289        (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
290   "cortex_a8_neon_dp")
291
292 ;; Instructions using this reservation read their (D|Q)n operands at N2,
293 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
294 ;; produce a result at N6 on cycle 2.
295 (define_insn_reservation "neon_mla_qqq_8_16" 7
296   (and (eq_attr "tune" "cortexa8")
297        (eq_attr "neon_type" "neon_mla_qqq_8_16"))
298   "cortex_a8_neon_dp_2")
299
300 ;; Instructions using this reservation read their (D|Q)n operands at N2,
301 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
302 ;; produce a result at N6 on cycle 2.
303 (define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
304   (and (eq_attr "tune" "cortexa8")
305        (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
306   "cortex_a8_neon_dp_2")
307
308 ;; Instructions using this reservation read their (D|Q)n operands at N2,
309 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
310 ;; produce a result at N6 on cycle 4.
311 (define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9
312   (and (eq_attr "tune" "cortexa8")
313        (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
314   "cortex_a8_neon_dp_4")
315
316 ;; Instructions using this reservation read their (D|Q)n operands at N2,
317 ;; their (D|Q)m operands at N1, and produce a result at N6.
318 (define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6
319   (and (eq_attr "tune" "cortexa8")
320        (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
321   "cortex_a8_neon_dp")
322
323 ;; Instructions using this reservation read their (D|Q)n operands at N2,
324 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
325 (define_insn_reservation "neon_mul_qqd_32_scalar" 9
326   (and (eq_attr "tune" "cortexa8")
327        (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
328   "cortex_a8_neon_dp_4")
329
330 ;; Instructions using this reservation read their (D|Q)n operands at N2,
331 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
332 ;; produce a result at N6.
333 (define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
334   (and (eq_attr "tune" "cortexa8")
335        (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
336   "cortex_a8_neon_dp")
337
338 ;; Instructions using this reservation read their source operands at N1, and
339 ;; produce a result at N3.
340 (define_insn_reservation "neon_shift_1" 3
341   (and (eq_attr "tune" "cortexa8")
342        (eq_attr "neon_type" "neon_shift_1"))
343   "cortex_a8_neon_dp")
344
345 ;; Instructions using this reservation read their source operands at N1, and
346 ;; produce a result at N4.
347 (define_insn_reservation "neon_shift_2" 4
348   (and (eq_attr "tune" "cortexa8")
349        (eq_attr "neon_type" "neon_shift_2"))
350   "cortex_a8_neon_dp")
351
352 ;; Instructions using this reservation read their source operands at N1, and
353 ;; produce a result at N3 on cycle 2.
354 (define_insn_reservation "neon_shift_3" 4
355   (and (eq_attr "tune" "cortexa8")
356        (eq_attr "neon_type" "neon_shift_3"))
357   "cortex_a8_neon_dp_2")
358
359 ;; Instructions using this reservation read their source operands at N1, and
360 ;; produce a result at N1.
361 (define_insn_reservation "neon_vshl_ddd" 1
362   (and (eq_attr "tune" "cortexa8")
363        (eq_attr "neon_type" "neon_vshl_ddd"))
364   "cortex_a8_neon_dp")
365
366 ;; Instructions using this reservation read their source operands at N1, and
367 ;; produce a result at N4 on cycle 2.
368 (define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5
369   (and (eq_attr "tune" "cortexa8")
370        (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
371   "cortex_a8_neon_dp_2")
372
373 ;; Instructions using this reservation read their (D|Q)m operands at N1,
374 ;; their (D|Q)d operands at N3, and produce a result at N6.
375 (define_insn_reservation "neon_vsra_vrsra" 6
376   (and (eq_attr "tune" "cortexa8")
377        (eq_attr "neon_type" "neon_vsra_vrsra"))
378   "cortex_a8_neon_dp")
379
380 ;; Instructions using this reservation read their source operands at N2, and
381 ;; produce a result at N5.
382 (define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5
383   (and (eq_attr "tune" "cortexa8")
384        (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
385   "cortex_a8_neon_fadd")
386
387 ;; Instructions using this reservation read their source operands at N2, and
388 ;; produce a result at N5 on cycle 2.
389 (define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6
390   (and (eq_attr "tune" "cortexa8")
391        (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
392   "cortex_a8_neon_fadd_2")
393
394 ;; Instructions using this reservation read their source operands at N1, and
395 ;; produce a result at N5.
396 (define_insn_reservation "neon_fp_vsum" 5
397   (and (eq_attr "tune" "cortexa8")
398        (eq_attr "neon_type" "neon_fp_vsum"))
399   "cortex_a8_neon_fadd")
400
401 ;; Instructions using this reservation read their (D|Q)n operands at N2,
402 ;; their (D|Q)m operands at N1, and produce a result at N5.
403 (define_insn_reservation "neon_fp_vmul_ddd" 5
404   (and (eq_attr "tune" "cortexa8")
405        (eq_attr "neon_type" "neon_fp_vmul_ddd"))
406   "cortex_a8_neon_dp")
407
408 ;; Instructions using this reservation read their (D|Q)n operands at N2,
409 ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
410 (define_insn_reservation "neon_fp_vmul_qqd" 6
411   (and (eq_attr "tune" "cortexa8")
412        (eq_attr "neon_type" "neon_fp_vmul_qqd"))
413   "cortex_a8_neon_dp_2")
414
415 ;; Instructions using this reservation read their (D|Q)n operands at N2,
416 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
417 ;; produce a result at N9.
418 (define_insn_reservation "neon_fp_vmla_ddd" 9
419   (and (eq_attr "tune" "cortexa8")
420        (eq_attr "neon_type" "neon_fp_vmla_ddd"))
421   "cortex_a8_neon_fmul_then_fadd")
422
423 ;; Instructions using this reservation read their (D|Q)n operands at N2,
424 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
425 ;; produce a result at N9 on cycle 2.
426 (define_insn_reservation "neon_fp_vmla_qqq" 10
427   (and (eq_attr "tune" "cortexa8")
428        (eq_attr "neon_type" "neon_fp_vmla_qqq"))
429   "cortex_a8_neon_fmul_then_fadd_2")
430
431 ;; Instructions using this reservation read their (D|Q)n operands at N2,
432 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
433 ;; produce a result at N9.
434 (define_insn_reservation "neon_fp_vmla_ddd_scalar" 9
435   (and (eq_attr "tune" "cortexa8")
436        (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
437   "cortex_a8_neon_fmul_then_fadd")
438
439 ;; Instructions using this reservation read their (D|Q)n operands at N2,
440 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
441 ;; produce a result at N9 on cycle 2.
442 (define_insn_reservation "neon_fp_vmla_qqq_scalar" 10
443   (and (eq_attr "tune" "cortexa8")
444        (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
445   "cortex_a8_neon_fmul_then_fadd_2")
446
447 ;; Instructions using this reservation read their source operands at N2, and
448 ;; produce a result at N9.
449 (define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9
450   (and (eq_attr "tune" "cortexa8")
451        (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
452   "cortex_a8_neon_fmul_then_fadd")
453
454 ;; Instructions using this reservation read their source operands at N2, and
455 ;; produce a result at N9 on cycle 2.
456 (define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10
457   (and (eq_attr "tune" "cortexa8")
458        (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
459   "cortex_a8_neon_fmul_then_fadd_2")
460
461 ;; Instructions using this reservation read their source operands at N1, and
462 ;; produce a result at N2.
463 (define_insn_reservation "neon_bp_simple" 2
464   (and (eq_attr "tune" "cortexa8")
465        (eq_attr "neon_type" "neon_bp_simple"))
466   "cortex_a8_neon_perm")
467
468 ;; Instructions using this reservation read their source operands at N1, and
469 ;; produce a result at N2 on cycle 2.
470 (define_insn_reservation "neon_bp_2cycle" 3
471   (and (eq_attr "tune" "cortexa8")
472        (eq_attr "neon_type" "neon_bp_2cycle"))
473   "cortex_a8_neon_perm_2")
474
475 ;; Instructions using this reservation read their source operands at N1, and
476 ;; produce a result at N2 on cycle 3.
477 (define_insn_reservation "neon_bp_3cycle" 4
478   (and (eq_attr "tune" "cortexa8")
479        (eq_attr "neon_type" "neon_bp_3cycle"))
480   "cortex_a8_neon_perm_3")
481
482 ;; Instructions using this reservation produce a result at N1.
483 (define_insn_reservation "neon_ldr" 1
484   (and (eq_attr "tune" "cortexa8")
485        (eq_attr "neon_type" "neon_ldr"))
486   "cortex_a8_neon_ls")
487
488 ;; Instructions using this reservation read their source operands at N1.
489 (define_insn_reservation "neon_str" 0
490   (and (eq_attr "tune" "cortexa8")
491        (eq_attr "neon_type" "neon_str"))
492   "cortex_a8_neon_ls")
493
494 ;; Instructions using this reservation produce a result at N1 on cycle 2.
495 (define_insn_reservation "neon_vld1_1_2_regs" 2
496   (and (eq_attr "tune" "cortexa8")
497        (eq_attr "neon_type" "neon_vld1_1_2_regs"))
498   "cortex_a8_neon_ls_2")
499
500 ;; Instructions using this reservation produce a result at N1 on cycle 3.
501 (define_insn_reservation "neon_vld1_3_4_regs" 3
502   (and (eq_attr "tune" "cortexa8")
503        (eq_attr "neon_type" "neon_vld1_3_4_regs"))
504   "cortex_a8_neon_ls_3")
505
506 ;; Instructions using this reservation produce a result at N2 on cycle 2.
507 (define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3
508   (and (eq_attr "tune" "cortexa8")
509        (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
510   "cortex_a8_neon_ls_2")
511
512 ;; Instructions using this reservation produce a result at N2 on cycle 3.
513 (define_insn_reservation "neon_vld2_4_regs" 4
514   (and (eq_attr "tune" "cortexa8")
515        (eq_attr "neon_type" "neon_vld2_4_regs"))
516   "cortex_a8_neon_ls_3")
517
518 ;; Instructions using this reservation produce a result at N2 on cycle 4.
519 (define_insn_reservation "neon_vld3_vld4" 5
520   (and (eq_attr "tune" "cortexa8")
521        (eq_attr "neon_type" "neon_vld3_vld4"))
522   "cortex_a8_neon_ls_4")
523
524 ;; Instructions using this reservation read their source operands at N1.
525 (define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0
526   (and (eq_attr "tune" "cortexa8")
527        (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
528   "cortex_a8_neon_ls_2")
529
530 ;; Instructions using this reservation read their source operands at N1.
531 (define_insn_reservation "neon_vst1_3_4_regs" 0
532   (and (eq_attr "tune" "cortexa8")
533        (eq_attr "neon_type" "neon_vst1_3_4_regs"))
534   "cortex_a8_neon_ls_3")
535
536 ;; Instructions using this reservation read their source operands at N1.
537 (define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0
538   (and (eq_attr "tune" "cortexa8")
539        (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
540   "cortex_a8_neon_ls_4")
541
542 ;; Instructions using this reservation read their source operands at N1.
543 (define_insn_reservation "neon_vst3_vst4" 0
544   (and (eq_attr "tune" "cortexa8")
545        (eq_attr "neon_type" "neon_vst3_vst4"))
546   "cortex_a8_neon_ls_4")
547
548 ;; Instructions using this reservation read their source operands at N1, and
549 ;; produce a result at N2 on cycle 3.
550 (define_insn_reservation "neon_vld1_vld2_lane" 4
551   (and (eq_attr "tune" "cortexa8")
552        (eq_attr "neon_type" "neon_vld1_vld2_lane"))
553   "cortex_a8_neon_ls_3")
554
555 ;; Instructions using this reservation read their source operands at N1, and
556 ;; produce a result at N2 on cycle 5.
557 (define_insn_reservation "neon_vld3_vld4_lane" 6
558   (and (eq_attr "tune" "cortexa8")
559        (eq_attr "neon_type" "neon_vld3_vld4_lane"))
560   "cortex_a8_neon_ls_5")
561
562 ;; Instructions using this reservation read their source operands at N1.
563 (define_insn_reservation "neon_vst1_vst2_lane" 0
564   (and (eq_attr "tune" "cortexa8")
565        (eq_attr "neon_type" "neon_vst1_vst2_lane"))
566   "cortex_a8_neon_ls_2")
567
568 ;; Instructions using this reservation read their source operands at N1.
569 (define_insn_reservation "neon_vst3_vst4_lane" 0
570   (and (eq_attr "tune" "cortexa8")
571        (eq_attr "neon_type" "neon_vst3_vst4_lane"))
572   "cortex_a8_neon_ls_3")
573
574 ;; Instructions using this reservation produce a result at N2 on cycle 2.
575 (define_insn_reservation "neon_vld3_vld4_all_lanes" 3
576   (and (eq_attr "tune" "cortexa8")
577        (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
578   "cortex_a8_neon_ls_3")
579
580 ;; Instructions using this reservation produce a result at N2.
581 (define_insn_reservation "neon_mcr" 2
582   (and (eq_attr "tune" "cortexa8")
583        (eq_attr "neon_type" "neon_mcr"))
584   "cortex_a8_neon_perm")
585
586 ;; Instructions using this reservation produce a result at N2.
587 (define_insn_reservation "neon_mcr_2_mcrr" 2
588   (and (eq_attr "tune" "cortexa8")
589        (eq_attr "neon_type" "neon_mcr_2_mcrr"))
590   "cortex_a8_neon_perm_2")
591
592 ;; Exceptions to the default latencies.
593
594 (define_bypass 1 "neon_mcr_2_mcrr"
595                "neon_int_1,\
596                neon_int_4,\
597                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
598                neon_mul_qqq_8_16_32_ddd_32,\
599                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
600                neon_mla_qqq_8_16,\
601                neon_fp_vadd_ddd_vabs_dd,\
602                neon_fp_vadd_qqq_vabs_qq,\
603                neon_fp_vmla_ddd,\
604                neon_fp_vmla_qqq,\
605                neon_fp_vrecps_vrsqrts_ddd,\
606                neon_fp_vrecps_vrsqrts_qqq")
607
608 (define_bypass 1 "neon_mcr"
609                "neon_int_1,\
610                neon_int_4,\
611                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
612                neon_mul_qqq_8_16_32_ddd_32,\
613                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
614                neon_mla_qqq_8_16,\
615                neon_fp_vadd_ddd_vabs_dd,\
616                neon_fp_vadd_qqq_vabs_qq,\
617                neon_fp_vmla_ddd,\
618                neon_fp_vmla_qqq,\
619                neon_fp_vrecps_vrsqrts_ddd,\
620                neon_fp_vrecps_vrsqrts_qqq")
621
622 (define_bypass 2 "neon_vld3_vld4_all_lanes"
623                "neon_int_1,\
624                neon_int_4,\
625                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
626                neon_mul_qqq_8_16_32_ddd_32,\
627                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
628                neon_mla_qqq_8_16,\
629                neon_fp_vadd_ddd_vabs_dd,\
630                neon_fp_vadd_qqq_vabs_qq,\
631                neon_fp_vmla_ddd,\
632                neon_fp_vmla_qqq,\
633                neon_fp_vrecps_vrsqrts_ddd,\
634                neon_fp_vrecps_vrsqrts_qqq")
635
636 (define_bypass 5 "neon_vld3_vld4_lane"
637                "neon_int_1,\
638                neon_int_4,\
639                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
640                neon_mul_qqq_8_16_32_ddd_32,\
641                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
642                neon_mla_qqq_8_16,\
643                neon_fp_vadd_ddd_vabs_dd,\
644                neon_fp_vadd_qqq_vabs_qq,\
645                neon_fp_vmla_ddd,\
646                neon_fp_vmla_qqq,\
647                neon_fp_vrecps_vrsqrts_ddd,\
648                neon_fp_vrecps_vrsqrts_qqq")
649
650 (define_bypass 3 "neon_vld1_vld2_lane"
651                "neon_int_1,\
652                neon_int_4,\
653                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
654                neon_mul_qqq_8_16_32_ddd_32,\
655                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
656                neon_mla_qqq_8_16,\
657                neon_fp_vadd_ddd_vabs_dd,\
658                neon_fp_vadd_qqq_vabs_qq,\
659                neon_fp_vmla_ddd,\
660                neon_fp_vmla_qqq,\
661                neon_fp_vrecps_vrsqrts_ddd,\
662                neon_fp_vrecps_vrsqrts_qqq")
663
664 (define_bypass 4 "neon_vld3_vld4"
665                "neon_int_1,\
666                neon_int_4,\
667                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
668                neon_mul_qqq_8_16_32_ddd_32,\
669                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
670                neon_mla_qqq_8_16,\
671                neon_fp_vadd_ddd_vabs_dd,\
672                neon_fp_vadd_qqq_vabs_qq,\
673                neon_fp_vmla_ddd,\
674                neon_fp_vmla_qqq,\
675                neon_fp_vrecps_vrsqrts_ddd,\
676                neon_fp_vrecps_vrsqrts_qqq")
677
678 (define_bypass 3 "neon_vld2_4_regs"
679                "neon_int_1,\
680                neon_int_4,\
681                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
682                neon_mul_qqq_8_16_32_ddd_32,\
683                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
684                neon_mla_qqq_8_16,\
685                neon_fp_vadd_ddd_vabs_dd,\
686                neon_fp_vadd_qqq_vabs_qq,\
687                neon_fp_vmla_ddd,\
688                neon_fp_vmla_qqq,\
689                neon_fp_vrecps_vrsqrts_ddd,\
690                neon_fp_vrecps_vrsqrts_qqq")
691
692 (define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes"
693                "neon_int_1,\
694                neon_int_4,\
695                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
696                neon_mul_qqq_8_16_32_ddd_32,\
697                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
698                neon_mla_qqq_8_16,\
699                neon_fp_vadd_ddd_vabs_dd,\
700                neon_fp_vadd_qqq_vabs_qq,\
701                neon_fp_vmla_ddd,\
702                neon_fp_vmla_qqq,\
703                neon_fp_vrecps_vrsqrts_ddd,\
704                neon_fp_vrecps_vrsqrts_qqq")
705
706 (define_bypass 2 "neon_vld1_3_4_regs"
707                "neon_int_1,\
708                neon_int_4,\
709                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
710                neon_mul_qqq_8_16_32_ddd_32,\
711                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
712                neon_mla_qqq_8_16,\
713                neon_fp_vadd_ddd_vabs_dd,\
714                neon_fp_vadd_qqq_vabs_qq,\
715                neon_fp_vmla_ddd,\
716                neon_fp_vmla_qqq,\
717                neon_fp_vrecps_vrsqrts_ddd,\
718                neon_fp_vrecps_vrsqrts_qqq")
719
720 (define_bypass 1 "neon_vld1_1_2_regs"
721                "neon_int_1,\
722                neon_int_4,\
723                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
724                neon_mul_qqq_8_16_32_ddd_32,\
725                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
726                neon_mla_qqq_8_16,\
727                neon_fp_vadd_ddd_vabs_dd,\
728                neon_fp_vadd_qqq_vabs_qq,\
729                neon_fp_vmla_ddd,\
730                neon_fp_vmla_qqq,\
731                neon_fp_vrecps_vrsqrts_ddd,\
732                neon_fp_vrecps_vrsqrts_qqq")
733
734 (define_bypass 0 "neon_ldr"
735                "neon_int_1,\
736                neon_int_4,\
737                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
738                neon_mul_qqq_8_16_32_ddd_32,\
739                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
740                neon_mla_qqq_8_16,\
741                neon_fp_vadd_ddd_vabs_dd,\
742                neon_fp_vadd_qqq_vabs_qq,\
743                neon_fp_vmla_ddd,\
744                neon_fp_vmla_qqq,\
745                neon_fp_vrecps_vrsqrts_ddd,\
746                neon_fp_vrecps_vrsqrts_qqq")
747
748 (define_bypass 3 "neon_bp_3cycle"
749                "neon_int_1,\
750                neon_int_4,\
751                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
752                neon_mul_qqq_8_16_32_ddd_32,\
753                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
754                neon_mla_qqq_8_16,\
755                neon_fp_vadd_ddd_vabs_dd,\
756                neon_fp_vadd_qqq_vabs_qq,\
757                neon_fp_vmla_ddd,\
758                neon_fp_vmla_qqq,\
759                neon_fp_vrecps_vrsqrts_ddd,\
760                neon_fp_vrecps_vrsqrts_qqq")
761
762 (define_bypass 2 "neon_bp_2cycle"
763                "neon_int_1,\
764                neon_int_4,\
765                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
766                neon_mul_qqq_8_16_32_ddd_32,\
767                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
768                neon_mla_qqq_8_16,\
769                neon_fp_vadd_ddd_vabs_dd,\
770                neon_fp_vadd_qqq_vabs_qq,\
771                neon_fp_vmla_ddd,\
772                neon_fp_vmla_qqq,\
773                neon_fp_vrecps_vrsqrts_ddd,\
774                neon_fp_vrecps_vrsqrts_qqq")
775
776 (define_bypass 1 "neon_bp_simple"
777                "neon_int_1,\
778                neon_int_4,\
779                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
780                neon_mul_qqq_8_16_32_ddd_32,\
781                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
782                neon_mla_qqq_8_16,\
783                neon_fp_vadd_ddd_vabs_dd,\
784                neon_fp_vadd_qqq_vabs_qq,\
785                neon_fp_vmla_ddd,\
786                neon_fp_vmla_qqq,\
787                neon_fp_vrecps_vrsqrts_ddd,\
788                neon_fp_vrecps_vrsqrts_qqq")
789
790 (define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq"
791                "neon_int_1,\
792                neon_int_4,\
793                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
794                neon_mul_qqq_8_16_32_ddd_32,\
795                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
796                neon_mla_qqq_8_16,\
797                neon_fp_vadd_ddd_vabs_dd,\
798                neon_fp_vadd_qqq_vabs_qq,\
799                neon_fp_vmla_ddd,\
800                neon_fp_vmla_qqq,\
801                neon_fp_vrecps_vrsqrts_ddd,\
802                neon_fp_vrecps_vrsqrts_qqq")
803
804 (define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd"
805                "neon_int_1,\
806                neon_int_4,\
807                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
808                neon_mul_qqq_8_16_32_ddd_32,\
809                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
810                neon_mla_qqq_8_16,\
811                neon_fp_vadd_ddd_vabs_dd,\
812                neon_fp_vadd_qqq_vabs_qq,\
813                neon_fp_vmla_ddd,\
814                neon_fp_vmla_qqq,\
815                neon_fp_vrecps_vrsqrts_ddd,\
816                neon_fp_vrecps_vrsqrts_qqq")
817
818 (define_bypass 9 "neon_fp_vmla_qqq_scalar"
819                "neon_int_1,\
820                neon_int_4,\
821                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
822                neon_mul_qqq_8_16_32_ddd_32,\
823                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
824                neon_mla_qqq_8_16,\
825                neon_fp_vadd_ddd_vabs_dd,\
826                neon_fp_vadd_qqq_vabs_qq,\
827                neon_fp_vmla_ddd,\
828                neon_fp_vmla_qqq,\
829                neon_fp_vrecps_vrsqrts_ddd,\
830                neon_fp_vrecps_vrsqrts_qqq")
831
832 (define_bypass 8 "neon_fp_vmla_ddd_scalar"
833                "neon_int_1,\
834                neon_int_4,\
835                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
836                neon_mul_qqq_8_16_32_ddd_32,\
837                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
838                neon_mla_qqq_8_16,\
839                neon_fp_vadd_ddd_vabs_dd,\
840                neon_fp_vadd_qqq_vabs_qq,\
841                neon_fp_vmla_ddd,\
842                neon_fp_vmla_qqq,\
843                neon_fp_vrecps_vrsqrts_ddd,\
844                neon_fp_vrecps_vrsqrts_qqq")
845
846 (define_bypass 9 "neon_fp_vmla_qqq"
847                "neon_int_1,\
848                neon_int_4,\
849                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
850                neon_mul_qqq_8_16_32_ddd_32,\
851                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
852                neon_mla_qqq_8_16,\
853                neon_fp_vadd_ddd_vabs_dd,\
854                neon_fp_vadd_qqq_vabs_qq,\
855                neon_fp_vmla_ddd,\
856                neon_fp_vmla_qqq,\
857                neon_fp_vrecps_vrsqrts_ddd,\
858                neon_fp_vrecps_vrsqrts_qqq")
859
860 (define_bypass 8 "neon_fp_vmla_ddd"
861                "neon_int_1,\
862                neon_int_4,\
863                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
864                neon_mul_qqq_8_16_32_ddd_32,\
865                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
866                neon_mla_qqq_8_16,\
867                neon_fp_vadd_ddd_vabs_dd,\
868                neon_fp_vadd_qqq_vabs_qq,\
869                neon_fp_vmla_ddd,\
870                neon_fp_vmla_qqq,\
871                neon_fp_vrecps_vrsqrts_ddd,\
872                neon_fp_vrecps_vrsqrts_qqq")
873
874 (define_bypass 5 "neon_fp_vmul_qqd"
875                "neon_int_1,\
876                neon_int_4,\
877                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
878                neon_mul_qqq_8_16_32_ddd_32,\
879                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
880                neon_mla_qqq_8_16,\
881                neon_fp_vadd_ddd_vabs_dd,\
882                neon_fp_vadd_qqq_vabs_qq,\
883                neon_fp_vmla_ddd,\
884                neon_fp_vmla_qqq,\
885                neon_fp_vrecps_vrsqrts_ddd,\
886                neon_fp_vrecps_vrsqrts_qqq")
887
888 (define_bypass 4 "neon_fp_vmul_ddd"
889                "neon_int_1,\
890                neon_int_4,\
891                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
892                neon_mul_qqq_8_16_32_ddd_32,\
893                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
894                neon_mla_qqq_8_16,\
895                neon_fp_vadd_ddd_vabs_dd,\
896                neon_fp_vadd_qqq_vabs_qq,\
897                neon_fp_vmla_ddd,\
898                neon_fp_vmla_qqq,\
899                neon_fp_vrecps_vrsqrts_ddd,\
900                neon_fp_vrecps_vrsqrts_qqq")
901
902 (define_bypass 4 "neon_fp_vsum"
903                "neon_int_1,\
904                neon_int_4,\
905                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
906                neon_mul_qqq_8_16_32_ddd_32,\
907                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
908                neon_mla_qqq_8_16,\
909                neon_fp_vadd_ddd_vabs_dd,\
910                neon_fp_vadd_qqq_vabs_qq,\
911                neon_fp_vmla_ddd,\
912                neon_fp_vmla_qqq,\
913                neon_fp_vrecps_vrsqrts_ddd,\
914                neon_fp_vrecps_vrsqrts_qqq")
915
916 (define_bypass 5 "neon_fp_vadd_qqq_vabs_qq"
917                "neon_int_1,\
918                neon_int_4,\
919                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
920                neon_mul_qqq_8_16_32_ddd_32,\
921                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
922                neon_mla_qqq_8_16,\
923                neon_fp_vadd_ddd_vabs_dd,\
924                neon_fp_vadd_qqq_vabs_qq,\
925                neon_fp_vmla_ddd,\
926                neon_fp_vmla_qqq,\
927                neon_fp_vrecps_vrsqrts_ddd,\
928                neon_fp_vrecps_vrsqrts_qqq")
929
930 (define_bypass 4 "neon_fp_vadd_ddd_vabs_dd"
931                "neon_int_1,\
932                neon_int_4,\
933                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
934                neon_mul_qqq_8_16_32_ddd_32,\
935                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
936                neon_mla_qqq_8_16,\
937                neon_fp_vadd_ddd_vabs_dd,\
938                neon_fp_vadd_qqq_vabs_qq,\
939                neon_fp_vmla_ddd,\
940                neon_fp_vmla_qqq,\
941                neon_fp_vrecps_vrsqrts_ddd,\
942                neon_fp_vrecps_vrsqrts_qqq")
943
944 (define_bypass 5 "neon_vsra_vrsra"
945                "neon_int_1,\
946                neon_int_4,\
947                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
948                neon_mul_qqq_8_16_32_ddd_32,\
949                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
950                neon_mla_qqq_8_16,\
951                neon_fp_vadd_ddd_vabs_dd,\
952                neon_fp_vadd_qqq_vabs_qq,\
953                neon_fp_vmla_ddd,\
954                neon_fp_vmla_qqq,\
955                neon_fp_vrecps_vrsqrts_ddd,\
956                neon_fp_vrecps_vrsqrts_qqq")
957
958 (define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq"
959                "neon_int_1,\
960                neon_int_4,\
961                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
962                neon_mul_qqq_8_16_32_ddd_32,\
963                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
964                neon_mla_qqq_8_16,\
965                neon_fp_vadd_ddd_vabs_dd,\
966                neon_fp_vadd_qqq_vabs_qq,\
967                neon_fp_vmla_ddd,\
968                neon_fp_vmla_qqq,\
969                neon_fp_vrecps_vrsqrts_ddd,\
970                neon_fp_vrecps_vrsqrts_qqq")
971
972 (define_bypass 0 "neon_vshl_ddd"
973                "neon_int_1,\
974                neon_int_4,\
975                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
976                neon_mul_qqq_8_16_32_ddd_32,\
977                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
978                neon_mla_qqq_8_16,\
979                neon_fp_vadd_ddd_vabs_dd,\
980                neon_fp_vadd_qqq_vabs_qq,\
981                neon_fp_vmla_ddd,\
982                neon_fp_vmla_qqq,\
983                neon_fp_vrecps_vrsqrts_ddd,\
984                neon_fp_vrecps_vrsqrts_qqq")
985
986 (define_bypass 3 "neon_shift_3"
987                "neon_int_1,\
988                neon_int_4,\
989                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
990                neon_mul_qqq_8_16_32_ddd_32,\
991                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
992                neon_mla_qqq_8_16,\
993                neon_fp_vadd_ddd_vabs_dd,\
994                neon_fp_vadd_qqq_vabs_qq,\
995                neon_fp_vmla_ddd,\
996                neon_fp_vmla_qqq,\
997                neon_fp_vrecps_vrsqrts_ddd,\
998                neon_fp_vrecps_vrsqrts_qqq")
999
1000 (define_bypass 3 "neon_shift_2"
1001                "neon_int_1,\
1002                neon_int_4,\
1003                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1004                neon_mul_qqq_8_16_32_ddd_32,\
1005                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1006                neon_mla_qqq_8_16,\
1007                neon_fp_vadd_ddd_vabs_dd,\
1008                neon_fp_vadd_qqq_vabs_qq,\
1009                neon_fp_vmla_ddd,\
1010                neon_fp_vmla_qqq,\
1011                neon_fp_vrecps_vrsqrts_ddd,\
1012                neon_fp_vrecps_vrsqrts_qqq")
1013
1014 (define_bypass 2 "neon_shift_1"
1015                "neon_int_1,\
1016                neon_int_4,\
1017                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1018                neon_mul_qqq_8_16_32_ddd_32,\
1019                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1020                neon_mla_qqq_8_16,\
1021                neon_fp_vadd_ddd_vabs_dd,\
1022                neon_fp_vadd_qqq_vabs_qq,\
1023                neon_fp_vmla_ddd,\
1024                neon_fp_vmla_qqq,\
1025                neon_fp_vrecps_vrsqrts_ddd,\
1026                neon_fp_vrecps_vrsqrts_qqq")
1027
1028 (define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
1029                "neon_int_1,\
1030                neon_int_4,\
1031                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1032                neon_mul_qqq_8_16_32_ddd_32,\
1033                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1034                neon_mla_qqq_8_16,\
1035                neon_fp_vadd_ddd_vabs_dd,\
1036                neon_fp_vadd_qqq_vabs_qq,\
1037                neon_fp_vmla_ddd,\
1038                neon_fp_vmla_qqq,\
1039                neon_fp_vrecps_vrsqrts_ddd,\
1040                neon_fp_vrecps_vrsqrts_qqq")
1041
1042 (define_bypass 8 "neon_mul_qqd_32_scalar"
1043                "neon_int_1,\
1044                neon_int_4,\
1045                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1046                neon_mul_qqq_8_16_32_ddd_32,\
1047                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1048                neon_mla_qqq_8_16,\
1049                neon_fp_vadd_ddd_vabs_dd,\
1050                neon_fp_vadd_qqq_vabs_qq,\
1051                neon_fp_vmla_ddd,\
1052                neon_fp_vmla_qqq,\
1053                neon_fp_vrecps_vrsqrts_ddd,\
1054                neon_fp_vrecps_vrsqrts_qqq")
1055
1056 (define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar"
1057                "neon_int_1,\
1058                neon_int_4,\
1059                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1060                neon_mul_qqq_8_16_32_ddd_32,\
1061                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1062                neon_mla_qqq_8_16,\
1063                neon_fp_vadd_ddd_vabs_dd,\
1064                neon_fp_vadd_qqq_vabs_qq,\
1065                neon_fp_vmla_ddd,\
1066                neon_fp_vmla_qqq,\
1067                neon_fp_vrecps_vrsqrts_ddd,\
1068                neon_fp_vrecps_vrsqrts_qqq")
1069
1070 (define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar"
1071                "neon_int_1,\
1072                neon_int_4,\
1073                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1074                neon_mul_qqq_8_16_32_ddd_32,\
1075                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1076                neon_mla_qqq_8_16,\
1077                neon_fp_vadd_ddd_vabs_dd,\
1078                neon_fp_vadd_qqq_vabs_qq,\
1079                neon_fp_vmla_ddd,\
1080                neon_fp_vmla_qqq,\
1081                neon_fp_vrecps_vrsqrts_ddd,\
1082                neon_fp_vrecps_vrsqrts_qqq")
1083
1084 (define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
1085                "neon_int_1,\
1086                neon_int_4,\
1087                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1088                neon_mul_qqq_8_16_32_ddd_32,\
1089                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1090                neon_mla_qqq_8_16,\
1091                neon_fp_vadd_ddd_vabs_dd,\
1092                neon_fp_vadd_qqq_vabs_qq,\
1093                neon_fp_vmla_ddd,\
1094                neon_fp_vmla_qqq,\
1095                neon_fp_vrecps_vrsqrts_ddd,\
1096                neon_fp_vrecps_vrsqrts_qqq")
1097
1098 (define_bypass 6 "neon_mla_qqq_8_16"
1099                "neon_int_1,\
1100                neon_int_4,\
1101                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1102                neon_mul_qqq_8_16_32_ddd_32,\
1103                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1104                neon_mla_qqq_8_16,\
1105                neon_fp_vadd_ddd_vabs_dd,\
1106                neon_fp_vadd_qqq_vabs_qq,\
1107                neon_fp_vmla_ddd,\
1108                neon_fp_vmla_qqq,\
1109                neon_fp_vrecps_vrsqrts_ddd,\
1110                neon_fp_vrecps_vrsqrts_qqq")
1111
1112 (define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
1113                "neon_int_1,\
1114                neon_int_4,\
1115                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1116                neon_mul_qqq_8_16_32_ddd_32,\
1117                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1118                neon_mla_qqq_8_16,\
1119                neon_fp_vadd_ddd_vabs_dd,\
1120                neon_fp_vadd_qqq_vabs_qq,\
1121                neon_fp_vmla_ddd,\
1122                neon_fp_vmla_qqq,\
1123                neon_fp_vrecps_vrsqrts_ddd,\
1124                neon_fp_vrecps_vrsqrts_qqq")
1125
1126 (define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
1127                "neon_int_1,\
1128                neon_int_4,\
1129                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1130                neon_mul_qqq_8_16_32_ddd_32,\
1131                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1132                neon_mla_qqq_8_16,\
1133                neon_fp_vadd_ddd_vabs_dd,\
1134                neon_fp_vadd_qqq_vabs_qq,\
1135                neon_fp_vmla_ddd,\
1136                neon_fp_vmla_qqq,\
1137                neon_fp_vrecps_vrsqrts_ddd,\
1138                neon_fp_vrecps_vrsqrts_qqq")
1139
1140 (define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32"
1141                "neon_int_1,\
1142                neon_int_4,\
1143                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1144                neon_mul_qqq_8_16_32_ddd_32,\
1145                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1146                neon_mla_qqq_8_16,\
1147                neon_fp_vadd_ddd_vabs_dd,\
1148                neon_fp_vadd_qqq_vabs_qq,\
1149                neon_fp_vmla_ddd,\
1150                neon_fp_vmla_qqq,\
1151                neon_fp_vrecps_vrsqrts_ddd,\
1152                neon_fp_vrecps_vrsqrts_qqq")
1153
1154 (define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
1155                "neon_int_1,\
1156                neon_int_4,\
1157                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1158                neon_mul_qqq_8_16_32_ddd_32,\
1159                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1160                neon_mla_qqq_8_16,\
1161                neon_fp_vadd_ddd_vabs_dd,\
1162                neon_fp_vadd_qqq_vabs_qq,\
1163                neon_fp_vmla_ddd,\
1164                neon_fp_vmla_qqq,\
1165                neon_fp_vrecps_vrsqrts_ddd,\
1166                neon_fp_vrecps_vrsqrts_qqq")
1167
1168 (define_bypass 5 "neon_vsma"
1169                "neon_int_1,\
1170                neon_int_4,\
1171                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1172                neon_mul_qqq_8_16_32_ddd_32,\
1173                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1174                neon_mla_qqq_8_16,\
1175                neon_fp_vadd_ddd_vabs_dd,\
1176                neon_fp_vadd_qqq_vabs_qq,\
1177                neon_fp_vmla_ddd,\
1178                neon_fp_vmla_qqq,\
1179                neon_fp_vrecps_vrsqrts_ddd,\
1180                neon_fp_vrecps_vrsqrts_qqq")
1181
1182 (define_bypass 6 "neon_vaba_qqq"
1183                "neon_int_1,\
1184                neon_int_4,\
1185                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1186                neon_mul_qqq_8_16_32_ddd_32,\
1187                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1188                neon_mla_qqq_8_16,\
1189                neon_fp_vadd_ddd_vabs_dd,\
1190                neon_fp_vadd_qqq_vabs_qq,\
1191                neon_fp_vmla_ddd,\
1192                neon_fp_vmla_qqq,\
1193                neon_fp_vrecps_vrsqrts_ddd,\
1194                neon_fp_vrecps_vrsqrts_qqq")
1195
1196 (define_bypass 5 "neon_vaba"
1197                "neon_int_1,\
1198                neon_int_4,\
1199                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1200                neon_mul_qqq_8_16_32_ddd_32,\
1201                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1202                neon_mla_qqq_8_16,\
1203                neon_fp_vadd_ddd_vabs_dd,\
1204                neon_fp_vadd_qqq_vabs_qq,\
1205                neon_fp_vmla_ddd,\
1206                neon_fp_vmla_qqq,\
1207                neon_fp_vrecps_vrsqrts_ddd,\
1208                neon_fp_vrecps_vrsqrts_qqq")
1209
1210 (define_bypass 2 "neon_vmov"
1211                "neon_int_1,\
1212                neon_int_4,\
1213                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1214                neon_mul_qqq_8_16_32_ddd_32,\
1215                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1216                neon_mla_qqq_8_16,\
1217                neon_fp_vadd_ddd_vabs_dd,\
1218                neon_fp_vadd_qqq_vabs_qq,\
1219                neon_fp_vmla_ddd,\
1220                neon_fp_vmla_qqq,\
1221                neon_fp_vrecps_vrsqrts_ddd,\
1222                neon_fp_vrecps_vrsqrts_qqq")
1223
1224 (define_bypass 3 "neon_vqneg_vqabs"
1225                "neon_int_1,\
1226                neon_int_4,\
1227                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1228                neon_mul_qqq_8_16_32_ddd_32,\
1229                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1230                neon_mla_qqq_8_16,\
1231                neon_fp_vadd_ddd_vabs_dd,\
1232                neon_fp_vadd_qqq_vabs_qq,\
1233                neon_fp_vmla_ddd,\
1234                neon_fp_vmla_qqq,\
1235                neon_fp_vrecps_vrsqrts_ddd,\
1236                neon_fp_vrecps_vrsqrts_qqq")
1237
1238 (define_bypass 3 "neon_int_5"
1239                "neon_int_1,\
1240                neon_int_4,\
1241                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1242                neon_mul_qqq_8_16_32_ddd_32,\
1243                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1244                neon_mla_qqq_8_16,\
1245                neon_fp_vadd_ddd_vabs_dd,\
1246                neon_fp_vadd_qqq_vabs_qq,\
1247                neon_fp_vmla_ddd,\
1248                neon_fp_vmla_qqq,\
1249                neon_fp_vrecps_vrsqrts_ddd,\
1250                neon_fp_vrecps_vrsqrts_qqq")
1251
1252 (define_bypass 3 "neon_int_4"
1253                "neon_int_1,\
1254                neon_int_4,\
1255                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1256                neon_mul_qqq_8_16_32_ddd_32,\
1257                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1258                neon_mla_qqq_8_16,\
1259                neon_fp_vadd_ddd_vabs_dd,\
1260                neon_fp_vadd_qqq_vabs_qq,\
1261                neon_fp_vmla_ddd,\
1262                neon_fp_vmla_qqq,\
1263                neon_fp_vrecps_vrsqrts_ddd,\
1264                neon_fp_vrecps_vrsqrts_qqq")
1265
1266 (define_bypass 2 "neon_int_3"
1267                "neon_int_1,\
1268                neon_int_4,\
1269                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1270                neon_mul_qqq_8_16_32_ddd_32,\
1271                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1272                neon_mla_qqq_8_16,\
1273                neon_fp_vadd_ddd_vabs_dd,\
1274                neon_fp_vadd_qqq_vabs_qq,\
1275                neon_fp_vmla_ddd,\
1276                neon_fp_vmla_qqq,\
1277                neon_fp_vrecps_vrsqrts_ddd,\
1278                neon_fp_vrecps_vrsqrts_qqq")
1279
1280 (define_bypass 2 "neon_int_2"
1281                "neon_int_1,\
1282                neon_int_4,\
1283                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1284                neon_mul_qqq_8_16_32_ddd_32,\
1285                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1286                neon_mla_qqq_8_16,\
1287                neon_fp_vadd_ddd_vabs_dd,\
1288                neon_fp_vadd_qqq_vabs_qq,\
1289                neon_fp_vmla_ddd,\
1290                neon_fp_vmla_qqq,\
1291                neon_fp_vrecps_vrsqrts_ddd,\
1292                neon_fp_vrecps_vrsqrts_qqq")
1293
1294 (define_bypass 2 "neon_int_1"
1295                "neon_int_1,\
1296                neon_int_4,\
1297                neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1298                neon_mul_qqq_8_16_32_ddd_32,\
1299                neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1300                neon_mla_qqq_8_16,\
1301                neon_fp_vadd_ddd_vabs_dd,\
1302                neon_fp_vadd_qqq_vabs_qq,\
1303                neon_fp_vmla_ddd,\
1304                neon_fp_vmla_qqq,\
1305                neon_fp_vrecps_vrsqrts_ddd,\
1306                neon_fp_vrecps_vrsqrts_qqq")
1307