1 ;; Constraint definitions for ARM and Thumb
2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ;; The following register constraints have been used:
23 ;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
24 ;; - in Thumb state: h, k, b
25 ;; - in both states: l, c
26 ;; In ARM state, 'l' is an alias for 'r'
28 ;; The following normal constraints have been used:
29 ;; in ARM/Thumb-2 state: G, H, I, J, K, L, M
30 ;; in Thumb-1 state: I, J, K, L, M, N, O
32 ;; The following multi-letter normal constraints have been used:
33 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv
35 ;; The following memory constraints have been used:
36 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us
40 (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
41 "Legacy FPA registers @code{f0}-@code{f7}.")
43 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
44 "The VFP registers @code{s0}-@code{s31}.")
46 (define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
47 "The Cirrus Maverick co-processor registers.")
49 (define_register_constraint "w"
50 "TARGET_32BIT ? (TARGET_VFP3 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
51 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
53 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
54 "The VFP registers @code{d0}-@code{d7}.")
56 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
57 "The Intel iWMMX co-processor registers.")
59 (define_register_constraint "z"
60 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
61 "The Intel iWMMX GR registers.")
63 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
64 "In Thumb state the core registers @code{r0}-@code{r7}.")
66 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
67 "In Thumb state the core registers @code{r8}-@code{r15}.")
69 (define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS"
71 Thumb only. The stack register.")
73 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
75 Thumb only. The union of the low registers and the stack register.")
77 (define_register_constraint "c" "CC_REG"
78 "@internal The condition code register.")
80 (define_constraint "I"
81 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
82 Data Processing instruction. In Thumb-1 state a constant in the range
84 (and (match_code "const_int")
85 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
86 : ival >= 0 && ival <= 255")))
88 (define_constraint "J"
89 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
90 state a constant in the range @minus{}255-@minus{}1."
91 (and (match_code "const_int")
92 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
93 : (ival >= -255 && ival <= -1)")))
95 (define_constraint "K"
96 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
97 inverted. In Thumb-1 state a constant that satisfies the @code{I}
98 constraint multiplied by any power of 2."
99 (and (match_code "const_int")
100 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
101 : thumb_shiftable_const (ival)")))
103 (define_constraint "L"
104 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
105 negated. In Thumb-1 state a constant in the range @minus{}7-7."
106 (and (match_code "const_int")
107 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
108 : (ival >= -7 && ival <= 7)")))
110 ;; The ARM state version is internal...
111 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
113 (define_constraint "M"
114 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
115 (and (match_code "const_int")
116 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
117 || ((ival & (ival - 1)) == 0))
118 : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
120 (define_constraint "N"
121 "In ARM/Thumb-2 state a constant suitable for a MOVW instruction.
122 In Thumb-1 state a constant in the range 0-31."
123 (and (match_code "const_int")
124 (match_test "TARGET_32BIT ? arm_arch_thumb2 && ((ival & 0xffff0000) == 0)
125 : (ival >= 0 && ival <= 31)")))
127 (define_constraint "O"
128 "In Thumb-1 state a constant that is a multiple of 4 in the range
130 (and (match_code "const_int")
131 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
132 && ((ival & 3) == 0)")))
134 (define_constraint "G"
135 "In ARM/Thumb-2 state a valid FPA immediate constant."
136 (and (match_code "const_double")
137 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
139 (define_constraint "H"
140 "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
141 (and (match_code "const_double")
142 (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
144 (define_constraint "Da"
146 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
147 be generated with two Data Processing insns."
148 (and (match_code "const_double,const_int,const_vector")
149 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
151 (define_constraint "Db"
153 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
154 be generated with three Data Processing insns."
155 (and (match_code "const_double,const_int,const_vector")
156 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
158 (define_constraint "Dc"
160 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
161 be generated with four Data Processing insns. This pattern is disabled
162 if optimizing for space or when we have load-delay slots to fill."
163 (and (match_code "const_double,const_int,const_vector")
164 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
165 && !(optimize_size || arm_ld_sched)")))
167 (define_constraint "Dn"
169 In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
170 immediate instruction."
171 (and (match_code "const_vector")
172 (match_test "TARGET_32BIT
173 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
175 (define_constraint "Dl"
177 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
179 (and (match_code "const_vector")
180 (match_test "TARGET_32BIT
181 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
183 (define_constraint "DL"
185 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
187 (and (match_code "const_vector")
188 (match_test "TARGET_32BIT
189 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
191 (define_constraint "Dv"
193 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
194 or fconstd instruction."
195 (and (match_code "const_double")
196 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
198 (define_memory_constraint "Ut"
200 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
201 types wider than TImode."
202 (and (match_code "mem")
203 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
205 (define_memory_constraint "Uv"
207 In ARM/Thumb-2 state a valid VFP load/store address."
208 (and (match_code "mem")
209 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
211 (define_memory_constraint "Uy"
213 In ARM/Thumb-2 state a valid iWMMX load/store address."
214 (and (match_code "mem")
215 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
217 (define_memory_constraint "Un"
219 In ARM/Thumb-2 state a valid address for Neon element and structure
220 load/store instructions."
221 (and (match_code "mem")
222 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)")))
224 (define_memory_constraint "Us"
226 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
227 quad-word values in four ARM registers."
228 (and (match_code "mem")
229 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)")))
231 (define_memory_constraint "Uq"
233 In ARM state an address valid in ldrsb instructions."
234 (and (match_code "mem")
235 (match_test "TARGET_ARM
236 && arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
239 (define_memory_constraint "Q"
241 In ARM/Thumb-2 state an address that is a single base register."
242 (and (match_code "mem")
243 (match_test "REG_P (XEXP (op, 0))")))
245 ;; We used to have constraint letters for S and R in ARM state, but
246 ;; all uses of these now appear to have been removed.
248 ;; Additionally, we used to have a Q constraint in Thumb state, but
249 ;; this wasn't really a valid memory constraint. Again, all uses of
250 ;; this now seem to have been removed.