1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
68 /* Add a define for interworking. \
69 Needed when building libgcc.a. */ \
70 if (arm_cpp_interwork) \
71 builtin_define ("__THUMB_INTERWORK__"); \
73 builtin_assert ("cpu=arm"); \
74 builtin_assert ("machine=arm"); \
76 builtin_define (arm_arch_name); \
77 if (arm_arch_cirrus) \
78 builtin_define ("__MAVERICK__"); \
79 if (arm_arch_xscale) \
80 builtin_define ("__XSCALE__"); \
81 if (arm_arch_iwmmxt) \
82 builtin_define ("__IWMMXT__"); \
83 if (TARGET_AAPCS_BASED) \
84 builtin_define ("__ARM_EABI__"); \
87 /* The various ARM cores. */
90 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
92 #include "arm-cores.def"
94 /* Used to indicate that no processor has been specified. */
100 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
102 #include "arm-cores.def"
107 /* The processor for which instructions should be scheduled. */
108 extern enum processor_type arm_tune;
110 typedef enum arm_cond_code
112 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
113 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
117 extern arm_cc arm_current_cc;
119 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
121 extern int arm_target_label;
122 extern int arm_ccfsm_state;
123 extern GTY(()) rtx arm_target_insn;
124 /* Define the information needed to generate branch insns. This is
125 stored from the compare operation. */
126 extern GTY(()) rtx arm_compare_op0;
127 extern GTY(()) rtx arm_compare_op1;
128 /* The label of the current constant pool. */
129 extern rtx pool_vector_label;
130 /* Set to 1 when a return insn is output, this means that the epilogue
132 extern int return_used_this_function;
133 /* Used to produce AOF syntax assembler. */
134 extern GTY(()) rtx aof_pic_label;
136 /* Just in case configure has failed to define anything. */
137 #ifndef TARGET_CPU_DEFAULT
138 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
143 #define CPP_SPEC "%(subtarget_cpp_spec) \
144 %{msoft-float:%{mhard-float: \
145 %e-msoft-float and -mhard_float may not be used together}} \
146 %{mbig-endian:%{mlittle-endian: \
147 %e-mbig-endian and -mlittle-endian may not be used together}}"
153 /* This macro defines names of additional specifications to put in the specs
154 that can be used in various specifications like CC1_SPEC. Its definition
155 is an initializer with a subgrouping for each command option.
157 Each subgrouping contains a string constant, that defines the
158 specification name, and a string constant that used by the GCC driver
161 Do not define this macro if it does not need to do anything. */
162 #define EXTRA_SPECS \
163 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
164 SUBTARGET_EXTRA_SPECS
166 #ifndef SUBTARGET_EXTRA_SPECS
167 #define SUBTARGET_EXTRA_SPECS
170 #ifndef SUBTARGET_CPP_SPEC
171 #define SUBTARGET_CPP_SPEC ""
174 /* Run-time Target Specification. */
175 #ifndef TARGET_VERSION
176 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
179 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
180 /* Use hardware floating point instructions. */
181 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
182 /* Use hardware floating point calling convention. */
183 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
184 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
185 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
186 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
187 #define TARGET_IWMMXT (arm_arch_iwmmxt)
188 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
189 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
190 #define TARGET_ARM (! TARGET_THUMB)
191 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
192 #define TARGET_BACKTRACE (leaf_function_p () \
193 ? TARGET_TPCS_LEAF_FRAME \
195 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
196 #define TARGET_AAPCS_BASED \
197 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
199 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
200 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
202 /* Only 16-bit thumb code. */
203 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
204 /* Arm or Thumb-2 32-bit code. */
205 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
206 /* 32-bit Thumb-2 code. */
207 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
209 /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
210 Neon automatically enables VFPv3 too. */
211 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
212 && (arm_fpu_arch == FPUTYPE_VFP3))
214 /* "DSP" multiply instructions, eg. SMULxy. */
215 #define TARGET_DSP_MULTIPLY \
216 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
217 /* Integer SIMD instructions, and extend-accumulate instructions. */
218 #define TARGET_INT_SIMD \
219 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
221 /* We could use unified syntax for arm mode, but for now we just use it
223 #define TARGET_UNIFIED_ASM TARGET_THUMB2
226 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
227 then TARGET_AAPCS_BASED must be true -- but the converse does not
228 hold. TARGET_BPABI implies the use of the BPABI runtime library,
229 etc., in addition to just the AAPCS calling conventions. */
231 #define TARGET_BPABI false
234 /* Support for a compile-time default CPU, et cetera. The rules are:
235 --with-arch is ignored if -march or -mcpu are specified.
236 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
238 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
240 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
242 --with-fpu is ignored if -mfpu is specified.
243 --with-abi is ignored is -mabi is specified. */
244 #define OPTION_DEFAULT_SPECS \
245 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
246 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
247 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
249 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
250 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
251 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
252 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
254 /* Which floating point model to use. */
257 ARM_FP_MODEL_UNKNOWN,
258 /* FPA model (Hardware or software). */
260 /* Cirrus Maverick floating point model. */
261 ARM_FP_MODEL_MAVERICK,
262 /* VFP floating point model. */
266 extern enum arm_fp_model arm_fp_model;
268 /* Which floating point hardware is available. Also update
269 fp_model_for_fpu in arm.c when adding entries to this list. */
272 /* No FP hardware. */
274 /* Full FPA support. */
276 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
278 /* Emulated FPA hardware, Issue 3 emulator. */
280 /* Cirrus Maverick floating point co-processor. */
288 /* Recast the floating point class to be the floating point attribute. */
289 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
291 /* What type of floating point to tune for */
292 extern enum fputype arm_fpu_tune;
294 /* What type of floating point instructions are available */
295 extern enum fputype arm_fpu_arch;
300 ARM_FLOAT_ABI_SOFTFP,
304 extern enum float_abi_type arm_float_abi;
306 #ifndef TARGET_DEFAULT_FLOAT_ABI
307 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
310 /* Which ABI to use. */
320 extern enum arm_abi_type arm_abi;
322 #ifndef ARM_DEFAULT_ABI
323 #define ARM_DEFAULT_ABI ARM_ABI_APCS
326 /* Which thread pointer access sequence to use. */
333 extern enum arm_tp_type target_thread_pointer;
335 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
336 extern int arm_arch3m;
338 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
339 extern int arm_arch4;
341 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
342 extern int arm_arch4t;
344 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
345 extern int arm_arch5;
347 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
348 extern int arm_arch5e;
350 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
351 extern int arm_arch6;
353 /* Nonzero if instructions not present in the 'M' profile can be used. */
354 extern int arm_arch_notm;
356 /* Nonzero if this chip can benefit from load scheduling. */
357 extern int arm_ld_sched;
359 /* Nonzero if generating thumb code. */
360 extern int thumb_code;
362 /* Nonzero if this chip is a StrongARM. */
363 extern int arm_tune_strongarm;
365 /* Nonzero if this chip is a Cirrus variant. */
366 extern int arm_arch_cirrus;
368 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
369 extern int arm_arch_iwmmxt;
371 /* Nonzero if this chip is an XScale. */
372 extern int arm_arch_xscale;
374 /* Nonzero if tuning for XScale. */
375 extern int arm_tune_xscale;
377 /* Nonzero if tuning for stores via the write buffer. */
378 extern int arm_tune_wbuf;
380 /* Nonzero if we should define __THUMB_INTERWORK__ in the
382 XXX This is a bit of a hack, it's intended to help work around
383 problems in GLD which doesn't understand that armv5t code is
384 interworking clean. */
385 extern int arm_cpp_interwork;
387 /* Nonzero if chip supports Thumb 2. */
388 extern int arm_arch_thumb2;
390 /* Nonzero if chip supports integer division instruction. */
391 extern int arm_arch_hwdiv;
393 #ifndef TARGET_DEFAULT
394 #define TARGET_DEFAULT (MASK_APCS_FRAME)
397 /* The frame pointer register used in gcc has nothing to do with debugging;
398 that is controlled by the APCS-FRAME option. */
399 #define CAN_DEBUG_WITHOUT_FP
401 #define OVERRIDE_OPTIONS arm_override_options ()
403 /* Nonzero if PIC code requires explicit qualifiers to generate
404 PLT and GOT relocs rather than the assembler doing so implicitly.
405 Subtargets can override these if required. */
406 #ifndef NEED_GOT_RELOC
407 #define NEED_GOT_RELOC 0
409 #ifndef NEED_PLT_RELOC
410 #define NEED_PLT_RELOC 0
413 /* Nonzero if we need to refer to the GOT with a PC-relative
414 offset. In other words, generate
416 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
420 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
422 The default is true, which matches NetBSD. Subtargets can
423 override this if required. */
428 /* Target machine storage Layout. */
431 /* Define this macro if it is advisable to hold scalars in registers
432 in a wider mode than that declared by the program. In such cases,
433 the value is constrained to be within the bounds of the declared
434 type, but kept valid in the wider mode. The signedness of the
435 extension may differ from that of the type. */
437 /* It is far faster to zero extend chars than to sign extend them */
439 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
440 if (GET_MODE_CLASS (MODE) == MODE_INT \
441 && GET_MODE_SIZE (MODE) < 4) \
443 if (MODE == QImode) \
445 else if (MODE == HImode) \
450 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
451 if ((GET_MODE_CLASS (MODE) == MODE_INT \
452 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
453 && GET_MODE_SIZE (MODE) < 4) \
456 /* Define this if most significant bit is lowest numbered
457 in instructions that operate on numbered bit-fields. */
458 #define BITS_BIG_ENDIAN 0
460 /* Define this if most significant byte of a word is the lowest numbered.
461 Most ARM processors are run in little endian mode, so that is the default.
462 If you want to have it run-time selectable, change the definition in a
463 cover file to be TARGET_BIG_ENDIAN. */
464 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
466 /* Define this if most significant word of a multiword number is the lowest
468 This is always false, even when in big-endian mode. */
469 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
471 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
472 on processor pre-defineds when compiling libgcc2.c. */
473 #if defined(__ARMEB__) && !defined(__ARMWEL__)
474 #define LIBGCC2_WORDS_BIG_ENDIAN 1
476 #define LIBGCC2_WORDS_BIG_ENDIAN 0
479 /* Define this if most significant word of doubles is the lowest numbered.
480 The rules are different based on whether or not we use FPA-format,
481 VFP-format or some other floating point co-processor's format doubles. */
482 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
484 #define UNITS_PER_WORD 4
486 /* True if natural alignment is used for doubleword types. */
487 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
489 #define DOUBLEWORD_ALIGNMENT 64
491 #define PARM_BOUNDARY 32
493 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
495 #define PREFERRED_STACK_BOUNDARY \
496 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
498 #define FUNCTION_BOUNDARY 32
500 /* The lowest bit is used to indicate Thumb-mode functions, so the
501 vbit must go into the delta field of pointers to member
503 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
505 #define EMPTY_FIELD_BOUNDARY 32
507 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
509 /* XXX Blah -- this macro is used directly by libobjc. Since it
510 supports no vector modes, cut out the complexity and fall back
511 on BIGGEST_FIELD_ALIGNMENT. */
512 #ifdef IN_TARGET_LIBS
513 #define BIGGEST_FIELD_ALIGNMENT 64
516 /* Make strings word-aligned so strcpy from constants will be faster. */
517 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
519 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
520 ((TREE_CODE (EXP) == STRING_CST \
522 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
523 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
525 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
526 value set in previous versions of this toolchain was 8, which produces more
527 compact structures. The command line option -mstructure_size_boundary=<n>
528 can be used to change this value. For compatibility with the ARM SDK
529 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
530 0020D) page 2-20 says "Structures are aligned on word boundaries".
531 The AAPCS specifies a value of 8. */
532 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
533 extern int arm_structure_size_boundary;
535 /* This is the value used to initialize arm_structure_size_boundary. If a
536 particular arm target wants to change the default value it should change
537 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
538 for an example of this. */
539 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
540 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
543 /* Nonzero if move instructions will actually fail to work
544 when given unaligned data. */
545 #define STRICT_ALIGNMENT 1
547 /* wchar_t is unsigned under the AAPCS. */
549 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
551 #define WCHAR_TYPE_SIZE BITS_PER_WORD
555 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
559 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
562 /* AAPCS requires that structure alignment is affected by bitfields. */
563 #ifndef PCC_BITFIELD_TYPE_MATTERS
564 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
568 /* Standard register usage. */
570 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
571 (S - saved over call).
573 r0 * argument word/integer result
576 r4-r8 S register variable
577 r9 S (rfp) register variable (real frame pointer)
579 r10 F S (sl) stack limit (used by -mapcs-stack-check)
580 r11 F S (fp) argument pointer
581 r12 (ip) temp workspace
582 r13 F S (sp) lower end of current stack frame
583 r14 (lr) link address/workspace
584 r15 F (pc) program counter
586 f0 floating point result
587 f1-f3 floating point scratch
589 f4-f7 S floating point variable
591 cc This is NOT a real register, but is used internally
592 to represent things that use or set the condition
594 sfp This isn't either. It is used during rtl generation
595 since the offset between the frame pointer and the
596 auto's isn't known until after register allocation.
597 afp Nor this, we only need this because of non-local
598 goto. Without it fp appears to be used and the
599 elimination code won't get rid of sfp. It tracks
600 fp exactly at all times.
602 *: See CONDITIONAL_REGISTER_USAGE */
605 mvf0 Cirrus floating point result
606 mvf1-mvf3 Cirrus floating point scratch
607 mvf4-mvf15 S Cirrus floating point variable. */
609 /* s0-s15 VFP scratch (aka d0-d7).
610 s16-s31 S VFP variable (aka d8-d15).
611 vfpcc Not a real register. Represents the VFP condition
614 /* The stack backtrace structure is as follows:
615 fp points to here: | save code pointer | [fp]
616 | return link value | [fp, #-4]
617 | return sp value | [fp, #-8]
618 | return fp value | [fp, #-12]
619 [| saved r10 value |]
630 [| saved f7 value |] three words
631 [| saved f6 value |] three words
632 [| saved f5 value |] three words
633 [| saved f4 value |] three words
634 r0-r3 are not normally saved in a C function. */
636 /* 1 for registers that have pervasive standard uses
637 and are not available for the register allocator. */
638 #define FIXED_REGISTERS \
660 /* 1 for registers not available across function calls.
661 These must include the FIXED_REGISTERS and also any
662 registers that can be used without being saved.
663 The latter must include the registers where values are returned
664 and the register where structure-value addresses are passed.
665 Aside from that, you can include as many other registers as you like.
666 The CC is not preserved over function calls on the ARM 6, so it is
667 easier to assume this for all. SFP is preserved, since FP is. */
668 #define CALL_USED_REGISTERS \
690 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
691 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
694 #define CONDITIONAL_REGISTER_USAGE \
698 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
700 for (regno = FIRST_FPA_REGNUM; \
701 regno <= LAST_FPA_REGNUM; ++regno) \
702 fixed_regs[regno] = call_used_regs[regno] = 1; \
705 if (TARGET_THUMB && optimize_size) \
707 /* When optimizing for size, it's better not to use \
708 the HI regs, because of the overhead of stacking \
710 /* ??? Is this still true for thumb2? */ \
711 for (regno = FIRST_HI_REGNUM; \
712 regno <= LAST_HI_REGNUM; ++regno) \
713 fixed_regs[regno] = call_used_regs[regno] = 1; \
716 /* The link register can be clobbered by any branch insn, \
717 but we have no way to track that at present, so mark \
718 it as unavailable. */ \
720 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
722 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
724 if (TARGET_MAVERICK) \
726 for (regno = FIRST_FPA_REGNUM; \
727 regno <= LAST_FPA_REGNUM; ++ regno) \
728 fixed_regs[regno] = call_used_regs[regno] = 1; \
729 for (regno = FIRST_CIRRUS_FP_REGNUM; \
730 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
732 fixed_regs[regno] = 0; \
733 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
738 /* VFPv3 registers are disabled when earlier VFP \
739 versions are selected due to the definition of \
740 LAST_VFP_REGNUM. */ \
741 for (regno = FIRST_VFP_REGNUM; \
742 regno <= LAST_VFP_REGNUM; ++ regno) \
744 fixed_regs[regno] = 0; \
745 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
746 || regno >= FIRST_VFP_REGNUM + 32; \
751 if (TARGET_REALLY_IWMMXT) \
753 regno = FIRST_IWMMXT_GR_REGNUM; \
754 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
755 and wCG1 as call-preserved registers. The 2002/11/21 \
756 revision changed this so that all wCG registers are \
757 scratch registers. */ \
758 for (regno = FIRST_IWMMXT_GR_REGNUM; \
759 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
760 fixed_regs[regno] = 0; \
761 /* The XScale ABI has wR0 - wR9 as scratch registers, \
762 the rest as call-preserved registers. */ \
763 for (regno = FIRST_IWMMXT_REGNUM; \
764 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
766 fixed_regs[regno] = 0; \
767 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
771 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
773 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
774 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
776 else if (TARGET_APCS_STACK) \
778 fixed_regs[10] = 1; \
779 call_used_regs[10] = 1; \
781 /* -mcaller-super-interworking reserves r11 for calls to \
782 _interwork_r11_call_via_rN(). Making the register global \
783 is an easy way of ensuring that it remains valid for all \
785 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
786 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
788 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
789 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
790 if (TARGET_CALLER_INTERWORKING) \
791 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
793 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
796 /* These are a couple of extensions to the formats accepted
798 %@ prints out ASM_COMMENT_START
799 %r prints out REGISTER_PREFIX reg_names[arg] */
800 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
802 fputs (ASM_COMMENT_START, FILE); \
806 fputs (REGISTER_PREFIX, FILE); \
807 fputs (reg_names [va_arg (ARGS, int)], FILE); \
810 /* Round X up to the nearest word. */
811 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
813 /* Convert fron bytes to ints. */
814 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
816 /* The number of (integer) registers required to hold a quantity of type MODE.
817 Also used for VFP registers. */
818 #define ARM_NUM_REGS(MODE) \
819 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
821 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
822 #define ARM_NUM_REGS2(MODE, TYPE) \
823 ARM_NUM_INTS ((MODE) == BLKmode ? \
824 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
826 /* The number of (integer) argument register available. */
827 #define NUM_ARG_REGS 4
829 /* Return the register number of the N'th (integer) argument. */
830 #define ARG_REGISTER(N) (N - 1)
832 /* Specify the registers used for certain standard purposes.
833 The values of these macros are register numbers. */
835 /* The number of the last argument register. */
836 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
838 /* The numbers of the Thumb register ranges. */
839 #define FIRST_LO_REGNUM 0
840 #define LAST_LO_REGNUM 7
841 #define FIRST_HI_REGNUM 8
842 #define LAST_HI_REGNUM 11
844 #ifndef TARGET_UNWIND_INFO
845 /* We use sjlj exceptions for backwards compatibility. */
846 #define MUST_USE_SJLJ_EXCEPTIONS 1
849 /* We can generate DWARF2 Unwind info, even though we don't use it. */
850 #define DWARF2_UNWIND_INFO 1
852 /* Use r0 and r1 to pass exception handling information. */
853 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
855 /* The register that holds the return address in exception handlers. */
856 #define ARM_EH_STACKADJ_REGNUM 2
857 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
859 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
860 as an invisible last argument (possible since varargs don't exist in
861 Pascal), so the following is not true. */
862 #define STATIC_CHAIN_REGNUM 12
864 /* Define this to be where the real frame pointer is if it is not possible to
865 work out the offset between the frame pointer and the automatic variables
866 until after register allocation has taken place. FRAME_POINTER_REGNUM
867 should point to a special register that we will make sure is eliminated.
869 For the Thumb we have another problem. The TPCS defines the frame pointer
870 as r11, and GCC believes that it is always possible to use the frame pointer
871 as base register for addressing purposes. (See comments in
872 find_reloads_address()). But - the Thumb does not allow high registers,
873 including r11, to be used as base address registers. Hence our problem.
875 The solution used here, and in the old thumb port is to use r7 instead of
876 r11 as the hard frame pointer and to have special code to generate
877 backtrace structures on the stack (if required to do so via a command line
878 option) using r11. This is the only 'user visible' use of r11 as a frame
880 #define ARM_HARD_FRAME_POINTER_REGNUM 11
881 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
883 #define HARD_FRAME_POINTER_REGNUM \
885 ? ARM_HARD_FRAME_POINTER_REGNUM \
886 : THUMB_HARD_FRAME_POINTER_REGNUM)
888 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
890 /* Register to use for pushing function arguments. */
891 #define STACK_POINTER_REGNUM SP_REGNUM
893 /* ARM floating pointer registers. */
894 #define FIRST_FPA_REGNUM 16
895 #define LAST_FPA_REGNUM 23
896 #define IS_FPA_REGNUM(REGNUM) \
897 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
899 #define FIRST_IWMMXT_GR_REGNUM 43
900 #define LAST_IWMMXT_GR_REGNUM 46
901 #define FIRST_IWMMXT_REGNUM 47
902 #define LAST_IWMMXT_REGNUM 62
903 #define IS_IWMMXT_REGNUM(REGNUM) \
904 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
905 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
906 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
908 /* Base register for access to local variables of the function. */
909 #define FRAME_POINTER_REGNUM 25
911 /* Base register for access to arguments of the function. */
912 #define ARG_POINTER_REGNUM 26
914 #define FIRST_CIRRUS_FP_REGNUM 27
915 #define LAST_CIRRUS_FP_REGNUM 42
916 #define IS_CIRRUS_REGNUM(REGNUM) \
917 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
919 #define FIRST_VFP_REGNUM 63
920 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
921 #define LAST_VFP_REGNUM \
922 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
924 #define IS_VFP_REGNUM(REGNUM) \
925 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
927 /* VFP registers are split into two types: those defined by VFP versions < 3
928 have D registers overlaid on consecutive pairs of S registers. VFP version 3
929 defines 16 new D registers (d16-d31) which, for simplicity and correctness
930 in various parts of the backend, we implement as "fake" single-precision
931 registers (which would be S32-S63, but cannot be used in that way). The
932 following macros define these ranges of registers. */
933 #define LAST_LO_VFP_REGNUM 94
934 #define FIRST_HI_VFP_REGNUM 95
935 #define LAST_HI_VFP_REGNUM 126
937 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
938 ((REGNUM) <= LAST_LO_VFP_REGNUM)
940 /* DFmode values are only valid in even register pairs. */
941 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
942 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
944 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
945 /* + 16 Cirrus registers take us up to 43. */
946 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
947 /* VFP (VFP3) adds 32 (64) + 1 more. */
948 #define FIRST_PSEUDO_REGISTER 128
950 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
952 /* Value should be nonzero if functions must have frame pointers.
953 Zero means the frame pointer need not be set up (and parms may be accessed
954 via the stack pointer) in functions that seem suitable.
955 If we have to have a frame pointer we might as well make use of it.
956 APCS says that the frame pointer does not need to be pushed in leaf
957 functions, or simple tail call functions. */
959 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
960 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
963 #define FRAME_POINTER_REQUIRED \
964 (current_function_has_nonlocal_label \
965 || SUBTARGET_FRAME_POINTER_REQUIRED \
966 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
968 /* Return number of consecutive hard regs needed starting at reg REGNO
969 to hold something of mode MODE.
970 This is ordinarily the length in words of a value of mode MODE
971 but can be less for certain modes in special long registers.
973 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
975 #define HARD_REGNO_NREGS(REGNO, MODE) \
977 && REGNO >= FIRST_FPA_REGNUM \
978 && REGNO != FRAME_POINTER_REGNUM \
979 && REGNO != ARG_POINTER_REGNUM) \
980 && !IS_VFP_REGNUM (REGNO) \
981 ? 1 : ARM_NUM_REGS (MODE))
983 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
984 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
985 arm_hard_regno_mode_ok ((REGNO), (MODE))
987 /* Value is 1 if it is a good idea to tie two pseudo registers
988 when one has mode MODE1 and one has mode MODE2.
989 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
990 for any hard reg, then this must be 0 for correct output. */
991 #define MODES_TIEABLE_P(MODE1, MODE2) \
992 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
994 #define VALID_IWMMXT_REG_MODE(MODE) \
995 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
997 /* The order in which register should be allocated. It is good to use ip
998 since no saving is required (though calls clobber it) and it never contains
999 function parameters. It is quite good to use lr since other calls may
1000 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1001 least likely to contain a function parameter; in addition results are
1003 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1004 then D8-D15. The reason for doing this is to attempt to reduce register
1005 pressure when both single- and double-precision registers are used in a
1008 #define REG_ALLOC_ORDER \
1010 3, 2, 1, 0, 12, 14, 4, 5, \
1011 6, 7, 8, 10, 9, 11, 13, 15, \
1012 16, 17, 18, 19, 20, 21, 22, 23, \
1013 27, 28, 29, 30, 31, 32, 33, 34, \
1014 35, 36, 37, 38, 39, 40, 41, 42, \
1015 43, 44, 45, 46, 47, 48, 49, 50, \
1016 51, 52, 53, 54, 55, 56, 57, 58, \
1019 95, 96, 97, 98, 99, 100, 101, 102, \
1020 103, 104, 105, 106, 107, 108, 109, 110, \
1021 111, 112, 113, 114, 115, 116, 117, 118, \
1022 119, 120, 121, 122, 123, 124, 125, 126, \
1023 78, 77, 76, 75, 74, 73, 72, 71, \
1024 70, 69, 68, 67, 66, 65, 64, 63, \
1025 79, 80, 81, 82, 83, 84, 85, 86, \
1026 87, 88, 89, 90, 91, 92, 93, 94, \
1030 /* Interrupt functions can only use registers that have already been
1031 saved by the prologue, even if they would normally be
1033 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1034 (! IS_INTERRUPT (cfun->machine->func_type) || \
1035 df_regs_ever_live_p (DST))
1037 /* Register and constant classes. */
1039 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1040 Now that the Thumb is involved it has become more complicated. */
1063 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1065 /* Give names of register classes as strings for dump file. */
1066 #define REG_CLASS_NAMES \
1087 /* Define which registers fit in which classes.
1088 This is an initializer for a vector of HARD_REG_SET
1089 of length N_REG_CLASSES. */
1090 #define REG_CLASS_CONTENTS \
1092 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1093 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1094 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1095 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1096 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1097 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1098 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1099 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1100 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1101 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1102 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1103 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1104 { 0x0000FF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1105 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1106 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1107 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1108 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1111 /* Any of the VFP register classes. */
1112 #define IS_VFP_CLASS(X) \
1113 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1114 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1116 /* The same information, inverted:
1117 Return the class number of the smallest class containing
1118 reg number REGNO. This could be a conditional expression
1119 or could index an array. */
1120 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1122 /* FPA registers can't do subreg as all values are reformatted to internal
1123 precision. VFP registers may only be accessed in the mode they
1125 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1126 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1127 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1128 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1131 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1132 using r0-r4 for function arguments, r7 for the stack frame and don't
1133 have enough left over to do doubleword arithmetic. */
1134 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1135 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1136 || (CLASS) == CC_REG)
1138 /* The class value for index registers, and the one for base regs. */
1139 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1140 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1142 /* For the Thumb the high registers cannot be used as base registers
1143 when addressing quantities in QI or HI mode; if we don't know the
1144 mode, then we must be conservative. */
1145 #define MODE_BASE_REG_CLASS(MODE) \
1146 (TARGET_32BIT ? GENERAL_REGS : \
1147 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1149 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1150 instead of BASE_REGS. */
1151 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1153 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1154 registers explicitly used in the rtl to be used as spill registers
1155 but prevents the compiler from extending the lifetime of these
1157 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1159 /* Given an rtx X being reloaded into a reg required to be
1160 in class CLASS, return the class of reg to actually use.
1161 In general this is just CLASS, but for the Thumb core registers and
1162 immediate constants we prefer a LO_REGS class or a subset. */
1163 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1164 (TARGET_ARM ? (CLASS) : \
1165 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1166 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1168 /* Must leave BASE_REGS reloads alone */
1169 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1170 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1171 ? ((true_regnum (X) == -1 ? LO_REGS \
1172 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1176 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1177 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1178 ? ((true_regnum (X) == -1 ? LO_REGS \
1179 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1183 /* Return the register class of a scratch register needed to copy IN into
1184 or out of a register in CLASS in MODE. If it can be done directly,
1185 NO_REGS is returned. */
1186 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1187 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1188 ((TARGET_VFP && TARGET_HARD_FLOAT \
1189 && IS_VFP_CLASS (CLASS)) \
1190 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1191 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1192 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1194 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1195 ? GENERAL_REGS : NO_REGS) \
1196 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1198 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1199 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1200 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1201 ((TARGET_VFP && TARGET_HARD_FLOAT \
1202 && IS_VFP_CLASS (CLASS)) \
1203 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1204 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1205 coproc_secondary_reload_class (MODE, X, TRUE) : \
1206 /* Cannot load constants into Cirrus registers. */ \
1207 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1208 && (CLASS) == CIRRUS_REGS \
1209 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1212 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1213 && CONSTANT_P (X)) \
1215 (((MODE) == HImode && ! arm_arch4 \
1216 && (GET_CODE (X) == MEM \
1217 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1218 && true_regnum (X) == -1))) \
1219 ? GENERAL_REGS : NO_REGS) \
1220 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1222 /* Try a machine-dependent way of reloading an illegitimate address
1223 operand. If we find one, push the reload and jump to WIN. This
1224 macro is used in only one place: `find_reloads_address' in reload.c.
1226 For the ARM, we wish to handle large displacements off a base
1227 register by splitting the addend across a MOV and the mem insn.
1228 This can cut the number of reloads needed. */
1229 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1232 if (GET_CODE (X) == PLUS \
1233 && GET_CODE (XEXP (X, 0)) == REG \
1234 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1235 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1236 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1238 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1239 HOST_WIDE_INT low, high; \
1241 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1242 low = ((val & 0xf) ^ 0x8) - 0x8; \
1243 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1244 /* Need to be careful, -256 is not a valid offset. */ \
1245 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1246 else if (MODE == SImode \
1247 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1248 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1249 /* Need to be careful, -4096 is not a valid offset. */ \
1250 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1251 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1252 /* Need to be careful, -256 is not a valid offset. */ \
1253 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1254 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1255 && TARGET_HARD_FLOAT && TARGET_FPA) \
1256 /* Need to be careful, -1024 is not a valid offset. */ \
1257 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1261 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1262 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1263 - (unsigned HOST_WIDE_INT) 0x80000000); \
1264 /* Check for overflow or zero */ \
1265 if (low == 0 || high == 0 || (high + low != val)) \
1268 /* Reload the high part into a base reg; leave the low part \
1270 X = gen_rtx_PLUS (GET_MODE (X), \
1271 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1274 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1275 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1276 VOIDmode, 0, 0, OPNUM, TYPE); \
1282 /* XXX If an HImode FP+large_offset address is converted to an HImode
1283 SP+large_offset address, then reload won't know how to fix it. It sees
1284 only that SP isn't valid for HImode, and so reloads the SP into an index
1285 register, but the resulting address is still invalid because the offset
1286 is too big. We fix it here instead by reloading the entire address. */
1287 /* We could probably achieve better results by defining PROMOTE_MODE to help
1288 cope with the variances between the Thumb's signed and unsigned byte and
1289 halfword load instructions. */
1290 /* ??? This should be safe for thumb2, but we may be able to do better. */
1291 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1293 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1301 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1303 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1305 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1307 /* Return the maximum number of consecutive registers
1308 needed to represent mode MODE in a register of class CLASS.
1309 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1310 #define CLASS_MAX_NREGS(CLASS, MODE) \
1311 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1313 /* If defined, gives a class of registers that cannot be used as the
1314 operand of a SUBREG that changes the mode of the object illegally. */
1316 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1317 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1319 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1320 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1321 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1322 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1323 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1324 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1325 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1326 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1327 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1330 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1332 /* Stack layout; function entry, exit and calling. */
1334 /* Define this if pushing a word on the stack
1335 makes the stack pointer a smaller address. */
1336 #define STACK_GROWS_DOWNWARD 1
1338 /* Define this to nonzero if the nominal address of the stack frame
1339 is at the high-address end of the local variables;
1340 that is, each additional local variable allocated
1341 goes at a more negative offset in the frame. */
1342 #define FRAME_GROWS_DOWNWARD 1
1344 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1345 When present, it is one word in size, and sits at the top of the frame,
1346 between the soft frame pointer and either r7 or r11.
1348 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1349 and only then if some outgoing arguments are passed on the stack. It would
1350 be tempting to also check whether the stack arguments are passed by indirect
1351 calls, but there seems to be no reason in principle why a post-reload pass
1352 couldn't convert a direct call into an indirect one. */
1353 #define CALLER_INTERWORKING_SLOT_SIZE \
1354 (TARGET_CALLER_INTERWORKING \
1355 && current_function_outgoing_args_size != 0 \
1356 ? UNITS_PER_WORD : 0)
1358 /* Offset within stack frame to start allocating local variables at.
1359 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1360 first local allocated. Otherwise, it is the offset to the BEGINNING
1361 of the first local allocated. */
1362 #define STARTING_FRAME_OFFSET 0
1364 /* If we generate an insn to push BYTES bytes,
1365 this says how many the stack pointer really advances by. */
1366 /* The push insns do not do this rounding implicitly.
1367 So don't define this. */
1368 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1370 /* Define this if the maximum size of all the outgoing args is to be
1371 accumulated and pushed during the prologue. The amount can be
1372 found in the variable current_function_outgoing_args_size. */
1373 #define ACCUMULATE_OUTGOING_ARGS 1
1375 /* Offset of first parameter from the argument pointer register value. */
1376 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1378 /* Value is the number of byte of arguments automatically
1379 popped when returning from a subroutine call.
1380 FUNDECL is the declaration node of the function (as a tree),
1381 FUNTYPE is the data type of the function (as a tree),
1382 or for a library call it is an identifier node for the subroutine name.
1383 SIZE is the number of bytes of arguments passed on the stack.
1385 On the ARM, the caller does not pop any of its arguments that were passed
1387 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1389 /* Define how to find the value returned by a library function
1390 assuming the value has mode MODE. */
1391 #define LIBCALL_VALUE(MODE) \
1392 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1393 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1394 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1395 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1396 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1397 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1398 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1399 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1400 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1402 /* Define how to find the value returned by a function.
1403 VALTYPE is the data type of the value (as a tree).
1404 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1405 otherwise, FUNC is 0. */
1406 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1407 arm_function_value (VALTYPE, FUNC);
1409 /* 1 if N is a possible register number for a function value.
1410 On the ARM, only r0 and f0 can return results. */
1411 /* On a Cirrus chip, mvf0 can return results. */
1412 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1413 ((REGNO) == ARG_REGISTER (1) \
1414 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1415 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1416 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1417 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1418 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1420 /* Amount of memory needed for an untyped call to save all possible return
1422 #define APPLY_RESULT_SIZE arm_apply_result_size()
1424 /* How large values are returned */
1425 /* A C expression which can inhibit the returning of certain function values
1426 in registers, based on the type of value. */
1427 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1429 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1430 values must be in memory. On the ARM, they need only do so if larger
1431 than a word, or if they contain elements offset from zero in the struct. */
1432 #define DEFAULT_PCC_STRUCT_RETURN 0
1434 /* These bits describe the different types of function supported
1435 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1436 normal function and an interworked function, for example. Knowing the
1437 type of a function is important for determining its prologue and
1439 Note value 7 is currently unassigned. Also note that the interrupt
1440 function types all have bit 2 set, so that they can be tested for easily.
1441 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1442 machine_function structure is initialized (to zero) func_type will
1443 default to unknown. This will force the first use of arm_current_func_type
1444 to call arm_compute_func_type. */
1445 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1446 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1447 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1448 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1449 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1450 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1452 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1454 /* In addition functions can have several type modifiers,
1455 outlined by these bit masks: */
1456 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1457 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1458 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1459 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1460 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1462 /* Some macros to test these flags. */
1463 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1464 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1465 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1466 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1467 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1468 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1471 /* Structure used to hold the function stack frame layout. Offsets are
1472 relative to the stack pointer on function entry. Positive offsets are
1473 in the direction of stack growth.
1474 Only soft_frame is used in thumb mode. */
1476 typedef struct arm_stack_offsets GTY(())
1478 int saved_args; /* ARG_POINTER_REGNUM. */
1479 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1481 int soft_frame; /* FRAME_POINTER_REGNUM. */
1482 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1483 int outgoing_args; /* STACK_POINTER_REGNUM. */
1487 /* A C structure for machine-specific, per-function data.
1488 This is added to the cfun structure. */
1489 typedef struct machine_function GTY(())
1491 /* Additional stack adjustment in __builtin_eh_throw. */
1492 rtx eh_epilogue_sp_ofs;
1493 /* Records if LR has to be saved for far jumps. */
1495 /* Records if ARG_POINTER was ever live. */
1496 int arg_pointer_live;
1497 /* Records if the save of LR has been eliminated. */
1498 int lr_save_eliminated;
1499 /* The size of the stack frame. Only valid after reload. */
1500 arm_stack_offsets stack_offsets;
1501 /* Records the type of the current function. */
1502 unsigned long func_type;
1503 /* Record if the function has a variable argument list. */
1504 int uses_anonymous_args;
1505 /* Records if sibcalls are blocked because an argument
1506 register is needed to preserve stack alignment. */
1507 int sibcall_blocked;
1508 /* The PIC register for this function. This might be a pseudo. */
1510 /* Labels for per-function Thumb call-via stubs. One per potential calling
1511 register. We can never call via LR or PC. We can call via SP if a
1512 trampoline happens to be on the top of the stack. */
1517 /* As in the machine_function, a global set of call-via labels, for code
1518 that is in text_section. */
1519 extern GTY(()) rtx thumb_call_via_label[14];
1521 /* A C type for declaring a variable that is used as the first argument of
1522 `FUNCTION_ARG' and other related values. For some target machines, the
1523 type `int' suffices and can hold the number of bytes of argument so far. */
1526 /* This is the number of registers of arguments scanned so far. */
1528 /* This is the number of iWMMXt register arguments scanned so far. */
1535 /* Define where to put the arguments to a function.
1536 Value is zero to push the argument on the stack,
1537 or a hard register in which to store the argument.
1539 MODE is the argument's machine mode.
1540 TYPE is the data type of the argument (as a tree).
1541 This is null for libcalls where that information may
1543 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1544 the preceding args and about the function being called.
1545 NAMED is nonzero if this argument is a named parameter
1546 (otherwise it is an extra parameter matching an ellipsis).
1548 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1549 other arguments are passed on the stack. If (NAMED == 0) (which happens
1550 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1551 defined), say it is passed in the stack (function_prologue will
1552 indeed make it pass in the stack if necessary). */
1553 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1554 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1556 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1557 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1559 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1560 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1562 /* For AAPCS, padding should never be below the argument. For other ABIs,
1563 * mimic the default. */
1564 #define PAD_VARARGS_DOWN \
1565 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1567 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1568 for a call to a function whose data type is FNTYPE.
1569 For a library call, FNTYPE is 0.
1570 On the ARM, the offset starts at 0. */
1571 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1572 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1574 /* Update the data in CUM to advance over an argument
1575 of mode MODE and data type TYPE.
1576 (TYPE is null for libcalls where that information may not be available.) */
1577 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1579 if (arm_vector_mode_supported_p (MODE) \
1580 && (CUM).named_count > (CUM).nargs \
1581 && TARGET_IWMMXT_ABI) \
1582 (CUM).iwmmxt_nregs += 1; \
1584 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1586 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1587 argument with the specified mode and type. If it is not defined,
1588 `PARM_BOUNDARY' is used for all arguments. */
1589 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1590 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1591 ? DOUBLEWORD_ALIGNMENT \
1594 /* 1 if N is a possible register number for function argument passing.
1595 On the ARM, r0-r3 are used to pass args. */
1596 #define FUNCTION_ARG_REGNO_P(REGNO) \
1597 (IN_RANGE ((REGNO), 0, 3) \
1598 || (TARGET_IWMMXT_ABI \
1599 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1602 /* If your target environment doesn't prefix user functions with an
1603 underscore, you may wish to re-define this to prevent any conflicts.
1604 e.g. AOF may prefix mcount with an underscore. */
1605 #ifndef ARM_MCOUNT_NAME
1606 #define ARM_MCOUNT_NAME "*mcount"
1609 /* Call the function profiler with a given profile label. The Acorn
1610 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1611 On the ARM the full profile code will look like:
1620 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1621 will output the .text section.
1623 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1624 ``prof'' doesn't seem to mind about this!
1626 Note - this version of the code is designed to work in both ARM and
1628 #ifndef ARM_FUNCTION_PROFILER
1629 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1634 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1635 IP_REGNUM, LR_REGNUM); \
1636 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1637 fputc ('\n', STREAM); \
1638 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1639 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1640 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1644 #ifdef THUMB_FUNCTION_PROFILER
1645 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1647 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1649 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1651 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1652 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1655 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1656 the stack pointer does not matter. The value is tested only in
1657 functions that have frame pointers.
1658 No definition is equivalent to always zero.
1660 On the ARM, the function epilogue recovers the stack pointer from the
1662 #define EXIT_IGNORE_STACK 1
1664 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1666 /* Determine if the epilogue should be output as RTL.
1667 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1668 /* This is disabled for Thumb-2 because it will confuse the
1669 conditional insn counter. */
1670 #define USE_RETURN_INSN(ISCOND) \
1671 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1673 /* Definitions for register eliminations.
1675 This is an array of structures. Each structure initializes one pair
1676 of eliminable registers. The "from" register number is given first,
1677 followed by "to". Eliminations of the same "from" register are listed
1678 in order of preference.
1680 We have two registers that can be eliminated on the ARM. First, the
1681 arg pointer register can often be eliminated in favor of the stack
1682 pointer register. Secondly, the pseudo frame pointer register can always
1683 be eliminated; it is replaced with either the stack or the real frame
1684 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1685 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1687 #define ELIMINABLE_REGS \
1688 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1689 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1690 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1691 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1692 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1693 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1694 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1696 /* Given FROM and TO register numbers, say whether this elimination is
1697 allowed. Frame pointer elimination is automatically handled.
1699 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1700 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1701 pointer, we must eliminate FRAME_POINTER_REGNUM into
1702 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1703 ARG_POINTER_REGNUM. */
1704 #define CAN_ELIMINATE(FROM, TO) \
1705 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1706 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1707 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1708 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1711 /* Define the offset between two registers, one to be eliminated, and the
1712 other its replacement, at the start of a routine. */
1713 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1715 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1717 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1719 /* Special case handling of the location of arguments passed on the stack. */
1720 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1722 /* Initialize data used by insn expanders. This is called from insn_emit,
1723 once for every function before code is generated. */
1724 #define INIT_EXPANDERS arm_init_expanders ()
1726 /* Output assembler code for a block containing the constant parts
1727 of a trampoline, leaving space for the variable parts.
1729 On the ARM, (if r8 is the static chain regnum, and remembering that
1730 referencing pc adds an offset of 8) the trampoline looks like:
1733 .word static chain value
1734 .word function's address
1735 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1736 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1738 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1739 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1740 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1741 PC_REGNUM, PC_REGNUM); \
1742 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1743 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1746 /* The Thumb-2 trampoline is similar to the arm implementation.
1747 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1748 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1750 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1751 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1752 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1753 PC_REGNUM, PC_REGNUM); \
1754 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1755 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1758 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1760 ASM_OUTPUT_ALIGN(FILE, 2); \
1761 fprintf (FILE, "\t.code\t16\n"); \
1762 fprintf (FILE, ".Ltrampoline_start:\n"); \
1763 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1764 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1766 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1767 STATIC_CHAIN_REGNUM); \
1768 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1770 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1772 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1774 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1775 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1778 #define TRAMPOLINE_TEMPLATE(FILE) \
1780 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1781 else if (TARGET_THUMB2) \
1782 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1784 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1786 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1788 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1791 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1792 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1795 /* Length in units of the trampoline for entering a nested function. */
1796 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1798 /* Alignment required for a trampoline in bits. */
1799 #define TRAMPOLINE_ALIGNMENT 32
1802 /* Emit RTL insns to initialize the variable parts of a trampoline.
1803 FNADDR is an RTX for the address of the function's pure code.
1804 CXT is an RTX for the static chain value for the function. */
1805 #ifndef INITIALIZE_TRAMPOLINE
1806 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1808 emit_move_insn (gen_rtx_MEM (SImode, \
1809 plus_constant (TRAMP, \
1810 TARGET_32BIT ? 8 : 12)), \
1812 emit_move_insn (gen_rtx_MEM (SImode, \
1813 plus_constant (TRAMP, \
1814 TARGET_32BIT ? 12 : 16)), \
1816 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1817 0, VOIDmode, 2, TRAMP, Pmode, \
1818 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1823 /* Addressing modes, and classification of registers for them. */
1824 #define HAVE_POST_INCREMENT 1
1825 #define HAVE_PRE_INCREMENT TARGET_32BIT
1826 #define HAVE_POST_DECREMENT TARGET_32BIT
1827 #define HAVE_PRE_DECREMENT TARGET_32BIT
1828 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1829 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1830 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1831 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1833 /* Macros to check register numbers against specific register classes. */
1835 /* These assume that REGNO is a hard or pseudo reg number.
1836 They give nonzero only if REGNO is a hard reg of the suitable class
1837 or a pseudo reg currently allocated to a suitable hard reg.
1838 Since they use reg_renumber, they are safe only once reg_renumber
1839 has been allocated, which happens in local-alloc.c. */
1840 #define TEST_REGNO(R, TEST, VALUE) \
1841 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1843 /* Don't allow the pc to be used. */
1844 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1845 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1846 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1847 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1849 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1850 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1851 || (GET_MODE_SIZE (MODE) >= 4 \
1852 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1854 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1856 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1857 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1859 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1860 For Thumb, we can not use SP + reg, so reject SP. */
1861 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1862 REGNO_OK_FOR_INDEX_P (X)
1864 /* For ARM code, we don't care about the mode, but for Thumb, the index
1865 must be suitable for use in a QImode load. */
1866 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1867 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1869 /* Maximum number of registers that can appear in a valid memory address.
1870 Shifts in addresses can't be by a register. */
1871 #define MAX_REGS_PER_ADDRESS 2
1873 /* Recognize any constant value that is a valid address. */
1874 /* XXX We can address any constant, eventually... */
1876 #ifdef AOF_ASSEMBLER
1878 #define CONSTANT_ADDRESS_P(X) \
1879 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1883 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1884 #define CONSTANT_ADDRESS_P(X) \
1885 (GET_CODE (X) == SYMBOL_REF \
1886 && (CONSTANT_POOL_ADDRESS_P (X) \
1887 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1889 #endif /* AOF_ASSEMBLER */
1891 /* Nonzero if the constant value X is a legitimate general operand.
1892 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1894 On the ARM, allow any integer (invalid ones are removed later by insn
1895 patterns), nice doubles and symbol_refs which refer to the function's
1898 When generating pic allow anything. */
1899 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1901 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1902 ( GET_CODE (X) == CONST_INT \
1903 || GET_CODE (X) == CONST_DOUBLE \
1904 || CONSTANT_ADDRESS_P (X) \
1907 #define LEGITIMATE_CONSTANT_P(X) \
1908 (!arm_tls_referenced_p (X) \
1909 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1910 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1912 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1913 #define SUBTARGET_NAME_ENCODING_LENGTHS
1916 /* This is a C fragment for the inside of a switch statement.
1917 Each case label should return the number of characters to
1918 be stripped from the start of a function's name, if that
1919 name starts with the indicated character. */
1920 #define ARM_NAME_ENCODING_LENGTHS \
1921 case '*': return 1; \
1922 SUBTARGET_NAME_ENCODING_LENGTHS
1924 /* This is how to output a reference to a user-level label named NAME.
1925 `assemble_name' uses this. */
1926 #undef ASM_OUTPUT_LABELREF
1927 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1928 arm_asm_output_labelref (FILE, NAME)
1930 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1931 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1932 if (TARGET_THUMB2) \
1933 thumb2_asm_output_opcode (STREAM);
1935 /* The EABI specifies that constructors should go in .init_array.
1936 Other targets use .ctors for compatibility. */
1937 #ifndef ARM_EABI_CTORS_SECTION_OP
1938 #define ARM_EABI_CTORS_SECTION_OP \
1939 "\t.section\t.init_array,\"aw\",%init_array"
1941 #ifndef ARM_EABI_DTORS_SECTION_OP
1942 #define ARM_EABI_DTORS_SECTION_OP \
1943 "\t.section\t.fini_array,\"aw\",%fini_array"
1945 #define ARM_CTORS_SECTION_OP \
1946 "\t.section\t.ctors,\"aw\",%progbits"
1947 #define ARM_DTORS_SECTION_OP \
1948 "\t.section\t.dtors,\"aw\",%progbits"
1950 /* Define CTORS_SECTION_ASM_OP. */
1951 #undef CTORS_SECTION_ASM_OP
1952 #undef DTORS_SECTION_ASM_OP
1954 # define CTORS_SECTION_ASM_OP \
1955 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1956 # define DTORS_SECTION_ASM_OP \
1957 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1958 #else /* !defined (IN_LIBGCC2) */
1959 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1960 so we cannot use the definition above. */
1961 # ifdef __ARM_EABI__
1962 /* The .ctors section is not part of the EABI, so we do not define
1963 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1964 from trying to use it. We do define it when doing normal
1965 compilation, as .init_array can be used instead of .ctors. */
1966 /* There is no need to emit begin or end markers when using
1967 init_array; the dynamic linker will compute the size of the
1968 array itself based on special symbols created by the static
1969 linker. However, we do need to arrange to set up
1970 exception-handling here. */
1971 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1972 # define CTOR_LIST_END /* empty */
1973 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1974 # define DTOR_LIST_END /* empty */
1975 # else /* !defined (__ARM_EABI__) */
1976 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1977 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1978 # endif /* !defined (__ARM_EABI__) */
1979 #endif /* !defined (IN_LIBCC2) */
1981 /* True if the operating system can merge entities with vague linkage
1982 (e.g., symbols in COMDAT group) during dynamic linking. */
1983 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1984 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1987 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1989 #ifdef TARGET_UNWIND_INFO
1990 #define ARM_EABI_UNWIND_TABLES \
1991 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1993 #define ARM_EABI_UNWIND_TABLES 0
1996 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1997 and check its validity for a certain class.
1998 We have two alternate definitions for each of them.
1999 The usual definition accepts all pseudo regs; the other rejects
2000 them unless they have been allocated suitable hard regs.
2001 The symbol REG_OK_STRICT causes the latter definition to be used.
2002 Thumb-2 has the same restrictions as arm. */
2003 #ifndef REG_OK_STRICT
2005 #define ARM_REG_OK_FOR_BASE_P(X) \
2006 (REGNO (X) <= LAST_ARM_REGNUM \
2007 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2008 || REGNO (X) == FRAME_POINTER_REGNUM \
2009 || REGNO (X) == ARG_POINTER_REGNUM)
2011 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2012 (REGNO (X) <= LAST_LO_REGNUM \
2013 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2014 || (GET_MODE_SIZE (MODE) >= 4 \
2015 && (REGNO (X) == STACK_POINTER_REGNUM \
2016 || (X) == hard_frame_pointer_rtx \
2017 || (X) == arg_pointer_rtx)))
2019 #define REG_STRICT_P 0
2021 #else /* REG_OK_STRICT */
2023 #define ARM_REG_OK_FOR_BASE_P(X) \
2024 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2026 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2027 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2029 #define REG_STRICT_P 1
2031 #endif /* REG_OK_STRICT */
2033 /* Now define some helpers in terms of the above. */
2035 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2037 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2038 : ARM_REG_OK_FOR_BASE_P (X))
2040 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2042 /* For 16-bit Thumb, a valid index register is anything that can be used in
2043 a byte load instruction. */
2044 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2045 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2047 /* Nonzero if X is a hard reg that can be used as an index
2048 or if it is a pseudo reg. On the Thumb, the stack pointer
2050 #define REG_OK_FOR_INDEX_P(X) \
2052 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2053 : ARM_REG_OK_FOR_INDEX_P (X))
2055 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2056 For Thumb, we can not use SP + reg, so reject SP. */
2057 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2058 REG_OK_FOR_INDEX_P (X)
2060 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2061 that is a valid memory address for an instruction.
2062 The MODE argument is the machine mode for the MEM expression
2063 that wants to use this address. */
2065 #define ARM_BASE_REGISTER_RTX_P(X) \
2066 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2068 #define ARM_INDEX_REGISTER_RTX_P(X) \
2069 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2071 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2073 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2077 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2079 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2083 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2085 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2089 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2091 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2092 else if (TARGET_THUMB2) \
2093 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2094 else /* if (TARGET_THUMB1) */ \
2095 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2098 /* Try machine-dependent ways of modifying an illegitimate address
2099 to be legitimate. If we find one, return the new, valid address. */
2100 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2102 X = arm_legitimize_address (X, OLDX, MODE); \
2105 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2106 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2110 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2112 X = thumb_legitimize_address (X, OLDX, MODE); \
2115 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2118 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2119 else if (TARGET_THUMB2) \
2120 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2122 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2124 if (memory_address_p (MODE, X)) \
2128 /* Go to LABEL if ADDR (a legitimate address expression)
2129 has an effect that depends on the machine mode it is used for. */
2130 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2132 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2133 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2137 /* Nothing helpful to do for the Thumb */
2138 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2140 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2143 /* Specify the machine mode that this machine uses
2144 for the index in the tablejump instruction. */
2145 #define CASE_VECTOR_MODE Pmode
2147 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2149 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2150 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2151 : (max >= 0x200) ? HImode \
2154 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2155 unsigned is probably best, but may break some code. */
2156 #ifndef DEFAULT_SIGNED_CHAR
2157 #define DEFAULT_SIGNED_CHAR 0
2160 /* Max number of bytes we can move from memory to memory
2161 in one reasonably fast instruction. */
2165 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2167 /* Define if operations between registers always perform the operation
2168 on the full register even if a narrower mode is specified. */
2169 #define WORD_REGISTER_OPERATIONS
2171 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2172 will either zero-extend or sign-extend. The value of this macro should
2173 be the code that says which one of the two operations is implicitly
2174 done, UNKNOWN if none. */
2175 #define LOAD_EXTEND_OP(MODE) \
2176 (TARGET_THUMB ? ZERO_EXTEND : \
2177 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2178 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2180 /* Nonzero if access to memory by bytes is slow and undesirable. */
2181 #define SLOW_BYTE_ACCESS 0
2183 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2185 /* Immediate shift counts are truncated by the output routines (or was it
2186 the assembler?). Shift counts in a register are truncated by ARM. Note
2187 that the native compiler puts too large (> 32) immediate shift counts
2188 into a register and shifts by the register, letting the ARM decide what
2189 to do instead of doing that itself. */
2190 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2191 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2192 On the arm, Y in a register is used modulo 256 for the shift. Only for
2193 rotates is modulo 32 used. */
2194 /* #define SHIFT_COUNT_TRUNCATED 1 */
2196 /* All integers have the same format so truncation is easy. */
2197 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2199 /* Calling from registers is a massive pain. */
2200 #define NO_FUNCTION_CSE 1
2202 /* The machine modes of pointers and functions */
2203 #define Pmode SImode
2204 #define FUNCTION_MODE Pmode
2206 #define ARM_FRAME_RTX(X) \
2207 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2208 || (X) == arg_pointer_rtx)
2210 /* Moves to and from memory are quite expensive */
2211 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2212 (TARGET_32BIT ? 10 : \
2213 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2214 * (CLASS == LO_REGS ? 1 : 2)))
2216 /* Try to generate sequences that don't involve branches, we can then use
2217 conditional instructions */
2218 #define BRANCH_COST \
2219 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2221 /* Position Independent Code. */
2222 /* We decide which register to use based on the compilation options and
2223 the assembler in use; this is more general than the APCS restriction of
2224 using sb (r9) all the time. */
2225 extern unsigned arm_pic_register;
2227 /* The register number of the register used to address a table of static
2228 data addresses in memory. */
2229 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2231 /* We can't directly access anything that contains a symbol,
2232 nor can we indirect via the constant pool. One exception is
2233 UNSPEC_TLS, which is always PIC. */
2234 #define LEGITIMATE_PIC_OPERAND_P(X) \
2235 (!(symbol_mentioned_p (X) \
2236 || label_mentioned_p (X) \
2237 || (GET_CODE (X) == SYMBOL_REF \
2238 && CONSTANT_POOL_ADDRESS_P (X) \
2239 && (symbol_mentioned_p (get_pool_constant (X)) \
2240 || label_mentioned_p (get_pool_constant (X))))) \
2241 || tls_mentioned_p (X))
2243 /* We need to know when we are making a constant pool; this determines
2244 whether data needs to be in the GOT or can be referenced via a GOT
2246 extern int making_const_table;
2248 /* Handle pragmas for compatibility with Intel's compilers. */
2249 #define REGISTER_TARGET_PRAGMAS() do { \
2250 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2251 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2252 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2255 /* Condition code information. */
2256 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2257 return the mode to be used for the comparison. */
2259 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2261 #define REVERSIBLE_CC_MODE(MODE) 1
2263 #define REVERSE_CONDITION(CODE,MODE) \
2264 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2265 ? reverse_condition_maybe_unordered (code) \
2266 : reverse_condition (code))
2268 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2271 if (GET_CODE (OP1) == CONST_INT \
2272 && ! (const_ok_for_arm (INTVAL (OP1)) \
2273 || (const_ok_for_arm (- INTVAL (OP1))))) \
2275 rtx const_op = OP1; \
2276 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2283 /* The arm5 clz instruction returns 32. */
2284 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2287 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2288 TARGET_THUMB2 ? "\t.thumb\n" : "")
2290 /* Output a push or a pop instruction (only used when profiling). */
2291 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2295 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2296 STACK_POINTER_REGNUM, REGNO); \
2298 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2302 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2306 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2307 STACK_POINTER_REGNUM, REGNO); \
2309 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2312 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2313 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2315 /* This is how to output a label which precedes a jumptable. Since
2316 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2317 #undef ASM_OUTPUT_CASE_LABEL
2318 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2321 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2322 ASM_OUTPUT_ALIGN (FILE, 2); \
2323 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2327 /* Make sure subsequent insns are aligned after a TBB. */
2328 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2331 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2332 ASM_OUTPUT_ALIGN (FILE, 1); \
2336 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2341 if (is_called_in_ARM_mode (DECL) \
2342 || (TARGET_THUMB1 && current_function_is_thunk)) \
2343 fprintf (STREAM, "\t.code 32\n") ; \
2344 else if (TARGET_THUMB1) \
2345 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2347 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2349 if (TARGET_POKE_FUNCTION_NAME) \
2350 arm_poke_function_name (STREAM, (char *) NAME); \
2354 /* For aliases of functions we use .thumb_set instead. */
2355 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2358 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2359 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2361 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2363 fprintf (FILE, "\t.thumb_set "); \
2364 assemble_name (FILE, LABEL1); \
2365 fprintf (FILE, ","); \
2366 assemble_name (FILE, LABEL2); \
2367 fprintf (FILE, "\n"); \
2370 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2374 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2375 /* To support -falign-* switches we need to use .p2align so
2376 that alignment directives in code sections will be padded
2377 with no-op instructions, rather than zeroes. */
2378 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2381 if ((MAX_SKIP) == 0) \
2382 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2384 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2385 (int) (LOG), (int) (MAX_SKIP)); \
2389 /* Add two bytes to the length of conditionally executed Thumb-2
2390 instructions for the IT instruction. */
2391 #define ADJUST_INSN_LENGTH(insn, length) \
2392 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2395 /* Only perform branch elimination (by making instructions conditional) if
2396 we're optimizing. For Thumb-2 check if any IT instructions need
2398 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2399 if (TARGET_ARM && optimize) \
2400 arm_final_prescan_insn (INSN); \
2401 else if (TARGET_THUMB2) \
2402 thumb2_final_prescan_insn (INSN); \
2403 else if (TARGET_THUMB1) \
2404 thumb1_final_prescan_insn (INSN)
2406 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2407 (CODE == '@' || CODE == '|' || CODE == '.' \
2408 || CODE == '(' || CODE == ')' \
2409 || (TARGET_32BIT && (CODE == '?')) \
2410 || (TARGET_THUMB2 && (CODE == '!')) \
2411 || (TARGET_THUMB && (CODE == '_')))
2413 /* Output an operand of an instruction. */
2414 #define PRINT_OPERAND(STREAM, X, CODE) \
2415 arm_print_operand (STREAM, X, CODE)
2417 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2418 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2419 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2420 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2421 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2422 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2425 /* Output the address of an operand. */
2426 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2428 int is_minus = GET_CODE (X) == MINUS; \
2430 if (GET_CODE (X) == REG) \
2431 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2432 else if (GET_CODE (X) == PLUS || is_minus) \
2434 rtx base = XEXP (X, 0); \
2435 rtx index = XEXP (X, 1); \
2436 HOST_WIDE_INT offset = 0; \
2437 if (GET_CODE (base) != REG) \
2439 /* Ensure that BASE is a register. */ \
2440 /* (one of them must be). */ \
2445 switch (GET_CODE (index)) \
2448 offset = INTVAL (index); \
2451 asm_fprintf (STREAM, "[%r, #%wd]", \
2452 REGNO (base), offset); \
2456 asm_fprintf (STREAM, "[%r, %s%r]", \
2457 REGNO (base), is_minus ? "-" : "", \
2467 asm_fprintf (STREAM, "[%r, %s%r", \
2468 REGNO (base), is_minus ? "-" : "", \
2469 REGNO (XEXP (index, 0))); \
2470 arm_print_operand (STREAM, index, 'S'); \
2471 fputs ("]", STREAM); \
2476 gcc_unreachable (); \
2479 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2480 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2482 extern enum machine_mode output_memory_reference_mode; \
2484 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2486 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2487 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2488 REGNO (XEXP (X, 0)), \
2489 GET_CODE (X) == PRE_DEC ? "-" : "", \
2490 GET_MODE_SIZE (output_memory_reference_mode)); \
2492 asm_fprintf (STREAM, "[%r], #%s%d", \
2493 REGNO (XEXP (X, 0)), \
2494 GET_CODE (X) == POST_DEC ? "-" : "", \
2495 GET_MODE_SIZE (output_memory_reference_mode)); \
2497 else if (GET_CODE (X) == PRE_MODIFY) \
2499 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2500 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2501 asm_fprintf (STREAM, "#%wd]!", \
2502 INTVAL (XEXP (XEXP (X, 1), 1))); \
2504 asm_fprintf (STREAM, "%r]!", \
2505 REGNO (XEXP (XEXP (X, 1), 1))); \
2507 else if (GET_CODE (X) == POST_MODIFY) \
2509 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2510 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2511 asm_fprintf (STREAM, "#%wd", \
2512 INTVAL (XEXP (XEXP (X, 1), 1))); \
2514 asm_fprintf (STREAM, "%r", \
2515 REGNO (XEXP (XEXP (X, 1), 1))); \
2517 else output_addr_const (STREAM, X); \
2520 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2522 if (GET_CODE (X) == REG) \
2523 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2524 else if (GET_CODE (X) == POST_INC) \
2525 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2526 else if (GET_CODE (X) == PLUS) \
2528 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2529 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2530 asm_fprintf (STREAM, "[%r, #%wd]", \
2531 REGNO (XEXP (X, 0)), \
2532 INTVAL (XEXP (X, 1))); \
2534 asm_fprintf (STREAM, "[%r, %r]", \
2535 REGNO (XEXP (X, 0)), \
2536 REGNO (XEXP (X, 1))); \
2539 output_addr_const (STREAM, X); \
2542 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2544 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2546 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2548 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2549 if (arm_output_addr_const_extra (file, x) == FALSE) \
2552 /* A C expression whose value is RTL representing the value of the return
2553 address for the frame COUNT steps up from the current frame. */
2555 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2556 arm_return_addr (COUNT, FRAME)
2558 /* Mask of the bits in the PC that contain the real return address
2559 when running in 26-bit mode. */
2560 #define RETURN_ADDR_MASK26 (0x03fffffc)
2562 /* Pick up the return address upon entry to a procedure. Used for
2563 dwarf2 unwind information. This also enables the table driven
2565 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2566 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2568 /* Used to mask out junk bits from the return address, such as
2569 processor state, interrupt status, condition codes and the like. */
2570 #define MASK_RETURN_ADDR \
2571 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2572 in 26 bit mode, the condition codes must be masked out of the \
2573 return address. This does not apply to ARM6 and later processors \
2574 when running in 32 bit mode. */ \
2575 ((arm_arch4 || TARGET_THUMB) \
2576 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2577 : arm_gen_return_addr_mask ())
2587 ARM_BUILTIN_WAVG2BR,
2588 ARM_BUILTIN_WAVG2HR,
2615 ARM_BUILTIN_TMOVMSKB,
2616 ARM_BUILTIN_TMOVMSKH,
2617 ARM_BUILTIN_TMOVMSKW,
2626 ARM_BUILTIN_WPACKHSS,
2627 ARM_BUILTIN_WPACKWSS,
2628 ARM_BUILTIN_WPACKDSS,
2629 ARM_BUILTIN_WPACKHUS,
2630 ARM_BUILTIN_WPACKWUS,
2631 ARM_BUILTIN_WPACKDUS,
2636 ARM_BUILTIN_WADDSSB,
2637 ARM_BUILTIN_WADDSSH,
2638 ARM_BUILTIN_WADDSSW,
2639 ARM_BUILTIN_WADDUSB,
2640 ARM_BUILTIN_WADDUSH,
2641 ARM_BUILTIN_WADDUSW,
2645 ARM_BUILTIN_WSUBSSB,
2646 ARM_BUILTIN_WSUBSSH,
2647 ARM_BUILTIN_WSUBSSW,
2648 ARM_BUILTIN_WSUBUSB,
2649 ARM_BUILTIN_WSUBUSH,
2650 ARM_BUILTIN_WSUBUSW,
2657 ARM_BUILTIN_WCMPEQB,
2658 ARM_BUILTIN_WCMPEQH,
2659 ARM_BUILTIN_WCMPEQW,
2660 ARM_BUILTIN_WCMPGTUB,
2661 ARM_BUILTIN_WCMPGTUH,
2662 ARM_BUILTIN_WCMPGTUW,
2663 ARM_BUILTIN_WCMPGTSB,
2664 ARM_BUILTIN_WCMPGTSH,
2665 ARM_BUILTIN_WCMPGTSW,
2667 ARM_BUILTIN_TEXTRMSB,
2668 ARM_BUILTIN_TEXTRMSH,
2669 ARM_BUILTIN_TEXTRMSW,
2670 ARM_BUILTIN_TEXTRMUB,
2671 ARM_BUILTIN_TEXTRMUH,
2672 ARM_BUILTIN_TEXTRMUW,
2722 ARM_BUILTIN_WUNPCKIHB,
2723 ARM_BUILTIN_WUNPCKIHH,
2724 ARM_BUILTIN_WUNPCKIHW,
2725 ARM_BUILTIN_WUNPCKILB,
2726 ARM_BUILTIN_WUNPCKILH,
2727 ARM_BUILTIN_WUNPCKILW,
2729 ARM_BUILTIN_WUNPCKEHSB,
2730 ARM_BUILTIN_WUNPCKEHSH,
2731 ARM_BUILTIN_WUNPCKEHSW,
2732 ARM_BUILTIN_WUNPCKEHUB,
2733 ARM_BUILTIN_WUNPCKEHUH,
2734 ARM_BUILTIN_WUNPCKEHUW,
2735 ARM_BUILTIN_WUNPCKELSB,
2736 ARM_BUILTIN_WUNPCKELSH,
2737 ARM_BUILTIN_WUNPCKELSW,
2738 ARM_BUILTIN_WUNPCKELUB,
2739 ARM_BUILTIN_WUNPCKELUH,
2740 ARM_BUILTIN_WUNPCKELUW,
2742 ARM_BUILTIN_THREAD_POINTER,
2747 /* Do not emit .note.GNU-stack by default. */
2748 #ifndef NEED_INDICATE_EXEC_STACK
2749 #define NEED_INDICATE_EXEC_STACK 0
2752 #endif /* ! GCC_ARM_H */
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