1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
39 #include "config/vxworks-dummy.h"
41 /* The architecture define. */
42 extern char arm_arch_name[];
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
53 builtin_define ("__thumb__"); \
55 builtin_define ("__thumb2__"); \
59 builtin_define ("__ARMEB__"); \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
67 builtin_define ("__ARMEL__"); \
69 builtin_define ("__THUMBEL__"); \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
76 builtin_define ("__VFP_FP__"); \
79 builtin_define ("__ARM_NEON__"); \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
97 builtin_define ("__ARM_EABI__"); \
100 /* The various ARM cores. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
107 /* Used to indicate that no processor has been specified. */
113 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
115 #include "arm-cores.def"
120 /* The processor for which instructions should be scheduled. */
121 extern enum processor_type arm_tune;
123 typedef enum arm_cond_code
125 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
126 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
130 extern arm_cc arm_current_cc;
132 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
134 extern int arm_target_label;
135 extern int arm_ccfsm_state;
136 extern GTY(()) rtx arm_target_insn;
137 /* The label of the current constant pool. */
138 extern rtx pool_vector_label;
139 /* Set to 1 when a return insn is output, this means that the epilogue
141 extern int return_used_this_function;
142 /* Callback to output language specific object attributes. */
143 extern void (*arm_lang_output_object_attributes_hook)(void);
145 /* Just in case configure has failed to define anything. */
146 #ifndef TARGET_CPU_DEFAULT
147 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
152 #define CPP_SPEC "%(subtarget_cpp_spec) \
153 %{msoft-float:%{mhard-float: \
154 %e-msoft-float and -mhard_float may not be used together}} \
155 %{mbig-endian:%{mlittle-endian: \
156 %e-mbig-endian and -mlittle-endian may not be used together}}"
162 /* This macro defines names of additional specifications to put in the specs
163 that can be used in various specifications like CC1_SPEC. Its definition
164 is an initializer with a subgrouping for each command option.
166 Each subgrouping contains a string constant, that defines the
167 specification name, and a string constant that used by the GCC driver
170 Do not define this macro if it does not need to do anything. */
171 #define EXTRA_SPECS \
172 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
173 SUBTARGET_EXTRA_SPECS
175 #ifndef SUBTARGET_EXTRA_SPECS
176 #define SUBTARGET_EXTRA_SPECS
179 #ifndef SUBTARGET_CPP_SPEC
180 #define SUBTARGET_CPP_SPEC ""
183 /* Run-time Target Specification. */
184 #ifndef TARGET_VERSION
185 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
188 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
189 /* Use hardware floating point instructions. */
190 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
191 /* Use hardware floating point calling convention. */
192 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
193 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
194 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
195 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
196 #define TARGET_IWMMXT (arm_arch_iwmmxt)
197 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
198 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
199 #define TARGET_ARM (! TARGET_THUMB)
200 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
201 #define TARGET_BACKTRACE (leaf_function_p () \
202 ? TARGET_TPCS_LEAF_FRAME \
204 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
205 #define TARGET_AAPCS_BASED \
206 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
208 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
209 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
211 /* Only 16-bit thumb code. */
212 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
213 /* Arm or Thumb-2 32-bit code. */
214 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
215 /* 32-bit Thumb-2 code. */
216 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
218 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
219 /* FPA emulator without LFM. */
220 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
222 /* The following two macros concern the ability to execute coprocessor
223 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
224 only ever tested when we know we are generating for VFP hardware; we need
225 to be more careful with TARGET_NEON as noted below. */
227 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
228 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
230 /* FPU supports VFPv3 instructions. */
231 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
233 /* FPU only supports VFP single-precision instructions. */
234 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
236 /* FPU supports VFP double-precision instructions. */
237 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
239 /* FPU supports half-precision floating-point with NEON element load/store. */
240 #define TARGET_NEON_FP16 \
241 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
243 /* FPU supports VFP half-precision floating-point. */
244 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
246 /* FPU supports Neon instructions. The setting of this macro gets
247 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
248 and TARGET_HARD_FLOAT to ensure that NEON instructions are
250 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
251 && TARGET_VFP && arm_fpu_desc->neon)
253 /* "DSP" multiply instructions, eg. SMULxy. */
254 #define TARGET_DSP_MULTIPLY \
255 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
256 /* Integer SIMD instructions, and extend-accumulate instructions. */
257 #define TARGET_INT_SIMD \
258 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
260 /* Should MOVW/MOVT be used in preference to a constant pool. */
261 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
263 /* We could use unified syntax for arm mode, but for now we just use it
265 #define TARGET_UNIFIED_ASM TARGET_THUMB2
268 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
269 then TARGET_AAPCS_BASED must be true -- but the converse does not
270 hold. TARGET_BPABI implies the use of the BPABI runtime library,
271 etc., in addition to just the AAPCS calling conventions. */
273 #define TARGET_BPABI false
276 /* Support for a compile-time default CPU, et cetera. The rules are:
277 --with-arch is ignored if -march or -mcpu are specified.
278 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
280 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
282 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
284 --with-fpu is ignored if -mfpu is specified.
285 --with-abi is ignored is -mabi is specified. */
286 #define OPTION_DEFAULT_SPECS \
287 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
288 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
289 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
291 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
292 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
293 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
294 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
296 /* Which floating point model to use. */
299 ARM_FP_MODEL_UNKNOWN,
300 /* FPA model (Hardware or software). */
302 /* Cirrus Maverick floating point model. */
303 ARM_FP_MODEL_MAVERICK,
304 /* VFP floating point model. */
316 extern const struct arm_fpu_desc
319 enum arm_fp_model model;
321 enum vfp_reg_type regs;
326 /* Which floating point hardware to schedule for. */
327 extern int arm_fpu_attr;
332 ARM_FLOAT_ABI_SOFTFP,
336 extern enum float_abi_type arm_float_abi;
338 #ifndef TARGET_DEFAULT_FLOAT_ABI
339 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
342 /* Which __fp16 format to use.
343 The enumeration values correspond to the numbering for the
344 Tag_ABI_FP_16bit_format attribute.
346 enum arm_fp16_format_type
348 ARM_FP16_FORMAT_NONE = 0,
349 ARM_FP16_FORMAT_IEEE = 1,
350 ARM_FP16_FORMAT_ALTERNATIVE = 2
353 extern enum arm_fp16_format_type arm_fp16_format;
354 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
355 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
357 /* Which ABI to use. */
367 extern enum arm_abi_type arm_abi;
369 #ifndef ARM_DEFAULT_ABI
370 #define ARM_DEFAULT_ABI ARM_ABI_APCS
373 /* Which thread pointer access sequence to use. */
380 extern enum arm_tp_type target_thread_pointer;
382 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
383 extern int arm_arch3m;
385 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
386 extern int arm_arch4;
388 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
389 extern int arm_arch4t;
391 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
392 extern int arm_arch5;
394 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
395 extern int arm_arch5e;
397 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
398 extern int arm_arch6;
400 /* Nonzero if instructions not present in the 'M' profile can be used. */
401 extern int arm_arch_notm;
403 /* Nonzero if instructions present in ARMv7E-M can be used. */
404 extern int arm_arch7em;
406 /* Nonzero if this chip can benefit from load scheduling. */
407 extern int arm_ld_sched;
409 /* Nonzero if generating thumb code. */
410 extern int thumb_code;
412 /* Nonzero if this chip is a StrongARM. */
413 extern int arm_tune_strongarm;
415 /* Nonzero if this chip is a Cirrus variant. */
416 extern int arm_arch_cirrus;
418 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
419 extern int arm_arch_iwmmxt;
421 /* Nonzero if this chip is an XScale. */
422 extern int arm_arch_xscale;
424 /* Nonzero if tuning for XScale. */
425 extern int arm_tune_xscale;
427 /* Nonzero if tuning for stores via the write buffer. */
428 extern int arm_tune_wbuf;
430 /* Nonzero if tuning for Cortex-A9. */
431 extern int arm_tune_cortex_a9;
433 /* Nonzero if we should define __THUMB_INTERWORK__ in the
435 XXX This is a bit of a hack, it's intended to help work around
436 problems in GLD which doesn't understand that armv5t code is
437 interworking clean. */
438 extern int arm_cpp_interwork;
440 /* Nonzero if chip supports Thumb 2. */
441 extern int arm_arch_thumb2;
443 /* Nonzero if chip supports integer division instruction. */
444 extern int arm_arch_hwdiv;
446 #ifndef TARGET_DEFAULT
447 #define TARGET_DEFAULT (MASK_APCS_FRAME)
450 /* The frame pointer register used in gcc has nothing to do with debugging;
451 that is controlled by the APCS-FRAME option. */
452 #define CAN_DEBUG_WITHOUT_FP
454 #define OVERRIDE_OPTIONS arm_override_options ()
456 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
457 arm_optimization_options ((LEVEL), (SIZE))
459 /* Nonzero if PIC code requires explicit qualifiers to generate
460 PLT and GOT relocs rather than the assembler doing so implicitly.
461 Subtargets can override these if required. */
462 #ifndef NEED_GOT_RELOC
463 #define NEED_GOT_RELOC 0
465 #ifndef NEED_PLT_RELOC
466 #define NEED_PLT_RELOC 0
469 /* Nonzero if we need to refer to the GOT with a PC-relative
470 offset. In other words, generate
472 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
476 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
478 The default is true, which matches NetBSD. Subtargets can
479 override this if required. */
484 /* Target machine storage Layout. */
487 /* Define this macro if it is advisable to hold scalars in registers
488 in a wider mode than that declared by the program. In such cases,
489 the value is constrained to be within the bounds of the declared
490 type, but kept valid in the wider mode. The signedness of the
491 extension may differ from that of the type. */
493 /* It is far faster to zero extend chars than to sign extend them */
495 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
496 if (GET_MODE_CLASS (MODE) == MODE_INT \
497 && GET_MODE_SIZE (MODE) < 4) \
499 if (MODE == QImode) \
501 else if (MODE == HImode) \
506 /* Define this if most significant bit is lowest numbered
507 in instructions that operate on numbered bit-fields. */
508 #define BITS_BIG_ENDIAN 0
510 /* Define this if most significant byte of a word is the lowest numbered.
511 Most ARM processors are run in little endian mode, so that is the default.
512 If you want to have it run-time selectable, change the definition in a
513 cover file to be TARGET_BIG_ENDIAN. */
514 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
516 /* Define this if most significant word of a multiword number is the lowest
518 This is always false, even when in big-endian mode. */
519 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
521 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
522 on processor pre-defineds when compiling libgcc2.c. */
523 #if defined(__ARMEB__) && !defined(__ARMWEL__)
524 #define LIBGCC2_WORDS_BIG_ENDIAN 1
526 #define LIBGCC2_WORDS_BIG_ENDIAN 0
529 /* Define this if most significant word of doubles is the lowest numbered.
530 The rules are different based on whether or not we use FPA-format,
531 VFP-format or some other floating point co-processor's format doubles. */
532 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
534 #define UNITS_PER_WORD 4
536 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
537 registers when autovectorizing for Neon, at least until multiple vector
538 widths are supported properly by the middle-end. */
539 #define UNITS_PER_SIMD_WORD(MODE) \
540 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
542 /* True if natural alignment is used for doubleword types. */
543 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
545 #define DOUBLEWORD_ALIGNMENT 64
547 #define PARM_BOUNDARY 32
549 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
551 #define PREFERRED_STACK_BOUNDARY \
552 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
554 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
556 /* The lowest bit is used to indicate Thumb-mode functions, so the
557 vbit must go into the delta field of pointers to member
559 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
561 #define EMPTY_FIELD_BOUNDARY 32
563 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
565 /* XXX Blah -- this macro is used directly by libobjc. Since it
566 supports no vector modes, cut out the complexity and fall back
567 on BIGGEST_FIELD_ALIGNMENT. */
568 #ifdef IN_TARGET_LIBS
569 #define BIGGEST_FIELD_ALIGNMENT 64
572 /* Make strings word-aligned so strcpy from constants will be faster. */
573 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
575 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
576 ((TREE_CODE (EXP) == STRING_CST \
578 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
579 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
581 /* Align definitions of arrays, unions and structures so that
582 initializations and copies can be made more efficient. This is not
583 ABI-changing, so it only affects places where we can see the
585 #define DATA_ALIGNMENT(EXP, ALIGN) \
586 ((((ALIGN) < BITS_PER_WORD) \
587 && (TREE_CODE (EXP) == ARRAY_TYPE \
588 || TREE_CODE (EXP) == UNION_TYPE \
589 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
591 /* Similarly, make sure that objects on the stack are sensibly aligned. */
592 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
594 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
595 value set in previous versions of this toolchain was 8, which produces more
596 compact structures. The command line option -mstructure_size_boundary=<n>
597 can be used to change this value. For compatibility with the ARM SDK
598 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
599 0020D) page 2-20 says "Structures are aligned on word boundaries".
600 The AAPCS specifies a value of 8. */
601 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
602 extern int arm_structure_size_boundary;
604 /* This is the value used to initialize arm_structure_size_boundary. If a
605 particular arm target wants to change the default value it should change
606 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
607 for an example of this. */
608 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
609 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
612 /* Nonzero if move instructions will actually fail to work
613 when given unaligned data. */
614 #define STRICT_ALIGNMENT 1
616 /* wchar_t is unsigned under the AAPCS. */
618 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
620 #define WCHAR_TYPE_SIZE BITS_PER_WORD
624 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
628 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
631 /* AAPCS requires that structure alignment is affected by bitfields. */
632 #ifndef PCC_BITFIELD_TYPE_MATTERS
633 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
637 /* Standard register usage. */
639 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
640 (S - saved over call).
642 r0 * argument word/integer result
645 r4-r8 S register variable
646 r9 S (rfp) register variable (real frame pointer)
648 r10 F S (sl) stack limit (used by -mapcs-stack-check)
649 r11 F S (fp) argument pointer
650 r12 (ip) temp workspace
651 r13 F S (sp) lower end of current stack frame
652 r14 (lr) link address/workspace
653 r15 F (pc) program counter
655 f0 floating point result
656 f1-f3 floating point scratch
658 f4-f7 S floating point variable
660 cc This is NOT a real register, but is used internally
661 to represent things that use or set the condition
663 sfp This isn't either. It is used during rtl generation
664 since the offset between the frame pointer and the
665 auto's isn't known until after register allocation.
666 afp Nor this, we only need this because of non-local
667 goto. Without it fp appears to be used and the
668 elimination code won't get rid of sfp. It tracks
669 fp exactly at all times.
671 *: See CONDITIONAL_REGISTER_USAGE */
674 mvf0 Cirrus floating point result
675 mvf1-mvf3 Cirrus floating point scratch
676 mvf4-mvf15 S Cirrus floating point variable. */
678 /* s0-s15 VFP scratch (aka d0-d7).
679 s16-s31 S VFP variable (aka d8-d15).
680 vfpcc Not a real register. Represents the VFP condition
683 /* The stack backtrace structure is as follows:
684 fp points to here: | save code pointer | [fp]
685 | return link value | [fp, #-4]
686 | return sp value | [fp, #-8]
687 | return fp value | [fp, #-12]
688 [| saved r10 value |]
699 [| saved f7 value |] three words
700 [| saved f6 value |] three words
701 [| saved f5 value |] three words
702 [| saved f4 value |] three words
703 r0-r3 are not normally saved in a C function. */
705 /* 1 for registers that have pervasive standard uses
706 and are not available for the register allocator. */
707 #define FIXED_REGISTERS \
729 /* 1 for registers not available across function calls.
730 These must include the FIXED_REGISTERS and also any
731 registers that can be used without being saved.
732 The latter must include the registers where values are returned
733 and the register where structure-value addresses are passed.
734 Aside from that, you can include as many other registers as you like.
735 The CC is not preserved over function calls on the ARM 6, so it is
736 easier to assume this for all. SFP is preserved, since FP is. */
737 #define CALL_USED_REGISTERS \
759 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
760 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
763 #define CONDITIONAL_REGISTER_USAGE \
767 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
769 for (regno = FIRST_FPA_REGNUM; \
770 regno <= LAST_FPA_REGNUM; ++regno) \
771 fixed_regs[regno] = call_used_regs[regno] = 1; \
774 if (TARGET_THUMB1 && optimize_size) \
776 /* When optimizing for size on Thumb-1, it's better not \
777 to use the HI regs, because of the overhead of \
779 for (regno = FIRST_HI_REGNUM; \
780 regno <= LAST_HI_REGNUM; ++regno) \
781 fixed_regs[regno] = call_used_regs[regno] = 1; \
784 /* The link register can be clobbered by any branch insn, \
785 but we have no way to track that at present, so mark \
786 it as unavailable. */ \
788 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
790 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
792 if (TARGET_MAVERICK) \
794 for (regno = FIRST_FPA_REGNUM; \
795 regno <= LAST_FPA_REGNUM; ++ regno) \
796 fixed_regs[regno] = call_used_regs[regno] = 1; \
797 for (regno = FIRST_CIRRUS_FP_REGNUM; \
798 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
800 fixed_regs[regno] = 0; \
801 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
806 /* VFPv3 registers are disabled when earlier VFP \
807 versions are selected due to the definition of \
808 LAST_VFP_REGNUM. */ \
809 for (regno = FIRST_VFP_REGNUM; \
810 regno <= LAST_VFP_REGNUM; ++ regno) \
812 fixed_regs[regno] = 0; \
813 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
814 || regno >= FIRST_VFP_REGNUM + 32; \
819 if (TARGET_REALLY_IWMMXT) \
821 regno = FIRST_IWMMXT_GR_REGNUM; \
822 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
823 and wCG1 as call-preserved registers. The 2002/11/21 \
824 revision changed this so that all wCG registers are \
825 scratch registers. */ \
826 for (regno = FIRST_IWMMXT_GR_REGNUM; \
827 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
828 fixed_regs[regno] = 0; \
829 /* The XScale ABI has wR0 - wR9 as scratch registers, \
830 the rest as call-preserved registers. */ \
831 for (regno = FIRST_IWMMXT_REGNUM; \
832 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
834 fixed_regs[regno] = 0; \
835 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
839 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
841 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
842 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
844 else if (TARGET_APCS_STACK) \
846 fixed_regs[10] = 1; \
847 call_used_regs[10] = 1; \
849 /* -mcaller-super-interworking reserves r11 for calls to \
850 _interwork_r11_call_via_rN(). Making the register global \
851 is an easy way of ensuring that it remains valid for all \
853 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
854 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
856 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
857 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
858 if (TARGET_CALLER_INTERWORKING) \
859 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
861 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
864 /* These are a couple of extensions to the formats accepted
866 %@ prints out ASM_COMMENT_START
867 %r prints out REGISTER_PREFIX reg_names[arg] */
868 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
870 fputs (ASM_COMMENT_START, FILE); \
874 fputs (REGISTER_PREFIX, FILE); \
875 fputs (reg_names [va_arg (ARGS, int)], FILE); \
878 /* Round X up to the nearest word. */
879 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
881 /* Convert fron bytes to ints. */
882 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
884 /* The number of (integer) registers required to hold a quantity of type MODE.
885 Also used for VFP registers. */
886 #define ARM_NUM_REGS(MODE) \
887 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
889 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
890 #define ARM_NUM_REGS2(MODE, TYPE) \
891 ARM_NUM_INTS ((MODE) == BLKmode ? \
892 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
894 /* The number of (integer) argument register available. */
895 #define NUM_ARG_REGS 4
897 /* And similarly for the VFP. */
898 #define NUM_VFP_ARG_REGS 16
900 /* Return the register number of the N'th (integer) argument. */
901 #define ARG_REGISTER(N) (N - 1)
903 /* Specify the registers used for certain standard purposes.
904 The values of these macros are register numbers. */
906 /* The number of the last argument register. */
907 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
909 /* The numbers of the Thumb register ranges. */
910 #define FIRST_LO_REGNUM 0
911 #define LAST_LO_REGNUM 7
912 #define FIRST_HI_REGNUM 8
913 #define LAST_HI_REGNUM 11
915 #ifndef TARGET_UNWIND_INFO
916 /* We use sjlj exceptions for backwards compatibility. */
917 #define MUST_USE_SJLJ_EXCEPTIONS 1
920 /* We can generate DWARF2 Unwind info, even though we don't use it. */
921 #define DWARF2_UNWIND_INFO 1
923 /* Use r0 and r1 to pass exception handling information. */
924 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
926 /* The register that holds the return address in exception handlers. */
927 #define ARM_EH_STACKADJ_REGNUM 2
928 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
930 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
931 as an invisible last argument (possible since varargs don't exist in
932 Pascal), so the following is not true. */
933 #define STATIC_CHAIN_REGNUM 12
935 /* Define this to be where the real frame pointer is if it is not possible to
936 work out the offset between the frame pointer and the automatic variables
937 until after register allocation has taken place. FRAME_POINTER_REGNUM
938 should point to a special register that we will make sure is eliminated.
940 For the Thumb we have another problem. The TPCS defines the frame pointer
941 as r11, and GCC believes that it is always possible to use the frame pointer
942 as base register for addressing purposes. (See comments in
943 find_reloads_address()). But - the Thumb does not allow high registers,
944 including r11, to be used as base address registers. Hence our problem.
946 The solution used here, and in the old thumb port is to use r7 instead of
947 r11 as the hard frame pointer and to have special code to generate
948 backtrace structures on the stack (if required to do so via a command line
949 option) using r11. This is the only 'user visible' use of r11 as a frame
951 #define ARM_HARD_FRAME_POINTER_REGNUM 11
952 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
954 #define HARD_FRAME_POINTER_REGNUM \
956 ? ARM_HARD_FRAME_POINTER_REGNUM \
957 : THUMB_HARD_FRAME_POINTER_REGNUM)
959 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
961 /* Register to use for pushing function arguments. */
962 #define STACK_POINTER_REGNUM SP_REGNUM
964 /* ARM floating pointer registers. */
965 #define FIRST_FPA_REGNUM 16
966 #define LAST_FPA_REGNUM 23
967 #define IS_FPA_REGNUM(REGNUM) \
968 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
970 #define FIRST_IWMMXT_GR_REGNUM 43
971 #define LAST_IWMMXT_GR_REGNUM 46
972 #define FIRST_IWMMXT_REGNUM 47
973 #define LAST_IWMMXT_REGNUM 62
974 #define IS_IWMMXT_REGNUM(REGNUM) \
975 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
976 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
977 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
979 /* Base register for access to local variables of the function. */
980 #define FRAME_POINTER_REGNUM 25
982 /* Base register for access to arguments of the function. */
983 #define ARG_POINTER_REGNUM 26
985 #define FIRST_CIRRUS_FP_REGNUM 27
986 #define LAST_CIRRUS_FP_REGNUM 42
987 #define IS_CIRRUS_REGNUM(REGNUM) \
988 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
990 #define FIRST_VFP_REGNUM 63
991 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
992 #define LAST_VFP_REGNUM \
993 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
995 #define IS_VFP_REGNUM(REGNUM) \
996 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
998 /* VFP registers are split into two types: those defined by VFP versions < 3
999 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1000 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1001 in various parts of the backend, we implement as "fake" single-precision
1002 registers (which would be S32-S63, but cannot be used in that way). The
1003 following macros define these ranges of registers. */
1004 #define LAST_LO_VFP_REGNUM 94
1005 #define FIRST_HI_VFP_REGNUM 95
1006 #define LAST_HI_VFP_REGNUM 126
1008 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1009 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1011 /* DFmode values are only valid in even register pairs. */
1012 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1013 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1015 /* Neon Quad values must start at a multiple of four registers. */
1016 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1017 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1019 /* Neon structures of vectors must be in even register pairs and there
1020 must be enough registers available. Because of various patterns
1021 requiring quad registers, we require them to start at a multiple of
1023 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1024 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1025 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1027 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1028 /* + 16 Cirrus registers take us up to 43. */
1029 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1030 /* VFP (VFP3) adds 32 (64) + 1 more. */
1031 #define FIRST_PSEUDO_REGISTER 128
1033 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1035 /* Value should be nonzero if functions must have frame pointers.
1036 Zero means the frame pointer need not be set up (and parms may be accessed
1037 via the stack pointer) in functions that seem suitable.
1038 If we have to have a frame pointer we might as well make use of it.
1039 APCS says that the frame pointer does not need to be pushed in leaf
1040 functions, or simple tail call functions. */
1042 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1043 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1046 /* Return number of consecutive hard regs needed starting at reg REGNO
1047 to hold something of mode MODE.
1048 This is ordinarily the length in words of a value of mode MODE
1049 but can be less for certain modes in special long registers.
1051 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1053 #define HARD_REGNO_NREGS(REGNO, MODE) \
1055 && REGNO >= FIRST_FPA_REGNUM \
1056 && REGNO != FRAME_POINTER_REGNUM \
1057 && REGNO != ARG_POINTER_REGNUM) \
1058 && !IS_VFP_REGNUM (REGNO) \
1059 ? 1 : ARM_NUM_REGS (MODE))
1061 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1062 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1063 arm_hard_regno_mode_ok ((REGNO), (MODE))
1065 /* Value is 1 if it is a good idea to tie two pseudo registers
1066 when one has mode MODE1 and one has mode MODE2.
1067 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1068 for any hard reg, then this must be 0 for correct output. */
1069 #define MODES_TIEABLE_P(MODE1, MODE2) \
1070 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1072 #define VALID_IWMMXT_REG_MODE(MODE) \
1073 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1075 /* Modes valid for Neon D registers. */
1076 #define VALID_NEON_DREG_MODE(MODE) \
1077 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1078 || (MODE) == V2SFmode || (MODE) == DImode)
1080 /* Modes valid for Neon Q registers. */
1081 #define VALID_NEON_QREG_MODE(MODE) \
1082 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1083 || (MODE) == V4SFmode || (MODE) == V2DImode)
1085 /* Structure modes valid for Neon registers. */
1086 #define VALID_NEON_STRUCT_MODE(MODE) \
1087 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1088 || (MODE) == CImode || (MODE) == XImode)
1090 /* The order in which register should be allocated. It is good to use ip
1091 since no saving is required (though calls clobber it) and it never contains
1092 function parameters. It is quite good to use lr since other calls may
1093 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1094 least likely to contain a function parameter; in addition results are
1096 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1097 then D8-D15. The reason for doing this is to attempt to reduce register
1098 pressure when both single- and double-precision registers are used in a
1101 #define REG_ALLOC_ORDER \
1103 3, 2, 1, 0, 12, 14, 4, 5, \
1104 6, 7, 8, 10, 9, 11, 13, 15, \
1105 16, 17, 18, 19, 20, 21, 22, 23, \
1106 27, 28, 29, 30, 31, 32, 33, 34, \
1107 35, 36, 37, 38, 39, 40, 41, 42, \
1108 43, 44, 45, 46, 47, 48, 49, 50, \
1109 51, 52, 53, 54, 55, 56, 57, 58, \
1112 95, 96, 97, 98, 99, 100, 101, 102, \
1113 103, 104, 105, 106, 107, 108, 109, 110, \
1114 111, 112, 113, 114, 115, 116, 117, 118, \
1115 119, 120, 121, 122, 123, 124, 125, 126, \
1116 78, 77, 76, 75, 74, 73, 72, 71, \
1117 70, 69, 68, 67, 66, 65, 64, 63, \
1118 79, 80, 81, 82, 83, 84, 85, 86, \
1119 87, 88, 89, 90, 91, 92, 93, 94, \
1123 /* Use different register alloc ordering for Thumb. */
1124 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1126 /* Tell IRA to use the order we define rather than messing it up with its
1127 own cost calculations. */
1128 #define HONOR_REG_ALLOC_ORDER
1130 /* Interrupt functions can only use registers that have already been
1131 saved by the prologue, even if they would normally be
1133 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1134 (! IS_INTERRUPT (cfun->machine->func_type) || \
1135 df_regs_ever_live_p (DST))
1137 /* Register and constant classes. */
1139 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1140 Now that the Thumb is involved it has become more complicated. */
1164 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166 /* Give names of register classes as strings for dump file. */
1167 #define REG_CLASS_NAMES \
1189 /* Define which registers fit in which classes.
1190 This is an initializer for a vector of HARD_REG_SET
1191 of length N_REG_CLASSES. */
1192 #define REG_CLASS_CONTENTS \
1194 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1195 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1196 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1197 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1198 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1199 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1200 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1201 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1202 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1203 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1204 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1205 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1206 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1207 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1208 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1209 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1210 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1211 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1214 /* Any of the VFP register classes. */
1215 #define IS_VFP_CLASS(X) \
1216 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1217 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1219 /* The same information, inverted:
1220 Return the class number of the smallest class containing
1221 reg number REGNO. This could be a conditional expression
1222 or could index an array. */
1223 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1225 /* The following macro defines cover classes for Integrated Register
1226 Allocator. Cover classes is a set of non-intersected register
1227 classes covering all hard registers used for register allocation
1228 purpose. Any move between two registers of a cover class should be
1229 cheaper than load or store of the registers. The macro value is
1230 array of register classes with LIM_REG_CLASSES used as the end
1233 #define IRA_COVER_CLASSES \
1235 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1239 /* FPA registers can't do subreg as all values are reformatted to internal
1240 precision. VFP registers may only be accessed in the mode they
1242 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1243 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1244 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1245 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1248 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1249 using r0-r4 for function arguments, r7 for the stack frame and don't
1250 have enough left over to do doubleword arithmetic. */
1251 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1252 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1253 || (CLASS) == CC_REG)
1255 /* The class value for index registers, and the one for base regs. */
1256 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1257 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1259 /* For the Thumb the high registers cannot be used as base registers
1260 when addressing quantities in QI or HI mode; if we don't know the
1261 mode, then we must be conservative. */
1262 #define MODE_BASE_REG_CLASS(MODE) \
1263 (TARGET_32BIT ? CORE_REGS : \
1264 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1266 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1267 instead of BASE_REGS. */
1268 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1270 /* When this hook returns true for MODE, the compiler allows
1271 registers explicitly used in the rtl to be used as spill registers
1272 but prevents the compiler from extending the lifetime of these
1274 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1275 arm_small_register_classes_for_mode_p
1277 /* Given an rtx X being reloaded into a reg required to be
1278 in class CLASS, return the class of reg to actually use.
1279 In general this is just CLASS, but for the Thumb core registers and
1280 immediate constants we prefer a LO_REGS class or a subset. */
1281 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1282 (TARGET_32BIT ? (CLASS) : \
1283 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1284 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1285 ? LO_REGS : (CLASS)))
1287 /* Must leave BASE_REGS reloads alone */
1288 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1289 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1290 ? ((true_regnum (X) == -1 ? LO_REGS \
1291 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1295 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1296 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1297 ? ((true_regnum (X) == -1 ? LO_REGS \
1298 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1302 /* Return the register class of a scratch register needed to copy IN into
1303 or out of a register in CLASS in MODE. If it can be done directly,
1304 NO_REGS is returned. */
1305 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1306 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1307 ((TARGET_VFP && TARGET_HARD_FLOAT \
1308 && IS_VFP_CLASS (CLASS)) \
1309 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1310 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1311 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1313 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1314 ? GENERAL_REGS : NO_REGS) \
1315 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1317 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1318 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1319 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1320 ((TARGET_VFP && TARGET_HARD_FLOAT \
1321 && IS_VFP_CLASS (CLASS)) \
1322 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1323 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1324 coproc_secondary_reload_class (MODE, X, TRUE) : \
1325 /* Cannot load constants into Cirrus registers. */ \
1326 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1327 && (CLASS) == CIRRUS_REGS \
1328 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1331 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1332 && CONSTANT_P (X)) \
1334 (((MODE) == HImode && ! arm_arch4 \
1335 && (GET_CODE (X) == MEM \
1336 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1337 && true_regnum (X) == -1))) \
1338 ? GENERAL_REGS : NO_REGS) \
1339 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1341 /* Try a machine-dependent way of reloading an illegitimate address
1342 operand. If we find one, push the reload and jump to WIN. This
1343 macro is used in only one place: `find_reloads_address' in reload.c.
1345 For the ARM, we wish to handle large displacements off a base
1346 register by splitting the addend across a MOV and the mem insn.
1347 This can cut the number of reloads needed. */
1348 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1351 if (GET_CODE (X) == PLUS \
1352 && GET_CODE (XEXP (X, 0)) == REG \
1353 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1354 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1355 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1357 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1358 HOST_WIDE_INT low, high; \
1360 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1361 low = ((val & 0xf) ^ 0x8) - 0x8; \
1362 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1363 /* Need to be careful, -256 is not a valid offset. */ \
1364 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1365 else if (MODE == SImode \
1366 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1367 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1368 /* Need to be careful, -4096 is not a valid offset. */ \
1369 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1370 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1371 /* Need to be careful, -256 is not a valid offset. */ \
1372 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1373 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1374 && TARGET_HARD_FLOAT && TARGET_FPA) \
1375 /* Need to be careful, -1024 is not a valid offset. */ \
1376 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1380 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1381 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1382 - (unsigned HOST_WIDE_INT) 0x80000000); \
1383 /* Check for overflow or zero */ \
1384 if (low == 0 || high == 0 || (high + low != val)) \
1387 /* Reload the high part into a base reg; leave the low part \
1389 X = gen_rtx_PLUS (GET_MODE (X), \
1390 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1393 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1394 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1395 VOIDmode, 0, 0, OPNUM, TYPE); \
1401 /* XXX If an HImode FP+large_offset address is converted to an HImode
1402 SP+large_offset address, then reload won't know how to fix it. It sees
1403 only that SP isn't valid for HImode, and so reloads the SP into an index
1404 register, but the resulting address is still invalid because the offset
1405 is too big. We fix it here instead by reloading the entire address. */
1406 /* We could probably achieve better results by defining PROMOTE_MODE to help
1407 cope with the variances between the Thumb's signed and unsigned byte and
1408 halfword load instructions. */
1409 /* ??? This should be safe for thumb2, but we may be able to do better. */
1410 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1412 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1420 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1422 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1424 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1426 /* Return the maximum number of consecutive registers
1427 needed to represent mode MODE in a register of class CLASS.
1428 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1429 #define CLASS_MAX_NREGS(CLASS, MODE) \
1430 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1432 /* If defined, gives a class of registers that cannot be used as the
1433 operand of a SUBREG that changes the mode of the object illegally. */
1435 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1436 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1437 it is typically more expensive than a single memory access. We set
1438 the cost to less than two memory accesses so that floating
1439 point to integer conversion does not go through memory. */
1440 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1442 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1443 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1444 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1445 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1446 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1447 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1448 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1449 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1450 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1453 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1455 /* Stack layout; function entry, exit and calling. */
1457 /* Define this if pushing a word on the stack
1458 makes the stack pointer a smaller address. */
1459 #define STACK_GROWS_DOWNWARD 1
1461 /* Define this to nonzero if the nominal address of the stack frame
1462 is at the high-address end of the local variables;
1463 that is, each additional local variable allocated
1464 goes at a more negative offset in the frame. */
1465 #define FRAME_GROWS_DOWNWARD 1
1467 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1468 When present, it is one word in size, and sits at the top of the frame,
1469 between the soft frame pointer and either r7 or r11.
1471 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1472 and only then if some outgoing arguments are passed on the stack. It would
1473 be tempting to also check whether the stack arguments are passed by indirect
1474 calls, but there seems to be no reason in principle why a post-reload pass
1475 couldn't convert a direct call into an indirect one. */
1476 #define CALLER_INTERWORKING_SLOT_SIZE \
1477 (TARGET_CALLER_INTERWORKING \
1478 && crtl->outgoing_args_size != 0 \
1479 ? UNITS_PER_WORD : 0)
1481 /* Offset within stack frame to start allocating local variables at.
1482 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1483 first local allocated. Otherwise, it is the offset to the BEGINNING
1484 of the first local allocated. */
1485 #define STARTING_FRAME_OFFSET 0
1487 /* If we generate an insn to push BYTES bytes,
1488 this says how many the stack pointer really advances by. */
1489 /* The push insns do not do this rounding implicitly.
1490 So don't define this. */
1491 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1493 /* Define this if the maximum size of all the outgoing args is to be
1494 accumulated and pushed during the prologue. The amount can be
1495 found in the variable crtl->outgoing_args_size. */
1496 #define ACCUMULATE_OUTGOING_ARGS 1
1498 /* Offset of first parameter from the argument pointer register value. */
1499 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1501 /* Define how to find the value returned by a library function
1502 assuming the value has mode MODE. */
1503 #define LIBCALL_VALUE(MODE) \
1504 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1505 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1506 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1507 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1508 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1509 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1510 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1511 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1512 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1513 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1515 /* 1 if REGNO is a possible register number for a function value. */
1516 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1517 ((REGNO) == ARG_REGISTER (1) \
1518 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1519 && TARGET_VFP && TARGET_HARD_FLOAT \
1520 && (REGNO) == FIRST_VFP_REGNUM) \
1521 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1522 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1523 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1524 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1525 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1527 /* Amount of memory needed for an untyped call to save all possible return
1529 #define APPLY_RESULT_SIZE arm_apply_result_size()
1531 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1532 values must be in memory. On the ARM, they need only do so if larger
1533 than a word, or if they contain elements offset from zero in the struct. */
1534 #define DEFAULT_PCC_STRUCT_RETURN 0
1536 /* These bits describe the different types of function supported
1537 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1538 normal function and an interworked function, for example. Knowing the
1539 type of a function is important for determining its prologue and
1541 Note value 7 is currently unassigned. Also note that the interrupt
1542 function types all have bit 2 set, so that they can be tested for easily.
1543 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1544 machine_function structure is initialized (to zero) func_type will
1545 default to unknown. This will force the first use of arm_current_func_type
1546 to call arm_compute_func_type. */
1547 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1548 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1549 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1550 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1551 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1552 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1554 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1556 /* In addition functions can have several type modifiers,
1557 outlined by these bit masks: */
1558 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1559 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1560 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1561 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1562 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1564 /* Some macros to test these flags. */
1565 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1566 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1567 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1568 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1569 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1570 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1573 /* Structure used to hold the function stack frame layout. Offsets are
1574 relative to the stack pointer on function entry. Positive offsets are
1575 in the direction of stack growth.
1576 Only soft_frame is used in thumb mode. */
1578 typedef struct GTY(()) arm_stack_offsets
1580 int saved_args; /* ARG_POINTER_REGNUM. */
1581 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1583 int soft_frame; /* FRAME_POINTER_REGNUM. */
1584 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1585 int outgoing_args; /* STACK_POINTER_REGNUM. */
1586 unsigned int saved_regs_mask;
1590 /* A C structure for machine-specific, per-function data.
1591 This is added to the cfun structure. */
1592 typedef struct GTY(()) machine_function
1594 /* Additional stack adjustment in __builtin_eh_throw. */
1595 rtx eh_epilogue_sp_ofs;
1596 /* Records if LR has to be saved for far jumps. */
1598 /* Records if ARG_POINTER was ever live. */
1599 int arg_pointer_live;
1600 /* Records if the save of LR has been eliminated. */
1601 int lr_save_eliminated;
1602 /* The size of the stack frame. Only valid after reload. */
1603 arm_stack_offsets stack_offsets;
1604 /* Records the type of the current function. */
1605 unsigned long func_type;
1606 /* Record if the function has a variable argument list. */
1607 int uses_anonymous_args;
1608 /* Records if sibcalls are blocked because an argument
1609 register is needed to preserve stack alignment. */
1610 int sibcall_blocked;
1611 /* The PIC register for this function. This might be a pseudo. */
1613 /* Labels for per-function Thumb call-via stubs. One per potential calling
1614 register. We can never call via LR or PC. We can call via SP if a
1615 trampoline happens to be on the top of the stack. */
1617 /* Set to 1 when a return insn is output, this means that the epilogue
1619 int return_used_this_function;
1623 /* As in the machine_function, a global set of call-via labels, for code
1624 that is in text_section. */
1625 extern GTY(()) rtx thumb_call_via_label[14];
1627 /* The number of potential ways of assigning to a co-processor. */
1628 #define ARM_NUM_COPROC_SLOTS 1
1630 /* Enumeration of procedure calling standard variants. We don't really
1631 support all of these yet. */
1634 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1635 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1636 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1637 /* This must be the last AAPCS variant. */
1638 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1639 ARM_PCS_ATPCS, /* ATPCS. */
1640 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1644 /* A C type for declaring a variable that is used as the first argument of
1645 `FUNCTION_ARG' and other related values. */
1648 /* This is the number of registers of arguments scanned so far. */
1650 /* This is the number of iWMMXt register arguments scanned so far. */
1654 /* Which procedure call variant to use for this call. */
1655 enum arm_pcs pcs_variant;
1657 /* AAPCS related state tracking. */
1658 int aapcs_arg_processed; /* No need to lay out this argument again. */
1659 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1660 this argument, or -1 if using core
1663 int aapcs_next_ncrn;
1664 rtx aapcs_reg; /* Register assigned to this argument. */
1665 int aapcs_partial; /* How many bytes are passed in regs (if
1666 split between core regs and stack.
1668 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1669 int can_split; /* Argument can be split between core regs
1671 /* Private data for tracking VFP register allocation */
1672 unsigned aapcs_vfp_regs_free;
1673 unsigned aapcs_vfp_reg_alloc;
1674 int aapcs_vfp_rcount;
1675 MACHMODE aapcs_vfp_rmode;
1678 /* Define where to put the arguments to a function.
1679 Value is zero to push the argument on the stack,
1680 or a hard register in which to store the argument.
1682 MODE is the argument's machine mode.
1683 TYPE is the data type of the argument (as a tree).
1684 This is null for libcalls where that information may
1686 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1687 the preceding args and about the function being called.
1688 NAMED is nonzero if this argument is a named parameter
1689 (otherwise it is an extra parameter matching an ellipsis).
1691 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1692 other arguments are passed on the stack. If (NAMED == 0) (which happens
1693 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1694 defined), say it is passed in the stack (function_prologue will
1695 indeed make it pass in the stack if necessary). */
1696 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1697 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1699 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1700 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1702 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1703 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1705 /* For AAPCS, padding should never be below the argument. For other ABIs,
1706 * mimic the default. */
1707 #define PAD_VARARGS_DOWN \
1708 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1710 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1711 for a call to a function whose data type is FNTYPE.
1712 For a library call, FNTYPE is 0.
1713 On the ARM, the offset starts at 0. */
1714 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1715 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1717 /* Update the data in CUM to advance over an argument
1718 of mode MODE and data type TYPE.
1719 (TYPE is null for libcalls where that information may not be available.) */
1720 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1721 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1723 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1724 argument with the specified mode and type. If it is not defined,
1725 `PARM_BOUNDARY' is used for all arguments. */
1726 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1727 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1728 ? DOUBLEWORD_ALIGNMENT \
1731 /* 1 if N is a possible register number for function argument passing.
1732 On the ARM, r0-r3 are used to pass args. */
1733 #define FUNCTION_ARG_REGNO_P(REGNO) \
1734 (IN_RANGE ((REGNO), 0, 3) \
1735 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1736 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1737 || (TARGET_IWMMXT_ABI \
1738 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1741 /* If your target environment doesn't prefix user functions with an
1742 underscore, you may wish to re-define this to prevent any conflicts. */
1743 #ifndef ARM_MCOUNT_NAME
1744 #define ARM_MCOUNT_NAME "*mcount"
1747 /* Call the function profiler with a given profile label. The Acorn
1748 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1749 On the ARM the full profile code will look like:
1758 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1759 will output the .text section.
1761 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1762 ``prof'' doesn't seem to mind about this!
1764 Note - this version of the code is designed to work in both ARM and
1766 #ifndef ARM_FUNCTION_PROFILER
1767 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1772 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1773 IP_REGNUM, LR_REGNUM); \
1774 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1775 fputc ('\n', STREAM); \
1776 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1777 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1778 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1782 #ifdef THUMB_FUNCTION_PROFILER
1783 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1785 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1787 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1789 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1790 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1793 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1794 the stack pointer does not matter. The value is tested only in
1795 functions that have frame pointers.
1796 No definition is equivalent to always zero.
1798 On the ARM, the function epilogue recovers the stack pointer from the
1800 #define EXIT_IGNORE_STACK 1
1802 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1804 /* Determine if the epilogue should be output as RTL.
1805 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1806 #define USE_RETURN_INSN(ISCOND) \
1807 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1809 /* Definitions for register eliminations.
1811 This is an array of structures. Each structure initializes one pair
1812 of eliminable registers. The "from" register number is given first,
1813 followed by "to". Eliminations of the same "from" register are listed
1814 in order of preference.
1816 We have two registers that can be eliminated on the ARM. First, the
1817 arg pointer register can often be eliminated in favor of the stack
1818 pointer register. Secondly, the pseudo frame pointer register can always
1819 be eliminated; it is replaced with either the stack or the real frame
1820 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1821 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1823 #define ELIMINABLE_REGS \
1824 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1825 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1826 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1827 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1828 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1829 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1830 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1832 /* Define the offset between two registers, one to be eliminated, and the
1833 other its replacement, at the start of a routine. */
1834 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1836 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1838 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1840 /* Special case handling of the location of arguments passed on the stack. */
1841 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1843 /* Initialize data used by insn expanders. This is called from insn_emit,
1844 once for every function before code is generated. */
1845 #define INIT_EXPANDERS arm_init_expanders ()
1847 /* Length in units of the trampoline for entering a nested function. */
1848 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1850 /* Alignment required for a trampoline in bits. */
1851 #define TRAMPOLINE_ALIGNMENT 32
1853 /* Addressing modes, and classification of registers for them. */
1854 #define HAVE_POST_INCREMENT 1
1855 #define HAVE_PRE_INCREMENT TARGET_32BIT
1856 #define HAVE_POST_DECREMENT TARGET_32BIT
1857 #define HAVE_PRE_DECREMENT TARGET_32BIT
1858 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1859 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1860 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1861 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1863 /* Macros to check register numbers against specific register classes. */
1865 /* These assume that REGNO is a hard or pseudo reg number.
1866 They give nonzero only if REGNO is a hard reg of the suitable class
1867 or a pseudo reg currently allocated to a suitable hard reg.
1868 Since they use reg_renumber, they are safe only once reg_renumber
1869 has been allocated, which happens in local-alloc.c. */
1870 #define TEST_REGNO(R, TEST, VALUE) \
1871 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1873 /* Don't allow the pc to be used. */
1874 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1875 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1876 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1877 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1879 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1880 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1881 || (GET_MODE_SIZE (MODE) >= 4 \
1882 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1884 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1886 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1887 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1889 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1890 For Thumb, we can not use SP + reg, so reject SP. */
1891 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1892 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1894 /* For ARM code, we don't care about the mode, but for Thumb, the index
1895 must be suitable for use in a QImode load. */
1896 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1897 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1898 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1900 /* Maximum number of registers that can appear in a valid memory address.
1901 Shifts in addresses can't be by a register. */
1902 #define MAX_REGS_PER_ADDRESS 2
1904 /* Recognize any constant value that is a valid address. */
1905 /* XXX We can address any constant, eventually... */
1906 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1907 #define CONSTANT_ADDRESS_P(X) \
1908 (GET_CODE (X) == SYMBOL_REF \
1909 && (CONSTANT_POOL_ADDRESS_P (X) \
1910 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1912 /* True if SYMBOL + OFFSET constants must refer to something within
1913 SYMBOL's section. */
1914 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1916 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1917 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1918 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1921 /* Nonzero if the constant value X is a legitimate general operand.
1922 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1924 On the ARM, allow any integer (invalid ones are removed later by insn
1925 patterns), nice doubles and symbol_refs which refer to the function's
1928 When generating pic allow anything. */
1929 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1931 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1932 ( GET_CODE (X) == CONST_INT \
1933 || GET_CODE (X) == CONST_DOUBLE \
1934 || CONSTANT_ADDRESS_P (X) \
1937 #define LEGITIMATE_CONSTANT_P(X) \
1938 (!arm_cannot_force_const_mem (X) \
1939 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1940 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1942 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1943 #define SUBTARGET_NAME_ENCODING_LENGTHS
1946 /* This is a C fragment for the inside of a switch statement.
1947 Each case label should return the number of characters to
1948 be stripped from the start of a function's name, if that
1949 name starts with the indicated character. */
1950 #define ARM_NAME_ENCODING_LENGTHS \
1951 case '*': return 1; \
1952 SUBTARGET_NAME_ENCODING_LENGTHS
1954 /* This is how to output a reference to a user-level label named NAME.
1955 `assemble_name' uses this. */
1956 #undef ASM_OUTPUT_LABELREF
1957 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1958 arm_asm_output_labelref (FILE, NAME)
1960 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1961 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1962 if (TARGET_THUMB2) \
1963 thumb2_asm_output_opcode (STREAM);
1965 /* The EABI specifies that constructors should go in .init_array.
1966 Other targets use .ctors for compatibility. */
1967 #ifndef ARM_EABI_CTORS_SECTION_OP
1968 #define ARM_EABI_CTORS_SECTION_OP \
1969 "\t.section\t.init_array,\"aw\",%init_array"
1971 #ifndef ARM_EABI_DTORS_SECTION_OP
1972 #define ARM_EABI_DTORS_SECTION_OP \
1973 "\t.section\t.fini_array,\"aw\",%fini_array"
1975 #define ARM_CTORS_SECTION_OP \
1976 "\t.section\t.ctors,\"aw\",%progbits"
1977 #define ARM_DTORS_SECTION_OP \
1978 "\t.section\t.dtors,\"aw\",%progbits"
1980 /* Define CTORS_SECTION_ASM_OP. */
1981 #undef CTORS_SECTION_ASM_OP
1982 #undef DTORS_SECTION_ASM_OP
1984 # define CTORS_SECTION_ASM_OP \
1985 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1986 # define DTORS_SECTION_ASM_OP \
1987 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1988 #else /* !defined (IN_LIBGCC2) */
1989 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1990 so we cannot use the definition above. */
1991 # ifdef __ARM_EABI__
1992 /* The .ctors section is not part of the EABI, so we do not define
1993 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1994 from trying to use it. We do define it when doing normal
1995 compilation, as .init_array can be used instead of .ctors. */
1996 /* There is no need to emit begin or end markers when using
1997 init_array; the dynamic linker will compute the size of the
1998 array itself based on special symbols created by the static
1999 linker. However, we do need to arrange to set up
2000 exception-handling here. */
2001 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2002 # define CTOR_LIST_END /* empty */
2003 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2004 # define DTOR_LIST_END /* empty */
2005 # else /* !defined (__ARM_EABI__) */
2006 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2007 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2008 # endif /* !defined (__ARM_EABI__) */
2009 #endif /* !defined (IN_LIBCC2) */
2011 /* True if the operating system can merge entities with vague linkage
2012 (e.g., symbols in COMDAT group) during dynamic linking. */
2013 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2014 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2017 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2019 #ifdef TARGET_UNWIND_INFO
2020 #define ARM_EABI_UNWIND_TABLES \
2021 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2023 #define ARM_EABI_UNWIND_TABLES 0
2026 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2027 and check its validity for a certain class.
2028 We have two alternate definitions for each of them.
2029 The usual definition accepts all pseudo regs; the other rejects
2030 them unless they have been allocated suitable hard regs.
2031 The symbol REG_OK_STRICT causes the latter definition to be used.
2032 Thumb-2 has the same restrictions as arm. */
2033 #ifndef REG_OK_STRICT
2035 #define ARM_REG_OK_FOR_BASE_P(X) \
2036 (REGNO (X) <= LAST_ARM_REGNUM \
2037 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2038 || REGNO (X) == FRAME_POINTER_REGNUM \
2039 || REGNO (X) == ARG_POINTER_REGNUM)
2041 #define ARM_REG_OK_FOR_INDEX_P(X) \
2042 ((REGNO (X) <= LAST_ARM_REGNUM \
2043 && REGNO (X) != STACK_POINTER_REGNUM) \
2044 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2045 || REGNO (X) == FRAME_POINTER_REGNUM \
2046 || REGNO (X) == ARG_POINTER_REGNUM)
2048 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2049 (REGNO (X) <= LAST_LO_REGNUM \
2050 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2051 || (GET_MODE_SIZE (MODE) >= 4 \
2052 && (REGNO (X) == STACK_POINTER_REGNUM \
2053 || (X) == hard_frame_pointer_rtx \
2054 || (X) == arg_pointer_rtx)))
2056 #define REG_STRICT_P 0
2058 #else /* REG_OK_STRICT */
2060 #define ARM_REG_OK_FOR_BASE_P(X) \
2061 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2063 #define ARM_REG_OK_FOR_INDEX_P(X) \
2064 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2066 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2067 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2069 #define REG_STRICT_P 1
2071 #endif /* REG_OK_STRICT */
2073 /* Now define some helpers in terms of the above. */
2075 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2077 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2078 : ARM_REG_OK_FOR_BASE_P (X))
2080 /* For 16-bit Thumb, a valid index register is anything that can be used in
2081 a byte load instruction. */
2082 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2083 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2085 /* Nonzero if X is a hard reg that can be used as an index
2086 or if it is a pseudo reg. On the Thumb, the stack pointer
2088 #define REG_OK_FOR_INDEX_P(X) \
2090 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2091 : ARM_REG_OK_FOR_INDEX_P (X))
2093 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2094 For Thumb, we can not use SP + reg, so reject SP. */
2095 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2096 REG_OK_FOR_INDEX_P (X)
2098 #define ARM_BASE_REGISTER_RTX_P(X) \
2099 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2101 #define ARM_INDEX_REGISTER_RTX_P(X) \
2102 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2104 /* Define this for compatibility reasons. */
2105 #define HANDLE_PRAGMA_PACK_PUSH_POP
2107 /* Specify the machine mode that this machine uses
2108 for the index in the tablejump instruction. */
2109 #define CASE_VECTOR_MODE Pmode
2111 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2113 && (optimize_size || flag_pic)))
2115 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2117 ? (min >= 0 && max < 512 \
2118 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2119 : min >= -256 && max < 256 \
2120 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2121 : min >= 0 && max < 8192 \
2122 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2123 : min >= -4096 && max < 4096 \
2124 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2126 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2127 : (max >= 0x200) ? HImode \
2130 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2131 unsigned is probably best, but may break some code. */
2132 #ifndef DEFAULT_SIGNED_CHAR
2133 #define DEFAULT_SIGNED_CHAR 0
2136 /* Max number of bytes we can move from memory to memory
2137 in one reasonably fast instruction. */
2141 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2143 /* Define if operations between registers always perform the operation
2144 on the full register even if a narrower mode is specified. */
2145 #define WORD_REGISTER_OPERATIONS
2147 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2148 will either zero-extend or sign-extend. The value of this macro should
2149 be the code that says which one of the two operations is implicitly
2150 done, UNKNOWN if none. */
2151 #define LOAD_EXTEND_OP(MODE) \
2152 (TARGET_THUMB ? ZERO_EXTEND : \
2153 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2154 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2156 /* Nonzero if access to memory by bytes is slow and undesirable. */
2157 #define SLOW_BYTE_ACCESS 0
2159 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2161 /* Immediate shift counts are truncated by the output routines (or was it
2162 the assembler?). Shift counts in a register are truncated by ARM. Note
2163 that the native compiler puts too large (> 32) immediate shift counts
2164 into a register and shifts by the register, letting the ARM decide what
2165 to do instead of doing that itself. */
2166 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2167 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2168 On the arm, Y in a register is used modulo 256 for the shift. Only for
2169 rotates is modulo 32 used. */
2170 /* #define SHIFT_COUNT_TRUNCATED 1 */
2172 /* All integers have the same format so truncation is easy. */
2173 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2175 /* Calling from registers is a massive pain. */
2176 #define NO_FUNCTION_CSE 1
2178 /* The machine modes of pointers and functions */
2179 #define Pmode SImode
2180 #define FUNCTION_MODE Pmode
2182 #define ARM_FRAME_RTX(X) \
2183 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2184 || (X) == arg_pointer_rtx)
2186 /* Moves to and from memory are quite expensive */
2187 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2188 (TARGET_32BIT ? 10 : \
2189 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2190 * (CLASS == LO_REGS ? 1 : 2)))
2192 /* Try to generate sequences that don't involve branches, we can then use
2193 conditional instructions */
2194 #define BRANCH_COST(speed_p, predictable_p) \
2195 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2197 /* Position Independent Code. */
2198 /* We decide which register to use based on the compilation options and
2199 the assembler in use; this is more general than the APCS restriction of
2200 using sb (r9) all the time. */
2201 extern unsigned arm_pic_register;
2203 /* The register number of the register used to address a table of static
2204 data addresses in memory. */
2205 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2207 /* We can't directly access anything that contains a symbol,
2208 nor can we indirect via the constant pool. One exception is
2209 UNSPEC_TLS, which is always PIC. */
2210 #define LEGITIMATE_PIC_OPERAND_P(X) \
2211 (!(symbol_mentioned_p (X) \
2212 || label_mentioned_p (X) \
2213 || (GET_CODE (X) == SYMBOL_REF \
2214 && CONSTANT_POOL_ADDRESS_P (X) \
2215 && (symbol_mentioned_p (get_pool_constant (X)) \
2216 || label_mentioned_p (get_pool_constant (X))))) \
2217 || tls_mentioned_p (X))
2219 /* We need to know when we are making a constant pool; this determines
2220 whether data needs to be in the GOT or can be referenced via a GOT
2222 extern int making_const_table;
2224 /* Handle pragmas for compatibility with Intel's compilers. */
2225 /* Also abuse this to register additional C specific EABI attributes. */
2226 #define REGISTER_TARGET_PRAGMAS() do { \
2227 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2228 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2229 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2230 arm_lang_object_attributes_init(); \
2233 /* Condition code information. */
2234 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2235 return the mode to be used for the comparison. */
2237 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2239 #define REVERSIBLE_CC_MODE(MODE) 1
2241 #define REVERSE_CONDITION(CODE,MODE) \
2242 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2243 ? reverse_condition_maybe_unordered (code) \
2244 : reverse_condition (code))
2246 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2247 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2249 /* The arm5 clz instruction returns 32. */
2250 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2251 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2254 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2255 TARGET_THUMB2 ? "\t.thumb\n" : "")
2257 /* Output a push or a pop instruction (only used when profiling).
2258 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2259 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2260 that r7 isn't used by the function profiler, so we can use it as a
2261 scratch reg. WARNING: This isn't safe in the general case! It may be
2262 sensitive to future changes in final.c:profile_function. */
2263 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2267 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2268 STACK_POINTER_REGNUM, REGNO); \
2269 else if (TARGET_THUMB1 \
2270 && (REGNO) == STATIC_CHAIN_REGNUM) \
2272 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2273 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2274 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2277 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2281 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2282 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2286 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2287 STACK_POINTER_REGNUM, REGNO); \
2288 else if (TARGET_THUMB1 \
2289 && (REGNO) == STATIC_CHAIN_REGNUM) \
2291 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2292 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2293 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2296 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2299 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2300 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2302 /* This is how to output a label which precedes a jumptable. Since
2303 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2304 #undef ASM_OUTPUT_CASE_LABEL
2305 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2308 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2309 ASM_OUTPUT_ALIGN (FILE, 2); \
2310 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2314 /* Make sure subsequent insns are aligned after a TBB. */
2315 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2318 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2319 ASM_OUTPUT_ALIGN (FILE, 1); \
2323 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2328 if (is_called_in_ARM_mode (DECL) \
2329 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2330 && cfun->is_thunk)) \
2331 fprintf (STREAM, "\t.code 32\n") ; \
2332 else if (TARGET_THUMB1) \
2333 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2335 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2337 if (TARGET_POKE_FUNCTION_NAME) \
2338 arm_poke_function_name (STREAM, (const char *) NAME); \
2342 /* For aliases of functions we use .thumb_set instead. */
2343 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2346 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2347 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2349 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2351 fprintf (FILE, "\t.thumb_set "); \
2352 assemble_name (FILE, LABEL1); \
2353 fprintf (FILE, ","); \
2354 assemble_name (FILE, LABEL2); \
2355 fprintf (FILE, "\n"); \
2358 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2362 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2363 /* To support -falign-* switches we need to use .p2align so
2364 that alignment directives in code sections will be padded
2365 with no-op instructions, rather than zeroes. */
2366 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2369 if ((MAX_SKIP) == 0) \
2370 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2372 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2373 (int) (LOG), (int) (MAX_SKIP)); \
2377 /* Add two bytes to the length of conditionally executed Thumb-2
2378 instructions for the IT instruction. */
2379 #define ADJUST_INSN_LENGTH(insn, length) \
2380 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2383 /* Only perform branch elimination (by making instructions conditional) if
2384 we're optimizing. For Thumb-2 check if any IT instructions need
2386 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2387 if (TARGET_ARM && optimize) \
2388 arm_final_prescan_insn (INSN); \
2389 else if (TARGET_THUMB2) \
2390 thumb2_final_prescan_insn (INSN); \
2391 else if (TARGET_THUMB1) \
2392 thumb1_final_prescan_insn (INSN)
2394 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2395 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2396 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2397 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2398 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2399 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2402 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2403 if (arm_output_addr_const_extra (file, x) == FALSE) \
2406 /* A C expression whose value is RTL representing the value of the return
2407 address for the frame COUNT steps up from the current frame. */
2409 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2410 arm_return_addr (COUNT, FRAME)
2412 /* Mask of the bits in the PC that contain the real return address
2413 when running in 26-bit mode. */
2414 #define RETURN_ADDR_MASK26 (0x03fffffc)
2416 /* Pick up the return address upon entry to a procedure. Used for
2417 dwarf2 unwind information. This also enables the table driven
2419 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2420 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2422 /* Used to mask out junk bits from the return address, such as
2423 processor state, interrupt status, condition codes and the like. */
2424 #define MASK_RETURN_ADDR \
2425 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2426 in 26 bit mode, the condition codes must be masked out of the \
2427 return address. This does not apply to ARM6 and later processors \
2428 when running in 32 bit mode. */ \
2429 ((arm_arch4 || TARGET_THUMB) \
2430 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2431 : arm_gen_return_addr_mask ())
2434 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2435 symbolic names defined here (which would require too much duplication).
2444 ARM_BUILTIN_WAVG2BR,
2445 ARM_BUILTIN_WAVG2HR,
2472 ARM_BUILTIN_TMOVMSKB,
2473 ARM_BUILTIN_TMOVMSKH,
2474 ARM_BUILTIN_TMOVMSKW,
2483 ARM_BUILTIN_WPACKHSS,
2484 ARM_BUILTIN_WPACKWSS,
2485 ARM_BUILTIN_WPACKDSS,
2486 ARM_BUILTIN_WPACKHUS,
2487 ARM_BUILTIN_WPACKWUS,
2488 ARM_BUILTIN_WPACKDUS,
2493 ARM_BUILTIN_WADDSSB,
2494 ARM_BUILTIN_WADDSSH,
2495 ARM_BUILTIN_WADDSSW,
2496 ARM_BUILTIN_WADDUSB,
2497 ARM_BUILTIN_WADDUSH,
2498 ARM_BUILTIN_WADDUSW,
2502 ARM_BUILTIN_WSUBSSB,
2503 ARM_BUILTIN_WSUBSSH,
2504 ARM_BUILTIN_WSUBSSW,
2505 ARM_BUILTIN_WSUBUSB,
2506 ARM_BUILTIN_WSUBUSH,
2507 ARM_BUILTIN_WSUBUSW,
2514 ARM_BUILTIN_WCMPEQB,
2515 ARM_BUILTIN_WCMPEQH,
2516 ARM_BUILTIN_WCMPEQW,
2517 ARM_BUILTIN_WCMPGTUB,
2518 ARM_BUILTIN_WCMPGTUH,
2519 ARM_BUILTIN_WCMPGTUW,
2520 ARM_BUILTIN_WCMPGTSB,
2521 ARM_BUILTIN_WCMPGTSH,
2522 ARM_BUILTIN_WCMPGTSW,
2524 ARM_BUILTIN_TEXTRMSB,
2525 ARM_BUILTIN_TEXTRMSH,
2526 ARM_BUILTIN_TEXTRMSW,
2527 ARM_BUILTIN_TEXTRMUB,
2528 ARM_BUILTIN_TEXTRMUH,
2529 ARM_BUILTIN_TEXTRMUW,
2579 ARM_BUILTIN_WUNPCKIHB,
2580 ARM_BUILTIN_WUNPCKIHH,
2581 ARM_BUILTIN_WUNPCKIHW,
2582 ARM_BUILTIN_WUNPCKILB,
2583 ARM_BUILTIN_WUNPCKILH,
2584 ARM_BUILTIN_WUNPCKILW,
2586 ARM_BUILTIN_WUNPCKEHSB,
2587 ARM_BUILTIN_WUNPCKEHSH,
2588 ARM_BUILTIN_WUNPCKEHSW,
2589 ARM_BUILTIN_WUNPCKEHUB,
2590 ARM_BUILTIN_WUNPCKEHUH,
2591 ARM_BUILTIN_WUNPCKEHUW,
2592 ARM_BUILTIN_WUNPCKELSB,
2593 ARM_BUILTIN_WUNPCKELSH,
2594 ARM_BUILTIN_WUNPCKELSW,
2595 ARM_BUILTIN_WUNPCKELUB,
2596 ARM_BUILTIN_WUNPCKELUH,
2597 ARM_BUILTIN_WUNPCKELUW,
2599 ARM_BUILTIN_THREAD_POINTER,
2601 ARM_BUILTIN_NEON_BASE,
2603 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2606 /* Do not emit .note.GNU-stack by default. */
2607 #ifndef NEED_INDICATE_EXEC_STACK
2608 #define NEED_INDICATE_EXEC_STACK 0
2611 /* The maximum number of parallel loads or stores we support in an ldm/stm
2613 #define MAX_LDM_STM_OPS 4
2615 #endif /* ! GCC_ARM_H */
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