1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* The archetecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
40 builtin_define ("__thumb__"); \
44 builtin_define ("__ARMEB__"); \
46 builtin_define ("__THUMBEB__"); \
47 if (TARGET_LITTLE_WORDS) \
48 builtin_define ("__ARMWEL__"); \
52 builtin_define ("__ARMEL__"); \
54 builtin_define ("__THUMBEL__"); \
58 builtin_define ("__APCS_32__"); \
60 builtin_define ("__APCS_26__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
68 /* Add a define for interworking. \
69 Needed when building libgcc.a. */ \
70 if (TARGET_INTERWORK) \
71 builtin_define ("__THUMB_INTERWORK__"); \
73 builtin_assert ("cpu=arm"); \
74 builtin_assert ("machine=arm"); \
76 builtin_define (arm_arch_name); \
77 if (arm_arch_cirrus) \
78 builtin_define ("__MAVERICK__"); \
79 if (arm_arch_xscale) \
80 builtin_define ("__XSCALE__"); \
81 if (arm_arch_iwmmxt) \
82 builtin_define ("__IWMMXT__"); \
85 /* The various ARM cores. */
88 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
90 #include "arm-cores.def"
92 /* Used to indicate that no processor has been specified. */
98 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
100 #include "arm-cores.def"
105 /* The processor for which instructions should be scheduled. */
106 extern enum processor_type arm_tune;
108 typedef enum arm_cond_code
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
115 extern arm_cc arm_current_cc;
117 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
119 extern int arm_target_label;
120 extern int arm_ccfsm_state;
121 extern GTY(()) rtx arm_target_insn;
122 /* Run-time compilation parameters selecting different hardware subsets. */
123 extern int target_flags;
124 /* The floating point mode. */
125 extern const char *target_fpu_name;
126 /* For backwards compatibility. */
127 extern const char *target_fpe_name;
128 /* Whether to use floating point hardware. */
129 extern const char *target_float_abi_name;
130 /* Which ABI to use. */
131 extern const char *target_abi_name;
132 /* Define the information needed to generate branch insns. This is
133 stored from the compare operation. */
134 extern GTY(()) rtx arm_compare_op0;
135 extern GTY(()) rtx arm_compare_op1;
136 /* The label of the current constant pool. */
137 extern rtx pool_vector_label;
138 /* Set to 1 when a return insn is output, this means that the epilogue
140 extern int return_used_this_function;
141 /* Used to produce AOF syntax assembler. */
142 extern GTY(()) rtx aof_pic_label;
144 /* Just in case configure has failed to define anything. */
145 #ifndef TARGET_CPU_DEFAULT
146 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
151 #define CPP_SPEC "%(subtarget_cpp_spec) \
152 %{mapcs-32:%{mapcs-26: \
153 %e-mapcs-26 and -mapcs-32 may not be used together}} \
154 %{msoft-float:%{mhard-float: \
155 %e-msoft-float and -mhard_float may not be used together}} \
156 %{mbig-endian:%{mlittle-endian: \
157 %e-mbig-endian and -mlittle-endian may not be used together}}"
163 /* This macro defines names of additional specifications to put in the specs
164 that can be used in various specifications like CC1_SPEC. Its definition
165 is an initializer with a subgrouping for each command option.
167 Each subgrouping contains a string constant, that defines the
168 specification name, and a string constant that used by the GCC driver
171 Do not define this macro if it does not need to do anything. */
172 #define EXTRA_SPECS \
173 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
174 SUBTARGET_EXTRA_SPECS
176 #ifndef SUBTARGET_EXTRA_SPECS
177 #define SUBTARGET_EXTRA_SPECS
180 #ifndef SUBTARGET_CPP_SPEC
181 #define SUBTARGET_CPP_SPEC ""
184 /* Run-time Target Specification. */
185 #ifndef TARGET_VERSION
186 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
189 /* Nonzero if the function prologue (and epilogue) should obey
190 the ARM Procedure Call Standard. */
191 #define ARM_FLAG_APCS_FRAME (1 << 0)
193 /* Nonzero if the function prologue should output the function name to enable
194 the post mortem debugger to print a backtrace (very useful on RISCOS,
195 unused on RISCiX). Specifying this flag also enables
196 -fno-omit-frame-pointer.
197 XXX Must still be implemented in the prologue. */
198 #define ARM_FLAG_POKE (1 << 1)
200 /* Nonzero if floating point instructions are emulated by the FPE, in which
201 case instruction scheduling becomes very uninteresting. */
202 #define ARM_FLAG_FPE (1 << 2)
204 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
205 that assume restoration of the condition flags when returning from a
206 branch and link (ie a function). */
207 #define ARM_FLAG_APCS_32 (1 << 3)
209 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
211 /* Nonzero if stack checking should be performed on entry to each function
212 which allocates temporary variables on the stack. */
213 #define ARM_FLAG_APCS_STACK (1 << 4)
215 /* Nonzero if floating point parameters should be passed to functions in
216 floating point registers. */
217 #define ARM_FLAG_APCS_FLOAT (1 << 5)
219 /* Nonzero if re-entrant, position independent code should be generated.
220 This is equivalent to -fpic. */
221 #define ARM_FLAG_APCS_REENT (1 << 6)
223 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
224 be loaded using either LDRH or LDRB instructions. */
225 #define ARM_FLAG_MMU_TRAPS (1 << 7)
227 /* Nonzero if all floating point instructions are missing (and there is no
228 emulator either). Generate function calls for all ops in this case. */
229 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
231 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
232 #define ARM_FLAG_BIG_END (1 << 9)
234 /* Nonzero if we should compile for Thumb interworking. */
235 #define ARM_FLAG_INTERWORK (1 << 10)
237 /* Nonzero if we should have little-endian words even when compiling for
238 big-endian (for backwards compatibility with older versions of GCC). */
239 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
241 /* Nonzero if we need to protect the prolog from scheduling */
242 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
244 /* Nonzero if a call to abort should be generated if a noreturn
245 function tries to return. */
246 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
248 /* Nonzero if function prologues should not load the PIC register. */
249 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
251 /* Nonzero if all call instructions should be indirect. */
252 #define ARM_FLAG_LONG_CALLS (1 << 15)
254 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
255 #define ARM_FLAG_THUMB (1 << 16)
257 /* Set if a TPCS style stack frame should be generated, for non-leaf
258 functions, even if they do not need one. */
259 #define THUMB_FLAG_BACKTRACE (1 << 17)
261 /* Set if a TPCS style stack frame should be generated, for leaf
262 functions, even if they do not need one. */
263 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
265 /* Set if externally visible functions should assume that they
266 might be called in ARM mode, from a non-thumb aware code. */
267 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
269 /* Set if calls via function pointers should assume that their
270 destination is non-Thumb aware. */
271 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
273 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
274 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
276 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
277 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
278 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
279 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
280 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
281 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
282 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
283 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
284 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
285 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
286 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
287 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
288 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
289 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
290 #define TARGET_IWMMXT (arm_arch_iwmmxt)
291 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
292 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
293 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
294 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
295 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
296 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
297 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
298 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
299 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
300 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
301 #define TARGET_ARM (! TARGET_THUMB)
302 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
303 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
304 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
305 #define TARGET_BACKTRACE (leaf_function_p () \
306 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
307 : (target_flags & THUMB_FLAG_BACKTRACE))
308 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
309 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
310 #define TARGET_AAPCS_BASED \
311 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
313 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
314 #ifndef SUBTARGET_SWITCHES
315 #define SUBTARGET_SWITCHES
318 #define TARGET_SWITCHES \
320 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
321 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
322 N_("Generate APCS conformant stack frames") }, \
323 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
324 {"poke-function-name", ARM_FLAG_POKE, \
325 N_("Store function names in object code") }, \
326 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
327 {"fpe", ARM_FLAG_FPE, "" }, \
328 {"apcs-32", ARM_FLAG_APCS_32, \
329 N_("Use the 32-bit version of the APCS") }, \
330 {"apcs-26", -ARM_FLAG_APCS_32, \
331 N_("Use the 26-bit version of the APCS") }, \
332 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
333 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
334 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
335 N_("Pass FP arguments in FP registers") }, \
336 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
337 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
338 N_("Generate re-entrant, PIC code") }, \
339 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
340 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
341 N_("The MMU will trap on unaligned accesses") }, \
342 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
343 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
344 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
345 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
346 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
347 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
348 N_("Use library calls to perform FP operations") }, \
349 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
350 N_("Use hardware floating point instructions") }, \
351 {"big-endian", ARM_FLAG_BIG_END, \
352 N_("Assume target CPU is configured as big endian") }, \
353 {"little-endian", -ARM_FLAG_BIG_END, \
354 N_("Assume target CPU is configured as little endian") }, \
355 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
356 N_("Assume big endian bytes, little endian words") }, \
357 {"thumb-interwork", ARM_FLAG_INTERWORK, \
358 N_("Support calls between Thumb and ARM instruction sets") }, \
359 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
360 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
361 N_("Generate a call to abort if a noreturn function returns")}, \
362 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
363 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
364 N_("Do not move instructions into a function's prologue") }, \
365 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
366 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
367 N_("Do not load the PIC register in function prologues") }, \
368 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
369 {"long-calls", ARM_FLAG_LONG_CALLS, \
370 N_("Generate call insns as indirect calls, if necessary") }, \
371 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
372 {"thumb", ARM_FLAG_THUMB, \
373 N_("Compile for the Thumb not the ARM") }, \
374 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
375 {"arm", -ARM_FLAG_THUMB, "" }, \
376 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
377 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
378 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
379 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
380 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
381 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
382 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
383 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
384 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
386 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
387 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
388 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
390 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
391 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
392 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
393 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
395 {"", TARGET_DEFAULT, "" } \
398 #define TARGET_OPTIONS \
400 {"cpu=", & arm_select[0].string, \
401 N_("Specify the name of the target CPU"), 0}, \
402 {"arch=", & arm_select[1].string, \
403 N_("Specify the name of the target architecture"), 0}, \
404 {"tune=", & arm_select[2].string, "", 0}, \
405 {"fpe=", & target_fpe_name, "", 0}, \
406 {"fp=", & target_fpe_name, "", 0}, \
407 {"fpu=", & target_fpu_name, \
408 N_("Specify the name of the target floating point hardware/format"), 0}, \
409 {"float-abi=", & target_float_abi_name, \
410 N_("Specify if floating point hardware should be used"), 0}, \
411 {"structure-size-boundary=", & structure_size_string, \
412 N_("Specify the minimum bit alignment of structures"), 0}, \
413 {"pic-register=", & arm_pic_register_string, \
414 N_("Specify the register to be used for PIC addressing"), 0}, \
415 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
418 /* Support for a compile-time default CPU, et cetera. The rules are:
419 --with-arch is ignored if -march or -mcpu are specified.
420 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
422 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
424 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
426 --with-fpu is ignored if -mfpu is specified.
427 --with-abi is ignored is -mabi is specified. */
428 #define OPTION_DEFAULT_SPECS \
429 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
430 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
431 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
433 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
434 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
435 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
437 struct arm_cpu_select
441 const struct processors * processors;
444 /* This is a magic array. If the user specifies a command line switch
445 which matches one of the entries in TARGET_OPTIONS then the corresponding
446 string pointer will be set to the value specified by the user. */
447 extern struct arm_cpu_select arm_select[];
455 /* Recast the program mode class to be the prog_mode attribute. */
456 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
458 extern enum prog_mode_type arm_prgmode;
460 /* Which floating point model to use. */
463 ARM_FP_MODEL_UNKNOWN,
464 /* FPA model (Hardware or software). */
466 /* Cirrus Maverick floating point model. */
467 ARM_FP_MODEL_MAVERICK,
468 /* VFP floating point model. */
472 extern enum arm_fp_model arm_fp_model;
474 /* Which floating point hardware is available. Also update
475 fp_model_for_fpu in arm.c when adding entries to this list. */
478 /* No FP hardware. */
480 /* Full FPA support. */
482 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
484 /* Emulated FPA hardware, Issue 3 emulator. */
486 /* Cirrus Maverick floating point co-processor. */
492 /* Recast the floating point class to be the floating point attribute. */
493 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
495 /* What type of floating point to tune for */
496 extern enum fputype arm_fpu_tune;
498 /* What type of floating point instructions are available */
499 extern enum fputype arm_fpu_arch;
504 ARM_FLOAT_ABI_SOFTFP,
508 extern enum float_abi_type arm_float_abi;
510 /* Which ABI to use. */
519 extern enum arm_abi_type arm_abi;
521 #ifndef ARM_DEFAULT_ABI
522 #define ARM_DEFAULT_ABI ARM_ABI_APCS
525 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
526 extern int arm_arch3m;
528 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
529 extern int arm_arch4;
531 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
532 extern int arm_arch5;
534 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
535 extern int arm_arch5e;
537 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
538 extern int arm_arch6;
540 /* Nonzero if this chip can benefit from load scheduling. */
541 extern int arm_ld_sched;
543 /* Nonzero if generating thumb code. */
544 extern int thumb_code;
546 /* Nonzero if this chip is a StrongARM. */
547 extern int arm_is_strong;
549 /* Nonzero if this chip is a Cirrus variant. */
550 extern int arm_arch_cirrus;
552 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
553 extern int arm_arch_iwmmxt;
555 /* Nonzero if this chip is an XScale. */
556 extern int arm_arch_xscale;
558 /* Nonzero if tuning for XScale */
559 extern int arm_tune_xscale;
561 /* Nonzero if this chip is an ARM6 or an ARM7. */
562 extern int arm_is_6_or_7;
564 #ifndef TARGET_DEFAULT
565 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
568 /* The frame pointer register used in gcc has nothing to do with debugging;
569 that is controlled by the APCS-FRAME option. */
570 #define CAN_DEBUG_WITHOUT_FP
572 #undef TARGET_MEM_FUNCTIONS
573 #define TARGET_MEM_FUNCTIONS 1
575 #define OVERRIDE_OPTIONS arm_override_options ()
577 /* Nonzero if PIC code requires explicit qualifiers to generate
578 PLT and GOT relocs rather than the assembler doing so implicitly.
579 Subtargets can override these if required. */
580 #ifndef NEED_GOT_RELOC
581 #define NEED_GOT_RELOC 0
583 #ifndef NEED_PLT_RELOC
584 #define NEED_PLT_RELOC 0
587 /* Nonzero if we need to refer to the GOT with a PC-relative
588 offset. In other words, generate
590 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
594 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
596 The default is true, which matches NetBSD. Subtargets can
597 override this if required. */
602 /* Target machine storage Layout. */
605 /* Define this macro if it is advisable to hold scalars in registers
606 in a wider mode than that declared by the program. In such cases,
607 the value is constrained to be within the bounds of the declared
608 type, but kept valid in the wider mode. The signedness of the
609 extension may differ from that of the type. */
611 /* It is far faster to zero extend chars than to sign extend them */
613 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
614 if (GET_MODE_CLASS (MODE) == MODE_INT \
615 && GET_MODE_SIZE (MODE) < 4) \
617 if (MODE == QImode) \
619 else if (MODE == HImode) \
620 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
624 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
625 if (GET_MODE_CLASS (MODE) == MODE_INT \
626 && GET_MODE_SIZE (MODE) < 4) \
629 /* Define this if most significant bit is lowest numbered
630 in instructions that operate on numbered bit-fields. */
631 #define BITS_BIG_ENDIAN 0
633 /* Define this if most significant byte of a word is the lowest numbered.
634 Most ARM processors are run in little endian mode, so that is the default.
635 If you want to have it run-time selectable, change the definition in a
636 cover file to be TARGET_BIG_ENDIAN. */
637 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
639 /* Define this if most significant word of a multiword number is the lowest
641 This is always false, even when in big-endian mode. */
642 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
644 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
645 on processor pre-defineds when compiling libgcc2.c. */
646 #if defined(__ARMEB__) && !defined(__ARMWEL__)
647 #define LIBGCC2_WORDS_BIG_ENDIAN 1
649 #define LIBGCC2_WORDS_BIG_ENDIAN 0
652 /* Define this if most significant word of doubles is the lowest numbered.
653 The rules are different based on whether or not we use FPA-format,
654 VFP-format or some other floating point co-processor's format doubles. */
655 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
657 #define UNITS_PER_WORD 4
659 /* True if natural alignment is used for doubleword types. */
660 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
662 #define DOUBLEWORD_ALIGNMENT 64
664 #define PARM_BOUNDARY 32
666 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
668 #define PREFERRED_STACK_BOUNDARY \
669 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
671 #define FUNCTION_BOUNDARY 32
673 /* The lowest bit is used to indicate Thumb-mode functions, so the
674 vbit must go into the delta field of pointers to member
676 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
678 #define EMPTY_FIELD_BOUNDARY 32
680 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
682 /* XXX Blah -- this macro is used directly by libobjc. Since it
683 supports no vector modes, cut out the complexity and fall back
684 on BIGGEST_FIELD_ALIGNMENT. */
685 #ifdef IN_TARGET_LIBS
686 #define BIGGEST_FIELD_ALIGNMENT 64
689 /* Make strings word-aligned so strcpy from constants will be faster. */
690 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
692 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
693 ((TREE_CODE (EXP) == STRING_CST \
694 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
695 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
697 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
698 value set in previous versions of this toolchain was 8, which produces more
699 compact structures. The command line option -mstructure_size_boundary=<n>
700 can be used to change this value. For compatibility with the ARM SDK
701 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
702 0020D) page 2-20 says "Structures are aligned on word boundaries".
703 The AAPCS specifies a value of 8. */
704 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
705 extern int arm_structure_size_boundary;
707 /* This is the value used to initialize arm_structure_size_boundary. If a
708 particular arm target wants to change the default value it should change
709 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
710 for an example of this. */
711 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
712 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
715 /* Used when parsing command line option -mstructure_size_boundary. */
716 extern const char * structure_size_string;
718 /* Nonzero if move instructions will actually fail to work
719 when given unaligned data. */
720 #define STRICT_ALIGNMENT 1
722 /* wchar_t is unsigned under the AAPCS. */
724 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
726 #define WCHAR_TYPE_SIZE BITS_PER_WORD
730 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
733 /* AAPCS requires that structure alignment is affected by bitfields. */
734 #ifndef PCC_BITFIELD_TYPE_MATTERS
735 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
739 /* Standard register usage. */
741 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
742 (S - saved over call).
744 r0 * argument word/integer result
747 r4-r8 S register variable
748 r9 S (rfp) register variable (real frame pointer)
750 r10 F S (sl) stack limit (used by -mapcs-stack-check)
751 r11 F S (fp) argument pointer
752 r12 (ip) temp workspace
753 r13 F S (sp) lower end of current stack frame
754 r14 (lr) link address/workspace
755 r15 F (pc) program counter
757 f0 floating point result
758 f1-f3 floating point scratch
760 f4-f7 S floating point variable
762 cc This is NOT a real register, but is used internally
763 to represent things that use or set the condition
765 sfp This isn't either. It is used during rtl generation
766 since the offset between the frame pointer and the
767 auto's isn't known until after register allocation.
768 afp Nor this, we only need this because of non-local
769 goto. Without it fp appears to be used and the
770 elimination code won't get rid of sfp. It tracks
771 fp exactly at all times.
773 *: See CONDITIONAL_REGISTER_USAGE */
776 mvf0 Cirrus floating point result
777 mvf1-mvf3 Cirrus floating point scratch
778 mvf4-mvf15 S Cirrus floating point variable. */
780 /* s0-s15 VFP scratch (aka d0-d7).
781 s16-s31 S VFP variable (aka d8-d15).
782 vfpcc Not a real register. Represents the VFP condition
785 /* The stack backtrace structure is as follows:
786 fp points to here: | save code pointer | [fp]
787 | return link value | [fp, #-4]
788 | return sp value | [fp, #-8]
789 | return fp value | [fp, #-12]
790 [| saved r10 value |]
801 [| saved f7 value |] three words
802 [| saved f6 value |] three words
803 [| saved f5 value |] three words
804 [| saved f4 value |] three words
805 r0-r3 are not normally saved in a C function. */
807 /* 1 for registers that have pervasive standard uses
808 and are not available for the register allocator. */
809 #define FIXED_REGISTERS \
827 /* 1 for registers not available across function calls.
828 These must include the FIXED_REGISTERS and also any
829 registers that can be used without being saved.
830 The latter must include the registers where values are returned
831 and the register where structure-value addresses are passed.
832 Aside from that, you can include as many other registers as you like.
833 The CC is not preserved over function calls on the ARM 6, so it is
834 easier to assume this for all. SFP is preserved, since FP is. */
835 #define CALL_USED_REGISTERS \
853 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
854 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
857 #define CONDITIONAL_REGISTER_USAGE \
861 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
863 for (regno = FIRST_FPA_REGNUM; \
864 regno <= LAST_FPA_REGNUM; ++regno) \
865 fixed_regs[regno] = call_used_regs[regno] = 1; \
868 if (TARGET_THUMB && optimize_size) \
870 /* When optimizing for size, it's better not to use \
871 the HI regs, because of the overhead of stacking \
873 for (regno = FIRST_HI_REGNUM; \
874 regno <= LAST_HI_REGNUM; ++regno) \
875 fixed_regs[regno] = call_used_regs[regno] = 1; \
878 /* The link register can be clobbered by any branch insn, \
879 but we have no way to track that at present, so mark \
880 it as unavailable. */ \
882 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
884 if (TARGET_ARM && TARGET_HARD_FLOAT) \
886 if (TARGET_MAVERICK) \
888 for (regno = FIRST_FPA_REGNUM; \
889 regno <= LAST_FPA_REGNUM; ++ regno) \
890 fixed_regs[regno] = call_used_regs[regno] = 1; \
891 for (regno = FIRST_CIRRUS_FP_REGNUM; \
892 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
894 fixed_regs[regno] = 0; \
895 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
900 for (regno = FIRST_VFP_REGNUM; \
901 regno <= LAST_VFP_REGNUM; ++ regno) \
903 fixed_regs[regno] = 0; \
904 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
909 if (TARGET_REALLY_IWMMXT) \
911 regno = FIRST_IWMMXT_GR_REGNUM; \
912 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
913 and wCG1 as call-preserved registers. The 2002/11/21 \
914 revision changed this so that all wCG registers are \
915 scratch registers. */ \
916 for (regno = FIRST_IWMMXT_GR_REGNUM; \
917 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
918 fixed_regs[regno] = call_used_regs[regno] = 0; \
919 /* The XScale ABI has wR0 - wR9 as scratch registers, \
920 the rest as call-preserved registers. */ \
921 for (regno = FIRST_IWMMXT_REGNUM; \
922 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
924 fixed_regs[regno] = 0; \
925 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
929 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
931 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
932 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
934 else if (TARGET_APCS_STACK) \
936 fixed_regs[10] = 1; \
937 call_used_regs[10] = 1; \
939 if (TARGET_APCS_FRAME) \
941 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
942 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
944 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
947 /* These are a couple of extensions to the formats accepted
949 %@ prints out ASM_COMMENT_START
950 %r prints out REGISTER_PREFIX reg_names[arg] */
951 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
953 fputs (ASM_COMMENT_START, FILE); \
957 fputs (REGISTER_PREFIX, FILE); \
958 fputs (reg_names [va_arg (ARGS, int)], FILE); \
961 /* Round X up to the nearest word. */
962 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
964 /* Convert fron bytes to ints. */
965 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
967 /* The number of (integer) registers required to hold a quantity of type MODE.
968 Also used for VFP registers. */
969 #define ARM_NUM_REGS(MODE) \
970 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
972 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
973 #define ARM_NUM_REGS2(MODE, TYPE) \
974 ARM_NUM_INTS ((MODE) == BLKmode ? \
975 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
977 /* The number of (integer) argument register available. */
978 #define NUM_ARG_REGS 4
980 /* Return the register number of the N'th (integer) argument. */
981 #define ARG_REGISTER(N) (N - 1)
983 /* Specify the registers used for certain standard purposes.
984 The values of these macros are register numbers. */
986 /* The number of the last argument register. */
987 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
989 /* The numbers of the Thumb register ranges. */
990 #define FIRST_LO_REGNUM 0
991 #define LAST_LO_REGNUM 7
992 #define FIRST_HI_REGNUM 8
993 #define LAST_HI_REGNUM 11
995 /* The register that holds the return address in exception handlers. */
996 #define EXCEPTION_LR_REGNUM 2
998 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
999 as an invisible last argument (possible since varargs don't exist in
1000 Pascal), so the following is not true. */
1001 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1003 /* Define this to be where the real frame pointer is if it is not possible to
1004 work out the offset between the frame pointer and the automatic variables
1005 until after register allocation has taken place. FRAME_POINTER_REGNUM
1006 should point to a special register that we will make sure is eliminated.
1008 For the Thumb we have another problem. The TPCS defines the frame pointer
1009 as r11, and GCC believes that it is always possible to use the frame pointer
1010 as base register for addressing purposes. (See comments in
1011 find_reloads_address()). But - the Thumb does not allow high registers,
1012 including r11, to be used as base address registers. Hence our problem.
1014 The solution used here, and in the old thumb port is to use r7 instead of
1015 r11 as the hard frame pointer and to have special code to generate
1016 backtrace structures on the stack (if required to do so via a command line
1017 option) using r11. This is the only 'user visible' use of r11 as a frame
1019 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1020 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1022 #define HARD_FRAME_POINTER_REGNUM \
1024 ? ARM_HARD_FRAME_POINTER_REGNUM \
1025 : THUMB_HARD_FRAME_POINTER_REGNUM)
1027 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1029 /* Register to use for pushing function arguments. */
1030 #define STACK_POINTER_REGNUM SP_REGNUM
1032 /* ARM floating pointer registers. */
1033 #define FIRST_FPA_REGNUM 16
1034 #define LAST_FPA_REGNUM 23
1036 #define FIRST_IWMMXT_GR_REGNUM 43
1037 #define LAST_IWMMXT_GR_REGNUM 46
1038 #define FIRST_IWMMXT_REGNUM 47
1039 #define LAST_IWMMXT_REGNUM 62
1040 #define IS_IWMMXT_REGNUM(REGNUM) \
1041 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1042 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1043 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1045 /* Base register for access to local variables of the function. */
1046 #define FRAME_POINTER_REGNUM 25
1048 /* Base register for access to arguments of the function. */
1049 #define ARG_POINTER_REGNUM 26
1051 #define FIRST_CIRRUS_FP_REGNUM 27
1052 #define LAST_CIRRUS_FP_REGNUM 42
1053 #define IS_CIRRUS_REGNUM(REGNUM) \
1054 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1056 #define FIRST_VFP_REGNUM 63
1057 #define LAST_VFP_REGNUM 94
1058 #define IS_VFP_REGNUM(REGNUM) \
1059 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1061 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1062 /* + 16 Cirrus registers take us up to 43. */
1063 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1064 /* VFP adds 32 + 1 more. */
1065 #define FIRST_PSEUDO_REGISTER 96
1067 /* Value should be nonzero if functions must have frame pointers.
1068 Zero means the frame pointer need not be set up (and parms may be accessed
1069 via the stack pointer) in functions that seem suitable.
1070 If we have to have a frame pointer we might as well make use of it.
1071 APCS says that the frame pointer does not need to be pushed in leaf
1072 functions, or simple tail call functions. */
1073 #define FRAME_POINTER_REQUIRED \
1074 (current_function_has_nonlocal_label \
1075 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1077 /* Return number of consecutive hard regs needed starting at reg REGNO
1078 to hold something of mode MODE.
1079 This is ordinarily the length in words of a value of mode MODE
1080 but can be less for certain modes in special long registers.
1082 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1084 #define HARD_REGNO_NREGS(REGNO, MODE) \
1086 && REGNO >= FIRST_FPA_REGNUM \
1087 && REGNO != FRAME_POINTER_REGNUM \
1088 && REGNO != ARG_POINTER_REGNUM) \
1089 && !IS_VFP_REGNUM (REGNO) \
1090 ? 1 : ARM_NUM_REGS (MODE))
1092 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1093 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1094 arm_hard_regno_mode_ok ((REGNO), (MODE))
1096 /* Value is 1 if it is a good idea to tie two pseudo registers
1097 when one has mode MODE1 and one has mode MODE2.
1098 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1099 for any hard reg, then this must be 0 for correct output. */
1100 #define MODES_TIEABLE_P(MODE1, MODE2) \
1101 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1103 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1104 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1106 #define VALID_IWMMXT_REG_MODE(MODE) \
1107 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1109 /* The order in which register should be allocated. It is good to use ip
1110 since no saving is required (though calls clobber it) and it never contains
1111 function parameters. It is quite good to use lr since other calls may
1112 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1113 least likely to contain a function parameter; in addition results are
1116 #define REG_ALLOC_ORDER \
1118 3, 2, 1, 0, 12, 14, 4, 5, \
1119 6, 7, 8, 10, 9, 11, 13, 15, \
1120 16, 17, 18, 19, 20, 21, 22, 23, \
1121 27, 28, 29, 30, 31, 32, 33, 34, \
1122 35, 36, 37, 38, 39, 40, 41, 42, \
1123 43, 44, 45, 46, 47, 48, 49, 50, \
1124 51, 52, 53, 54, 55, 56, 57, 58, \
1127 78, 77, 76, 75, 74, 73, 72, 71, \
1128 70, 69, 68, 67, 66, 65, 64, 63, \
1129 79, 80, 81, 82, 83, 84, 85, 86, \
1130 87, 88, 89, 90, 91, 92, 93, 94, \
1134 /* Interrupt functions can only use registers that have already been
1135 saved by the prologue, even if they would normally be
1137 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1138 (! IS_INTERRUPT (cfun->machine->func_type) || \
1139 regs_ever_live[DST])
1141 /* Register and constant classes. */
1143 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1144 Now that the Thumb is involved it has become more complicated. */
1164 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1166 /* Give names of register classes as strings for dump file. */
1167 #define REG_CLASS_NAMES \
1185 /* Define which registers fit in which classes.
1186 This is an initializer for a vector of HARD_REG_SET
1187 of length N_REG_CLASSES. */
1188 #define REG_CLASS_CONTENTS \
1190 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1191 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1192 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1193 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1194 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1195 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1196 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1197 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1198 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1199 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1200 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1201 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1202 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1203 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1206 /* The same information, inverted:
1207 Return the class number of the smallest class containing
1208 reg number REGNO. This could be a conditional expression
1209 or could index an array. */
1210 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1212 /* FPA registers can't do subreg as all values are reformatted to internal
1213 precision. VFP registers may only be accessed in the mode they
1215 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1216 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1217 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1218 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1221 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1222 using r0-r4 for function arguments, r7 for the stack frame and don't
1223 have enough left over to do doubleword arithmetic. */
1224 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1225 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1226 || (CLASS) == CC_REG)
1228 /* The class value for index registers, and the one for base regs. */
1229 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1230 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1232 /* For the Thumb the high registers cannot be used as base registers
1233 when addressing quantities in QI or HI mode; if we don't know the
1234 mode, then we must be conservative. After reload we must also be
1235 conservative, since we can't support SP+reg addressing, and we
1236 can't fix up any bad substitutions. */
1237 #define MODE_BASE_REG_CLASS(MODE) \
1238 (TARGET_ARM ? GENERAL_REGS : \
1239 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1241 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1242 registers explicitly used in the rtl to be used as spill registers
1243 but prevents the compiler from extending the lifetime of these
1245 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1247 /* Get reg_class from a letter such as appears in the machine description.
1248 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1249 ARM, but several more letters for the Thumb. */
1250 #define REG_CLASS_FROM_LETTER(C) \
1251 ( (C) == 'f' ? FPA_REGS \
1252 : (C) == 'v' ? CIRRUS_REGS \
1253 : (C) == 'w' ? VFP_REGS \
1254 : (C) == 'y' ? IWMMXT_REGS \
1255 : (C) == 'z' ? IWMMXT_GR_REGS \
1256 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1257 : TARGET_ARM ? NO_REGS \
1258 : (C) == 'h' ? HI_REGS \
1259 : (C) == 'b' ? BASE_REGS \
1260 : (C) == 'k' ? STACK_REG \
1261 : (C) == 'c' ? CC_REG \
1264 /* The letters I, J, K, L and M in a register constraint string
1265 can be used to stand for particular ranges of immediate operands.
1266 This macro defines what the ranges are.
1267 C is the letter, and VALUE is a constant value.
1268 Return 1 if VALUE is in the range specified by C.
1269 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1270 J: valid indexing constants.
1271 K: ~value ok in rhs argument of data operand.
1272 L: -value ok in rhs argument of data operand.
1273 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1274 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1275 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1276 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1277 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1278 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1279 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1280 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1283 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1284 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1285 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1286 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1287 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1288 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1289 && ((VAL) & 3) == 0) : \
1290 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1291 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1294 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1296 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1298 /* Constant letter 'G' for the FP immediate constants.
1299 'H' means the same constant negated. */
1300 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1301 ((C) == 'G' ? arm_const_double_rtx (X) : \
1302 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1304 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1306 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1308 /* For the ARM, `Q' means that this is a memory operand that is just
1309 an offset from a register.
1310 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1311 address. This means that the symbol is in the text segment and can be
1312 accessed without using a load.
1313 'U' Prefixes an extended memory constraint where:
1314 'Uv' is an address valid for VFP load/store insns.
1315 'Uy' is an address valid for iwmmxt load/store insns.
1316 'Uq' is an address valid for ldrsb. */
1318 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1319 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1320 && GET_CODE (XEXP (OP, 0)) == REG) : \
1321 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1322 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1323 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1324 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1325 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1326 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1327 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1328 ((C) == 'U' && (STR)[1] == 'q') \
1329 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1332 #define CONSTRAINT_LEN(C,STR) \
1333 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1335 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1336 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1337 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1339 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1341 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1342 : EXTRA_CONSTRAINT_THUMB (X, C))
1344 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1346 /* Given an rtx X being reloaded into a reg required to be
1347 in class CLASS, return the class of reg to actually use.
1348 In general this is just CLASS, but for the Thumb we prefer
1349 a LO_REGS class or a subset. */
1350 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1351 (TARGET_ARM ? (CLASS) : \
1352 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1354 /* Must leave BASE_REGS reloads alone */
1355 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1356 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1357 ? ((true_regnum (X) == -1 ? LO_REGS \
1358 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1362 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1363 ((CLASS) != LO_REGS \
1364 ? ((true_regnum (X) == -1 ? LO_REGS \
1365 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1369 /* Return the register class of a scratch register needed to copy IN into
1370 or out of a register in CLASS in MODE. If it can be done directly,
1371 NO_REGS is returned. */
1372 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1373 /* Restrict which direct reloads are allowed for VFP regs. */ \
1374 ((TARGET_VFP && TARGET_HARD_FLOAT \
1375 && (CLASS) == VFP_REGS) \
1376 ? vfp_secondary_reload_class (MODE, X) \
1378 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1379 ? GENERAL_REGS : NO_REGS) \
1380 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1382 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1383 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1384 /* Restrict which direct reloads are allowed for VFP regs. */ \
1385 ((TARGET_VFP && TARGET_HARD_FLOAT \
1386 && (CLASS) == VFP_REGS) \
1387 ? vfp_secondary_reload_class (MODE, X) : \
1388 /* Cannot load constants into Cirrus registers. */ \
1389 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1390 && (CLASS) == CIRRUS_REGS \
1391 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1394 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1395 && CONSTANT_P (X)) \
1397 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1398 && (GET_CODE (X) == MEM \
1399 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1400 && true_regnum (X) == -1))) \
1401 ? GENERAL_REGS : NO_REGS) \
1402 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1404 /* Try a machine-dependent way of reloading an illegitimate address
1405 operand. If we find one, push the reload and jump to WIN. This
1406 macro is used in only one place: `find_reloads_address' in reload.c.
1408 For the ARM, we wish to handle large displacements off a base
1409 register by splitting the addend across a MOV and the mem insn.
1410 This can cut the number of reloads needed. */
1411 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1414 if (GET_CODE (X) == PLUS \
1415 && GET_CODE (XEXP (X, 0)) == REG \
1416 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1417 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1418 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1420 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1421 HOST_WIDE_INT low, high; \
1423 if (MODE == DImode || (TARGET_SOFT_FLOAT && TARGET_FPA \
1424 && MODE == DFmode)) \
1425 low = ((val & 0xf) ^ 0x8) - 0x8; \
1426 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1427 /* Need to be careful, -256 is not a valid offset. */ \
1428 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1429 else if (MODE == SImode \
1430 || (MODE == SFmode && TARGET_SOFT_FLOAT && TARGET_FPA) \
1431 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1432 /* Need to be careful, -4096 is not a valid offset. */ \
1433 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1434 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1435 /* Need to be careful, -256 is not a valid offset. */ \
1436 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1437 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1438 && TARGET_HARD_FLOAT && TARGET_FPA) \
1439 /* Need to be careful, -1024 is not a valid offset. */ \
1440 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1444 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1445 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1446 - (unsigned HOST_WIDE_INT) 0x80000000); \
1447 /* Check for overflow or zero */ \
1448 if (low == 0 || high == 0 || (high + low != val)) \
1451 /* Reload the high part into a base reg; leave the low part \
1453 X = gen_rtx_PLUS (GET_MODE (X), \
1454 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1457 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1458 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1459 VOIDmode, 0, 0, OPNUM, TYPE); \
1465 /* XXX If an HImode FP+large_offset address is converted to an HImode
1466 SP+large_offset address, then reload won't know how to fix it. It sees
1467 only that SP isn't valid for HImode, and so reloads the SP into an index
1468 register, but the resulting address is still invalid because the offset
1469 is too big. We fix it here instead by reloading the entire address. */
1470 /* We could probably achieve better results by defining PROMOTE_MODE to help
1471 cope with the variances between the Thumb's signed and unsigned byte and
1472 halfword load instructions. */
1473 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1475 if (GET_CODE (X) == PLUS \
1476 && GET_MODE_SIZE (MODE) < 4 \
1477 && GET_CODE (XEXP (X, 0)) == REG \
1478 && XEXP (X, 0) == stack_pointer_rtx \
1479 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1480 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1484 push_reload (orig_X, NULL_RTX, &X, NULL, \
1485 MODE_BASE_REG_CLASS (MODE), \
1486 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1491 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1493 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1495 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1497 /* Return the maximum number of consecutive registers
1498 needed to represent mode MODE in a register of class CLASS.
1499 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1500 #define CLASS_MAX_NREGS(CLASS, MODE) \
1501 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1503 /* If defined, gives a class of registers that cannot be used as the
1504 operand of a SUBREG that changes the mode of the object illegally. */
1506 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1507 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1509 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1510 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1511 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1512 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1513 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1514 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1515 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1516 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1517 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1520 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1522 /* Stack layout; function entry, exit and calling. */
1524 /* Define this if pushing a word on the stack
1525 makes the stack pointer a smaller address. */
1526 #define STACK_GROWS_DOWNWARD 1
1528 /* Define this if the nominal address of the stack frame
1529 is at the high-address end of the local variables;
1530 that is, each additional local variable allocated
1531 goes at a more negative offset in the frame. */
1532 #define FRAME_GROWS_DOWNWARD 1
1534 /* Offset within stack frame to start allocating local variables at.
1535 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1536 first local allocated. Otherwise, it is the offset to the BEGINNING
1537 of the first local allocated. */
1538 #define STARTING_FRAME_OFFSET 0
1540 /* If we generate an insn to push BYTES bytes,
1541 this says how many the stack pointer really advances by. */
1542 /* The push insns do not do this rounding implicitly.
1543 So don't define this. */
1544 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1546 /* Define this if the maximum size of all the outgoing args is to be
1547 accumulated and pushed during the prologue. The amount can be
1548 found in the variable current_function_outgoing_args_size. */
1549 #define ACCUMULATE_OUTGOING_ARGS 1
1551 /* Offset of first parameter from the argument pointer register value. */
1552 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1554 /* Value is the number of byte of arguments automatically
1555 popped when returning from a subroutine call.
1556 FUNDECL is the declaration node of the function (as a tree),
1557 FUNTYPE is the data type of the function (as a tree),
1558 or for a library call it is an identifier node for the subroutine name.
1559 SIZE is the number of bytes of arguments passed on the stack.
1561 On the ARM, the caller does not pop any of its arguments that were passed
1563 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1565 /* Define how to find the value returned by a library function
1566 assuming the value has mode MODE. */
1567 #define LIBCALL_VALUE(MODE) \
1568 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1569 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1570 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1571 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1572 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1573 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1574 : TARGET_IWMMXT_ABI && VECTOR_MODE_SUPPORTED_P (MODE) \
1575 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1576 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1578 /* Define how to find the value returned by a function.
1579 VALTYPE is the data type of the value (as a tree).
1580 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1581 otherwise, FUNC is 0. */
1582 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1583 arm_function_value (VALTYPE, FUNC);
1585 /* 1 if N is a possible register number for a function value.
1586 On the ARM, only r0 and f0 can return results. */
1587 /* On a Cirrus chip, mvf0 can return results. */
1588 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1589 ((REGNO) == ARG_REGISTER (1) \
1590 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1591 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1592 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1593 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1594 && TARGET_HARD_FLOAT && TARGET_FPA))
1596 /* How large values are returned */
1597 /* A C expression which can inhibit the returning of certain function values
1598 in registers, based on the type of value. */
1599 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1601 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1602 values must be in memory. On the ARM, they need only do so if larger
1603 than a word, or if they contain elements offset from zero in the struct. */
1604 #define DEFAULT_PCC_STRUCT_RETURN 0
1606 /* Flags for the call/call_value rtl operations set up by function_arg. */
1607 #define CALL_NORMAL 0x00000000 /* No special processing. */
1608 #define CALL_LONG 0x00000001 /* Always call indirect. */
1609 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1611 /* These bits describe the different types of function supported
1612 by the ARM backend. They are exclusive. ie a function cannot be both a
1613 normal function and an interworked function, for example. Knowing the
1614 type of a function is important for determining its prologue and
1616 Note value 7 is currently unassigned. Also note that the interrupt
1617 function types all have bit 2 set, so that they can be tested for easily.
1618 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1619 machine_function structure is initialized (to zero) func_type will
1620 default to unknown. This will force the first use of arm_current_func_type
1621 to call arm_compute_func_type. */
1622 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1623 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1624 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1625 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1626 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1627 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1628 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1630 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1632 /* In addition functions can have several type modifiers,
1633 outlined by these bit masks: */
1634 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1635 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1636 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1637 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1639 /* Some macros to test these flags. */
1640 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1641 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1642 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1643 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1644 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1647 /* Structure used to hold the function stack frame layout. Offsets are
1648 relative to the stack pointer on function entry. Positive offsets are
1649 in the direction of stack growth.
1650 Only soft_frame is used in thumb mode. */
1652 typedef struct arm_stack_offsets GTY(())
1654 int saved_args; /* ARG_POINTER_REGNUM. */
1655 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1657 int soft_frame; /* FRAME_POINTER_REGNUM. */
1658 int outgoing_args; /* STACK_POINTER_REGNUM. */
1662 /* A C structure for machine-specific, per-function data.
1663 This is added to the cfun structure. */
1664 typedef struct machine_function GTY(())
1666 /* Additional stack adjustment in __builtin_eh_throw. */
1667 rtx eh_epilogue_sp_ofs;
1668 /* Records if LR has to be saved for far jumps. */
1670 /* Records if ARG_POINTER was ever live. */
1671 int arg_pointer_live;
1672 /* Records if the save of LR has been eliminated. */
1673 int lr_save_eliminated;
1674 /* The size of the stack frame. Only valid after reload. */
1675 arm_stack_offsets stack_offsets;
1676 /* Records the type of the current function. */
1677 unsigned long func_type;
1678 /* Record if the function has a variable argument list. */
1679 int uses_anonymous_args;
1680 /* Records if sibcalls are blocked because an argument
1681 register is needed to preserve stack alignment. */
1682 int sibcall_blocked;
1686 /* A C type for declaring a variable that is used as the first argument of
1687 `FUNCTION_ARG' and other related values. For some target machines, the
1688 type `int' suffices and can hold the number of bytes of argument so far. */
1691 /* This is the number of registers of arguments scanned so far. */
1693 /* This is the number of iWMMXt register arguments scanned so far. */
1697 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1702 /* Define where to put the arguments to a function.
1703 Value is zero to push the argument on the stack,
1704 or a hard register in which to store the argument.
1706 MODE is the argument's machine mode.
1707 TYPE is the data type of the argument (as a tree).
1708 This is null for libcalls where that information may
1710 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1711 the preceding args and about the function being called.
1712 NAMED is nonzero if this argument is a named parameter
1713 (otherwise it is an extra parameter matching an ellipsis).
1715 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1716 other arguments are passed on the stack. If (NAMED == 0) (which happens
1717 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1718 defined), say it is passed in the stack (function_prologue will
1719 indeed make it pass in the stack if necessary). */
1720 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1721 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1723 /* For an arg passed partly in registers and partly in memory,
1724 this is the number of registers used.
1725 For args passed entirely in registers or entirely in memory, zero. */
1726 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1727 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1728 NUM_ARG_REGS > (CUM).nregs \
1729 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1730 && (CUM).can_split) \
1731 ? NUM_ARG_REGS - (CUM).nregs : 0)
1733 /* A C expression that indicates when an argument must be passed by
1734 reference. If nonzero for an argument, a copy of that argument is
1735 made in memory and a pointer to the argument is passed instead of
1736 the argument itself. The pointer is passed in whatever way is
1737 appropriate for passing a pointer to that type. */
1738 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1739 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1741 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1742 for a call to a function whose data type is FNTYPE.
1743 For a library call, FNTYPE is 0.
1744 On the ARM, the offset starts at 0. */
1745 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1746 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1748 /* Update the data in CUM to advance over an argument
1749 of mode MODE and data type TYPE.
1750 (TYPE is null for libcalls where that information may not be available.) */
1751 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1753 if (VECTOR_MODE_SUPPORTED_P (MODE) \
1754 && (CUM).named_count > (CUM).nargs) \
1755 (CUM).iwmmxt_nregs += 1; \
1757 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1759 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1760 argument with the specified mode and type. If it is not defined,
1761 `PARM_BOUNDARY' is used for all arguments. */
1762 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1763 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1764 ? DOUBLEWORD_ALIGNMENT \
1767 /* 1 if N is a possible register number for function argument passing.
1768 On the ARM, r0-r3 are used to pass args. */
1769 #define FUNCTION_ARG_REGNO_P(REGNO) \
1770 (IN_RANGE ((REGNO), 0, 3) \
1771 || (TARGET_IWMMXT_ABI \
1772 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1774 /* Implement `va_arg'. */
1775 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1776 arm_va_arg (valist, type)
1779 /* If your target environment doesn't prefix user functions with an
1780 underscore, you may wish to re-define this to prevent any conflicts.
1781 e.g. AOF may prefix mcount with an underscore. */
1782 #ifndef ARM_MCOUNT_NAME
1783 #define ARM_MCOUNT_NAME "*mcount"
1786 /* Call the function profiler with a given profile label. The Acorn
1787 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1788 On the ARM the full profile code will look like:
1797 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1798 will output the .text section.
1800 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1801 ``prof'' doesn't seem to mind about this!
1803 Note - this version of the code is designed to work in both ARM and
1805 #ifndef ARM_FUNCTION_PROFILER
1806 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1811 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1812 IP_REGNUM, LR_REGNUM); \
1813 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1814 fputc ('\n', STREAM); \
1815 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1816 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1817 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1821 #ifdef THUMB_FUNCTION_PROFILER
1822 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1824 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1826 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1828 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1829 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1832 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1833 the stack pointer does not matter. The value is tested only in
1834 functions that have frame pointers.
1835 No definition is equivalent to always zero.
1837 On the ARM, the function epilogue recovers the stack pointer from the
1839 #define EXIT_IGNORE_STACK 1
1841 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1843 /* Determine if the epilogue should be output as RTL.
1844 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1845 #define USE_RETURN_INSN(ISCOND) \
1846 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1848 /* Definitions for register eliminations.
1850 This is an array of structures. Each structure initializes one pair
1851 of eliminable registers. The "from" register number is given first,
1852 followed by "to". Eliminations of the same "from" register are listed
1853 in order of preference.
1855 We have two registers that can be eliminated on the ARM. First, the
1856 arg pointer register can often be eliminated in favor of the stack
1857 pointer register. Secondly, the pseudo frame pointer register can always
1858 be eliminated; it is replaced with either the stack or the real frame
1859 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1860 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1862 #define ELIMINABLE_REGS \
1863 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1864 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1865 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1866 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1867 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1868 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1869 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1871 /* Given FROM and TO register numbers, say whether this elimination is
1872 allowed. Frame pointer elimination is automatically handled.
1874 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1875 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1876 pointer, we must eliminate FRAME_POINTER_REGNUM into
1877 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1878 ARG_POINTER_REGNUM. */
1879 #define CAN_ELIMINATE(FROM, TO) \
1880 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1881 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1882 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1883 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1886 #define THUMB_REG_PUSHED_P(reg) \
1887 (regs_ever_live [reg] \
1888 && (! call_used_regs [reg] \
1889 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1890 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1892 /* Define the offset between two registers, one to be eliminated, and the
1893 other its replacement, at the start of a routine. */
1894 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1896 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1898 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1900 /* Special case handling of the location of arguments passed on the stack. */
1901 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1903 /* Initialize data used by insn expanders. This is called from insn_emit,
1904 once for every function before code is generated. */
1905 #define INIT_EXPANDERS arm_init_expanders ()
1907 /* Output assembler code for a block containing the constant parts
1908 of a trampoline, leaving space for the variable parts.
1910 On the ARM, (if r8 is the static chain regnum, and remembering that
1911 referencing pc adds an offset of 8) the trampoline looks like:
1914 .word static chain value
1915 .word function's address
1916 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1917 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1919 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1920 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1921 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1922 PC_REGNUM, PC_REGNUM); \
1923 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1924 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1927 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1928 Why - because it is easier. This code will always be branched to via
1929 a BX instruction and since the compiler magically generates the address
1930 of the function the linker has no opportunity to ensure that the
1931 bottom bit is set. Thus the processor will be in ARM mode when it
1932 reaches this code. So we duplicate the ARM trampoline code and add
1933 a switch into Thumb mode as well. */
1934 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1936 fprintf (FILE, "\t.code 32\n"); \
1937 fprintf (FILE, ".Ltrampoline_start:\n"); \
1938 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1939 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1940 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1941 IP_REGNUM, PC_REGNUM); \
1942 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1943 IP_REGNUM, IP_REGNUM); \
1944 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1945 fprintf (FILE, "\t.word\t0\n"); \
1946 fprintf (FILE, "\t.word\t0\n"); \
1947 fprintf (FILE, "\t.code 16\n"); \
1950 #define TRAMPOLINE_TEMPLATE(FILE) \
1952 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1954 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1956 /* Length in units of the trampoline for entering a nested function. */
1957 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1959 /* Alignment required for a trampoline in bits. */
1960 #define TRAMPOLINE_ALIGNMENT 32
1962 /* Emit RTL insns to initialize the variable parts of a trampoline.
1963 FNADDR is an RTX for the address of the function's pure code.
1964 CXT is an RTX for the static chain value for the function. */
1965 #ifndef INITIALIZE_TRAMPOLINE
1966 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1968 emit_move_insn (gen_rtx_MEM (SImode, \
1969 plus_constant (TRAMP, \
1970 TARGET_ARM ? 8 : 16)), \
1972 emit_move_insn (gen_rtx_MEM (SImode, \
1973 plus_constant (TRAMP, \
1974 TARGET_ARM ? 12 : 20)), \
1980 /* Addressing modes, and classification of registers for them. */
1981 #define HAVE_POST_INCREMENT 1
1982 #define HAVE_PRE_INCREMENT TARGET_ARM
1983 #define HAVE_POST_DECREMENT TARGET_ARM
1984 #define HAVE_PRE_DECREMENT TARGET_ARM
1985 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1986 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1987 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1988 #define HAVE_POST_MODIFY_REG TARGET_ARM
1990 /* Macros to check register numbers against specific register classes. */
1992 /* These assume that REGNO is a hard or pseudo reg number.
1993 They give nonzero only if REGNO is a hard reg of the suitable class
1994 or a pseudo reg currently allocated to a suitable hard reg.
1995 Since they use reg_renumber, they are safe only once reg_renumber
1996 has been allocated, which happens in local-alloc.c. */
1997 #define TEST_REGNO(R, TEST, VALUE) \
1998 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2000 /* On the ARM, don't allow the pc to be used. */
2001 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2002 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2003 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2004 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2006 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2007 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2008 || (GET_MODE_SIZE (MODE) >= 4 \
2009 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2011 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2013 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2014 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2016 /* For ARM code, we don't care about the mode, but for Thumb, the index
2017 must be suitable for use in a QImode load. */
2018 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2019 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2021 /* Maximum number of registers that can appear in a valid memory address.
2022 Shifts in addresses can't be by a register. */
2023 #define MAX_REGS_PER_ADDRESS 2
2025 /* Recognize any constant value that is a valid address. */
2026 /* XXX We can address any constant, eventually... */
2028 #ifdef AOF_ASSEMBLER
2030 #define CONSTANT_ADDRESS_P(X) \
2031 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2035 #define CONSTANT_ADDRESS_P(X) \
2036 (GET_CODE (X) == SYMBOL_REF \
2037 && (CONSTANT_POOL_ADDRESS_P (X) \
2038 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2040 #endif /* AOF_ASSEMBLER */
2042 /* Nonzero if the constant value X is a legitimate general operand.
2043 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2045 On the ARM, allow any integer (invalid ones are removed later by insn
2046 patterns), nice doubles and symbol_refs which refer to the function's
2049 When generating pic allow anything. */
2050 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2052 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2053 ( GET_CODE (X) == CONST_INT \
2054 || GET_CODE (X) == CONST_DOUBLE \
2055 || CONSTANT_ADDRESS_P (X) \
2058 #define LEGITIMATE_CONSTANT_P(X) \
2059 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2061 /* Special characters prefixed to function names
2062 in order to encode attribute like information.
2063 Note, '@' and '*' have already been taken. */
2064 #define SHORT_CALL_FLAG_CHAR '^'
2065 #define LONG_CALL_FLAG_CHAR '#'
2067 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2068 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2070 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2071 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2073 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2074 #define SUBTARGET_NAME_ENCODING_LENGTHS
2077 /* This is a C fragment for the inside of a switch statement.
2078 Each case label should return the number of characters to
2079 be stripped from the start of a function's name, if that
2080 name starts with the indicated character. */
2081 #define ARM_NAME_ENCODING_LENGTHS \
2082 case SHORT_CALL_FLAG_CHAR: return 1; \
2083 case LONG_CALL_FLAG_CHAR: return 1; \
2084 case '*': return 1; \
2085 SUBTARGET_NAME_ENCODING_LENGTHS
2087 /* This is how to output a reference to a user-level label named NAME.
2088 `assemble_name' uses this. */
2089 #undef ASM_OUTPUT_LABELREF
2090 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2091 arm_asm_output_labelref (FILE, NAME)
2093 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2094 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2096 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2097 and check its validity for a certain class.
2098 We have two alternate definitions for each of them.
2099 The usual definition accepts all pseudo regs; the other rejects
2100 them unless they have been allocated suitable hard regs.
2101 The symbol REG_OK_STRICT causes the latter definition to be used. */
2102 #ifndef REG_OK_STRICT
2104 #define ARM_REG_OK_FOR_BASE_P(X) \
2105 (REGNO (X) <= LAST_ARM_REGNUM \
2106 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2107 || REGNO (X) == FRAME_POINTER_REGNUM \
2108 || REGNO (X) == ARG_POINTER_REGNUM)
2110 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2111 (REGNO (X) <= LAST_LO_REGNUM \
2112 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2113 || (GET_MODE_SIZE (MODE) >= 4 \
2114 && (REGNO (X) == STACK_POINTER_REGNUM \
2115 || (X) == hard_frame_pointer_rtx \
2116 || (X) == arg_pointer_rtx)))
2118 #define REG_STRICT_P 0
2120 #else /* REG_OK_STRICT */
2122 #define ARM_REG_OK_FOR_BASE_P(X) \
2123 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2125 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2126 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2128 #define REG_STRICT_P 1
2130 #endif /* REG_OK_STRICT */
2132 /* Now define some helpers in terms of the above. */
2134 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2136 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2137 : ARM_REG_OK_FOR_BASE_P (X))
2139 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2141 /* For Thumb, a valid index register is anything that can be used in
2142 a byte load instruction. */
2143 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2145 /* Nonzero if X is a hard reg that can be used as an index
2146 or if it is a pseudo reg. On the Thumb, the stack pointer
2148 #define REG_OK_FOR_INDEX_P(X) \
2150 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2151 : ARM_REG_OK_FOR_INDEX_P (X))
2154 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2155 that is a valid memory address for an instruction.
2156 The MODE argument is the machine mode for the MEM expression
2157 that wants to use this address. */
2159 #define ARM_BASE_REGISTER_RTX_P(X) \
2160 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2162 #define ARM_INDEX_REGISTER_RTX_P(X) \
2163 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2165 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2167 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2171 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2173 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2177 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2179 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2180 else /* if (TARGET_THUMB) */ \
2181 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2184 /* Try machine-dependent ways of modifying an illegitimate address
2185 to be legitimate. If we find one, return the new, valid address. */
2186 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2188 X = arm_legitimize_address (X, OLDX, MODE); \
2191 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2193 X = thumb_legitimize_address (X, OLDX, MODE); \
2196 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2199 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2201 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2203 if (memory_address_p (MODE, X)) \
2207 /* Go to LABEL if ADDR (a legitimate address expression)
2208 has an effect that depends on the machine mode it is used for. */
2209 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2211 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2212 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2216 /* Nothing helpful to do for the Thumb */
2217 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2219 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2222 /* Specify the machine mode that this machine uses
2223 for the index in the tablejump instruction. */
2224 #define CASE_VECTOR_MODE Pmode
2226 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2227 unsigned is probably best, but may break some code. */
2228 #ifndef DEFAULT_SIGNED_CHAR
2229 #define DEFAULT_SIGNED_CHAR 0
2232 /* Don't cse the address of the function being compiled. */
2233 #define NO_RECURSIVE_FUNCTION_CSE 1
2235 /* Max number of bytes we can move from memory to memory
2236 in one reasonably fast instruction. */
2240 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2242 /* Define if operations between registers always perform the operation
2243 on the full register even if a narrower mode is specified. */
2244 #define WORD_REGISTER_OPERATIONS
2246 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2247 will either zero-extend or sign-extend. The value of this macro should
2248 be the code that says which one of the two operations is implicitly
2249 done, NIL if none. */
2250 #define LOAD_EXTEND_OP(MODE) \
2251 (TARGET_THUMB ? ZERO_EXTEND : \
2252 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2253 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2255 /* Nonzero if access to memory by bytes is slow and undesirable. */
2256 #define SLOW_BYTE_ACCESS 0
2258 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2260 /* Immediate shift counts are truncated by the output routines (or was it
2261 the assembler?). Shift counts in a register are truncated by ARM. Note
2262 that the native compiler puts too large (> 32) immediate shift counts
2263 into a register and shifts by the register, letting the ARM decide what
2264 to do instead of doing that itself. */
2265 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2266 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2267 On the arm, Y in a register is used modulo 256 for the shift. Only for
2268 rotates is modulo 32 used. */
2269 /* #define SHIFT_COUNT_TRUNCATED 1 */
2271 /* All integers have the same format so truncation is easy. */
2272 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2274 /* Calling from registers is a massive pain. */
2275 #define NO_FUNCTION_CSE 1
2277 /* The machine modes of pointers and functions */
2278 #define Pmode SImode
2279 #define FUNCTION_MODE Pmode
2281 #define ARM_FRAME_RTX(X) \
2282 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2283 || (X) == arg_pointer_rtx)
2285 /* Moves to and from memory are quite expensive */
2286 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2287 (TARGET_ARM ? 10 : \
2288 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2289 * (CLASS == LO_REGS ? 1 : 2)))
2291 /* Try to generate sequences that don't involve branches, we can then use
2292 conditional instructions */
2293 #define BRANCH_COST \
2294 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2296 /* Position Independent Code. */
2297 /* We decide which register to use based on the compilation options and
2298 the assembler in use; this is more general than the APCS restriction of
2299 using sb (r9) all the time. */
2300 extern int arm_pic_register;
2302 /* Used when parsing command line option -mpic-register=. */
2303 extern const char * arm_pic_register_string;
2305 /* The register number of the register used to address a table of static
2306 data addresses in memory. */
2307 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2309 #define FINALIZE_PIC arm_finalize_pic (1)
2311 /* We can't directly access anything that contains a symbol,
2312 nor can we indirect via the constant pool. */
2313 #define LEGITIMATE_PIC_OPERAND_P(X) \
2314 (!(symbol_mentioned_p (X) \
2315 || label_mentioned_p (X) \
2316 || (GET_CODE (X) == SYMBOL_REF \
2317 && CONSTANT_POOL_ADDRESS_P (X) \
2318 && (symbol_mentioned_p (get_pool_constant (X)) \
2319 || label_mentioned_p (get_pool_constant (X))))))
2321 /* We need to know when we are making a constant pool; this determines
2322 whether data needs to be in the GOT or can be referenced via a GOT
2324 extern int making_const_table;
2326 /* Handle pragmas for compatibility with Intel's compilers. */
2327 #define REGISTER_TARGET_PRAGMAS() do { \
2328 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2329 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2330 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2333 /* Condition code information. */
2334 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2335 return the mode to be used for the comparison. */
2337 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2339 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2341 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2344 if (GET_CODE (OP1) == CONST_INT \
2345 && ! (const_ok_for_arm (INTVAL (OP1)) \
2346 || (const_ok_for_arm (- INTVAL (OP1))))) \
2348 rtx const_op = OP1; \
2349 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2355 /* The arm5 clz instruction returns 32. */
2356 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2359 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2361 /* Output a push or a pop instruction (only used when profiling). */
2362 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2366 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2367 STACK_POINTER_REGNUM, REGNO); \
2369 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2373 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2377 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2378 STACK_POINTER_REGNUM, REGNO); \
2380 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2383 /* This is how to output a label which precedes a jumptable. Since
2384 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2385 #undef ASM_OUTPUT_CASE_LABEL
2386 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2390 ASM_OUTPUT_ALIGN (FILE, 2); \
2391 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2395 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2400 if (is_called_in_ARM_mode (DECL) \
2401 || current_function_is_thunk) \
2402 fprintf (STREAM, "\t.code 32\n") ; \
2404 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2406 if (TARGET_POKE_FUNCTION_NAME) \
2407 arm_poke_function_name (STREAM, (char *) NAME); \
2411 /* For aliases of functions we use .thumb_set instead. */
2412 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2415 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2416 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2418 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2420 fprintf (FILE, "\t.thumb_set "); \
2421 assemble_name (FILE, LABEL1); \
2422 fprintf (FILE, ","); \
2423 assemble_name (FILE, LABEL2); \
2424 fprintf (FILE, "\n"); \
2427 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2431 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2432 /* To support -falign-* switches we need to use .p2align so
2433 that alignment directives in code sections will be padded
2434 with no-op instructions, rather than zeroes. */
2435 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2438 if ((MAX_SKIP) == 0) \
2439 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2441 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2442 (int) (LOG), (int) (MAX_SKIP)); \
2446 /* Only perform branch elimination (by making instructions conditional) if
2447 we're optimizing. Otherwise it's of no use anyway. */
2448 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2449 if (TARGET_ARM && optimize) \
2450 arm_final_prescan_insn (INSN); \
2451 else if (TARGET_THUMB) \
2452 thumb_final_prescan_insn (INSN)
2454 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2455 (CODE == '@' || CODE == '|' \
2456 || (TARGET_ARM && (CODE == '?')) \
2457 || (TARGET_THUMB && (CODE == '_')))
2459 /* Output an operand of an instruction. */
2460 #define PRINT_OPERAND(STREAM, X, CODE) \
2461 arm_print_operand (STREAM, X, CODE)
2463 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2464 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2465 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2466 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2467 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2468 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2471 /* Output the address of an operand. */
2472 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2474 int is_minus = GET_CODE (X) == MINUS; \
2476 if (GET_CODE (X) == REG) \
2477 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2478 else if (GET_CODE (X) == PLUS || is_minus) \
2480 rtx base = XEXP (X, 0); \
2481 rtx index = XEXP (X, 1); \
2482 HOST_WIDE_INT offset = 0; \
2483 if (GET_CODE (base) != REG) \
2485 /* Ensure that BASE is a register. */ \
2486 /* (one of them must be). */ \
2491 switch (GET_CODE (index)) \
2494 offset = INTVAL (index); \
2497 asm_fprintf (STREAM, "[%r, #%wd]", \
2498 REGNO (base), offset); \
2502 asm_fprintf (STREAM, "[%r, %s%r]", \
2503 REGNO (base), is_minus ? "-" : "", \
2513 asm_fprintf (STREAM, "[%r, %s%r", \
2514 REGNO (base), is_minus ? "-" : "", \
2515 REGNO (XEXP (index, 0))); \
2516 arm_print_operand (STREAM, index, 'S'); \
2517 fputs ("]", STREAM); \
2525 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2526 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2528 extern enum machine_mode output_memory_reference_mode; \
2530 if (GET_CODE (XEXP (X, 0)) != REG) \
2533 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2534 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2535 REGNO (XEXP (X, 0)), \
2536 GET_CODE (X) == PRE_DEC ? "-" : "", \
2537 GET_MODE_SIZE (output_memory_reference_mode)); \
2539 asm_fprintf (STREAM, "[%r], #%s%d", \
2540 REGNO (XEXP (X, 0)), \
2541 GET_CODE (X) == POST_DEC ? "-" : "", \
2542 GET_MODE_SIZE (output_memory_reference_mode)); \
2544 else if (GET_CODE (X) == PRE_MODIFY) \
2546 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2547 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2548 asm_fprintf (STREAM, "#%wd]!", \
2549 INTVAL (XEXP (XEXP (X, 1), 1))); \
2551 asm_fprintf (STREAM, "%r]!", \
2552 REGNO (XEXP (XEXP (X, 1), 1))); \
2554 else if (GET_CODE (X) == POST_MODIFY) \
2556 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2557 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2558 asm_fprintf (STREAM, "#%wd", \
2559 INTVAL (XEXP (XEXP (X, 1), 1))); \
2561 asm_fprintf (STREAM, "%r", \
2562 REGNO (XEXP (XEXP (X, 1), 1))); \
2564 else output_addr_const (STREAM, X); \
2567 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2569 if (GET_CODE (X) == REG) \
2570 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2571 else if (GET_CODE (X) == POST_INC) \
2572 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2573 else if (GET_CODE (X) == PLUS) \
2575 if (GET_CODE (XEXP (X, 0)) != REG) \
2577 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2578 asm_fprintf (STREAM, "[%r, #%wd]", \
2579 REGNO (XEXP (X, 0)), \
2580 INTVAL (XEXP (X, 1))); \
2582 asm_fprintf (STREAM, "[%r, %r]", \
2583 REGNO (XEXP (X, 0)), \
2584 REGNO (XEXP (X, 1))); \
2587 output_addr_const (STREAM, X); \
2590 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2592 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2594 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2596 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2597 if (GET_CODE (X) != CONST_VECTOR \
2598 || ! arm_emit_vector_const (FILE, X)) \
2601 /* A C expression whose value is RTL representing the value of the return
2602 address for the frame COUNT steps up from the current frame. */
2604 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2605 arm_return_addr (COUNT, FRAME)
2607 /* Mask of the bits in the PC that contain the real return address
2608 when running in 26-bit mode. */
2609 #define RETURN_ADDR_MASK26 (0x03fffffc)
2611 /* Pick up the return address upon entry to a procedure. Used for
2612 dwarf2 unwind information. This also enables the table driven
2614 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2615 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2617 /* Used to mask out junk bits from the return address, such as
2618 processor state, interrupt status, condition codes and the like. */
2619 #define MASK_RETURN_ADDR \
2620 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2621 in 26 bit mode, the condition codes must be masked out of the \
2622 return address. This does not apply to ARM6 and later processors \
2623 when running in 32 bit mode. */ \
2624 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2625 : (arm_arch4 || TARGET_THUMB) ? \
2626 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2627 : arm_gen_return_addr_mask ())
2630 /* Define the codes that are matched by predicates in arm.c */
2631 #define PREDICATE_CODES \
2632 {"s_register_operand", {SUBREG, REG}}, \
2633 {"arm_general_register_operand", {SUBREG, REG}}, \
2634 {"arm_hard_register_operand", {REG}}, \
2635 {"f_register_operand", {SUBREG, REG}}, \
2636 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2637 {"arm_addimm_operand", {CONST_INT}}, \
2638 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2639 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2640 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2641 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2642 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2643 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2644 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2645 {"thumb_cmpneg_operand", {CONST_INT}}, \
2646 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2647 {"offsettable_memory_operand", {MEM}}, \
2648 {"alignable_memory_operand", {MEM}}, \
2649 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2650 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2651 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2652 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2653 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2654 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2655 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2656 {"load_multiple_operation", {PARALLEL}}, \
2657 {"store_multiple_operation", {PARALLEL}}, \
2658 {"equality_operator", {EQ, NE}}, \
2659 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2660 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2662 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2663 {"const_shift_operand", {CONST_INT}}, \
2664 {"multi_register_push", {PARALLEL}}, \
2665 {"cc_register", {REG}}, \
2666 {"logical_binary_operator", {AND, IOR, XOR}}, \
2667 {"cirrus_register_operand", {REG}}, \
2668 {"cirrus_fp_register", {REG}}, \
2669 {"cirrus_shift_const", {CONST_INT}}, \
2670 {"dominant_cc_register", {REG}}, \
2671 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2672 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2674 /* Define this if you have special predicates that know special things
2675 about modes. Genrecog will warn about certain forms of
2676 match_operand without a mode; if the operand predicate is listed in
2677 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2678 #define SPECIAL_MODE_PREDICATES \
2679 "cc_register", "dominant_cc_register",
2688 ARM_BUILTIN_WAVG2BR,
2689 ARM_BUILTIN_WAVG2HR,
2716 ARM_BUILTIN_TMOVMSKB,
2717 ARM_BUILTIN_TMOVMSKH,
2718 ARM_BUILTIN_TMOVMSKW,
2727 ARM_BUILTIN_WPACKHSS,
2728 ARM_BUILTIN_WPACKWSS,
2729 ARM_BUILTIN_WPACKDSS,
2730 ARM_BUILTIN_WPACKHUS,
2731 ARM_BUILTIN_WPACKWUS,
2732 ARM_BUILTIN_WPACKDUS,
2737 ARM_BUILTIN_WADDSSB,
2738 ARM_BUILTIN_WADDSSH,
2739 ARM_BUILTIN_WADDSSW,
2740 ARM_BUILTIN_WADDUSB,
2741 ARM_BUILTIN_WADDUSH,
2742 ARM_BUILTIN_WADDUSW,
2746 ARM_BUILTIN_WSUBSSB,
2747 ARM_BUILTIN_WSUBSSH,
2748 ARM_BUILTIN_WSUBSSW,
2749 ARM_BUILTIN_WSUBUSB,
2750 ARM_BUILTIN_WSUBUSH,
2751 ARM_BUILTIN_WSUBUSW,
2758 ARM_BUILTIN_WCMPEQB,
2759 ARM_BUILTIN_WCMPEQH,
2760 ARM_BUILTIN_WCMPEQW,
2761 ARM_BUILTIN_WCMPGTUB,
2762 ARM_BUILTIN_WCMPGTUH,
2763 ARM_BUILTIN_WCMPGTUW,
2764 ARM_BUILTIN_WCMPGTSB,
2765 ARM_BUILTIN_WCMPGTSH,
2766 ARM_BUILTIN_WCMPGTSW,
2768 ARM_BUILTIN_TEXTRMSB,
2769 ARM_BUILTIN_TEXTRMSH,
2770 ARM_BUILTIN_TEXTRMSW,
2771 ARM_BUILTIN_TEXTRMUB,
2772 ARM_BUILTIN_TEXTRMUH,
2773 ARM_BUILTIN_TEXTRMUW,
2823 ARM_BUILTIN_WUNPCKIHB,
2824 ARM_BUILTIN_WUNPCKIHH,
2825 ARM_BUILTIN_WUNPCKIHW,
2826 ARM_BUILTIN_WUNPCKILB,
2827 ARM_BUILTIN_WUNPCKILH,
2828 ARM_BUILTIN_WUNPCKILW,
2830 ARM_BUILTIN_WUNPCKEHSB,
2831 ARM_BUILTIN_WUNPCKEHSH,
2832 ARM_BUILTIN_WUNPCKEHSW,
2833 ARM_BUILTIN_WUNPCKEHUB,
2834 ARM_BUILTIN_WUNPCKEHUH,
2835 ARM_BUILTIN_WUNPCKEHUW,
2836 ARM_BUILTIN_WUNPCKELSB,
2837 ARM_BUILTIN_WUNPCKELSH,
2838 ARM_BUILTIN_WUNPCKELSW,
2839 ARM_BUILTIN_WUNPCKELUB,
2840 ARM_BUILTIN_WUNPCKELUH,
2841 ARM_BUILTIN_WUNPCKELUW,
2845 #endif /* ! GCC_ARM_H */
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