1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define ("__arm__"); \
36 builtin_define ("__thumb__"); \
40 builtin_define ("__ARMEB__"); \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
48 builtin_define ("__ARMEL__"); \
50 builtin_define ("__THUMBEL__"); \
54 builtin_define ("__APCS_32__"); \
56 builtin_define ("__APCS_26__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 #define TARGET_CPU_iwmmxt 0x0400
101 /* Configure didn't specify. */
102 #define TARGET_CPU_generic 0x8000
104 typedef enum arm_cond_code
106 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
107 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
111 extern arm_cc arm_current_cc;
113 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
115 extern int arm_target_label;
116 extern int arm_ccfsm_state;
117 extern GTY(()) rtx arm_target_insn;
118 /* Run-time compilation parameters selecting different hardware subsets. */
119 extern int target_flags;
120 /* The floating point instruction architecture, can be 2 or 3 */
121 extern const char * target_fp_name;
122 /* Define the information needed to generate branch insns. This is
123 stored from the compare operation. */
124 extern GTY(()) rtx arm_compare_op0;
125 extern GTY(()) rtx arm_compare_op1;
126 /* The label of the current constant pool. */
127 extern rtx pool_vector_label;
128 /* Set to 1 when a return insn is output, this means that the epilogue
130 extern int return_used_this_function;
131 /* Used to produce AOF syntax assembler. */
132 extern GTY(()) rtx aof_pic_label;
134 /* Just in case configure has failed to define anything. */
135 #ifndef TARGET_CPU_DEFAULT
136 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
139 /* If the configuration file doesn't specify the cpu, the subtarget may
140 override it. If it doesn't, then default to an ARM6. */
141 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
142 #undef TARGET_CPU_DEFAULT
144 #ifdef SUBTARGET_CPU_DEFAULT
145 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
147 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
151 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
152 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
154 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
155 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
157 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
158 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
160 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
161 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
163 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
164 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
167 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
169 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
170 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
171 /* Set TARGET_DEFAULT to the default, but without soft-float. */
172 #ifdef TARGET_DEFAULT
173 #undef TARGET_DEFAULT
174 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
175 #endif /* TARGET_CPU_DEFAULT */
177 Unrecognized value in TARGET_CPU_DEFAULT.
187 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
188 %{mapcs-32:%{mapcs-26: \
189 %e-mapcs-26 and -mapcs-32 may not be used together}} \
190 %{msoft-float:%{mhard-float: \
191 %e-msoft-float and -mhard_float may not be used together}} \
192 %{mbig-endian:%{mlittle-endian: \
193 %e-mbig-endian and -mlittle-endian may not be used together}}"
195 /* Set the architecture define -- if -march= is set, then it overrides
196 the -mcpu= setting. */
197 #define CPP_CPU_ARCH_SPEC "\
198 %{march=arm2:-D__ARM_ARCH_2__} \
199 %{march=arm250:-D__ARM_ARCH_2__} \
200 %{march=arm3:-D__ARM_ARCH_2__} \
201 %{march=arm6:-D__ARM_ARCH_3__} \
202 %{march=arm600:-D__ARM_ARCH_3__} \
203 %{march=arm610:-D__ARM_ARCH_3__} \
204 %{march=arm7:-D__ARM_ARCH_3__} \
205 %{march=arm700:-D__ARM_ARCH_3__} \
206 %{march=arm710:-D__ARM_ARCH_3__} \
207 %{march=arm720:-D__ARM_ARCH_3__} \
208 %{march=arm7100:-D__ARM_ARCH_3__} \
209 %{march=arm7500:-D__ARM_ARCH_3__} \
210 %{march=arm7500fe:-D__ARM_ARCH_3__} \
211 %{march=arm7m:-D__ARM_ARCH_3M__} \
212 %{march=arm7dm:-D__ARM_ARCH_3M__} \
213 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
214 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
215 %{march=arm8:-D__ARM_ARCH_4__} \
216 %{march=arm810:-D__ARM_ARCH_4__} \
217 %{march=arm9:-D__ARM_ARCH_4T__} \
218 %{march=arm920:-D__ARM_ARCH_4__} \
219 %{march=arm920t:-D__ARM_ARCH_4T__} \
220 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
221 %{march=strongarm:-D__ARM_ARCH_4__} \
222 %{march=strongarm110:-D__ARM_ARCH_4__} \
223 %{march=strongarm1100:-D__ARM_ARCH_4__} \
224 %{march=xscale:-D__ARM_ARCH_5TE__} \
225 %{march=xscale:-D__XSCALE__} \
226 %{march=ep9312:-D__ARM_ARCH_4T__} \
227 %{march=ep9312:-D__MAVERICK__} \
228 %{march=armv2:-D__ARM_ARCH_2__} \
229 %{march=armv2a:-D__ARM_ARCH_2__} \
230 %{march=armv3:-D__ARM_ARCH_3__} \
231 %{march=armv3m:-D__ARM_ARCH_3M__} \
232 %{march=armv4:-D__ARM_ARCH_4__} \
233 %{march=armv4t:-D__ARM_ARCH_4T__} \
234 %{march=armv5:-D__ARM_ARCH_5__} \
235 %{march=armv5t:-D__ARM_ARCH_5T__} \
236 %{march=armv5e:-D__ARM_ARCH_5E__} \
237 %{march=armv5te:-D__ARM_ARCH_5TE__} \
239 %{mcpu=arm2:-D__ARM_ARCH_2__} \
240 %{mcpu=arm250:-D__ARM_ARCH_2__} \
241 %{mcpu=arm3:-D__ARM_ARCH_2__} \
242 %{mcpu=arm6:-D__ARM_ARCH_3__} \
243 %{mcpu=arm600:-D__ARM_ARCH_3__} \
244 %{mcpu=arm610:-D__ARM_ARCH_3__} \
245 %{mcpu=arm7:-D__ARM_ARCH_3__} \
246 %{mcpu=arm700:-D__ARM_ARCH_3__} \
247 %{mcpu=arm710:-D__ARM_ARCH_3__} \
248 %{mcpu=arm720:-D__ARM_ARCH_3__} \
249 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
250 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
251 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
252 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
253 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
254 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
255 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
256 %{mcpu=arm8:-D__ARM_ARCH_4__} \
257 %{mcpu=arm810:-D__ARM_ARCH_4__} \
258 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
259 %{mcpu=arm920:-D__ARM_ARCH_4__} \
260 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
261 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
262 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
263 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
264 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
265 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
266 %{mcpu=xscale:-D__XSCALE__} \
267 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
268 %{mcpu=ep9312:-D__MAVERICK__} \
269 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
270 %{mcpu=iwmmxt:-D__XSCALE__} \
271 %{mcpu=iwmmxt:-D__IWMMXT__} \
272 %{!mcpu*:%(cpp_cpu_arch_default)}} \
279 /* This macro defines names of additional specifications to put in the specs
280 that can be used in various specifications like CC1_SPEC. Its definition
281 is an initializer with a subgrouping for each command option.
283 Each subgrouping contains a string constant, that defines the
284 specification name, and a string constant that used by the GCC driver
287 Do not define this macro if it does not need to do anything. */
288 #define EXTRA_SPECS \
289 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
290 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
291 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
292 SUBTARGET_EXTRA_SPECS
294 #ifndef SUBTARGET_EXTRA_SPECS
295 #define SUBTARGET_EXTRA_SPECS
298 #ifndef SUBTARGET_CPP_SPEC
299 #define SUBTARGET_CPP_SPEC ""
302 /* Run-time Target Specification. */
303 #ifndef TARGET_VERSION
304 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
307 /* Nonzero if the function prologue (and epilogue) should obey
308 the ARM Procedure Call Standard. */
309 #define ARM_FLAG_APCS_FRAME (1 << 0)
311 /* Nonzero if the function prologue should output the function name to enable
312 the post mortem debugger to print a backtrace (very useful on RISCOS,
313 unused on RISCiX). Specifying this flag also enables
314 -fno-omit-frame-pointer.
315 XXX Must still be implemented in the prologue. */
316 #define ARM_FLAG_POKE (1 << 1)
318 /* Nonzero if floating point instructions are emulated by the FPE, in which
319 case instruction scheduling becomes very uninteresting. */
320 #define ARM_FLAG_FPE (1 << 2)
322 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
323 that assume restoration of the condition flags when returning from a
324 branch and link (ie a function). */
325 #define ARM_FLAG_APCS_32 (1 << 3)
327 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
329 /* Nonzero if stack checking should be performed on entry to each function
330 which allocates temporary variables on the stack. */
331 #define ARM_FLAG_APCS_STACK (1 << 4)
333 /* Nonzero if floating point parameters should be passed to functions in
334 floating point registers. */
335 #define ARM_FLAG_APCS_FLOAT (1 << 5)
337 /* Nonzero if re-entrant, position independent code should be generated.
338 This is equivalent to -fpic. */
339 #define ARM_FLAG_APCS_REENT (1 << 6)
341 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
342 be loaded using either LDRH or LDRB instructions. */
343 #define ARM_FLAG_MMU_TRAPS (1 << 7)
345 /* Nonzero if all floating point instructions are missing (and there is no
346 emulator either). Generate function calls for all ops in this case. */
347 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
349 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
350 #define ARM_FLAG_BIG_END (1 << 9)
352 /* Nonzero if we should compile for Thumb interworking. */
353 #define ARM_FLAG_INTERWORK (1 << 10)
355 /* Nonzero if we should have little-endian words even when compiling for
356 big-endian (for backwards compatibility with older versions of GCC). */
357 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
359 /* Nonzero if we need to protect the prolog from scheduling */
360 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
362 /* Nonzero if a call to abort should be generated if a noreturn
363 function tries to return. */
364 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
366 /* Nonzero if function prologues should not load the PIC register. */
367 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
369 /* Nonzero if all call instructions should be indirect. */
370 #define ARM_FLAG_LONG_CALLS (1 << 15)
372 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
373 #define ARM_FLAG_THUMB (1 << 16)
375 /* Set if a TPCS style stack frame should be generated, for non-leaf
376 functions, even if they do not need one. */
377 #define THUMB_FLAG_BACKTRACE (1 << 17)
379 /* Set if a TPCS style stack frame should be generated, for leaf
380 functions, even if they do not need one. */
381 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
383 /* Set if externally visible functions should assume that they
384 might be called in ARM mode, from a non-thumb aware code. */
385 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
387 /* Set if calls via function pointers should assume that their
388 destination is non-Thumb aware. */
389 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
391 /* Nonzero means target uses VFP FP. */
392 #define ARM_FLAG_VFP (1 << 21)
394 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
395 #define ARM_FLAG_ATPCS (1 << 22)
397 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
398 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
400 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
401 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
402 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
403 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
404 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
405 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
406 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
407 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
408 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
409 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
410 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
411 #define TARGET_CIRRUS (arm_is_cirrus)
412 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
413 #define TARGET_IWMMXT (arm_arch_iwmmxt)
414 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
415 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
416 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
417 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
418 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
419 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
420 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
421 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
422 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
423 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
424 #define TARGET_ARM (! TARGET_THUMB)
425 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
426 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
427 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
428 #define TARGET_BACKTRACE (leaf_function_p () \
429 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
430 : (target_flags & THUMB_FLAG_BACKTRACE))
431 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
433 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
434 #ifndef SUBTARGET_SWITCHES
435 #define SUBTARGET_SWITCHES
438 #define TARGET_SWITCHES \
440 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
441 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
442 N_("Generate APCS conformant stack frames") }, \
443 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
444 {"poke-function-name", ARM_FLAG_POKE, \
445 N_("Store function names in object code") }, \
446 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
447 {"fpe", ARM_FLAG_FPE, "" }, \
448 {"apcs-32", ARM_FLAG_APCS_32, \
449 N_("Use the 32-bit version of the APCS") }, \
450 {"apcs-26", -ARM_FLAG_APCS_32, \
451 N_("Use the 26-bit version of the APCS") }, \
452 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
453 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
454 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
455 N_("Pass FP arguments in FP registers") }, \
456 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
457 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
458 N_("Generate re-entrant, PIC code") }, \
459 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
460 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
461 N_("The MMU will trap on unaligned accesses") }, \
462 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
463 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
464 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
465 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
466 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
467 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
468 N_("Use library calls to perform FP operations") }, \
469 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
470 N_("Use hardware floating point instructions") }, \
471 {"big-endian", ARM_FLAG_BIG_END, \
472 N_("Assume target CPU is configured as big endian") }, \
473 {"little-endian", -ARM_FLAG_BIG_END, \
474 N_("Assume target CPU is configured as little endian") }, \
475 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
476 N_("Assume big endian bytes, little endian words") }, \
477 {"thumb-interwork", ARM_FLAG_INTERWORK, \
478 N_("Support calls between Thumb and ARM instruction sets") }, \
479 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
480 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
481 N_("Generate a call to abort if a noreturn function returns")}, \
482 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
483 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
484 N_("Do not move instructions into a function's prologue") }, \
485 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
486 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
487 N_("Do not load the PIC register in function prologues") }, \
488 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
489 {"long-calls", ARM_FLAG_LONG_CALLS, \
490 N_("Generate call insns as indirect calls, if necessary") }, \
491 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
492 {"thumb", ARM_FLAG_THUMB, \
493 N_("Compile for the Thumb not the ARM") }, \
494 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
495 {"arm", -ARM_FLAG_THUMB, "" }, \
496 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
497 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
498 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
499 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
500 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
501 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
502 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
503 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
504 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
506 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
507 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
508 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
510 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
511 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
512 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
513 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
515 {"", TARGET_DEFAULT, "" } \
518 #define TARGET_OPTIONS \
520 {"cpu=", & arm_select[0].string, \
521 N_("Specify the name of the target CPU"), 0}, \
522 {"arch=", & arm_select[1].string, \
523 N_("Specify the name of the target architecture"), 0}, \
524 {"tune=", & arm_select[2].string, "", 0}, \
525 {"fpe=", & target_fp_name, "" , 0}, \
526 {"fp=", & target_fp_name, \
527 N_("Specify the version of the floating point emulator"), 0},\
528 {"structure-size-boundary=", & structure_size_string, \
529 N_("Specify the minimum bit alignment of structures"), 0}, \
530 {"pic-register=", & arm_pic_register_string, \
531 N_("Specify the register to be used for PIC addressing"), 0} \
534 /* Support for a compile-time default CPU, et cetera. The rules are:
535 --with-arch is ignored if -march or -mcpu are specified.
536 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
538 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
540 --with-float is ignored if -mhard-float or -msoft-float are
542 #define OPTION_DEFAULT_SPECS \
543 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
544 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
545 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
546 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
548 struct arm_cpu_select
552 const struct processors * processors;
555 /* This is a magic array. If the user specifies a command line switch
556 which matches one of the entries in TARGET_OPTIONS then the corresponding
557 string pointer will be set to the value specified by the user. */
558 extern struct arm_cpu_select arm_select[];
566 /* Recast the program mode class to be the prog_mode attribute */
567 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
569 extern enum prog_mode_type arm_prgmode;
571 /* What sort of floating point unit do we have? Hardware or software.
572 If software, is it issue 2 or issue 3? */
575 /* Software floating point, FPA style double fmt. */
577 /* Full FPA support. */
579 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
581 /* Emulated FPA hardware, Issue 3 emulator. */
583 /* Cirrus Maverick floating point co-processor. */
587 /* Recast the floating point class to be the floating point attribute. */
588 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
590 /* What type of floating point to tune for */
591 extern enum fputype arm_fpu_tune;
593 /* What type of floating point instructions are available */
594 extern enum fputype arm_fpu_arch;
596 /* Default floating point architecture. Override in sub-target if
598 #ifndef FPUTYPE_DEFAULT
599 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
602 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
603 #undef FPUTYPE_DEFAULT
604 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
607 /* Nonzero if the processor has a fast multiply insn, and one that does
608 a 64-bit multiply of two 32-bit values. */
609 extern int arm_fast_multiply;
611 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
612 extern int arm_arch4;
614 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
615 extern int arm_arch5;
617 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
618 extern int arm_arch5e;
620 /* Nonzero if this chip can benefit from load scheduling. */
621 extern int arm_ld_sched;
623 /* Nonzero if generating thumb code. */
624 extern int thumb_code;
626 /* Nonzero if this chip is a StrongARM. */
627 extern int arm_is_strong;
629 /* Nonzero if this chip is a Cirrus variant. */
630 extern int arm_is_cirrus;
632 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
633 extern int arm_arch_iwmmxt;
635 /* Nonzero if this chip is an XScale. */
636 extern int arm_arch_xscale;
638 /* Nonzero if tuning for XScale */
639 extern int arm_tune_xscale;
641 /* Nonzero if this chip is an ARM6 or an ARM7. */
642 extern int arm_is_6_or_7;
644 #ifndef TARGET_DEFAULT
645 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
648 /* The frame pointer register used in gcc has nothing to do with debugging;
649 that is controlled by the APCS-FRAME option. */
650 #define CAN_DEBUG_WITHOUT_FP
652 #undef TARGET_MEM_FUNCTIONS
653 #define TARGET_MEM_FUNCTIONS 1
655 #define OVERRIDE_OPTIONS arm_override_options ()
657 /* Nonzero if PIC code requires explicit qualifiers to generate
658 PLT and GOT relocs rather than the assembler doing so implicitly.
659 Subtargets can override these if required. */
660 #ifndef NEED_GOT_RELOC
661 #define NEED_GOT_RELOC 0
663 #ifndef NEED_PLT_RELOC
664 #define NEED_PLT_RELOC 0
667 /* Nonzero if we need to refer to the GOT with a PC-relative
668 offset. In other words, generate
670 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
674 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
676 The default is true, which matches NetBSD. Subtargets can
677 override this if required. */
682 /* Target machine storage Layout. */
685 /* Define this macro if it is advisable to hold scalars in registers
686 in a wider mode than that declared by the program. In such cases,
687 the value is constrained to be within the bounds of the declared
688 type, but kept valid in the wider mode. The signedness of the
689 extension may differ from that of the type. */
691 /* It is far faster to zero extend chars than to sign extend them */
693 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
694 if (GET_MODE_CLASS (MODE) == MODE_INT \
695 && GET_MODE_SIZE (MODE) < 4) \
697 if (MODE == QImode) \
699 else if (MODE == HImode) \
700 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
704 /* Define this macro if the promotion described by `PROMOTE_MODE'
705 should also be done for outgoing function arguments. */
706 /* This is required to ensure that push insns always push a word. */
707 #define PROMOTE_FUNCTION_ARGS
709 /* Define this if most significant bit is lowest numbered
710 in instructions that operate on numbered bit-fields. */
711 #define BITS_BIG_ENDIAN 0
713 /* Define this if most significant byte of a word is the lowest numbered.
714 Most ARM processors are run in little endian mode, so that is the default.
715 If you want to have it run-time selectable, change the definition in a
716 cover file to be TARGET_BIG_ENDIAN. */
717 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
719 /* Define this if most significant word of a multiword number is the lowest
721 This is always false, even when in big-endian mode. */
722 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
724 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
725 on processor pre-defineds when compiling libgcc2.c. */
726 #if defined(__ARMEB__) && !defined(__ARMWEL__)
727 #define LIBGCC2_WORDS_BIG_ENDIAN 1
729 #define LIBGCC2_WORDS_BIG_ENDIAN 0
732 /* Define this if most significant word of doubles is the lowest numbered.
733 The rules are different based on whether or not we use FPA-format,
734 VFP-format or some other floating point co-processor's format doubles. */
735 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
737 #define UNITS_PER_WORD 4
739 #define PARM_BOUNDARY 32
741 #define IWMMXT_ALIGNMENT 64
743 #define STACK_BOUNDARY 32
745 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
747 #define FUNCTION_BOUNDARY 32
749 /* The lowest bit is used to indicate Thumb-mode functions, so the
750 vbit must go into the delta field of pointers to member
752 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
754 #define EMPTY_FIELD_BOUNDARY 32
756 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
758 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
759 (TARGET_REALLY_IWMMXT \
760 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
762 /* XXX Blah -- this macro is used directly by libobjc. Since it
763 supports no vector modes, cut out the complexity and fall back
764 on BIGGEST_FIELD_ALIGNMENT. */
765 #ifdef IN_TARGET_LIBS
766 #define BIGGEST_FIELD_ALIGNMENT BIGGEST_ALIGNMENT
768 /* An expression for the alignment of a structure field FIELD if the
769 alignment computed in the usual way is COMPUTED. GCC uses this
770 value instead of the value in `BIGGEST_ALIGNMENT' or
771 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
772 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
773 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
778 /* If defined, a C expression to compute the alignment for a static variable.
779 TYPE is the data type, and ALIGN is the alignment that the object
780 would ordinarily have. The value of this macro is used instead of that
781 alignment to align the object.
783 If this macro is not defined, then ALIGN is used. */
784 #define DATA_ALIGNMENT(TYPE, ALIGN) \
785 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
787 /* If defined, a C expression to compute the alignment for a
788 variables in the local store. TYPE is the data type, and
789 BASIC-ALIGN is the alignment that the object would ordinarily
790 have. The value of this macro is used instead of that alignment
793 If this macro is not defined, then BASIC-ALIGN is used. */
794 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
795 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
797 /* Make strings word-aligned so strcpy from constants will be faster. */
798 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
800 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
801 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
802 (TREE_CODE (EXP) == STRING_CST \
803 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
804 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
806 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
807 value set in previous versions of this toolchain was 8, which produces more
808 compact structures. The command line option -mstructure_size_boundary=<n>
809 can be used to change this value. For compatibility with the ARM SDK
810 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
811 0020D) page 2-20 says "Structures are aligned on word boundaries". */
812 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
813 extern int arm_structure_size_boundary;
815 /* This is the value used to initialize arm_structure_size_boundary. If a
816 particular arm target wants to change the default value it should change
817 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
818 for an example of this. */
819 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
820 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
823 /* Used when parsing command line option -mstructure_size_boundary. */
824 extern const char * structure_size_string;
826 /* Nonzero if move instructions will actually fail to work
827 when given unaligned data. */
828 #define STRICT_ALIGNMENT 1
830 /* Standard register usage. */
832 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
833 (S - saved over call).
835 r0 * argument word/integer result
838 r4-r8 S register variable
839 r9 S (rfp) register variable (real frame pointer)
841 r10 F S (sl) stack limit (used by -mapcs-stack-check)
842 r11 F S (fp) argument pointer
843 r12 (ip) temp workspace
844 r13 F S (sp) lower end of current stack frame
845 r14 (lr) link address/workspace
846 r15 F (pc) program counter
848 f0 floating point result
849 f1-f3 floating point scratch
851 f4-f7 S floating point variable
853 cc This is NOT a real register, but is used internally
854 to represent things that use or set the condition
856 sfp This isn't either. It is used during rtl generation
857 since the offset between the frame pointer and the
858 auto's isn't known until after register allocation.
859 afp Nor this, we only need this because of non-local
860 goto. Without it fp appears to be used and the
861 elimination code won't get rid of sfp. It tracks
862 fp exactly at all times.
864 *: See CONDITIONAL_REGISTER_USAGE */
867 mvf0 Cirrus floating point result
868 mvf1-mvf3 Cirrus floating point scratch
869 mvf4-mvf15 S Cirrus floating point variable. */
871 /* The stack backtrace structure is as follows:
872 fp points to here: | save code pointer | [fp]
873 | return link value | [fp, #-4]
874 | return sp value | [fp, #-8]
875 | return fp value | [fp, #-12]
876 [| saved r10 value |]
887 [| saved f7 value |] three words
888 [| saved f6 value |] three words
889 [| saved f5 value |] three words
890 [| saved f4 value |] three words
891 r0-r3 are not normally saved in a C function. */
893 /* 1 for registers that have pervasive standard uses
894 and are not available for the register allocator. */
895 #define FIXED_REGISTERS \
908 /* 1 for registers not available across function calls.
909 These must include the FIXED_REGISTERS and also any
910 registers that can be used without being saved.
911 The latter must include the registers where values are returned
912 and the register where structure-value addresses are passed.
913 Aside from that, you can include as many other registers as you like.
914 The CC is not preserved over function calls on the ARM 6, so it is
915 easier to assume this for all. SFP is preserved, since FP is. */
916 #define CALL_USED_REGISTERS \
929 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
930 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
933 #define CONDITIONAL_REGISTER_USAGE \
937 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
939 for (regno = FIRST_ARM_FP_REGNUM; \
940 regno <= LAST_ARM_FP_REGNUM; ++regno) \
941 fixed_regs[regno] = call_used_regs[regno] = 1; \
946 for (regno = FIRST_ARM_FP_REGNUM; \
947 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
948 fixed_regs[regno] = call_used_regs[regno] = 1; \
949 for (regno = FIRST_CIRRUS_FP_REGNUM; \
950 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
952 fixed_regs[regno] = 0; \
953 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
957 if (TARGET_REALLY_IWMMXT) \
959 regno = FIRST_IWMMXT_GR_REGNUM; \
960 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
961 and wCG1 as call-preserved registers. The 2002/11/21 \
962 revision changed this so that all wCG registers are \
963 scratch registers. */ \
964 for (regno = FIRST_IWMMXT_GR_REGNUM; \
965 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
966 fixed_regs[regno] = call_used_regs[regno] = 0; \
967 /* The XScale ABI has wR0 - wR9 as scratch registers, \
968 the rest as call-preserved registers. */ \
969 for (regno = FIRST_IWMMXT_REGNUM; \
970 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
972 fixed_regs[regno] = 0; \
973 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
977 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
979 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
980 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
982 else if (TARGET_APCS_STACK) \
984 fixed_regs[10] = 1; \
985 call_used_regs[10] = 1; \
987 if (TARGET_APCS_FRAME) \
989 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
990 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
992 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
995 /* These are a couple of extensions to the formats accepted
997 %@ prints out ASM_COMMENT_START
998 %r prints out REGISTER_PREFIX reg_names[arg] */
999 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1001 fputs (ASM_COMMENT_START, FILE); \
1005 fputs (REGISTER_PREFIX, FILE); \
1006 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1009 /* Round X up to the nearest word. */
1010 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1012 /* Convert fron bytes to ints. */
1013 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1015 /* The number of (integer) registers required to hold a quantity of type MODE. */
1016 #define ARM_NUM_REGS(MODE) \
1017 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1019 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1020 #define ARM_NUM_REGS2(MODE, TYPE) \
1021 ARM_NUM_INTS ((MODE) == BLKmode ? \
1022 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1024 /* The number of (integer) argument register available. */
1025 #define NUM_ARG_REGS 4
1027 /* Return the regiser number of the N'th (integer) argument. */
1028 #define ARG_REGISTER(N) (N - 1)
1030 #if 0 /* FIXME: The ARM backend has special code to handle structure
1031 returns, and will reserve its own hidden first argument. So
1032 if this macro is enabled a *second* hidden argument will be
1033 reserved, which will break binary compatibility with old
1034 toolchains and also thunk handling. One day this should be
1036 /* RTX for structure returns. NULL means use a hidden first argument. */
1037 #define STRUCT_VALUE 0
1039 /* Register in which address to store a structure value
1040 is passed to a function. */
1041 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
1044 /* Specify the registers used for certain standard purposes.
1045 The values of these macros are register numbers. */
1047 /* The number of the last argument register. */
1048 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1050 /* The number of the last "lo" register (thumb). */
1051 #define LAST_LO_REGNUM 7
1053 /* The register that holds the return address in exception handlers. */
1054 #define EXCEPTION_LR_REGNUM 2
1056 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1057 as an invisible last argument (possible since varargs don't exist in
1058 Pascal), so the following is not true. */
1059 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1061 /* Define this to be where the real frame pointer is if it is not possible to
1062 work out the offset between the frame pointer and the automatic variables
1063 until after register allocation has taken place. FRAME_POINTER_REGNUM
1064 should point to a special register that we will make sure is eliminated.
1066 For the Thumb we have another problem. The TPCS defines the frame pointer
1067 as r11, and GCC believes that it is always possible to use the frame pointer
1068 as base register for addressing purposes. (See comments in
1069 find_reloads_address()). But - the Thumb does not allow high registers,
1070 including r11, to be used as base address registers. Hence our problem.
1072 The solution used here, and in the old thumb port is to use r7 instead of
1073 r11 as the hard frame pointer and to have special code to generate
1074 backtrace structures on the stack (if required to do so via a command line
1075 option) using r11. This is the only 'user visible' use of r11 as a frame
1077 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1078 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1080 #define HARD_FRAME_POINTER_REGNUM \
1082 ? ARM_HARD_FRAME_POINTER_REGNUM \
1083 : THUMB_HARD_FRAME_POINTER_REGNUM)
1085 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1087 /* Register to use for pushing function arguments. */
1088 #define STACK_POINTER_REGNUM SP_REGNUM
1090 /* ARM floating pointer registers. */
1091 #define FIRST_ARM_FP_REGNUM 16
1092 #define LAST_ARM_FP_REGNUM 23
1094 #define FIRST_IWMMXT_GR_REGNUM 43
1095 #define LAST_IWMMXT_GR_REGNUM 46
1096 #define FIRST_IWMMXT_REGNUM 47
1097 #define LAST_IWMMXT_REGNUM 62
1098 #define IS_IWMMXT_REGNUM(REGNUM) \
1099 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1100 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1101 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1103 /* Base register for access to local variables of the function. */
1104 #define FRAME_POINTER_REGNUM 25
1106 /* Base register for access to arguments of the function. */
1107 #define ARG_POINTER_REGNUM 26
1109 #define FIRST_CIRRUS_FP_REGNUM 27
1110 #define LAST_CIRRUS_FP_REGNUM 42
1111 #define IS_CIRRUS_REGNUM(REGNUM) \
1112 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1114 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1115 /* + 16 Cirrus registers take us up to 43. */
1116 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1117 #define FIRST_PSEUDO_REGISTER 63
1119 /* Value should be nonzero if functions must have frame pointers.
1120 Zero means the frame pointer need not be set up (and parms may be accessed
1121 via the stack pointer) in functions that seem suitable.
1122 If we have to have a frame pointer we might as well make use of it.
1123 APCS says that the frame pointer does not need to be pushed in leaf
1124 functions, or simple tail call functions. */
1125 #define FRAME_POINTER_REQUIRED \
1126 (current_function_has_nonlocal_label \
1127 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1129 /* Return number of consecutive hard regs needed starting at reg REGNO
1130 to hold something of mode MODE.
1131 This is ordinarily the length in words of a value of mode MODE
1132 but can be less for certain modes in special long registers.
1134 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1136 #define HARD_REGNO_NREGS(REGNO, MODE) \
1138 && REGNO >= FIRST_ARM_FP_REGNUM \
1139 && REGNO != FRAME_POINTER_REGNUM \
1140 && REGNO != ARG_POINTER_REGNUM) \
1141 ? 1 : ARM_NUM_REGS (MODE))
1143 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1144 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1145 arm_hard_regno_mode_ok ((REGNO), (MODE))
1147 /* Value is 1 if it is a good idea to tie two pseudo registers
1148 when one has mode MODE1 and one has mode MODE2.
1149 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1150 for any hard reg, then this must be 0 for correct output. */
1151 #define MODES_TIEABLE_P(MODE1, MODE2) \
1152 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1154 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1155 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1157 #define VALID_IWMMXT_REG_MODE(MODE) \
1158 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1160 /* The order in which register should be allocated. It is good to use ip
1161 since no saving is required (though calls clobber it) and it never contains
1162 function parameters. It is quite good to use lr since other calls may
1163 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1164 least likely to contain a function parameter; in addition results are
1166 #define REG_ALLOC_ORDER \
1168 3, 2, 1, 0, 12, 14, 4, 5, \
1169 6, 7, 8, 10, 9, 11, 13, 15, \
1170 16, 17, 18, 19, 20, 21, 22, 23, \
1171 27, 28, 29, 30, 31, 32, 33, 34, \
1172 35, 36, 37, 38, 39, 40, 41, 42, \
1173 43, 44, 45, 46, 47, 48, 49, 50, \
1174 51, 52, 53, 54, 55, 56, 57, 58, \
1179 /* Interrupt functions can only use registers that have already been
1180 saved by the prologue, even if they would normally be
1182 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1183 (! IS_INTERRUPT (cfun->machine->func_type) || \
1184 regs_ever_live[DST])
1186 /* Register and constant classes. */
1188 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1189 Now that the Thumb is involved it has become more complicated. */
1207 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1209 /* Give names of register classes as strings for dump file. */
1210 #define REG_CLASS_NAMES \
1226 /* Define which registers fit in which classes.
1227 This is an initializer for a vector of HARD_REG_SET
1228 of length N_REG_CLASSES. */
1229 #define REG_CLASS_CONTENTS \
1231 { 0x00000000, 0x0 }, /* NO_REGS */ \
1232 { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
1233 { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
1234 { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\
1235 { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \
1236 { 0x000000FF, 0x0 }, /* LO_REGS */ \
1237 { 0x00002000, 0x0 }, /* STACK_REG */ \
1238 { 0x000020FF, 0x0 }, /* BASE_REGS */ \
1239 { 0x0000FF00, 0x0 }, /* HI_REGS */ \
1240 { 0x01000000, 0x0 }, /* CC_REG */ \
1241 { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\
1242 { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1245 /* The same information, inverted:
1246 Return the class number of the smallest class containing
1247 reg number REGNO. This could be a conditional expression
1248 or could index an array. */
1249 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1251 /* FPA registers can't do dubreg as all values are reformatted to internal
1253 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1254 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1255 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0)
1257 /* The class value for index registers, and the one for base regs. */
1258 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1259 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1261 /* For the Thumb the high registers cannot be used as base registers
1262 when addressing quantities in QI or HI mode; if we don't know the
1263 mode, then we must be conservative. After reload we must also be
1264 conservative, since we can't support SP+reg addressing, and we
1265 can't fix up any bad substitutions. */
1266 #define MODE_BASE_REG_CLASS(MODE) \
1267 (TARGET_ARM ? GENERAL_REGS : \
1268 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1270 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1271 registers explicitly used in the rtl to be used as spill registers
1272 but prevents the compiler from extending the lifetime of these
1274 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1276 /* Get reg_class from a letter such as appears in the machine description.
1277 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1278 ARM, but several more letters for the Thumb. */
1279 #define REG_CLASS_FROM_LETTER(C) \
1280 ( (C) == 'f' ? FPA_REGS \
1281 : (C) == 'v' ? CIRRUS_REGS \
1282 : (C) == 'y' ? IWMMXT_REGS \
1283 : (C) == 'z' ? IWMMXT_GR_REGS \
1284 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1285 : TARGET_ARM ? NO_REGS \
1286 : (C) == 'h' ? HI_REGS \
1287 : (C) == 'b' ? BASE_REGS \
1288 : (C) == 'k' ? STACK_REG \
1289 : (C) == 'c' ? CC_REG \
1292 /* The letters I, J, K, L and M in a register constraint string
1293 can be used to stand for particular ranges of immediate operands.
1294 This macro defines what the ranges are.
1295 C is the letter, and VALUE is a constant value.
1296 Return 1 if VALUE is in the range specified by C.
1297 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1298 J: valid indexing constants.
1299 K: ~value ok in rhs argument of data operand.
1300 L: -value ok in rhs argument of data operand.
1301 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1302 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1303 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1304 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1305 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1306 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1307 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1308 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1311 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1312 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1313 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1314 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1315 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1316 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1317 && ((VAL) & 3) == 0) : \
1318 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1319 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1322 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1324 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1326 /* Constant letter 'G' for the FPA immediate constants.
1327 'H' means the same constant negated. */
1328 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1329 ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
1330 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1332 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1334 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1336 /* For the ARM, `Q' means that this is a memory operand that is just
1337 an offset from a register.
1338 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1339 address. This means that the symbol is in the text segment and can be
1340 accessed without using a load. */
1342 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1343 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1344 (C) == 'R' ? (GET_CODE (OP) == MEM \
1345 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1346 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1347 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1348 (C) == 'T' ? cirrus_memory_offset (OP) : \
1351 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1352 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1353 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1355 #define EXTRA_CONSTRAINT(X, C) \
1357 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1359 /* Given an rtx X being reloaded into a reg required to be
1360 in class CLASS, return the class of reg to actually use.
1361 In general this is just CLASS, but for the Thumb we prefer
1362 a LO_REGS class or a subset. */
1363 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1364 (TARGET_ARM ? (CLASS) : \
1365 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1367 /* Must leave BASE_REGS reloads alone */
1368 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1369 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1370 ? ((true_regnum (X) == -1 ? LO_REGS \
1371 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1375 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1376 ((CLASS) != LO_REGS \
1377 ? ((true_regnum (X) == -1 ? LO_REGS \
1378 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1382 /* Return the register class of a scratch register needed to copy IN into
1383 or out of a register in CLASS in MODE. If it can be done directly,
1384 NO_REGS is returned. */
1385 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1387 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1388 ? GENERAL_REGS : NO_REGS) \
1389 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1391 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1392 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1393 /* Cannot load constants into Cirrus registers. */ \
1395 && (CLASS) == CIRRUS_REGS \
1396 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1399 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1400 && CONSTANT_P (X)) \
1402 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1403 && (GET_CODE (X) == MEM \
1404 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1405 && true_regnum (X) == -1))) \
1406 ? GENERAL_REGS : NO_REGS) \
1407 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1409 /* Try a machine-dependent way of reloading an illegitimate address
1410 operand. If we find one, push the reload and jump to WIN. This
1411 macro is used in only one place: `find_reloads_address' in reload.c.
1413 For the ARM, we wish to handle large displacements off a base
1414 register by splitting the addend across a MOV and the mem insn.
1415 This can cut the number of reloads needed. */
1416 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1419 if (GET_CODE (X) == PLUS \
1420 && GET_CODE (XEXP (X, 0)) == REG \
1421 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1422 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1423 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1425 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1426 HOST_WIDE_INT low, high; \
1428 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1429 low = ((val & 0xf) ^ 0x8) - 0x8; \
1430 else if (TARGET_CIRRUS) \
1431 /* Need to be careful, -256 is not a valid offset. */ \
1432 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1433 else if (MODE == SImode \
1434 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1435 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1436 /* Need to be careful, -4096 is not a valid offset. */ \
1437 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1438 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1439 /* Need to be careful, -256 is not a valid offset. */ \
1440 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1441 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1442 && TARGET_HARD_FLOAT) \
1443 /* Need to be careful, -1024 is not a valid offset. */ \
1444 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1448 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1449 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1450 - (unsigned HOST_WIDE_INT) 0x80000000); \
1451 /* Check for overflow or zero */ \
1452 if (low == 0 || high == 0 || (high + low != val)) \
1455 /* Reload the high part into a base reg; leave the low part \
1457 X = gen_rtx_PLUS (GET_MODE (X), \
1458 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1461 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1462 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1463 VOIDmode, 0, 0, OPNUM, TYPE); \
1469 /* XXX If an HImode FP+large_offset address is converted to an HImode
1470 SP+large_offset address, then reload won't know how to fix it. It sees
1471 only that SP isn't valid for HImode, and so reloads the SP into an index
1472 register, but the resulting address is still invalid because the offset
1473 is too big. We fix it here instead by reloading the entire address. */
1474 /* We could probably achieve better results by defining PROMOTE_MODE to help
1475 cope with the variances between the Thumb's signed and unsigned byte and
1476 halfword load instructions. */
1477 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1479 if (GET_CODE (X) == PLUS \
1480 && GET_MODE_SIZE (MODE) < 4 \
1481 && GET_CODE (XEXP (X, 0)) == REG \
1482 && XEXP (X, 0) == stack_pointer_rtx \
1483 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1484 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1488 push_reload (orig_X, NULL_RTX, &X, NULL, \
1489 MODE_BASE_REG_CLASS (MODE), \
1490 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1495 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1497 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1499 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1501 /* Return the maximum number of consecutive registers
1502 needed to represent mode MODE in a register of class CLASS.
1503 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1504 #define CLASS_MAX_NREGS(CLASS, MODE) \
1505 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1507 /* If defined, gives a class of registers that cannot be used as the
1508 operand of a SUBREG that changes the mode of the object illegally. */
1510 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1511 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1513 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1514 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1515 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1516 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1517 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1518 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1519 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1522 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1524 /* Stack layout; function entry, exit and calling. */
1526 /* Define this if pushing a word on the stack
1527 makes the stack pointer a smaller address. */
1528 #define STACK_GROWS_DOWNWARD 1
1530 /* Define this if the nominal address of the stack frame
1531 is at the high-address end of the local variables;
1532 that is, each additional local variable allocated
1533 goes at a more negative offset in the frame. */
1534 #define FRAME_GROWS_DOWNWARD 1
1536 /* Offset within stack frame to start allocating local variables at.
1537 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1538 first local allocated. Otherwise, it is the offset to the BEGINNING
1539 of the first local allocated. */
1540 #define STARTING_FRAME_OFFSET 0
1542 /* If we generate an insn to push BYTES bytes,
1543 this says how many the stack pointer really advances by. */
1544 /* The push insns do not do this rounding implicitly.
1545 So don't define this. */
1546 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1548 /* Define this if the maximum size of all the outgoing args is to be
1549 accumulated and pushed during the prologue. The amount can be
1550 found in the variable current_function_outgoing_args_size. */
1551 #define ACCUMULATE_OUTGOING_ARGS 1
1553 /* Offset of first parameter from the argument pointer register value. */
1554 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1556 /* Value is the number of byte of arguments automatically
1557 popped when returning from a subroutine call.
1558 FUNDECL is the declaration node of the function (as a tree),
1559 FUNTYPE is the data type of the function (as a tree),
1560 or for a library call it is an identifier node for the subroutine name.
1561 SIZE is the number of bytes of arguments passed on the stack.
1563 On the ARM, the caller does not pop any of its arguments that were passed
1565 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1567 /* Define how to find the value returned by a library function
1568 assuming the value has mode MODE. */
1569 #define LIBCALL_VALUE(MODE) \
1570 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1571 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1572 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1573 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1574 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1575 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1576 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1578 /* Define how to find the value returned by a function.
1579 VALTYPE is the data type of the value (as a tree).
1580 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1581 otherwise, FUNC is 0. */
1582 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1583 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1585 /* 1 if N is a possible register number for a function value.
1586 On the ARM, only r0 and f0 can return results. */
1587 /* On a Cirrus chip, mvf0 can return results. */
1588 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1589 ((REGNO) == ARG_REGISTER (1) \
1590 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1591 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1592 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1594 /* How large values are returned */
1595 /* A C expression which can inhibit the returning of certain function values
1596 in registers, based on the type of value. */
1597 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1599 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1600 values must be in memory. On the ARM, they need only do so if larger
1601 than a word, or if they contain elements offset from zero in the struct. */
1602 #define DEFAULT_PCC_STRUCT_RETURN 0
1604 /* Flags for the call/call_value rtl operations set up by function_arg. */
1605 #define CALL_NORMAL 0x00000000 /* No special processing. */
1606 #define CALL_LONG 0x00000001 /* Always call indirect. */
1607 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1609 /* These bits describe the different types of function supported
1610 by the ARM backend. They are exclusive. ie a function cannot be both a
1611 normal function and an interworked function, for example. Knowing the
1612 type of a function is important for determining its prologue and
1614 Note value 7 is currently unassigned. Also note that the interrupt
1615 function types all have bit 2 set, so that they can be tested for easily.
1616 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1617 machine_function structure is initialized (to zero) func_type will
1618 default to unknown. This will force the first use of arm_current_func_type
1619 to call arm_compute_func_type. */
1620 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1621 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1622 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1623 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1624 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1625 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1626 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1628 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1630 /* In addition functions can have several type modifiers,
1631 outlined by these bit masks: */
1632 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1633 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1634 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1635 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1637 /* Some macros to test these flags. */
1638 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1639 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1640 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1641 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1642 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1644 /* A C structure for machine-specific, per-function data.
1645 This is added to the cfun structure. */
1646 typedef struct machine_function GTY(())
1648 /* Additional stack adjustment in __builtin_eh_throw. */
1649 rtx eh_epilogue_sp_ofs;
1650 /* Records if LR has to be saved for far jumps. */
1652 /* Records if ARG_POINTER was ever live. */
1653 int arg_pointer_live;
1654 /* Records if the save of LR has been eliminated. */
1655 int lr_save_eliminated;
1656 /* The size of the stack frame. Only valid after reload. */
1658 /* Records the type of the current function. */
1659 unsigned long func_type;
1660 /* Record if the function has a variable argument list. */
1661 int uses_anonymous_args;
1662 /* Records if sibcalls are blocked because an argument
1663 register is needed to preserve stack alignment. */
1664 int sibcall_blocked;
1668 /* A C type for declaring a variable that is used as the first argument of
1669 `FUNCTION_ARG' and other related values. For some target machines, the
1670 type `int' suffices and can hold the number of bytes of argument so far. */
1673 /* This is the number of registers of arguments scanned so far. */
1675 /* This is the number of iWMMXt register arguments scanned so far. */
1679 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1683 /* Define where to put the arguments to a function.
1684 Value is zero to push the argument on the stack,
1685 or a hard register in which to store the argument.
1687 MODE is the argument's machine mode.
1688 TYPE is the data type of the argument (as a tree).
1689 This is null for libcalls where that information may
1691 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1692 the preceding args and about the function being called.
1693 NAMED is nonzero if this argument is a named parameter
1694 (otherwise it is an extra parameter matching an ellipsis).
1696 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1697 other arguments are passed on the stack. If (NAMED == 0) (which happens
1698 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1699 passed in the stack (function_prologue will indeed make it pass in the
1700 stack if necessary). */
1701 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1702 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1704 /* For an arg passed partly in registers and partly in memory,
1705 this is the number of registers used.
1706 For args passed entirely in registers or entirely in memory, zero. */
1707 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1708 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1709 NUM_ARG_REGS > (CUM).nregs \
1710 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1711 ? NUM_ARG_REGS - (CUM).nregs : 0)
1713 /* A C expression that indicates when an argument must be passed by
1714 reference. If nonzero for an argument, a copy of that argument is
1715 made in memory and a pointer to the argument is passed instead of
1716 the argument itself. The pointer is passed in whatever way is
1717 appropriate for passing a pointer to that type. */
1718 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1719 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1721 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1722 for a call to a function whose data type is FNTYPE.
1723 For a library call, FNTYPE is 0.
1724 On the ARM, the offset starts at 0. */
1725 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1726 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1728 /* Update the data in CUM to advance over an argument
1729 of mode MODE and data type TYPE.
1730 (TYPE is null for libcalls where that information may not be available.) */
1731 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1733 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1734 if ((CUM).named_count <= (CUM).nargs) \
1737 (CUM).iwmmxt_nregs += 1; \
1739 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1741 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1742 argument with the specified mode and type. If it is not defined,
1743 `PARM_BOUNDARY' is used for all arguments. */
1744 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1745 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1746 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1748 /* 1 if N is a possible register number for function argument passing.
1749 On the ARM, r0-r3 are used to pass args. */
1750 #define FUNCTION_ARG_REGNO_P(REGNO) \
1751 (IN_RANGE ((REGNO), 0, 3) \
1752 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1754 /* Implement `va_arg'. */
1755 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1756 arm_va_arg (valist, type)
1759 /* Perform any actions needed for a function that is receiving a variable
1760 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1761 of the current parameter. PRETEND_SIZE is a variable that should be set to
1762 the amount of stack that must be pushed by the prolog to pretend that our
1765 Normally, this macro will push all remaining incoming registers on the
1766 stack and set PRETEND_SIZE to the length of the registers pushed.
1768 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1769 named arg and all anonymous args onto the stack.
1770 XXX I know the prologue shouldn't be pushing registers, but it is faster
1772 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1774 cfun->machine->uses_anonymous_args = 1; \
1775 if ((CUM).nregs < NUM_ARG_REGS) \
1776 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1779 /* If your target environment doesn't prefix user functions with an
1780 underscore, you may wish to re-define this to prevent any conflicts.
1781 e.g. AOF may prefix mcount with an underscore. */
1782 #ifndef ARM_MCOUNT_NAME
1783 #define ARM_MCOUNT_NAME "*mcount"
1786 /* Call the function profiler with a given profile label. The Acorn
1787 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1788 On the ARM the full profile code will look like:
1797 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1798 will output the .text section.
1800 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1801 ``prof'' doesn't seem to mind about this!
1803 Note - this version of the code is designed to work in both ARM and
1805 #ifndef ARM_FUNCTION_PROFILER
1806 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1811 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1812 IP_REGNUM, LR_REGNUM); \
1813 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1814 fputc ('\n', STREAM); \
1815 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1816 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1817 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1821 #ifdef THUMB_FUNCTION_PROFILER
1822 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1824 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1826 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1828 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1829 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1832 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1833 the stack pointer does not matter. The value is tested only in
1834 functions that have frame pointers.
1835 No definition is equivalent to always zero.
1837 On the ARM, the function epilogue recovers the stack pointer from the
1839 #define EXIT_IGNORE_STACK 1
1841 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1843 /* Determine if the epilogue should be output as RTL.
1844 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1845 #define USE_RETURN_INSN(ISCOND) \
1846 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1848 /* Definitions for register eliminations.
1850 This is an array of structures. Each structure initializes one pair
1851 of eliminable registers. The "from" register number is given first,
1852 followed by "to". Eliminations of the same "from" register are listed
1853 in order of preference.
1855 We have two registers that can be eliminated on the ARM. First, the
1856 arg pointer register can often be eliminated in favor of the stack
1857 pointer register. Secondly, the pseudo frame pointer register can always
1858 be eliminated; it is replaced with either the stack or the real frame
1859 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1860 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1862 #define ELIMINABLE_REGS \
1863 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1864 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1865 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1866 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1867 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1868 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1869 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1871 /* Given FROM and TO register numbers, say whether this elimination is
1872 allowed. Frame pointer elimination is automatically handled.
1874 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1875 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1876 pointer, we must eliminate FRAME_POINTER_REGNUM into
1877 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1878 ARG_POINTER_REGNUM. */
1879 #define CAN_ELIMINATE(FROM, TO) \
1880 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1881 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1882 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1883 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1886 #define THUMB_REG_PUSHED_P(reg) \
1887 (regs_ever_live [reg] \
1888 && (! call_used_regs [reg] \
1889 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1890 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1892 /* Define the offset between two registers, one to be eliminated, and the
1893 other its replacement, at the start of a routine. */
1894 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1897 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1901 /* Note: This macro must match the code in thumb_function_prologue(). */
1902 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1905 if ((FROM) == ARG_POINTER_REGNUM) \
1907 int count_regs = 0; \
1909 for (regno = 8; regno < 13; regno ++) \
1910 if (THUMB_REG_PUSHED_P (regno)) \
1913 (OFFSET) += 4 * count_regs; \
1915 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1916 if (THUMB_REG_PUSHED_P (regno)) \
1918 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1919 (OFFSET) += 4 * (count_regs + 1); \
1920 if (TARGET_BACKTRACE) \
1922 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1928 if ((TO) == STACK_POINTER_REGNUM) \
1930 (OFFSET) += current_function_outgoing_args_size; \
1931 (OFFSET) += thumb_get_frame_size (); \
1935 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1937 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1939 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1941 /* Special case handling of the location of arguments passed on the stack. */
1942 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1944 /* Initialize data used by insn expanders. This is called from insn_emit,
1945 once for every function before code is generated. */
1946 #define INIT_EXPANDERS arm_init_expanders ()
1948 /* Output assembler code for a block containing the constant parts
1949 of a trampoline, leaving space for the variable parts.
1951 On the ARM, (if r8 is the static chain regnum, and remembering that
1952 referencing pc adds an offset of 8) the trampoline looks like:
1955 .word static chain value
1956 .word function's address
1957 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1958 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1960 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1961 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1962 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1963 PC_REGNUM, PC_REGNUM); \
1964 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1965 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1968 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1969 Why - because it is easier. This code will always be branched to via
1970 a BX instruction and since the compiler magically generates the address
1971 of the function the linker has no opportunity to ensure that the
1972 bottom bit is set. Thus the processor will be in ARM mode when it
1973 reaches this code. So we duplicate the ARM trampoline code and add
1974 a switch into Thumb mode as well. */
1975 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1977 fprintf (FILE, "\t.code 32\n"); \
1978 fprintf (FILE, ".Ltrampoline_start:\n"); \
1979 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1980 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1981 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1982 IP_REGNUM, PC_REGNUM); \
1983 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1984 IP_REGNUM, IP_REGNUM); \
1985 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1986 fprintf (FILE, "\t.word\t0\n"); \
1987 fprintf (FILE, "\t.word\t0\n"); \
1988 fprintf (FILE, "\t.code 16\n"); \
1991 #define TRAMPOLINE_TEMPLATE(FILE) \
1993 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1995 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1997 /* Length in units of the trampoline for entering a nested function. */
1998 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2000 /* Alignment required for a trampoline in bits. */
2001 #define TRAMPOLINE_ALIGNMENT 32
2003 /* Emit RTL insns to initialize the variable parts of a trampoline.
2004 FNADDR is an RTX for the address of the function's pure code.
2005 CXT is an RTX for the static chain value for the function. */
2006 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2009 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
2011 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
2015 /* Addressing modes, and classification of registers for them. */
2016 #define HAVE_POST_INCREMENT 1
2017 #define HAVE_PRE_INCREMENT TARGET_ARM
2018 #define HAVE_POST_DECREMENT TARGET_ARM
2019 #define HAVE_PRE_DECREMENT TARGET_ARM
2020 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2021 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2022 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2023 #define HAVE_POST_MODIFY_REG TARGET_ARM
2025 /* Macros to check register numbers against specific register classes. */
2027 /* These assume that REGNO is a hard or pseudo reg number.
2028 They give nonzero only if REGNO is a hard reg of the suitable class
2029 or a pseudo reg currently allocated to a suitable hard reg.
2030 Since they use reg_renumber, they are safe only once reg_renumber
2031 has been allocated, which happens in local-alloc.c. */
2032 #define TEST_REGNO(R, TEST, VALUE) \
2033 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2035 /* On the ARM, don't allow the pc to be used. */
2036 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2037 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2038 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2039 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2041 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2042 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2043 || (GET_MODE_SIZE (MODE) >= 4 \
2044 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2046 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2048 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2049 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2051 /* For ARM code, we don't care about the mode, but for Thumb, the index
2052 must be suitable for use in a QImode load. */
2053 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2054 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2056 /* Maximum number of registers that can appear in a valid memory address.
2057 Shifts in addresses can't be by a register. */
2058 #define MAX_REGS_PER_ADDRESS 2
2060 /* Recognize any constant value that is a valid address. */
2061 /* XXX We can address any constant, eventually... */
2063 #ifdef AOF_ASSEMBLER
2065 #define CONSTANT_ADDRESS_P(X) \
2066 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2070 #define CONSTANT_ADDRESS_P(X) \
2071 (GET_CODE (X) == SYMBOL_REF \
2072 && (CONSTANT_POOL_ADDRESS_P (X) \
2073 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2075 #endif /* AOF_ASSEMBLER */
2077 /* Nonzero if the constant value X is a legitimate general operand.
2078 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2080 On the ARM, allow any integer (invalid ones are removed later by insn
2081 patterns), nice doubles and symbol_refs which refer to the function's
2084 When generating pic allow anything. */
2085 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2087 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2088 ( GET_CODE (X) == CONST_INT \
2089 || GET_CODE (X) == CONST_DOUBLE \
2090 || CONSTANT_ADDRESS_P (X) \
2093 #define LEGITIMATE_CONSTANT_P(X) \
2094 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2096 /* Special characters prefixed to function names
2097 in order to encode attribute like information.
2098 Note, '@' and '*' have already been taken. */
2099 #define SHORT_CALL_FLAG_CHAR '^'
2100 #define LONG_CALL_FLAG_CHAR '#'
2102 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2103 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2105 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2106 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2108 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2109 #define SUBTARGET_NAME_ENCODING_LENGTHS
2112 /* This is a C fragment for the inside of a switch statement.
2113 Each case label should return the number of characters to
2114 be stripped from the start of a function's name, if that
2115 name starts with the indicated character. */
2116 #define ARM_NAME_ENCODING_LENGTHS \
2117 case SHORT_CALL_FLAG_CHAR: return 1; \
2118 case LONG_CALL_FLAG_CHAR: return 1; \
2119 case '*': return 1; \
2120 SUBTARGET_NAME_ENCODING_LENGTHS
2122 /* This is how to output a reference to a user-level label named NAME.
2123 `assemble_name' uses this. */
2124 #undef ASM_OUTPUT_LABELREF
2125 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2126 arm_asm_output_labelref (FILE, NAME)
2128 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2129 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2131 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2132 and check its validity for a certain class.
2133 We have two alternate definitions for each of them.
2134 The usual definition accepts all pseudo regs; the other rejects
2135 them unless they have been allocated suitable hard regs.
2136 The symbol REG_OK_STRICT causes the latter definition to be used. */
2137 #ifndef REG_OK_STRICT
2139 #define ARM_REG_OK_FOR_BASE_P(X) \
2140 (REGNO (X) <= LAST_ARM_REGNUM \
2141 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2142 || REGNO (X) == FRAME_POINTER_REGNUM \
2143 || REGNO (X) == ARG_POINTER_REGNUM)
2145 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2146 (REGNO (X) <= LAST_LO_REGNUM \
2147 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2148 || (GET_MODE_SIZE (MODE) >= 4 \
2149 && (REGNO (X) == STACK_POINTER_REGNUM \
2150 || (X) == hard_frame_pointer_rtx \
2151 || (X) == arg_pointer_rtx)))
2153 #define REG_STRICT_P 0
2155 #else /* REG_OK_STRICT */
2157 #define ARM_REG_OK_FOR_BASE_P(X) \
2158 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2160 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2161 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2163 #define REG_STRICT_P 1
2165 #endif /* REG_OK_STRICT */
2167 /* Now define some helpers in terms of the above. */
2169 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2171 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2172 : ARM_REG_OK_FOR_BASE_P (X))
2174 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2176 /* For Thumb, a valid index register is anything that can be used in
2177 a byte load instruction. */
2178 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2180 /* Nonzero if X is a hard reg that can be used as an index
2181 or if it is a pseudo reg. On the Thumb, the stack pointer
2183 #define REG_OK_FOR_INDEX_P(X) \
2185 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2186 : ARM_REG_OK_FOR_INDEX_P (X))
2189 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2190 that is a valid memory address for an instruction.
2191 The MODE argument is the machine mode for the MEM expression
2192 that wants to use this address. */
2194 #define ARM_BASE_REGISTER_RTX_P(X) \
2195 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2197 #define ARM_INDEX_REGISTER_RTX_P(X) \
2198 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2200 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2202 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2206 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2208 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2212 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2214 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2215 else /* if (TARGET_THUMB) */ \
2216 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2219 /* Try machine-dependent ways of modifying an illegitimate address
2220 to be legitimate. If we find one, return the new, valid address. */
2221 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2223 X = arm_legitimize_address (X, OLDX, MODE); \
2225 if (memory_address_p (MODE, X)) \
2229 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2232 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2235 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2238 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2240 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2243 /* Go to LABEL if ADDR (a legitimate address expression)
2244 has an effect that depends on the machine mode it is used for. */
2245 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2247 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2248 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2252 /* Nothing helpful to do for the Thumb */
2253 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2255 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2258 /* Specify the machine mode that this machine uses
2259 for the index in the tablejump instruction. */
2260 #define CASE_VECTOR_MODE Pmode
2262 /* Define as C expression which evaluates to nonzero if the tablejump
2263 instruction expects the table to contain offsets from the address of the
2265 Do not define this if the table should contain absolute addresses. */
2266 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2268 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2269 unsigned is probably best, but may break some code. */
2270 #ifndef DEFAULT_SIGNED_CHAR
2271 #define DEFAULT_SIGNED_CHAR 0
2274 /* Don't cse the address of the function being compiled. */
2275 #define NO_RECURSIVE_FUNCTION_CSE 1
2277 /* Max number of bytes we can move from memory to memory
2278 in one reasonably fast instruction. */
2282 #define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
2284 /* Define if operations between registers always perform the operation
2285 on the full register even if a narrower mode is specified. */
2286 #define WORD_REGISTER_OPERATIONS
2288 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2289 will either zero-extend or sign-extend. The value of this macro should
2290 be the code that says which one of the two operations is implicitly
2291 done, NIL if none. */
2292 #define LOAD_EXTEND_OP(MODE) \
2293 (TARGET_THUMB ? ZERO_EXTEND : \
2294 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2295 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2297 /* Nonzero if access to memory by bytes is slow and undesirable. */
2298 #define SLOW_BYTE_ACCESS 0
2300 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2302 /* Immediate shift counts are truncated by the output routines (or was it
2303 the assembler?). Shift counts in a register are truncated by ARM. Note
2304 that the native compiler puts too large (> 32) immediate shift counts
2305 into a register and shifts by the register, letting the ARM decide what
2306 to do instead of doing that itself. */
2307 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2308 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2309 On the arm, Y in a register is used modulo 256 for the shift. Only for
2310 rotates is modulo 32 used. */
2311 /* #define SHIFT_COUNT_TRUNCATED 1 */
2313 /* All integers have the same format so truncation is easy. */
2314 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2316 /* Calling from registers is a massive pain. */
2317 #define NO_FUNCTION_CSE 1
2319 /* Chars and shorts should be passed as ints. */
2320 #define PROMOTE_PROTOTYPES 1
2322 /* The machine modes of pointers and functions */
2323 #define Pmode SImode
2324 #define FUNCTION_MODE Pmode
2326 #define ARM_FRAME_RTX(X) \
2327 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2328 || (X) == arg_pointer_rtx)
2330 /* Moves to and from memory are quite expensive */
2331 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2332 (TARGET_ARM ? 10 : \
2333 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2334 * (CLASS == LO_REGS ? 1 : 2)))
2336 /* Try to generate sequences that don't involve branches, we can then use
2337 conditional instructions */
2338 #define BRANCH_COST \
2339 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2341 /* Position Independent Code. */
2342 /* We decide which register to use based on the compilation options and
2343 the assembler in use; this is more general than the APCS restriction of
2344 using sb (r9) all the time. */
2345 extern int arm_pic_register;
2347 /* Used when parsing command line option -mpic-register=. */
2348 extern const char * arm_pic_register_string;
2350 /* The register number of the register used to address a table of static
2351 data addresses in memory. */
2352 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2354 #define FINALIZE_PIC arm_finalize_pic (1)
2356 /* We can't directly access anything that contains a symbol,
2357 nor can we indirect via the constant pool. */
2358 #define LEGITIMATE_PIC_OPERAND_P(X) \
2359 (!(symbol_mentioned_p (X) \
2360 || label_mentioned_p (X) \
2361 || (GET_CODE (X) == SYMBOL_REF \
2362 && CONSTANT_POOL_ADDRESS_P (X) \
2363 && (symbol_mentioned_p (get_pool_constant (X)) \
2364 || label_mentioned_p (get_pool_constant (X))))))
2366 /* We need to know when we are making a constant pool; this determines
2367 whether data needs to be in the GOT or can be referenced via a GOT
2369 extern int making_const_table;
2371 /* Handle pragmas for compatibility with Intel's compilers. */
2372 #define REGISTER_TARGET_PRAGMAS() do { \
2373 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2374 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2375 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2378 /* Condition code information. */
2379 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2380 return the mode to be used for the comparison. */
2382 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2384 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2386 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2389 if (GET_CODE (OP1) == CONST_INT \
2390 && ! (const_ok_for_arm (INTVAL (OP1)) \
2391 || (const_ok_for_arm (- INTVAL (OP1))))) \
2393 rtx const_op = OP1; \
2394 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2400 /* The arm5 clz instruction returns 32. */
2401 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2404 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2406 /* Output a push or a pop instruction (only used when profiling). */
2407 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2409 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2410 STACK_POINTER_REGNUM, REGNO); \
2412 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2415 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2417 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2418 STACK_POINTER_REGNUM, REGNO); \
2420 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2422 /* This is how to output a label which precedes a jumptable. Since
2423 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2424 #undef ASM_OUTPUT_CASE_LABEL
2425 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2429 ASM_OUTPUT_ALIGN (FILE, 2); \
2430 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2434 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2439 if (is_called_in_ARM_mode (DECL)) \
2440 fprintf (STREAM, "\t.code 32\n") ; \
2442 fprintf (STREAM, "\t.thumb_func\n") ; \
2444 if (TARGET_POKE_FUNCTION_NAME) \
2445 arm_poke_function_name (STREAM, (char *) NAME); \
2449 /* For aliases of functions we use .thumb_set instead. */
2450 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2453 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2454 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2456 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2458 fprintf (FILE, "\t.thumb_set "); \
2459 assemble_name (FILE, LABEL1); \
2460 fprintf (FILE, ","); \
2461 assemble_name (FILE, LABEL2); \
2462 fprintf (FILE, "\n"); \
2465 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2469 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2470 /* To support -falign-* switches we need to use .p2align so
2471 that alignment directives in code sections will be padded
2472 with no-op instructions, rather than zeroes. */
2473 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2476 if ((MAX_SKIP) == 0) \
2477 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2479 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2480 (int) (LOG), (int) (MAX_SKIP)); \
2484 /* Only perform branch elimination (by making instructions conditional) if
2485 we're optimizing. Otherwise it's of no use anyway. */
2486 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2487 if (TARGET_ARM && optimize) \
2488 arm_final_prescan_insn (INSN); \
2489 else if (TARGET_THUMB) \
2490 thumb_final_prescan_insn (INSN)
2492 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2493 (CODE == '@' || CODE == '|' \
2494 || (TARGET_ARM && (CODE == '?')) \
2495 || (TARGET_THUMB && (CODE == '_')))
2497 /* Output an operand of an instruction. */
2498 #define PRINT_OPERAND(STREAM, X, CODE) \
2499 arm_print_operand (STREAM, X, CODE)
2501 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2502 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2503 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2504 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2505 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2506 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2509 /* Output the address of an operand. */
2510 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2512 int is_minus = GET_CODE (X) == MINUS; \
2514 if (GET_CODE (X) == REG) \
2515 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2516 else if (GET_CODE (X) == PLUS || is_minus) \
2518 rtx base = XEXP (X, 0); \
2519 rtx index = XEXP (X, 1); \
2520 HOST_WIDE_INT offset = 0; \
2521 if (GET_CODE (base) != REG) \
2523 /* Ensure that BASE is a register */ \
2524 /* (one of them must be). */ \
2529 switch (GET_CODE (index)) \
2532 offset = INTVAL (index); \
2535 asm_fprintf (STREAM, "[%r, #%wd]", \
2536 REGNO (base), offset); \
2540 asm_fprintf (STREAM, "[%r, %s%r]", \
2541 REGNO (base), is_minus ? "-" : "", \
2551 asm_fprintf (STREAM, "[%r, %s%r", \
2552 REGNO (base), is_minus ? "-" : "", \
2553 REGNO (XEXP (index, 0))); \
2554 arm_print_operand (STREAM, index, 'S'); \
2555 fputs ("]", STREAM); \
2563 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2564 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2566 extern enum machine_mode output_memory_reference_mode; \
2568 if (GET_CODE (XEXP (X, 0)) != REG) \
2571 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2572 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2573 REGNO (XEXP (X, 0)), \
2574 GET_CODE (X) == PRE_DEC ? "-" : "", \
2575 GET_MODE_SIZE (output_memory_reference_mode)); \
2577 asm_fprintf (STREAM, "[%r], #%s%d", \
2578 REGNO (XEXP (X, 0)), \
2579 GET_CODE (X) == POST_DEC ? "-" : "", \
2580 GET_MODE_SIZE (output_memory_reference_mode)); \
2582 else if (GET_CODE (X) == PRE_MODIFY) \
2584 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2585 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2586 asm_fprintf (STREAM, "#%wd]!", \
2587 INTVAL (XEXP (XEXP (X, 1), 1))); \
2589 asm_fprintf (STREAM, "%r]!", \
2590 REGNO (XEXP (XEXP (X, 1), 1))); \
2592 else if (GET_CODE (X) == POST_MODIFY) \
2594 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2595 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2596 asm_fprintf (STREAM, "#%wd", \
2597 INTVAL (XEXP (XEXP (X, 1), 1))); \
2599 asm_fprintf (STREAM, "%r", \
2600 REGNO (XEXP (XEXP (X, 1), 1))); \
2602 else output_addr_const (STREAM, X); \
2605 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2607 if (GET_CODE (X) == REG) \
2608 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2609 else if (GET_CODE (X) == POST_INC) \
2610 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2611 else if (GET_CODE (X) == PLUS) \
2613 if (GET_CODE (XEXP (X, 0)) != REG) \
2615 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2616 asm_fprintf (STREAM, "[%r, #%wd]", \
2617 REGNO (XEXP (X, 0)), \
2618 INTVAL (XEXP (X, 1))); \
2620 asm_fprintf (STREAM, "[%r, %r]", \
2621 REGNO (XEXP (X, 0)), \
2622 REGNO (XEXP (X, 1))); \
2625 output_addr_const (STREAM, X); \
2628 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2630 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2632 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2634 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2635 if (GET_CODE (X) != CONST_VECTOR \
2636 || ! arm_emit_vector_const (FILE, X)) \
2639 /* A C expression whose value is RTL representing the value of the return
2640 address for the frame COUNT steps up from the current frame. */
2642 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2643 arm_return_addr (COUNT, FRAME)
2645 /* Mask of the bits in the PC that contain the real return address
2646 when running in 26-bit mode. */
2647 #define RETURN_ADDR_MASK26 (0x03fffffc)
2649 /* Pick up the return address upon entry to a procedure. Used for
2650 dwarf2 unwind information. This also enables the table driven
2652 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2653 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2655 /* Used to mask out junk bits from the return address, such as
2656 processor state, interrupt status, condition codes and the like. */
2657 #define MASK_RETURN_ADDR \
2658 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2659 in 26 bit mode, the condition codes must be masked out of the \
2660 return address. This does not apply to ARM6 and later processors \
2661 when running in 32 bit mode. */ \
2662 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2663 : (arm_arch4 || TARGET_THUMB) ? \
2664 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2665 : arm_gen_return_addr_mask ())
2668 /* Define the codes that are matched by predicates in arm.c */
2669 #define PREDICATE_CODES \
2670 {"s_register_operand", {SUBREG, REG}}, \
2671 {"arm_hard_register_operand", {REG}}, \
2672 {"f_register_operand", {SUBREG, REG}}, \
2673 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2674 {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2675 {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2676 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2677 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2678 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2679 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2680 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2681 {"offsettable_memory_operand", {MEM}}, \
2682 {"bad_signed_byte_operand", {MEM}}, \
2683 {"alignable_memory_operand", {MEM}}, \
2684 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2685 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2686 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2687 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2688 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2689 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2690 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2691 {"load_multiple_operation", {PARALLEL}}, \
2692 {"store_multiple_operation", {PARALLEL}}, \
2693 {"equality_operator", {EQ, NE}}, \
2694 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2695 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2697 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2698 {"const_shift_operand", {CONST_INT}}, \
2699 {"multi_register_push", {PARALLEL}}, \
2700 {"cc_register", {REG}}, \
2701 {"logical_binary_operator", {AND, IOR, XOR}}, \
2702 {"cirrus_register_operand", {REG}}, \
2703 {"cirrus_fp_register", {REG}}, \
2704 {"cirrus_shift_const", {CONST_INT}}, \
2705 {"dominant_cc_register", {REG}},
2707 /* Define this if you have special predicates that know special things
2708 about modes. Genrecog will warn about certain forms of
2709 match_operand without a mode; if the operand predicate is listed in
2710 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2711 #define SPECIAL_MODE_PREDICATES \
2712 "cc_register", "dominant_cc_register",
2721 ARM_BUILTIN_WAVG2BR,
2722 ARM_BUILTIN_WAVG2HR,
2749 ARM_BUILTIN_TMOVMSKB,
2750 ARM_BUILTIN_TMOVMSKH,
2751 ARM_BUILTIN_TMOVMSKW,
2760 ARM_BUILTIN_WPACKHSS,
2761 ARM_BUILTIN_WPACKWSS,
2762 ARM_BUILTIN_WPACKDSS,
2763 ARM_BUILTIN_WPACKHUS,
2764 ARM_BUILTIN_WPACKWUS,
2765 ARM_BUILTIN_WPACKDUS,
2770 ARM_BUILTIN_WADDSSB,
2771 ARM_BUILTIN_WADDSSH,
2772 ARM_BUILTIN_WADDSSW,
2773 ARM_BUILTIN_WADDUSB,
2774 ARM_BUILTIN_WADDUSH,
2775 ARM_BUILTIN_WADDUSW,
2779 ARM_BUILTIN_WSUBSSB,
2780 ARM_BUILTIN_WSUBSSH,
2781 ARM_BUILTIN_WSUBSSW,
2782 ARM_BUILTIN_WSUBUSB,
2783 ARM_BUILTIN_WSUBUSH,
2784 ARM_BUILTIN_WSUBUSW,
2791 ARM_BUILTIN_WCMPEQB,
2792 ARM_BUILTIN_WCMPEQH,
2793 ARM_BUILTIN_WCMPEQW,
2794 ARM_BUILTIN_WCMPGTUB,
2795 ARM_BUILTIN_WCMPGTUH,
2796 ARM_BUILTIN_WCMPGTUW,
2797 ARM_BUILTIN_WCMPGTSB,
2798 ARM_BUILTIN_WCMPGTSH,
2799 ARM_BUILTIN_WCMPGTSW,
2801 ARM_BUILTIN_TEXTRMSB,
2802 ARM_BUILTIN_TEXTRMSH,
2803 ARM_BUILTIN_TEXTRMSW,
2804 ARM_BUILTIN_TEXTRMUB,
2805 ARM_BUILTIN_TEXTRMUH,
2806 ARM_BUILTIN_TEXTRMUW,
2856 ARM_BUILTIN_WUNPCKIHB,
2857 ARM_BUILTIN_WUNPCKIHH,
2858 ARM_BUILTIN_WUNPCKIHW,
2859 ARM_BUILTIN_WUNPCKILB,
2860 ARM_BUILTIN_WUNPCKILH,
2861 ARM_BUILTIN_WUNPCKILW,
2863 ARM_BUILTIN_WUNPCKEHSB,
2864 ARM_BUILTIN_WUNPCKEHSH,
2865 ARM_BUILTIN_WUNPCKEHSW,
2866 ARM_BUILTIN_WUNPCKEHUB,
2867 ARM_BUILTIN_WUNPCKEHUH,
2868 ARM_BUILTIN_WUNPCKEHUW,
2869 ARM_BUILTIN_WUNPCKELSB,
2870 ARM_BUILTIN_WUNPCKELSH,
2871 ARM_BUILTIN_WUNPCKELSW,
2872 ARM_BUILTIN_WUNPCKELUB,
2873 ARM_BUILTIN_WUNPCKELUH,
2874 ARM_BUILTIN_WUNPCKELUW,
2878 #endif /* ! GCC_ARM_H */
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