1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define ("__arm__"); \
36 builtin_define ("__thumb__"); \
40 builtin_define ("__ARMEB__"); \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
48 builtin_define ("__ARMEL__"); \
50 builtin_define ("__THUMBEL__"); \
54 builtin_define ("__APCS_32__"); \
56 builtin_define ("__APCS_26__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 #define TARGET_CPU_iwmmxt 0x0400
101 #define TARGET_CPU_arm926ej_s 0x0800
102 #define TARGET_CPU_arm1026ej_s 0x1000
103 #define TARGET_CPU_arm1136j_s 0x2000
104 #define TARGET_CPU_arm1136jf_s 0x4000
105 /* Configure didn't specify. */
106 #define TARGET_CPU_generic 0x8000
108 typedef enum arm_cond_code
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
115 extern arm_cc arm_current_cc;
117 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
119 extern int arm_target_label;
120 extern int arm_ccfsm_state;
121 extern GTY(()) rtx arm_target_insn;
122 /* Run-time compilation parameters selecting different hardware subsets. */
123 extern int target_flags;
124 /* The floating point instruction architecture, can be 2 or 3 */
125 extern const char * target_fp_name;
126 /* Define the information needed to generate branch insns. This is
127 stored from the compare operation. */
128 extern GTY(()) rtx arm_compare_op0;
129 extern GTY(()) rtx arm_compare_op1;
130 /* The label of the current constant pool. */
131 extern rtx pool_vector_label;
132 /* Set to 1 when a return insn is output, this means that the epilogue
134 extern int return_used_this_function;
135 /* Used to produce AOF syntax assembler. */
136 extern GTY(()) rtx aof_pic_label;
138 /* Just in case configure has failed to define anything. */
139 #ifndef TARGET_CPU_DEFAULT
140 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
143 /* If the configuration file doesn't specify the cpu, the subtarget may
144 override it. If it doesn't, then default to an ARM6. */
145 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
146 #undef TARGET_CPU_DEFAULT
148 #ifdef SUBTARGET_CPU_DEFAULT
149 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
151 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
155 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
156 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
158 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
159 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
162 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
164 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
165 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
168 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
170 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
171 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
173 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
174 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
175 /* Set TARGET_DEFAULT to the default, but without soft-float. */
176 #ifdef TARGET_DEFAULT
177 #undef TARGET_DEFAULT
178 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
182 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
184 #error Unrecognized value in TARGET_CPU_DEFAULT.
195 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
196 %{mapcs-32:%{mapcs-26: \
197 %e-mapcs-26 and -mapcs-32 may not be used together}} \
198 %{msoft-float:%{mhard-float: \
199 %e-msoft-float and -mhard_float may not be used together}} \
200 %{mbig-endian:%{mlittle-endian: \
201 %e-mbig-endian and -mlittle-endian may not be used together}}"
203 /* Set the architecture define -- if -march= is set, then it overrides
204 the -mcpu= setting. */
205 #define CPP_CPU_ARCH_SPEC "\
206 %{march=arm2:-D__ARM_ARCH_2__} \
207 %{march=arm250:-D__ARM_ARCH_2__} \
208 %{march=arm3:-D__ARM_ARCH_2__} \
209 %{march=arm6:-D__ARM_ARCH_3__} \
210 %{march=arm600:-D__ARM_ARCH_3__} \
211 %{march=arm610:-D__ARM_ARCH_3__} \
212 %{march=arm7:-D__ARM_ARCH_3__} \
213 %{march=arm700:-D__ARM_ARCH_3__} \
214 %{march=arm710:-D__ARM_ARCH_3__} \
215 %{march=arm720:-D__ARM_ARCH_3__} \
216 %{march=arm7100:-D__ARM_ARCH_3__} \
217 %{march=arm7500:-D__ARM_ARCH_3__} \
218 %{march=arm7500fe:-D__ARM_ARCH_3__} \
219 %{march=arm7m:-D__ARM_ARCH_3M__} \
220 %{march=arm7dm:-D__ARM_ARCH_3M__} \
221 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
222 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
223 %{march=arm8:-D__ARM_ARCH_4__} \
224 %{march=arm810:-D__ARM_ARCH_4__} \
225 %{march=arm9:-D__ARM_ARCH_4T__} \
226 %{march=arm920:-D__ARM_ARCH_4__} \
227 %{march=arm920t:-D__ARM_ARCH_4T__} \
228 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
229 %{march=strongarm:-D__ARM_ARCH_4__} \
230 %{march=strongarm110:-D__ARM_ARCH_4__} \
231 %{march=strongarm1100:-D__ARM_ARCH_4__} \
232 %{march=xscale:-D__ARM_ARCH_5TE__} \
233 %{march=xscale:-D__XSCALE__} \
234 %{march=ep9312:-D__ARM_ARCH_4T__} \
235 %{march=ep9312:-D__MAVERICK__} \
236 %{march=armv2:-D__ARM_ARCH_2__} \
237 %{march=armv2a:-D__ARM_ARCH_2__} \
238 %{march=armv3:-D__ARM_ARCH_3__} \
239 %{march=armv3m:-D__ARM_ARCH_3M__} \
240 %{march=armv4:-D__ARM_ARCH_4__} \
241 %{march=armv4t:-D__ARM_ARCH_4T__} \
242 %{march=armv5:-D__ARM_ARCH_5__} \
243 %{march=armv5t:-D__ARM_ARCH_5T__} \
244 %{march=armv5e:-D__ARM_ARCH_5E__} \
245 %{march=armv5te:-D__ARM_ARCH_5TE__} \
247 %{mcpu=arm2:-D__ARM_ARCH_2__} \
248 %{mcpu=arm250:-D__ARM_ARCH_2__} \
249 %{mcpu=arm3:-D__ARM_ARCH_2__} \
250 %{mcpu=arm6:-D__ARM_ARCH_3__} \
251 %{mcpu=arm600:-D__ARM_ARCH_3__} \
252 %{mcpu=arm610:-D__ARM_ARCH_3__} \
253 %{mcpu=arm7:-D__ARM_ARCH_3__} \
254 %{mcpu=arm700:-D__ARM_ARCH_3__} \
255 %{mcpu=arm710:-D__ARM_ARCH_3__} \
256 %{mcpu=arm720:-D__ARM_ARCH_3__} \
257 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
258 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
259 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
260 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
261 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
262 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
263 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
264 %{mcpu=arm8:-D__ARM_ARCH_4__} \
265 %{mcpu=arm810:-D__ARM_ARCH_4__} \
266 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
267 %{mcpu=arm920:-D__ARM_ARCH_4__} \
268 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
269 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
270 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
271 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
272 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
273 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
274 %{mcpu=xscale:-D__XSCALE__} \
275 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
276 %{mcpu=ep9312:-D__MAVERICK__} \
277 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
278 %{mcpu=iwmmxt:-D__XSCALE__} \
279 %{mcpu=iwmmxt:-D__IWMMXT__} \
280 %{!mcpu*:%(cpp_cpu_arch_default)}} \
287 /* This macro defines names of additional specifications to put in the specs
288 that can be used in various specifications like CC1_SPEC. Its definition
289 is an initializer with a subgrouping for each command option.
291 Each subgrouping contains a string constant, that defines the
292 specification name, and a string constant that used by the GCC driver
295 Do not define this macro if it does not need to do anything. */
296 #define EXTRA_SPECS \
297 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
298 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
299 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
300 SUBTARGET_EXTRA_SPECS
302 #ifndef SUBTARGET_EXTRA_SPECS
303 #define SUBTARGET_EXTRA_SPECS
306 #ifndef SUBTARGET_CPP_SPEC
307 #define SUBTARGET_CPP_SPEC ""
310 /* Run-time Target Specification. */
311 #ifndef TARGET_VERSION
312 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
315 /* Nonzero if the function prologue (and epilogue) should obey
316 the ARM Procedure Call Standard. */
317 #define ARM_FLAG_APCS_FRAME (1 << 0)
319 /* Nonzero if the function prologue should output the function name to enable
320 the post mortem debugger to print a backtrace (very useful on RISCOS,
321 unused on RISCiX). Specifying this flag also enables
322 -fno-omit-frame-pointer.
323 XXX Must still be implemented in the prologue. */
324 #define ARM_FLAG_POKE (1 << 1)
326 /* Nonzero if floating point instructions are emulated by the FPE, in which
327 case instruction scheduling becomes very uninteresting. */
328 #define ARM_FLAG_FPE (1 << 2)
330 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
331 that assume restoration of the condition flags when returning from a
332 branch and link (ie a function). */
333 #define ARM_FLAG_APCS_32 (1 << 3)
335 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
337 /* Nonzero if stack checking should be performed on entry to each function
338 which allocates temporary variables on the stack. */
339 #define ARM_FLAG_APCS_STACK (1 << 4)
341 /* Nonzero if floating point parameters should be passed to functions in
342 floating point registers. */
343 #define ARM_FLAG_APCS_FLOAT (1 << 5)
345 /* Nonzero if re-entrant, position independent code should be generated.
346 This is equivalent to -fpic. */
347 #define ARM_FLAG_APCS_REENT (1 << 6)
349 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
350 be loaded using either LDRH or LDRB instructions. */
351 #define ARM_FLAG_MMU_TRAPS (1 << 7)
353 /* Nonzero if all floating point instructions are missing (and there is no
354 emulator either). Generate function calls for all ops in this case. */
355 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
357 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
358 #define ARM_FLAG_BIG_END (1 << 9)
360 /* Nonzero if we should compile for Thumb interworking. */
361 #define ARM_FLAG_INTERWORK (1 << 10)
363 /* Nonzero if we should have little-endian words even when compiling for
364 big-endian (for backwards compatibility with older versions of GCC). */
365 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
367 /* Nonzero if we need to protect the prolog from scheduling */
368 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
370 /* Nonzero if a call to abort should be generated if a noreturn
371 function tries to return. */
372 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
374 /* Nonzero if function prologues should not load the PIC register. */
375 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
377 /* Nonzero if all call instructions should be indirect. */
378 #define ARM_FLAG_LONG_CALLS (1 << 15)
380 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
381 #define ARM_FLAG_THUMB (1 << 16)
383 /* Set if a TPCS style stack frame should be generated, for non-leaf
384 functions, even if they do not need one. */
385 #define THUMB_FLAG_BACKTRACE (1 << 17)
387 /* Set if a TPCS style stack frame should be generated, for leaf
388 functions, even if they do not need one. */
389 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
391 /* Set if externally visible functions should assume that they
392 might be called in ARM mode, from a non-thumb aware code. */
393 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
395 /* Set if calls via function pointers should assume that their
396 destination is non-Thumb aware. */
397 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
399 /* Nonzero means target uses VFP FP. */
400 #define ARM_FLAG_VFP (1 << 21)
402 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
403 #define ARM_FLAG_ATPCS (1 << 22)
405 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
406 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
408 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
409 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
410 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
411 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
412 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
413 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
414 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
415 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
416 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
417 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
418 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
419 #define TARGET_CIRRUS (arm_is_cirrus)
420 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
421 #define TARGET_IWMMXT (arm_arch_iwmmxt)
422 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
423 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
424 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
425 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
426 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
427 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
428 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
429 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
430 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
431 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
432 #define TARGET_ARM (! TARGET_THUMB)
433 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
434 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
435 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
436 #define TARGET_BACKTRACE (leaf_function_p () \
437 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
438 : (target_flags & THUMB_FLAG_BACKTRACE))
439 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
441 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
442 #ifndef SUBTARGET_SWITCHES
443 #define SUBTARGET_SWITCHES
446 #define TARGET_SWITCHES \
448 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
449 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
450 N_("Generate APCS conformant stack frames") }, \
451 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
452 {"poke-function-name", ARM_FLAG_POKE, \
453 N_("Store function names in object code") }, \
454 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
455 {"fpe", ARM_FLAG_FPE, "" }, \
456 {"apcs-32", ARM_FLAG_APCS_32, \
457 N_("Use the 32-bit version of the APCS") }, \
458 {"apcs-26", -ARM_FLAG_APCS_32, \
459 N_("Use the 26-bit version of the APCS") }, \
460 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
461 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
462 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
463 N_("Pass FP arguments in FP registers") }, \
464 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
465 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
466 N_("Generate re-entrant, PIC code") }, \
467 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
468 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
469 N_("The MMU will trap on unaligned accesses") }, \
470 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
471 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
472 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
473 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
474 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
475 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
476 N_("Use library calls to perform FP operations") }, \
477 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
478 N_("Use hardware floating point instructions") }, \
479 {"big-endian", ARM_FLAG_BIG_END, \
480 N_("Assume target CPU is configured as big endian") }, \
481 {"little-endian", -ARM_FLAG_BIG_END, \
482 N_("Assume target CPU is configured as little endian") }, \
483 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
484 N_("Assume big endian bytes, little endian words") }, \
485 {"thumb-interwork", ARM_FLAG_INTERWORK, \
486 N_("Support calls between Thumb and ARM instruction sets") }, \
487 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
488 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
489 N_("Generate a call to abort if a noreturn function returns")}, \
490 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
491 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
492 N_("Do not move instructions into a function's prologue") }, \
493 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
494 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
495 N_("Do not load the PIC register in function prologues") }, \
496 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
497 {"long-calls", ARM_FLAG_LONG_CALLS, \
498 N_("Generate call insns as indirect calls, if necessary") }, \
499 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
500 {"thumb", ARM_FLAG_THUMB, \
501 N_("Compile for the Thumb not the ARM") }, \
502 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
503 {"arm", -ARM_FLAG_THUMB, "" }, \
504 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
505 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
506 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
507 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
508 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
509 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
510 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
511 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
512 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
514 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
515 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
516 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
518 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
519 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
520 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
521 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
523 {"", TARGET_DEFAULT, "" } \
526 #define TARGET_OPTIONS \
528 {"cpu=", & arm_select[0].string, \
529 N_("Specify the name of the target CPU"), 0}, \
530 {"arch=", & arm_select[1].string, \
531 N_("Specify the name of the target architecture"), 0}, \
532 {"tune=", & arm_select[2].string, "", 0}, \
533 {"fpe=", & target_fp_name, "" , 0}, \
534 {"fp=", & target_fp_name, \
535 N_("Specify the version of the floating point emulator"), 0},\
536 {"structure-size-boundary=", & structure_size_string, \
537 N_("Specify the minimum bit alignment of structures"), 0}, \
538 {"pic-register=", & arm_pic_register_string, \
539 N_("Specify the register to be used for PIC addressing"), 0} \
542 /* Support for a compile-time default CPU, et cetera. The rules are:
543 --with-arch is ignored if -march or -mcpu are specified.
544 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
546 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
548 --with-float is ignored if -mhard-float or -msoft-float are
550 #define OPTION_DEFAULT_SPECS \
551 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
552 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
553 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
554 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
556 struct arm_cpu_select
560 const struct processors * processors;
563 /* This is a magic array. If the user specifies a command line switch
564 which matches one of the entries in TARGET_OPTIONS then the corresponding
565 string pointer will be set to the value specified by the user. */
566 extern struct arm_cpu_select arm_select[];
574 /* Recast the program mode class to be the prog_mode attribute. */
575 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
577 extern enum prog_mode_type arm_prgmode;
579 /* What sort of floating point unit do we have? Hardware or software.
580 If software, is it issue 2 or issue 3? */
583 /* Software floating point, FPA style double fmt. */
585 /* Full FPA support. */
587 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
589 /* Emulated FPA hardware, Issue 3 emulator. */
591 /* Cirrus Maverick floating point co-processor. */
595 /* Recast the floating point class to be the floating point attribute. */
596 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
598 /* What type of floating point to tune for */
599 extern enum fputype arm_fpu_tune;
601 /* What type of floating point instructions are available */
602 extern enum fputype arm_fpu_arch;
604 /* Default floating point architecture. Override in sub-target if
606 #ifndef FPUTYPE_DEFAULT
607 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
610 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
611 #undef FPUTYPE_DEFAULT
612 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
615 /* Nonzero if the processor has a fast multiply insn, and one that does
616 a 64-bit multiply of two 32-bit values. */
617 extern int arm_fast_multiply;
619 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
620 extern int arm_arch4;
622 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
623 extern int arm_arch5;
625 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
626 extern int arm_arch5e;
628 /* Nonzero if this chip can benefit from load scheduling. */
629 extern int arm_ld_sched;
631 /* Nonzero if generating thumb code. */
632 extern int thumb_code;
634 /* Nonzero if this chip is a StrongARM. */
635 extern int arm_is_strong;
637 /* Nonzero if this chip is a Cirrus variant. */
638 extern int arm_is_cirrus;
640 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
641 extern int arm_arch_iwmmxt;
643 /* Nonzero if this chip is an XScale. */
644 extern int arm_arch_xscale;
646 /* Nonzero if tuning for XScale */
647 extern int arm_tune_xscale;
649 /* Nonzero if this chip is an ARM6 or an ARM7. */
650 extern int arm_is_6_or_7;
652 #ifndef TARGET_DEFAULT
653 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
656 /* The frame pointer register used in gcc has nothing to do with debugging;
657 that is controlled by the APCS-FRAME option. */
658 #define CAN_DEBUG_WITHOUT_FP
660 #undef TARGET_MEM_FUNCTIONS
661 #define TARGET_MEM_FUNCTIONS 1
663 #define OVERRIDE_OPTIONS arm_override_options ()
665 /* Nonzero if PIC code requires explicit qualifiers to generate
666 PLT and GOT relocs rather than the assembler doing so implicitly.
667 Subtargets can override these if required. */
668 #ifndef NEED_GOT_RELOC
669 #define NEED_GOT_RELOC 0
671 #ifndef NEED_PLT_RELOC
672 #define NEED_PLT_RELOC 0
675 /* Nonzero if we need to refer to the GOT with a PC-relative
676 offset. In other words, generate
678 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
682 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
684 The default is true, which matches NetBSD. Subtargets can
685 override this if required. */
690 /* Target machine storage Layout. */
693 /* Define this macro if it is advisable to hold scalars in registers
694 in a wider mode than that declared by the program. In such cases,
695 the value is constrained to be within the bounds of the declared
696 type, but kept valid in the wider mode. The signedness of the
697 extension may differ from that of the type. */
699 /* It is far faster to zero extend chars than to sign extend them */
701 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
702 if (GET_MODE_CLASS (MODE) == MODE_INT \
703 && GET_MODE_SIZE (MODE) < 4) \
705 if (MODE == QImode) \
707 else if (MODE == HImode) \
708 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
712 /* Define this if most significant bit is lowest numbered
713 in instructions that operate on numbered bit-fields. */
714 #define BITS_BIG_ENDIAN 0
716 /* Define this if most significant byte of a word is the lowest numbered.
717 Most ARM processors are run in little endian mode, so that is the default.
718 If you want to have it run-time selectable, change the definition in a
719 cover file to be TARGET_BIG_ENDIAN. */
720 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
722 /* Define this if most significant word of a multiword number is the lowest
724 This is always false, even when in big-endian mode. */
725 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
727 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
728 on processor pre-defineds when compiling libgcc2.c. */
729 #if defined(__ARMEB__) && !defined(__ARMWEL__)
730 #define LIBGCC2_WORDS_BIG_ENDIAN 1
732 #define LIBGCC2_WORDS_BIG_ENDIAN 0
735 /* Define this if most significant word of doubles is the lowest numbered.
736 The rules are different based on whether or not we use FPA-format,
737 VFP-format or some other floating point co-processor's format doubles. */
738 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
740 #define UNITS_PER_WORD 4
742 #define PARM_BOUNDARY 32
744 #define IWMMXT_ALIGNMENT 64
746 #define STACK_BOUNDARY 32
748 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
750 #define FUNCTION_BOUNDARY 32
752 /* The lowest bit is used to indicate Thumb-mode functions, so the
753 vbit must go into the delta field of pointers to member
755 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
757 #define EMPTY_FIELD_BOUNDARY 32
759 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
761 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
762 (TARGET_REALLY_IWMMXT \
763 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
765 /* XXX Blah -- this macro is used directly by libobjc. Since it
766 supports no vector modes, cut out the complexity and fall back
767 on BIGGEST_FIELD_ALIGNMENT. */
768 #ifdef IN_TARGET_LIBS
769 #define BIGGEST_FIELD_ALIGNMENT 64
771 /* An expression for the alignment of a structure field FIELD if the
772 alignment computed in the usual way is COMPUTED. GCC uses this
773 value instead of the value in `BIGGEST_ALIGNMENT' or
774 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
775 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
776 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
781 /* If defined, a C expression to compute the alignment for a static variable.
782 TYPE is the data type, and ALIGN is the alignment that the object
783 would ordinarily have. The value of this macro is used instead of that
784 alignment to align the object.
786 If this macro is not defined, then ALIGN is used. */
787 #define DATA_ALIGNMENT(TYPE, ALIGN) \
788 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
790 /* If defined, a C expression to compute the alignment for a
791 variables in the local store. TYPE is the data type, and
792 BASIC-ALIGN is the alignment that the object would ordinarily
793 have. The value of this macro is used instead of that alignment
796 If this macro is not defined, then BASIC-ALIGN is used. */
797 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
798 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
800 /* Make strings word-aligned so strcpy from constants will be faster. */
801 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
803 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
804 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
805 (TREE_CODE (EXP) == STRING_CST \
806 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
807 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
809 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
810 value set in previous versions of this toolchain was 8, which produces more
811 compact structures. The command line option -mstructure_size_boundary=<n>
812 can be used to change this value. For compatibility with the ARM SDK
813 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
814 0020D) page 2-20 says "Structures are aligned on word boundaries". */
815 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
816 extern int arm_structure_size_boundary;
818 /* This is the value used to initialize arm_structure_size_boundary. If a
819 particular arm target wants to change the default value it should change
820 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
821 for an example of this. */
822 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
823 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
826 /* Used when parsing command line option -mstructure_size_boundary. */
827 extern const char * structure_size_string;
829 /* Nonzero if move instructions will actually fail to work
830 when given unaligned data. */
831 #define STRICT_ALIGNMENT 1
833 /* Standard register usage. */
835 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
836 (S - saved over call).
838 r0 * argument word/integer result
841 r4-r8 S register variable
842 r9 S (rfp) register variable (real frame pointer)
844 r10 F S (sl) stack limit (used by -mapcs-stack-check)
845 r11 F S (fp) argument pointer
846 r12 (ip) temp workspace
847 r13 F S (sp) lower end of current stack frame
848 r14 (lr) link address/workspace
849 r15 F (pc) program counter
851 f0 floating point result
852 f1-f3 floating point scratch
854 f4-f7 S floating point variable
856 cc This is NOT a real register, but is used internally
857 to represent things that use or set the condition
859 sfp This isn't either. It is used during rtl generation
860 since the offset between the frame pointer and the
861 auto's isn't known until after register allocation.
862 afp Nor this, we only need this because of non-local
863 goto. Without it fp appears to be used and the
864 elimination code won't get rid of sfp. It tracks
865 fp exactly at all times.
867 *: See CONDITIONAL_REGISTER_USAGE */
870 mvf0 Cirrus floating point result
871 mvf1-mvf3 Cirrus floating point scratch
872 mvf4-mvf15 S Cirrus floating point variable. */
874 /* The stack backtrace structure is as follows:
875 fp points to here: | save code pointer | [fp]
876 | return link value | [fp, #-4]
877 | return sp value | [fp, #-8]
878 | return fp value | [fp, #-12]
879 [| saved r10 value |]
890 [| saved f7 value |] three words
891 [| saved f6 value |] three words
892 [| saved f5 value |] three words
893 [| saved f4 value |] three words
894 r0-r3 are not normally saved in a C function. */
896 /* 1 for registers that have pervasive standard uses
897 and are not available for the register allocator. */
898 #define FIXED_REGISTERS \
911 /* 1 for registers not available across function calls.
912 These must include the FIXED_REGISTERS and also any
913 registers that can be used without being saved.
914 The latter must include the registers where values are returned
915 and the register where structure-value addresses are passed.
916 Aside from that, you can include as many other registers as you like.
917 The CC is not preserved over function calls on the ARM 6, so it is
918 easier to assume this for all. SFP is preserved, since FP is. */
919 #define CALL_USED_REGISTERS \
932 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
933 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
936 #define CONDITIONAL_REGISTER_USAGE \
940 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
942 for (regno = FIRST_ARM_FP_REGNUM; \
943 regno <= LAST_ARM_FP_REGNUM; ++regno) \
944 fixed_regs[regno] = call_used_regs[regno] = 1; \
947 if (TARGET_THUMB && optimize_size) \
949 /* When optimizing for size, it's better not to use \
950 the HI regs, because of the overhead of stacking \
952 for (regno = FIRST_HI_REGNUM; \
953 regno <= LAST_HI_REGNUM; ++regno) \
954 fixed_regs[regno] = call_used_regs[regno] = 1; \
957 /* The link register can be clobbered by any branch insn, \
958 but we have no way to track that at present, so mark \
959 it as unavailable. */ \
961 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
965 for (regno = FIRST_ARM_FP_REGNUM; \
966 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
967 fixed_regs[regno] = call_used_regs[regno] = 1; \
968 for (regno = FIRST_CIRRUS_FP_REGNUM; \
969 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
971 fixed_regs[regno] = 0; \
972 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
976 if (TARGET_REALLY_IWMMXT) \
978 regno = FIRST_IWMMXT_GR_REGNUM; \
979 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
980 and wCG1 as call-preserved registers. The 2002/11/21 \
981 revision changed this so that all wCG registers are \
982 scratch registers. */ \
983 for (regno = FIRST_IWMMXT_GR_REGNUM; \
984 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
985 fixed_regs[regno] = call_used_regs[regno] = 0; \
986 /* The XScale ABI has wR0 - wR9 as scratch registers, \
987 the rest as call-preserved registers. */ \
988 for (regno = FIRST_IWMMXT_REGNUM; \
989 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
991 fixed_regs[regno] = 0; \
992 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
996 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
998 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
999 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1001 else if (TARGET_APCS_STACK) \
1003 fixed_regs[10] = 1; \
1004 call_used_regs[10] = 1; \
1006 if (TARGET_APCS_FRAME) \
1008 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1009 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1011 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
1014 /* These are a couple of extensions to the formats accepted
1016 %@ prints out ASM_COMMENT_START
1017 %r prints out REGISTER_PREFIX reg_names[arg] */
1018 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1020 fputs (ASM_COMMENT_START, FILE); \
1024 fputs (REGISTER_PREFIX, FILE); \
1025 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1028 /* Round X up to the nearest word. */
1029 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1031 /* Convert fron bytes to ints. */
1032 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1034 /* The number of (integer) registers required to hold a quantity of type MODE. */
1035 #define ARM_NUM_REGS(MODE) \
1036 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1038 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1039 #define ARM_NUM_REGS2(MODE, TYPE) \
1040 ARM_NUM_INTS ((MODE) == BLKmode ? \
1041 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1043 /* The number of (integer) argument register available. */
1044 #define NUM_ARG_REGS 4
1046 /* Return the register number of the N'th (integer) argument. */
1047 #define ARG_REGISTER(N) (N - 1)
1049 /* Specify the registers used for certain standard purposes.
1050 The values of these macros are register numbers. */
1052 /* The number of the last argument register. */
1053 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1055 /* The numbers of the Thumb register ranges. */
1056 #define FIRST_LO_REGNUM 0
1057 #define LAST_LO_REGNUM 7
1058 #define FIRST_HI_REGNUM 8
1059 #define LAST_HI_REGNUM 11
1061 /* The register that holds the return address in exception handlers. */
1062 #define EXCEPTION_LR_REGNUM 2
1064 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1065 as an invisible last argument (possible since varargs don't exist in
1066 Pascal), so the following is not true. */
1067 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1069 /* Define this to be where the real frame pointer is if it is not possible to
1070 work out the offset between the frame pointer and the automatic variables
1071 until after register allocation has taken place. FRAME_POINTER_REGNUM
1072 should point to a special register that we will make sure is eliminated.
1074 For the Thumb we have another problem. The TPCS defines the frame pointer
1075 as r11, and GCC believes that it is always possible to use the frame pointer
1076 as base register for addressing purposes. (See comments in
1077 find_reloads_address()). But - the Thumb does not allow high registers,
1078 including r11, to be used as base address registers. Hence our problem.
1080 The solution used here, and in the old thumb port is to use r7 instead of
1081 r11 as the hard frame pointer and to have special code to generate
1082 backtrace structures on the stack (if required to do so via a command line
1083 option) using r11. This is the only 'user visible' use of r11 as a frame
1085 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1086 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1088 #define HARD_FRAME_POINTER_REGNUM \
1090 ? ARM_HARD_FRAME_POINTER_REGNUM \
1091 : THUMB_HARD_FRAME_POINTER_REGNUM)
1093 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1095 /* Register to use for pushing function arguments. */
1096 #define STACK_POINTER_REGNUM SP_REGNUM
1098 /* ARM floating pointer registers. */
1099 #define FIRST_ARM_FP_REGNUM 16
1100 #define LAST_ARM_FP_REGNUM 23
1102 #define FIRST_IWMMXT_GR_REGNUM 43
1103 #define LAST_IWMMXT_GR_REGNUM 46
1104 #define FIRST_IWMMXT_REGNUM 47
1105 #define LAST_IWMMXT_REGNUM 62
1106 #define IS_IWMMXT_REGNUM(REGNUM) \
1107 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1108 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1109 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1111 /* Base register for access to local variables of the function. */
1112 #define FRAME_POINTER_REGNUM 25
1114 /* Base register for access to arguments of the function. */
1115 #define ARG_POINTER_REGNUM 26
1117 #define FIRST_CIRRUS_FP_REGNUM 27
1118 #define LAST_CIRRUS_FP_REGNUM 42
1119 #define IS_CIRRUS_REGNUM(REGNUM) \
1120 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1122 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1123 /* + 16 Cirrus registers take us up to 43. */
1124 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1125 #define FIRST_PSEUDO_REGISTER 63
1127 /* Value should be nonzero if functions must have frame pointers.
1128 Zero means the frame pointer need not be set up (and parms may be accessed
1129 via the stack pointer) in functions that seem suitable.
1130 If we have to have a frame pointer we might as well make use of it.
1131 APCS says that the frame pointer does not need to be pushed in leaf
1132 functions, or simple tail call functions. */
1133 #define FRAME_POINTER_REQUIRED \
1134 (current_function_has_nonlocal_label \
1135 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1137 /* Return number of consecutive hard regs needed starting at reg REGNO
1138 to hold something of mode MODE.
1139 This is ordinarily the length in words of a value of mode MODE
1140 but can be less for certain modes in special long registers.
1142 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1144 #define HARD_REGNO_NREGS(REGNO, MODE) \
1146 && REGNO >= FIRST_ARM_FP_REGNUM \
1147 && REGNO != FRAME_POINTER_REGNUM \
1148 && REGNO != ARG_POINTER_REGNUM) \
1149 ? 1 : ARM_NUM_REGS (MODE))
1151 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1152 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1153 arm_hard_regno_mode_ok ((REGNO), (MODE))
1155 /* Value is 1 if it is a good idea to tie two pseudo registers
1156 when one has mode MODE1 and one has mode MODE2.
1157 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1158 for any hard reg, then this must be 0 for correct output. */
1159 #define MODES_TIEABLE_P(MODE1, MODE2) \
1160 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1162 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1163 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1165 #define VALID_IWMMXT_REG_MODE(MODE) \
1166 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1168 /* The order in which register should be allocated. It is good to use ip
1169 since no saving is required (though calls clobber it) and it never contains
1170 function parameters. It is quite good to use lr since other calls may
1171 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1172 least likely to contain a function parameter; in addition results are
1174 #define REG_ALLOC_ORDER \
1176 3, 2, 1, 0, 12, 14, 4, 5, \
1177 6, 7, 8, 10, 9, 11, 13, 15, \
1178 16, 17, 18, 19, 20, 21, 22, 23, \
1179 27, 28, 29, 30, 31, 32, 33, 34, \
1180 35, 36, 37, 38, 39, 40, 41, 42, \
1181 43, 44, 45, 46, 47, 48, 49, 50, \
1182 51, 52, 53, 54, 55, 56, 57, 58, \
1187 /* Interrupt functions can only use registers that have already been
1188 saved by the prologue, even if they would normally be
1190 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1191 (! IS_INTERRUPT (cfun->machine->func_type) || \
1192 regs_ever_live[DST])
1194 /* Register and constant classes. */
1196 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1197 Now that the Thumb is involved it has become more complicated. */
1215 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1217 /* Give names of register classes as strings for dump file. */
1218 #define REG_CLASS_NAMES \
1234 /* Define which registers fit in which classes.
1235 This is an initializer for a vector of HARD_REG_SET
1236 of length N_REG_CLASSES. */
1237 #define REG_CLASS_CONTENTS \
1239 { 0x00000000, 0x0 }, /* NO_REGS */ \
1240 { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
1241 { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
1242 { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\
1243 { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \
1244 { 0x000000FF, 0x0 }, /* LO_REGS */ \
1245 { 0x00002000, 0x0 }, /* STACK_REG */ \
1246 { 0x000020FF, 0x0 }, /* BASE_REGS */ \
1247 { 0x0000FF00, 0x0 }, /* HI_REGS */ \
1248 { 0x01000000, 0x0 }, /* CC_REG */ \
1249 { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\
1250 { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1253 /* The same information, inverted:
1254 Return the class number of the smallest class containing
1255 reg number REGNO. This could be a conditional expression
1256 or could index an array. */
1257 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1259 /* FPA registers can't do dubreg as all values are reformatted to internal
1261 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1262 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1263 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0)
1265 /* The class value for index registers, and the one for base regs. */
1266 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1267 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1269 /* For the Thumb the high registers cannot be used as base registers
1270 when addressing quantities in QI or HI mode; if we don't know the
1271 mode, then we must be conservative. After reload we must also be
1272 conservative, since we can't support SP+reg addressing, and we
1273 can't fix up any bad substitutions. */
1274 #define MODE_BASE_REG_CLASS(MODE) \
1275 (TARGET_ARM ? GENERAL_REGS : \
1276 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1278 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1279 registers explicitly used in the rtl to be used as spill registers
1280 but prevents the compiler from extending the lifetime of these
1282 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1284 /* Get reg_class from a letter such as appears in the machine description.
1285 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1286 ARM, but several more letters for the Thumb. */
1287 #define REG_CLASS_FROM_LETTER(C) \
1288 ( (C) == 'f' ? FPA_REGS \
1289 : (C) == 'v' ? CIRRUS_REGS \
1290 : (C) == 'y' ? IWMMXT_REGS \
1291 : (C) == 'z' ? IWMMXT_GR_REGS \
1292 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1293 : TARGET_ARM ? NO_REGS \
1294 : (C) == 'h' ? HI_REGS \
1295 : (C) == 'b' ? BASE_REGS \
1296 : (C) == 'k' ? STACK_REG \
1297 : (C) == 'c' ? CC_REG \
1300 /* The letters I, J, K, L and M in a register constraint string
1301 can be used to stand for particular ranges of immediate operands.
1302 This macro defines what the ranges are.
1303 C is the letter, and VALUE is a constant value.
1304 Return 1 if VALUE is in the range specified by C.
1305 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1306 J: valid indexing constants.
1307 K: ~value ok in rhs argument of data operand.
1308 L: -value ok in rhs argument of data operand.
1309 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1310 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1311 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1312 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1313 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1314 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1315 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1316 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1319 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1320 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1321 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1322 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1323 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1324 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1325 && ((VAL) & 3) == 0) : \
1326 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1327 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1330 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1332 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1334 /* Constant letter 'G' for the FPA immediate constants.
1335 'H' means the same constant negated. */
1336 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1337 ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
1338 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1340 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1342 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1344 /* For the ARM, `Q' means that this is a memory operand that is just
1345 an offset from a register.
1346 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1347 address. This means that the symbol is in the text segment and can be
1348 accessed without using a load. */
1350 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1351 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1352 (C) == 'R' ? (GET_CODE (OP) == MEM \
1353 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1354 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1355 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1356 (C) == 'T' ? cirrus_memory_offset (OP) : \
1359 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1360 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1361 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1363 #define EXTRA_CONSTRAINT(X, C) \
1365 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1367 /* Given an rtx X being reloaded into a reg required to be
1368 in class CLASS, return the class of reg to actually use.
1369 In general this is just CLASS, but for the Thumb we prefer
1370 a LO_REGS class or a subset. */
1371 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1372 (TARGET_ARM ? (CLASS) : \
1373 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1375 /* Must leave BASE_REGS reloads alone */
1376 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1377 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1378 ? ((true_regnum (X) == -1 ? LO_REGS \
1379 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1383 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1384 ((CLASS) != LO_REGS \
1385 ? ((true_regnum (X) == -1 ? LO_REGS \
1386 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1390 /* Return the register class of a scratch register needed to copy IN into
1391 or out of a register in CLASS in MODE. If it can be done directly,
1392 NO_REGS is returned. */
1393 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1395 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1396 ? GENERAL_REGS : NO_REGS) \
1397 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1399 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1400 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1401 /* Cannot load constants into Cirrus registers. */ \
1403 && (CLASS) == CIRRUS_REGS \
1404 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1407 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1408 && CONSTANT_P (X)) \
1410 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1411 && (GET_CODE (X) == MEM \
1412 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1413 && true_regnum (X) == -1))) \
1414 ? GENERAL_REGS : NO_REGS) \
1415 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1417 /* Try a machine-dependent way of reloading an illegitimate address
1418 operand. If we find one, push the reload and jump to WIN. This
1419 macro is used in only one place: `find_reloads_address' in reload.c.
1421 For the ARM, we wish to handle large displacements off a base
1422 register by splitting the addend across a MOV and the mem insn.
1423 This can cut the number of reloads needed. */
1424 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1427 if (GET_CODE (X) == PLUS \
1428 && GET_CODE (XEXP (X, 0)) == REG \
1429 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1430 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1431 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1433 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1434 HOST_WIDE_INT low, high; \
1436 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1437 low = ((val & 0xf) ^ 0x8) - 0x8; \
1438 else if (TARGET_CIRRUS) \
1439 /* Need to be careful, -256 is not a valid offset. */ \
1440 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1441 else if (MODE == SImode \
1442 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1443 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1444 /* Need to be careful, -4096 is not a valid offset. */ \
1445 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1446 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1447 /* Need to be careful, -256 is not a valid offset. */ \
1448 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1449 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1450 && TARGET_HARD_FLOAT) \
1451 /* Need to be careful, -1024 is not a valid offset. */ \
1452 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1456 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1457 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1458 - (unsigned HOST_WIDE_INT) 0x80000000); \
1459 /* Check for overflow or zero */ \
1460 if (low == 0 || high == 0 || (high + low != val)) \
1463 /* Reload the high part into a base reg; leave the low part \
1465 X = gen_rtx_PLUS (GET_MODE (X), \
1466 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1469 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1470 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1471 VOIDmode, 0, 0, OPNUM, TYPE); \
1477 /* XXX If an HImode FP+large_offset address is converted to an HImode
1478 SP+large_offset address, then reload won't know how to fix it. It sees
1479 only that SP isn't valid for HImode, and so reloads the SP into an index
1480 register, but the resulting address is still invalid because the offset
1481 is too big. We fix it here instead by reloading the entire address. */
1482 /* We could probably achieve better results by defining PROMOTE_MODE to help
1483 cope with the variances between the Thumb's signed and unsigned byte and
1484 halfword load instructions. */
1485 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1487 if (GET_CODE (X) == PLUS \
1488 && GET_MODE_SIZE (MODE) < 4 \
1489 && GET_CODE (XEXP (X, 0)) == REG \
1490 && XEXP (X, 0) == stack_pointer_rtx \
1491 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1492 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1496 push_reload (orig_X, NULL_RTX, &X, NULL, \
1497 MODE_BASE_REG_CLASS (MODE), \
1498 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1503 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1505 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1507 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1509 /* Return the maximum number of consecutive registers
1510 needed to represent mode MODE in a register of class CLASS.
1511 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1512 #define CLASS_MAX_NREGS(CLASS, MODE) \
1513 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1515 /* If defined, gives a class of registers that cannot be used as the
1516 operand of a SUBREG that changes the mode of the object illegally. */
1518 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1519 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1521 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1522 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1523 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1524 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1525 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1526 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1527 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1530 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1532 /* Stack layout; function entry, exit and calling. */
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD 1
1538 /* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542 #define FRAME_GROWS_DOWNWARD 1
1544 /* Offset within stack frame to start allocating local variables at.
1545 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1546 first local allocated. Otherwise, it is the offset to the BEGINNING
1547 of the first local allocated. */
1548 #define STARTING_FRAME_OFFSET 0
1550 /* If we generate an insn to push BYTES bytes,
1551 this says how many the stack pointer really advances by. */
1552 /* The push insns do not do this rounding implicitly.
1553 So don't define this. */
1554 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1556 /* Define this if the maximum size of all the outgoing args is to be
1557 accumulated and pushed during the prologue. The amount can be
1558 found in the variable current_function_outgoing_args_size. */
1559 #define ACCUMULATE_OUTGOING_ARGS 1
1561 /* Offset of first parameter from the argument pointer register value. */
1562 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1564 /* Value is the number of byte of arguments automatically
1565 popped when returning from a subroutine call.
1566 FUNDECL is the declaration node of the function (as a tree),
1567 FUNTYPE is the data type of the function (as a tree),
1568 or for a library call it is an identifier node for the subroutine name.
1569 SIZE is the number of bytes of arguments passed on the stack.
1571 On the ARM, the caller does not pop any of its arguments that were passed
1573 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1575 /* Define how to find the value returned by a library function
1576 assuming the value has mode MODE. */
1577 #define LIBCALL_VALUE(MODE) \
1578 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1579 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1580 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1581 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1582 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1583 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1584 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1586 /* Define how to find the value returned by a function.
1587 VALTYPE is the data type of the value (as a tree).
1588 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1589 otherwise, FUNC is 0. */
1590 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1591 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1593 /* 1 if N is a possible register number for a function value.
1594 On the ARM, only r0 and f0 can return results. */
1595 /* On a Cirrus chip, mvf0 can return results. */
1596 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1597 ((REGNO) == ARG_REGISTER (1) \
1598 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1599 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1600 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1602 /* How large values are returned */
1603 /* A C expression which can inhibit the returning of certain function values
1604 in registers, based on the type of value. */
1605 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1607 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1608 values must be in memory. On the ARM, they need only do so if larger
1609 than a word, or if they contain elements offset from zero in the struct. */
1610 #define DEFAULT_PCC_STRUCT_RETURN 0
1612 /* Flags for the call/call_value rtl operations set up by function_arg. */
1613 #define CALL_NORMAL 0x00000000 /* No special processing. */
1614 #define CALL_LONG 0x00000001 /* Always call indirect. */
1615 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1617 /* These bits describe the different types of function supported
1618 by the ARM backend. They are exclusive. ie a function cannot be both a
1619 normal function and an interworked function, for example. Knowing the
1620 type of a function is important for determining its prologue and
1622 Note value 7 is currently unassigned. Also note that the interrupt
1623 function types all have bit 2 set, so that they can be tested for easily.
1624 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1625 machine_function structure is initialized (to zero) func_type will
1626 default to unknown. This will force the first use of arm_current_func_type
1627 to call arm_compute_func_type. */
1628 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1629 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1630 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1631 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1632 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1633 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1634 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1636 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1638 /* In addition functions can have several type modifiers,
1639 outlined by these bit masks: */
1640 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1641 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1642 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1643 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1645 /* Some macros to test these flags. */
1646 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1647 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1648 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1649 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1650 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1652 /* A C structure for machine-specific, per-function data.
1653 This is added to the cfun structure. */
1654 typedef struct machine_function GTY(())
1656 /* Additional stack adjustment in __builtin_eh_throw. */
1657 rtx eh_epilogue_sp_ofs;
1658 /* Records if LR has to be saved for far jumps. */
1660 /* Records if ARG_POINTER was ever live. */
1661 int arg_pointer_live;
1662 /* Records if the save of LR has been eliminated. */
1663 int lr_save_eliminated;
1664 /* The size of the stack frame. Only valid after reload. */
1666 /* Records the type of the current function. */
1667 unsigned long func_type;
1668 /* Record if the function has a variable argument list. */
1669 int uses_anonymous_args;
1670 /* Records if sibcalls are blocked because an argument
1671 register is needed to preserve stack alignment. */
1672 int sibcall_blocked;
1676 /* A C type for declaring a variable that is used as the first argument of
1677 `FUNCTION_ARG' and other related values. For some target machines, the
1678 type `int' suffices and can hold the number of bytes of argument so far. */
1681 /* This is the number of registers of arguments scanned so far. */
1683 /* This is the number of iWMMXt register arguments scanned so far. */
1687 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1691 /* Define where to put the arguments to a function.
1692 Value is zero to push the argument on the stack,
1693 or a hard register in which to store the argument.
1695 MODE is the argument's machine mode.
1696 TYPE is the data type of the argument (as a tree).
1697 This is null for libcalls where that information may
1699 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1700 the preceding args and about the function being called.
1701 NAMED is nonzero if this argument is a named parameter
1702 (otherwise it is an extra parameter matching an ellipsis).
1704 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1705 other arguments are passed on the stack. If (NAMED == 0) (which happens
1706 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1707 defined), say it is passed in the stack (function_prologue will
1708 indeed make it pass in the stack if necessary). */
1709 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1710 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1712 /* For an arg passed partly in registers and partly in memory,
1713 this is the number of registers used.
1714 For args passed entirely in registers or entirely in memory, zero. */
1715 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1716 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1717 NUM_ARG_REGS > (CUM).nregs \
1718 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1719 ? NUM_ARG_REGS - (CUM).nregs : 0)
1721 /* A C expression that indicates when an argument must be passed by
1722 reference. If nonzero for an argument, a copy of that argument is
1723 made in memory and a pointer to the argument is passed instead of
1724 the argument itself. The pointer is passed in whatever way is
1725 appropriate for passing a pointer to that type. */
1726 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1727 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1729 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1730 for a call to a function whose data type is FNTYPE.
1731 For a library call, FNTYPE is 0.
1732 On the ARM, the offset starts at 0. */
1733 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1734 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1736 /* Update the data in CUM to advance over an argument
1737 of mode MODE and data type TYPE.
1738 (TYPE is null for libcalls where that information may not be available.) */
1739 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1741 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1742 if ((CUM).named_count <= (CUM).nargs) \
1745 (CUM).iwmmxt_nregs += 1; \
1747 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1749 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1750 argument with the specified mode and type. If it is not defined,
1751 `PARM_BOUNDARY' is used for all arguments. */
1752 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1753 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1754 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1756 /* 1 if N is a possible register number for function argument passing.
1757 On the ARM, r0-r3 are used to pass args. */
1758 #define FUNCTION_ARG_REGNO_P(REGNO) \
1759 (IN_RANGE ((REGNO), 0, 3) \
1760 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1762 /* Implement `va_arg'. */
1763 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1764 arm_va_arg (valist, type)
1767 /* If your target environment doesn't prefix user functions with an
1768 underscore, you may wish to re-define this to prevent any conflicts.
1769 e.g. AOF may prefix mcount with an underscore. */
1770 #ifndef ARM_MCOUNT_NAME
1771 #define ARM_MCOUNT_NAME "*mcount"
1774 /* Call the function profiler with a given profile label. The Acorn
1775 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1776 On the ARM the full profile code will look like:
1785 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1786 will output the .text section.
1788 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1789 ``prof'' doesn't seem to mind about this!
1791 Note - this version of the code is designed to work in both ARM and
1793 #ifndef ARM_FUNCTION_PROFILER
1794 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1799 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1800 IP_REGNUM, LR_REGNUM); \
1801 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1802 fputc ('\n', STREAM); \
1803 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1804 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1805 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1809 #ifdef THUMB_FUNCTION_PROFILER
1810 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1812 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1814 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1816 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1817 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1820 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1821 the stack pointer does not matter. The value is tested only in
1822 functions that have frame pointers.
1823 No definition is equivalent to always zero.
1825 On the ARM, the function epilogue recovers the stack pointer from the
1827 #define EXIT_IGNORE_STACK 1
1829 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1831 /* Determine if the epilogue should be output as RTL.
1832 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1833 #define USE_RETURN_INSN(ISCOND) \
1834 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1836 /* Definitions for register eliminations.
1838 This is an array of structures. Each structure initializes one pair
1839 of eliminable registers. The "from" register number is given first,
1840 followed by "to". Eliminations of the same "from" register are listed
1841 in order of preference.
1843 We have two registers that can be eliminated on the ARM. First, the
1844 arg pointer register can often be eliminated in favor of the stack
1845 pointer register. Secondly, the pseudo frame pointer register can always
1846 be eliminated; it is replaced with either the stack or the real frame
1847 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1848 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1850 #define ELIMINABLE_REGS \
1851 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1852 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1853 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1854 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1855 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1856 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1857 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1859 /* Given FROM and TO register numbers, say whether this elimination is
1860 allowed. Frame pointer elimination is automatically handled.
1862 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1863 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1864 pointer, we must eliminate FRAME_POINTER_REGNUM into
1865 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1866 ARG_POINTER_REGNUM. */
1867 #define CAN_ELIMINATE(FROM, TO) \
1868 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1869 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1870 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1871 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1874 #define THUMB_REG_PUSHED_P(reg) \
1875 (regs_ever_live [reg] \
1876 && (! call_used_regs [reg] \
1877 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1878 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1880 /* Define the offset between two registers, one to be eliminated, and the
1881 other its replacement, at the start of a routine. */
1882 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1885 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1889 /* Note: This macro must match the code in thumb_function_prologue(). */
1890 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1893 if ((FROM) == ARG_POINTER_REGNUM) \
1895 int count_regs = 0; \
1897 for (regno = 8; regno < 13; regno ++) \
1898 if (THUMB_REG_PUSHED_P (regno)) \
1901 (OFFSET) += 4 * count_regs; \
1903 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1904 if (THUMB_REG_PUSHED_P (regno)) \
1906 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1907 (OFFSET) += 4 * (count_regs + 1); \
1908 if (TARGET_BACKTRACE) \
1910 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1916 if ((TO) == STACK_POINTER_REGNUM) \
1918 (OFFSET) += current_function_outgoing_args_size; \
1919 (OFFSET) += thumb_get_frame_size (); \
1923 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1925 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1927 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1929 /* Special case handling of the location of arguments passed on the stack. */
1930 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1932 /* Initialize data used by insn expanders. This is called from insn_emit,
1933 once for every function before code is generated. */
1934 #define INIT_EXPANDERS arm_init_expanders ()
1936 /* Output assembler code for a block containing the constant parts
1937 of a trampoline, leaving space for the variable parts.
1939 On the ARM, (if r8 is the static chain regnum, and remembering that
1940 referencing pc adds an offset of 8) the trampoline looks like:
1943 .word static chain value
1944 .word function's address
1945 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1946 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1948 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1949 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1950 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1951 PC_REGNUM, PC_REGNUM); \
1952 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1953 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1956 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1957 Why - because it is easier. This code will always be branched to via
1958 a BX instruction and since the compiler magically generates the address
1959 of the function the linker has no opportunity to ensure that the
1960 bottom bit is set. Thus the processor will be in ARM mode when it
1961 reaches this code. So we duplicate the ARM trampoline code and add
1962 a switch into Thumb mode as well. */
1963 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1965 fprintf (FILE, "\t.code 32\n"); \
1966 fprintf (FILE, ".Ltrampoline_start:\n"); \
1967 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1968 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1969 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1970 IP_REGNUM, PC_REGNUM); \
1971 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1972 IP_REGNUM, IP_REGNUM); \
1973 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1974 fprintf (FILE, "\t.word\t0\n"); \
1975 fprintf (FILE, "\t.word\t0\n"); \
1976 fprintf (FILE, "\t.code 16\n"); \
1979 #define TRAMPOLINE_TEMPLATE(FILE) \
1981 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1983 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1985 /* Length in units of the trampoline for entering a nested function. */
1986 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1988 /* Alignment required for a trampoline in bits. */
1989 #define TRAMPOLINE_ALIGNMENT 32
1991 /* Emit RTL insns to initialize the variable parts of a trampoline.
1992 FNADDR is an RTX for the address of the function's pure code.
1993 CXT is an RTX for the static chain value for the function. */
1994 #ifndef INITIALIZE_TRAMPOLINE
1995 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1997 emit_move_insn (gen_rtx_MEM (SImode, \
1998 plus_constant (TRAMP, \
1999 TARGET_ARM ? 8 : 16)), \
2001 emit_move_insn (gen_rtx_MEM (SImode, \
2002 plus_constant (TRAMP, \
2003 TARGET_ARM ? 12 : 20)), \
2009 /* Addressing modes, and classification of registers for them. */
2010 #define HAVE_POST_INCREMENT 1
2011 #define HAVE_PRE_INCREMENT TARGET_ARM
2012 #define HAVE_POST_DECREMENT TARGET_ARM
2013 #define HAVE_PRE_DECREMENT TARGET_ARM
2014 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2015 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2016 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2017 #define HAVE_POST_MODIFY_REG TARGET_ARM
2019 /* Macros to check register numbers against specific register classes. */
2021 /* These assume that REGNO is a hard or pseudo reg number.
2022 They give nonzero only if REGNO is a hard reg of the suitable class
2023 or a pseudo reg currently allocated to a suitable hard reg.
2024 Since they use reg_renumber, they are safe only once reg_renumber
2025 has been allocated, which happens in local-alloc.c. */
2026 #define TEST_REGNO(R, TEST, VALUE) \
2027 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2029 /* On the ARM, don't allow the pc to be used. */
2030 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2031 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2032 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2033 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2035 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2036 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2037 || (GET_MODE_SIZE (MODE) >= 4 \
2038 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2040 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2042 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2043 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2045 /* For ARM code, we don't care about the mode, but for Thumb, the index
2046 must be suitable for use in a QImode load. */
2047 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2048 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2050 /* Maximum number of registers that can appear in a valid memory address.
2051 Shifts in addresses can't be by a register. */
2052 #define MAX_REGS_PER_ADDRESS 2
2054 /* Recognize any constant value that is a valid address. */
2055 /* XXX We can address any constant, eventually... */
2057 #ifdef AOF_ASSEMBLER
2059 #define CONSTANT_ADDRESS_P(X) \
2060 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2064 #define CONSTANT_ADDRESS_P(X) \
2065 (GET_CODE (X) == SYMBOL_REF \
2066 && (CONSTANT_POOL_ADDRESS_P (X) \
2067 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2069 #endif /* AOF_ASSEMBLER */
2071 /* Nonzero if the constant value X is a legitimate general operand.
2072 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2074 On the ARM, allow any integer (invalid ones are removed later by insn
2075 patterns), nice doubles and symbol_refs which refer to the function's
2078 When generating pic allow anything. */
2079 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2081 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2082 ( GET_CODE (X) == CONST_INT \
2083 || GET_CODE (X) == CONST_DOUBLE \
2084 || CONSTANT_ADDRESS_P (X) \
2087 #define LEGITIMATE_CONSTANT_P(X) \
2088 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2090 /* Special characters prefixed to function names
2091 in order to encode attribute like information.
2092 Note, '@' and '*' have already been taken. */
2093 #define SHORT_CALL_FLAG_CHAR '^'
2094 #define LONG_CALL_FLAG_CHAR '#'
2096 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2097 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2099 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2100 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2102 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2103 #define SUBTARGET_NAME_ENCODING_LENGTHS
2106 /* This is a C fragment for the inside of a switch statement.
2107 Each case label should return the number of characters to
2108 be stripped from the start of a function's name, if that
2109 name starts with the indicated character. */
2110 #define ARM_NAME_ENCODING_LENGTHS \
2111 case SHORT_CALL_FLAG_CHAR: return 1; \
2112 case LONG_CALL_FLAG_CHAR: return 1; \
2113 case '*': return 1; \
2114 SUBTARGET_NAME_ENCODING_LENGTHS
2116 /* This is how to output a reference to a user-level label named NAME.
2117 `assemble_name' uses this. */
2118 #undef ASM_OUTPUT_LABELREF
2119 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2120 arm_asm_output_labelref (FILE, NAME)
2122 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2123 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2125 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2126 and check its validity for a certain class.
2127 We have two alternate definitions for each of them.
2128 The usual definition accepts all pseudo regs; the other rejects
2129 them unless they have been allocated suitable hard regs.
2130 The symbol REG_OK_STRICT causes the latter definition to be used. */
2131 #ifndef REG_OK_STRICT
2133 #define ARM_REG_OK_FOR_BASE_P(X) \
2134 (REGNO (X) <= LAST_ARM_REGNUM \
2135 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2136 || REGNO (X) == FRAME_POINTER_REGNUM \
2137 || REGNO (X) == ARG_POINTER_REGNUM)
2139 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2140 (REGNO (X) <= LAST_LO_REGNUM \
2141 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2142 || (GET_MODE_SIZE (MODE) >= 4 \
2143 && (REGNO (X) == STACK_POINTER_REGNUM \
2144 || (X) == hard_frame_pointer_rtx \
2145 || (X) == arg_pointer_rtx)))
2147 #define REG_STRICT_P 0
2149 #else /* REG_OK_STRICT */
2151 #define ARM_REG_OK_FOR_BASE_P(X) \
2152 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2154 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2155 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2157 #define REG_STRICT_P 1
2159 #endif /* REG_OK_STRICT */
2161 /* Now define some helpers in terms of the above. */
2163 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2165 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2166 : ARM_REG_OK_FOR_BASE_P (X))
2168 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2170 /* For Thumb, a valid index register is anything that can be used in
2171 a byte load instruction. */
2172 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2174 /* Nonzero if X is a hard reg that can be used as an index
2175 or if it is a pseudo reg. On the Thumb, the stack pointer
2177 #define REG_OK_FOR_INDEX_P(X) \
2179 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2180 : ARM_REG_OK_FOR_INDEX_P (X))
2183 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2184 that is a valid memory address for an instruction.
2185 The MODE argument is the machine mode for the MEM expression
2186 that wants to use this address. */
2188 #define ARM_BASE_REGISTER_RTX_P(X) \
2189 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2191 #define ARM_INDEX_REGISTER_RTX_P(X) \
2192 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2194 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2196 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2200 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2202 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2206 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2208 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2209 else /* if (TARGET_THUMB) */ \
2210 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2213 /* Try machine-dependent ways of modifying an illegitimate address
2214 to be legitimate. If we find one, return the new, valid address. */
2215 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2217 X = arm_legitimize_address (X, OLDX, MODE); \
2219 if (memory_address_p (MODE, X)) \
2223 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2226 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2229 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2232 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2234 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2237 /* Go to LABEL if ADDR (a legitimate address expression)
2238 has an effect that depends on the machine mode it is used for. */
2239 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2241 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2242 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2246 /* Nothing helpful to do for the Thumb */
2247 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2249 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2252 /* Specify the machine mode that this machine uses
2253 for the index in the tablejump instruction. */
2254 #define CASE_VECTOR_MODE Pmode
2256 /* Define as C expression which evaluates to nonzero if the tablejump
2257 instruction expects the table to contain offsets from the address of the
2259 Do not define this if the table should contain absolute addresses. */
2260 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2262 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2263 unsigned is probably best, but may break some code. */
2264 #ifndef DEFAULT_SIGNED_CHAR
2265 #define DEFAULT_SIGNED_CHAR 0
2268 /* Don't cse the address of the function being compiled. */
2269 #define NO_RECURSIVE_FUNCTION_CSE 1
2271 /* Max number of bytes we can move from memory to memory
2272 in one reasonably fast instruction. */
2276 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2278 /* Define if operations between registers always perform the operation
2279 on the full register even if a narrower mode is specified. */
2280 #define WORD_REGISTER_OPERATIONS
2282 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2283 will either zero-extend or sign-extend. The value of this macro should
2284 be the code that says which one of the two operations is implicitly
2285 done, NIL if none. */
2286 #define LOAD_EXTEND_OP(MODE) \
2287 (TARGET_THUMB ? ZERO_EXTEND : \
2288 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2289 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2291 /* Nonzero if access to memory by bytes is slow and undesirable. */
2292 #define SLOW_BYTE_ACCESS 0
2294 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2296 /* Immediate shift counts are truncated by the output routines (or was it
2297 the assembler?). Shift counts in a register are truncated by ARM. Note
2298 that the native compiler puts too large (> 32) immediate shift counts
2299 into a register and shifts by the register, letting the ARM decide what
2300 to do instead of doing that itself. */
2301 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2302 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2303 On the arm, Y in a register is used modulo 256 for the shift. Only for
2304 rotates is modulo 32 used. */
2305 /* #define SHIFT_COUNT_TRUNCATED 1 */
2307 /* All integers have the same format so truncation is easy. */
2308 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2310 /* Calling from registers is a massive pain. */
2311 #define NO_FUNCTION_CSE 1
2313 /* The machine modes of pointers and functions */
2314 #define Pmode SImode
2315 #define FUNCTION_MODE Pmode
2317 #define ARM_FRAME_RTX(X) \
2318 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2319 || (X) == arg_pointer_rtx)
2321 /* Moves to and from memory are quite expensive */
2322 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2323 (TARGET_ARM ? 10 : \
2324 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2325 * (CLASS == LO_REGS ? 1 : 2)))
2327 /* Try to generate sequences that don't involve branches, we can then use
2328 conditional instructions */
2329 #define BRANCH_COST \
2330 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2332 /* Position Independent Code. */
2333 /* We decide which register to use based on the compilation options and
2334 the assembler in use; this is more general than the APCS restriction of
2335 using sb (r9) all the time. */
2336 extern int arm_pic_register;
2338 /* Used when parsing command line option -mpic-register=. */
2339 extern const char * arm_pic_register_string;
2341 /* The register number of the register used to address a table of static
2342 data addresses in memory. */
2343 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2345 #define FINALIZE_PIC arm_finalize_pic (1)
2347 /* We can't directly access anything that contains a symbol,
2348 nor can we indirect via the constant pool. */
2349 #define LEGITIMATE_PIC_OPERAND_P(X) \
2350 (!(symbol_mentioned_p (X) \
2351 || label_mentioned_p (X) \
2352 || (GET_CODE (X) == SYMBOL_REF \
2353 && CONSTANT_POOL_ADDRESS_P (X) \
2354 && (symbol_mentioned_p (get_pool_constant (X)) \
2355 || label_mentioned_p (get_pool_constant (X))))))
2357 /* We need to know when we are making a constant pool; this determines
2358 whether data needs to be in the GOT or can be referenced via a GOT
2360 extern int making_const_table;
2362 /* Handle pragmas for compatibility with Intel's compilers. */
2363 #define REGISTER_TARGET_PRAGMAS() do { \
2364 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2365 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2366 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2369 /* Condition code information. */
2370 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2371 return the mode to be used for the comparison. */
2373 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2375 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2377 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2380 if (GET_CODE (OP1) == CONST_INT \
2381 && ! (const_ok_for_arm (INTVAL (OP1)) \
2382 || (const_ok_for_arm (- INTVAL (OP1))))) \
2384 rtx const_op = OP1; \
2385 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2391 /* The arm5 clz instruction returns 32. */
2392 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2395 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2397 /* Output a push or a pop instruction (only used when profiling). */
2398 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2402 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2403 STACK_POINTER_REGNUM, REGNO); \
2405 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2409 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2413 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2414 STACK_POINTER_REGNUM, REGNO); \
2416 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2419 /* This is how to output a label which precedes a jumptable. Since
2420 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2421 #undef ASM_OUTPUT_CASE_LABEL
2422 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2426 ASM_OUTPUT_ALIGN (FILE, 2); \
2427 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2431 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2436 if (is_called_in_ARM_mode (DECL)) \
2437 fprintf (STREAM, "\t.code 32\n") ; \
2439 fprintf (STREAM, "\t.thumb_func\n") ; \
2441 if (TARGET_POKE_FUNCTION_NAME) \
2442 arm_poke_function_name (STREAM, (char *) NAME); \
2446 /* For aliases of functions we use .thumb_set instead. */
2447 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2450 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2451 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2453 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2455 fprintf (FILE, "\t.thumb_set "); \
2456 assemble_name (FILE, LABEL1); \
2457 fprintf (FILE, ","); \
2458 assemble_name (FILE, LABEL2); \
2459 fprintf (FILE, "\n"); \
2462 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2466 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2467 /* To support -falign-* switches we need to use .p2align so
2468 that alignment directives in code sections will be padded
2469 with no-op instructions, rather than zeroes. */
2470 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2473 if ((MAX_SKIP) == 0) \
2474 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2476 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2477 (int) (LOG), (int) (MAX_SKIP)); \
2481 /* Only perform branch elimination (by making instructions conditional) if
2482 we're optimizing. Otherwise it's of no use anyway. */
2483 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2484 if (TARGET_ARM && optimize) \
2485 arm_final_prescan_insn (INSN); \
2486 else if (TARGET_THUMB) \
2487 thumb_final_prescan_insn (INSN)
2489 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2490 (CODE == '@' || CODE == '|' \
2491 || (TARGET_ARM && (CODE == '?')) \
2492 || (TARGET_THUMB && (CODE == '_')))
2494 /* Output an operand of an instruction. */
2495 #define PRINT_OPERAND(STREAM, X, CODE) \
2496 arm_print_operand (STREAM, X, CODE)
2498 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2499 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2500 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2501 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2502 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2503 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2506 /* Output the address of an operand. */
2507 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2509 int is_minus = GET_CODE (X) == MINUS; \
2511 if (GET_CODE (X) == REG) \
2512 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2513 else if (GET_CODE (X) == PLUS || is_minus) \
2515 rtx base = XEXP (X, 0); \
2516 rtx index = XEXP (X, 1); \
2517 HOST_WIDE_INT offset = 0; \
2518 if (GET_CODE (base) != REG) \
2520 /* Ensure that BASE is a register. */ \
2521 /* (one of them must be). */ \
2526 switch (GET_CODE (index)) \
2529 offset = INTVAL (index); \
2532 asm_fprintf (STREAM, "[%r, #%wd]", \
2533 REGNO (base), offset); \
2537 asm_fprintf (STREAM, "[%r, %s%r]", \
2538 REGNO (base), is_minus ? "-" : "", \
2548 asm_fprintf (STREAM, "[%r, %s%r", \
2549 REGNO (base), is_minus ? "-" : "", \
2550 REGNO (XEXP (index, 0))); \
2551 arm_print_operand (STREAM, index, 'S'); \
2552 fputs ("]", STREAM); \
2560 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2561 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2563 extern enum machine_mode output_memory_reference_mode; \
2565 if (GET_CODE (XEXP (X, 0)) != REG) \
2568 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2569 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2570 REGNO (XEXP (X, 0)), \
2571 GET_CODE (X) == PRE_DEC ? "-" : "", \
2572 GET_MODE_SIZE (output_memory_reference_mode)); \
2574 asm_fprintf (STREAM, "[%r], #%s%d", \
2575 REGNO (XEXP (X, 0)), \
2576 GET_CODE (X) == POST_DEC ? "-" : "", \
2577 GET_MODE_SIZE (output_memory_reference_mode)); \
2579 else if (GET_CODE (X) == PRE_MODIFY) \
2581 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2582 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2583 asm_fprintf (STREAM, "#%wd]!", \
2584 INTVAL (XEXP (XEXP (X, 1), 1))); \
2586 asm_fprintf (STREAM, "%r]!", \
2587 REGNO (XEXP (XEXP (X, 1), 1))); \
2589 else if (GET_CODE (X) == POST_MODIFY) \
2591 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2592 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2593 asm_fprintf (STREAM, "#%wd", \
2594 INTVAL (XEXP (XEXP (X, 1), 1))); \
2596 asm_fprintf (STREAM, "%r", \
2597 REGNO (XEXP (XEXP (X, 1), 1))); \
2599 else output_addr_const (STREAM, X); \
2602 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2604 if (GET_CODE (X) == REG) \
2605 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2606 else if (GET_CODE (X) == POST_INC) \
2607 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2608 else if (GET_CODE (X) == PLUS) \
2610 if (GET_CODE (XEXP (X, 0)) != REG) \
2612 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2613 asm_fprintf (STREAM, "[%r, #%wd]", \
2614 REGNO (XEXP (X, 0)), \
2615 INTVAL (XEXP (X, 1))); \
2617 asm_fprintf (STREAM, "[%r, %r]", \
2618 REGNO (XEXP (X, 0)), \
2619 REGNO (XEXP (X, 1))); \
2622 output_addr_const (STREAM, X); \
2625 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2627 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2629 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2631 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2632 if (GET_CODE (X) != CONST_VECTOR \
2633 || ! arm_emit_vector_const (FILE, X)) \
2636 /* A C expression whose value is RTL representing the value of the return
2637 address for the frame COUNT steps up from the current frame. */
2639 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2640 arm_return_addr (COUNT, FRAME)
2642 /* Mask of the bits in the PC that contain the real return address
2643 when running in 26-bit mode. */
2644 #define RETURN_ADDR_MASK26 (0x03fffffc)
2646 /* Pick up the return address upon entry to a procedure. Used for
2647 dwarf2 unwind information. This also enables the table driven
2649 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2650 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2652 /* Used to mask out junk bits from the return address, such as
2653 processor state, interrupt status, condition codes and the like. */
2654 #define MASK_RETURN_ADDR \
2655 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2656 in 26 bit mode, the condition codes must be masked out of the \
2657 return address. This does not apply to ARM6 and later processors \
2658 when running in 32 bit mode. */ \
2659 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2660 : (arm_arch4 || TARGET_THUMB) ? \
2661 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2662 : arm_gen_return_addr_mask ())
2665 /* Define the codes that are matched by predicates in arm.c */
2666 #define PREDICATE_CODES \
2667 {"s_register_operand", {SUBREG, REG}}, \
2668 {"arm_hard_register_operand", {REG}}, \
2669 {"f_register_operand", {SUBREG, REG}}, \
2670 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2671 {"arm_addimm_operand", {CONST_INT}}, \
2672 {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2673 {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2674 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2675 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2676 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2677 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2678 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2679 {"thumb_cmpneg_operand", {CONST_INT}}, \
2680 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2681 {"offsettable_memory_operand", {MEM}}, \
2682 {"bad_signed_byte_operand", {MEM}}, \
2683 {"alignable_memory_operand", {MEM}}, \
2684 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2685 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2686 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2687 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2688 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2689 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2690 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2691 {"load_multiple_operation", {PARALLEL}}, \
2692 {"store_multiple_operation", {PARALLEL}}, \
2693 {"equality_operator", {EQ, NE}}, \
2694 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2695 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2697 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2698 {"const_shift_operand", {CONST_INT}}, \
2699 {"multi_register_push", {PARALLEL}}, \
2700 {"cc_register", {REG}}, \
2701 {"logical_binary_operator", {AND, IOR, XOR}}, \
2702 {"cirrus_register_operand", {REG}}, \
2703 {"cirrus_fp_register", {REG}}, \
2704 {"cirrus_shift_const", {CONST_INT}}, \
2705 {"dominant_cc_register", {REG}},
2707 /* Define this if you have special predicates that know special things
2708 about modes. Genrecog will warn about certain forms of
2709 match_operand without a mode; if the operand predicate is listed in
2710 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2711 #define SPECIAL_MODE_PREDICATES \
2712 "cc_register", "dominant_cc_register",
2721 ARM_BUILTIN_WAVG2BR,
2722 ARM_BUILTIN_WAVG2HR,
2749 ARM_BUILTIN_TMOVMSKB,
2750 ARM_BUILTIN_TMOVMSKH,
2751 ARM_BUILTIN_TMOVMSKW,
2760 ARM_BUILTIN_WPACKHSS,
2761 ARM_BUILTIN_WPACKWSS,
2762 ARM_BUILTIN_WPACKDSS,
2763 ARM_BUILTIN_WPACKHUS,
2764 ARM_BUILTIN_WPACKWUS,
2765 ARM_BUILTIN_WPACKDUS,
2770 ARM_BUILTIN_WADDSSB,
2771 ARM_BUILTIN_WADDSSH,
2772 ARM_BUILTIN_WADDSSW,
2773 ARM_BUILTIN_WADDUSB,
2774 ARM_BUILTIN_WADDUSH,
2775 ARM_BUILTIN_WADDUSW,
2779 ARM_BUILTIN_WSUBSSB,
2780 ARM_BUILTIN_WSUBSSH,
2781 ARM_BUILTIN_WSUBSSW,
2782 ARM_BUILTIN_WSUBUSB,
2783 ARM_BUILTIN_WSUBUSH,
2784 ARM_BUILTIN_WSUBUSW,
2791 ARM_BUILTIN_WCMPEQB,
2792 ARM_BUILTIN_WCMPEQH,
2793 ARM_BUILTIN_WCMPEQW,
2794 ARM_BUILTIN_WCMPGTUB,
2795 ARM_BUILTIN_WCMPGTUH,
2796 ARM_BUILTIN_WCMPGTUW,
2797 ARM_BUILTIN_WCMPGTSB,
2798 ARM_BUILTIN_WCMPGTSH,
2799 ARM_BUILTIN_WCMPGTSW,
2801 ARM_BUILTIN_TEXTRMSB,
2802 ARM_BUILTIN_TEXTRMSH,
2803 ARM_BUILTIN_TEXTRMSW,
2804 ARM_BUILTIN_TEXTRMUB,
2805 ARM_BUILTIN_TEXTRMUH,
2806 ARM_BUILTIN_TEXTRMUW,
2856 ARM_BUILTIN_WUNPCKIHB,
2857 ARM_BUILTIN_WUNPCKIHH,
2858 ARM_BUILTIN_WUNPCKIHW,
2859 ARM_BUILTIN_WUNPCKILB,
2860 ARM_BUILTIN_WUNPCKILH,
2861 ARM_BUILTIN_WUNPCKILW,
2863 ARM_BUILTIN_WUNPCKEHSB,
2864 ARM_BUILTIN_WUNPCKEHSH,
2865 ARM_BUILTIN_WUNPCKEHSW,
2866 ARM_BUILTIN_WUNPCKEHUB,
2867 ARM_BUILTIN_WUNPCKEHUH,
2868 ARM_BUILTIN_WUNPCKEHUW,
2869 ARM_BUILTIN_WUNPCKELSB,
2870 ARM_BUILTIN_WUNPCKELSH,
2871 ARM_BUILTIN_WUNPCKELSW,
2872 ARM_BUILTIN_WUNPCKELUB,
2873 ARM_BUILTIN_WUNPCKELUH,
2874 ARM_BUILTIN_WUNPCKELUW,
2878 #endif /* ! GCC_ARM_H */
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