1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define ("__arm__"); \
36 builtin_define ("__thumb__"); \
40 builtin_define ("__ARMEB__"); \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
48 builtin_define ("__ARMEL__"); \
50 builtin_define ("__THUMBEL__"); \
54 builtin_define ("__APCS_32__"); \
56 builtin_define ("__APCS_26__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 /* Configure didn't specify. */
101 #define TARGET_CPU_generic 0x8000
103 typedef enum arm_cond_code
105 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
106 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 extern arm_cc arm_current_cc;
112 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
114 extern int arm_target_label;
115 extern int arm_ccfsm_state;
116 extern GTY(()) rtx arm_target_insn;
117 /* Run-time compilation parameters selecting different hardware subsets. */
118 extern int target_flags;
119 /* The floating point instruction architecture, can be 2 or 3 */
120 extern const char * target_fp_name;
121 /* Define the information needed to generate branch insns. This is
122 stored from the compare operation. */
123 extern GTY(()) rtx arm_compare_op0;
124 extern GTY(()) rtx arm_compare_op1;
125 /* The label of the current constant pool. */
126 extern rtx pool_vector_label;
127 /* Set to 1 when a return insn is output, this means that the epilogue
129 extern int return_used_this_function;
130 /* Used to produce AOF syntax assembler. */
131 extern GTY(()) rtx aof_pic_label;
133 /* Just in case configure has failed to define anything. */
134 #ifndef TARGET_CPU_DEFAULT
135 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
138 /* If the configuration file doesn't specify the cpu, the subtarget may
139 override it. If it doesn't, then default to an ARM6. */
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
141 #undef TARGET_CPU_DEFAULT
143 #ifdef SUBTARGET_CPU_DEFAULT
144 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
146 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
151 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
153 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
154 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
157 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
159 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
160 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
163 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
165 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
166 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
168 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
169 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
170 /* Set TARGET_DEFAULT to the default, but without soft-float. */
171 #ifdef TARGET_DEFAULT
172 #undef TARGET_DEFAULT
173 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
174 #endif /* TARGET_CPU_DEFAULT */
176 Unrecognized value in TARGET_CPU_DEFAULT.
186 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
187 %{mapcs-32:%{mapcs-26: \
188 %e-mapcs-26 and -mapcs-32 may not be used together}} \
189 %{msoft-float:%{mhard-float: \
190 %e-msoft-float and -mhard_float may not be used together}} \
191 %{mbig-endian:%{mlittle-endian: \
192 %e-mbig-endian and -mlittle-endian may not be used together}}"
194 /* Set the architecture define -- if -march= is set, then it overrides
195 the -mcpu= setting. */
196 #define CPP_CPU_ARCH_SPEC "\
197 %{march=arm2:-D__ARM_ARCH_2__} \
198 %{march=arm250:-D__ARM_ARCH_2__} \
199 %{march=arm3:-D__ARM_ARCH_2__} \
200 %{march=arm6:-D__ARM_ARCH_3__} \
201 %{march=arm600:-D__ARM_ARCH_3__} \
202 %{march=arm610:-D__ARM_ARCH_3__} \
203 %{march=arm7:-D__ARM_ARCH_3__} \
204 %{march=arm700:-D__ARM_ARCH_3__} \
205 %{march=arm710:-D__ARM_ARCH_3__} \
206 %{march=arm720:-D__ARM_ARCH_3__} \
207 %{march=arm7100:-D__ARM_ARCH_3__} \
208 %{march=arm7500:-D__ARM_ARCH_3__} \
209 %{march=arm7500fe:-D__ARM_ARCH_3__} \
210 %{march=arm7m:-D__ARM_ARCH_3M__} \
211 %{march=arm7dm:-D__ARM_ARCH_3M__} \
212 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
213 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
214 %{march=arm8:-D__ARM_ARCH_4__} \
215 %{march=arm810:-D__ARM_ARCH_4__} \
216 %{march=arm9:-D__ARM_ARCH_4T__} \
217 %{march=arm920:-D__ARM_ARCH_4__} \
218 %{march=arm920t:-D__ARM_ARCH_4T__} \
219 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
220 %{march=strongarm:-D__ARM_ARCH_4__} \
221 %{march=strongarm110:-D__ARM_ARCH_4__} \
222 %{march=strongarm1100:-D__ARM_ARCH_4__} \
223 %{march=xscale:-D__ARM_ARCH_5TE__} \
224 %{march=xscale:-D__XSCALE__} \
225 %{march=ep9312:-D__ARM_ARCH_4T__} \
226 %{march=ep9312:-D__MAVERICK__} \
227 %{march=armv2:-D__ARM_ARCH_2__} \
228 %{march=armv2a:-D__ARM_ARCH_2__} \
229 %{march=armv3:-D__ARM_ARCH_3__} \
230 %{march=armv3m:-D__ARM_ARCH_3M__} \
231 %{march=armv4:-D__ARM_ARCH_4__} \
232 %{march=armv4t:-D__ARM_ARCH_4T__} \
233 %{march=armv5:-D__ARM_ARCH_5__} \
234 %{march=armv5t:-D__ARM_ARCH_5T__} \
235 %{march=armv5e:-D__ARM_ARCH_5E__} \
236 %{march=armv5te:-D__ARM_ARCH_5TE__} \
238 %{mcpu=arm2:-D__ARM_ARCH_2__} \
239 %{mcpu=arm250:-D__ARM_ARCH_2__} \
240 %{mcpu=arm3:-D__ARM_ARCH_2__} \
241 %{mcpu=arm6:-D__ARM_ARCH_3__} \
242 %{mcpu=arm600:-D__ARM_ARCH_3__} \
243 %{mcpu=arm610:-D__ARM_ARCH_3__} \
244 %{mcpu=arm7:-D__ARM_ARCH_3__} \
245 %{mcpu=arm700:-D__ARM_ARCH_3__} \
246 %{mcpu=arm710:-D__ARM_ARCH_3__} \
247 %{mcpu=arm720:-D__ARM_ARCH_3__} \
248 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
249 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
250 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
251 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
252 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
253 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
254 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
255 %{mcpu=arm8:-D__ARM_ARCH_4__} \
256 %{mcpu=arm810:-D__ARM_ARCH_4__} \
257 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
258 %{mcpu=arm920:-D__ARM_ARCH_4__} \
259 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
260 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
261 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
262 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
263 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
264 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
265 %{mcpu=xscale:-D__XSCALE__} \
266 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
267 %{mcpu=ep9312:-D__MAVERICK__} \
268 %{!mcpu*:%(cpp_cpu_arch_default)}} \
275 /* This macro defines names of additional specifications to put in the specs
276 that can be used in various specifications like CC1_SPEC. Its definition
277 is an initializer with a subgrouping for each command option.
279 Each subgrouping contains a string constant, that defines the
280 specification name, and a string constant that used by the GCC driver
283 Do not define this macro if it does not need to do anything. */
284 #define EXTRA_SPECS \
285 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
286 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
287 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
288 SUBTARGET_EXTRA_SPECS
290 #ifndef SUBTARGET_EXTRA_SPECS
291 #define SUBTARGET_EXTRA_SPECS
294 #ifndef SUBTARGET_CPP_SPEC
295 #define SUBTARGET_CPP_SPEC ""
298 /* Run-time Target Specification. */
299 #ifndef TARGET_VERSION
300 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
303 /* Nonzero if the function prologue (and epilogue) should obey
304 the ARM Procedure Call Standard. */
305 #define ARM_FLAG_APCS_FRAME (1 << 0)
307 /* Nonzero if the function prologue should output the function name to enable
308 the post mortem debugger to print a backtrace (very useful on RISCOS,
309 unused on RISCiX). Specifying this flag also enables
310 -fno-omit-frame-pointer.
311 XXX Must still be implemented in the prologue. */
312 #define ARM_FLAG_POKE (1 << 1)
314 /* Nonzero if floating point instructions are emulated by the FPE, in which
315 case instruction scheduling becomes very uninteresting. */
316 #define ARM_FLAG_FPE (1 << 2)
318 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
319 that assume restoration of the condition flags when returning from a
320 branch and link (ie a function). */
321 #define ARM_FLAG_APCS_32 (1 << 3)
323 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
325 /* Nonzero if stack checking should be performed on entry to each function
326 which allocates temporary variables on the stack. */
327 #define ARM_FLAG_APCS_STACK (1 << 4)
329 /* Nonzero if floating point parameters should be passed to functions in
330 floating point registers. */
331 #define ARM_FLAG_APCS_FLOAT (1 << 5)
333 /* Nonzero if re-entrant, position independent code should be generated.
334 This is equivalent to -fpic. */
335 #define ARM_FLAG_APCS_REENT (1 << 6)
337 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
338 be loaded using either LDRH or LDRB instructions. */
339 #define ARM_FLAG_MMU_TRAPS (1 << 7)
341 /* Nonzero if all floating point instructions are missing (and there is no
342 emulator either). Generate function calls for all ops in this case. */
343 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
345 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
346 #define ARM_FLAG_BIG_END (1 << 9)
348 /* Nonzero if we should compile for Thumb interworking. */
349 #define ARM_FLAG_INTERWORK (1 << 10)
351 /* Nonzero if we should have little-endian words even when compiling for
352 big-endian (for backwards compatibility with older versions of GCC). */
353 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
355 /* Nonzero if we need to protect the prolog from scheduling */
356 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
358 /* Nonzero if a call to abort should be generated if a noreturn
359 function tries to return. */
360 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
362 /* Nonzero if function prologues should not load the PIC register. */
363 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
365 /* Nonzero if all call instructions should be indirect. */
366 #define ARM_FLAG_LONG_CALLS (1 << 15)
368 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
369 #define ARM_FLAG_THUMB (1 << 16)
371 /* Set if a TPCS style stack frame should be generated, for non-leaf
372 functions, even if they do not need one. */
373 #define THUMB_FLAG_BACKTRACE (1 << 17)
375 /* Set if a TPCS style stack frame should be generated, for leaf
376 functions, even if they do not need one. */
377 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
379 /* Set if externally visible functions should assume that they
380 might be called in ARM mode, from a non-thumb aware code. */
381 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
383 /* Set if calls via function pointers should assume that their
384 destination is non-Thumb aware. */
385 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
387 /* Nonzero means target uses VFP FP. */
388 #define ARM_FLAG_VFP (1 << 21)
390 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
391 #define ARM_FLAG_ATPCS (1 << 22)
393 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
394 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
396 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
397 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
398 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
399 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
400 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
401 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
402 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
403 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
404 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
405 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
406 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
407 #define TARGET_CIRRUS (arm_is_cirrus)
408 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
409 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
410 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
411 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
412 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
413 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
414 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
415 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
416 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
417 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
418 #define TARGET_ARM (! TARGET_THUMB)
419 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
420 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
421 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
422 #define TARGET_BACKTRACE (leaf_function_p () \
423 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
424 : (target_flags & THUMB_FLAG_BACKTRACE))
425 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
427 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
428 #ifndef SUBTARGET_SWITCHES
429 #define SUBTARGET_SWITCHES
432 #define TARGET_SWITCHES \
434 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
435 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
436 N_("Generate APCS conformant stack frames") }, \
437 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
438 {"poke-function-name", ARM_FLAG_POKE, \
439 N_("Store function names in object code") }, \
440 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
441 {"fpe", ARM_FLAG_FPE, "" }, \
442 {"apcs-32", ARM_FLAG_APCS_32, \
443 N_("Use the 32-bit version of the APCS") }, \
444 {"apcs-26", -ARM_FLAG_APCS_32, \
445 N_("Use the 26-bit version of the APCS") }, \
446 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
447 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
448 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
449 N_("Pass FP arguments in FP registers") }, \
450 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
451 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
452 N_("Generate re-entrant, PIC code") }, \
453 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
454 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
455 N_("The MMU will trap on unaligned accesses") }, \
456 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
457 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
458 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
459 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
460 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
461 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
462 N_("Use library calls to perform FP operations") }, \
463 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
464 N_("Use hardware floating point instructions") }, \
465 {"big-endian", ARM_FLAG_BIG_END, \
466 N_("Assume target CPU is configured as big endian") }, \
467 {"little-endian", -ARM_FLAG_BIG_END, \
468 N_("Assume target CPU is configured as little endian") }, \
469 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
470 N_("Assume big endian bytes, little endian words") }, \
471 {"thumb-interwork", ARM_FLAG_INTERWORK, \
472 N_("Support calls between Thumb and ARM instruction sets") }, \
473 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
474 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
475 N_("Generate a call to abort if a noreturn function returns")}, \
476 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
477 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
478 N_("Do not move instructions into a function's prologue") }, \
479 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
480 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
481 N_("Do not load the PIC register in function prologues") }, \
482 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
483 {"long-calls", ARM_FLAG_LONG_CALLS, \
484 N_("Generate call insns as indirect calls, if necessary") }, \
485 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
486 {"thumb", ARM_FLAG_THUMB, \
487 N_("Compile for the Thumb not the ARM") }, \
488 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
489 {"arm", -ARM_FLAG_THUMB, "" }, \
490 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
491 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
492 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
493 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
494 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
495 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
496 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
497 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
498 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
500 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
501 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
502 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
504 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
505 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
506 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
507 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
509 {"", TARGET_DEFAULT, "" } \
512 #define TARGET_OPTIONS \
514 {"cpu=", & arm_select[0].string, \
515 N_("Specify the name of the target CPU") }, \
516 {"arch=", & arm_select[1].string, \
517 N_("Specify the name of the target architecture") }, \
518 {"tune=", & arm_select[2].string, "" }, \
519 {"fpe=", & target_fp_name, "" }, \
520 {"fp=", & target_fp_name, \
521 N_("Specify the version of the floating point emulator") }, \
522 {"structure-size-boundary=", & structure_size_string, \
523 N_("Specify the minimum bit alignment of structures") }, \
524 {"pic-register=", & arm_pic_register_string, \
525 N_("Specify the register to be used for PIC addressing") } \
528 struct arm_cpu_select
532 const struct processors * processors;
535 /* This is a magic array. If the user specifies a command line switch
536 which matches one of the entries in TARGET_OPTIONS then the corresponding
537 string pointer will be set to the value specified by the user. */
538 extern struct arm_cpu_select arm_select[];
546 /* Recast the program mode class to be the prog_mode attribute */
547 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
549 extern enum prog_mode_type arm_prgmode;
551 /* What sort of floating point unit do we have? Hardware or software.
552 If software, is it issue 2 or issue 3? */
555 /* Software floating point, FPA style double fmt. */
557 /* Full FPA support. */
559 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
561 /* Emulated FPA hardware, Issue 3 emulator. */
563 /* Cirrus Maverick floating point co-processor. */
567 /* Recast the floating point class to be the floating point attribute. */
568 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
570 /* What type of floating point to tune for */
571 extern enum fputype arm_fpu_tune;
573 /* What type of floating point instructions are available */
574 extern enum fputype arm_fpu_arch;
576 /* Default floating point architecture. Override in sub-target if
578 #ifndef FPUTYPE_DEFAULT
579 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
582 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
583 #undef FPUTYPE_DEFAULT
584 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
587 /* Nonzero if the processor has a fast multiply insn, and one that does
588 a 64-bit multiply of two 32-bit values. */
589 extern int arm_fast_multiply;
591 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
592 extern int arm_arch4;
594 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
595 extern int arm_arch5;
597 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
598 extern int arm_arch5e;
600 /* Nonzero if this chip can benefit from load scheduling. */
601 extern int arm_ld_sched;
603 /* Nonzero if generating thumb code. */
604 extern int thumb_code;
606 /* Nonzero if this chip is a StrongARM. */
607 extern int arm_is_strong;
609 /* Nonzero if this chip is a Cirrus variant. */
610 extern int arm_is_cirrus;
612 /* Nonzero if this chip is an XScale. */
613 extern int arm_is_xscale;
615 /* Nonzero if this chip is an ARM6 or an ARM7. */
616 extern int arm_is_6_or_7;
618 #ifndef TARGET_DEFAULT
619 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
622 /* The frame pointer register used in gcc has nothing to do with debugging;
623 that is controlled by the APCS-FRAME option. */
624 #define CAN_DEBUG_WITHOUT_FP
626 #undef TARGET_MEM_FUNCTIONS
627 #define TARGET_MEM_FUNCTIONS 1
629 #define OVERRIDE_OPTIONS arm_override_options ()
631 /* Nonzero if PIC code requires explicit qualifiers to generate
632 PLT and GOT relocs rather than the assembler doing so implicitly.
633 Subtargets can override these if required. */
634 #ifndef NEED_GOT_RELOC
635 #define NEED_GOT_RELOC 0
637 #ifndef NEED_PLT_RELOC
638 #define NEED_PLT_RELOC 0
641 /* Nonzero if we need to refer to the GOT with a PC-relative
642 offset. In other words, generate
644 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
648 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
650 The default is true, which matches NetBSD. Subtargets can
651 override this if required. */
656 /* Target machine storage Layout. */
659 /* Define this macro if it is advisable to hold scalars in registers
660 in a wider mode than that declared by the program. In such cases,
661 the value is constrained to be within the bounds of the declared
662 type, but kept valid in the wider mode. The signedness of the
663 extension may differ from that of the type. */
665 /* It is far faster to zero extend chars than to sign extend them */
667 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
668 if (GET_MODE_CLASS (MODE) == MODE_INT \
669 && GET_MODE_SIZE (MODE) < 4) \
671 if (MODE == QImode) \
673 else if (MODE == HImode) \
674 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
678 /* Define this macro if the promotion described by `PROMOTE_MODE'
679 should also be done for outgoing function arguments. */
680 /* This is required to ensure that push insns always push a word. */
681 #define PROMOTE_FUNCTION_ARGS
683 /* Define this if most significant bit is lowest numbered
684 in instructions that operate on numbered bit-fields. */
685 #define BITS_BIG_ENDIAN 0
687 /* Define this if most significant byte of a word is the lowest numbered.
688 Most ARM processors are run in little endian mode, so that is the default.
689 If you want to have it run-time selectable, change the definition in a
690 cover file to be TARGET_BIG_ENDIAN. */
691 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
693 /* Define this if most significant word of a multiword number is the lowest
695 This is always false, even when in big-endian mode. */
696 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
698 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
699 on processor pre-defineds when compiling libgcc2.c. */
700 #if defined(__ARMEB__) && !defined(__ARMWEL__)
701 #define LIBGCC2_WORDS_BIG_ENDIAN 1
703 #define LIBGCC2_WORDS_BIG_ENDIAN 0
706 /* Define this if most significant word of doubles is the lowest numbered.
707 The rules are different based on whether or not we use FPA-format,
708 VFP-format or some other floating point co-processor's format doubles. */
709 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
711 #define UNITS_PER_WORD 4
713 #define PARM_BOUNDARY 32
715 #define STACK_BOUNDARY 32
717 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
719 #define FUNCTION_BOUNDARY 32
721 /* The lowest bit is used to indicate Thumb-mode functions, so the
722 vbit must go into the delta field of pointers to member
724 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
726 #define EMPTY_FIELD_BOUNDARY 32
728 #define BIGGEST_ALIGNMENT 32
730 /* Make strings word-aligned so strcpy from constants will be faster. */
731 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
733 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
734 ((TREE_CODE (EXP) == STRING_CST \
735 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
736 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
738 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
739 value set in previous versions of this toolchain was 8, which produces more
740 compact structures. The command line option -mstructure_size_boundary=<n>
741 can be used to change this value. For compatibility with the ARM SDK
742 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
743 0020D) page 2-20 says "Structures are aligned on word boundaries". */
744 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
745 extern int arm_structure_size_boundary;
747 /* This is the value used to initialize arm_structure_size_boundary. If a
748 particular arm target wants to change the default value it should change
749 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
750 for an example of this. */
751 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
752 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
755 /* Used when parsing command line option -mstructure_size_boundary. */
756 extern const char * structure_size_string;
758 /* Nonzero if move instructions will actually fail to work
759 when given unaligned data. */
760 #define STRICT_ALIGNMENT 1
762 /* Standard register usage. */
764 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
765 (S - saved over call).
767 r0 * argument word/integer result
770 r4-r8 S register variable
771 r9 S (rfp) register variable (real frame pointer)
773 r10 F S (sl) stack limit (used by -mapcs-stack-check)
774 r11 F S (fp) argument pointer
775 r12 (ip) temp workspace
776 r13 F S (sp) lower end of current stack frame
777 r14 (lr) link address/workspace
778 r15 F (pc) program counter
780 f0 floating point result
781 f1-f3 floating point scratch
783 f4-f7 S floating point variable
785 cc This is NOT a real register, but is used internally
786 to represent things that use or set the condition
788 sfp This isn't either. It is used during rtl generation
789 since the offset between the frame pointer and the
790 auto's isn't known until after register allocation.
791 afp Nor this, we only need this because of non-local
792 goto. Without it fp appears to be used and the
793 elimination code won't get rid of sfp. It tracks
794 fp exactly at all times.
796 *: See CONDITIONAL_REGISTER_USAGE */
799 mvf0 Cirrus floating point result
800 mvf1-mvf3 Cirrus floating point scratch
801 mvf4-mvf15 S Cirrus floating point variable. */
803 /* The stack backtrace structure is as follows:
804 fp points to here: | save code pointer | [fp]
805 | return link value | [fp, #-4]
806 | return sp value | [fp, #-8]
807 | return fp value | [fp, #-12]
808 [| saved r10 value |]
819 [| saved f7 value |] three words
820 [| saved f6 value |] three words
821 [| saved f5 value |] three words
822 [| saved f4 value |] three words
823 r0-r3 are not normally saved in a C function. */
825 /* 1 for registers that have pervasive standard uses
826 and are not available for the register allocator. */
827 #define FIXED_REGISTERS \
837 /* 1 for registers not available across function calls.
838 These must include the FIXED_REGISTERS and also any
839 registers that can be used without being saved.
840 The latter must include the registers where values are returned
841 and the register where structure-value addresses are passed.
842 Aside from that, you can include as many other registers as you like.
843 The CC is not preserved over function calls on the ARM 6, so it is
844 easier to assume this for all. SFP is preserved, since FP is. */
845 #define CALL_USED_REGISTERS \
855 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
856 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
859 #define CONDITIONAL_REGISTER_USAGE \
863 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
865 for (regno = FIRST_ARM_FP_REGNUM; \
866 regno <= LAST_ARM_FP_REGNUM; ++regno) \
867 fixed_regs[regno] = call_used_regs[regno] = 1; \
872 for (regno = FIRST_ARM_FP_REGNUM; \
873 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
874 fixed_regs[regno] = call_used_regs[regno] = 1; \
875 for (regno = FIRST_CIRRUS_FP_REGNUM; \
876 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
878 fixed_regs[regno] = 0; \
879 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
883 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
885 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
886 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
888 else if (TARGET_APCS_STACK) \
890 fixed_regs[10] = 1; \
891 call_used_regs[10] = 1; \
893 if (TARGET_APCS_FRAME) \
895 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
896 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
898 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
901 /* These are a couple of extensions to the formats accepted
903 %@ prints out ASM_COMMENT_START
904 %r prints out REGISTER_PREFIX reg_names[arg] */
905 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
907 fputs (ASM_COMMENT_START, FILE); \
911 fputs (REGISTER_PREFIX, FILE); \
912 fputs (reg_names [va_arg (ARGS, int)], FILE); \
915 /* Round X up to the nearest word. */
916 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
918 /* Convert fron bytes to ints. */
919 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
921 /* The number of (integer) registers required to hold a quantity of type MODE. */
922 #define ARM_NUM_REGS(MODE) \
923 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
925 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
926 #define ARM_NUM_REGS2(MODE, TYPE) \
927 ARM_NUM_INTS ((MODE) == BLKmode ? \
928 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
930 /* The number of (integer) argument register available. */
931 #define NUM_ARG_REGS 4
933 /* Return the regiser number of the N'th (integer) argument. */
934 #define ARG_REGISTER(N) (N - 1)
936 #if 0 /* FIXME: The ARM backend has special code to handle structure
937 returns, and will reserve its own hidden first argument. So
938 if this macro is enabled a *second* hidden argument will be
939 reserved, which will break binary compatibility with old
940 toolchains and also thunk handling. One day this should be
942 /* RTX for structure returns. NULL means use a hidden first argument. */
943 #define STRUCT_VALUE 0
945 /* Register in which address to store a structure value
946 is passed to a function. */
947 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
950 /* Specify the registers used for certain standard purposes.
951 The values of these macros are register numbers. */
953 /* The number of the last argument register. */
954 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
956 /* The number of the last "lo" register (thumb). */
957 #define LAST_LO_REGNUM 7
959 /* The register that holds the return address in exception handlers. */
960 #define EXCEPTION_LR_REGNUM 2
962 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
963 as an invisible last argument (possible since varargs don't exist in
964 Pascal), so the following is not true. */
965 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
967 /* Define this to be where the real frame pointer is if it is not possible to
968 work out the offset between the frame pointer and the automatic variables
969 until after register allocation has taken place. FRAME_POINTER_REGNUM
970 should point to a special register that we will make sure is eliminated.
972 For the Thumb we have another problem. The TPCS defines the frame pointer
973 as r11, and GCC believes that it is always possible to use the frame pointer
974 as base register for addressing purposes. (See comments in
975 find_reloads_address()). But - the Thumb does not allow high registers,
976 including r11, to be used as base address registers. Hence our problem.
978 The solution used here, and in the old thumb port is to use r7 instead of
979 r11 as the hard frame pointer and to have special code to generate
980 backtrace structures on the stack (if required to do so via a command line
981 option) using r11. This is the only 'user visible' use of r11 as a frame
983 #define ARM_HARD_FRAME_POINTER_REGNUM 11
984 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
986 #define HARD_FRAME_POINTER_REGNUM \
988 ? ARM_HARD_FRAME_POINTER_REGNUM \
989 : THUMB_HARD_FRAME_POINTER_REGNUM)
991 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
993 /* Register to use for pushing function arguments. */
994 #define STACK_POINTER_REGNUM SP_REGNUM
996 /* ARM floating pointer registers. */
997 #define FIRST_ARM_FP_REGNUM 16
998 #define LAST_ARM_FP_REGNUM 23
1000 /* Base register for access to local variables of the function. */
1001 #define FRAME_POINTER_REGNUM 25
1003 /* Base register for access to arguments of the function. */
1004 #define ARG_POINTER_REGNUM 26
1006 #define FIRST_CIRRUS_FP_REGNUM 27
1007 #define LAST_CIRRUS_FP_REGNUM 42
1008 #define IS_CIRRUS_REGNUM(REGNUM) \
1009 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1011 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1012 /* + 16 Cirrus registers take us up to 43. */
1013 #define FIRST_PSEUDO_REGISTER 43
1015 /* Value should be nonzero if functions must have frame pointers.
1016 Zero means the frame pointer need not be set up (and parms may be accessed
1017 via the stack pointer) in functions that seem suitable.
1018 If we have to have a frame pointer we might as well make use of it.
1019 APCS says that the frame pointer does not need to be pushed in leaf
1020 functions, or simple tail call functions. */
1021 #define FRAME_POINTER_REQUIRED \
1022 (current_function_has_nonlocal_label \
1023 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1025 /* Return number of consecutive hard regs needed starting at reg REGNO
1026 to hold something of mode MODE.
1027 This is ordinarily the length in words of a value of mode MODE
1028 but can be less for certain modes in special long registers.
1030 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1032 #define HARD_REGNO_NREGS(REGNO, MODE) \
1034 && REGNO >= FIRST_ARM_FP_REGNUM \
1035 && REGNO != FRAME_POINTER_REGNUM \
1036 && REGNO != ARG_POINTER_REGNUM) \
1037 ? 1 : ARM_NUM_REGS (MODE))
1039 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1040 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1041 arm_hard_regno_mode_ok ((REGNO), (MODE))
1043 /* Value is 1 if it is a good idea to tie two pseudo registers
1044 when one has mode MODE1 and one has mode MODE2.
1045 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1046 for any hard reg, then this must be 0 for correct output. */
1047 #define MODES_TIEABLE_P(MODE1, MODE2) \
1048 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1050 /* The order in which register should be allocated. It is good to use ip
1051 since no saving is required (though calls clobber it) and it never contains
1052 function parameters. It is quite good to use lr since other calls may
1053 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1054 least likely to contain a function parameter; in addition results are
1056 #define REG_ALLOC_ORDER \
1058 3, 2, 1, 0, 12, 14, 4, 5, \
1059 6, 7, 8, 10, 9, 11, 13, 15, \
1060 16, 17, 18, 19, 20, 21, 22, 23, \
1061 27, 28, 29, 30, 31, 32, 33, 34, \
1062 35, 36, 37, 38, 39, 40, 41, 42, \
1066 /* Interrupt functions can only use registers that have already been
1067 saved by the prologue, even if they would normally be
1069 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1070 (! IS_INTERRUPT (cfun->machine->func_type) || \
1071 regs_ever_live[DST])
1073 /* Register and constant classes. */
1075 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1076 Now that the Thumb is involved it has become more complicated. */
1092 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1094 /* Give names of register classes as strings for dump file. */
1095 #define REG_CLASS_NAMES \
1109 /* Define which registers fit in which classes.
1110 This is an initializer for a vector of HARD_REG_SET
1111 of length N_REG_CLASSES. */
1112 #define REG_CLASS_CONTENTS \
1114 { 0x00000000, 0x0 }, /* NO_REGS */ \
1115 { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
1116 { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
1117 { 0x000000FF, 0x0 }, /* LO_REGS */ \
1118 { 0x00002000, 0x0 }, /* STACK_REG */ \
1119 { 0x000020FF, 0x0 }, /* BASE_REGS */ \
1120 { 0x0000FF00, 0x0 }, /* HI_REGS */ \
1121 { 0x01000000, 0x0 }, /* CC_REG */ \
1122 { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\
1123 { 0xFAFFFFFF, 0x000007FF } /* ALL_REGS */ \
1126 /* The same information, inverted:
1127 Return the class number of the smallest class containing
1128 reg number REGNO. This could be a conditional expression
1129 or could index an array. */
1130 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1132 /* The class value for index registers, and the one for base regs. */
1133 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1134 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1136 /* For the Thumb the high registers cannot be used as base registers
1137 when addressing quantities in QI or HI mode; if we don't know the
1138 mode, then we must be conservative. After reload we must also be
1139 conservative, since we can't support SP+reg addressing, and we
1140 can't fix up any bad substitutions. */
1141 #define MODE_BASE_REG_CLASS(MODE) \
1142 (TARGET_ARM ? GENERAL_REGS : \
1143 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1145 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1146 registers explicitly used in the rtl to be used as spill registers
1147 but prevents the compiler from extending the lifetime of these
1149 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1151 /* Get reg_class from a letter such as appears in the machine description.
1152 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1153 ARM, but several more letters for the Thumb. */
1154 #define REG_CLASS_FROM_LETTER(C) \
1155 ( (C) == 'f' ? FPA_REGS \
1156 : (C) == 'v' ? CIRRUS_REGS \
1157 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1158 : TARGET_ARM ? NO_REGS \
1159 : (C) == 'h' ? HI_REGS \
1160 : (C) == 'b' ? BASE_REGS \
1161 : (C) == 'k' ? STACK_REG \
1162 : (C) == 'c' ? CC_REG \
1165 /* The letters I, J, K, L and M in a register constraint string
1166 can be used to stand for particular ranges of immediate operands.
1167 This macro defines what the ranges are.
1168 C is the letter, and VALUE is a constant value.
1169 Return 1 if VALUE is in the range specified by C.
1170 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1171 J: valid indexing constants.
1172 K: ~value ok in rhs argument of data operand.
1173 L: -value ok in rhs argument of data operand.
1174 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1175 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1176 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1177 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1178 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1179 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1180 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1181 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1184 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1185 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1186 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1187 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1188 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1189 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1190 && ((VAL) & 3) == 0) : \
1191 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1192 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1195 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1197 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1199 /* Constant letter 'G' for the FPA immediate constants.
1200 'H' means the same constant negated. */
1201 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1202 ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
1203 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1205 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1207 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1209 /* For the ARM, `Q' means that this is a memory operand that is just
1210 an offset from a register.
1211 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1212 address. This means that the symbol is in the text segment and can be
1213 accessed without using a load. */
1215 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1216 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1217 (C) == 'R' ? (GET_CODE (OP) == MEM \
1218 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1219 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1220 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1221 (C) == 'T' ? cirrus_memory_offset (OP) : \
1224 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1225 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1226 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1228 #define EXTRA_CONSTRAINT(X, C) \
1230 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1232 /* Given an rtx X being reloaded into a reg required to be
1233 in class CLASS, return the class of reg to actually use.
1234 In general this is just CLASS, but for the Thumb we prefer
1235 a LO_REGS class or a subset. */
1236 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1237 (TARGET_ARM ? (CLASS) : \
1238 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1240 /* Must leave BASE_REGS reloads alone */
1241 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1242 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1243 ? ((true_regnum (X) == -1 ? LO_REGS \
1244 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1248 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1249 ((CLASS) != LO_REGS \
1250 ? ((true_regnum (X) == -1 ? LO_REGS \
1251 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1255 /* Return the register class of a scratch register needed to copy IN into
1256 or out of a register in CLASS in MODE. If it can be done directly,
1257 NO_REGS is returned. */
1258 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1260 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1261 ? GENERAL_REGS : NO_REGS) \
1262 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1264 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1265 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1266 /* Cannot load constants into Cirrus registers. */ \
1268 && (CLASS) == CIRRUS_REGS \
1269 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1272 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1273 && (GET_CODE (X) == MEM \
1274 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1275 && true_regnum (X) == -1))) \
1276 ? GENERAL_REGS : NO_REGS) \
1277 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1279 /* Try a machine-dependent way of reloading an illegitimate address
1280 operand. If we find one, push the reload and jump to WIN. This
1281 macro is used in only one place: `find_reloads_address' in reload.c.
1283 For the ARM, we wish to handle large displacements off a base
1284 register by splitting the addend across a MOV and the mem insn.
1285 This can cut the number of reloads needed. */
1286 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1289 if (GET_CODE (X) == PLUS \
1290 && GET_CODE (XEXP (X, 0)) == REG \
1291 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1292 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1293 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1295 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1296 HOST_WIDE_INT low, high; \
1298 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1299 low = ((val & 0xf) ^ 0x8) - 0x8; \
1300 else if (TARGET_CIRRUS) \
1301 /* Need to be careful, -256 is not a valid offset. */ \
1302 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1303 else if (MODE == SImode \
1304 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1305 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1306 /* Need to be careful, -4096 is not a valid offset. */ \
1307 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1308 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1309 /* Need to be careful, -256 is not a valid offset. */ \
1310 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1311 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1312 && TARGET_HARD_FLOAT) \
1313 /* Need to be careful, -1024 is not a valid offset. */ \
1314 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1318 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1319 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1320 - (unsigned HOST_WIDE_INT) 0x80000000); \
1321 /* Check for overflow or zero */ \
1322 if (low == 0 || high == 0 || (high + low != val)) \
1325 /* Reload the high part into a base reg; leave the low part \
1327 X = gen_rtx_PLUS (GET_MODE (X), \
1328 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1331 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1332 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1333 VOIDmode, 0, 0, OPNUM, TYPE); \
1339 /* ??? If an HImode FP+large_offset address is converted to an HImode
1340 SP+large_offset address, then reload won't know how to fix it. It sees
1341 only that SP isn't valid for HImode, and so reloads the SP into an index
1342 register, but the resulting address is still invalid because the offset
1343 is too big. We fix it here instead by reloading the entire address. */
1344 /* We could probably achieve better results by defining PROMOTE_MODE to help
1345 cope with the variances between the Thumb's signed and unsigned byte and
1346 halfword load instructions. */
1347 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1349 if (GET_CODE (X) == PLUS \
1350 && GET_MODE_SIZE (MODE) < 4 \
1351 && GET_CODE (XEXP (X, 0)) == REG \
1352 && XEXP (X, 0) == stack_pointer_rtx \
1353 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1354 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1358 push_reload (orig_X, NULL_RTX, &X, NULL, \
1359 MODE_BASE_REG_CLASS (MODE), \
1360 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1365 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1367 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1369 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1371 /* Return the maximum number of consecutive registers
1372 needed to represent mode MODE in a register of class CLASS.
1373 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1374 #define CLASS_MAX_NREGS(CLASS, MODE) \
1375 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1377 /* If defined, gives a class of registers that cannot be used as the
1378 operand of a SUBREG that changes the mode of the object illegally. */
1380 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1381 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1383 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1384 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1385 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1386 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1389 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1391 /* Stack layout; function entry, exit and calling. */
1393 /* Define this if pushing a word on the stack
1394 makes the stack pointer a smaller address. */
1395 #define STACK_GROWS_DOWNWARD 1
1397 /* Define this if the nominal address of the stack frame
1398 is at the high-address end of the local variables;
1399 that is, each additional local variable allocated
1400 goes at a more negative offset in the frame. */
1401 #define FRAME_GROWS_DOWNWARD 1
1403 /* Offset within stack frame to start allocating local variables at.
1404 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1405 first local allocated. Otherwise, it is the offset to the BEGINNING
1406 of the first local allocated. */
1407 #define STARTING_FRAME_OFFSET 0
1409 /* If we generate an insn to push BYTES bytes,
1410 this says how many the stack pointer really advances by. */
1411 /* The push insns do not do this rounding implicitly.
1412 So don't define this. */
1413 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1415 /* Define this if the maximum size of all the outgoing args is to be
1416 accumulated and pushed during the prologue. The amount can be
1417 found in the variable current_function_outgoing_args_size. */
1418 #define ACCUMULATE_OUTGOING_ARGS 1
1420 /* Offset of first parameter from the argument pointer register value. */
1421 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1423 /* Value is the number of byte of arguments automatically
1424 popped when returning from a subroutine call.
1425 FUNDECL is the declaration node of the function (as a tree),
1426 FUNTYPE is the data type of the function (as a tree),
1427 or for a library call it is an identifier node for the subroutine name.
1428 SIZE is the number of bytes of arguments passed on the stack.
1430 On the ARM, the caller does not pop any of its arguments that were passed
1432 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1434 /* Define how to find the value returned by a library function
1435 assuming the value has mode MODE. */
1436 #define LIBCALL_VALUE(MODE) \
1437 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1438 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1439 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1440 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1441 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1443 /* Define how to find the value returned by a function.
1444 VALTYPE is the data type of the value (as a tree).
1445 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1446 otherwise, FUNC is 0. */
1447 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1448 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1450 /* 1 if N is a possible register number for a function value.
1451 On the ARM, only r0 and f0 can return results. */
1452 /* On a Cirrus chip, mvf0 can return results. */
1453 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1454 ((REGNO) == ARG_REGISTER (1) \
1455 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1456 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1458 /* How large values are returned */
1459 /* A C expression which can inhibit the returning of certain function values
1460 in registers, based on the type of value. */
1461 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1463 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1464 values must be in memory. On the ARM, they need only do so if larger
1465 than a word, or if they contain elements offset from zero in the struct. */
1466 #define DEFAULT_PCC_STRUCT_RETURN 0
1468 /* Flags for the call/call_value rtl operations set up by function_arg. */
1469 #define CALL_NORMAL 0x00000000 /* No special processing. */
1470 #define CALL_LONG 0x00000001 /* Always call indirect. */
1471 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1473 /* These bits describe the different types of function supported
1474 by the ARM backend. They are exclusive. ie a function cannot be both a
1475 normal function and an interworked function, for example. Knowing the
1476 type of a function is important for determining its prologue and
1478 Note value 7 is currently unassigned. Also note that the interrupt
1479 function types all have bit 2 set, so that they can be tested for easily.
1480 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1481 machine_function structure is initialized (to zero) func_type will
1482 default to unknown. This will force the first use of arm_current_func_type
1483 to call arm_compute_func_type. */
1484 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1485 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1486 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1487 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1488 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1489 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1490 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1492 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1494 /* In addition functions can have several type modifiers,
1495 outlined by these bit masks: */
1496 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1497 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1498 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1499 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1501 /* Some macros to test these flags. */
1502 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1503 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1504 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1505 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1506 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1508 /* A C structure for machine-specific, per-function data.
1509 This is added to the cfun structure. */
1510 typedef struct machine_function GTY(())
1512 /* Additional stack adjustment in __builtin_eh_throw. */
1513 rtx eh_epilogue_sp_ofs;
1514 /* Records if LR has to be saved for far jumps. */
1516 /* Records if ARG_POINTER was ever live. */
1517 int arg_pointer_live;
1518 /* Records if the save of LR has been eliminated. */
1519 int lr_save_eliminated;
1520 /* The size of the stack frame. Only valid after reload. */
1522 /* Records the type of the current function. */
1523 unsigned long func_type;
1524 /* Record if the function has a variable argument list. */
1525 int uses_anonymous_args;
1529 /* A C type for declaring a variable that is used as the first argument of
1530 `FUNCTION_ARG' and other related values. For some target machines, the
1531 type `int' suffices and can hold the number of bytes of argument so far. */
1534 /* This is the number of registers of arguments scanned so far. */
1536 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1540 /* Define where to put the arguments to a function.
1541 Value is zero to push the argument on the stack,
1542 or a hard register in which to store the argument.
1544 MODE is the argument's machine mode.
1545 TYPE is the data type of the argument (as a tree).
1546 This is null for libcalls where that information may
1548 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1549 the preceding args and about the function being called.
1550 NAMED is nonzero if this argument is a named parameter
1551 (otherwise it is an extra parameter matching an ellipsis).
1553 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1554 other arguments are passed on the stack. If (NAMED == 0) (which happens
1555 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1556 passed in the stack (function_prologue will indeed make it pass in the
1557 stack if necessary). */
1558 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1559 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1561 /* For an arg passed partly in registers and partly in memory,
1562 this is the number of registers used.
1563 For args passed entirely in registers or entirely in memory, zero. */
1564 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1565 ( NUM_ARG_REGS > (CUM).nregs \
1566 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1567 ? NUM_ARG_REGS - (CUM).nregs : 0)
1569 /* A C expression that indicates when an argument must be passed by
1570 reference. If nonzero for an argument, a copy of that argument is
1571 made in memory and a pointer to the argument is passed instead of
1572 the argument itself. The pointer is passed in whatever way is
1573 appropriate for passing a pointer to that type. */
1574 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1575 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1577 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1578 for a call to a function whose data type is FNTYPE.
1579 For a library call, FNTYPE is 0.
1580 On the ARM, the offset starts at 0. */
1581 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1582 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1584 /* Update the data in CUM to advance over an argument
1585 of mode MODE and data type TYPE.
1586 (TYPE is null for libcalls where that information may not be available.) */
1587 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1588 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1590 /* 1 if N is a possible register number for function argument passing.
1591 On the ARM, r0-r3 are used to pass args. */
1592 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1594 /* Implement `va_arg'. */
1595 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1596 arm_va_arg (valist, type)
1599 /* Perform any actions needed for a function that is receiving a variable
1600 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1601 of the current parameter. PRETEND_SIZE is a variable that should be set to
1602 the amount of stack that must be pushed by the prolog to pretend that our
1605 Normally, this macro will push all remaining incoming registers on the
1606 stack and set PRETEND_SIZE to the length of the registers pushed.
1608 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1609 named arg and all anonymous args onto the stack.
1610 XXX I know the prologue shouldn't be pushing registers, but it is faster
1612 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1614 cfun->machine->uses_anonymous_args = 1; \
1615 if ((CUM).nregs < NUM_ARG_REGS) \
1616 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1619 /* If your target environment doesn't prefix user functions with an
1620 underscore, you may wish to re-define this to prevent any conflicts.
1621 e.g. AOF may prefix mcount with an underscore. */
1622 #ifndef ARM_MCOUNT_NAME
1623 #define ARM_MCOUNT_NAME "*mcount"
1626 /* Call the function profiler with a given profile label. The Acorn
1627 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1628 On the ARM the full profile code will look like:
1637 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1638 will output the .text section.
1640 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1641 ``prof'' doesn't seem to mind about this!
1643 Note - this version of the code is designed to work in both ARM and
1645 #ifndef ARM_FUNCTION_PROFILER
1646 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1651 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1652 IP_REGNUM, LR_REGNUM); \
1653 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1654 fputc ('\n', STREAM); \
1655 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1656 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1657 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1661 #ifdef THUMB_FUNCTION_PROFILER
1662 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1664 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1666 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1668 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1669 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1672 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1673 the stack pointer does not matter. The value is tested only in
1674 functions that have frame pointers.
1675 No definition is equivalent to always zero.
1677 On the ARM, the function epilogue recovers the stack pointer from the
1679 #define EXIT_IGNORE_STACK 1
1681 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1683 /* Determine if the epilogue should be output as RTL.
1684 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1685 #define USE_RETURN_INSN(ISCOND) \
1686 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1688 /* Definitions for register eliminations.
1690 This is an array of structures. Each structure initializes one pair
1691 of eliminable registers. The "from" register number is given first,
1692 followed by "to". Eliminations of the same "from" register are listed
1693 in order of preference.
1695 We have two registers that can be eliminated on the ARM. First, the
1696 arg pointer register can often be eliminated in favor of the stack
1697 pointer register. Secondly, the pseudo frame pointer register can always
1698 be eliminated; it is replaced with either the stack or the real frame
1699 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1700 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1702 #define ELIMINABLE_REGS \
1703 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1704 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1705 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1706 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1707 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1708 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1709 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1711 /* Given FROM and TO register numbers, say whether this elimination is
1712 allowed. Frame pointer elimination is automatically handled.
1714 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1715 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1716 pointer, we must eliminate FRAME_POINTER_REGNUM into
1717 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1718 ARG_POINTER_REGNUM. */
1719 #define CAN_ELIMINATE(FROM, TO) \
1720 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1721 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1722 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1723 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1726 #define THUMB_REG_PUSHED_P(reg) \
1727 (regs_ever_live [reg] \
1728 && (! call_used_regs [reg] \
1729 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1730 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1732 /* Define the offset between two registers, one to be eliminated, and the
1733 other its replacement, at the start of a routine. */
1734 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1737 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1741 /* Note: This macro must match the code in thumb_function_prologue(). */
1742 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1745 if ((FROM) == ARG_POINTER_REGNUM) \
1747 int count_regs = 0; \
1749 for (regno = 8; regno < 13; regno ++) \
1750 if (THUMB_REG_PUSHED_P (regno)) \
1753 (OFFSET) += 4 * count_regs; \
1755 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1756 if (THUMB_REG_PUSHED_P (regno)) \
1758 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1759 (OFFSET) += 4 * (count_regs + 1); \
1760 if (TARGET_BACKTRACE) \
1762 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1768 if ((TO) == STACK_POINTER_REGNUM) \
1770 (OFFSET) += current_function_outgoing_args_size; \
1771 (OFFSET) += thumb_get_frame_size (); \
1775 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1777 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1779 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1781 /* Special case handling of the location of arguments passed on the stack. */
1782 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1784 /* Initialize data used by insn expanders. This is called from insn_emit,
1785 once for every function before code is generated. */
1786 #define INIT_EXPANDERS arm_init_expanders ()
1788 /* Output assembler code for a block containing the constant parts
1789 of a trampoline, leaving space for the variable parts.
1791 On the ARM, (if r8 is the static chain regnum, and remembering that
1792 referencing pc adds an offset of 8) the trampoline looks like:
1795 .word static chain value
1796 .word function's address
1797 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1798 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1800 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1801 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1802 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1803 PC_REGNUM, PC_REGNUM); \
1804 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1805 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1808 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1809 Why - because it is easier. This code will always be branched to via
1810 a BX instruction and since the compiler magically generates the address
1811 of the function the linker has no opportunity to ensure that the
1812 bottom bit is set. Thus the processor will be in ARM mode when it
1813 reaches this code. So we duplicate the ARM trampoline code and add
1814 a switch into Thumb mode as well. */
1815 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1817 fprintf (FILE, "\t.code 32\n"); \
1818 fprintf (FILE, ".Ltrampoline_start:\n"); \
1819 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1820 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1821 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1822 IP_REGNUM, PC_REGNUM); \
1823 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1824 IP_REGNUM, IP_REGNUM); \
1825 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1826 fprintf (FILE, "\t.word\t0\n"); \
1827 fprintf (FILE, "\t.word\t0\n"); \
1828 fprintf (FILE, "\t.code 16\n"); \
1831 #define TRAMPOLINE_TEMPLATE(FILE) \
1833 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1835 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1837 /* Length in units of the trampoline for entering a nested function. */
1838 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1840 /* Alignment required for a trampoline in bits. */
1841 #define TRAMPOLINE_ALIGNMENT 32
1843 /* Emit RTL insns to initialize the variable parts of a trampoline.
1844 FNADDR is an RTX for the address of the function's pure code.
1845 CXT is an RTX for the static chain value for the function. */
1846 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1849 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1851 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1855 /* Addressing modes, and classification of registers for them. */
1856 #define HAVE_POST_INCREMENT 1
1857 #define HAVE_PRE_INCREMENT TARGET_ARM
1858 #define HAVE_POST_DECREMENT TARGET_ARM
1859 #define HAVE_PRE_DECREMENT TARGET_ARM
1860 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1861 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1862 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1863 #define HAVE_POST_MODIFY_REG TARGET_ARM
1865 /* Macros to check register numbers against specific register classes. */
1867 /* These assume that REGNO is a hard or pseudo reg number.
1868 They give nonzero only if REGNO is a hard reg of the suitable class
1869 or a pseudo reg currently allocated to a suitable hard reg.
1870 Since they use reg_renumber, they are safe only once reg_renumber
1871 has been allocated, which happens in local-alloc.c. */
1872 #define TEST_REGNO(R, TEST, VALUE) \
1873 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1875 /* On the ARM, don't allow the pc to be used. */
1876 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1877 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1878 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1879 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1881 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1882 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1883 || (GET_MODE_SIZE (MODE) >= 4 \
1884 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1886 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1888 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1889 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1891 /* For ARM code, we don't care about the mode, but for Thumb, the index
1892 must be suitable for use in a QImode load. */
1893 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1894 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1896 /* Maximum number of registers that can appear in a valid memory address.
1897 Shifts in addresses can't be by a register. */
1898 #define MAX_REGS_PER_ADDRESS 2
1900 /* Recognize any constant value that is a valid address. */
1901 /* XXX We can address any constant, eventually... */
1903 #ifdef AOF_ASSEMBLER
1905 #define CONSTANT_ADDRESS_P(X) \
1906 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1910 #define CONSTANT_ADDRESS_P(X) \
1911 (GET_CODE (X) == SYMBOL_REF \
1912 && (CONSTANT_POOL_ADDRESS_P (X) \
1913 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1915 #endif /* AOF_ASSEMBLER */
1917 /* Nonzero if the constant value X is a legitimate general operand.
1918 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1920 On the ARM, allow any integer (invalid ones are removed later by insn
1921 patterns), nice doubles and symbol_refs which refer to the function's
1924 When generating pic allow anything. */
1925 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1927 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1928 ( GET_CODE (X) == CONST_INT \
1929 || GET_CODE (X) == CONST_DOUBLE \
1930 || CONSTANT_ADDRESS_P (X) \
1933 #define LEGITIMATE_CONSTANT_P(X) \
1934 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1936 /* Special characters prefixed to function names
1937 in order to encode attribute like information.
1938 Note, '@' and '*' have already been taken. */
1939 #define SHORT_CALL_FLAG_CHAR '^'
1940 #define LONG_CALL_FLAG_CHAR '#'
1942 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1943 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1945 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1946 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1948 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1949 #define SUBTARGET_NAME_ENCODING_LENGTHS
1952 /* This is a C fragment for the inside of a switch statement.
1953 Each case label should return the number of characters to
1954 be stripped from the start of a function's name, if that
1955 name starts with the indicated character. */
1956 #define ARM_NAME_ENCODING_LENGTHS \
1957 case SHORT_CALL_FLAG_CHAR: return 1; \
1958 case LONG_CALL_FLAG_CHAR: return 1; \
1959 case '*': return 1; \
1960 SUBTARGET_NAME_ENCODING_LENGTHS
1962 /* This is how to output a reference to a user-level label named NAME.
1963 `assemble_name' uses this. */
1964 #undef ASM_OUTPUT_LABELREF
1965 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1966 arm_asm_output_labelref (FILE, NAME)
1968 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1969 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1971 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1972 and check its validity for a certain class.
1973 We have two alternate definitions for each of them.
1974 The usual definition accepts all pseudo regs; the other rejects
1975 them unless they have been allocated suitable hard regs.
1976 The symbol REG_OK_STRICT causes the latter definition to be used. */
1977 #ifndef REG_OK_STRICT
1979 #define ARM_REG_OK_FOR_BASE_P(X) \
1980 (REGNO (X) <= LAST_ARM_REGNUM \
1981 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1982 || REGNO (X) == FRAME_POINTER_REGNUM \
1983 || REGNO (X) == ARG_POINTER_REGNUM)
1985 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1986 (REGNO (X) <= LAST_LO_REGNUM \
1987 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1988 || (GET_MODE_SIZE (MODE) >= 4 \
1989 && (REGNO (X) == STACK_POINTER_REGNUM \
1990 || (X) == hard_frame_pointer_rtx \
1991 || (X) == arg_pointer_rtx)))
1993 #define REG_STRICT_P 0
1995 #else /* REG_OK_STRICT */
1997 #define ARM_REG_OK_FOR_BASE_P(X) \
1998 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2000 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2001 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2003 #define REG_STRICT_P 1
2005 #endif /* REG_OK_STRICT */
2007 /* Now define some helpers in terms of the above. */
2009 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2011 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2012 : ARM_REG_OK_FOR_BASE_P (X))
2014 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2016 /* For Thumb, a valid index register is anything that can be used in
2017 a byte load instruction. */
2018 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2020 /* Nonzero if X is a hard reg that can be used as an index
2021 or if it is a pseudo reg. On the Thumb, the stack pointer
2023 #define REG_OK_FOR_INDEX_P(X) \
2025 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2026 : ARM_REG_OK_FOR_INDEX_P (X))
2029 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2030 that is a valid memory address for an instruction.
2031 The MODE argument is the machine mode for the MEM expression
2032 that wants to use this address. */
2034 #define ARM_BASE_REGISTER_RTX_P(X) \
2035 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2037 #define ARM_INDEX_REGISTER_RTX_P(X) \
2038 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2040 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2042 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2046 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2048 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2052 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2054 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2055 else /* if (TARGET_THUMB) */ \
2056 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2059 /* Try machine-dependent ways of modifying an illegitimate address
2060 to be legitimate. If we find one, return the new, valid address. */
2061 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2063 X = arm_legitimize_address (X, OLDX, MODE); \
2065 if (memory_address_p (MODE, X)) \
2069 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2072 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2075 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2078 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2080 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2083 /* Go to LABEL if ADDR (a legitimate address expression)
2084 has an effect that depends on the machine mode it is used for. */
2085 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2087 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2088 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2092 /* Nothing helpful to do for the Thumb */
2093 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2095 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2098 /* Specify the machine mode that this machine uses
2099 for the index in the tablejump instruction. */
2100 #define CASE_VECTOR_MODE Pmode
2102 /* Define as C expression which evaluates to nonzero if the tablejump
2103 instruction expects the table to contain offsets from the address of the
2105 Do not define this if the table should contain absolute addresses. */
2106 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2108 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2109 unsigned is probably best, but may break some code. */
2110 #ifndef DEFAULT_SIGNED_CHAR
2111 #define DEFAULT_SIGNED_CHAR 0
2114 /* Don't cse the address of the function being compiled. */
2115 #define NO_RECURSIVE_FUNCTION_CSE 1
2117 /* Max number of bytes we can move from memory to memory
2118 in one reasonably fast instruction. */
2122 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2124 /* Define if operations between registers always perform the operation
2125 on the full register even if a narrower mode is specified. */
2126 #define WORD_REGISTER_OPERATIONS
2128 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2129 will either zero-extend or sign-extend. The value of this macro should
2130 be the code that says which one of the two operations is implicitly
2131 done, NIL if none. */
2132 #define LOAD_EXTEND_OP(MODE) \
2133 (TARGET_THUMB ? ZERO_EXTEND : \
2134 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2135 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2137 /* Nonzero if access to memory by bytes is slow and undesirable. */
2138 #define SLOW_BYTE_ACCESS 0
2140 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2142 /* Immediate shift counts are truncated by the output routines (or was it
2143 the assembler?). Shift counts in a register are truncated by ARM. Note
2144 that the native compiler puts too large (> 32) immediate shift counts
2145 into a register and shifts by the register, letting the ARM decide what
2146 to do instead of doing that itself. */
2147 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2148 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2149 On the arm, Y in a register is used modulo 256 for the shift. Only for
2150 rotates is modulo 32 used. */
2151 /* #define SHIFT_COUNT_TRUNCATED 1 */
2153 /* All integers have the same format so truncation is easy. */
2154 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2156 /* Calling from registers is a massive pain. */
2157 #define NO_FUNCTION_CSE 1
2159 /* Chars and shorts should be passed as ints. */
2160 #define PROMOTE_PROTOTYPES 1
2162 /* The machine modes of pointers and functions */
2163 #define Pmode SImode
2164 #define FUNCTION_MODE Pmode
2166 #define ARM_FRAME_RTX(X) \
2167 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2168 || (X) == arg_pointer_rtx)
2170 /* Moves to and from memory are quite expensive */
2171 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2172 (TARGET_ARM ? 10 : \
2173 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2174 * (CLASS == LO_REGS ? 1 : 2)))
2176 /* Try to generate sequences that don't involve branches, we can then use
2177 conditional instructions */
2178 #define BRANCH_COST \
2179 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2181 /* Position Independent Code. */
2182 /* We decide which register to use based on the compilation options and
2183 the assembler in use; this is more general than the APCS restriction of
2184 using sb (r9) all the time. */
2185 extern int arm_pic_register;
2187 /* Used when parsing command line option -mpic-register=. */
2188 extern const char * arm_pic_register_string;
2190 /* The register number of the register used to address a table of static
2191 data addresses in memory. */
2192 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2194 #define FINALIZE_PIC arm_finalize_pic (1)
2196 /* We can't directly access anything that contains a symbol,
2197 nor can we indirect via the constant pool. */
2198 #define LEGITIMATE_PIC_OPERAND_P(X) \
2199 (!(symbol_mentioned_p (X) \
2200 || label_mentioned_p (X) \
2201 || (GET_CODE (X) == SYMBOL_REF \
2202 && CONSTANT_POOL_ADDRESS_P (X) \
2203 && (symbol_mentioned_p (get_pool_constant (X)) \
2204 || label_mentioned_p (get_pool_constant (X))))))
2206 /* We need to know when we are making a constant pool; this determines
2207 whether data needs to be in the GOT or can be referenced via a GOT
2209 extern int making_const_table;
2211 /* Handle pragmas for compatibility with Intel's compilers. */
2212 #define REGISTER_TARGET_PRAGMAS() do { \
2213 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2214 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2215 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2218 /* Condition code information. */
2219 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2220 return the mode to be used for the comparison. */
2222 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2224 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2226 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2229 if (GET_CODE (OP1) == CONST_INT \
2230 && ! (const_ok_for_arm (INTVAL (OP1)) \
2231 || (const_ok_for_arm (- INTVAL (OP1))))) \
2233 rtx const_op = OP1; \
2234 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2240 #define STORE_FLAG_VALUE 1
2242 /* The arm5 clz instruction returns 32. */
2243 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2246 /* Gcc puts the pool in the wrong place for ARM, since we can only
2247 load addresses a limited distance around the pc. We do some
2248 special munging to move the constant pool values to the correct
2249 point in the code. */
2250 #define MACHINE_DEPENDENT_REORG(INSN) \
2254 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2256 /* Output a push or a pop instruction (only used when profiling). */
2257 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2259 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2260 STACK_POINTER_REGNUM, REGNO); \
2262 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2265 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2267 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2268 STACK_POINTER_REGNUM, REGNO); \
2270 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2272 /* This is how to output a label which precedes a jumptable. Since
2273 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2274 #undef ASM_OUTPUT_CASE_LABEL
2275 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2279 ASM_OUTPUT_ALIGN (FILE, 2); \
2280 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2284 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2289 if (is_called_in_ARM_mode (DECL)) \
2290 fprintf (STREAM, "\t.code 32\n") ; \
2292 fprintf (STREAM, "\t.thumb_func\n") ; \
2294 if (TARGET_POKE_FUNCTION_NAME) \
2295 arm_poke_function_name (STREAM, (char *) NAME); \
2299 /* For aliases of functions we use .thumb_set instead. */
2300 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2303 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2304 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2306 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2308 fprintf (FILE, "\t.thumb_set "); \
2309 assemble_name (FILE, LABEL1); \
2310 fprintf (FILE, ","); \
2311 assemble_name (FILE, LABEL2); \
2312 fprintf (FILE, "\n"); \
2315 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2319 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2320 /* To support -falign-* switches we need to use .p2align so
2321 that alignment directives in code sections will be padded
2322 with no-op instructions, rather than zeroes. */
2323 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2326 if ((MAX_SKIP) == 0) \
2327 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2329 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2330 (LOG), (MAX_SKIP)); \
2334 /* Only perform branch elimination (by making instructions conditional) if
2335 we're optimising. Otherwise it's of no use anyway. */
2336 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2337 if (TARGET_ARM && optimize) \
2338 arm_final_prescan_insn (INSN); \
2339 else if (TARGET_THUMB) \
2340 thumb_final_prescan_insn (INSN)
2342 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2343 (CODE == '@' || CODE == '|' \
2344 || (TARGET_ARM && (CODE == '?')) \
2345 || (TARGET_THUMB && (CODE == '_')))
2347 /* Output an operand of an instruction. */
2348 #define PRINT_OPERAND(STREAM, X, CODE) \
2349 arm_print_operand (STREAM, X, CODE)
2351 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2352 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2353 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2354 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2355 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2356 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2359 /* Output the address of an operand. */
2360 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2362 int is_minus = GET_CODE (X) == MINUS; \
2364 if (GET_CODE (X) == REG) \
2365 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2366 else if (GET_CODE (X) == PLUS || is_minus) \
2368 rtx base = XEXP (X, 0); \
2369 rtx index = XEXP (X, 1); \
2370 HOST_WIDE_INT offset = 0; \
2371 if (GET_CODE (base) != REG) \
2373 /* Ensure that BASE is a register */ \
2374 /* (one of them must be). */ \
2379 switch (GET_CODE (index)) \
2382 offset = INTVAL (index); \
2385 asm_fprintf (STREAM, "[%r, #%d]", \
2386 REGNO (base), offset); \
2390 asm_fprintf (STREAM, "[%r, %s%r]", \
2391 REGNO (base), is_minus ? "-" : "", \
2401 asm_fprintf (STREAM, "[%r, %s%r", \
2402 REGNO (base), is_minus ? "-" : "", \
2403 REGNO (XEXP (index, 0))); \
2404 arm_print_operand (STREAM, index, 'S'); \
2405 fputs ("]", STREAM); \
2413 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2414 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2416 extern enum machine_mode output_memory_reference_mode; \
2418 if (GET_CODE (XEXP (X, 0)) != REG) \
2421 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2422 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2423 REGNO (XEXP (X, 0)), \
2424 GET_CODE (X) == PRE_DEC ? "-" : "", \
2425 GET_MODE_SIZE (output_memory_reference_mode)); \
2427 asm_fprintf (STREAM, "[%r], #%s%d", \
2428 REGNO (XEXP (X, 0)), \
2429 GET_CODE (X) == POST_DEC ? "-" : "", \
2430 GET_MODE_SIZE (output_memory_reference_mode)); \
2432 else if (GET_CODE (X) == PRE_MODIFY) \
2434 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2435 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2436 asm_fprintf (STREAM, "#%d]!", \
2437 INTVAL (XEXP (XEXP (X, 1), 1))); \
2439 asm_fprintf (STREAM, "%r]!", \
2440 REGNO (XEXP (XEXP (X, 1), 1))); \
2442 else if (GET_CODE (X) == POST_MODIFY) \
2444 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2445 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2446 asm_fprintf (STREAM, "#%d", \
2447 INTVAL (XEXP (XEXP (X, 1), 1))); \
2449 asm_fprintf (STREAM, "%r", \
2450 REGNO (XEXP (XEXP (X, 1), 1))); \
2452 else output_addr_const (STREAM, X); \
2455 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2457 if (GET_CODE (X) == REG) \
2458 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2459 else if (GET_CODE (X) == POST_INC) \
2460 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2461 else if (GET_CODE (X) == PLUS) \
2463 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2464 asm_fprintf (STREAM, "[%r, #%d]", \
2465 REGNO (XEXP (X, 0)), \
2466 (int) INTVAL (XEXP (X, 1))); \
2468 asm_fprintf (STREAM, "[%r, %r]", \
2469 REGNO (XEXP (X, 0)), \
2470 REGNO (XEXP (X, 1))); \
2473 output_addr_const (STREAM, X); \
2476 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2478 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2480 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2482 /* A C expression whose value is RTL representing the value of the return
2483 address for the frame COUNT steps up from the current frame. */
2485 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2486 arm_return_addr (COUNT, FRAME)
2488 /* Mask of the bits in the PC that contain the real return address
2489 when running in 26-bit mode. */
2490 #define RETURN_ADDR_MASK26 (0x03fffffc)
2492 /* Pick up the return address upon entry to a procedure. Used for
2493 dwarf2 unwind information. This also enables the table driven
2495 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2496 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2498 /* Used to mask out junk bits from the return address, such as
2499 processor state, interrupt status, condition codes and the like. */
2500 #define MASK_RETURN_ADDR \
2501 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2502 in 26 bit mode, the condition codes must be masked out of the \
2503 return address. This does not apply to ARM6 and later processors \
2504 when running in 32 bit mode. */ \
2505 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2506 : (arm_arch4 || TARGET_THUMB) ? \
2507 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2508 : arm_gen_return_addr_mask ())
2511 /* Define the codes that are matched by predicates in arm.c */
2512 #define PREDICATE_CODES \
2513 {"s_register_operand", {SUBREG, REG}}, \
2514 {"arm_hard_register_operand", {REG}}, \
2515 {"f_register_operand", {SUBREG, REG}}, \
2516 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2517 {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2518 {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2519 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2520 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2521 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2522 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2523 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2524 {"offsettable_memory_operand", {MEM}}, \
2525 {"bad_signed_byte_operand", {MEM}}, \
2526 {"alignable_memory_operand", {MEM}}, \
2527 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2528 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2529 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2530 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2531 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2532 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2533 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2534 {"load_multiple_operation", {PARALLEL}}, \
2535 {"store_multiple_operation", {PARALLEL}}, \
2536 {"equality_operator", {EQ, NE}}, \
2537 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2538 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2540 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2541 {"const_shift_operand", {CONST_INT}}, \
2542 {"multi_register_push", {PARALLEL}}, \
2543 {"cc_register", {REG}}, \
2544 {"logical_binary_operator", {AND, IOR, XOR}}, \
2545 {"cirrus_register_operand", {REG}}, \
2546 {"cirrus_fp_register", {REG}}, \
2547 {"cirrus_shift_const", {CONST_INT}}, \
2548 {"dominant_cc_register", {REG}},
2550 /* Define this if you have special predicates that know special things
2551 about modes. Genrecog will warn about certain forms of
2552 match_operand without a mode; if the operand predicate is listed in
2553 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2554 #define SPECIAL_MODE_PREDICATES \
2555 "cc_register", "dominant_cc_register",
2557 #endif /* ! GCC_ARM_H */
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