1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
69 builtin_define ("__ARM_NEON__"); \
71 /* Add a define for interworking. \
72 Needed when building libgcc.a. */ \
73 if (arm_cpp_interwork) \
74 builtin_define ("__THUMB_INTERWORK__"); \
76 builtin_assert ("cpu=arm"); \
77 builtin_assert ("machine=arm"); \
79 builtin_define (arm_arch_name); \
80 if (arm_arch_cirrus) \
81 builtin_define ("__MAVERICK__"); \
82 if (arm_arch_xscale) \
83 builtin_define ("__XSCALE__"); \
84 if (arm_arch_iwmmxt) \
85 builtin_define ("__IWMMXT__"); \
86 if (TARGET_AAPCS_BASED) \
87 builtin_define ("__ARM_EABI__"); \
90 /* The various ARM cores. */
93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
95 #include "arm-cores.def"
97 /* Used to indicate that no processor has been specified. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
110 /* The processor for which instructions should be scheduled. */
111 extern enum processor_type arm_tune;
113 typedef enum arm_cond_code
115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
120 extern arm_cc arm_current_cc;
122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
124 extern int arm_target_label;
125 extern int arm_ccfsm_state;
126 extern GTY(()) rtx arm_target_insn;
127 /* Define the information needed to generate branch insns. This is
128 stored from the compare operation. */
129 extern GTY(()) rtx arm_compare_op0;
130 extern GTY(()) rtx arm_compare_op1;
131 /* The label of the current constant pool. */
132 extern rtx pool_vector_label;
133 /* Set to 1 when a return insn is output, this means that the epilogue
135 extern int return_used_this_function;
136 /* Callback to output language specific object attributes. */
137 extern void (*arm_lang_output_object_attributes_hook)(void);
139 /* Just in case configure has failed to define anything. */
140 #ifndef TARGET_CPU_DEFAULT
141 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
146 #define CPP_SPEC "%(subtarget_cpp_spec) \
147 %{msoft-float:%{mhard-float: \
148 %e-msoft-float and -mhard_float may not be used together}} \
149 %{mbig-endian:%{mlittle-endian: \
150 %e-mbig-endian and -mlittle-endian may not be used together}}"
156 /* This macro defines names of additional specifications to put in the specs
157 that can be used in various specifications like CC1_SPEC. Its definition
158 is an initializer with a subgrouping for each command option.
160 Each subgrouping contains a string constant, that defines the
161 specification name, and a string constant that used by the GCC driver
164 Do not define this macro if it does not need to do anything. */
165 #define EXTRA_SPECS \
166 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
167 SUBTARGET_EXTRA_SPECS
169 #ifndef SUBTARGET_EXTRA_SPECS
170 #define SUBTARGET_EXTRA_SPECS
173 #ifndef SUBTARGET_CPP_SPEC
174 #define SUBTARGET_CPP_SPEC ""
177 /* Run-time Target Specification. */
178 #ifndef TARGET_VERSION
179 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
182 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
183 /* Use hardware floating point instructions. */
184 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
185 /* Use hardware floating point calling convention. */
186 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
187 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
188 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
189 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
190 #define TARGET_IWMMXT (arm_arch_iwmmxt)
191 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
192 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
193 #define TARGET_ARM (! TARGET_THUMB)
194 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
195 #define TARGET_BACKTRACE (leaf_function_p () \
196 ? TARGET_TPCS_LEAF_FRAME \
198 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
199 #define TARGET_AAPCS_BASED \
200 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
202 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
203 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
205 /* Only 16-bit thumb code. */
206 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
207 /* Arm or Thumb-2 32-bit code. */
208 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
209 /* 32-bit Thumb-2 code. */
210 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
212 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
214 /* The following two macros concern the ability to execute coprocessor
215 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
216 only ever tested when we know we are generating for VFP hardware; we need
217 to be more careful with TARGET_NEON as noted below. */
219 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
220 #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \
221 && (arm_fpu_arch == FPUTYPE_VFP3 \
222 || arm_fpu_arch == FPUTYPE_NEON))
224 /* FPU supports VFPv3 instructions. */
225 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
226 && (arm_fpu_arch == FPUTYPE_VFP3D16 \
229 /* FPU supports Neon instructions. The setting of this macro gets
230 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
231 and TARGET_HARD_FLOAT to ensure that NEON instructions are
233 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
234 && arm_fp_model == ARM_FP_MODEL_VFP \
235 && arm_fpu_arch == FPUTYPE_NEON)
237 /* "DSP" multiply instructions, eg. SMULxy. */
238 #define TARGET_DSP_MULTIPLY \
239 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
240 /* Integer SIMD instructions, and extend-accumulate instructions. */
241 #define TARGET_INT_SIMD \
242 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
244 /* Should MOVW/MOVT be used in preference to a constant pool. */
245 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
247 /* We could use unified syntax for arm mode, but for now we just use it
249 #define TARGET_UNIFIED_ASM TARGET_THUMB2
252 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
253 then TARGET_AAPCS_BASED must be true -- but the converse does not
254 hold. TARGET_BPABI implies the use of the BPABI runtime library,
255 etc., in addition to just the AAPCS calling conventions. */
257 #define TARGET_BPABI false
260 /* Support for a compile-time default CPU, et cetera. The rules are:
261 --with-arch is ignored if -march or -mcpu are specified.
262 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
264 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
266 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
268 --with-fpu is ignored if -mfpu is specified.
269 --with-abi is ignored is -mabi is specified. */
270 #define OPTION_DEFAULT_SPECS \
271 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
272 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
273 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
275 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
276 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
277 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
278 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
280 /* Which floating point model to use. */
283 ARM_FP_MODEL_UNKNOWN,
284 /* FPA model (Hardware or software). */
286 /* Cirrus Maverick floating point model. */
287 ARM_FP_MODEL_MAVERICK,
288 /* VFP floating point model. */
292 extern enum arm_fp_model arm_fp_model;
294 /* Which floating point hardware is available. Also update
295 fp_model_for_fpu in arm.c when adding entries to this list. */
298 /* No FP hardware. */
300 /* Full FPA support. */
302 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
304 /* Emulated FPA hardware, Issue 3 emulator. */
306 /* Cirrus Maverick floating point co-processor. */
318 /* Recast the floating point class to be the floating point attribute. */
319 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
321 /* What type of floating point to tune for */
322 extern enum fputype arm_fpu_tune;
324 /* What type of floating point instructions are available */
325 extern enum fputype arm_fpu_arch;
330 ARM_FLOAT_ABI_SOFTFP,
334 extern enum float_abi_type arm_float_abi;
336 #ifndef TARGET_DEFAULT_FLOAT_ABI
337 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
340 /* Which ABI to use. */
350 extern enum arm_abi_type arm_abi;
352 #ifndef ARM_DEFAULT_ABI
353 #define ARM_DEFAULT_ABI ARM_ABI_APCS
356 /* Which thread pointer access sequence to use. */
363 extern enum arm_tp_type target_thread_pointer;
365 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
366 extern int arm_arch3m;
368 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
369 extern int arm_arch4;
371 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
372 extern int arm_arch4t;
374 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
375 extern int arm_arch5;
377 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
378 extern int arm_arch5e;
380 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
381 extern int arm_arch6;
383 /* Nonzero if instructions not present in the 'M' profile can be used. */
384 extern int arm_arch_notm;
386 /* Nonzero if this chip can benefit from load scheduling. */
387 extern int arm_ld_sched;
389 /* Nonzero if generating thumb code. */
390 extern int thumb_code;
392 /* Nonzero if this chip is a StrongARM. */
393 extern int arm_tune_strongarm;
395 /* Nonzero if this chip is a Cirrus variant. */
396 extern int arm_arch_cirrus;
398 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
399 extern int arm_arch_iwmmxt;
401 /* Nonzero if this chip is an XScale. */
402 extern int arm_arch_xscale;
404 /* Nonzero if tuning for XScale. */
405 extern int arm_tune_xscale;
407 /* Nonzero if tuning for stores via the write buffer. */
408 extern int arm_tune_wbuf;
410 /* Nonzero if tuning for Cortex-A9. */
411 extern int arm_tune_cortex_a9;
413 /* Nonzero if we should define __THUMB_INTERWORK__ in the
415 XXX This is a bit of a hack, it's intended to help work around
416 problems in GLD which doesn't understand that armv5t code is
417 interworking clean. */
418 extern int arm_cpp_interwork;
420 /* Nonzero if chip supports Thumb 2. */
421 extern int arm_arch_thumb2;
423 /* Nonzero if chip supports integer division instruction. */
424 extern int arm_arch_hwdiv;
426 #ifndef TARGET_DEFAULT
427 #define TARGET_DEFAULT (MASK_APCS_FRAME)
430 /* The frame pointer register used in gcc has nothing to do with debugging;
431 that is controlled by the APCS-FRAME option. */
432 #define CAN_DEBUG_WITHOUT_FP
434 #define OVERRIDE_OPTIONS arm_override_options ()
436 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
437 arm_optimization_options ((LEVEL), (SIZE))
439 /* Nonzero if PIC code requires explicit qualifiers to generate
440 PLT and GOT relocs rather than the assembler doing so implicitly.
441 Subtargets can override these if required. */
442 #ifndef NEED_GOT_RELOC
443 #define NEED_GOT_RELOC 0
445 #ifndef NEED_PLT_RELOC
446 #define NEED_PLT_RELOC 0
449 /* Nonzero if we need to refer to the GOT with a PC-relative
450 offset. In other words, generate
452 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
456 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
458 The default is true, which matches NetBSD. Subtargets can
459 override this if required. */
464 /* Target machine storage Layout. */
467 /* Define this macro if it is advisable to hold scalars in registers
468 in a wider mode than that declared by the program. In such cases,
469 the value is constrained to be within the bounds of the declared
470 type, but kept valid in the wider mode. The signedness of the
471 extension may differ from that of the type. */
473 /* It is far faster to zero extend chars than to sign extend them */
475 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
476 if (GET_MODE_CLASS (MODE) == MODE_INT \
477 && GET_MODE_SIZE (MODE) < 4) \
479 if (MODE == QImode) \
481 else if (MODE == HImode) \
486 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
487 if ((GET_MODE_CLASS (MODE) == MODE_INT \
488 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
489 && GET_MODE_SIZE (MODE) < 4) \
492 /* Define this if most significant bit is lowest numbered
493 in instructions that operate on numbered bit-fields. */
494 #define BITS_BIG_ENDIAN 0
496 /* Define this if most significant byte of a word is the lowest numbered.
497 Most ARM processors are run in little endian mode, so that is the default.
498 If you want to have it run-time selectable, change the definition in a
499 cover file to be TARGET_BIG_ENDIAN. */
500 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
502 /* Define this if most significant word of a multiword number is the lowest
504 This is always false, even when in big-endian mode. */
505 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
507 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
508 on processor pre-defineds when compiling libgcc2.c. */
509 #if defined(__ARMEB__) && !defined(__ARMWEL__)
510 #define LIBGCC2_WORDS_BIG_ENDIAN 1
512 #define LIBGCC2_WORDS_BIG_ENDIAN 0
515 /* Define this if most significant word of doubles is the lowest numbered.
516 The rules are different based on whether or not we use FPA-format,
517 VFP-format or some other floating point co-processor's format doubles. */
518 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
520 #define UNITS_PER_WORD 4
522 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
523 registers when autovectorizing for Neon, at least until multiple vector
524 widths are supported properly by the middle-end. */
525 #define UNITS_PER_SIMD_WORD(MODE) \
526 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
528 /* True if natural alignment is used for doubleword types. */
529 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
531 #define DOUBLEWORD_ALIGNMENT 64
533 #define PARM_BOUNDARY 32
535 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
537 #define PREFERRED_STACK_BOUNDARY \
538 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
540 #define FUNCTION_BOUNDARY 32
542 /* The lowest bit is used to indicate Thumb-mode functions, so the
543 vbit must go into the delta field of pointers to member
545 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
547 #define EMPTY_FIELD_BOUNDARY 32
549 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
551 /* XXX Blah -- this macro is used directly by libobjc. Since it
552 supports no vector modes, cut out the complexity and fall back
553 on BIGGEST_FIELD_ALIGNMENT. */
554 #ifdef IN_TARGET_LIBS
555 #define BIGGEST_FIELD_ALIGNMENT 64
558 /* Make strings word-aligned so strcpy from constants will be faster. */
559 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
561 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
562 ((TREE_CODE (EXP) == STRING_CST \
564 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
565 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
567 /* Align definitions of arrays, unions and structures so that
568 initializations and copies can be made more efficient. This is not
569 ABI-changing, so it only affects places where we can see the
571 #define DATA_ALIGNMENT(EXP, ALIGN) \
572 ((((ALIGN) < BITS_PER_WORD) \
573 && (TREE_CODE (EXP) == ARRAY_TYPE \
574 || TREE_CODE (EXP) == UNION_TYPE \
575 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
577 /* Similarly, make sure that objects on the stack are sensibly aligned. */
578 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
580 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
581 value set in previous versions of this toolchain was 8, which produces more
582 compact structures. The command line option -mstructure_size_boundary=<n>
583 can be used to change this value. For compatibility with the ARM SDK
584 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
585 0020D) page 2-20 says "Structures are aligned on word boundaries".
586 The AAPCS specifies a value of 8. */
587 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
588 extern int arm_structure_size_boundary;
590 /* This is the value used to initialize arm_structure_size_boundary. If a
591 particular arm target wants to change the default value it should change
592 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
593 for an example of this. */
594 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
595 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
598 /* Nonzero if move instructions will actually fail to work
599 when given unaligned data. */
600 #define STRICT_ALIGNMENT 1
602 /* wchar_t is unsigned under the AAPCS. */
604 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
606 #define WCHAR_TYPE_SIZE BITS_PER_WORD
610 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
614 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
617 /* AAPCS requires that structure alignment is affected by bitfields. */
618 #ifndef PCC_BITFIELD_TYPE_MATTERS
619 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
623 /* Standard register usage. */
625 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
626 (S - saved over call).
628 r0 * argument word/integer result
631 r4-r8 S register variable
632 r9 S (rfp) register variable (real frame pointer)
634 r10 F S (sl) stack limit (used by -mapcs-stack-check)
635 r11 F S (fp) argument pointer
636 r12 (ip) temp workspace
637 r13 F S (sp) lower end of current stack frame
638 r14 (lr) link address/workspace
639 r15 F (pc) program counter
641 f0 floating point result
642 f1-f3 floating point scratch
644 f4-f7 S floating point variable
646 cc This is NOT a real register, but is used internally
647 to represent things that use or set the condition
649 sfp This isn't either. It is used during rtl generation
650 since the offset between the frame pointer and the
651 auto's isn't known until after register allocation.
652 afp Nor this, we only need this because of non-local
653 goto. Without it fp appears to be used and the
654 elimination code won't get rid of sfp. It tracks
655 fp exactly at all times.
657 *: See CONDITIONAL_REGISTER_USAGE */
660 mvf0 Cirrus floating point result
661 mvf1-mvf3 Cirrus floating point scratch
662 mvf4-mvf15 S Cirrus floating point variable. */
664 /* s0-s15 VFP scratch (aka d0-d7).
665 s16-s31 S VFP variable (aka d8-d15).
666 vfpcc Not a real register. Represents the VFP condition
669 /* The stack backtrace structure is as follows:
670 fp points to here: | save code pointer | [fp]
671 | return link value | [fp, #-4]
672 | return sp value | [fp, #-8]
673 | return fp value | [fp, #-12]
674 [| saved r10 value |]
685 [| saved f7 value |] three words
686 [| saved f6 value |] three words
687 [| saved f5 value |] three words
688 [| saved f4 value |] three words
689 r0-r3 are not normally saved in a C function. */
691 /* 1 for registers that have pervasive standard uses
692 and are not available for the register allocator. */
693 #define FIXED_REGISTERS \
715 /* 1 for registers not available across function calls.
716 These must include the FIXED_REGISTERS and also any
717 registers that can be used without being saved.
718 The latter must include the registers where values are returned
719 and the register where structure-value addresses are passed.
720 Aside from that, you can include as many other registers as you like.
721 The CC is not preserved over function calls on the ARM 6, so it is
722 easier to assume this for all. SFP is preserved, since FP is. */
723 #define CALL_USED_REGISTERS \
745 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
746 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
749 #define CONDITIONAL_REGISTER_USAGE \
753 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
755 for (regno = FIRST_FPA_REGNUM; \
756 regno <= LAST_FPA_REGNUM; ++regno) \
757 fixed_regs[regno] = call_used_regs[regno] = 1; \
760 if (TARGET_THUMB && optimize_size) \
762 /* When optimizing for size, it's better not to use \
763 the HI regs, because of the overhead of stacking \
765 /* ??? Is this still true for thumb2? */ \
766 for (regno = FIRST_HI_REGNUM; \
767 regno <= LAST_HI_REGNUM; ++regno) \
768 fixed_regs[regno] = call_used_regs[regno] = 1; \
771 /* The link register can be clobbered by any branch insn, \
772 but we have no way to track that at present, so mark \
773 it as unavailable. */ \
775 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
777 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
779 if (TARGET_MAVERICK) \
781 for (regno = FIRST_FPA_REGNUM; \
782 regno <= LAST_FPA_REGNUM; ++ regno) \
783 fixed_regs[regno] = call_used_regs[regno] = 1; \
784 for (regno = FIRST_CIRRUS_FP_REGNUM; \
785 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
787 fixed_regs[regno] = 0; \
788 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
793 /* VFPv3 registers are disabled when earlier VFP \
794 versions are selected due to the definition of \
795 LAST_VFP_REGNUM. */ \
796 for (regno = FIRST_VFP_REGNUM; \
797 regno <= LAST_VFP_REGNUM; ++ regno) \
799 fixed_regs[regno] = 0; \
800 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
801 || regno >= FIRST_VFP_REGNUM + 32; \
806 if (TARGET_REALLY_IWMMXT) \
808 regno = FIRST_IWMMXT_GR_REGNUM; \
809 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
810 and wCG1 as call-preserved registers. The 2002/11/21 \
811 revision changed this so that all wCG registers are \
812 scratch registers. */ \
813 for (regno = FIRST_IWMMXT_GR_REGNUM; \
814 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
815 fixed_regs[regno] = 0; \
816 /* The XScale ABI has wR0 - wR9 as scratch registers, \
817 the rest as call-preserved registers. */ \
818 for (regno = FIRST_IWMMXT_REGNUM; \
819 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
821 fixed_regs[regno] = 0; \
822 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
826 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
828 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
829 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
831 else if (TARGET_APCS_STACK) \
833 fixed_regs[10] = 1; \
834 call_used_regs[10] = 1; \
836 /* -mcaller-super-interworking reserves r11 for calls to \
837 _interwork_r11_call_via_rN(). Making the register global \
838 is an easy way of ensuring that it remains valid for all \
840 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
841 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
843 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
844 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
845 if (TARGET_CALLER_INTERWORKING) \
846 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
848 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
851 /* These are a couple of extensions to the formats accepted
853 %@ prints out ASM_COMMENT_START
854 %r prints out REGISTER_PREFIX reg_names[arg] */
855 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
857 fputs (ASM_COMMENT_START, FILE); \
861 fputs (REGISTER_PREFIX, FILE); \
862 fputs (reg_names [va_arg (ARGS, int)], FILE); \
865 /* Round X up to the nearest word. */
866 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
868 /* Convert fron bytes to ints. */
869 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
871 /* The number of (integer) registers required to hold a quantity of type MODE.
872 Also used for VFP registers. */
873 #define ARM_NUM_REGS(MODE) \
874 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
876 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
877 #define ARM_NUM_REGS2(MODE, TYPE) \
878 ARM_NUM_INTS ((MODE) == BLKmode ? \
879 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
881 /* The number of (integer) argument register available. */
882 #define NUM_ARG_REGS 4
884 /* Return the register number of the N'th (integer) argument. */
885 #define ARG_REGISTER(N) (N - 1)
887 /* Specify the registers used for certain standard purposes.
888 The values of these macros are register numbers. */
890 /* The number of the last argument register. */
891 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
893 /* The numbers of the Thumb register ranges. */
894 #define FIRST_LO_REGNUM 0
895 #define LAST_LO_REGNUM 7
896 #define FIRST_HI_REGNUM 8
897 #define LAST_HI_REGNUM 11
899 #ifndef TARGET_UNWIND_INFO
900 /* We use sjlj exceptions for backwards compatibility. */
901 #define MUST_USE_SJLJ_EXCEPTIONS 1
904 /* We can generate DWARF2 Unwind info, even though we don't use it. */
905 #define DWARF2_UNWIND_INFO 1
907 /* Use r0 and r1 to pass exception handling information. */
908 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
910 /* The register that holds the return address in exception handlers. */
911 #define ARM_EH_STACKADJ_REGNUM 2
912 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
914 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
915 as an invisible last argument (possible since varargs don't exist in
916 Pascal), so the following is not true. */
917 #define STATIC_CHAIN_REGNUM 12
919 /* Define this to be where the real frame pointer is if it is not possible to
920 work out the offset between the frame pointer and the automatic variables
921 until after register allocation has taken place. FRAME_POINTER_REGNUM
922 should point to a special register that we will make sure is eliminated.
924 For the Thumb we have another problem. The TPCS defines the frame pointer
925 as r11, and GCC believes that it is always possible to use the frame pointer
926 as base register for addressing purposes. (See comments in
927 find_reloads_address()). But - the Thumb does not allow high registers,
928 including r11, to be used as base address registers. Hence our problem.
930 The solution used here, and in the old thumb port is to use r7 instead of
931 r11 as the hard frame pointer and to have special code to generate
932 backtrace structures on the stack (if required to do so via a command line
933 option) using r11. This is the only 'user visible' use of r11 as a frame
935 #define ARM_HARD_FRAME_POINTER_REGNUM 11
936 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
938 #define HARD_FRAME_POINTER_REGNUM \
940 ? ARM_HARD_FRAME_POINTER_REGNUM \
941 : THUMB_HARD_FRAME_POINTER_REGNUM)
943 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
945 /* Register to use for pushing function arguments. */
946 #define STACK_POINTER_REGNUM SP_REGNUM
948 /* ARM floating pointer registers. */
949 #define FIRST_FPA_REGNUM 16
950 #define LAST_FPA_REGNUM 23
951 #define IS_FPA_REGNUM(REGNUM) \
952 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
954 #define FIRST_IWMMXT_GR_REGNUM 43
955 #define LAST_IWMMXT_GR_REGNUM 46
956 #define FIRST_IWMMXT_REGNUM 47
957 #define LAST_IWMMXT_REGNUM 62
958 #define IS_IWMMXT_REGNUM(REGNUM) \
959 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
960 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
961 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
963 /* Base register for access to local variables of the function. */
964 #define FRAME_POINTER_REGNUM 25
966 /* Base register for access to arguments of the function. */
967 #define ARG_POINTER_REGNUM 26
969 #define FIRST_CIRRUS_FP_REGNUM 27
970 #define LAST_CIRRUS_FP_REGNUM 42
971 #define IS_CIRRUS_REGNUM(REGNUM) \
972 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
974 #define FIRST_VFP_REGNUM 63
975 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
976 #define LAST_VFP_REGNUM \
977 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
979 #define IS_VFP_REGNUM(REGNUM) \
980 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
982 /* VFP registers are split into two types: those defined by VFP versions < 3
983 have D registers overlaid on consecutive pairs of S registers. VFP version 3
984 defines 16 new D registers (d16-d31) which, for simplicity and correctness
985 in various parts of the backend, we implement as "fake" single-precision
986 registers (which would be S32-S63, but cannot be used in that way). The
987 following macros define these ranges of registers. */
988 #define LAST_LO_VFP_REGNUM 94
989 #define FIRST_HI_VFP_REGNUM 95
990 #define LAST_HI_VFP_REGNUM 126
992 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
993 ((REGNUM) <= LAST_LO_VFP_REGNUM)
995 /* DFmode values are only valid in even register pairs. */
996 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
997 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
999 /* Neon Quad values must start at a multiple of four registers. */
1000 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1001 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1003 /* Neon structures of vectors must be in even register pairs and there
1004 must be enough registers available. Because of various patterns
1005 requiring quad registers, we require them to start at a multiple of
1007 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1008 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1009 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1011 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1012 /* + 16 Cirrus registers take us up to 43. */
1013 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1014 /* VFP (VFP3) adds 32 (64) + 1 more. */
1015 #define FIRST_PSEUDO_REGISTER 128
1017 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1019 /* Value should be nonzero if functions must have frame pointers.
1020 Zero means the frame pointer need not be set up (and parms may be accessed
1021 via the stack pointer) in functions that seem suitable.
1022 If we have to have a frame pointer we might as well make use of it.
1023 APCS says that the frame pointer does not need to be pushed in leaf
1024 functions, or simple tail call functions. */
1026 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1027 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1030 #define FRAME_POINTER_REQUIRED \
1031 (cfun->has_nonlocal_label \
1032 || SUBTARGET_FRAME_POINTER_REQUIRED \
1033 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1035 /* Return number of consecutive hard regs needed starting at reg REGNO
1036 to hold something of mode MODE.
1037 This is ordinarily the length in words of a value of mode MODE
1038 but can be less for certain modes in special long registers.
1040 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1042 #define HARD_REGNO_NREGS(REGNO, MODE) \
1044 && REGNO >= FIRST_FPA_REGNUM \
1045 && REGNO != FRAME_POINTER_REGNUM \
1046 && REGNO != ARG_POINTER_REGNUM) \
1047 && !IS_VFP_REGNUM (REGNO) \
1048 ? 1 : ARM_NUM_REGS (MODE))
1050 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1051 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1052 arm_hard_regno_mode_ok ((REGNO), (MODE))
1054 /* Value is 1 if it is a good idea to tie two pseudo registers
1055 when one has mode MODE1 and one has mode MODE2.
1056 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1057 for any hard reg, then this must be 0 for correct output. */
1058 #define MODES_TIEABLE_P(MODE1, MODE2) \
1059 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1061 #define VALID_IWMMXT_REG_MODE(MODE) \
1062 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1064 /* Modes valid for Neon D registers. */
1065 #define VALID_NEON_DREG_MODE(MODE) \
1066 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1067 || (MODE) == V2SFmode || (MODE) == DImode)
1069 /* Modes valid for Neon Q registers. */
1070 #define VALID_NEON_QREG_MODE(MODE) \
1071 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1072 || (MODE) == V4SFmode || (MODE) == V2DImode)
1074 /* Structure modes valid for Neon registers. */
1075 #define VALID_NEON_STRUCT_MODE(MODE) \
1076 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1077 || (MODE) == CImode || (MODE) == XImode)
1079 /* The order in which register should be allocated. It is good to use ip
1080 since no saving is required (though calls clobber it) and it never contains
1081 function parameters. It is quite good to use lr since other calls may
1082 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1083 least likely to contain a function parameter; in addition results are
1085 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1086 then D8-D15. The reason for doing this is to attempt to reduce register
1087 pressure when both single- and double-precision registers are used in a
1090 #define REG_ALLOC_ORDER \
1092 3, 2, 1, 0, 12, 14, 4, 5, \
1093 6, 7, 8, 10, 9, 11, 13, 15, \
1094 16, 17, 18, 19, 20, 21, 22, 23, \
1095 27, 28, 29, 30, 31, 32, 33, 34, \
1096 35, 36, 37, 38, 39, 40, 41, 42, \
1097 43, 44, 45, 46, 47, 48, 49, 50, \
1098 51, 52, 53, 54, 55, 56, 57, 58, \
1101 95, 96, 97, 98, 99, 100, 101, 102, \
1102 103, 104, 105, 106, 107, 108, 109, 110, \
1103 111, 112, 113, 114, 115, 116, 117, 118, \
1104 119, 120, 121, 122, 123, 124, 125, 126, \
1105 78, 77, 76, 75, 74, 73, 72, 71, \
1106 70, 69, 68, 67, 66, 65, 64, 63, \
1107 79, 80, 81, 82, 83, 84, 85, 86, \
1108 87, 88, 89, 90, 91, 92, 93, 94, \
1112 /* Use different register alloc ordering for Thumb. */
1113 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
1115 /* Interrupt functions can only use registers that have already been
1116 saved by the prologue, even if they would normally be
1118 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1119 (! IS_INTERRUPT (cfun->machine->func_type) || \
1120 df_regs_ever_live_p (DST))
1122 /* Register and constant classes. */
1124 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1125 Now that the Thumb is involved it has become more complicated. */
1149 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1151 /* Give names of register classes as strings for dump file. */
1152 #define REG_CLASS_NAMES \
1174 /* Define which registers fit in which classes.
1175 This is an initializer for a vector of HARD_REG_SET
1176 of length N_REG_CLASSES. */
1177 #define REG_CLASS_CONTENTS \
1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1180 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1181 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1182 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1183 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1184 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1185 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1186 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1187 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1188 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1189 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1190 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1191 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1192 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1193 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1194 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1195 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1196 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1199 /* Any of the VFP register classes. */
1200 #define IS_VFP_CLASS(X) \
1201 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1202 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1204 /* The same information, inverted:
1205 Return the class number of the smallest class containing
1206 reg number REGNO. This could be a conditional expression
1207 or could index an array. */
1208 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1210 /* The following macro defines cover classes for Integrated Register
1211 Allocator. Cover classes is a set of non-intersected register
1212 classes covering all hard registers used for register allocation
1213 purpose. Any move between two registers of a cover class should be
1214 cheaper than load or store of the registers. The macro value is
1215 array of register classes with LIM_REG_CLASSES used as the end
1218 #define IRA_COVER_CLASSES \
1220 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1224 /* FPA registers can't do subreg as all values are reformatted to internal
1225 precision. VFP registers may only be accessed in the mode they
1227 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1228 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1229 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1230 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1233 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1234 using r0-r4 for function arguments, r7 for the stack frame and don't
1235 have enough left over to do doubleword arithmetic. */
1236 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1237 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1238 || (CLASS) == CC_REG)
1240 /* The class value for index registers, and the one for base regs. */
1241 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1242 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1244 /* For the Thumb the high registers cannot be used as base registers
1245 when addressing quantities in QI or HI mode; if we don't know the
1246 mode, then we must be conservative. */
1247 #define MODE_BASE_REG_CLASS(MODE) \
1248 (TARGET_32BIT ? CORE_REGS : \
1249 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1251 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1252 instead of BASE_REGS. */
1253 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1255 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1256 registers explicitly used in the rtl to be used as spill registers
1257 but prevents the compiler from extending the lifetime of these
1259 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1261 /* Given an rtx X being reloaded into a reg required to be
1262 in class CLASS, return the class of reg to actually use.
1263 In general this is just CLASS, but for the Thumb core registers and
1264 immediate constants we prefer a LO_REGS class or a subset. */
1265 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1266 (TARGET_ARM ? (CLASS) : \
1267 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1268 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1269 ? LO_REGS : (CLASS)))
1271 /* Must leave BASE_REGS reloads alone */
1272 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1273 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1274 ? ((true_regnum (X) == -1 ? LO_REGS \
1275 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1279 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1280 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1281 ? ((true_regnum (X) == -1 ? LO_REGS \
1282 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1286 /* Return the register class of a scratch register needed to copy IN into
1287 or out of a register in CLASS in MODE. If it can be done directly,
1288 NO_REGS is returned. */
1289 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1290 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1291 ((TARGET_VFP && TARGET_HARD_FLOAT \
1292 && IS_VFP_CLASS (CLASS)) \
1293 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1294 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1295 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1297 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1298 ? GENERAL_REGS : NO_REGS) \
1299 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1301 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1302 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1303 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1304 ((TARGET_VFP && TARGET_HARD_FLOAT \
1305 && IS_VFP_CLASS (CLASS)) \
1306 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1307 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1308 coproc_secondary_reload_class (MODE, X, TRUE) : \
1309 /* Cannot load constants into Cirrus registers. */ \
1310 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1311 && (CLASS) == CIRRUS_REGS \
1312 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1315 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1316 && CONSTANT_P (X)) \
1318 (((MODE) == HImode && ! arm_arch4 \
1319 && (GET_CODE (X) == MEM \
1320 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1321 && true_regnum (X) == -1))) \
1322 ? GENERAL_REGS : NO_REGS) \
1323 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1325 /* Try a machine-dependent way of reloading an illegitimate address
1326 operand. If we find one, push the reload and jump to WIN. This
1327 macro is used in only one place: `find_reloads_address' in reload.c.
1329 For the ARM, we wish to handle large displacements off a base
1330 register by splitting the addend across a MOV and the mem insn.
1331 This can cut the number of reloads needed. */
1332 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1335 if (GET_CODE (X) == PLUS \
1336 && GET_CODE (XEXP (X, 0)) == REG \
1337 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1338 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1339 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1341 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1342 HOST_WIDE_INT low, high; \
1344 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1345 low = ((val & 0xf) ^ 0x8) - 0x8; \
1346 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1347 /* Need to be careful, -256 is not a valid offset. */ \
1348 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1349 else if (MODE == SImode \
1350 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1351 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1352 /* Need to be careful, -4096 is not a valid offset. */ \
1353 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1354 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1355 /* Need to be careful, -256 is not a valid offset. */ \
1356 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1357 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1358 && TARGET_HARD_FLOAT && TARGET_FPA) \
1359 /* Need to be careful, -1024 is not a valid offset. */ \
1360 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1364 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1365 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1366 - (unsigned HOST_WIDE_INT) 0x80000000); \
1367 /* Check for overflow or zero */ \
1368 if (low == 0 || high == 0 || (high + low != val)) \
1371 /* Reload the high part into a base reg; leave the low part \
1373 X = gen_rtx_PLUS (GET_MODE (X), \
1374 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1377 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1378 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1379 VOIDmode, 0, 0, OPNUM, TYPE); \
1385 /* XXX If an HImode FP+large_offset address is converted to an HImode
1386 SP+large_offset address, then reload won't know how to fix it. It sees
1387 only that SP isn't valid for HImode, and so reloads the SP into an index
1388 register, but the resulting address is still invalid because the offset
1389 is too big. We fix it here instead by reloading the entire address. */
1390 /* We could probably achieve better results by defining PROMOTE_MODE to help
1391 cope with the variances between the Thumb's signed and unsigned byte and
1392 halfword load instructions. */
1393 /* ??? This should be safe for thumb2, but we may be able to do better. */
1394 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1396 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1404 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1406 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1408 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1410 /* Return the maximum number of consecutive registers
1411 needed to represent mode MODE in a register of class CLASS.
1412 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1413 #define CLASS_MAX_NREGS(CLASS, MODE) \
1414 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1416 /* If defined, gives a class of registers that cannot be used as the
1417 operand of a SUBREG that changes the mode of the object illegally. */
1419 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1420 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1422 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1423 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1424 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1425 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1426 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1427 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1428 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1429 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1430 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1433 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1435 /* Stack layout; function entry, exit and calling. */
1437 /* Define this if pushing a word on the stack
1438 makes the stack pointer a smaller address. */
1439 #define STACK_GROWS_DOWNWARD 1
1441 /* Define this to nonzero if the nominal address of the stack frame
1442 is at the high-address end of the local variables;
1443 that is, each additional local variable allocated
1444 goes at a more negative offset in the frame. */
1445 #define FRAME_GROWS_DOWNWARD 1
1447 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1448 When present, it is one word in size, and sits at the top of the frame,
1449 between the soft frame pointer and either r7 or r11.
1451 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1452 and only then if some outgoing arguments are passed on the stack. It would
1453 be tempting to also check whether the stack arguments are passed by indirect
1454 calls, but there seems to be no reason in principle why a post-reload pass
1455 couldn't convert a direct call into an indirect one. */
1456 #define CALLER_INTERWORKING_SLOT_SIZE \
1457 (TARGET_CALLER_INTERWORKING \
1458 && crtl->outgoing_args_size != 0 \
1459 ? UNITS_PER_WORD : 0)
1461 /* Offset within stack frame to start allocating local variables at.
1462 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1463 first local allocated. Otherwise, it is the offset to the BEGINNING
1464 of the first local allocated. */
1465 #define STARTING_FRAME_OFFSET 0
1467 /* If we generate an insn to push BYTES bytes,
1468 this says how many the stack pointer really advances by. */
1469 /* The push insns do not do this rounding implicitly.
1470 So don't define this. */
1471 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1473 /* Define this if the maximum size of all the outgoing args is to be
1474 accumulated and pushed during the prologue. The amount can be
1475 found in the variable crtl->outgoing_args_size. */
1476 #define ACCUMULATE_OUTGOING_ARGS 1
1478 /* Offset of first parameter from the argument pointer register value. */
1479 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1481 /* Value is the number of byte of arguments automatically
1482 popped when returning from a subroutine call.
1483 FUNDECL is the declaration node of the function (as a tree),
1484 FUNTYPE is the data type of the function (as a tree),
1485 or for a library call it is an identifier node for the subroutine name.
1486 SIZE is the number of bytes of arguments passed on the stack.
1488 On the ARM, the caller does not pop any of its arguments that were passed
1490 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1492 /* Define how to find the value returned by a library function
1493 assuming the value has mode MODE. */
1494 #define LIBCALL_VALUE(MODE) \
1495 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1496 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1497 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1498 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1499 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1500 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1501 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1502 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1503 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1505 /* Define how to find the value returned by a function.
1506 VALTYPE is the data type of the value (as a tree).
1507 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1508 otherwise, FUNC is 0. */
1509 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1510 arm_function_value (VALTYPE, FUNC);
1512 /* 1 if N is a possible register number for a function value.
1513 On the ARM, only r0 and f0 can return results. */
1514 /* On a Cirrus chip, mvf0 can return results. */
1515 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1516 ((REGNO) == ARG_REGISTER (1) \
1517 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1518 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1519 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1520 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1521 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1523 /* Amount of memory needed for an untyped call to save all possible return
1525 #define APPLY_RESULT_SIZE arm_apply_result_size()
1527 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1528 values must be in memory. On the ARM, they need only do so if larger
1529 than a word, or if they contain elements offset from zero in the struct. */
1530 #define DEFAULT_PCC_STRUCT_RETURN 0
1532 /* These bits describe the different types of function supported
1533 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1534 normal function and an interworked function, for example. Knowing the
1535 type of a function is important for determining its prologue and
1537 Note value 7 is currently unassigned. Also note that the interrupt
1538 function types all have bit 2 set, so that they can be tested for easily.
1539 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1540 machine_function structure is initialized (to zero) func_type will
1541 default to unknown. This will force the first use of arm_current_func_type
1542 to call arm_compute_func_type. */
1543 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1544 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1545 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1546 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1547 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1548 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1550 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1552 /* In addition functions can have several type modifiers,
1553 outlined by these bit masks: */
1554 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1555 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1556 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1557 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1558 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1560 /* Some macros to test these flags. */
1561 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1562 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1563 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1564 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1565 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1566 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1569 /* Structure used to hold the function stack frame layout. Offsets are
1570 relative to the stack pointer on function entry. Positive offsets are
1571 in the direction of stack growth.
1572 Only soft_frame is used in thumb mode. */
1574 typedef struct arm_stack_offsets GTY(())
1576 int saved_args; /* ARG_POINTER_REGNUM. */
1577 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1579 int soft_frame; /* FRAME_POINTER_REGNUM. */
1580 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1581 int outgoing_args; /* STACK_POINTER_REGNUM. */
1582 unsigned int saved_regs_mask;
1586 /* A C structure for machine-specific, per-function data.
1587 This is added to the cfun structure. */
1588 typedef struct machine_function GTY(())
1590 /* Additional stack adjustment in __builtin_eh_throw. */
1591 rtx eh_epilogue_sp_ofs;
1592 /* Records if LR has to be saved for far jumps. */
1594 /* Records if ARG_POINTER was ever live. */
1595 int arg_pointer_live;
1596 /* Records if the save of LR has been eliminated. */
1597 int lr_save_eliminated;
1598 /* The size of the stack frame. Only valid after reload. */
1599 arm_stack_offsets stack_offsets;
1600 /* Records the type of the current function. */
1601 unsigned long func_type;
1602 /* Record if the function has a variable argument list. */
1603 int uses_anonymous_args;
1604 /* Records if sibcalls are blocked because an argument
1605 register is needed to preserve stack alignment. */
1606 int sibcall_blocked;
1607 /* The PIC register for this function. This might be a pseudo. */
1609 /* Labels for per-function Thumb call-via stubs. One per potential calling
1610 register. We can never call via LR or PC. We can call via SP if a
1611 trampoline happens to be on the top of the stack. */
1616 /* As in the machine_function, a global set of call-via labels, for code
1617 that is in text_section. */
1618 extern GTY(()) rtx thumb_call_via_label[14];
1620 /* A C type for declaring a variable that is used as the first argument of
1621 `FUNCTION_ARG' and other related values. For some target machines, the
1622 type `int' suffices and can hold the number of bytes of argument so far. */
1625 /* This is the number of registers of arguments scanned so far. */
1627 /* This is the number of iWMMXt register arguments scanned so far. */
1634 /* Define where to put the arguments to a function.
1635 Value is zero to push the argument on the stack,
1636 or a hard register in which to store the argument.
1638 MODE is the argument's machine mode.
1639 TYPE is the data type of the argument (as a tree).
1640 This is null for libcalls where that information may
1642 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1643 the preceding args and about the function being called.
1644 NAMED is nonzero if this argument is a named parameter
1645 (otherwise it is an extra parameter matching an ellipsis).
1647 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1648 other arguments are passed on the stack. If (NAMED == 0) (which happens
1649 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1650 defined), say it is passed in the stack (function_prologue will
1651 indeed make it pass in the stack if necessary). */
1652 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1653 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1655 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1656 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1658 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1659 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1661 /* For AAPCS, padding should never be below the argument. For other ABIs,
1662 * mimic the default. */
1663 #define PAD_VARARGS_DOWN \
1664 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1666 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1667 for a call to a function whose data type is FNTYPE.
1668 For a library call, FNTYPE is 0.
1669 On the ARM, the offset starts at 0. */
1670 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1671 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1673 /* Update the data in CUM to advance over an argument
1674 of mode MODE and data type TYPE.
1675 (TYPE is null for libcalls where that information may not be available.) */
1676 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1678 if (arm_vector_mode_supported_p (MODE) \
1679 && (CUM).named_count > (CUM).nargs \
1680 && TARGET_IWMMXT_ABI) \
1681 (CUM).iwmmxt_nregs += 1; \
1683 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1685 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1686 argument with the specified mode and type. If it is not defined,
1687 `PARM_BOUNDARY' is used for all arguments. */
1688 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1689 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1690 ? DOUBLEWORD_ALIGNMENT \
1693 /* 1 if N is a possible register number for function argument passing.
1694 On the ARM, r0-r3 are used to pass args. */
1695 #define FUNCTION_ARG_REGNO_P(REGNO) \
1696 (IN_RANGE ((REGNO), 0, 3) \
1697 || (TARGET_IWMMXT_ABI \
1698 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1701 /* If your target environment doesn't prefix user functions with an
1702 underscore, you may wish to re-define this to prevent any conflicts. */
1703 #ifndef ARM_MCOUNT_NAME
1704 #define ARM_MCOUNT_NAME "*mcount"
1707 /* Call the function profiler with a given profile label. The Acorn
1708 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1709 On the ARM the full profile code will look like:
1718 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1719 will output the .text section.
1721 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1722 ``prof'' doesn't seem to mind about this!
1724 Note - this version of the code is designed to work in both ARM and
1726 #ifndef ARM_FUNCTION_PROFILER
1727 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1732 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1733 IP_REGNUM, LR_REGNUM); \
1734 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1735 fputc ('\n', STREAM); \
1736 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1737 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1738 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1742 #ifdef THUMB_FUNCTION_PROFILER
1743 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1745 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1747 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1749 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1750 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1753 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1754 the stack pointer does not matter. The value is tested only in
1755 functions that have frame pointers.
1756 No definition is equivalent to always zero.
1758 On the ARM, the function epilogue recovers the stack pointer from the
1760 #define EXIT_IGNORE_STACK 1
1762 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1764 /* Determine if the epilogue should be output as RTL.
1765 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1766 /* This is disabled for Thumb-2 because it will confuse the
1767 conditional insn counter. */
1768 #define USE_RETURN_INSN(ISCOND) \
1769 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1771 /* Definitions for register eliminations.
1773 This is an array of structures. Each structure initializes one pair
1774 of eliminable registers. The "from" register number is given first,
1775 followed by "to". Eliminations of the same "from" register are listed
1776 in order of preference.
1778 We have two registers that can be eliminated on the ARM. First, the
1779 arg pointer register can often be eliminated in favor of the stack
1780 pointer register. Secondly, the pseudo frame pointer register can always
1781 be eliminated; it is replaced with either the stack or the real frame
1782 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1783 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1785 #define ELIMINABLE_REGS \
1786 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1787 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1788 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1789 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1790 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1791 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1792 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1794 /* Given FROM and TO register numbers, say whether this elimination is
1795 allowed. Frame pointer elimination is automatically handled.
1797 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1798 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1799 pointer, we must eliminate FRAME_POINTER_REGNUM into
1800 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1801 ARG_POINTER_REGNUM. */
1802 #define CAN_ELIMINATE(FROM, TO) \
1803 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1804 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1805 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1806 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1809 /* Define the offset between two registers, one to be eliminated, and the
1810 other its replacement, at the start of a routine. */
1811 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1813 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1815 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1817 /* Special case handling of the location of arguments passed on the stack. */
1818 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1820 /* Initialize data used by insn expanders. This is called from insn_emit,
1821 once for every function before code is generated. */
1822 #define INIT_EXPANDERS arm_init_expanders ()
1824 /* Output assembler code for a block containing the constant parts
1825 of a trampoline, leaving space for the variable parts.
1827 On the ARM, (if r8 is the static chain regnum, and remembering that
1828 referencing pc adds an offset of 8) the trampoline looks like:
1831 .word static chain value
1832 .word function's address
1833 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1834 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1836 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1837 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1838 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1839 PC_REGNUM, PC_REGNUM); \
1840 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1841 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1844 /* The Thumb-2 trampoline is similar to the arm implementation.
1845 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1846 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1848 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1849 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1850 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1851 PC_REGNUM, PC_REGNUM); \
1852 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1853 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1856 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1858 ASM_OUTPUT_ALIGN(FILE, 2); \
1859 fprintf (FILE, "\t.code\t16\n"); \
1860 fprintf (FILE, ".Ltrampoline_start:\n"); \
1861 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1862 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1864 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1865 STATIC_CHAIN_REGNUM); \
1866 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1868 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1870 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1872 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1873 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1876 #define TRAMPOLINE_TEMPLATE(FILE) \
1878 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1879 else if (TARGET_THUMB2) \
1880 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1882 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1884 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1886 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1889 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1890 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1893 /* Length in units of the trampoline for entering a nested function. */
1894 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1896 /* Alignment required for a trampoline in bits. */
1897 #define TRAMPOLINE_ALIGNMENT 32
1900 /* Emit RTL insns to initialize the variable parts of a trampoline.
1901 FNADDR is an RTX for the address of the function's pure code.
1902 CXT is an RTX for the static chain value for the function. */
1903 #ifndef INITIALIZE_TRAMPOLINE
1904 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1906 emit_move_insn (gen_rtx_MEM (SImode, \
1907 plus_constant (TRAMP, \
1908 TARGET_32BIT ? 8 : 12)), \
1910 emit_move_insn (gen_rtx_MEM (SImode, \
1911 plus_constant (TRAMP, \
1912 TARGET_32BIT ? 12 : 16)), \
1914 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1915 0, VOIDmode, 2, TRAMP, Pmode, \
1916 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1921 /* Addressing modes, and classification of registers for them. */
1922 #define HAVE_POST_INCREMENT 1
1923 #define HAVE_PRE_INCREMENT TARGET_32BIT
1924 #define HAVE_POST_DECREMENT TARGET_32BIT
1925 #define HAVE_PRE_DECREMENT TARGET_32BIT
1926 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1927 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1928 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1929 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1931 /* Macros to check register numbers against specific register classes. */
1933 /* These assume that REGNO is a hard or pseudo reg number.
1934 They give nonzero only if REGNO is a hard reg of the suitable class
1935 or a pseudo reg currently allocated to a suitable hard reg.
1936 Since they use reg_renumber, they are safe only once reg_renumber
1937 has been allocated, which happens in local-alloc.c. */
1938 #define TEST_REGNO(R, TEST, VALUE) \
1939 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1941 /* Don't allow the pc to be used. */
1942 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1943 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1944 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1945 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1947 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1948 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1949 || (GET_MODE_SIZE (MODE) >= 4 \
1950 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1952 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1954 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1955 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1957 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1958 For Thumb, we can not use SP + reg, so reject SP. */
1959 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1960 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1962 /* For ARM code, we don't care about the mode, but for Thumb, the index
1963 must be suitable for use in a QImode load. */
1964 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1965 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1966 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1968 /* Maximum number of registers that can appear in a valid memory address.
1969 Shifts in addresses can't be by a register. */
1970 #define MAX_REGS_PER_ADDRESS 2
1972 /* Recognize any constant value that is a valid address. */
1973 /* XXX We can address any constant, eventually... */
1974 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1975 #define CONSTANT_ADDRESS_P(X) \
1976 (GET_CODE (X) == SYMBOL_REF \
1977 && (CONSTANT_POOL_ADDRESS_P (X) \
1978 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1980 /* True if SYMBOL + OFFSET constants must refer to something within
1981 SYMBOL's section. */
1982 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1984 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1985 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1986 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1989 /* Nonzero if the constant value X is a legitimate general operand.
1990 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1992 On the ARM, allow any integer (invalid ones are removed later by insn
1993 patterns), nice doubles and symbol_refs which refer to the function's
1996 When generating pic allow anything. */
1997 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1999 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2000 ( GET_CODE (X) == CONST_INT \
2001 || GET_CODE (X) == CONST_DOUBLE \
2002 || CONSTANT_ADDRESS_P (X) \
2005 #define LEGITIMATE_CONSTANT_P(X) \
2006 (!arm_cannot_force_const_mem (X) \
2007 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
2008 : THUMB_LEGITIMATE_CONSTANT_P (X)))
2010 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2011 #define SUBTARGET_NAME_ENCODING_LENGTHS
2014 /* This is a C fragment for the inside of a switch statement.
2015 Each case label should return the number of characters to
2016 be stripped from the start of a function's name, if that
2017 name starts with the indicated character. */
2018 #define ARM_NAME_ENCODING_LENGTHS \
2019 case '*': return 1; \
2020 SUBTARGET_NAME_ENCODING_LENGTHS
2022 /* This is how to output a reference to a user-level label named NAME.
2023 `assemble_name' uses this. */
2024 #undef ASM_OUTPUT_LABELREF
2025 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2026 arm_asm_output_labelref (FILE, NAME)
2028 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
2029 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2030 if (TARGET_THUMB2) \
2031 thumb2_asm_output_opcode (STREAM);
2033 /* The EABI specifies that constructors should go in .init_array.
2034 Other targets use .ctors for compatibility. */
2035 #ifndef ARM_EABI_CTORS_SECTION_OP
2036 #define ARM_EABI_CTORS_SECTION_OP \
2037 "\t.section\t.init_array,\"aw\",%init_array"
2039 #ifndef ARM_EABI_DTORS_SECTION_OP
2040 #define ARM_EABI_DTORS_SECTION_OP \
2041 "\t.section\t.fini_array,\"aw\",%fini_array"
2043 #define ARM_CTORS_SECTION_OP \
2044 "\t.section\t.ctors,\"aw\",%progbits"
2045 #define ARM_DTORS_SECTION_OP \
2046 "\t.section\t.dtors,\"aw\",%progbits"
2048 /* Define CTORS_SECTION_ASM_OP. */
2049 #undef CTORS_SECTION_ASM_OP
2050 #undef DTORS_SECTION_ASM_OP
2052 # define CTORS_SECTION_ASM_OP \
2053 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2054 # define DTORS_SECTION_ASM_OP \
2055 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2056 #else /* !defined (IN_LIBGCC2) */
2057 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2058 so we cannot use the definition above. */
2059 # ifdef __ARM_EABI__
2060 /* The .ctors section is not part of the EABI, so we do not define
2061 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2062 from trying to use it. We do define it when doing normal
2063 compilation, as .init_array can be used instead of .ctors. */
2064 /* There is no need to emit begin or end markers when using
2065 init_array; the dynamic linker will compute the size of the
2066 array itself based on special symbols created by the static
2067 linker. However, we do need to arrange to set up
2068 exception-handling here. */
2069 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2070 # define CTOR_LIST_END /* empty */
2071 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2072 # define DTOR_LIST_END /* empty */
2073 # else /* !defined (__ARM_EABI__) */
2074 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2075 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2076 # endif /* !defined (__ARM_EABI__) */
2077 #endif /* !defined (IN_LIBCC2) */
2079 /* True if the operating system can merge entities with vague linkage
2080 (e.g., symbols in COMDAT group) during dynamic linking. */
2081 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2082 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2085 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2087 #ifdef TARGET_UNWIND_INFO
2088 #define ARM_EABI_UNWIND_TABLES \
2089 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2091 #define ARM_EABI_UNWIND_TABLES 0
2094 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2095 and check its validity for a certain class.
2096 We have two alternate definitions for each of them.
2097 The usual definition accepts all pseudo regs; the other rejects
2098 them unless they have been allocated suitable hard regs.
2099 The symbol REG_OK_STRICT causes the latter definition to be used.
2100 Thumb-2 has the same restrictions as arm. */
2101 #ifndef REG_OK_STRICT
2103 #define ARM_REG_OK_FOR_BASE_P(X) \
2104 (REGNO (X) <= LAST_ARM_REGNUM \
2105 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2106 || REGNO (X) == FRAME_POINTER_REGNUM \
2107 || REGNO (X) == ARG_POINTER_REGNUM)
2109 #define ARM_REG_OK_FOR_INDEX_P(X) \
2110 ((REGNO (X) <= LAST_ARM_REGNUM \
2111 && REGNO (X) != STACK_POINTER_REGNUM) \
2112 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2113 || REGNO (X) == FRAME_POINTER_REGNUM \
2114 || REGNO (X) == ARG_POINTER_REGNUM)
2116 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2117 (REGNO (X) <= LAST_LO_REGNUM \
2118 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2119 || (GET_MODE_SIZE (MODE) >= 4 \
2120 && (REGNO (X) == STACK_POINTER_REGNUM \
2121 || (X) == hard_frame_pointer_rtx \
2122 || (X) == arg_pointer_rtx)))
2124 #define REG_STRICT_P 0
2126 #else /* REG_OK_STRICT */
2128 #define ARM_REG_OK_FOR_BASE_P(X) \
2129 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2131 #define ARM_REG_OK_FOR_INDEX_P(X) \
2132 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2134 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2135 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2137 #define REG_STRICT_P 1
2139 #endif /* REG_OK_STRICT */
2141 /* Now define some helpers in terms of the above. */
2143 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2145 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2146 : ARM_REG_OK_FOR_BASE_P (X))
2148 /* For 16-bit Thumb, a valid index register is anything that can be used in
2149 a byte load instruction. */
2150 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2151 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2153 /* Nonzero if X is a hard reg that can be used as an index
2154 or if it is a pseudo reg. On the Thumb, the stack pointer
2156 #define REG_OK_FOR_INDEX_P(X) \
2158 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2159 : ARM_REG_OK_FOR_INDEX_P (X))
2161 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2162 For Thumb, we can not use SP + reg, so reject SP. */
2163 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2164 REG_OK_FOR_INDEX_P (X)
2166 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2167 that is a valid memory address for an instruction.
2168 The MODE argument is the machine mode for the MEM expression
2169 that wants to use this address. */
2171 #define ARM_BASE_REGISTER_RTX_P(X) \
2172 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2174 #define ARM_INDEX_REGISTER_RTX_P(X) \
2175 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2177 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2179 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2183 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2185 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2189 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2191 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2195 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2197 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2198 else if (TARGET_THUMB2) \
2199 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2200 else /* if (TARGET_THUMB1) */ \
2201 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2204 /* Try machine-dependent ways of modifying an illegitimate address
2205 to be legitimate. If we find one, return the new, valid address. */
2206 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2208 X = arm_legitimize_address (X, OLDX, MODE); \
2211 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2212 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2216 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2218 X = thumb_legitimize_address (X, OLDX, MODE); \
2221 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2224 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2225 else if (TARGET_THUMB2) \
2226 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2228 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2230 if (memory_address_p (MODE, X)) \
2234 /* Go to LABEL if ADDR (a legitimate address expression)
2235 has an effect that depends on the machine mode it is used for. */
2236 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2238 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2239 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2243 /* Nothing helpful to do for the Thumb */
2244 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2246 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2249 /* Specify the machine mode that this machine uses
2250 for the index in the tablejump instruction. */
2251 #define CASE_VECTOR_MODE Pmode
2253 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2255 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2256 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2257 : (max >= 0x200) ? HImode \
2260 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2261 unsigned is probably best, but may break some code. */
2262 #ifndef DEFAULT_SIGNED_CHAR
2263 #define DEFAULT_SIGNED_CHAR 0
2266 /* Max number of bytes we can move from memory to memory
2267 in one reasonably fast instruction. */
2271 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2273 /* Define if operations between registers always perform the operation
2274 on the full register even if a narrower mode is specified. */
2275 #define WORD_REGISTER_OPERATIONS
2277 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2278 will either zero-extend or sign-extend. The value of this macro should
2279 be the code that says which one of the two operations is implicitly
2280 done, UNKNOWN if none. */
2281 #define LOAD_EXTEND_OP(MODE) \
2282 (TARGET_THUMB ? ZERO_EXTEND : \
2283 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2284 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2286 /* Nonzero if access to memory by bytes is slow and undesirable. */
2287 #define SLOW_BYTE_ACCESS 0
2289 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2291 /* Immediate shift counts are truncated by the output routines (or was it
2292 the assembler?). Shift counts in a register are truncated by ARM. Note
2293 that the native compiler puts too large (> 32) immediate shift counts
2294 into a register and shifts by the register, letting the ARM decide what
2295 to do instead of doing that itself. */
2296 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2297 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2298 On the arm, Y in a register is used modulo 256 for the shift. Only for
2299 rotates is modulo 32 used. */
2300 /* #define SHIFT_COUNT_TRUNCATED 1 */
2302 /* All integers have the same format so truncation is easy. */
2303 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2305 /* Calling from registers is a massive pain. */
2306 #define NO_FUNCTION_CSE 1
2308 /* The machine modes of pointers and functions */
2309 #define Pmode SImode
2310 #define FUNCTION_MODE Pmode
2312 #define ARM_FRAME_RTX(X) \
2313 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2314 || (X) == arg_pointer_rtx)
2316 /* Moves to and from memory are quite expensive */
2317 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2318 (TARGET_32BIT ? 10 : \
2319 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2320 * (CLASS == LO_REGS ? 1 : 2)))
2322 /* Try to generate sequences that don't involve branches, we can then use
2323 conditional instructions */
2324 #define BRANCH_COST(speed_p, predictable_p) \
2325 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2327 /* Position Independent Code. */
2328 /* We decide which register to use based on the compilation options and
2329 the assembler in use; this is more general than the APCS restriction of
2330 using sb (r9) all the time. */
2331 extern unsigned arm_pic_register;
2333 /* The register number of the register used to address a table of static
2334 data addresses in memory. */
2335 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2337 /* We can't directly access anything that contains a symbol,
2338 nor can we indirect via the constant pool. One exception is
2339 UNSPEC_TLS, which is always PIC. */
2340 #define LEGITIMATE_PIC_OPERAND_P(X) \
2341 (!(symbol_mentioned_p (X) \
2342 || label_mentioned_p (X) \
2343 || (GET_CODE (X) == SYMBOL_REF \
2344 && CONSTANT_POOL_ADDRESS_P (X) \
2345 && (symbol_mentioned_p (get_pool_constant (X)) \
2346 || label_mentioned_p (get_pool_constant (X))))) \
2347 || tls_mentioned_p (X))
2349 /* We need to know when we are making a constant pool; this determines
2350 whether data needs to be in the GOT or can be referenced via a GOT
2352 extern int making_const_table;
2354 /* Handle pragmas for compatibility with Intel's compilers. */
2355 /* Also abuse this to register additional C specific EABI attributes. */
2356 #define REGISTER_TARGET_PRAGMAS() do { \
2357 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2358 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2359 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2360 arm_lang_object_attributes_init(); \
2363 /* Condition code information. */
2364 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2365 return the mode to be used for the comparison. */
2367 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2369 #define REVERSIBLE_CC_MODE(MODE) 1
2371 #define REVERSE_CONDITION(CODE,MODE) \
2372 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2373 ? reverse_condition_maybe_unordered (code) \
2374 : reverse_condition (code))
2376 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2379 if (GET_CODE (OP1) == CONST_INT \
2380 && ! (const_ok_for_arm (INTVAL (OP1)) \
2381 || (const_ok_for_arm (- INTVAL (OP1))))) \
2383 rtx const_op = OP1; \
2384 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2391 /* The arm5 clz instruction returns 32. */
2392 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2395 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2396 TARGET_THUMB2 ? "\t.thumb\n" : "")
2398 /* Output a push or a pop instruction (only used when profiling). */
2399 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2403 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2404 STACK_POINTER_REGNUM, REGNO); \
2406 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2410 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2414 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2415 STACK_POINTER_REGNUM, REGNO); \
2417 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2420 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2421 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2423 /* This is how to output a label which precedes a jumptable. Since
2424 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2425 #undef ASM_OUTPUT_CASE_LABEL
2426 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2429 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2430 ASM_OUTPUT_ALIGN (FILE, 2); \
2431 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2435 /* Make sure subsequent insns are aligned after a TBB. */
2436 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2439 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2440 ASM_OUTPUT_ALIGN (FILE, 1); \
2444 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2449 if (is_called_in_ARM_mode (DECL) \
2450 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2451 && cfun->is_thunk)) \
2452 fprintf (STREAM, "\t.code 32\n") ; \
2453 else if (TARGET_THUMB1) \
2454 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2456 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2458 if (TARGET_POKE_FUNCTION_NAME) \
2459 arm_poke_function_name (STREAM, (const char *) NAME); \
2463 /* For aliases of functions we use .thumb_set instead. */
2464 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2467 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2468 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2470 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2472 fprintf (FILE, "\t.thumb_set "); \
2473 assemble_name (FILE, LABEL1); \
2474 fprintf (FILE, ","); \
2475 assemble_name (FILE, LABEL2); \
2476 fprintf (FILE, "\n"); \
2479 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2483 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2484 /* To support -falign-* switches we need to use .p2align so
2485 that alignment directives in code sections will be padded
2486 with no-op instructions, rather than zeroes. */
2487 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2490 if ((MAX_SKIP) == 0) \
2491 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2493 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2494 (int) (LOG), (int) (MAX_SKIP)); \
2498 /* Add two bytes to the length of conditionally executed Thumb-2
2499 instructions for the IT instruction. */
2500 #define ADJUST_INSN_LENGTH(insn, length) \
2501 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2504 /* Only perform branch elimination (by making instructions conditional) if
2505 we're optimizing. For Thumb-2 check if any IT instructions need
2507 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2508 if (TARGET_ARM && optimize) \
2509 arm_final_prescan_insn (INSN); \
2510 else if (TARGET_THUMB2) \
2511 thumb2_final_prescan_insn (INSN); \
2512 else if (TARGET_THUMB1) \
2513 thumb1_final_prescan_insn (INSN)
2515 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2516 (CODE == '@' || CODE == '|' || CODE == '.' \
2517 || CODE == '(' || CODE == ')' || CODE == '#' \
2518 || (TARGET_32BIT && (CODE == '?')) \
2519 || (TARGET_THUMB2 && (CODE == '!')) \
2520 || (TARGET_THUMB && (CODE == '_')))
2522 /* Output an operand of an instruction. */
2523 #define PRINT_OPERAND(STREAM, X, CODE) \
2524 arm_print_operand (STREAM, X, CODE)
2526 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2527 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2528 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2529 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2530 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2531 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2534 /* Output the address of an operand. */
2535 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2537 int is_minus = GET_CODE (X) == MINUS; \
2539 if (GET_CODE (X) == REG) \
2540 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2541 else if (GET_CODE (X) == PLUS || is_minus) \
2543 rtx base = XEXP (X, 0); \
2544 rtx index = XEXP (X, 1); \
2545 HOST_WIDE_INT offset = 0; \
2546 if (GET_CODE (base) != REG \
2547 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2549 /* Ensure that BASE is a register. */ \
2550 /* (one of them must be). */ \
2551 /* Also ensure the SP is not used as in index register. */ \
2556 switch (GET_CODE (index)) \
2559 offset = INTVAL (index); \
2562 asm_fprintf (STREAM, "[%r, #%wd]", \
2563 REGNO (base), offset); \
2567 asm_fprintf (STREAM, "[%r, %s%r]", \
2568 REGNO (base), is_minus ? "-" : "", \
2578 asm_fprintf (STREAM, "[%r, %s%r", \
2579 REGNO (base), is_minus ? "-" : "", \
2580 REGNO (XEXP (index, 0))); \
2581 arm_print_operand (STREAM, index, 'S'); \
2582 fputs ("]", STREAM); \
2587 gcc_unreachable (); \
2590 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2591 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2593 extern enum machine_mode output_memory_reference_mode; \
2595 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2597 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2598 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2599 REGNO (XEXP (X, 0)), \
2600 GET_CODE (X) == PRE_DEC ? "-" : "", \
2601 GET_MODE_SIZE (output_memory_reference_mode)); \
2603 asm_fprintf (STREAM, "[%r], #%s%d", \
2604 REGNO (XEXP (X, 0)), \
2605 GET_CODE (X) == POST_DEC ? "-" : "", \
2606 GET_MODE_SIZE (output_memory_reference_mode)); \
2608 else if (GET_CODE (X) == PRE_MODIFY) \
2610 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2611 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2612 asm_fprintf (STREAM, "#%wd]!", \
2613 INTVAL (XEXP (XEXP (X, 1), 1))); \
2615 asm_fprintf (STREAM, "%r]!", \
2616 REGNO (XEXP (XEXP (X, 1), 1))); \
2618 else if (GET_CODE (X) == POST_MODIFY) \
2620 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2621 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2622 asm_fprintf (STREAM, "#%wd", \
2623 INTVAL (XEXP (XEXP (X, 1), 1))); \
2625 asm_fprintf (STREAM, "%r", \
2626 REGNO (XEXP (XEXP (X, 1), 1))); \
2628 else output_addr_const (STREAM, X); \
2631 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2633 if (GET_CODE (X) == REG) \
2634 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2635 else if (GET_CODE (X) == POST_INC) \
2636 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2637 else if (GET_CODE (X) == PLUS) \
2639 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2640 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2641 asm_fprintf (STREAM, "[%r, #%wd]", \
2642 REGNO (XEXP (X, 0)), \
2643 INTVAL (XEXP (X, 1))); \
2645 asm_fprintf (STREAM, "[%r, %r]", \
2646 REGNO (XEXP (X, 0)), \
2647 REGNO (XEXP (X, 1))); \
2650 output_addr_const (STREAM, X); \
2653 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2655 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2657 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2659 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2660 if (arm_output_addr_const_extra (file, x) == FALSE) \
2663 /* A C expression whose value is RTL representing the value of the return
2664 address for the frame COUNT steps up from the current frame. */
2666 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2667 arm_return_addr (COUNT, FRAME)
2669 /* Mask of the bits in the PC that contain the real return address
2670 when running in 26-bit mode. */
2671 #define RETURN_ADDR_MASK26 (0x03fffffc)
2673 /* Pick up the return address upon entry to a procedure. Used for
2674 dwarf2 unwind information. This also enables the table driven
2676 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2677 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2679 /* Used to mask out junk bits from the return address, such as
2680 processor state, interrupt status, condition codes and the like. */
2681 #define MASK_RETURN_ADDR \
2682 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2683 in 26 bit mode, the condition codes must be masked out of the \
2684 return address. This does not apply to ARM6 and later processors \
2685 when running in 32 bit mode. */ \
2686 ((arm_arch4 || TARGET_THUMB) \
2687 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2688 : arm_gen_return_addr_mask ())
2691 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2692 symbolic names defined here (which would require too much duplication).
2701 ARM_BUILTIN_WAVG2BR,
2702 ARM_BUILTIN_WAVG2HR,
2729 ARM_BUILTIN_TMOVMSKB,
2730 ARM_BUILTIN_TMOVMSKH,
2731 ARM_BUILTIN_TMOVMSKW,
2740 ARM_BUILTIN_WPACKHSS,
2741 ARM_BUILTIN_WPACKWSS,
2742 ARM_BUILTIN_WPACKDSS,
2743 ARM_BUILTIN_WPACKHUS,
2744 ARM_BUILTIN_WPACKWUS,
2745 ARM_BUILTIN_WPACKDUS,
2750 ARM_BUILTIN_WADDSSB,
2751 ARM_BUILTIN_WADDSSH,
2752 ARM_BUILTIN_WADDSSW,
2753 ARM_BUILTIN_WADDUSB,
2754 ARM_BUILTIN_WADDUSH,
2755 ARM_BUILTIN_WADDUSW,
2759 ARM_BUILTIN_WSUBSSB,
2760 ARM_BUILTIN_WSUBSSH,
2761 ARM_BUILTIN_WSUBSSW,
2762 ARM_BUILTIN_WSUBUSB,
2763 ARM_BUILTIN_WSUBUSH,
2764 ARM_BUILTIN_WSUBUSW,
2771 ARM_BUILTIN_WCMPEQB,
2772 ARM_BUILTIN_WCMPEQH,
2773 ARM_BUILTIN_WCMPEQW,
2774 ARM_BUILTIN_WCMPGTUB,
2775 ARM_BUILTIN_WCMPGTUH,
2776 ARM_BUILTIN_WCMPGTUW,
2777 ARM_BUILTIN_WCMPGTSB,
2778 ARM_BUILTIN_WCMPGTSH,
2779 ARM_BUILTIN_WCMPGTSW,
2781 ARM_BUILTIN_TEXTRMSB,
2782 ARM_BUILTIN_TEXTRMSH,
2783 ARM_BUILTIN_TEXTRMSW,
2784 ARM_BUILTIN_TEXTRMUB,
2785 ARM_BUILTIN_TEXTRMUH,
2786 ARM_BUILTIN_TEXTRMUW,
2836 ARM_BUILTIN_WUNPCKIHB,
2837 ARM_BUILTIN_WUNPCKIHH,
2838 ARM_BUILTIN_WUNPCKIHW,
2839 ARM_BUILTIN_WUNPCKILB,
2840 ARM_BUILTIN_WUNPCKILH,
2841 ARM_BUILTIN_WUNPCKILW,
2843 ARM_BUILTIN_WUNPCKEHSB,
2844 ARM_BUILTIN_WUNPCKEHSH,
2845 ARM_BUILTIN_WUNPCKEHSW,
2846 ARM_BUILTIN_WUNPCKEHUB,
2847 ARM_BUILTIN_WUNPCKEHUH,
2848 ARM_BUILTIN_WUNPCKEHUW,
2849 ARM_BUILTIN_WUNPCKELSB,
2850 ARM_BUILTIN_WUNPCKELSH,
2851 ARM_BUILTIN_WUNPCKELSW,
2852 ARM_BUILTIN_WUNPCKELUB,
2853 ARM_BUILTIN_WUNPCKELUH,
2854 ARM_BUILTIN_WUNPCKELUW,
2856 ARM_BUILTIN_THREAD_POINTER,
2858 ARM_BUILTIN_NEON_BASE,
2860 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2863 /* Do not emit .note.GNU-stack by default. */
2864 #ifndef NEED_INDICATE_EXEC_STACK
2865 #define NEED_INDICATE_EXEC_STACK 0
2868 #endif /* ! GCC_ARM_H */
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