1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
39 #include "config/vxworks-dummy.h"
41 /* The architecture define. */
42 extern char arm_arch_name[];
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
53 builtin_define ("__thumb__"); \
55 builtin_define ("__thumb2__"); \
59 builtin_define ("__ARMEB__"); \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
67 builtin_define ("__ARMEL__"); \
69 builtin_define ("__THUMBEL__"); \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
76 builtin_define ("__VFP_FP__"); \
79 builtin_define ("__ARM_NEON__"); \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
99 builtin_define ("__ARM_PCS_VFP"); \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
101 builtin_define ("__ARM_PCS"); \
102 builtin_define ("__ARM_EABI__"); \
106 /* The various ARM cores. */
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
111 #include "arm-cores.def"
113 /* Used to indicate that no processor has been specified. */
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
121 #include "arm-cores.def"
126 /* The processor for which instructions should be scheduled. */
127 extern enum processor_type arm_tune;
129 typedef enum arm_cond_code
131 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
132 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
136 extern arm_cc arm_current_cc;
138 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
140 extern int arm_target_label;
141 extern int arm_ccfsm_state;
142 extern GTY(()) rtx arm_target_insn;
143 /* The label of the current constant pool. */
144 extern rtx pool_vector_label;
145 /* Set to 1 when a return insn is output, this means that the epilogue
147 extern int return_used_this_function;
148 /* Callback to output language specific object attributes. */
149 extern void (*arm_lang_output_object_attributes_hook)(void);
151 /* Just in case configure has failed to define anything. */
152 #ifndef TARGET_CPU_DEFAULT
153 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
158 #define CPP_SPEC "%(subtarget_cpp_spec) \
159 %{msoft-float:%{mhard-float: \
160 %e-msoft-float and -mhard_float may not be used together}} \
161 %{mbig-endian:%{mlittle-endian: \
162 %e-mbig-endian and -mlittle-endian may not be used together}}"
168 /* This macro defines names of additional specifications to put in the specs
169 that can be used in various specifications like CC1_SPEC. Its definition
170 is an initializer with a subgrouping for each command option.
172 Each subgrouping contains a string constant, that defines the
173 specification name, and a string constant that used by the GCC driver
176 Do not define this macro if it does not need to do anything. */
177 #define EXTRA_SPECS \
178 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
179 SUBTARGET_EXTRA_SPECS
181 #ifndef SUBTARGET_EXTRA_SPECS
182 #define SUBTARGET_EXTRA_SPECS
185 #ifndef SUBTARGET_CPP_SPEC
186 #define SUBTARGET_CPP_SPEC ""
189 /* Run-time Target Specification. */
190 #ifndef TARGET_VERSION
191 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
194 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
195 /* Use hardware floating point instructions. */
196 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
197 /* Use hardware floating point calling convention. */
198 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
199 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
200 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
201 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
202 #define TARGET_IWMMXT (arm_arch_iwmmxt)
203 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
204 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
205 #define TARGET_ARM (! TARGET_THUMB)
206 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
207 #define TARGET_BACKTRACE (leaf_function_p () \
208 ? TARGET_TPCS_LEAF_FRAME \
210 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
211 #define TARGET_AAPCS_BASED \
212 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
214 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
215 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
217 /* Only 16-bit thumb code. */
218 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
219 /* Arm or Thumb-2 32-bit code. */
220 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
221 /* 32-bit Thumb-2 code. */
222 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
224 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
225 /* FPA emulator without LFM. */
226 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
228 /* The following two macros concern the ability to execute coprocessor
229 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
230 only ever tested when we know we are generating for VFP hardware; we need
231 to be more careful with TARGET_NEON as noted below. */
233 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
234 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
236 /* FPU supports VFPv3 instructions. */
237 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
239 /* FPU only supports VFP single-precision instructions. */
240 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
242 /* FPU supports VFP double-precision instructions. */
243 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
245 /* FPU supports half-precision floating-point with NEON element load/store. */
246 #define TARGET_NEON_FP16 \
247 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
249 /* FPU supports VFP half-precision floating-point. */
250 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
252 /* FPU supports Neon instructions. The setting of this macro gets
253 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
254 and TARGET_HARD_FLOAT to ensure that NEON instructions are
256 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
257 && TARGET_VFP && arm_fpu_desc->neon)
259 /* "DSP" multiply instructions, eg. SMULxy. */
260 #define TARGET_DSP_MULTIPLY \
261 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
262 /* Integer SIMD instructions, and extend-accumulate instructions. */
263 #define TARGET_INT_SIMD \
264 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
266 /* Should MOVW/MOVT be used in preference to a constant pool. */
267 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
269 /* We could use unified syntax for arm mode, but for now we just use it
271 #define TARGET_UNIFIED_ASM TARGET_THUMB2
274 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
275 then TARGET_AAPCS_BASED must be true -- but the converse does not
276 hold. TARGET_BPABI implies the use of the BPABI runtime library,
277 etc., in addition to just the AAPCS calling conventions. */
279 #define TARGET_BPABI false
282 /* Support for a compile-time default CPU, et cetera. The rules are:
283 --with-arch is ignored if -march or -mcpu are specified.
284 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
286 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
288 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
290 --with-fpu is ignored if -mfpu is specified.
291 --with-abi is ignored is -mabi is specified. */
292 #define OPTION_DEFAULT_SPECS \
293 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
294 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
295 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
297 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
298 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
299 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
300 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
302 /* Which floating point model to use. */
305 ARM_FP_MODEL_UNKNOWN,
306 /* FPA model (Hardware or software). */
308 /* Cirrus Maverick floating point model. */
309 ARM_FP_MODEL_MAVERICK,
310 /* VFP floating point model. */
322 extern const struct arm_fpu_desc
325 enum arm_fp_model model;
327 enum vfp_reg_type regs;
332 /* Which floating point hardware to schedule for. */
333 extern int arm_fpu_attr;
338 ARM_FLOAT_ABI_SOFTFP,
342 extern enum float_abi_type arm_float_abi;
344 #ifndef TARGET_DEFAULT_FLOAT_ABI
345 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
348 /* Which __fp16 format to use.
349 The enumeration values correspond to the numbering for the
350 Tag_ABI_FP_16bit_format attribute.
352 enum arm_fp16_format_type
354 ARM_FP16_FORMAT_NONE = 0,
355 ARM_FP16_FORMAT_IEEE = 1,
356 ARM_FP16_FORMAT_ALTERNATIVE = 2
359 extern enum arm_fp16_format_type arm_fp16_format;
360 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
361 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
363 /* Which ABI to use. */
373 extern enum arm_abi_type arm_abi;
375 #ifndef ARM_DEFAULT_ABI
376 #define ARM_DEFAULT_ABI ARM_ABI_APCS
379 /* Which thread pointer access sequence to use. */
386 extern enum arm_tp_type target_thread_pointer;
388 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
389 extern int arm_arch3m;
391 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
392 extern int arm_arch4;
394 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
395 extern int arm_arch4t;
397 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
398 extern int arm_arch5;
400 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
401 extern int arm_arch5e;
403 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
404 extern int arm_arch6;
406 /* Nonzero if instructions not present in the 'M' profile can be used. */
407 extern int arm_arch_notm;
409 /* Nonzero if instructions present in ARMv7E-M can be used. */
410 extern int arm_arch7em;
412 /* Nonzero if this chip can benefit from load scheduling. */
413 extern int arm_ld_sched;
415 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
416 extern int thumb_code;
418 /* Nonzero if generating Thumb-1 code. */
419 extern int thumb1_code;
421 /* Nonzero if this chip is a StrongARM. */
422 extern int arm_tune_strongarm;
424 /* Nonzero if this chip is a Cirrus variant. */
425 extern int arm_arch_cirrus;
427 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
428 extern int arm_arch_iwmmxt;
430 /* Nonzero if this chip is an XScale. */
431 extern int arm_arch_xscale;
433 /* Nonzero if tuning for XScale. */
434 extern int arm_tune_xscale;
436 /* Nonzero if tuning for stores via the write buffer. */
437 extern int arm_tune_wbuf;
439 /* Nonzero if tuning for Cortex-A9. */
440 extern int arm_tune_cortex_a9;
442 /* Nonzero if we should define __THUMB_INTERWORK__ in the
444 XXX This is a bit of a hack, it's intended to help work around
445 problems in GLD which doesn't understand that armv5t code is
446 interworking clean. */
447 extern int arm_cpp_interwork;
449 /* Nonzero if chip supports Thumb 2. */
450 extern int arm_arch_thumb2;
452 /* Nonzero if chip supports integer division instruction. */
453 extern int arm_arch_hwdiv;
455 #ifndef TARGET_DEFAULT
456 #define TARGET_DEFAULT (MASK_APCS_FRAME)
459 /* The frame pointer register used in gcc has nothing to do with debugging;
460 that is controlled by the APCS-FRAME option. */
461 #define CAN_DEBUG_WITHOUT_FP
463 #define OVERRIDE_OPTIONS arm_override_options ()
465 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
466 arm_optimization_options ((LEVEL), (SIZE))
468 /* Nonzero if PIC code requires explicit qualifiers to generate
469 PLT and GOT relocs rather than the assembler doing so implicitly.
470 Subtargets can override these if required. */
471 #ifndef NEED_GOT_RELOC
472 #define NEED_GOT_RELOC 0
474 #ifndef NEED_PLT_RELOC
475 #define NEED_PLT_RELOC 0
478 /* Nonzero if we need to refer to the GOT with a PC-relative
479 offset. In other words, generate
481 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
485 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
487 The default is true, which matches NetBSD. Subtargets can
488 override this if required. */
493 /* Target machine storage Layout. */
496 /* Define this macro if it is advisable to hold scalars in registers
497 in a wider mode than that declared by the program. In such cases,
498 the value is constrained to be within the bounds of the declared
499 type, but kept valid in the wider mode. The signedness of the
500 extension may differ from that of the type. */
502 /* It is far faster to zero extend chars than to sign extend them */
504 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
505 if (GET_MODE_CLASS (MODE) == MODE_INT \
506 && GET_MODE_SIZE (MODE) < 4) \
508 if (MODE == QImode) \
510 else if (MODE == HImode) \
515 /* Define this if most significant bit is lowest numbered
516 in instructions that operate on numbered bit-fields. */
517 #define BITS_BIG_ENDIAN 0
519 /* Define this if most significant byte of a word is the lowest numbered.
520 Most ARM processors are run in little endian mode, so that is the default.
521 If you want to have it run-time selectable, change the definition in a
522 cover file to be TARGET_BIG_ENDIAN. */
523 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
525 /* Define this if most significant word of a multiword number is the lowest
527 This is always false, even when in big-endian mode. */
528 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
530 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
531 on processor pre-defineds when compiling libgcc2.c. */
532 #if defined(__ARMEB__) && !defined(__ARMWEL__)
533 #define LIBGCC2_WORDS_BIG_ENDIAN 1
535 #define LIBGCC2_WORDS_BIG_ENDIAN 0
538 /* Define this if most significant word of doubles is the lowest numbered.
539 The rules are different based on whether or not we use FPA-format,
540 VFP-format or some other floating point co-processor's format doubles. */
541 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
543 #define UNITS_PER_WORD 4
545 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
546 registers when autovectorizing for Neon, at least until multiple vector
547 widths are supported properly by the middle-end. */
548 #define UNITS_PER_SIMD_WORD(MODE) \
549 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
551 /* True if natural alignment is used for doubleword types. */
552 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
554 #define DOUBLEWORD_ALIGNMENT 64
556 #define PARM_BOUNDARY 32
558 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
560 #define PREFERRED_STACK_BOUNDARY \
561 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
563 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
565 /* The lowest bit is used to indicate Thumb-mode functions, so the
566 vbit must go into the delta field of pointers to member
568 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
570 #define EMPTY_FIELD_BOUNDARY 32
572 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
574 /* XXX Blah -- this macro is used directly by libobjc. Since it
575 supports no vector modes, cut out the complexity and fall back
576 on BIGGEST_FIELD_ALIGNMENT. */
577 #ifdef IN_TARGET_LIBS
578 #define BIGGEST_FIELD_ALIGNMENT 64
581 /* Make strings word-aligned so strcpy from constants will be faster. */
582 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
584 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
585 ((TREE_CODE (EXP) == STRING_CST \
587 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
588 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
590 /* Align definitions of arrays, unions and structures so that
591 initializations and copies can be made more efficient. This is not
592 ABI-changing, so it only affects places where we can see the
594 #define DATA_ALIGNMENT(EXP, ALIGN) \
595 ((((ALIGN) < BITS_PER_WORD) \
596 && (TREE_CODE (EXP) == ARRAY_TYPE \
597 || TREE_CODE (EXP) == UNION_TYPE \
598 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
600 /* Similarly, make sure that objects on the stack are sensibly aligned. */
601 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
603 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
604 value set in previous versions of this toolchain was 8, which produces more
605 compact structures. The command line option -mstructure_size_boundary=<n>
606 can be used to change this value. For compatibility with the ARM SDK
607 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
608 0020D) page 2-20 says "Structures are aligned on word boundaries".
609 The AAPCS specifies a value of 8. */
610 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
611 extern int arm_structure_size_boundary;
613 /* This is the value used to initialize arm_structure_size_boundary. If a
614 particular arm target wants to change the default value it should change
615 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
616 for an example of this. */
617 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
618 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
621 /* Nonzero if move instructions will actually fail to work
622 when given unaligned data. */
623 #define STRICT_ALIGNMENT 1
625 /* wchar_t is unsigned under the AAPCS. */
627 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
629 #define WCHAR_TYPE_SIZE BITS_PER_WORD
633 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
637 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
640 /* AAPCS requires that structure alignment is affected by bitfields. */
641 #ifndef PCC_BITFIELD_TYPE_MATTERS
642 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
646 /* Standard register usage. */
648 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
649 (S - saved over call).
651 r0 * argument word/integer result
654 r4-r8 S register variable
655 r9 S (rfp) register variable (real frame pointer)
657 r10 F S (sl) stack limit (used by -mapcs-stack-check)
658 r11 F S (fp) argument pointer
659 r12 (ip) temp workspace
660 r13 F S (sp) lower end of current stack frame
661 r14 (lr) link address/workspace
662 r15 F (pc) program counter
664 f0 floating point result
665 f1-f3 floating point scratch
667 f4-f7 S floating point variable
669 cc This is NOT a real register, but is used internally
670 to represent things that use or set the condition
672 sfp This isn't either. It is used during rtl generation
673 since the offset between the frame pointer and the
674 auto's isn't known until after register allocation.
675 afp Nor this, we only need this because of non-local
676 goto. Without it fp appears to be used and the
677 elimination code won't get rid of sfp. It tracks
678 fp exactly at all times.
680 *: See CONDITIONAL_REGISTER_USAGE */
683 mvf0 Cirrus floating point result
684 mvf1-mvf3 Cirrus floating point scratch
685 mvf4-mvf15 S Cirrus floating point variable. */
687 /* s0-s15 VFP scratch (aka d0-d7).
688 s16-s31 S VFP variable (aka d8-d15).
689 vfpcc Not a real register. Represents the VFP condition
692 /* The stack backtrace structure is as follows:
693 fp points to here: | save code pointer | [fp]
694 | return link value | [fp, #-4]
695 | return sp value | [fp, #-8]
696 | return fp value | [fp, #-12]
697 [| saved r10 value |]
708 [| saved f7 value |] three words
709 [| saved f6 value |] three words
710 [| saved f5 value |] three words
711 [| saved f4 value |] three words
712 r0-r3 are not normally saved in a C function. */
714 /* 1 for registers that have pervasive standard uses
715 and are not available for the register allocator. */
716 #define FIXED_REGISTERS \
738 /* 1 for registers not available across function calls.
739 These must include the FIXED_REGISTERS and also any
740 registers that can be used without being saved.
741 The latter must include the registers where values are returned
742 and the register where structure-value addresses are passed.
743 Aside from that, you can include as many other registers as you like.
744 The CC is not preserved over function calls on the ARM 6, so it is
745 easier to assume this for all. SFP is preserved, since FP is. */
746 #define CALL_USED_REGISTERS \
768 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
769 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
772 #define CONDITIONAL_REGISTER_USAGE \
776 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
778 for (regno = FIRST_FPA_REGNUM; \
779 regno <= LAST_FPA_REGNUM; ++regno) \
780 fixed_regs[regno] = call_used_regs[regno] = 1; \
783 if (TARGET_THUMB1 && optimize_size) \
785 /* When optimizing for size on Thumb-1, it's better not \
786 to use the HI regs, because of the overhead of \
788 for (regno = FIRST_HI_REGNUM; \
789 regno <= LAST_HI_REGNUM; ++regno) \
790 fixed_regs[regno] = call_used_regs[regno] = 1; \
793 /* The link register can be clobbered by any branch insn, \
794 but we have no way to track that at present, so mark \
795 it as unavailable. */ \
797 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
799 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
801 if (TARGET_MAVERICK) \
803 for (regno = FIRST_FPA_REGNUM; \
804 regno <= LAST_FPA_REGNUM; ++ regno) \
805 fixed_regs[regno] = call_used_regs[regno] = 1; \
806 for (regno = FIRST_CIRRUS_FP_REGNUM; \
807 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
809 fixed_regs[regno] = 0; \
810 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
815 /* VFPv3 registers are disabled when earlier VFP \
816 versions are selected due to the definition of \
817 LAST_VFP_REGNUM. */ \
818 for (regno = FIRST_VFP_REGNUM; \
819 regno <= LAST_VFP_REGNUM; ++ regno) \
821 fixed_regs[regno] = 0; \
822 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
823 || regno >= FIRST_VFP_REGNUM + 32; \
828 if (TARGET_REALLY_IWMMXT) \
830 regno = FIRST_IWMMXT_GR_REGNUM; \
831 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
832 and wCG1 as call-preserved registers. The 2002/11/21 \
833 revision changed this so that all wCG registers are \
834 scratch registers. */ \
835 for (regno = FIRST_IWMMXT_GR_REGNUM; \
836 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
837 fixed_regs[regno] = 0; \
838 /* The XScale ABI has wR0 - wR9 as scratch registers, \
839 the rest as call-preserved registers. */ \
840 for (regno = FIRST_IWMMXT_REGNUM; \
841 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
843 fixed_regs[regno] = 0; \
844 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
848 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
850 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
851 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
853 else if (TARGET_APCS_STACK) \
855 fixed_regs[10] = 1; \
856 call_used_regs[10] = 1; \
858 /* -mcaller-super-interworking reserves r11 for calls to \
859 _interwork_r11_call_via_rN(). Making the register global \
860 is an easy way of ensuring that it remains valid for all \
862 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
863 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
865 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
866 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
867 if (TARGET_CALLER_INTERWORKING) \
868 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
870 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
873 /* These are a couple of extensions to the formats accepted
875 %@ prints out ASM_COMMENT_START
876 %r prints out REGISTER_PREFIX reg_names[arg] */
877 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
879 fputs (ASM_COMMENT_START, FILE); \
883 fputs (REGISTER_PREFIX, FILE); \
884 fputs (reg_names [va_arg (ARGS, int)], FILE); \
887 /* Round X up to the nearest word. */
888 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
890 /* Convert fron bytes to ints. */
891 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
893 /* The number of (integer) registers required to hold a quantity of type MODE.
894 Also used for VFP registers. */
895 #define ARM_NUM_REGS(MODE) \
896 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
898 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
899 #define ARM_NUM_REGS2(MODE, TYPE) \
900 ARM_NUM_INTS ((MODE) == BLKmode ? \
901 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
903 /* The number of (integer) argument register available. */
904 #define NUM_ARG_REGS 4
906 /* And similarly for the VFP. */
907 #define NUM_VFP_ARG_REGS 16
909 /* Return the register number of the N'th (integer) argument. */
910 #define ARG_REGISTER(N) (N - 1)
912 /* Specify the registers used for certain standard purposes.
913 The values of these macros are register numbers. */
915 /* The number of the last argument register. */
916 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
918 /* The numbers of the Thumb register ranges. */
919 #define FIRST_LO_REGNUM 0
920 #define LAST_LO_REGNUM 7
921 #define FIRST_HI_REGNUM 8
922 #define LAST_HI_REGNUM 11
924 #ifndef TARGET_UNWIND_INFO
925 /* We use sjlj exceptions for backwards compatibility. */
926 #define MUST_USE_SJLJ_EXCEPTIONS 1
929 /* We can generate DWARF2 Unwind info, even though we don't use it. */
930 #define DWARF2_UNWIND_INFO 1
932 /* Use r0 and r1 to pass exception handling information. */
933 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
935 /* The register that holds the return address in exception handlers. */
936 #define ARM_EH_STACKADJ_REGNUM 2
937 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
939 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
940 as an invisible last argument (possible since varargs don't exist in
941 Pascal), so the following is not true. */
942 #define STATIC_CHAIN_REGNUM 12
944 /* Define this to be where the real frame pointer is if it is not possible to
945 work out the offset between the frame pointer and the automatic variables
946 until after register allocation has taken place. FRAME_POINTER_REGNUM
947 should point to a special register that we will make sure is eliminated.
949 For the Thumb we have another problem. The TPCS defines the frame pointer
950 as r11, and GCC believes that it is always possible to use the frame pointer
951 as base register for addressing purposes. (See comments in
952 find_reloads_address()). But - the Thumb does not allow high registers,
953 including r11, to be used as base address registers. Hence our problem.
955 The solution used here, and in the old thumb port is to use r7 instead of
956 r11 as the hard frame pointer and to have special code to generate
957 backtrace structures on the stack (if required to do so via a command line
958 option) using r11. This is the only 'user visible' use of r11 as a frame
960 #define ARM_HARD_FRAME_POINTER_REGNUM 11
961 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
963 #define HARD_FRAME_POINTER_REGNUM \
965 ? ARM_HARD_FRAME_POINTER_REGNUM \
966 : THUMB_HARD_FRAME_POINTER_REGNUM)
968 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
970 /* Register to use for pushing function arguments. */
971 #define STACK_POINTER_REGNUM SP_REGNUM
973 /* ARM floating pointer registers. */
974 #define FIRST_FPA_REGNUM 16
975 #define LAST_FPA_REGNUM 23
976 #define IS_FPA_REGNUM(REGNUM) \
977 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
979 #define FIRST_IWMMXT_GR_REGNUM 43
980 #define LAST_IWMMXT_GR_REGNUM 46
981 #define FIRST_IWMMXT_REGNUM 47
982 #define LAST_IWMMXT_REGNUM 62
983 #define IS_IWMMXT_REGNUM(REGNUM) \
984 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
985 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
986 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
988 /* Base register for access to local variables of the function. */
989 #define FRAME_POINTER_REGNUM 25
991 /* Base register for access to arguments of the function. */
992 #define ARG_POINTER_REGNUM 26
994 #define FIRST_CIRRUS_FP_REGNUM 27
995 #define LAST_CIRRUS_FP_REGNUM 42
996 #define IS_CIRRUS_REGNUM(REGNUM) \
997 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
999 #define FIRST_VFP_REGNUM 63
1000 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
1001 #define LAST_VFP_REGNUM \
1002 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1004 #define IS_VFP_REGNUM(REGNUM) \
1005 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1007 /* VFP registers are split into two types: those defined by VFP versions < 3
1008 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1009 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1010 in various parts of the backend, we implement as "fake" single-precision
1011 registers (which would be S32-S63, but cannot be used in that way). The
1012 following macros define these ranges of registers. */
1013 #define LAST_LO_VFP_REGNUM 94
1014 #define FIRST_HI_VFP_REGNUM 95
1015 #define LAST_HI_VFP_REGNUM 126
1017 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1018 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1020 /* DFmode values are only valid in even register pairs. */
1021 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1022 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1024 /* Neon Quad values must start at a multiple of four registers. */
1025 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1026 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1028 /* Neon structures of vectors must be in even register pairs and there
1029 must be enough registers available. Because of various patterns
1030 requiring quad registers, we require them to start at a multiple of
1032 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1033 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1034 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1036 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1037 /* + 16 Cirrus registers take us up to 43. */
1038 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1039 /* VFP (VFP3) adds 32 (64) + 1 more. */
1040 #define FIRST_PSEUDO_REGISTER 128
1042 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1044 /* Value should be nonzero if functions must have frame pointers.
1045 Zero means the frame pointer need not be set up (and parms may be accessed
1046 via the stack pointer) in functions that seem suitable.
1047 If we have to have a frame pointer we might as well make use of it.
1048 APCS says that the frame pointer does not need to be pushed in leaf
1049 functions, or simple tail call functions. */
1051 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1052 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1055 /* Return number of consecutive hard regs needed starting at reg REGNO
1056 to hold something of mode MODE.
1057 This is ordinarily the length in words of a value of mode MODE
1058 but can be less for certain modes in special long registers.
1060 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1062 #define HARD_REGNO_NREGS(REGNO, MODE) \
1064 && REGNO >= FIRST_FPA_REGNUM \
1065 && REGNO != FRAME_POINTER_REGNUM \
1066 && REGNO != ARG_POINTER_REGNUM) \
1067 && !IS_VFP_REGNUM (REGNO) \
1068 ? 1 : ARM_NUM_REGS (MODE))
1070 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1071 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1072 arm_hard_regno_mode_ok ((REGNO), (MODE))
1074 /* Value is 1 if it is a good idea to tie two pseudo registers
1075 when one has mode MODE1 and one has mode MODE2.
1076 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1077 for any hard reg, then this must be 0 for correct output. */
1078 #define MODES_TIEABLE_P(MODE1, MODE2) \
1079 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1081 #define VALID_IWMMXT_REG_MODE(MODE) \
1082 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1084 /* Modes valid for Neon D registers. */
1085 #define VALID_NEON_DREG_MODE(MODE) \
1086 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1087 || (MODE) == V2SFmode || (MODE) == DImode)
1089 /* Modes valid for Neon Q registers. */
1090 #define VALID_NEON_QREG_MODE(MODE) \
1091 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1092 || (MODE) == V4SFmode || (MODE) == V2DImode)
1094 /* Structure modes valid for Neon registers. */
1095 #define VALID_NEON_STRUCT_MODE(MODE) \
1096 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1097 || (MODE) == CImode || (MODE) == XImode)
1099 /* The order in which register should be allocated. It is good to use ip
1100 since no saving is required (though calls clobber it) and it never contains
1101 function parameters. It is quite good to use lr since other calls may
1102 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1103 least likely to contain a function parameter; in addition results are
1105 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1106 then D8-D15. The reason for doing this is to attempt to reduce register
1107 pressure when both single- and double-precision registers are used in a
1110 #define REG_ALLOC_ORDER \
1112 3, 2, 1, 0, 12, 14, 4, 5, \
1113 6, 7, 8, 10, 9, 11, 13, 15, \
1114 16, 17, 18, 19, 20, 21, 22, 23, \
1115 27, 28, 29, 30, 31, 32, 33, 34, \
1116 35, 36, 37, 38, 39, 40, 41, 42, \
1117 43, 44, 45, 46, 47, 48, 49, 50, \
1118 51, 52, 53, 54, 55, 56, 57, 58, \
1121 95, 96, 97, 98, 99, 100, 101, 102, \
1122 103, 104, 105, 106, 107, 108, 109, 110, \
1123 111, 112, 113, 114, 115, 116, 117, 118, \
1124 119, 120, 121, 122, 123, 124, 125, 126, \
1125 78, 77, 76, 75, 74, 73, 72, 71, \
1126 70, 69, 68, 67, 66, 65, 64, 63, \
1127 79, 80, 81, 82, 83, 84, 85, 86, \
1128 87, 88, 89, 90, 91, 92, 93, 94, \
1132 /* Use different register alloc ordering for Thumb. */
1133 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1135 /* Tell IRA to use the order we define rather than messing it up with its
1136 own cost calculations. */
1137 #define HONOR_REG_ALLOC_ORDER
1139 /* Interrupt functions can only use registers that have already been
1140 saved by the prologue, even if they would normally be
1142 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1143 (! IS_INTERRUPT (cfun->machine->func_type) || \
1144 df_regs_ever_live_p (DST))
1146 /* Register and constant classes. */
1148 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1149 Now that the Thumb is involved it has become more complicated. */
1173 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1175 /* Give names of register classes as strings for dump file. */
1176 #define REG_CLASS_NAMES \
1198 /* Define which registers fit in which classes.
1199 This is an initializer for a vector of HARD_REG_SET
1200 of length N_REG_CLASSES. */
1201 #define REG_CLASS_CONTENTS \
1203 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1204 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1205 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1206 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1207 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1208 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1209 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1210 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1211 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1212 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1213 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1214 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1215 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1216 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1217 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1218 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1219 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1220 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1223 /* Any of the VFP register classes. */
1224 #define IS_VFP_CLASS(X) \
1225 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1226 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1228 /* The same information, inverted:
1229 Return the class number of the smallest class containing
1230 reg number REGNO. This could be a conditional expression
1231 or could index an array. */
1232 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1234 /* The following macro defines cover classes for Integrated Register
1235 Allocator. Cover classes is a set of non-intersected register
1236 classes covering all hard registers used for register allocation
1237 purpose. Any move between two registers of a cover class should be
1238 cheaper than load or store of the registers. The macro value is
1239 array of register classes with LIM_REG_CLASSES used as the end
1242 #define IRA_COVER_CLASSES \
1244 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1248 /* FPA registers can't do subreg as all values are reformatted to internal
1249 precision. VFP registers may only be accessed in the mode they
1251 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1252 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1253 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1254 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1257 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1258 using r0-r4 for function arguments, r7 for the stack frame and don't
1259 have enough left over to do doubleword arithmetic. */
1260 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1261 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1262 || (CLASS) == CC_REG)
1264 /* The class value for index registers, and the one for base regs. */
1265 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1266 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1268 /* For the Thumb the high registers cannot be used as base registers
1269 when addressing quantities in QI or HI mode; if we don't know the
1270 mode, then we must be conservative. */
1271 #define MODE_BASE_REG_CLASS(MODE) \
1272 (TARGET_32BIT ? CORE_REGS : \
1273 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1275 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1276 instead of BASE_REGS. */
1277 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1279 /* When this hook returns true for MODE, the compiler allows
1280 registers explicitly used in the rtl to be used as spill registers
1281 but prevents the compiler from extending the lifetime of these
1283 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1284 arm_small_register_classes_for_mode_p
1286 /* Given an rtx X being reloaded into a reg required to be
1287 in class CLASS, return the class of reg to actually use.
1288 In general this is just CLASS, but for the Thumb core registers and
1289 immediate constants we prefer a LO_REGS class or a subset. */
1290 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1291 (TARGET_32BIT ? (CLASS) : \
1292 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1293 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1294 ? LO_REGS : (CLASS)))
1296 /* Must leave BASE_REGS reloads alone */
1297 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1298 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1299 ? ((true_regnum (X) == -1 ? LO_REGS \
1300 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1304 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1305 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1306 ? ((true_regnum (X) == -1 ? LO_REGS \
1307 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1311 /* Return the register class of a scratch register needed to copy IN into
1312 or out of a register in CLASS in MODE. If it can be done directly,
1313 NO_REGS is returned. */
1314 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1315 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1316 ((TARGET_VFP && TARGET_HARD_FLOAT \
1317 && IS_VFP_CLASS (CLASS)) \
1318 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1319 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1320 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1322 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1323 ? GENERAL_REGS : NO_REGS) \
1324 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1326 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1327 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1328 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1329 ((TARGET_VFP && TARGET_HARD_FLOAT \
1330 && IS_VFP_CLASS (CLASS)) \
1331 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1332 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1333 coproc_secondary_reload_class (MODE, X, TRUE) : \
1334 /* Cannot load constants into Cirrus registers. */ \
1335 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1336 && (CLASS) == CIRRUS_REGS \
1337 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1340 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1341 && CONSTANT_P (X)) \
1343 (((MODE) == HImode && ! arm_arch4 \
1344 && (GET_CODE (X) == MEM \
1345 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1346 && true_regnum (X) == -1))) \
1347 ? GENERAL_REGS : NO_REGS) \
1348 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1350 /* Try a machine-dependent way of reloading an illegitimate address
1351 operand. If we find one, push the reload and jump to WIN. This
1352 macro is used in only one place: `find_reloads_address' in reload.c.
1354 For the ARM, we wish to handle large displacements off a base
1355 register by splitting the addend across a MOV and the mem insn.
1356 This can cut the number of reloads needed. */
1357 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1360 if (GET_CODE (X) == PLUS \
1361 && GET_CODE (XEXP (X, 0)) == REG \
1362 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1363 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1364 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1366 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1367 HOST_WIDE_INT low, high; \
1369 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1370 low = ((val & 0xf) ^ 0x8) - 0x8; \
1371 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1372 /* Need to be careful, -256 is not a valid offset. */ \
1373 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1374 else if (MODE == SImode \
1375 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1376 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1377 /* Need to be careful, -4096 is not a valid offset. */ \
1378 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1379 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1380 /* Need to be careful, -256 is not a valid offset. */ \
1381 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1382 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1383 && TARGET_HARD_FLOAT && TARGET_FPA) \
1384 /* Need to be careful, -1024 is not a valid offset. */ \
1385 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1389 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1390 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1391 - (unsigned HOST_WIDE_INT) 0x80000000); \
1392 /* Check for overflow or zero */ \
1393 if (low == 0 || high == 0 || (high + low != val)) \
1396 /* Reload the high part into a base reg; leave the low part \
1398 X = gen_rtx_PLUS (GET_MODE (X), \
1399 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1402 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1403 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1404 VOIDmode, 0, 0, OPNUM, TYPE); \
1410 /* XXX If an HImode FP+large_offset address is converted to an HImode
1411 SP+large_offset address, then reload won't know how to fix it. It sees
1412 only that SP isn't valid for HImode, and so reloads the SP into an index
1413 register, but the resulting address is still invalid because the offset
1414 is too big. We fix it here instead by reloading the entire address. */
1415 /* We could probably achieve better results by defining PROMOTE_MODE to help
1416 cope with the variances between the Thumb's signed and unsigned byte and
1417 halfword load instructions. */
1418 /* ??? This should be safe for thumb2, but we may be able to do better. */
1419 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1421 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1429 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1431 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1433 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1435 /* Return the maximum number of consecutive registers
1436 needed to represent mode MODE in a register of class CLASS.
1437 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1438 #define CLASS_MAX_NREGS(CLASS, MODE) \
1439 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1441 /* If defined, gives a class of registers that cannot be used as the
1442 operand of a SUBREG that changes the mode of the object illegally. */
1444 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1445 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1446 it is typically more expensive than a single memory access. We set
1447 the cost to less than two memory accesses so that floating
1448 point to integer conversion does not go through memory. */
1449 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1451 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1452 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1453 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1454 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1455 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1456 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1457 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1458 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1459 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1462 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1464 /* Stack layout; function entry, exit and calling. */
1466 /* Define this if pushing a word on the stack
1467 makes the stack pointer a smaller address. */
1468 #define STACK_GROWS_DOWNWARD 1
1470 /* Define this to nonzero if the nominal address of the stack frame
1471 is at the high-address end of the local variables;
1472 that is, each additional local variable allocated
1473 goes at a more negative offset in the frame. */
1474 #define FRAME_GROWS_DOWNWARD 1
1476 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1477 When present, it is one word in size, and sits at the top of the frame,
1478 between the soft frame pointer and either r7 or r11.
1480 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1481 and only then if some outgoing arguments are passed on the stack. It would
1482 be tempting to also check whether the stack arguments are passed by indirect
1483 calls, but there seems to be no reason in principle why a post-reload pass
1484 couldn't convert a direct call into an indirect one. */
1485 #define CALLER_INTERWORKING_SLOT_SIZE \
1486 (TARGET_CALLER_INTERWORKING \
1487 && crtl->outgoing_args_size != 0 \
1488 ? UNITS_PER_WORD : 0)
1490 /* Offset within stack frame to start allocating local variables at.
1491 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1492 first local allocated. Otherwise, it is the offset to the BEGINNING
1493 of the first local allocated. */
1494 #define STARTING_FRAME_OFFSET 0
1496 /* If we generate an insn to push BYTES bytes,
1497 this says how many the stack pointer really advances by. */
1498 /* The push insns do not do this rounding implicitly.
1499 So don't define this. */
1500 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1502 /* Define this if the maximum size of all the outgoing args is to be
1503 accumulated and pushed during the prologue. The amount can be
1504 found in the variable crtl->outgoing_args_size. */
1505 #define ACCUMULATE_OUTGOING_ARGS 1
1507 /* Offset of first parameter from the argument pointer register value. */
1508 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1510 /* Define how to find the value returned by a library function
1511 assuming the value has mode MODE. */
1512 #define LIBCALL_VALUE(MODE) \
1513 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1514 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1515 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1516 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1517 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1518 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1519 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1520 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1521 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1522 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1524 /* 1 if REGNO is a possible register number for a function value. */
1525 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1526 ((REGNO) == ARG_REGISTER (1) \
1527 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1528 && TARGET_VFP && TARGET_HARD_FLOAT \
1529 && (REGNO) == FIRST_VFP_REGNUM) \
1530 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1531 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1532 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1533 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1534 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1536 /* Amount of memory needed for an untyped call to save all possible return
1538 #define APPLY_RESULT_SIZE arm_apply_result_size()
1540 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1541 values must be in memory. On the ARM, they need only do so if larger
1542 than a word, or if they contain elements offset from zero in the struct. */
1543 #define DEFAULT_PCC_STRUCT_RETURN 0
1545 /* These bits describe the different types of function supported
1546 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1547 normal function and an interworked function, for example. Knowing the
1548 type of a function is important for determining its prologue and
1550 Note value 7 is currently unassigned. Also note that the interrupt
1551 function types all have bit 2 set, so that they can be tested for easily.
1552 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1553 machine_function structure is initialized (to zero) func_type will
1554 default to unknown. This will force the first use of arm_current_func_type
1555 to call arm_compute_func_type. */
1556 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1557 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1558 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1559 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1560 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1561 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1563 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1565 /* In addition functions can have several type modifiers,
1566 outlined by these bit masks: */
1567 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1568 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1569 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1570 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1571 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1573 /* Some macros to test these flags. */
1574 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1575 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1576 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1577 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1578 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1579 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1582 /* Structure used to hold the function stack frame layout. Offsets are
1583 relative to the stack pointer on function entry. Positive offsets are
1584 in the direction of stack growth.
1585 Only soft_frame is used in thumb mode. */
1587 typedef struct GTY(()) arm_stack_offsets
1589 int saved_args; /* ARG_POINTER_REGNUM. */
1590 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1592 int soft_frame; /* FRAME_POINTER_REGNUM. */
1593 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1594 int outgoing_args; /* STACK_POINTER_REGNUM. */
1595 unsigned int saved_regs_mask;
1599 #ifndef GENERATOR_FILE
1600 /* A C structure for machine-specific, per-function data.
1601 This is added to the cfun structure. */
1602 typedef struct GTY(()) machine_function
1604 /* Additional stack adjustment in __builtin_eh_throw. */
1605 rtx eh_epilogue_sp_ofs;
1606 /* Records if LR has to be saved for far jumps. */
1608 /* Records if ARG_POINTER was ever live. */
1609 int arg_pointer_live;
1610 /* Records if the save of LR has been eliminated. */
1611 int lr_save_eliminated;
1612 /* The size of the stack frame. Only valid after reload. */
1613 arm_stack_offsets stack_offsets;
1614 /* Records the type of the current function. */
1615 unsigned long func_type;
1616 /* Record if the function has a variable argument list. */
1617 int uses_anonymous_args;
1618 /* Records if sibcalls are blocked because an argument
1619 register is needed to preserve stack alignment. */
1620 int sibcall_blocked;
1621 /* The PIC register for this function. This might be a pseudo. */
1623 /* Labels for per-function Thumb call-via stubs. One per potential calling
1624 register. We can never call via LR or PC. We can call via SP if a
1625 trampoline happens to be on the top of the stack. */
1627 /* Set to 1 when a return insn is output, this means that the epilogue
1629 int return_used_this_function;
1630 /* When outputting Thumb-1 code, record the last insn that provides
1631 information about condition codes, and the comparison operands. */
1635 /* Also record the CC mode that is supported. */
1636 enum machine_mode thumb1_cc_mode;
1641 /* As in the machine_function, a global set of call-via labels, for code
1642 that is in text_section. */
1643 extern GTY(()) rtx thumb_call_via_label[14];
1645 /* The number of potential ways of assigning to a co-processor. */
1646 #define ARM_NUM_COPROC_SLOTS 1
1648 /* Enumeration of procedure calling standard variants. We don't really
1649 support all of these yet. */
1652 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1653 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1654 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1655 /* This must be the last AAPCS variant. */
1656 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1657 ARM_PCS_ATPCS, /* ATPCS. */
1658 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1662 /* Default procedure calling standard of current compilation unit. */
1663 extern enum arm_pcs arm_pcs_default;
1665 /* A C type for declaring a variable that is used as the first argument of
1666 `FUNCTION_ARG' and other related values. */
1669 /* This is the number of registers of arguments scanned so far. */
1671 /* This is the number of iWMMXt register arguments scanned so far. */
1675 /* Which procedure call variant to use for this call. */
1676 enum arm_pcs pcs_variant;
1678 /* AAPCS related state tracking. */
1679 int aapcs_arg_processed; /* No need to lay out this argument again. */
1680 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1681 this argument, or -1 if using core
1684 int aapcs_next_ncrn;
1685 rtx aapcs_reg; /* Register assigned to this argument. */
1686 int aapcs_partial; /* How many bytes are passed in regs (if
1687 split between core regs and stack.
1689 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1690 int can_split; /* Argument can be split between core regs
1692 /* Private data for tracking VFP register allocation */
1693 unsigned aapcs_vfp_regs_free;
1694 unsigned aapcs_vfp_reg_alloc;
1695 int aapcs_vfp_rcount;
1696 MACHMODE aapcs_vfp_rmode;
1699 /* Define where to put the arguments to a function.
1700 Value is zero to push the argument on the stack,
1701 or a hard register in which to store the argument.
1703 MODE is the argument's machine mode.
1704 TYPE is the data type of the argument (as a tree).
1705 This is null for libcalls where that information may
1707 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1708 the preceding args and about the function being called.
1709 NAMED is nonzero if this argument is a named parameter
1710 (otherwise it is an extra parameter matching an ellipsis).
1712 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1713 other arguments are passed on the stack. If (NAMED == 0) (which happens
1714 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1715 defined), say it is passed in the stack (function_prologue will
1716 indeed make it pass in the stack if necessary). */
1717 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1718 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1720 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1721 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1723 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1724 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1726 /* For AAPCS, padding should never be below the argument. For other ABIs,
1727 * mimic the default. */
1728 #define PAD_VARARGS_DOWN \
1729 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1731 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1732 for a call to a function whose data type is FNTYPE.
1733 For a library call, FNTYPE is 0.
1734 On the ARM, the offset starts at 0. */
1735 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1736 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1738 /* Update the data in CUM to advance over an argument
1739 of mode MODE and data type TYPE.
1740 (TYPE is null for libcalls where that information may not be available.) */
1741 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1742 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1744 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1745 argument with the specified mode and type. If it is not defined,
1746 `PARM_BOUNDARY' is used for all arguments. */
1747 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1748 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1749 ? DOUBLEWORD_ALIGNMENT \
1752 /* 1 if N is a possible register number for function argument passing.
1753 On the ARM, r0-r3 are used to pass args. */
1754 #define FUNCTION_ARG_REGNO_P(REGNO) \
1755 (IN_RANGE ((REGNO), 0, 3) \
1756 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1757 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1758 || (TARGET_IWMMXT_ABI \
1759 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1762 /* If your target environment doesn't prefix user functions with an
1763 underscore, you may wish to re-define this to prevent any conflicts. */
1764 #ifndef ARM_MCOUNT_NAME
1765 #define ARM_MCOUNT_NAME "*mcount"
1768 /* Call the function profiler with a given profile label. The Acorn
1769 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1770 On the ARM the full profile code will look like:
1779 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1780 will output the .text section.
1782 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1783 ``prof'' doesn't seem to mind about this!
1785 Note - this version of the code is designed to work in both ARM and
1787 #ifndef ARM_FUNCTION_PROFILER
1788 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1793 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1794 IP_REGNUM, LR_REGNUM); \
1795 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1796 fputc ('\n', STREAM); \
1797 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1798 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1799 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1803 #ifdef THUMB_FUNCTION_PROFILER
1804 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1806 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1808 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1810 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1811 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1814 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1815 the stack pointer does not matter. The value is tested only in
1816 functions that have frame pointers.
1817 No definition is equivalent to always zero.
1819 On the ARM, the function epilogue recovers the stack pointer from the
1821 #define EXIT_IGNORE_STACK 1
1823 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1825 /* Determine if the epilogue should be output as RTL.
1826 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1827 #define USE_RETURN_INSN(ISCOND) \
1828 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1830 /* Definitions for register eliminations.
1832 This is an array of structures. Each structure initializes one pair
1833 of eliminable registers. The "from" register number is given first,
1834 followed by "to". Eliminations of the same "from" register are listed
1835 in order of preference.
1837 We have two registers that can be eliminated on the ARM. First, the
1838 arg pointer register can often be eliminated in favor of the stack
1839 pointer register. Secondly, the pseudo frame pointer register can always
1840 be eliminated; it is replaced with either the stack or the real frame
1841 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1842 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1844 #define ELIMINABLE_REGS \
1845 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1846 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1847 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1848 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1849 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1850 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1851 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1853 /* Define the offset between two registers, one to be eliminated, and the
1854 other its replacement, at the start of a routine. */
1855 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1857 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1859 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1861 /* Special case handling of the location of arguments passed on the stack. */
1862 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1864 /* Initialize data used by insn expanders. This is called from insn_emit,
1865 once for every function before code is generated. */
1866 #define INIT_EXPANDERS arm_init_expanders ()
1868 /* Length in units of the trampoline for entering a nested function. */
1869 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1871 /* Alignment required for a trampoline in bits. */
1872 #define TRAMPOLINE_ALIGNMENT 32
1874 /* Addressing modes, and classification of registers for them. */
1875 #define HAVE_POST_INCREMENT 1
1876 #define HAVE_PRE_INCREMENT TARGET_32BIT
1877 #define HAVE_POST_DECREMENT TARGET_32BIT
1878 #define HAVE_PRE_DECREMENT TARGET_32BIT
1879 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1880 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1881 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1882 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1884 /* Macros to check register numbers against specific register classes. */
1886 /* These assume that REGNO is a hard or pseudo reg number.
1887 They give nonzero only if REGNO is a hard reg of the suitable class
1888 or a pseudo reg currently allocated to a suitable hard reg.
1889 Since they use reg_renumber, they are safe only once reg_renumber
1890 has been allocated, which happens in local-alloc.c. */
1891 #define TEST_REGNO(R, TEST, VALUE) \
1892 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1894 /* Don't allow the pc to be used. */
1895 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1896 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1897 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1898 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1900 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1901 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1902 || (GET_MODE_SIZE (MODE) >= 4 \
1903 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1905 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1907 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1908 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1910 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1911 For Thumb, we can not use SP + reg, so reject SP. */
1912 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1913 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1915 /* For ARM code, we don't care about the mode, but for Thumb, the index
1916 must be suitable for use in a QImode load. */
1917 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1918 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1919 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1921 /* Maximum number of registers that can appear in a valid memory address.
1922 Shifts in addresses can't be by a register. */
1923 #define MAX_REGS_PER_ADDRESS 2
1925 /* Recognize any constant value that is a valid address. */
1926 /* XXX We can address any constant, eventually... */
1927 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1928 #define CONSTANT_ADDRESS_P(X) \
1929 (GET_CODE (X) == SYMBOL_REF \
1930 && (CONSTANT_POOL_ADDRESS_P (X) \
1931 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1933 /* True if SYMBOL + OFFSET constants must refer to something within
1934 SYMBOL's section. */
1935 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1937 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1938 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1939 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1942 /* Nonzero if the constant value X is a legitimate general operand.
1943 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1945 On the ARM, allow any integer (invalid ones are removed later by insn
1946 patterns), nice doubles and symbol_refs which refer to the function's
1949 When generating pic allow anything. */
1950 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1952 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1953 ( GET_CODE (X) == CONST_INT \
1954 || GET_CODE (X) == CONST_DOUBLE \
1955 || CONSTANT_ADDRESS_P (X) \
1958 #define LEGITIMATE_CONSTANT_P(X) \
1959 (!arm_cannot_force_const_mem (X) \
1960 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1961 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1963 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1964 #define SUBTARGET_NAME_ENCODING_LENGTHS
1967 /* This is a C fragment for the inside of a switch statement.
1968 Each case label should return the number of characters to
1969 be stripped from the start of a function's name, if that
1970 name starts with the indicated character. */
1971 #define ARM_NAME_ENCODING_LENGTHS \
1972 case '*': return 1; \
1973 SUBTARGET_NAME_ENCODING_LENGTHS
1975 /* This is how to output a reference to a user-level label named NAME.
1976 `assemble_name' uses this. */
1977 #undef ASM_OUTPUT_LABELREF
1978 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1979 arm_asm_output_labelref (FILE, NAME)
1981 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1982 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1983 if (TARGET_THUMB2) \
1984 thumb2_asm_output_opcode (STREAM);
1986 /* The EABI specifies that constructors should go in .init_array.
1987 Other targets use .ctors for compatibility. */
1988 #ifndef ARM_EABI_CTORS_SECTION_OP
1989 #define ARM_EABI_CTORS_SECTION_OP \
1990 "\t.section\t.init_array,\"aw\",%init_array"
1992 #ifndef ARM_EABI_DTORS_SECTION_OP
1993 #define ARM_EABI_DTORS_SECTION_OP \
1994 "\t.section\t.fini_array,\"aw\",%fini_array"
1996 #define ARM_CTORS_SECTION_OP \
1997 "\t.section\t.ctors,\"aw\",%progbits"
1998 #define ARM_DTORS_SECTION_OP \
1999 "\t.section\t.dtors,\"aw\",%progbits"
2001 /* Define CTORS_SECTION_ASM_OP. */
2002 #undef CTORS_SECTION_ASM_OP
2003 #undef DTORS_SECTION_ASM_OP
2005 # define CTORS_SECTION_ASM_OP \
2006 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2007 # define DTORS_SECTION_ASM_OP \
2008 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2009 #else /* !defined (IN_LIBGCC2) */
2010 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2011 so we cannot use the definition above. */
2012 # ifdef __ARM_EABI__
2013 /* The .ctors section is not part of the EABI, so we do not define
2014 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2015 from trying to use it. We do define it when doing normal
2016 compilation, as .init_array can be used instead of .ctors. */
2017 /* There is no need to emit begin or end markers when using
2018 init_array; the dynamic linker will compute the size of the
2019 array itself based on special symbols created by the static
2020 linker. However, we do need to arrange to set up
2021 exception-handling here. */
2022 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2023 # define CTOR_LIST_END /* empty */
2024 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2025 # define DTOR_LIST_END /* empty */
2026 # else /* !defined (__ARM_EABI__) */
2027 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2028 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2029 # endif /* !defined (__ARM_EABI__) */
2030 #endif /* !defined (IN_LIBCC2) */
2032 /* True if the operating system can merge entities with vague linkage
2033 (e.g., symbols in COMDAT group) during dynamic linking. */
2034 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2035 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2038 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2040 #ifdef TARGET_UNWIND_INFO
2041 #define ARM_EABI_UNWIND_TABLES \
2042 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2044 #define ARM_EABI_UNWIND_TABLES 0
2047 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2048 and check its validity for a certain class.
2049 We have two alternate definitions for each of them.
2050 The usual definition accepts all pseudo regs; the other rejects
2051 them unless they have been allocated suitable hard regs.
2052 The symbol REG_OK_STRICT causes the latter definition to be used.
2053 Thumb-2 has the same restrictions as arm. */
2054 #ifndef REG_OK_STRICT
2056 #define ARM_REG_OK_FOR_BASE_P(X) \
2057 (REGNO (X) <= LAST_ARM_REGNUM \
2058 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2059 || REGNO (X) == FRAME_POINTER_REGNUM \
2060 || REGNO (X) == ARG_POINTER_REGNUM)
2062 #define ARM_REG_OK_FOR_INDEX_P(X) \
2063 ((REGNO (X) <= LAST_ARM_REGNUM \
2064 && REGNO (X) != STACK_POINTER_REGNUM) \
2065 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2066 || REGNO (X) == FRAME_POINTER_REGNUM \
2067 || REGNO (X) == ARG_POINTER_REGNUM)
2069 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2070 (REGNO (X) <= LAST_LO_REGNUM \
2071 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2072 || (GET_MODE_SIZE (MODE) >= 4 \
2073 && (REGNO (X) == STACK_POINTER_REGNUM \
2074 || (X) == hard_frame_pointer_rtx \
2075 || (X) == arg_pointer_rtx)))
2077 #define REG_STRICT_P 0
2079 #else /* REG_OK_STRICT */
2081 #define ARM_REG_OK_FOR_BASE_P(X) \
2082 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2084 #define ARM_REG_OK_FOR_INDEX_P(X) \
2085 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2087 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2088 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2090 #define REG_STRICT_P 1
2092 #endif /* REG_OK_STRICT */
2094 /* Now define some helpers in terms of the above. */
2096 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2098 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2099 : ARM_REG_OK_FOR_BASE_P (X))
2101 /* For 16-bit Thumb, a valid index register is anything that can be used in
2102 a byte load instruction. */
2103 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2104 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2106 /* Nonzero if X is a hard reg that can be used as an index
2107 or if it is a pseudo reg. On the Thumb, the stack pointer
2109 #define REG_OK_FOR_INDEX_P(X) \
2111 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2112 : ARM_REG_OK_FOR_INDEX_P (X))
2114 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2115 For Thumb, we can not use SP + reg, so reject SP. */
2116 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2117 REG_OK_FOR_INDEX_P (X)
2119 #define ARM_BASE_REGISTER_RTX_P(X) \
2120 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2122 #define ARM_INDEX_REGISTER_RTX_P(X) \
2123 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2125 /* Define this for compatibility reasons. */
2126 #define HANDLE_PRAGMA_PACK_PUSH_POP
2128 /* Specify the machine mode that this machine uses
2129 for the index in the tablejump instruction. */
2130 #define CASE_VECTOR_MODE Pmode
2132 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2134 && (optimize_size || flag_pic)))
2136 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2138 ? (min >= 0 && max < 512 \
2139 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2140 : min >= -256 && max < 256 \
2141 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2142 : min >= 0 && max < 8192 \
2143 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2144 : min >= -4096 && max < 4096 \
2145 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2147 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2148 : (max >= 0x200) ? HImode \
2151 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2152 unsigned is probably best, but may break some code. */
2153 #ifndef DEFAULT_SIGNED_CHAR
2154 #define DEFAULT_SIGNED_CHAR 0
2157 /* Max number of bytes we can move from memory to memory
2158 in one reasonably fast instruction. */
2162 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2164 /* Define if operations between registers always perform the operation
2165 on the full register even if a narrower mode is specified. */
2166 #define WORD_REGISTER_OPERATIONS
2168 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2169 will either zero-extend or sign-extend. The value of this macro should
2170 be the code that says which one of the two operations is implicitly
2171 done, UNKNOWN if none. */
2172 #define LOAD_EXTEND_OP(MODE) \
2173 (TARGET_THUMB ? ZERO_EXTEND : \
2174 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2175 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2177 /* Nonzero if access to memory by bytes is slow and undesirable. */
2178 #define SLOW_BYTE_ACCESS 0
2180 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2182 /* Immediate shift counts are truncated by the output routines (or was it
2183 the assembler?). Shift counts in a register are truncated by ARM. Note
2184 that the native compiler puts too large (> 32) immediate shift counts
2185 into a register and shifts by the register, letting the ARM decide what
2186 to do instead of doing that itself. */
2187 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2188 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2189 On the arm, Y in a register is used modulo 256 for the shift. Only for
2190 rotates is modulo 32 used. */
2191 /* #define SHIFT_COUNT_TRUNCATED 1 */
2193 /* All integers have the same format so truncation is easy. */
2194 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2196 /* Calling from registers is a massive pain. */
2197 #define NO_FUNCTION_CSE 1
2199 /* The machine modes of pointers and functions */
2200 #define Pmode SImode
2201 #define FUNCTION_MODE Pmode
2203 #define ARM_FRAME_RTX(X) \
2204 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2205 || (X) == arg_pointer_rtx)
2207 /* Moves to and from memory are quite expensive */
2208 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2209 (TARGET_32BIT ? 10 : \
2210 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2211 * (CLASS == LO_REGS ? 1 : 2)))
2213 /* Try to generate sequences that don't involve branches, we can then use
2214 conditional instructions */
2215 #define BRANCH_COST(speed_p, predictable_p) \
2216 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2218 /* Position Independent Code. */
2219 /* We decide which register to use based on the compilation options and
2220 the assembler in use; this is more general than the APCS restriction of
2221 using sb (r9) all the time. */
2222 extern unsigned arm_pic_register;
2224 /* The register number of the register used to address a table of static
2225 data addresses in memory. */
2226 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2228 /* We can't directly access anything that contains a symbol,
2229 nor can we indirect via the constant pool. One exception is
2230 UNSPEC_TLS, which is always PIC. */
2231 #define LEGITIMATE_PIC_OPERAND_P(X) \
2232 (!(symbol_mentioned_p (X) \
2233 || label_mentioned_p (X) \
2234 || (GET_CODE (X) == SYMBOL_REF \
2235 && CONSTANT_POOL_ADDRESS_P (X) \
2236 && (symbol_mentioned_p (get_pool_constant (X)) \
2237 || label_mentioned_p (get_pool_constant (X))))) \
2238 || tls_mentioned_p (X))
2240 /* We need to know when we are making a constant pool; this determines
2241 whether data needs to be in the GOT or can be referenced via a GOT
2243 extern int making_const_table;
2245 /* Handle pragmas for compatibility with Intel's compilers. */
2246 /* Also abuse this to register additional C specific EABI attributes. */
2247 #define REGISTER_TARGET_PRAGMAS() do { \
2248 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2249 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2250 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2251 arm_lang_object_attributes_init(); \
2254 /* Condition code information. */
2255 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2256 return the mode to be used for the comparison. */
2258 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2260 #define REVERSIBLE_CC_MODE(MODE) 1
2262 #define REVERSE_CONDITION(CODE,MODE) \
2263 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2264 ? reverse_condition_maybe_unordered (code) \
2265 : reverse_condition (code))
2267 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2268 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2270 /* The arm5 clz instruction returns 32. */
2271 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2272 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2274 #define CC_STATUS_INIT \
2275 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2278 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2279 TARGET_THUMB2 ? "\t.thumb\n" : "")
2281 /* Output a push or a pop instruction (only used when profiling).
2282 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2283 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2284 that r7 isn't used by the function profiler, so we can use it as a
2285 scratch reg. WARNING: This isn't safe in the general case! It may be
2286 sensitive to future changes in final.c:profile_function. */
2287 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2291 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2292 STACK_POINTER_REGNUM, REGNO); \
2293 else if (TARGET_THUMB1 \
2294 && (REGNO) == STATIC_CHAIN_REGNUM) \
2296 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2297 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2298 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2301 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2305 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2306 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2310 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2311 STACK_POINTER_REGNUM, REGNO); \
2312 else if (TARGET_THUMB1 \
2313 && (REGNO) == STATIC_CHAIN_REGNUM) \
2315 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2316 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2317 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2320 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2323 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2324 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2326 /* This is how to output a label which precedes a jumptable. Since
2327 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2328 #undef ASM_OUTPUT_CASE_LABEL
2329 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2332 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2333 ASM_OUTPUT_ALIGN (FILE, 2); \
2334 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2338 /* Make sure subsequent insns are aligned after a TBB. */
2339 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2342 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2343 ASM_OUTPUT_ALIGN (FILE, 1); \
2347 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2352 if (is_called_in_ARM_mode (DECL) \
2353 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2354 && cfun->is_thunk)) \
2355 fprintf (STREAM, "\t.code 32\n") ; \
2356 else if (TARGET_THUMB1) \
2357 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2359 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2361 if (TARGET_POKE_FUNCTION_NAME) \
2362 arm_poke_function_name (STREAM, (const char *) NAME); \
2366 /* For aliases of functions we use .thumb_set instead. */
2367 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2370 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2371 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2373 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2375 fprintf (FILE, "\t.thumb_set "); \
2376 assemble_name (FILE, LABEL1); \
2377 fprintf (FILE, ","); \
2378 assemble_name (FILE, LABEL2); \
2379 fprintf (FILE, "\n"); \
2382 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2386 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2387 /* To support -falign-* switches we need to use .p2align so
2388 that alignment directives in code sections will be padded
2389 with no-op instructions, rather than zeroes. */
2390 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2393 if ((MAX_SKIP) == 0) \
2394 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2396 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2397 (int) (LOG), (int) (MAX_SKIP)); \
2401 /* Add two bytes to the length of conditionally executed Thumb-2
2402 instructions for the IT instruction. */
2403 #define ADJUST_INSN_LENGTH(insn, length) \
2404 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2407 /* Only perform branch elimination (by making instructions conditional) if
2408 we're optimizing. For Thumb-2 check if any IT instructions need
2410 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2411 if (TARGET_ARM && optimize) \
2412 arm_final_prescan_insn (INSN); \
2413 else if (TARGET_THUMB2) \
2414 thumb2_final_prescan_insn (INSN); \
2415 else if (TARGET_THUMB1) \
2416 thumb1_final_prescan_insn (INSN)
2418 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2419 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2420 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2421 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2422 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2423 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2426 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2427 if (arm_output_addr_const_extra (file, x) == FALSE) \
2430 /* A C expression whose value is RTL representing the value of the return
2431 address for the frame COUNT steps up from the current frame. */
2433 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2434 arm_return_addr (COUNT, FRAME)
2436 /* Mask of the bits in the PC that contain the real return address
2437 when running in 26-bit mode. */
2438 #define RETURN_ADDR_MASK26 (0x03fffffc)
2440 /* Pick up the return address upon entry to a procedure. Used for
2441 dwarf2 unwind information. This also enables the table driven
2443 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2444 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2446 /* Used to mask out junk bits from the return address, such as
2447 processor state, interrupt status, condition codes and the like. */
2448 #define MASK_RETURN_ADDR \
2449 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2450 in 26 bit mode, the condition codes must be masked out of the \
2451 return address. This does not apply to ARM6 and later processors \
2452 when running in 32 bit mode. */ \
2453 ((arm_arch4 || TARGET_THUMB) \
2454 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2455 : arm_gen_return_addr_mask ())
2458 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2459 symbolic names defined here (which would require too much duplication).
2468 ARM_BUILTIN_WAVG2BR,
2469 ARM_BUILTIN_WAVG2HR,
2496 ARM_BUILTIN_TMOVMSKB,
2497 ARM_BUILTIN_TMOVMSKH,
2498 ARM_BUILTIN_TMOVMSKW,
2507 ARM_BUILTIN_WPACKHSS,
2508 ARM_BUILTIN_WPACKWSS,
2509 ARM_BUILTIN_WPACKDSS,
2510 ARM_BUILTIN_WPACKHUS,
2511 ARM_BUILTIN_WPACKWUS,
2512 ARM_BUILTIN_WPACKDUS,
2517 ARM_BUILTIN_WADDSSB,
2518 ARM_BUILTIN_WADDSSH,
2519 ARM_BUILTIN_WADDSSW,
2520 ARM_BUILTIN_WADDUSB,
2521 ARM_BUILTIN_WADDUSH,
2522 ARM_BUILTIN_WADDUSW,
2526 ARM_BUILTIN_WSUBSSB,
2527 ARM_BUILTIN_WSUBSSH,
2528 ARM_BUILTIN_WSUBSSW,
2529 ARM_BUILTIN_WSUBUSB,
2530 ARM_BUILTIN_WSUBUSH,
2531 ARM_BUILTIN_WSUBUSW,
2538 ARM_BUILTIN_WCMPEQB,
2539 ARM_BUILTIN_WCMPEQH,
2540 ARM_BUILTIN_WCMPEQW,
2541 ARM_BUILTIN_WCMPGTUB,
2542 ARM_BUILTIN_WCMPGTUH,
2543 ARM_BUILTIN_WCMPGTUW,
2544 ARM_BUILTIN_WCMPGTSB,
2545 ARM_BUILTIN_WCMPGTSH,
2546 ARM_BUILTIN_WCMPGTSW,
2548 ARM_BUILTIN_TEXTRMSB,
2549 ARM_BUILTIN_TEXTRMSH,
2550 ARM_BUILTIN_TEXTRMSW,
2551 ARM_BUILTIN_TEXTRMUB,
2552 ARM_BUILTIN_TEXTRMUH,
2553 ARM_BUILTIN_TEXTRMUW,
2603 ARM_BUILTIN_WUNPCKIHB,
2604 ARM_BUILTIN_WUNPCKIHH,
2605 ARM_BUILTIN_WUNPCKIHW,
2606 ARM_BUILTIN_WUNPCKILB,
2607 ARM_BUILTIN_WUNPCKILH,
2608 ARM_BUILTIN_WUNPCKILW,
2610 ARM_BUILTIN_WUNPCKEHSB,
2611 ARM_BUILTIN_WUNPCKEHSH,
2612 ARM_BUILTIN_WUNPCKEHSW,
2613 ARM_BUILTIN_WUNPCKEHUB,
2614 ARM_BUILTIN_WUNPCKEHUH,
2615 ARM_BUILTIN_WUNPCKEHUW,
2616 ARM_BUILTIN_WUNPCKELSB,
2617 ARM_BUILTIN_WUNPCKELSH,
2618 ARM_BUILTIN_WUNPCKELSW,
2619 ARM_BUILTIN_WUNPCKELUB,
2620 ARM_BUILTIN_WUNPCKELUH,
2621 ARM_BUILTIN_WUNPCKELUW,
2623 ARM_BUILTIN_THREAD_POINTER,
2625 ARM_BUILTIN_NEON_BASE,
2627 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2630 /* Do not emit .note.GNU-stack by default. */
2631 #ifndef NEED_INDICATE_EXEC_STACK
2632 #define NEED_INDICATE_EXEC_STACK 0
2635 /* The maximum number of parallel loads or stores we support in an ldm/stm
2637 #define MAX_LDM_STM_OPS 4
2639 #endif /* ! GCC_ARM_H */
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