1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* The archetecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
41 builtin_define ("__thumb__"); \
45 builtin_define ("__ARMEB__"); \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
53 builtin_define ("__ARMEL__"); \
55 builtin_define ("__THUMBEL__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
62 builtin_define ("__VFP_FP__"); \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
83 /* The various ARM cores. */
86 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
88 #include "arm-cores.def"
90 /* Used to indicate that no processor has been specified. */
96 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
98 #include "arm-cores.def"
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
106 typedef enum arm_cond_code
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
113 extern arm_cc arm_current_cc;
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* Which ABI to use. */
129 extern const char *target_abi_name;
130 /* Define the information needed to generate branch insns. This is
131 stored from the compare operation. */
132 extern GTY(()) rtx arm_compare_op0;
133 extern GTY(()) rtx arm_compare_op1;
134 /* The label of the current constant pool. */
135 extern rtx pool_vector_label;
136 /* Set to 1 when a return insn is output, this means that the epilogue
138 extern int return_used_this_function;
139 /* Used to produce AOF syntax assembler. */
140 extern GTY(()) rtx aof_pic_label;
142 /* Just in case configure has failed to define anything. */
143 #ifndef TARGET_CPU_DEFAULT
144 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
149 #define CPP_SPEC "%(subtarget_cpp_spec) \
150 %{msoft-float:%{mhard-float: \
151 %e-msoft-float and -mhard_float may not be used together}} \
152 %{mbig-endian:%{mlittle-endian: \
153 %e-mbig-endian and -mlittle-endian may not be used together}}"
159 /* This macro defines names of additional specifications to put in the specs
160 that can be used in various specifications like CC1_SPEC. Its definition
161 is an initializer with a subgrouping for each command option.
163 Each subgrouping contains a string constant, that defines the
164 specification name, and a string constant that used by the GCC driver
167 Do not define this macro if it does not need to do anything. */
168 #define EXTRA_SPECS \
169 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
170 SUBTARGET_EXTRA_SPECS
172 #ifndef SUBTARGET_EXTRA_SPECS
173 #define SUBTARGET_EXTRA_SPECS
176 #ifndef SUBTARGET_CPP_SPEC
177 #define SUBTARGET_CPP_SPEC ""
180 /* Run-time Target Specification. */
181 #ifndef TARGET_VERSION
182 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
185 /* Nonzero if the function prologue (and epilogue) should obey
186 the ARM Procedure Call Standard. */
187 #define ARM_FLAG_APCS_FRAME (1 << 0)
189 /* Nonzero if the function prologue should output the function name to enable
190 the post mortem debugger to print a backtrace (very useful on RISCOS,
191 unused on RISCiX). Specifying this flag also enables
192 -fno-omit-frame-pointer.
193 XXX Must still be implemented in the prologue. */
194 #define ARM_FLAG_POKE (1 << 1)
196 /* Nonzero if floating point instructions are emulated by the FPE, in which
197 case instruction scheduling becomes very uninteresting. */
198 #define ARM_FLAG_FPE (1 << 2)
200 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
202 /* Nonzero if stack checking should be performed on entry to each function
203 which allocates temporary variables on the stack. */
204 #define ARM_FLAG_APCS_STACK (1 << 4)
206 /* Nonzero if floating point parameters should be passed to functions in
207 floating point registers. */
208 #define ARM_FLAG_APCS_FLOAT (1 << 5)
210 /* Nonzero if re-entrant, position independent code should be generated.
211 This is equivalent to -fpic. */
212 #define ARM_FLAG_APCS_REENT (1 << 6)
214 /* FLAG 0x0080 now spare (used to be alignment traps). */
215 /* Nonzero if all floating point instructions are missing (and there is no
216 emulator either). Generate function calls for all ops in this case. */
217 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
272 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
273 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
274 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
275 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
276 #define TARGET_IWMMXT (arm_arch_iwmmxt)
277 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
278 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
279 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
280 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
281 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
282 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
283 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
284 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
285 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
286 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
287 #define TARGET_ARM (! TARGET_THUMB)
288 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
289 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
290 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
291 #define TARGET_BACKTRACE (leaf_function_p () \
292 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
293 : (target_flags & THUMB_FLAG_BACKTRACE))
294 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
295 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
296 #define TARGET_AAPCS_BASED \
297 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
299 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
300 #ifndef SUBTARGET_SWITCHES
301 #define SUBTARGET_SWITCHES
304 #define TARGET_SWITCHES \
306 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
307 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
308 N_("Generate APCS conformant stack frames") }, \
309 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
310 {"poke-function-name", ARM_FLAG_POKE, \
311 N_("Store function names in object code") }, \
312 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
313 {"fpe", ARM_FLAG_FPE, "" }, \
314 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
315 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
316 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
317 N_("Pass FP arguments in FP registers") }, \
318 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
319 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
320 N_("Generate re-entrant, PIC code") }, \
321 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
322 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
323 N_("Use library calls to perform FP operations") }, \
324 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
325 N_("Use hardware floating point instructions") }, \
326 {"big-endian", ARM_FLAG_BIG_END, \
327 N_("Assume target CPU is configured as big endian") }, \
328 {"little-endian", -ARM_FLAG_BIG_END, \
329 N_("Assume target CPU is configured as little endian") }, \
330 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
331 N_("Assume big endian bytes, little endian words") }, \
332 {"thumb-interwork", ARM_FLAG_INTERWORK, \
333 N_("Support calls between Thumb and ARM instruction sets") }, \
334 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
335 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
336 N_("Generate a call to abort if a noreturn function returns")}, \
337 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
338 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
339 N_("Do not move instructions into a function's prologue") }, \
340 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
341 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
342 N_("Do not load the PIC register in function prologues") }, \
343 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
344 {"long-calls", ARM_FLAG_LONG_CALLS, \
345 N_("Generate call insns as indirect calls, if necessary") }, \
346 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
347 {"thumb", ARM_FLAG_THUMB, \
348 N_("Compile for the Thumb not the ARM") }, \
349 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
350 {"arm", -ARM_FLAG_THUMB, "" }, \
351 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
352 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
353 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
354 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
355 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
356 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
357 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
358 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
359 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
361 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
362 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
363 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
365 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
366 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
367 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
368 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
370 {"", TARGET_DEFAULT, "" } \
373 #define TARGET_OPTIONS \
375 {"cpu=", & arm_select[0].string, \
376 N_("Specify the name of the target CPU"), 0}, \
377 {"arch=", & arm_select[1].string, \
378 N_("Specify the name of the target architecture"), 0}, \
379 {"tune=", & arm_select[2].string, "", 0}, \
380 {"fpe=", & target_fpe_name, "", 0}, \
381 {"fp=", & target_fpe_name, "", 0}, \
382 {"fpu=", & target_fpu_name, \
383 N_("Specify the name of the target floating point hardware/format"), 0}, \
384 {"float-abi=", & target_float_abi_name, \
385 N_("Specify if floating point hardware should be used"), 0}, \
386 {"structure-size-boundary=", & structure_size_string, \
387 N_("Specify the minimum bit alignment of structures"), 0}, \
388 {"pic-register=", & arm_pic_register_string, \
389 N_("Specify the register to be used for PIC addressing"), 0}, \
390 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
393 /* Support for a compile-time default CPU, et cetera. The rules are:
394 --with-arch is ignored if -march or -mcpu are specified.
395 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
397 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
399 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
401 --with-fpu is ignored if -mfpu is specified.
402 --with-abi is ignored is -mabi is specified. */
403 #define OPTION_DEFAULT_SPECS \
404 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
405 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
406 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
408 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
409 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
410 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
412 struct arm_cpu_select
416 const struct processors * processors;
419 /* This is a magic array. If the user specifies a command line switch
420 which matches one of the entries in TARGET_OPTIONS then the corresponding
421 string pointer will be set to the value specified by the user. */
422 extern struct arm_cpu_select arm_select[];
424 /* Which floating point model to use. */
427 ARM_FP_MODEL_UNKNOWN,
428 /* FPA model (Hardware or software). */
430 /* Cirrus Maverick floating point model. */
431 ARM_FP_MODEL_MAVERICK,
432 /* VFP floating point model. */
436 extern enum arm_fp_model arm_fp_model;
438 /* Which floating point hardware is available. Also update
439 fp_model_for_fpu in arm.c when adding entries to this list. */
442 /* No FP hardware. */
444 /* Full FPA support. */
446 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
448 /* Emulated FPA hardware, Issue 3 emulator. */
450 /* Cirrus Maverick floating point co-processor. */
456 /* Recast the floating point class to be the floating point attribute. */
457 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
459 /* What type of floating point to tune for */
460 extern enum fputype arm_fpu_tune;
462 /* What type of floating point instructions are available */
463 extern enum fputype arm_fpu_arch;
468 ARM_FLOAT_ABI_SOFTFP,
472 extern enum float_abi_type arm_float_abi;
474 /* Which ABI to use. */
483 extern enum arm_abi_type arm_abi;
485 #ifndef ARM_DEFAULT_ABI
486 #define ARM_DEFAULT_ABI ARM_ABI_APCS
489 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
490 extern int arm_arch3m;
492 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
493 extern int arm_arch4;
495 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
496 extern int arm_arch4t;
498 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
499 extern int arm_arch5;
501 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
502 extern int arm_arch5e;
504 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
505 extern int arm_arch6;
507 /* Nonzero if this chip can benefit from load scheduling. */
508 extern int arm_ld_sched;
510 /* Nonzero if generating thumb code. */
511 extern int thumb_code;
513 /* Nonzero if this chip is a StrongARM. */
514 extern int arm_is_strong;
516 /* Nonzero if this chip is a Cirrus variant. */
517 extern int arm_arch_cirrus;
519 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
520 extern int arm_arch_iwmmxt;
522 /* Nonzero if this chip is an XScale. */
523 extern int arm_arch_xscale;
525 /* Nonzero if tuning for XScale */
526 extern int arm_tune_xscale;
528 /* Nonzero if this chip is an ARM6 or an ARM7. */
529 extern int arm_is_6_or_7;
531 /* Nonzero if we should define __THUMB_INTERWORK__ in the
533 XXX This is a bit of a hack, it's intended to help work around
534 problems in GLD which doesn't understand that armv5t code is
535 interworking clean. */
536 extern int arm_cpp_interwork;
538 #ifndef TARGET_DEFAULT
539 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
542 /* The frame pointer register used in gcc has nothing to do with debugging;
543 that is controlled by the APCS-FRAME option. */
544 #define CAN_DEBUG_WITHOUT_FP
546 #define OVERRIDE_OPTIONS arm_override_options ()
548 /* Nonzero if PIC code requires explicit qualifiers to generate
549 PLT and GOT relocs rather than the assembler doing so implicitly.
550 Subtargets can override these if required. */
551 #ifndef NEED_GOT_RELOC
552 #define NEED_GOT_RELOC 0
554 #ifndef NEED_PLT_RELOC
555 #define NEED_PLT_RELOC 0
558 /* Nonzero if we need to refer to the GOT with a PC-relative
559 offset. In other words, generate
561 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
565 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
567 The default is true, which matches NetBSD. Subtargets can
568 override this if required. */
573 /* Target machine storage Layout. */
576 /* Define this macro if it is advisable to hold scalars in registers
577 in a wider mode than that declared by the program. In such cases,
578 the value is constrained to be within the bounds of the declared
579 type, but kept valid in the wider mode. The signedness of the
580 extension may differ from that of the type. */
582 /* It is far faster to zero extend chars than to sign extend them */
584 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
585 if (GET_MODE_CLASS (MODE) == MODE_INT \
586 && GET_MODE_SIZE (MODE) < 4) \
588 if (MODE == QImode) \
590 else if (MODE == HImode) \
595 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
596 if (GET_MODE_CLASS (MODE) == MODE_INT \
597 && GET_MODE_SIZE (MODE) < 4) \
600 /* Define this if most significant bit is lowest numbered
601 in instructions that operate on numbered bit-fields. */
602 #define BITS_BIG_ENDIAN 0
604 /* Define this if most significant byte of a word is the lowest numbered.
605 Most ARM processors are run in little endian mode, so that is the default.
606 If you want to have it run-time selectable, change the definition in a
607 cover file to be TARGET_BIG_ENDIAN. */
608 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
610 /* Define this if most significant word of a multiword number is the lowest
612 This is always false, even when in big-endian mode. */
613 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
615 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
616 on processor pre-defineds when compiling libgcc2.c. */
617 #if defined(__ARMEB__) && !defined(__ARMWEL__)
618 #define LIBGCC2_WORDS_BIG_ENDIAN 1
620 #define LIBGCC2_WORDS_BIG_ENDIAN 0
623 /* Define this if most significant word of doubles is the lowest numbered.
624 The rules are different based on whether or not we use FPA-format,
625 VFP-format or some other floating point co-processor's format doubles. */
626 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
628 #define UNITS_PER_WORD 4
630 /* True if natural alignment is used for doubleword types. */
631 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
633 #define DOUBLEWORD_ALIGNMENT 64
635 #define PARM_BOUNDARY 32
637 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
639 #define PREFERRED_STACK_BOUNDARY \
640 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
642 #define FUNCTION_BOUNDARY 32
644 /* The lowest bit is used to indicate Thumb-mode functions, so the
645 vbit must go into the delta field of pointers to member
647 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
649 #define EMPTY_FIELD_BOUNDARY 32
651 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
653 /* XXX Blah -- this macro is used directly by libobjc. Since it
654 supports no vector modes, cut out the complexity and fall back
655 on BIGGEST_FIELD_ALIGNMENT. */
656 #ifdef IN_TARGET_LIBS
657 #define BIGGEST_FIELD_ALIGNMENT 64
660 /* Make strings word-aligned so strcpy from constants will be faster. */
661 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
663 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
664 ((TREE_CODE (EXP) == STRING_CST \
665 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
666 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
668 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
669 value set in previous versions of this toolchain was 8, which produces more
670 compact structures. The command line option -mstructure_size_boundary=<n>
671 can be used to change this value. For compatibility with the ARM SDK
672 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
673 0020D) page 2-20 says "Structures are aligned on word boundaries".
674 The AAPCS specifies a value of 8. */
675 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
676 extern int arm_structure_size_boundary;
678 /* This is the value used to initialize arm_structure_size_boundary. If a
679 particular arm target wants to change the default value it should change
680 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
681 for an example of this. */
682 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
683 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
686 /* Used when parsing command line option -mstructure_size_boundary. */
687 extern const char * structure_size_string;
689 /* Nonzero if move instructions will actually fail to work
690 when given unaligned data. */
691 #define STRICT_ALIGNMENT 1
693 /* wchar_t is unsigned under the AAPCS. */
695 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
697 #define WCHAR_TYPE_SIZE BITS_PER_WORD
701 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
704 /* AAPCS requires that structure alignment is affected by bitfields. */
705 #ifndef PCC_BITFIELD_TYPE_MATTERS
706 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
710 /* Standard register usage. */
712 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
713 (S - saved over call).
715 r0 * argument word/integer result
718 r4-r8 S register variable
719 r9 S (rfp) register variable (real frame pointer)
721 r10 F S (sl) stack limit (used by -mapcs-stack-check)
722 r11 F S (fp) argument pointer
723 r12 (ip) temp workspace
724 r13 F S (sp) lower end of current stack frame
725 r14 (lr) link address/workspace
726 r15 F (pc) program counter
728 f0 floating point result
729 f1-f3 floating point scratch
731 f4-f7 S floating point variable
733 cc This is NOT a real register, but is used internally
734 to represent things that use or set the condition
736 sfp This isn't either. It is used during rtl generation
737 since the offset between the frame pointer and the
738 auto's isn't known until after register allocation.
739 afp Nor this, we only need this because of non-local
740 goto. Without it fp appears to be used and the
741 elimination code won't get rid of sfp. It tracks
742 fp exactly at all times.
744 *: See CONDITIONAL_REGISTER_USAGE */
747 mvf0 Cirrus floating point result
748 mvf1-mvf3 Cirrus floating point scratch
749 mvf4-mvf15 S Cirrus floating point variable. */
751 /* s0-s15 VFP scratch (aka d0-d7).
752 s16-s31 S VFP variable (aka d8-d15).
753 vfpcc Not a real register. Represents the VFP condition
756 /* The stack backtrace structure is as follows:
757 fp points to here: | save code pointer | [fp]
758 | return link value | [fp, #-4]
759 | return sp value | [fp, #-8]
760 | return fp value | [fp, #-12]
761 [| saved r10 value |]
772 [| saved f7 value |] three words
773 [| saved f6 value |] three words
774 [| saved f5 value |] three words
775 [| saved f4 value |] three words
776 r0-r3 are not normally saved in a C function. */
778 /* 1 for registers that have pervasive standard uses
779 and are not available for the register allocator. */
780 #define FIXED_REGISTERS \
798 /* 1 for registers not available across function calls.
799 These must include the FIXED_REGISTERS and also any
800 registers that can be used without being saved.
801 The latter must include the registers where values are returned
802 and the register where structure-value addresses are passed.
803 Aside from that, you can include as many other registers as you like.
804 The CC is not preserved over function calls on the ARM 6, so it is
805 easier to assume this for all. SFP is preserved, since FP is. */
806 #define CALL_USED_REGISTERS \
824 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
825 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
828 #define CONDITIONAL_REGISTER_USAGE \
832 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
834 for (regno = FIRST_FPA_REGNUM; \
835 regno <= LAST_FPA_REGNUM; ++regno) \
836 fixed_regs[regno] = call_used_regs[regno] = 1; \
839 if (TARGET_THUMB && optimize_size) \
841 /* When optimizing for size, it's better not to use \
842 the HI regs, because of the overhead of stacking \
844 for (regno = FIRST_HI_REGNUM; \
845 regno <= LAST_HI_REGNUM; ++regno) \
846 fixed_regs[regno] = call_used_regs[regno] = 1; \
849 /* The link register can be clobbered by any branch insn, \
850 but we have no way to track that at present, so mark \
851 it as unavailable. */ \
853 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
855 if (TARGET_ARM && TARGET_HARD_FLOAT) \
857 if (TARGET_MAVERICK) \
859 for (regno = FIRST_FPA_REGNUM; \
860 regno <= LAST_FPA_REGNUM; ++ regno) \
861 fixed_regs[regno] = call_used_regs[regno] = 1; \
862 for (regno = FIRST_CIRRUS_FP_REGNUM; \
863 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
865 fixed_regs[regno] = 0; \
866 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
871 for (regno = FIRST_VFP_REGNUM; \
872 regno <= LAST_VFP_REGNUM; ++ regno) \
874 fixed_regs[regno] = 0; \
875 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
880 if (TARGET_REALLY_IWMMXT) \
882 regno = FIRST_IWMMXT_GR_REGNUM; \
883 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
884 and wCG1 as call-preserved registers. The 2002/11/21 \
885 revision changed this so that all wCG registers are \
886 scratch registers. */ \
887 for (regno = FIRST_IWMMXT_GR_REGNUM; \
888 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
889 fixed_regs[regno] = call_used_regs[regno] = 0; \
890 /* The XScale ABI has wR0 - wR9 as scratch registers, \
891 the rest as call-preserved registers. */ \
892 for (regno = FIRST_IWMMXT_REGNUM; \
893 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
895 fixed_regs[regno] = 0; \
896 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
900 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
902 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
903 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
905 else if (TARGET_APCS_STACK) \
907 fixed_regs[10] = 1; \
908 call_used_regs[10] = 1; \
910 if (TARGET_APCS_FRAME) \
912 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
913 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
915 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
918 /* These are a couple of extensions to the formats accepted
920 %@ prints out ASM_COMMENT_START
921 %r prints out REGISTER_PREFIX reg_names[arg] */
922 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
924 fputs (ASM_COMMENT_START, FILE); \
928 fputs (REGISTER_PREFIX, FILE); \
929 fputs (reg_names [va_arg (ARGS, int)], FILE); \
932 /* Round X up to the nearest word. */
933 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
935 /* Convert fron bytes to ints. */
936 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
938 /* The number of (integer) registers required to hold a quantity of type MODE.
939 Also used for VFP registers. */
940 #define ARM_NUM_REGS(MODE) \
941 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
943 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
944 #define ARM_NUM_REGS2(MODE, TYPE) \
945 ARM_NUM_INTS ((MODE) == BLKmode ? \
946 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
948 /* The number of (integer) argument register available. */
949 #define NUM_ARG_REGS 4
951 /* Return the register number of the N'th (integer) argument. */
952 #define ARG_REGISTER(N) (N - 1)
954 /* Specify the registers used for certain standard purposes.
955 The values of these macros are register numbers. */
957 /* The number of the last argument register. */
958 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
960 /* The numbers of the Thumb register ranges. */
961 #define FIRST_LO_REGNUM 0
962 #define LAST_LO_REGNUM 7
963 #define FIRST_HI_REGNUM 8
964 #define LAST_HI_REGNUM 11
966 /* The register that holds the return address in exception handlers. */
967 #define EXCEPTION_LR_REGNUM 2
969 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
970 as an invisible last argument (possible since varargs don't exist in
971 Pascal), so the following is not true. */
972 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
974 /* Define this to be where the real frame pointer is if it is not possible to
975 work out the offset between the frame pointer and the automatic variables
976 until after register allocation has taken place. FRAME_POINTER_REGNUM
977 should point to a special register that we will make sure is eliminated.
979 For the Thumb we have another problem. The TPCS defines the frame pointer
980 as r11, and GCC believes that it is always possible to use the frame pointer
981 as base register for addressing purposes. (See comments in
982 find_reloads_address()). But - the Thumb does not allow high registers,
983 including r11, to be used as base address registers. Hence our problem.
985 The solution used here, and in the old thumb port is to use r7 instead of
986 r11 as the hard frame pointer and to have special code to generate
987 backtrace structures on the stack (if required to do so via a command line
988 option) using r11. This is the only 'user visible' use of r11 as a frame
990 #define ARM_HARD_FRAME_POINTER_REGNUM 11
991 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
993 #define HARD_FRAME_POINTER_REGNUM \
995 ? ARM_HARD_FRAME_POINTER_REGNUM \
996 : THUMB_HARD_FRAME_POINTER_REGNUM)
998 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1000 /* Register to use for pushing function arguments. */
1001 #define STACK_POINTER_REGNUM SP_REGNUM
1003 /* ARM floating pointer registers. */
1004 #define FIRST_FPA_REGNUM 16
1005 #define LAST_FPA_REGNUM 23
1007 #define FIRST_IWMMXT_GR_REGNUM 43
1008 #define LAST_IWMMXT_GR_REGNUM 46
1009 #define FIRST_IWMMXT_REGNUM 47
1010 #define LAST_IWMMXT_REGNUM 62
1011 #define IS_IWMMXT_REGNUM(REGNUM) \
1012 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1013 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1014 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1016 /* Base register for access to local variables of the function. */
1017 #define FRAME_POINTER_REGNUM 25
1019 /* Base register for access to arguments of the function. */
1020 #define ARG_POINTER_REGNUM 26
1022 #define FIRST_CIRRUS_FP_REGNUM 27
1023 #define LAST_CIRRUS_FP_REGNUM 42
1024 #define IS_CIRRUS_REGNUM(REGNUM) \
1025 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1027 #define FIRST_VFP_REGNUM 63
1028 #define LAST_VFP_REGNUM 94
1029 #define IS_VFP_REGNUM(REGNUM) \
1030 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1032 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1033 /* + 16 Cirrus registers take us up to 43. */
1034 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1035 /* VFP adds 32 + 1 more. */
1036 #define FIRST_PSEUDO_REGISTER 96
1038 /* Value should be nonzero if functions must have frame pointers.
1039 Zero means the frame pointer need not be set up (and parms may be accessed
1040 via the stack pointer) in functions that seem suitable.
1041 If we have to have a frame pointer we might as well make use of it.
1042 APCS says that the frame pointer does not need to be pushed in leaf
1043 functions, or simple tail call functions. */
1044 #define FRAME_POINTER_REQUIRED \
1045 (current_function_has_nonlocal_label \
1046 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1048 /* Return number of consecutive hard regs needed starting at reg REGNO
1049 to hold something of mode MODE.
1050 This is ordinarily the length in words of a value of mode MODE
1051 but can be less for certain modes in special long registers.
1053 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1055 #define HARD_REGNO_NREGS(REGNO, MODE) \
1057 && REGNO >= FIRST_FPA_REGNUM \
1058 && REGNO != FRAME_POINTER_REGNUM \
1059 && REGNO != ARG_POINTER_REGNUM) \
1060 && !IS_VFP_REGNUM (REGNO) \
1061 ? 1 : ARM_NUM_REGS (MODE))
1063 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1064 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1065 arm_hard_regno_mode_ok ((REGNO), (MODE))
1067 /* Value is 1 if it is a good idea to tie two pseudo registers
1068 when one has mode MODE1 and one has mode MODE2.
1069 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1070 for any hard reg, then this must be 0 for correct output. */
1071 #define MODES_TIEABLE_P(MODE1, MODE2) \
1072 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1074 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1075 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1077 #define VALID_IWMMXT_REG_MODE(MODE) \
1078 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1080 /* The order in which register should be allocated. It is good to use ip
1081 since no saving is required (though calls clobber it) and it never contains
1082 function parameters. It is quite good to use lr since other calls may
1083 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1084 least likely to contain a function parameter; in addition results are
1087 #define REG_ALLOC_ORDER \
1089 3, 2, 1, 0, 12, 14, 4, 5, \
1090 6, 7, 8, 10, 9, 11, 13, 15, \
1091 16, 17, 18, 19, 20, 21, 22, 23, \
1092 27, 28, 29, 30, 31, 32, 33, 34, \
1093 35, 36, 37, 38, 39, 40, 41, 42, \
1094 43, 44, 45, 46, 47, 48, 49, 50, \
1095 51, 52, 53, 54, 55, 56, 57, 58, \
1098 78, 77, 76, 75, 74, 73, 72, 71, \
1099 70, 69, 68, 67, 66, 65, 64, 63, \
1100 79, 80, 81, 82, 83, 84, 85, 86, \
1101 87, 88, 89, 90, 91, 92, 93, 94, \
1105 /* Interrupt functions can only use registers that have already been
1106 saved by the prologue, even if they would normally be
1108 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1109 (! IS_INTERRUPT (cfun->machine->func_type) || \
1110 regs_ever_live[DST])
1112 /* Register and constant classes. */
1114 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1115 Now that the Thumb is involved it has become more complicated. */
1135 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1137 /* Give names of register classes as strings for dump file. */
1138 #define REG_CLASS_NAMES \
1156 /* Define which registers fit in which classes.
1157 This is an initializer for a vector of HARD_REG_SET
1158 of length N_REG_CLASSES. */
1159 #define REG_CLASS_CONTENTS \
1161 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1162 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1163 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1164 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1165 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1166 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1167 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1168 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1169 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1170 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1171 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1172 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1173 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1174 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1177 /* The same information, inverted:
1178 Return the class number of the smallest class containing
1179 reg number REGNO. This could be a conditional expression
1180 or could index an array. */
1181 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1183 /* FPA registers can't do subreg as all values are reformatted to internal
1184 precision. VFP registers may only be accessed in the mode they
1186 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1187 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1188 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1189 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1192 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1193 using r0-r4 for function arguments, r7 for the stack frame and don't
1194 have enough left over to do doubleword arithmetic. */
1195 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1196 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1197 || (CLASS) == CC_REG)
1199 /* The class value for index registers, and the one for base regs. */
1200 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1201 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1203 /* For the Thumb the high registers cannot be used as base registers
1204 when addressing quantities in QI or HI mode; if we don't know the
1205 mode, then we must be conservative. After reload we must also be
1206 conservative, since we can't support SP+reg addressing, and we
1207 can't fix up any bad substitutions. */
1208 #define MODE_BASE_REG_CLASS(MODE) \
1209 (TARGET_ARM ? GENERAL_REGS : \
1210 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1212 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1213 registers explicitly used in the rtl to be used as spill registers
1214 but prevents the compiler from extending the lifetime of these
1216 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1218 /* Get reg_class from a letter such as appears in the machine description.
1219 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1220 ARM, but several more letters for the Thumb. */
1221 #define REG_CLASS_FROM_LETTER(C) \
1222 ( (C) == 'f' ? FPA_REGS \
1223 : (C) == 'v' ? CIRRUS_REGS \
1224 : (C) == 'w' ? VFP_REGS \
1225 : (C) == 'y' ? IWMMXT_REGS \
1226 : (C) == 'z' ? IWMMXT_GR_REGS \
1227 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1228 : TARGET_ARM ? NO_REGS \
1229 : (C) == 'h' ? HI_REGS \
1230 : (C) == 'b' ? BASE_REGS \
1231 : (C) == 'k' ? STACK_REG \
1232 : (C) == 'c' ? CC_REG \
1235 /* The letters I, J, K, L and M in a register constraint string
1236 can be used to stand for particular ranges of immediate operands.
1237 This macro defines what the ranges are.
1238 C is the letter, and VALUE is a constant value.
1239 Return 1 if VALUE is in the range specified by C.
1240 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1241 J: valid indexing constants.
1242 K: ~value ok in rhs argument of data operand.
1243 L: -value ok in rhs argument of data operand.
1244 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1245 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1246 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1247 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1248 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1249 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1250 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1251 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1254 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1255 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1256 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1257 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1258 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1259 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1260 && ((VAL) & 3) == 0) : \
1261 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1262 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1265 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1267 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1269 /* Constant letter 'G' for the FP immediate constants.
1270 'H' means the same constant negated. */
1271 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1272 ((C) == 'G' ? arm_const_double_rtx (X) : \
1273 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1275 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1277 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1279 /* For the ARM, `Q' means that this is a memory operand that is just
1280 an offset from a register.
1281 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1282 address. This means that the symbol is in the text segment and can be
1283 accessed without using a load.
1284 'U' Prefixes an extended memory constraint where:
1285 'Uv' is an address valid for VFP load/store insns.
1286 'Uy' is an address valid for iwmmxt load/store insns.
1287 'Uq' is an address valid for ldrsb. */
1289 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1290 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1291 && GET_CODE (XEXP (OP, 0)) == REG) : \
1292 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1293 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1294 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1295 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1296 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1297 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1298 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1299 ((C) == 'U' && (STR)[1] == 'q') \
1300 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1303 #define CONSTRAINT_LEN(C,STR) \
1304 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1306 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1307 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1308 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1310 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1312 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1313 : EXTRA_CONSTRAINT_THUMB (X, C))
1315 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1317 /* Given an rtx X being reloaded into a reg required to be
1318 in class CLASS, return the class of reg to actually use.
1319 In general this is just CLASS, but for the Thumb we prefer
1320 a LO_REGS class or a subset. */
1321 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1322 (TARGET_ARM ? (CLASS) : \
1323 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1325 /* Must leave BASE_REGS reloads alone */
1326 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1327 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1328 ? ((true_regnum (X) == -1 ? LO_REGS \
1329 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1333 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1334 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1335 ? ((true_regnum (X) == -1 ? LO_REGS \
1336 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1340 /* Return the register class of a scratch register needed to copy IN into
1341 or out of a register in CLASS in MODE. If it can be done directly,
1342 NO_REGS is returned. */
1343 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1344 /* Restrict which direct reloads are allowed for VFP regs. */ \
1345 ((TARGET_VFP && TARGET_HARD_FLOAT \
1346 && (CLASS) == VFP_REGS) \
1347 ? vfp_secondary_reload_class (MODE, X) \
1349 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1350 ? GENERAL_REGS : NO_REGS) \
1351 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1353 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1354 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1355 /* Restrict which direct reloads are allowed for VFP regs. */ \
1356 ((TARGET_VFP && TARGET_HARD_FLOAT \
1357 && (CLASS) == VFP_REGS) \
1358 ? vfp_secondary_reload_class (MODE, X) : \
1359 /* Cannot load constants into Cirrus registers. */ \
1360 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1361 && (CLASS) == CIRRUS_REGS \
1362 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1365 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1366 && CONSTANT_P (X)) \
1368 (((MODE) == HImode && ! arm_arch4 \
1369 && (GET_CODE (X) == MEM \
1370 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1371 && true_regnum (X) == -1))) \
1372 ? GENERAL_REGS : NO_REGS) \
1373 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1375 /* Try a machine-dependent way of reloading an illegitimate address
1376 operand. If we find one, push the reload and jump to WIN. This
1377 macro is used in only one place: `find_reloads_address' in reload.c.
1379 For the ARM, we wish to handle large displacements off a base
1380 register by splitting the addend across a MOV and the mem insn.
1381 This can cut the number of reloads needed. */
1382 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1385 if (GET_CODE (X) == PLUS \
1386 && GET_CODE (XEXP (X, 0)) == REG \
1387 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1388 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1389 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1391 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1392 HOST_WIDE_INT low, high; \
1394 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1395 low = ((val & 0xf) ^ 0x8) - 0x8; \
1396 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1397 /* Need to be careful, -256 is not a valid offset. */ \
1398 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1399 else if (MODE == SImode \
1400 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1401 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1402 /* Need to be careful, -4096 is not a valid offset. */ \
1403 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1404 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1405 /* Need to be careful, -256 is not a valid offset. */ \
1406 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1407 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1408 && TARGET_HARD_FLOAT && TARGET_FPA) \
1409 /* Need to be careful, -1024 is not a valid offset. */ \
1410 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1414 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1415 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1416 - (unsigned HOST_WIDE_INT) 0x80000000); \
1417 /* Check for overflow or zero */ \
1418 if (low == 0 || high == 0 || (high + low != val)) \
1421 /* Reload the high part into a base reg; leave the low part \
1423 X = gen_rtx_PLUS (GET_MODE (X), \
1424 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1427 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1428 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1429 VOIDmode, 0, 0, OPNUM, TYPE); \
1435 /* XXX If an HImode FP+large_offset address is converted to an HImode
1436 SP+large_offset address, then reload won't know how to fix it. It sees
1437 only that SP isn't valid for HImode, and so reloads the SP into an index
1438 register, but the resulting address is still invalid because the offset
1439 is too big. We fix it here instead by reloading the entire address. */
1440 /* We could probably achieve better results by defining PROMOTE_MODE to help
1441 cope with the variances between the Thumb's signed and unsigned byte and
1442 halfword load instructions. */
1443 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1445 if (GET_CODE (X) == PLUS \
1446 && GET_MODE_SIZE (MODE) < 4 \
1447 && GET_CODE (XEXP (X, 0)) == REG \
1448 && XEXP (X, 0) == stack_pointer_rtx \
1449 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1450 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1454 push_reload (orig_X, NULL_RTX, &X, NULL, \
1455 MODE_BASE_REG_CLASS (MODE), \
1456 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1461 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1463 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1465 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1467 /* Return the maximum number of consecutive registers
1468 needed to represent mode MODE in a register of class CLASS.
1469 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1470 #define CLASS_MAX_NREGS(CLASS, MODE) \
1471 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1473 /* If defined, gives a class of registers that cannot be used as the
1474 operand of a SUBREG that changes the mode of the object illegally. */
1476 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1477 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1479 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1480 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1481 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1482 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1483 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1484 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1485 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1486 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1487 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1490 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1492 /* Stack layout; function entry, exit and calling. */
1494 /* Define this if pushing a word on the stack
1495 makes the stack pointer a smaller address. */
1496 #define STACK_GROWS_DOWNWARD 1
1498 /* Define this if the nominal address of the stack frame
1499 is at the high-address end of the local variables;
1500 that is, each additional local variable allocated
1501 goes at a more negative offset in the frame. */
1502 #define FRAME_GROWS_DOWNWARD 1
1504 /* Offset within stack frame to start allocating local variables at.
1505 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1506 first local allocated. Otherwise, it is the offset to the BEGINNING
1507 of the first local allocated. */
1508 #define STARTING_FRAME_OFFSET 0
1510 /* If we generate an insn to push BYTES bytes,
1511 this says how many the stack pointer really advances by. */
1512 /* The push insns do not do this rounding implicitly.
1513 So don't define this. */
1514 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1516 /* Define this if the maximum size of all the outgoing args is to be
1517 accumulated and pushed during the prologue. The amount can be
1518 found in the variable current_function_outgoing_args_size. */
1519 #define ACCUMULATE_OUTGOING_ARGS 1
1521 /* Offset of first parameter from the argument pointer register value. */
1522 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1524 /* Value is the number of byte of arguments automatically
1525 popped when returning from a subroutine call.
1526 FUNDECL is the declaration node of the function (as a tree),
1527 FUNTYPE is the data type of the function (as a tree),
1528 or for a library call it is an identifier node for the subroutine name.
1529 SIZE is the number of bytes of arguments passed on the stack.
1531 On the ARM, the caller does not pop any of its arguments that were passed
1533 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1535 /* Define how to find the value returned by a library function
1536 assuming the value has mode MODE. */
1537 #define LIBCALL_VALUE(MODE) \
1538 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1539 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1540 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1541 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1542 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1543 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1544 : TARGET_IWMMXT_ABI && VECTOR_MODE_SUPPORTED_P (MODE) \
1545 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1546 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1548 /* Define how to find the value returned by a function.
1549 VALTYPE is the data type of the value (as a tree).
1550 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1551 otherwise, FUNC is 0. */
1552 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1553 arm_function_value (VALTYPE, FUNC);
1555 /* 1 if N is a possible register number for a function value.
1556 On the ARM, only r0 and f0 can return results. */
1557 /* On a Cirrus chip, mvf0 can return results. */
1558 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1559 ((REGNO) == ARG_REGISTER (1) \
1560 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1561 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1562 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1563 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1564 && TARGET_HARD_FLOAT && TARGET_FPA))
1566 /* How large values are returned */
1567 /* A C expression which can inhibit the returning of certain function values
1568 in registers, based on the type of value. */
1569 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1571 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1572 values must be in memory. On the ARM, they need only do so if larger
1573 than a word, or if they contain elements offset from zero in the struct. */
1574 #define DEFAULT_PCC_STRUCT_RETURN 0
1576 /* Flags for the call/call_value rtl operations set up by function_arg. */
1577 #define CALL_NORMAL 0x00000000 /* No special processing. */
1578 #define CALL_LONG 0x00000001 /* Always call indirect. */
1579 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1581 /* These bits describe the different types of function supported
1582 by the ARM backend. They are exclusive. ie a function cannot be both a
1583 normal function and an interworked function, for example. Knowing the
1584 type of a function is important for determining its prologue and
1586 Note value 7 is currently unassigned. Also note that the interrupt
1587 function types all have bit 2 set, so that they can be tested for easily.
1588 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1589 machine_function structure is initialized (to zero) func_type will
1590 default to unknown. This will force the first use of arm_current_func_type
1591 to call arm_compute_func_type. */
1592 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1593 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1594 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1595 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1596 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1597 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1598 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1600 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1602 /* In addition functions can have several type modifiers,
1603 outlined by these bit masks: */
1604 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1605 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1606 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1607 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1609 /* Some macros to test these flags. */
1610 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1611 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1612 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1613 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1614 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1617 /* Structure used to hold the function stack frame layout. Offsets are
1618 relative to the stack pointer on function entry. Positive offsets are
1619 in the direction of stack growth.
1620 Only soft_frame is used in thumb mode. */
1622 typedef struct arm_stack_offsets GTY(())
1624 int saved_args; /* ARG_POINTER_REGNUM. */
1625 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1627 int soft_frame; /* FRAME_POINTER_REGNUM. */
1628 int outgoing_args; /* STACK_POINTER_REGNUM. */
1632 /* A C structure for machine-specific, per-function data.
1633 This is added to the cfun structure. */
1634 typedef struct machine_function GTY(())
1636 /* Additional stack adjustment in __builtin_eh_throw. */
1637 rtx eh_epilogue_sp_ofs;
1638 /* Records if LR has to be saved for far jumps. */
1640 /* Records if ARG_POINTER was ever live. */
1641 int arg_pointer_live;
1642 /* Records if the save of LR has been eliminated. */
1643 int lr_save_eliminated;
1644 /* The size of the stack frame. Only valid after reload. */
1645 arm_stack_offsets stack_offsets;
1646 /* Records the type of the current function. */
1647 unsigned long func_type;
1648 /* Record if the function has a variable argument list. */
1649 int uses_anonymous_args;
1650 /* Records if sibcalls are blocked because an argument
1651 register is needed to preserve stack alignment. */
1652 int sibcall_blocked;
1656 /* A C type for declaring a variable that is used as the first argument of
1657 `FUNCTION_ARG' and other related values. For some target machines, the
1658 type `int' suffices and can hold the number of bytes of argument so far. */
1661 /* This is the number of registers of arguments scanned so far. */
1663 /* This is the number of iWMMXt register arguments scanned so far. */
1667 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1672 /* Define where to put the arguments to a function.
1673 Value is zero to push the argument on the stack,
1674 or a hard register in which to store the argument.
1676 MODE is the argument's machine mode.
1677 TYPE is the data type of the argument (as a tree).
1678 This is null for libcalls where that information may
1680 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1681 the preceding args and about the function being called.
1682 NAMED is nonzero if this argument is a named parameter
1683 (otherwise it is an extra parameter matching an ellipsis).
1685 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1686 other arguments are passed on the stack. If (NAMED == 0) (which happens
1687 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1688 defined), say it is passed in the stack (function_prologue will
1689 indeed make it pass in the stack if necessary). */
1690 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1691 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1693 /* For an arg passed partly in registers and partly in memory,
1694 this is the number of registers used.
1695 For args passed entirely in registers or entirely in memory, zero. */
1696 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1697 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1698 NUM_ARG_REGS > (CUM).nregs \
1699 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1700 && (CUM).can_split) \
1701 ? NUM_ARG_REGS - (CUM).nregs : 0)
1703 /* A C expression that indicates when an argument must be passed by
1704 reference. If nonzero for an argument, a copy of that argument is
1705 made in memory and a pointer to the argument is passed instead of
1706 the argument itself. The pointer is passed in whatever way is
1707 appropriate for passing a pointer to that type. */
1708 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1709 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1711 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1712 for a call to a function whose data type is FNTYPE.
1713 For a library call, FNTYPE is 0.
1714 On the ARM, the offset starts at 0. */
1715 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1716 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1718 /* Update the data in CUM to advance over an argument
1719 of mode MODE and data type TYPE.
1720 (TYPE is null for libcalls where that information may not be available.) */
1721 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1723 if (VECTOR_MODE_SUPPORTED_P (MODE) \
1724 && (CUM).named_count > (CUM).nargs) \
1725 (CUM).iwmmxt_nregs += 1; \
1727 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1729 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1730 argument with the specified mode and type. If it is not defined,
1731 `PARM_BOUNDARY' is used for all arguments. */
1732 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1733 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1734 ? DOUBLEWORD_ALIGNMENT \
1737 /* 1 if N is a possible register number for function argument passing.
1738 On the ARM, r0-r3 are used to pass args. */
1739 #define FUNCTION_ARG_REGNO_P(REGNO) \
1740 (IN_RANGE ((REGNO), 0, 3) \
1741 || (TARGET_IWMMXT_ABI \
1742 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1744 /* Implement `va_arg'. */
1745 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1746 arm_va_arg (valist, type)
1749 /* If your target environment doesn't prefix user functions with an
1750 underscore, you may wish to re-define this to prevent any conflicts.
1751 e.g. AOF may prefix mcount with an underscore. */
1752 #ifndef ARM_MCOUNT_NAME
1753 #define ARM_MCOUNT_NAME "*mcount"
1756 /* Call the function profiler with a given profile label. The Acorn
1757 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1758 On the ARM the full profile code will look like:
1767 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1768 will output the .text section.
1770 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1771 ``prof'' doesn't seem to mind about this!
1773 Note - this version of the code is designed to work in both ARM and
1775 #ifndef ARM_FUNCTION_PROFILER
1776 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1781 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1782 IP_REGNUM, LR_REGNUM); \
1783 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1784 fputc ('\n', STREAM); \
1785 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1786 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1787 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1791 #ifdef THUMB_FUNCTION_PROFILER
1792 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1794 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1796 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1798 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1799 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1802 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1803 the stack pointer does not matter. The value is tested only in
1804 functions that have frame pointers.
1805 No definition is equivalent to always zero.
1807 On the ARM, the function epilogue recovers the stack pointer from the
1809 #define EXIT_IGNORE_STACK 1
1811 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1813 /* Determine if the epilogue should be output as RTL.
1814 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1815 #define USE_RETURN_INSN(ISCOND) \
1816 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1818 /* Definitions for register eliminations.
1820 This is an array of structures. Each structure initializes one pair
1821 of eliminable registers. The "from" register number is given first,
1822 followed by "to". Eliminations of the same "from" register are listed
1823 in order of preference.
1825 We have two registers that can be eliminated on the ARM. First, the
1826 arg pointer register can often be eliminated in favor of the stack
1827 pointer register. Secondly, the pseudo frame pointer register can always
1828 be eliminated; it is replaced with either the stack or the real frame
1829 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1830 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1832 #define ELIMINABLE_REGS \
1833 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1834 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1835 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1836 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1837 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1838 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1839 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1841 /* Given FROM and TO register numbers, say whether this elimination is
1842 allowed. Frame pointer elimination is automatically handled.
1844 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1845 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1846 pointer, we must eliminate FRAME_POINTER_REGNUM into
1847 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1848 ARG_POINTER_REGNUM. */
1849 #define CAN_ELIMINATE(FROM, TO) \
1850 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1851 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1852 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1853 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1856 #define THUMB_REG_PUSHED_P(reg) \
1857 (regs_ever_live [reg] \
1858 && (! call_used_regs [reg] \
1859 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1860 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1862 /* Define the offset between two registers, one to be eliminated, and the
1863 other its replacement, at the start of a routine. */
1864 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1866 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1868 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1870 /* Special case handling of the location of arguments passed on the stack. */
1871 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1873 /* Initialize data used by insn expanders. This is called from insn_emit,
1874 once for every function before code is generated. */
1875 #define INIT_EXPANDERS arm_init_expanders ()
1877 /* Output assembler code for a block containing the constant parts
1878 of a trampoline, leaving space for the variable parts.
1880 On the ARM, (if r8 is the static chain regnum, and remembering that
1881 referencing pc adds an offset of 8) the trampoline looks like:
1884 .word static chain value
1885 .word function's address
1886 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1887 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1889 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1890 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1891 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1892 PC_REGNUM, PC_REGNUM); \
1893 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1894 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1897 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1898 Why - because it is easier. This code will always be branched to via
1899 a BX instruction and since the compiler magically generates the address
1900 of the function the linker has no opportunity to ensure that the
1901 bottom bit is set. Thus the processor will be in ARM mode when it
1902 reaches this code. So we duplicate the ARM trampoline code and add
1903 a switch into Thumb mode as well. */
1904 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1906 fprintf (FILE, "\t.code 32\n"); \
1907 fprintf (FILE, ".Ltrampoline_start:\n"); \
1908 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1909 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1910 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1911 IP_REGNUM, PC_REGNUM); \
1912 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1913 IP_REGNUM, IP_REGNUM); \
1914 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1915 fprintf (FILE, "\t.word\t0\n"); \
1916 fprintf (FILE, "\t.word\t0\n"); \
1917 fprintf (FILE, "\t.code 16\n"); \
1920 #define TRAMPOLINE_TEMPLATE(FILE) \
1922 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1924 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1926 /* Length in units of the trampoline for entering a nested function. */
1927 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1929 /* Alignment required for a trampoline in bits. */
1930 #define TRAMPOLINE_ALIGNMENT 32
1932 /* Emit RTL insns to initialize the variable parts of a trampoline.
1933 FNADDR is an RTX for the address of the function's pure code.
1934 CXT is an RTX for the static chain value for the function. */
1935 #ifndef INITIALIZE_TRAMPOLINE
1936 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1938 emit_move_insn (gen_rtx_MEM (SImode, \
1939 plus_constant (TRAMP, \
1940 TARGET_ARM ? 8 : 16)), \
1942 emit_move_insn (gen_rtx_MEM (SImode, \
1943 plus_constant (TRAMP, \
1944 TARGET_ARM ? 12 : 20)), \
1950 /* Addressing modes, and classification of registers for them. */
1951 #define HAVE_POST_INCREMENT 1
1952 #define HAVE_PRE_INCREMENT TARGET_ARM
1953 #define HAVE_POST_DECREMENT TARGET_ARM
1954 #define HAVE_PRE_DECREMENT TARGET_ARM
1955 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1956 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1957 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1958 #define HAVE_POST_MODIFY_REG TARGET_ARM
1960 /* Macros to check register numbers against specific register classes. */
1962 /* These assume that REGNO is a hard or pseudo reg number.
1963 They give nonzero only if REGNO is a hard reg of the suitable class
1964 or a pseudo reg currently allocated to a suitable hard reg.
1965 Since they use reg_renumber, they are safe only once reg_renumber
1966 has been allocated, which happens in local-alloc.c. */
1967 #define TEST_REGNO(R, TEST, VALUE) \
1968 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1970 /* On the ARM, don't allow the pc to be used. */
1971 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1972 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1973 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1974 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1976 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1977 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1978 || (GET_MODE_SIZE (MODE) >= 4 \
1979 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1981 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1983 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1984 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1986 /* For ARM code, we don't care about the mode, but for Thumb, the index
1987 must be suitable for use in a QImode load. */
1988 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1989 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1991 /* Maximum number of registers that can appear in a valid memory address.
1992 Shifts in addresses can't be by a register. */
1993 #define MAX_REGS_PER_ADDRESS 2
1995 /* Recognize any constant value that is a valid address. */
1996 /* XXX We can address any constant, eventually... */
1998 #ifdef AOF_ASSEMBLER
2000 #define CONSTANT_ADDRESS_P(X) \
2001 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2005 #define CONSTANT_ADDRESS_P(X) \
2006 (GET_CODE (X) == SYMBOL_REF \
2007 && (CONSTANT_POOL_ADDRESS_P (X) \
2008 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2010 #endif /* AOF_ASSEMBLER */
2012 /* Nonzero if the constant value X is a legitimate general operand.
2013 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2015 On the ARM, allow any integer (invalid ones are removed later by insn
2016 patterns), nice doubles and symbol_refs which refer to the function's
2019 When generating pic allow anything. */
2020 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2022 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2023 ( GET_CODE (X) == CONST_INT \
2024 || GET_CODE (X) == CONST_DOUBLE \
2025 || CONSTANT_ADDRESS_P (X) \
2028 #define LEGITIMATE_CONSTANT_P(X) \
2029 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2031 /* Special characters prefixed to function names
2032 in order to encode attribute like information.
2033 Note, '@' and '*' have already been taken. */
2034 #define SHORT_CALL_FLAG_CHAR '^'
2035 #define LONG_CALL_FLAG_CHAR '#'
2037 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2038 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2040 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2041 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2043 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2044 #define SUBTARGET_NAME_ENCODING_LENGTHS
2047 /* This is a C fragment for the inside of a switch statement.
2048 Each case label should return the number of characters to
2049 be stripped from the start of a function's name, if that
2050 name starts with the indicated character. */
2051 #define ARM_NAME_ENCODING_LENGTHS \
2052 case SHORT_CALL_FLAG_CHAR: return 1; \
2053 case LONG_CALL_FLAG_CHAR: return 1; \
2054 case '*': return 1; \
2055 SUBTARGET_NAME_ENCODING_LENGTHS
2057 /* This is how to output a reference to a user-level label named NAME.
2058 `assemble_name' uses this. */
2059 #undef ASM_OUTPUT_LABELREF
2060 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2061 arm_asm_output_labelref (FILE, NAME)
2063 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2064 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2066 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2067 and check its validity for a certain class.
2068 We have two alternate definitions for each of them.
2069 The usual definition accepts all pseudo regs; the other rejects
2070 them unless they have been allocated suitable hard regs.
2071 The symbol REG_OK_STRICT causes the latter definition to be used. */
2072 #ifndef REG_OK_STRICT
2074 #define ARM_REG_OK_FOR_BASE_P(X) \
2075 (REGNO (X) <= LAST_ARM_REGNUM \
2076 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2077 || REGNO (X) == FRAME_POINTER_REGNUM \
2078 || REGNO (X) == ARG_POINTER_REGNUM)
2080 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2081 (REGNO (X) <= LAST_LO_REGNUM \
2082 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2083 || (GET_MODE_SIZE (MODE) >= 4 \
2084 && (REGNO (X) == STACK_POINTER_REGNUM \
2085 || (X) == hard_frame_pointer_rtx \
2086 || (X) == arg_pointer_rtx)))
2088 #define REG_STRICT_P 0
2090 #else /* REG_OK_STRICT */
2092 #define ARM_REG_OK_FOR_BASE_P(X) \
2093 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2095 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2096 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2098 #define REG_STRICT_P 1
2100 #endif /* REG_OK_STRICT */
2102 /* Now define some helpers in terms of the above. */
2104 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2106 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2107 : ARM_REG_OK_FOR_BASE_P (X))
2109 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2111 /* For Thumb, a valid index register is anything that can be used in
2112 a byte load instruction. */
2113 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2115 /* Nonzero if X is a hard reg that can be used as an index
2116 or if it is a pseudo reg. On the Thumb, the stack pointer
2118 #define REG_OK_FOR_INDEX_P(X) \
2120 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2121 : ARM_REG_OK_FOR_INDEX_P (X))
2124 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2125 that is a valid memory address for an instruction.
2126 The MODE argument is the machine mode for the MEM expression
2127 that wants to use this address. */
2129 #define ARM_BASE_REGISTER_RTX_P(X) \
2130 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2132 #define ARM_INDEX_REGISTER_RTX_P(X) \
2133 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2135 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2137 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2141 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2143 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2147 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2149 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2150 else /* if (TARGET_THUMB) */ \
2151 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2154 /* Try machine-dependent ways of modifying an illegitimate address
2155 to be legitimate. If we find one, return the new, valid address. */
2156 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2158 X = arm_legitimize_address (X, OLDX, MODE); \
2161 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2163 X = thumb_legitimize_address (X, OLDX, MODE); \
2166 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2169 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2171 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2173 if (memory_address_p (MODE, X)) \
2177 /* Go to LABEL if ADDR (a legitimate address expression)
2178 has an effect that depends on the machine mode it is used for. */
2179 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2181 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2182 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2186 /* Nothing helpful to do for the Thumb */
2187 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2189 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2192 /* Specify the machine mode that this machine uses
2193 for the index in the tablejump instruction. */
2194 #define CASE_VECTOR_MODE Pmode
2196 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2197 unsigned is probably best, but may break some code. */
2198 #ifndef DEFAULT_SIGNED_CHAR
2199 #define DEFAULT_SIGNED_CHAR 0
2202 /* Max number of bytes we can move from memory to memory
2203 in one reasonably fast instruction. */
2207 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2209 /* Define if operations between registers always perform the operation
2210 on the full register even if a narrower mode is specified. */
2211 #define WORD_REGISTER_OPERATIONS
2213 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2214 will either zero-extend or sign-extend. The value of this macro should
2215 be the code that says which one of the two operations is implicitly
2216 done, NIL if none. */
2217 #define LOAD_EXTEND_OP(MODE) \
2218 (TARGET_THUMB ? ZERO_EXTEND : \
2219 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2220 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2222 /* Nonzero if access to memory by bytes is slow and undesirable. */
2223 #define SLOW_BYTE_ACCESS 0
2225 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2227 /* Immediate shift counts are truncated by the output routines (or was it
2228 the assembler?). Shift counts in a register are truncated by ARM. Note
2229 that the native compiler puts too large (> 32) immediate shift counts
2230 into a register and shifts by the register, letting the ARM decide what
2231 to do instead of doing that itself. */
2232 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2233 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2234 On the arm, Y in a register is used modulo 256 for the shift. Only for
2235 rotates is modulo 32 used. */
2236 /* #define SHIFT_COUNT_TRUNCATED 1 */
2238 /* All integers have the same format so truncation is easy. */
2239 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2241 /* Calling from registers is a massive pain. */
2242 #define NO_FUNCTION_CSE 1
2244 /* The machine modes of pointers and functions */
2245 #define Pmode SImode
2246 #define FUNCTION_MODE Pmode
2248 #define ARM_FRAME_RTX(X) \
2249 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2250 || (X) == arg_pointer_rtx)
2252 /* Moves to and from memory are quite expensive */
2253 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2254 (TARGET_ARM ? 10 : \
2255 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2256 * (CLASS == LO_REGS ? 1 : 2)))
2258 /* Try to generate sequences that don't involve branches, we can then use
2259 conditional instructions */
2260 #define BRANCH_COST \
2261 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2263 /* Position Independent Code. */
2264 /* We decide which register to use based on the compilation options and
2265 the assembler in use; this is more general than the APCS restriction of
2266 using sb (r9) all the time. */
2267 extern int arm_pic_register;
2269 /* Used when parsing command line option -mpic-register=. */
2270 extern const char * arm_pic_register_string;
2272 /* The register number of the register used to address a table of static
2273 data addresses in memory. */
2274 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2276 #define FINALIZE_PIC arm_finalize_pic (1)
2278 /* We can't directly access anything that contains a symbol,
2279 nor can we indirect via the constant pool. */
2280 #define LEGITIMATE_PIC_OPERAND_P(X) \
2281 (!(symbol_mentioned_p (X) \
2282 || label_mentioned_p (X) \
2283 || (GET_CODE (X) == SYMBOL_REF \
2284 && CONSTANT_POOL_ADDRESS_P (X) \
2285 && (symbol_mentioned_p (get_pool_constant (X)) \
2286 || label_mentioned_p (get_pool_constant (X))))))
2288 /* We need to know when we are making a constant pool; this determines
2289 whether data needs to be in the GOT or can be referenced via a GOT
2291 extern int making_const_table;
2293 /* Handle pragmas for compatibility with Intel's compilers. */
2294 #define REGISTER_TARGET_PRAGMAS() do { \
2295 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2296 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2297 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2300 /* Condition code information. */
2301 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2302 return the mode to be used for the comparison. */
2304 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2306 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2308 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2311 if (GET_CODE (OP1) == CONST_INT \
2312 && ! (const_ok_for_arm (INTVAL (OP1)) \
2313 || (const_ok_for_arm (- INTVAL (OP1))))) \
2315 rtx const_op = OP1; \
2316 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2322 /* The arm5 clz instruction returns 32. */
2323 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2326 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2328 /* Output a push or a pop instruction (only used when profiling). */
2329 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2333 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2334 STACK_POINTER_REGNUM, REGNO); \
2336 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2340 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2344 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2345 STACK_POINTER_REGNUM, REGNO); \
2347 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2350 /* This is how to output a label which precedes a jumptable. Since
2351 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2352 #undef ASM_OUTPUT_CASE_LABEL
2353 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2357 ASM_OUTPUT_ALIGN (FILE, 2); \
2358 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2362 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2367 if (is_called_in_ARM_mode (DECL) \
2368 || current_function_is_thunk) \
2369 fprintf (STREAM, "\t.code 32\n") ; \
2371 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2373 if (TARGET_POKE_FUNCTION_NAME) \
2374 arm_poke_function_name (STREAM, (char *) NAME); \
2378 /* For aliases of functions we use .thumb_set instead. */
2379 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2382 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2383 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2385 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2387 fprintf (FILE, "\t.thumb_set "); \
2388 assemble_name (FILE, LABEL1); \
2389 fprintf (FILE, ","); \
2390 assemble_name (FILE, LABEL2); \
2391 fprintf (FILE, "\n"); \
2394 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2398 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2399 /* To support -falign-* switches we need to use .p2align so
2400 that alignment directives in code sections will be padded
2401 with no-op instructions, rather than zeroes. */
2402 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2405 if ((MAX_SKIP) == 0) \
2406 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2408 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2409 (int) (LOG), (int) (MAX_SKIP)); \
2413 /* Only perform branch elimination (by making instructions conditional) if
2414 we're optimizing. Otherwise it's of no use anyway. */
2415 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2416 if (TARGET_ARM && optimize) \
2417 arm_final_prescan_insn (INSN); \
2418 else if (TARGET_THUMB) \
2419 thumb_final_prescan_insn (INSN)
2421 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2422 (CODE == '@' || CODE == '|' \
2423 || (TARGET_ARM && (CODE == '?')) \
2424 || (TARGET_THUMB && (CODE == '_')))
2426 /* Output an operand of an instruction. */
2427 #define PRINT_OPERAND(STREAM, X, CODE) \
2428 arm_print_operand (STREAM, X, CODE)
2430 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2431 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2432 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2433 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2434 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2435 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2438 /* Output the address of an operand. */
2439 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2441 int is_minus = GET_CODE (X) == MINUS; \
2443 if (GET_CODE (X) == REG) \
2444 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2445 else if (GET_CODE (X) == PLUS || is_minus) \
2447 rtx base = XEXP (X, 0); \
2448 rtx index = XEXP (X, 1); \
2449 HOST_WIDE_INT offset = 0; \
2450 if (GET_CODE (base) != REG) \
2452 /* Ensure that BASE is a register. */ \
2453 /* (one of them must be). */ \
2458 switch (GET_CODE (index)) \
2461 offset = INTVAL (index); \
2464 asm_fprintf (STREAM, "[%r, #%wd]", \
2465 REGNO (base), offset); \
2469 asm_fprintf (STREAM, "[%r, %s%r]", \
2470 REGNO (base), is_minus ? "-" : "", \
2480 asm_fprintf (STREAM, "[%r, %s%r", \
2481 REGNO (base), is_minus ? "-" : "", \
2482 REGNO (XEXP (index, 0))); \
2483 arm_print_operand (STREAM, index, 'S'); \
2484 fputs ("]", STREAM); \
2492 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2493 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2495 extern enum machine_mode output_memory_reference_mode; \
2497 if (GET_CODE (XEXP (X, 0)) != REG) \
2500 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2501 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2502 REGNO (XEXP (X, 0)), \
2503 GET_CODE (X) == PRE_DEC ? "-" : "", \
2504 GET_MODE_SIZE (output_memory_reference_mode)); \
2506 asm_fprintf (STREAM, "[%r], #%s%d", \
2507 REGNO (XEXP (X, 0)), \
2508 GET_CODE (X) == POST_DEC ? "-" : "", \
2509 GET_MODE_SIZE (output_memory_reference_mode)); \
2511 else if (GET_CODE (X) == PRE_MODIFY) \
2513 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2514 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2515 asm_fprintf (STREAM, "#%wd]!", \
2516 INTVAL (XEXP (XEXP (X, 1), 1))); \
2518 asm_fprintf (STREAM, "%r]!", \
2519 REGNO (XEXP (XEXP (X, 1), 1))); \
2521 else if (GET_CODE (X) == POST_MODIFY) \
2523 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2524 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2525 asm_fprintf (STREAM, "#%wd", \
2526 INTVAL (XEXP (XEXP (X, 1), 1))); \
2528 asm_fprintf (STREAM, "%r", \
2529 REGNO (XEXP (XEXP (X, 1), 1))); \
2531 else output_addr_const (STREAM, X); \
2534 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2536 if (GET_CODE (X) == REG) \
2537 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2538 else if (GET_CODE (X) == POST_INC) \
2539 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2540 else if (GET_CODE (X) == PLUS) \
2542 if (GET_CODE (XEXP (X, 0)) != REG) \
2544 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2545 asm_fprintf (STREAM, "[%r, #%wd]", \
2546 REGNO (XEXP (X, 0)), \
2547 INTVAL (XEXP (X, 1))); \
2549 asm_fprintf (STREAM, "[%r, %r]", \
2550 REGNO (XEXP (X, 0)), \
2551 REGNO (XEXP (X, 1))); \
2554 output_addr_const (STREAM, X); \
2557 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2559 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2561 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2563 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2564 if (GET_CODE (X) != CONST_VECTOR \
2565 || ! arm_emit_vector_const (FILE, X)) \
2568 /* A C expression whose value is RTL representing the value of the return
2569 address for the frame COUNT steps up from the current frame. */
2571 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2572 arm_return_addr (COUNT, FRAME)
2574 /* Mask of the bits in the PC that contain the real return address
2575 when running in 26-bit mode. */
2576 #define RETURN_ADDR_MASK26 (0x03fffffc)
2578 /* Pick up the return address upon entry to a procedure. Used for
2579 dwarf2 unwind information. This also enables the table driven
2581 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2582 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2584 /* Used to mask out junk bits from the return address, such as
2585 processor state, interrupt status, condition codes and the like. */
2586 #define MASK_RETURN_ADDR \
2587 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2588 in 26 bit mode, the condition codes must be masked out of the \
2589 return address. This does not apply to ARM6 and later processors \
2590 when running in 32 bit mode. */ \
2591 ((arm_arch4 || TARGET_THUMB) \
2592 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2593 : arm_gen_return_addr_mask ())
2596 /* Define the codes that are matched by predicates in arm.c */
2597 #define PREDICATE_CODES \
2598 {"s_register_operand", {SUBREG, REG}}, \
2599 {"arm_general_register_operand", {SUBREG, REG}}, \
2600 {"arm_hard_register_operand", {REG}}, \
2601 {"f_register_operand", {SUBREG, REG}}, \
2602 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2603 {"arm_addimm_operand", {CONST_INT}}, \
2604 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2605 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2606 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2607 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2608 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2609 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2610 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2611 {"thumb_cmpneg_operand", {CONST_INT}}, \
2612 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2613 {"offsettable_memory_operand", {MEM}}, \
2614 {"alignable_memory_operand", {MEM}}, \
2615 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2616 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2617 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2618 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2619 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2620 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2621 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2622 {"load_multiple_operation", {PARALLEL}}, \
2623 {"store_multiple_operation", {PARALLEL}}, \
2624 {"equality_operator", {EQ, NE}}, \
2625 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2626 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2628 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2629 {"const_shift_operand", {CONST_INT}}, \
2630 {"multi_register_push", {PARALLEL}}, \
2631 {"cc_register", {REG}}, \
2632 {"logical_binary_operator", {AND, IOR, XOR}}, \
2633 {"cirrus_register_operand", {REG}}, \
2634 {"cirrus_fp_register", {REG}}, \
2635 {"cirrus_shift_const", {CONST_INT}}, \
2636 {"dominant_cc_register", {REG}}, \
2637 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2638 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2640 /* Define this if you have special predicates that know special things
2641 about modes. Genrecog will warn about certain forms of
2642 match_operand without a mode; if the operand predicate is listed in
2643 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2644 #define SPECIAL_MODE_PREDICATES \
2645 "cc_register", "dominant_cc_register",
2654 ARM_BUILTIN_WAVG2BR,
2655 ARM_BUILTIN_WAVG2HR,
2682 ARM_BUILTIN_TMOVMSKB,
2683 ARM_BUILTIN_TMOVMSKH,
2684 ARM_BUILTIN_TMOVMSKW,
2693 ARM_BUILTIN_WPACKHSS,
2694 ARM_BUILTIN_WPACKWSS,
2695 ARM_BUILTIN_WPACKDSS,
2696 ARM_BUILTIN_WPACKHUS,
2697 ARM_BUILTIN_WPACKWUS,
2698 ARM_BUILTIN_WPACKDUS,
2703 ARM_BUILTIN_WADDSSB,
2704 ARM_BUILTIN_WADDSSH,
2705 ARM_BUILTIN_WADDSSW,
2706 ARM_BUILTIN_WADDUSB,
2707 ARM_BUILTIN_WADDUSH,
2708 ARM_BUILTIN_WADDUSW,
2712 ARM_BUILTIN_WSUBSSB,
2713 ARM_BUILTIN_WSUBSSH,
2714 ARM_BUILTIN_WSUBSSW,
2715 ARM_BUILTIN_WSUBUSB,
2716 ARM_BUILTIN_WSUBUSH,
2717 ARM_BUILTIN_WSUBUSW,
2724 ARM_BUILTIN_WCMPEQB,
2725 ARM_BUILTIN_WCMPEQH,
2726 ARM_BUILTIN_WCMPEQW,
2727 ARM_BUILTIN_WCMPGTUB,
2728 ARM_BUILTIN_WCMPGTUH,
2729 ARM_BUILTIN_WCMPGTUW,
2730 ARM_BUILTIN_WCMPGTSB,
2731 ARM_BUILTIN_WCMPGTSH,
2732 ARM_BUILTIN_WCMPGTSW,
2734 ARM_BUILTIN_TEXTRMSB,
2735 ARM_BUILTIN_TEXTRMSH,
2736 ARM_BUILTIN_TEXTRMSW,
2737 ARM_BUILTIN_TEXTRMUB,
2738 ARM_BUILTIN_TEXTRMUH,
2739 ARM_BUILTIN_TEXTRMUW,
2789 ARM_BUILTIN_WUNPCKIHB,
2790 ARM_BUILTIN_WUNPCKIHH,
2791 ARM_BUILTIN_WUNPCKIHW,
2792 ARM_BUILTIN_WUNPCKILB,
2793 ARM_BUILTIN_WUNPCKILH,
2794 ARM_BUILTIN_WUNPCKILW,
2796 ARM_BUILTIN_WUNPCKEHSB,
2797 ARM_BUILTIN_WUNPCKEHSH,
2798 ARM_BUILTIN_WUNPCKEHSW,
2799 ARM_BUILTIN_WUNPCKEHUB,
2800 ARM_BUILTIN_WUNPCKEHUH,
2801 ARM_BUILTIN_WUNPCKEHUW,
2802 ARM_BUILTIN_WUNPCKELSB,
2803 ARM_BUILTIN_WUNPCKELSH,
2804 ARM_BUILTIN_WUNPCKELSW,
2805 ARM_BUILTIN_WUNPCKELUB,
2806 ARM_BUILTIN_WUNPCKELUH,
2807 ARM_BUILTIN_WUNPCKELUW,
2811 #endif /* ! GCC_ARM_H */
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