1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
39 #include "config/vxworks-dummy.h"
41 /* The architecture define. */
42 extern char arm_arch_name[];
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
53 builtin_define ("__thumb__"); \
55 builtin_define ("__thumb2__"); \
59 builtin_define ("__ARMEB__"); \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
67 builtin_define ("__ARMEL__"); \
69 builtin_define ("__THUMBEL__"); \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
76 builtin_define ("__VFP_FP__"); \
79 builtin_define ("__ARM_NEON__"); \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
97 builtin_define ("__ARM_EABI__"); \
100 /* The various ARM cores. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
107 /* Used to indicate that no processor has been specified. */
113 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
115 #include "arm-cores.def"
120 /* The processor for which instructions should be scheduled. */
121 extern enum processor_type arm_tune;
123 typedef enum arm_cond_code
125 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
126 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
130 extern arm_cc arm_current_cc;
132 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
134 extern int arm_target_label;
135 extern int arm_ccfsm_state;
136 extern GTY(()) rtx arm_target_insn;
137 /* The label of the current constant pool. */
138 extern rtx pool_vector_label;
139 /* Set to 1 when a return insn is output, this means that the epilogue
141 extern int return_used_this_function;
142 /* Callback to output language specific object attributes. */
143 extern void (*arm_lang_output_object_attributes_hook)(void);
145 /* Just in case configure has failed to define anything. */
146 #ifndef TARGET_CPU_DEFAULT
147 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
152 #define CPP_SPEC "%(subtarget_cpp_spec) \
153 %{msoft-float:%{mhard-float: \
154 %e-msoft-float and -mhard_float may not be used together}} \
155 %{mbig-endian:%{mlittle-endian: \
156 %e-mbig-endian and -mlittle-endian may not be used together}}"
162 /* This macro defines names of additional specifications to put in the specs
163 that can be used in various specifications like CC1_SPEC. Its definition
164 is an initializer with a subgrouping for each command option.
166 Each subgrouping contains a string constant, that defines the
167 specification name, and a string constant that used by the GCC driver
170 Do not define this macro if it does not need to do anything. */
171 #define EXTRA_SPECS \
172 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
173 SUBTARGET_EXTRA_SPECS
175 #ifndef SUBTARGET_EXTRA_SPECS
176 #define SUBTARGET_EXTRA_SPECS
179 #ifndef SUBTARGET_CPP_SPEC
180 #define SUBTARGET_CPP_SPEC ""
183 /* Run-time Target Specification. */
184 #ifndef TARGET_VERSION
185 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
188 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
189 /* Use hardware floating point instructions. */
190 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
191 /* Use hardware floating point calling convention. */
192 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
193 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
194 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
195 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
196 #define TARGET_IWMMXT (arm_arch_iwmmxt)
197 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
198 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
199 #define TARGET_ARM (! TARGET_THUMB)
200 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
201 #define TARGET_BACKTRACE (leaf_function_p () \
202 ? TARGET_TPCS_LEAF_FRAME \
204 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
205 #define TARGET_AAPCS_BASED \
206 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
208 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
209 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
211 /* Only 16-bit thumb code. */
212 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
213 /* Arm or Thumb-2 32-bit code. */
214 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
215 /* 32-bit Thumb-2 code. */
216 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
218 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
219 /* FPA emulator without LFM. */
220 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
222 /* The following two macros concern the ability to execute coprocessor
223 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
224 only ever tested when we know we are generating for VFP hardware; we need
225 to be more careful with TARGET_NEON as noted below. */
227 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
228 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
230 /* FPU supports VFPv3 instructions. */
231 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
233 /* FPU supports NEON/VFP half-precision floating-point. */
234 #define TARGET_NEON_FP16 \
235 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
237 /* FPU supports Neon instructions. The setting of this macro gets
238 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
239 and TARGET_HARD_FLOAT to ensure that NEON instructions are
241 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
242 && TARGET_VFP && arm_fpu_desc->neon)
244 /* "DSP" multiply instructions, eg. SMULxy. */
245 #define TARGET_DSP_MULTIPLY \
246 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
247 /* Integer SIMD instructions, and extend-accumulate instructions. */
248 #define TARGET_INT_SIMD \
249 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
251 /* Should MOVW/MOVT be used in preference to a constant pool. */
252 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
254 /* We could use unified syntax for arm mode, but for now we just use it
256 #define TARGET_UNIFIED_ASM TARGET_THUMB2
259 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
260 then TARGET_AAPCS_BASED must be true -- but the converse does not
261 hold. TARGET_BPABI implies the use of the BPABI runtime library,
262 etc., in addition to just the AAPCS calling conventions. */
264 #define TARGET_BPABI false
267 /* Support for a compile-time default CPU, et cetera. The rules are:
268 --with-arch is ignored if -march or -mcpu are specified.
269 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
271 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
273 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
275 --with-fpu is ignored if -mfpu is specified.
276 --with-abi is ignored is -mabi is specified. */
277 #define OPTION_DEFAULT_SPECS \
278 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
279 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
280 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
282 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
283 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
284 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
285 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
287 /* Which floating point model to use. */
290 ARM_FP_MODEL_UNKNOWN,
291 /* FPA model (Hardware or software). */
293 /* Cirrus Maverick floating point model. */
294 ARM_FP_MODEL_MAVERICK,
295 /* VFP floating point model. */
306 extern const struct arm_fpu_desc
309 enum arm_fp_model model;
311 enum vfp_reg_type regs;
316 /* Which floating point hardware to schedule for. */
317 extern int arm_fpu_attr;
322 ARM_FLOAT_ABI_SOFTFP,
326 extern enum float_abi_type arm_float_abi;
328 #ifndef TARGET_DEFAULT_FLOAT_ABI
329 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
332 /* Which __fp16 format to use.
333 The enumeration values correspond to the numbering for the
334 Tag_ABI_FP_16bit_format attribute.
336 enum arm_fp16_format_type
338 ARM_FP16_FORMAT_NONE = 0,
339 ARM_FP16_FORMAT_IEEE = 1,
340 ARM_FP16_FORMAT_ALTERNATIVE = 2
343 extern enum arm_fp16_format_type arm_fp16_format;
344 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
345 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
347 /* Which ABI to use. */
357 extern enum arm_abi_type arm_abi;
359 #ifndef ARM_DEFAULT_ABI
360 #define ARM_DEFAULT_ABI ARM_ABI_APCS
363 /* Which thread pointer access sequence to use. */
370 extern enum arm_tp_type target_thread_pointer;
372 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
373 extern int arm_arch3m;
375 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
376 extern int arm_arch4;
378 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
379 extern int arm_arch4t;
381 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
382 extern int arm_arch5;
384 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
385 extern int arm_arch5e;
387 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
388 extern int arm_arch6;
390 /* Nonzero if instructions not present in the 'M' profile can be used. */
391 extern int arm_arch_notm;
393 /* Nonzero if this chip can benefit from load scheduling. */
394 extern int arm_ld_sched;
396 /* Nonzero if generating thumb code. */
397 extern int thumb_code;
399 /* Nonzero if this chip is a StrongARM. */
400 extern int arm_tune_strongarm;
402 /* Nonzero if this chip is a Cirrus variant. */
403 extern int arm_arch_cirrus;
405 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
406 extern int arm_arch_iwmmxt;
408 /* Nonzero if this chip is an XScale. */
409 extern int arm_arch_xscale;
411 /* Nonzero if tuning for XScale. */
412 extern int arm_tune_xscale;
414 /* Nonzero if tuning for stores via the write buffer. */
415 extern int arm_tune_wbuf;
417 /* Nonzero if tuning for Cortex-A9. */
418 extern int arm_tune_cortex_a9;
420 /* Nonzero if we should define __THUMB_INTERWORK__ in the
422 XXX This is a bit of a hack, it's intended to help work around
423 problems in GLD which doesn't understand that armv5t code is
424 interworking clean. */
425 extern int arm_cpp_interwork;
427 /* Nonzero if chip supports Thumb 2. */
428 extern int arm_arch_thumb2;
430 /* Nonzero if chip supports integer division instruction. */
431 extern int arm_arch_hwdiv;
433 #ifndef TARGET_DEFAULT
434 #define TARGET_DEFAULT (MASK_APCS_FRAME)
437 /* The frame pointer register used in gcc has nothing to do with debugging;
438 that is controlled by the APCS-FRAME option. */
439 #define CAN_DEBUG_WITHOUT_FP
441 #define OVERRIDE_OPTIONS arm_override_options ()
443 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
444 arm_optimization_options ((LEVEL), (SIZE))
446 /* Nonzero if PIC code requires explicit qualifiers to generate
447 PLT and GOT relocs rather than the assembler doing so implicitly.
448 Subtargets can override these if required. */
449 #ifndef NEED_GOT_RELOC
450 #define NEED_GOT_RELOC 0
452 #ifndef NEED_PLT_RELOC
453 #define NEED_PLT_RELOC 0
456 /* Nonzero if we need to refer to the GOT with a PC-relative
457 offset. In other words, generate
459 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
463 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
465 The default is true, which matches NetBSD. Subtargets can
466 override this if required. */
471 /* Target machine storage Layout. */
474 /* Define this macro if it is advisable to hold scalars in registers
475 in a wider mode than that declared by the program. In such cases,
476 the value is constrained to be within the bounds of the declared
477 type, but kept valid in the wider mode. The signedness of the
478 extension may differ from that of the type. */
480 /* It is far faster to zero extend chars than to sign extend them */
482 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
483 if (GET_MODE_CLASS (MODE) == MODE_INT \
484 && GET_MODE_SIZE (MODE) < 4) \
486 if (MODE == QImode) \
488 else if (MODE == HImode) \
493 /* Define this if most significant bit is lowest numbered
494 in instructions that operate on numbered bit-fields. */
495 #define BITS_BIG_ENDIAN 0
497 /* Define this if most significant byte of a word is the lowest numbered.
498 Most ARM processors are run in little endian mode, so that is the default.
499 If you want to have it run-time selectable, change the definition in a
500 cover file to be TARGET_BIG_ENDIAN. */
501 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
503 /* Define this if most significant word of a multiword number is the lowest
505 This is always false, even when in big-endian mode. */
506 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
508 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
509 on processor pre-defineds when compiling libgcc2.c. */
510 #if defined(__ARMEB__) && !defined(__ARMWEL__)
511 #define LIBGCC2_WORDS_BIG_ENDIAN 1
513 #define LIBGCC2_WORDS_BIG_ENDIAN 0
516 /* Define this if most significant word of doubles is the lowest numbered.
517 The rules are different based on whether or not we use FPA-format,
518 VFP-format or some other floating point co-processor's format doubles. */
519 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
521 #define UNITS_PER_WORD 4
523 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
524 registers when autovectorizing for Neon, at least until multiple vector
525 widths are supported properly by the middle-end. */
526 #define UNITS_PER_SIMD_WORD(MODE) \
527 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
529 /* True if natural alignment is used for doubleword types. */
530 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
532 #define DOUBLEWORD_ALIGNMENT 64
534 #define PARM_BOUNDARY 32
536 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
538 #define PREFERRED_STACK_BOUNDARY \
539 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
541 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
543 /* The lowest bit is used to indicate Thumb-mode functions, so the
544 vbit must go into the delta field of pointers to member
546 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
548 #define EMPTY_FIELD_BOUNDARY 32
550 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
552 /* XXX Blah -- this macro is used directly by libobjc. Since it
553 supports no vector modes, cut out the complexity and fall back
554 on BIGGEST_FIELD_ALIGNMENT. */
555 #ifdef IN_TARGET_LIBS
556 #define BIGGEST_FIELD_ALIGNMENT 64
559 /* Make strings word-aligned so strcpy from constants will be faster. */
560 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
562 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
563 ((TREE_CODE (EXP) == STRING_CST \
565 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
566 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
568 /* Align definitions of arrays, unions and structures so that
569 initializations and copies can be made more efficient. This is not
570 ABI-changing, so it only affects places where we can see the
572 #define DATA_ALIGNMENT(EXP, ALIGN) \
573 ((((ALIGN) < BITS_PER_WORD) \
574 && (TREE_CODE (EXP) == ARRAY_TYPE \
575 || TREE_CODE (EXP) == UNION_TYPE \
576 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
578 /* Similarly, make sure that objects on the stack are sensibly aligned. */
579 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
581 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
582 value set in previous versions of this toolchain was 8, which produces more
583 compact structures. The command line option -mstructure_size_boundary=<n>
584 can be used to change this value. For compatibility with the ARM SDK
585 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
586 0020D) page 2-20 says "Structures are aligned on word boundaries".
587 The AAPCS specifies a value of 8. */
588 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
589 extern int arm_structure_size_boundary;
591 /* This is the value used to initialize arm_structure_size_boundary. If a
592 particular arm target wants to change the default value it should change
593 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
594 for an example of this. */
595 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
596 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
599 /* Nonzero if move instructions will actually fail to work
600 when given unaligned data. */
601 #define STRICT_ALIGNMENT 1
603 /* wchar_t is unsigned under the AAPCS. */
605 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
607 #define WCHAR_TYPE_SIZE BITS_PER_WORD
611 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
615 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
618 /* AAPCS requires that structure alignment is affected by bitfields. */
619 #ifndef PCC_BITFIELD_TYPE_MATTERS
620 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
624 /* Standard register usage. */
626 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
627 (S - saved over call).
629 r0 * argument word/integer result
632 r4-r8 S register variable
633 r9 S (rfp) register variable (real frame pointer)
635 r10 F S (sl) stack limit (used by -mapcs-stack-check)
636 r11 F S (fp) argument pointer
637 r12 (ip) temp workspace
638 r13 F S (sp) lower end of current stack frame
639 r14 (lr) link address/workspace
640 r15 F (pc) program counter
642 f0 floating point result
643 f1-f3 floating point scratch
645 f4-f7 S floating point variable
647 cc This is NOT a real register, but is used internally
648 to represent things that use or set the condition
650 sfp This isn't either. It is used during rtl generation
651 since the offset between the frame pointer and the
652 auto's isn't known until after register allocation.
653 afp Nor this, we only need this because of non-local
654 goto. Without it fp appears to be used and the
655 elimination code won't get rid of sfp. It tracks
656 fp exactly at all times.
658 *: See CONDITIONAL_REGISTER_USAGE */
661 mvf0 Cirrus floating point result
662 mvf1-mvf3 Cirrus floating point scratch
663 mvf4-mvf15 S Cirrus floating point variable. */
665 /* s0-s15 VFP scratch (aka d0-d7).
666 s16-s31 S VFP variable (aka d8-d15).
667 vfpcc Not a real register. Represents the VFP condition
670 /* The stack backtrace structure is as follows:
671 fp points to here: | save code pointer | [fp]
672 | return link value | [fp, #-4]
673 | return sp value | [fp, #-8]
674 | return fp value | [fp, #-12]
675 [| saved r10 value |]
686 [| saved f7 value |] three words
687 [| saved f6 value |] three words
688 [| saved f5 value |] three words
689 [| saved f4 value |] three words
690 r0-r3 are not normally saved in a C function. */
692 /* 1 for registers that have pervasive standard uses
693 and are not available for the register allocator. */
694 #define FIXED_REGISTERS \
716 /* 1 for registers not available across function calls.
717 These must include the FIXED_REGISTERS and also any
718 registers that can be used without being saved.
719 The latter must include the registers where values are returned
720 and the register where structure-value addresses are passed.
721 Aside from that, you can include as many other registers as you like.
722 The CC is not preserved over function calls on the ARM 6, so it is
723 easier to assume this for all. SFP is preserved, since FP is. */
724 #define CALL_USED_REGISTERS \
746 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
747 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
750 #define CONDITIONAL_REGISTER_USAGE \
754 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
756 for (regno = FIRST_FPA_REGNUM; \
757 regno <= LAST_FPA_REGNUM; ++regno) \
758 fixed_regs[regno] = call_used_regs[regno] = 1; \
761 if (TARGET_THUMB && optimize_size) \
763 /* When optimizing for size, it's better not to use \
764 the HI regs, because of the overhead of stacking \
766 /* ??? Is this still true for thumb2? */ \
767 for (regno = FIRST_HI_REGNUM; \
768 regno <= LAST_HI_REGNUM; ++regno) \
769 fixed_regs[regno] = call_used_regs[regno] = 1; \
772 /* The link register can be clobbered by any branch insn, \
773 but we have no way to track that at present, so mark \
774 it as unavailable. */ \
776 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
778 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
780 if (TARGET_MAVERICK) \
782 for (regno = FIRST_FPA_REGNUM; \
783 regno <= LAST_FPA_REGNUM; ++ regno) \
784 fixed_regs[regno] = call_used_regs[regno] = 1; \
785 for (regno = FIRST_CIRRUS_FP_REGNUM; \
786 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
788 fixed_regs[regno] = 0; \
789 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
794 /* VFPv3 registers are disabled when earlier VFP \
795 versions are selected due to the definition of \
796 LAST_VFP_REGNUM. */ \
797 for (regno = FIRST_VFP_REGNUM; \
798 regno <= LAST_VFP_REGNUM; ++ regno) \
800 fixed_regs[regno] = 0; \
801 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
802 || regno >= FIRST_VFP_REGNUM + 32; \
807 if (TARGET_REALLY_IWMMXT) \
809 regno = FIRST_IWMMXT_GR_REGNUM; \
810 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
811 and wCG1 as call-preserved registers. The 2002/11/21 \
812 revision changed this so that all wCG registers are \
813 scratch registers. */ \
814 for (regno = FIRST_IWMMXT_GR_REGNUM; \
815 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
816 fixed_regs[regno] = 0; \
817 /* The XScale ABI has wR0 - wR9 as scratch registers, \
818 the rest as call-preserved registers. */ \
819 for (regno = FIRST_IWMMXT_REGNUM; \
820 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
822 fixed_regs[regno] = 0; \
823 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
827 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
829 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
830 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
832 else if (TARGET_APCS_STACK) \
834 fixed_regs[10] = 1; \
835 call_used_regs[10] = 1; \
837 /* -mcaller-super-interworking reserves r11 for calls to \
838 _interwork_r11_call_via_rN(). Making the register global \
839 is an easy way of ensuring that it remains valid for all \
841 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
842 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
844 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
845 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
846 if (TARGET_CALLER_INTERWORKING) \
847 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
849 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
852 /* These are a couple of extensions to the formats accepted
854 %@ prints out ASM_COMMENT_START
855 %r prints out REGISTER_PREFIX reg_names[arg] */
856 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
858 fputs (ASM_COMMENT_START, FILE); \
862 fputs (REGISTER_PREFIX, FILE); \
863 fputs (reg_names [va_arg (ARGS, int)], FILE); \
866 /* Round X up to the nearest word. */
867 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
869 /* Convert fron bytes to ints. */
870 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
872 /* The number of (integer) registers required to hold a quantity of type MODE.
873 Also used for VFP registers. */
874 #define ARM_NUM_REGS(MODE) \
875 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
877 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
878 #define ARM_NUM_REGS2(MODE, TYPE) \
879 ARM_NUM_INTS ((MODE) == BLKmode ? \
880 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
882 /* The number of (integer) argument register available. */
883 #define NUM_ARG_REGS 4
885 /* And similarly for the VFP. */
886 #define NUM_VFP_ARG_REGS 16
888 /* Return the register number of the N'th (integer) argument. */
889 #define ARG_REGISTER(N) (N - 1)
891 /* Specify the registers used for certain standard purposes.
892 The values of these macros are register numbers. */
894 /* The number of the last argument register. */
895 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
897 /* The numbers of the Thumb register ranges. */
898 #define FIRST_LO_REGNUM 0
899 #define LAST_LO_REGNUM 7
900 #define FIRST_HI_REGNUM 8
901 #define LAST_HI_REGNUM 11
903 #ifndef TARGET_UNWIND_INFO
904 /* We use sjlj exceptions for backwards compatibility. */
905 #define MUST_USE_SJLJ_EXCEPTIONS 1
908 /* We can generate DWARF2 Unwind info, even though we don't use it. */
909 #define DWARF2_UNWIND_INFO 1
911 /* Use r0 and r1 to pass exception handling information. */
912 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
914 /* The register that holds the return address in exception handlers. */
915 #define ARM_EH_STACKADJ_REGNUM 2
916 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
918 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
919 as an invisible last argument (possible since varargs don't exist in
920 Pascal), so the following is not true. */
921 #define STATIC_CHAIN_REGNUM 12
923 /* Define this to be where the real frame pointer is if it is not possible to
924 work out the offset between the frame pointer and the automatic variables
925 until after register allocation has taken place. FRAME_POINTER_REGNUM
926 should point to a special register that we will make sure is eliminated.
928 For the Thumb we have another problem. The TPCS defines the frame pointer
929 as r11, and GCC believes that it is always possible to use the frame pointer
930 as base register for addressing purposes. (See comments in
931 find_reloads_address()). But - the Thumb does not allow high registers,
932 including r11, to be used as base address registers. Hence our problem.
934 The solution used here, and in the old thumb port is to use r7 instead of
935 r11 as the hard frame pointer and to have special code to generate
936 backtrace structures on the stack (if required to do so via a command line
937 option) using r11. This is the only 'user visible' use of r11 as a frame
939 #define ARM_HARD_FRAME_POINTER_REGNUM 11
940 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
942 #define HARD_FRAME_POINTER_REGNUM \
944 ? ARM_HARD_FRAME_POINTER_REGNUM \
945 : THUMB_HARD_FRAME_POINTER_REGNUM)
947 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
949 /* Register to use for pushing function arguments. */
950 #define STACK_POINTER_REGNUM SP_REGNUM
952 /* ARM floating pointer registers. */
953 #define FIRST_FPA_REGNUM 16
954 #define LAST_FPA_REGNUM 23
955 #define IS_FPA_REGNUM(REGNUM) \
956 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
958 #define FIRST_IWMMXT_GR_REGNUM 43
959 #define LAST_IWMMXT_GR_REGNUM 46
960 #define FIRST_IWMMXT_REGNUM 47
961 #define LAST_IWMMXT_REGNUM 62
962 #define IS_IWMMXT_REGNUM(REGNUM) \
963 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
964 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
965 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
967 /* Base register for access to local variables of the function. */
968 #define FRAME_POINTER_REGNUM 25
970 /* Base register for access to arguments of the function. */
971 #define ARG_POINTER_REGNUM 26
973 #define FIRST_CIRRUS_FP_REGNUM 27
974 #define LAST_CIRRUS_FP_REGNUM 42
975 #define IS_CIRRUS_REGNUM(REGNUM) \
976 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
978 #define FIRST_VFP_REGNUM 63
979 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
980 #define LAST_VFP_REGNUM \
981 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
983 #define IS_VFP_REGNUM(REGNUM) \
984 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
986 /* VFP registers are split into two types: those defined by VFP versions < 3
987 have D registers overlaid on consecutive pairs of S registers. VFP version 3
988 defines 16 new D registers (d16-d31) which, for simplicity and correctness
989 in various parts of the backend, we implement as "fake" single-precision
990 registers (which would be S32-S63, but cannot be used in that way). The
991 following macros define these ranges of registers. */
992 #define LAST_LO_VFP_REGNUM 94
993 #define FIRST_HI_VFP_REGNUM 95
994 #define LAST_HI_VFP_REGNUM 126
996 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
997 ((REGNUM) <= LAST_LO_VFP_REGNUM)
999 /* DFmode values are only valid in even register pairs. */
1000 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1001 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1003 /* Neon Quad values must start at a multiple of four registers. */
1004 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1005 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1007 /* Neon structures of vectors must be in even register pairs and there
1008 must be enough registers available. Because of various patterns
1009 requiring quad registers, we require them to start at a multiple of
1011 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1012 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1013 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1015 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1016 /* + 16 Cirrus registers take us up to 43. */
1017 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1018 /* VFP (VFP3) adds 32 (64) + 1 more. */
1019 #define FIRST_PSEUDO_REGISTER 128
1021 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1023 /* Value should be nonzero if functions must have frame pointers.
1024 Zero means the frame pointer need not be set up (and parms may be accessed
1025 via the stack pointer) in functions that seem suitable.
1026 If we have to have a frame pointer we might as well make use of it.
1027 APCS says that the frame pointer does not need to be pushed in leaf
1028 functions, or simple tail call functions. */
1030 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1031 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1034 /* Return number of consecutive hard regs needed starting at reg REGNO
1035 to hold something of mode MODE.
1036 This is ordinarily the length in words of a value of mode MODE
1037 but can be less for certain modes in special long registers.
1039 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1041 #define HARD_REGNO_NREGS(REGNO, MODE) \
1043 && REGNO >= FIRST_FPA_REGNUM \
1044 && REGNO != FRAME_POINTER_REGNUM \
1045 && REGNO != ARG_POINTER_REGNUM) \
1046 && !IS_VFP_REGNUM (REGNO) \
1047 ? 1 : ARM_NUM_REGS (MODE))
1049 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1050 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1051 arm_hard_regno_mode_ok ((REGNO), (MODE))
1053 /* Value is 1 if it is a good idea to tie two pseudo registers
1054 when one has mode MODE1 and one has mode MODE2.
1055 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1056 for any hard reg, then this must be 0 for correct output. */
1057 #define MODES_TIEABLE_P(MODE1, MODE2) \
1058 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1060 #define VALID_IWMMXT_REG_MODE(MODE) \
1061 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1063 /* Modes valid for Neon D registers. */
1064 #define VALID_NEON_DREG_MODE(MODE) \
1065 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1066 || (MODE) == V2SFmode || (MODE) == DImode)
1068 /* Modes valid for Neon Q registers. */
1069 #define VALID_NEON_QREG_MODE(MODE) \
1070 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1071 || (MODE) == V4SFmode || (MODE) == V2DImode)
1073 /* Structure modes valid for Neon registers. */
1074 #define VALID_NEON_STRUCT_MODE(MODE) \
1075 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1076 || (MODE) == CImode || (MODE) == XImode)
1078 /* The order in which register should be allocated. It is good to use ip
1079 since no saving is required (though calls clobber it) and it never contains
1080 function parameters. It is quite good to use lr since other calls may
1081 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1082 least likely to contain a function parameter; in addition results are
1084 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1085 then D8-D15. The reason for doing this is to attempt to reduce register
1086 pressure when both single- and double-precision registers are used in a
1089 #define REG_ALLOC_ORDER \
1091 3, 2, 1, 0, 12, 14, 4, 5, \
1092 6, 7, 8, 10, 9, 11, 13, 15, \
1093 16, 17, 18, 19, 20, 21, 22, 23, \
1094 27, 28, 29, 30, 31, 32, 33, 34, \
1095 35, 36, 37, 38, 39, 40, 41, 42, \
1096 43, 44, 45, 46, 47, 48, 49, 50, \
1097 51, 52, 53, 54, 55, 56, 57, 58, \
1100 95, 96, 97, 98, 99, 100, 101, 102, \
1101 103, 104, 105, 106, 107, 108, 109, 110, \
1102 111, 112, 113, 114, 115, 116, 117, 118, \
1103 119, 120, 121, 122, 123, 124, 125, 126, \
1104 78, 77, 76, 75, 74, 73, 72, 71, \
1105 70, 69, 68, 67, 66, 65, 64, 63, \
1106 79, 80, 81, 82, 83, 84, 85, 86, \
1107 87, 88, 89, 90, 91, 92, 93, 94, \
1111 /* Use different register alloc ordering for Thumb. */
1112 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
1114 /* Interrupt functions can only use registers that have already been
1115 saved by the prologue, even if they would normally be
1117 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1118 (! IS_INTERRUPT (cfun->machine->func_type) || \
1119 df_regs_ever_live_p (DST))
1121 /* Register and constant classes. */
1123 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1124 Now that the Thumb is involved it has become more complicated. */
1148 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1150 /* Give names of register classes as strings for dump file. */
1151 #define REG_CLASS_NAMES \
1173 /* Define which registers fit in which classes.
1174 This is an initializer for a vector of HARD_REG_SET
1175 of length N_REG_CLASSES. */
1176 #define REG_CLASS_CONTENTS \
1178 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1179 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1180 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1181 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1182 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1183 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1184 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1185 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1186 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1187 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1188 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1189 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1190 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1191 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1192 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1193 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1194 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1195 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1198 /* Any of the VFP register classes. */
1199 #define IS_VFP_CLASS(X) \
1200 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1201 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1203 /* The same information, inverted:
1204 Return the class number of the smallest class containing
1205 reg number REGNO. This could be a conditional expression
1206 or could index an array. */
1207 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1209 /* The following macro defines cover classes for Integrated Register
1210 Allocator. Cover classes is a set of non-intersected register
1211 classes covering all hard registers used for register allocation
1212 purpose. Any move between two registers of a cover class should be
1213 cheaper than load or store of the registers. The macro value is
1214 array of register classes with LIM_REG_CLASSES used as the end
1217 #define IRA_COVER_CLASSES \
1219 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1223 /* FPA registers can't do subreg as all values are reformatted to internal
1224 precision. VFP registers may only be accessed in the mode they
1226 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1227 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1228 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1229 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1232 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1233 using r0-r4 for function arguments, r7 for the stack frame and don't
1234 have enough left over to do doubleword arithmetic. */
1235 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1236 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1237 || (CLASS) == CC_REG)
1239 /* The class value for index registers, and the one for base regs. */
1240 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1241 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1243 /* For the Thumb the high registers cannot be used as base registers
1244 when addressing quantities in QI or HI mode; if we don't know the
1245 mode, then we must be conservative. */
1246 #define MODE_BASE_REG_CLASS(MODE) \
1247 (TARGET_32BIT ? CORE_REGS : \
1248 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1250 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1251 instead of BASE_REGS. */
1252 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1254 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1255 registers explicitly used in the rtl to be used as spill registers
1256 but prevents the compiler from extending the lifetime of these
1258 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1260 /* Given an rtx X being reloaded into a reg required to be
1261 in class CLASS, return the class of reg to actually use.
1262 In general this is just CLASS, but for the Thumb core registers and
1263 immediate constants we prefer a LO_REGS class or a subset. */
1264 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1265 (TARGET_ARM ? (CLASS) : \
1266 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1267 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1268 ? LO_REGS : (CLASS)))
1270 /* Must leave BASE_REGS reloads alone */
1271 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1272 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1273 ? ((true_regnum (X) == -1 ? LO_REGS \
1274 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1278 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1279 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1280 ? ((true_regnum (X) == -1 ? LO_REGS \
1281 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1285 /* Return the register class of a scratch register needed to copy IN into
1286 or out of a register in CLASS in MODE. If it can be done directly,
1287 NO_REGS is returned. */
1288 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1289 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1290 ((TARGET_VFP && TARGET_HARD_FLOAT \
1291 && IS_VFP_CLASS (CLASS)) \
1292 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1293 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1294 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1296 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1297 ? GENERAL_REGS : NO_REGS) \
1298 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1300 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1301 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1302 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1303 ((TARGET_VFP && TARGET_HARD_FLOAT \
1304 && IS_VFP_CLASS (CLASS)) \
1305 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1306 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1307 coproc_secondary_reload_class (MODE, X, TRUE) : \
1308 /* Cannot load constants into Cirrus registers. */ \
1309 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1310 && (CLASS) == CIRRUS_REGS \
1311 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1314 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1315 && CONSTANT_P (X)) \
1317 (((MODE) == HImode && ! arm_arch4 \
1318 && (GET_CODE (X) == MEM \
1319 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1320 && true_regnum (X) == -1))) \
1321 ? GENERAL_REGS : NO_REGS) \
1322 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1324 /* Try a machine-dependent way of reloading an illegitimate address
1325 operand. If we find one, push the reload and jump to WIN. This
1326 macro is used in only one place: `find_reloads_address' in reload.c.
1328 For the ARM, we wish to handle large displacements off a base
1329 register by splitting the addend across a MOV and the mem insn.
1330 This can cut the number of reloads needed. */
1331 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1334 if (GET_CODE (X) == PLUS \
1335 && GET_CODE (XEXP (X, 0)) == REG \
1336 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1337 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1338 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1340 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1341 HOST_WIDE_INT low, high; \
1343 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1344 low = ((val & 0xf) ^ 0x8) - 0x8; \
1345 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1346 /* Need to be careful, -256 is not a valid offset. */ \
1347 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1348 else if (MODE == SImode \
1349 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1350 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1351 /* Need to be careful, -4096 is not a valid offset. */ \
1352 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1353 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1354 /* Need to be careful, -256 is not a valid offset. */ \
1355 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1356 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1357 && TARGET_HARD_FLOAT && TARGET_FPA) \
1358 /* Need to be careful, -1024 is not a valid offset. */ \
1359 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1363 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1364 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1365 - (unsigned HOST_WIDE_INT) 0x80000000); \
1366 /* Check for overflow or zero */ \
1367 if (low == 0 || high == 0 || (high + low != val)) \
1370 /* Reload the high part into a base reg; leave the low part \
1372 X = gen_rtx_PLUS (GET_MODE (X), \
1373 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1376 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1377 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1378 VOIDmode, 0, 0, OPNUM, TYPE); \
1384 /* XXX If an HImode FP+large_offset address is converted to an HImode
1385 SP+large_offset address, then reload won't know how to fix it. It sees
1386 only that SP isn't valid for HImode, and so reloads the SP into an index
1387 register, but the resulting address is still invalid because the offset
1388 is too big. We fix it here instead by reloading the entire address. */
1389 /* We could probably achieve better results by defining PROMOTE_MODE to help
1390 cope with the variances between the Thumb's signed and unsigned byte and
1391 halfword load instructions. */
1392 /* ??? This should be safe for thumb2, but we may be able to do better. */
1393 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1395 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1403 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1405 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1407 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1409 /* Return the maximum number of consecutive registers
1410 needed to represent mode MODE in a register of class CLASS.
1411 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1412 #define CLASS_MAX_NREGS(CLASS, MODE) \
1413 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1415 /* If defined, gives a class of registers that cannot be used as the
1416 operand of a SUBREG that changes the mode of the object illegally. */
1418 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1419 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1420 it is typically more expensive than a single memory access. We set
1421 the cost to less than two memory accesses so that floating
1422 point to integer conversion does not go through memory. */
1423 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1425 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1426 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1427 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1428 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1429 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1430 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1431 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1432 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1433 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1436 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1438 /* Stack layout; function entry, exit and calling. */
1440 /* Define this if pushing a word on the stack
1441 makes the stack pointer a smaller address. */
1442 #define STACK_GROWS_DOWNWARD 1
1444 /* Define this to nonzero if the nominal address of the stack frame
1445 is at the high-address end of the local variables;
1446 that is, each additional local variable allocated
1447 goes at a more negative offset in the frame. */
1448 #define FRAME_GROWS_DOWNWARD 1
1450 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1451 When present, it is one word in size, and sits at the top of the frame,
1452 between the soft frame pointer and either r7 or r11.
1454 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1455 and only then if some outgoing arguments are passed on the stack. It would
1456 be tempting to also check whether the stack arguments are passed by indirect
1457 calls, but there seems to be no reason in principle why a post-reload pass
1458 couldn't convert a direct call into an indirect one. */
1459 #define CALLER_INTERWORKING_SLOT_SIZE \
1460 (TARGET_CALLER_INTERWORKING \
1461 && crtl->outgoing_args_size != 0 \
1462 ? UNITS_PER_WORD : 0)
1464 /* Offset within stack frame to start allocating local variables at.
1465 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1466 first local allocated. Otherwise, it is the offset to the BEGINNING
1467 of the first local allocated. */
1468 #define STARTING_FRAME_OFFSET 0
1470 /* If we generate an insn to push BYTES bytes,
1471 this says how many the stack pointer really advances by. */
1472 /* The push insns do not do this rounding implicitly.
1473 So don't define this. */
1474 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1476 /* Define this if the maximum size of all the outgoing args is to be
1477 accumulated and pushed during the prologue. The amount can be
1478 found in the variable crtl->outgoing_args_size. */
1479 #define ACCUMULATE_OUTGOING_ARGS 1
1481 /* Offset of first parameter from the argument pointer register value. */
1482 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1484 /* Value is the number of byte of arguments automatically
1485 popped when returning from a subroutine call.
1486 FUNDECL is the declaration node of the function (as a tree),
1487 FUNTYPE is the data type of the function (as a tree),
1488 or for a library call it is an identifier node for the subroutine name.
1489 SIZE is the number of bytes of arguments passed on the stack.
1491 On the ARM, the caller does not pop any of its arguments that were passed
1493 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1495 /* Define how to find the value returned by a library function
1496 assuming the value has mode MODE. */
1497 #define LIBCALL_VALUE(MODE) \
1498 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1499 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1500 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1501 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1502 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1503 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1504 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1505 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1506 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1507 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1509 /* 1 if REGNO is a possible register number for a function value. */
1510 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1511 ((REGNO) == ARG_REGISTER (1) \
1512 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1513 && TARGET_VFP && TARGET_HARD_FLOAT \
1514 && (REGNO) == FIRST_VFP_REGNUM) \
1515 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1516 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1517 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1518 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1519 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1521 /* Amount of memory needed for an untyped call to save all possible return
1523 #define APPLY_RESULT_SIZE arm_apply_result_size()
1525 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1526 values must be in memory. On the ARM, they need only do so if larger
1527 than a word, or if they contain elements offset from zero in the struct. */
1528 #define DEFAULT_PCC_STRUCT_RETURN 0
1530 /* These bits describe the different types of function supported
1531 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1532 normal function and an interworked function, for example. Knowing the
1533 type of a function is important for determining its prologue and
1535 Note value 7 is currently unassigned. Also note that the interrupt
1536 function types all have bit 2 set, so that they can be tested for easily.
1537 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1538 machine_function structure is initialized (to zero) func_type will
1539 default to unknown. This will force the first use of arm_current_func_type
1540 to call arm_compute_func_type. */
1541 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1542 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1543 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1544 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1545 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1546 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1548 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1550 /* In addition functions can have several type modifiers,
1551 outlined by these bit masks: */
1552 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1553 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1554 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1555 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1556 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1558 /* Some macros to test these flags. */
1559 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1560 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1561 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1562 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1563 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1564 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1567 /* Structure used to hold the function stack frame layout. Offsets are
1568 relative to the stack pointer on function entry. Positive offsets are
1569 in the direction of stack growth.
1570 Only soft_frame is used in thumb mode. */
1572 typedef struct GTY(()) arm_stack_offsets
1574 int saved_args; /* ARG_POINTER_REGNUM. */
1575 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1577 int soft_frame; /* FRAME_POINTER_REGNUM. */
1578 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1579 int outgoing_args; /* STACK_POINTER_REGNUM. */
1580 unsigned int saved_regs_mask;
1584 /* A C structure for machine-specific, per-function data.
1585 This is added to the cfun structure. */
1586 typedef struct GTY(()) machine_function
1588 /* Additional stack adjustment in __builtin_eh_throw. */
1589 rtx eh_epilogue_sp_ofs;
1590 /* Records if LR has to be saved for far jumps. */
1592 /* Records if ARG_POINTER was ever live. */
1593 int arg_pointer_live;
1594 /* Records if the save of LR has been eliminated. */
1595 int lr_save_eliminated;
1596 /* The size of the stack frame. Only valid after reload. */
1597 arm_stack_offsets stack_offsets;
1598 /* Records the type of the current function. */
1599 unsigned long func_type;
1600 /* Record if the function has a variable argument list. */
1601 int uses_anonymous_args;
1602 /* Records if sibcalls are blocked because an argument
1603 register is needed to preserve stack alignment. */
1604 int sibcall_blocked;
1605 /* The PIC register for this function. This might be a pseudo. */
1607 /* Labels for per-function Thumb call-via stubs. One per potential calling
1608 register. We can never call via LR or PC. We can call via SP if a
1609 trampoline happens to be on the top of the stack. */
1611 /* Set to 1 when a return insn is output, this means that the epilogue
1613 int return_used_this_function;
1617 /* As in the machine_function, a global set of call-via labels, for code
1618 that is in text_section. */
1619 extern GTY(()) rtx thumb_call_via_label[14];
1621 /* The number of potential ways of assigning to a co-processor. */
1622 #define ARM_NUM_COPROC_SLOTS 1
1624 /* Enumeration of procedure calling standard variants. We don't really
1625 support all of these yet. */
1628 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1629 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1630 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1631 /* This must be the last AAPCS variant. */
1632 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1633 ARM_PCS_ATPCS, /* ATPCS. */
1634 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1638 /* A C type for declaring a variable that is used as the first argument of
1639 `FUNCTION_ARG' and other related values. */
1642 /* This is the number of registers of arguments scanned so far. */
1644 /* This is the number of iWMMXt register arguments scanned so far. */
1648 /* Which procedure call variant to use for this call. */
1649 enum arm_pcs pcs_variant;
1651 /* AAPCS related state tracking. */
1652 int aapcs_arg_processed; /* No need to lay out this argument again. */
1653 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1654 this argument, or -1 if using core
1657 int aapcs_next_ncrn;
1658 rtx aapcs_reg; /* Register assigned to this argument. */
1659 int aapcs_partial; /* How many bytes are passed in regs (if
1660 split between core regs and stack.
1662 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1663 int can_split; /* Argument can be split between core regs
1665 /* Private data for tracking VFP register allocation */
1666 unsigned aapcs_vfp_regs_free;
1667 unsigned aapcs_vfp_reg_alloc;
1668 int aapcs_vfp_rcount;
1669 MACHMODE aapcs_vfp_rmode;
1672 /* Define where to put the arguments to a function.
1673 Value is zero to push the argument on the stack,
1674 or a hard register in which to store the argument.
1676 MODE is the argument's machine mode.
1677 TYPE is the data type of the argument (as a tree).
1678 This is null for libcalls where that information may
1680 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1681 the preceding args and about the function being called.
1682 NAMED is nonzero if this argument is a named parameter
1683 (otherwise it is an extra parameter matching an ellipsis).
1685 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1686 other arguments are passed on the stack. If (NAMED == 0) (which happens
1687 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1688 defined), say it is passed in the stack (function_prologue will
1689 indeed make it pass in the stack if necessary). */
1690 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1691 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1693 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1694 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1696 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1697 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1699 /* For AAPCS, padding should never be below the argument. For other ABIs,
1700 * mimic the default. */
1701 #define PAD_VARARGS_DOWN \
1702 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1704 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1705 for a call to a function whose data type is FNTYPE.
1706 For a library call, FNTYPE is 0.
1707 On the ARM, the offset starts at 0. */
1708 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1709 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1711 /* Update the data in CUM to advance over an argument
1712 of mode MODE and data type TYPE.
1713 (TYPE is null for libcalls where that information may not be available.) */
1714 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1715 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1717 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1718 argument with the specified mode and type. If it is not defined,
1719 `PARM_BOUNDARY' is used for all arguments. */
1720 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1721 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1722 ? DOUBLEWORD_ALIGNMENT \
1725 /* 1 if N is a possible register number for function argument passing.
1726 On the ARM, r0-r3 are used to pass args. */
1727 #define FUNCTION_ARG_REGNO_P(REGNO) \
1728 (IN_RANGE ((REGNO), 0, 3) \
1729 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1730 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1731 || (TARGET_IWMMXT_ABI \
1732 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1735 /* If your target environment doesn't prefix user functions with an
1736 underscore, you may wish to re-define this to prevent any conflicts. */
1737 #ifndef ARM_MCOUNT_NAME
1738 #define ARM_MCOUNT_NAME "*mcount"
1741 /* Call the function profiler with a given profile label. The Acorn
1742 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1743 On the ARM the full profile code will look like:
1752 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1753 will output the .text section.
1755 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1756 ``prof'' doesn't seem to mind about this!
1758 Note - this version of the code is designed to work in both ARM and
1760 #ifndef ARM_FUNCTION_PROFILER
1761 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1766 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1767 IP_REGNUM, LR_REGNUM); \
1768 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1769 fputc ('\n', STREAM); \
1770 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1771 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1772 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1776 #ifdef THUMB_FUNCTION_PROFILER
1777 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1779 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1781 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1783 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1784 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1787 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1788 the stack pointer does not matter. The value is tested only in
1789 functions that have frame pointers.
1790 No definition is equivalent to always zero.
1792 On the ARM, the function epilogue recovers the stack pointer from the
1794 #define EXIT_IGNORE_STACK 1
1796 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1798 /* Determine if the epilogue should be output as RTL.
1799 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1800 /* This is disabled for Thumb-2 because it will confuse the
1801 conditional insn counter. */
1802 #define USE_RETURN_INSN(ISCOND) \
1803 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1805 /* Definitions for register eliminations.
1807 This is an array of structures. Each structure initializes one pair
1808 of eliminable registers. The "from" register number is given first,
1809 followed by "to". Eliminations of the same "from" register are listed
1810 in order of preference.
1812 We have two registers that can be eliminated on the ARM. First, the
1813 arg pointer register can often be eliminated in favor of the stack
1814 pointer register. Secondly, the pseudo frame pointer register can always
1815 be eliminated; it is replaced with either the stack or the real frame
1816 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1817 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1819 #define ELIMINABLE_REGS \
1820 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1821 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1822 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1823 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1824 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1825 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1826 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1828 /* Define the offset between two registers, one to be eliminated, and the
1829 other its replacement, at the start of a routine. */
1830 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1832 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1834 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1836 /* Special case handling of the location of arguments passed on the stack. */
1837 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1839 /* Initialize data used by insn expanders. This is called from insn_emit,
1840 once for every function before code is generated. */
1841 #define INIT_EXPANDERS arm_init_expanders ()
1843 /* Length in units of the trampoline for entering a nested function. */
1844 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1846 /* Alignment required for a trampoline in bits. */
1847 #define TRAMPOLINE_ALIGNMENT 32
1849 /* Addressing modes, and classification of registers for them. */
1850 #define HAVE_POST_INCREMENT 1
1851 #define HAVE_PRE_INCREMENT TARGET_32BIT
1852 #define HAVE_POST_DECREMENT TARGET_32BIT
1853 #define HAVE_PRE_DECREMENT TARGET_32BIT
1854 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1855 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1856 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1857 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1859 /* Macros to check register numbers against specific register classes. */
1861 /* These assume that REGNO is a hard or pseudo reg number.
1862 They give nonzero only if REGNO is a hard reg of the suitable class
1863 or a pseudo reg currently allocated to a suitable hard reg.
1864 Since they use reg_renumber, they are safe only once reg_renumber
1865 has been allocated, which happens in local-alloc.c. */
1866 #define TEST_REGNO(R, TEST, VALUE) \
1867 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1869 /* Don't allow the pc to be used. */
1870 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1871 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1872 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1873 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1875 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1876 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1877 || (GET_MODE_SIZE (MODE) >= 4 \
1878 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1880 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1882 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1883 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1885 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1886 For Thumb, we can not use SP + reg, so reject SP. */
1887 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1888 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1890 /* For ARM code, we don't care about the mode, but for Thumb, the index
1891 must be suitable for use in a QImode load. */
1892 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1893 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1894 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1896 /* Maximum number of registers that can appear in a valid memory address.
1897 Shifts in addresses can't be by a register. */
1898 #define MAX_REGS_PER_ADDRESS 2
1900 /* Recognize any constant value that is a valid address. */
1901 /* XXX We can address any constant, eventually... */
1902 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1903 #define CONSTANT_ADDRESS_P(X) \
1904 (GET_CODE (X) == SYMBOL_REF \
1905 && (CONSTANT_POOL_ADDRESS_P (X) \
1906 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1908 /* True if SYMBOL + OFFSET constants must refer to something within
1909 SYMBOL's section. */
1910 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1912 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1913 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1914 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1917 /* Nonzero if the constant value X is a legitimate general operand.
1918 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1920 On the ARM, allow any integer (invalid ones are removed later by insn
1921 patterns), nice doubles and symbol_refs which refer to the function's
1924 When generating pic allow anything. */
1925 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1927 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1928 ( GET_CODE (X) == CONST_INT \
1929 || GET_CODE (X) == CONST_DOUBLE \
1930 || CONSTANT_ADDRESS_P (X) \
1933 #define LEGITIMATE_CONSTANT_P(X) \
1934 (!arm_cannot_force_const_mem (X) \
1935 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1936 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1938 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1939 #define SUBTARGET_NAME_ENCODING_LENGTHS
1942 /* This is a C fragment for the inside of a switch statement.
1943 Each case label should return the number of characters to
1944 be stripped from the start of a function's name, if that
1945 name starts with the indicated character. */
1946 #define ARM_NAME_ENCODING_LENGTHS \
1947 case '*': return 1; \
1948 SUBTARGET_NAME_ENCODING_LENGTHS
1950 /* This is how to output a reference to a user-level label named NAME.
1951 `assemble_name' uses this. */
1952 #undef ASM_OUTPUT_LABELREF
1953 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1954 arm_asm_output_labelref (FILE, NAME)
1956 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1957 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1958 if (TARGET_THUMB2) \
1959 thumb2_asm_output_opcode (STREAM);
1961 /* The EABI specifies that constructors should go in .init_array.
1962 Other targets use .ctors for compatibility. */
1963 #ifndef ARM_EABI_CTORS_SECTION_OP
1964 #define ARM_EABI_CTORS_SECTION_OP \
1965 "\t.section\t.init_array,\"aw\",%init_array"
1967 #ifndef ARM_EABI_DTORS_SECTION_OP
1968 #define ARM_EABI_DTORS_SECTION_OP \
1969 "\t.section\t.fini_array,\"aw\",%fini_array"
1971 #define ARM_CTORS_SECTION_OP \
1972 "\t.section\t.ctors,\"aw\",%progbits"
1973 #define ARM_DTORS_SECTION_OP \
1974 "\t.section\t.dtors,\"aw\",%progbits"
1976 /* Define CTORS_SECTION_ASM_OP. */
1977 #undef CTORS_SECTION_ASM_OP
1978 #undef DTORS_SECTION_ASM_OP
1980 # define CTORS_SECTION_ASM_OP \
1981 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1982 # define DTORS_SECTION_ASM_OP \
1983 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1984 #else /* !defined (IN_LIBGCC2) */
1985 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1986 so we cannot use the definition above. */
1987 # ifdef __ARM_EABI__
1988 /* The .ctors section is not part of the EABI, so we do not define
1989 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1990 from trying to use it. We do define it when doing normal
1991 compilation, as .init_array can be used instead of .ctors. */
1992 /* There is no need to emit begin or end markers when using
1993 init_array; the dynamic linker will compute the size of the
1994 array itself based on special symbols created by the static
1995 linker. However, we do need to arrange to set up
1996 exception-handling here. */
1997 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1998 # define CTOR_LIST_END /* empty */
1999 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2000 # define DTOR_LIST_END /* empty */
2001 # else /* !defined (__ARM_EABI__) */
2002 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2003 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2004 # endif /* !defined (__ARM_EABI__) */
2005 #endif /* !defined (IN_LIBCC2) */
2007 /* True if the operating system can merge entities with vague linkage
2008 (e.g., symbols in COMDAT group) during dynamic linking. */
2009 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2010 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2013 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2015 #ifdef TARGET_UNWIND_INFO
2016 #define ARM_EABI_UNWIND_TABLES \
2017 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2019 #define ARM_EABI_UNWIND_TABLES 0
2022 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2023 and check its validity for a certain class.
2024 We have two alternate definitions for each of them.
2025 The usual definition accepts all pseudo regs; the other rejects
2026 them unless they have been allocated suitable hard regs.
2027 The symbol REG_OK_STRICT causes the latter definition to be used.
2028 Thumb-2 has the same restrictions as arm. */
2029 #ifndef REG_OK_STRICT
2031 #define ARM_REG_OK_FOR_BASE_P(X) \
2032 (REGNO (X) <= LAST_ARM_REGNUM \
2033 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2034 || REGNO (X) == FRAME_POINTER_REGNUM \
2035 || REGNO (X) == ARG_POINTER_REGNUM)
2037 #define ARM_REG_OK_FOR_INDEX_P(X) \
2038 ((REGNO (X) <= LAST_ARM_REGNUM \
2039 && REGNO (X) != STACK_POINTER_REGNUM) \
2040 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2041 || REGNO (X) == FRAME_POINTER_REGNUM \
2042 || REGNO (X) == ARG_POINTER_REGNUM)
2044 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2045 (REGNO (X) <= LAST_LO_REGNUM \
2046 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2047 || (GET_MODE_SIZE (MODE) >= 4 \
2048 && (REGNO (X) == STACK_POINTER_REGNUM \
2049 || (X) == hard_frame_pointer_rtx \
2050 || (X) == arg_pointer_rtx)))
2052 #define REG_STRICT_P 0
2054 #else /* REG_OK_STRICT */
2056 #define ARM_REG_OK_FOR_BASE_P(X) \
2057 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2059 #define ARM_REG_OK_FOR_INDEX_P(X) \
2060 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2062 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2063 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2065 #define REG_STRICT_P 1
2067 #endif /* REG_OK_STRICT */
2069 /* Now define some helpers in terms of the above. */
2071 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2073 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2074 : ARM_REG_OK_FOR_BASE_P (X))
2076 /* For 16-bit Thumb, a valid index register is anything that can be used in
2077 a byte load instruction. */
2078 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2079 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2081 /* Nonzero if X is a hard reg that can be used as an index
2082 or if it is a pseudo reg. On the Thumb, the stack pointer
2084 #define REG_OK_FOR_INDEX_P(X) \
2086 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2087 : ARM_REG_OK_FOR_INDEX_P (X))
2089 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2090 For Thumb, we can not use SP + reg, so reject SP. */
2091 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2092 REG_OK_FOR_INDEX_P (X)
2094 #define ARM_BASE_REGISTER_RTX_P(X) \
2095 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2097 #define ARM_INDEX_REGISTER_RTX_P(X) \
2098 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2100 /* Define this for compatibility reasons. */
2101 #define HANDLE_PRAGMA_PACK_PUSH_POP
2103 /* Specify the machine mode that this machine uses
2104 for the index in the tablejump instruction. */
2105 #define CASE_VECTOR_MODE Pmode
2107 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2109 && (optimize_size || flag_pic)))
2111 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2113 ? (min >= 0 && max < 512 \
2114 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2115 : min >= -256 && max < 256 \
2116 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2117 : min >= 0 && max < 8192 \
2118 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2119 : min >= -4096 && max < 4096 \
2120 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2122 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2123 : (max >= 0x200) ? HImode \
2126 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2127 unsigned is probably best, but may break some code. */
2128 #ifndef DEFAULT_SIGNED_CHAR
2129 #define DEFAULT_SIGNED_CHAR 0
2132 /* Max number of bytes we can move from memory to memory
2133 in one reasonably fast instruction. */
2137 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2139 /* Define if operations between registers always perform the operation
2140 on the full register even if a narrower mode is specified. */
2141 #define WORD_REGISTER_OPERATIONS
2143 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2144 will either zero-extend or sign-extend. The value of this macro should
2145 be the code that says which one of the two operations is implicitly
2146 done, UNKNOWN if none. */
2147 #define LOAD_EXTEND_OP(MODE) \
2148 (TARGET_THUMB ? ZERO_EXTEND : \
2149 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2150 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2152 /* Nonzero if access to memory by bytes is slow and undesirable. */
2153 #define SLOW_BYTE_ACCESS 0
2155 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2157 /* Immediate shift counts are truncated by the output routines (or was it
2158 the assembler?). Shift counts in a register are truncated by ARM. Note
2159 that the native compiler puts too large (> 32) immediate shift counts
2160 into a register and shifts by the register, letting the ARM decide what
2161 to do instead of doing that itself. */
2162 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2163 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2164 On the arm, Y in a register is used modulo 256 for the shift. Only for
2165 rotates is modulo 32 used. */
2166 /* #define SHIFT_COUNT_TRUNCATED 1 */
2168 /* All integers have the same format so truncation is easy. */
2169 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2171 /* Calling from registers is a massive pain. */
2172 #define NO_FUNCTION_CSE 1
2174 /* The machine modes of pointers and functions */
2175 #define Pmode SImode
2176 #define FUNCTION_MODE Pmode
2178 #define ARM_FRAME_RTX(X) \
2179 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2180 || (X) == arg_pointer_rtx)
2182 /* Moves to and from memory are quite expensive */
2183 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2184 (TARGET_32BIT ? 10 : \
2185 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2186 * (CLASS == LO_REGS ? 1 : 2)))
2188 /* Try to generate sequences that don't involve branches, we can then use
2189 conditional instructions */
2190 #define BRANCH_COST(speed_p, predictable_p) \
2191 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2193 /* Position Independent Code. */
2194 /* We decide which register to use based on the compilation options and
2195 the assembler in use; this is more general than the APCS restriction of
2196 using sb (r9) all the time. */
2197 extern unsigned arm_pic_register;
2199 /* The register number of the register used to address a table of static
2200 data addresses in memory. */
2201 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2203 /* We can't directly access anything that contains a symbol,
2204 nor can we indirect via the constant pool. One exception is
2205 UNSPEC_TLS, which is always PIC. */
2206 #define LEGITIMATE_PIC_OPERAND_P(X) \
2207 (!(symbol_mentioned_p (X) \
2208 || label_mentioned_p (X) \
2209 || (GET_CODE (X) == SYMBOL_REF \
2210 && CONSTANT_POOL_ADDRESS_P (X) \
2211 && (symbol_mentioned_p (get_pool_constant (X)) \
2212 || label_mentioned_p (get_pool_constant (X))))) \
2213 || tls_mentioned_p (X))
2215 /* We need to know when we are making a constant pool; this determines
2216 whether data needs to be in the GOT or can be referenced via a GOT
2218 extern int making_const_table;
2220 /* Handle pragmas for compatibility with Intel's compilers. */
2221 /* Also abuse this to register additional C specific EABI attributes. */
2222 #define REGISTER_TARGET_PRAGMAS() do { \
2223 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2224 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2225 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2226 arm_lang_object_attributes_init(); \
2229 /* Condition code information. */
2230 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2231 return the mode to be used for the comparison. */
2233 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2235 #define REVERSIBLE_CC_MODE(MODE) 1
2237 #define REVERSE_CONDITION(CODE,MODE) \
2238 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2239 ? reverse_condition_maybe_unordered (code) \
2240 : reverse_condition (code))
2242 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2245 if (GET_CODE (OP1) == CONST_INT \
2246 && ! (const_ok_for_arm (INTVAL (OP1)) \
2247 || (const_ok_for_arm (- INTVAL (OP1))))) \
2249 rtx const_op = OP1; \
2250 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2257 /* The arm5 clz instruction returns 32. */
2258 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2259 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2262 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2263 TARGET_THUMB2 ? "\t.thumb\n" : "")
2265 /* Output a push or a pop instruction (only used when profiling). */
2266 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2270 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2271 STACK_POINTER_REGNUM, REGNO); \
2273 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2277 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2281 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2282 STACK_POINTER_REGNUM, REGNO); \
2284 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2287 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2288 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2290 /* This is how to output a label which precedes a jumptable. Since
2291 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2292 #undef ASM_OUTPUT_CASE_LABEL
2293 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2296 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2297 ASM_OUTPUT_ALIGN (FILE, 2); \
2298 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2302 /* Make sure subsequent insns are aligned after a TBB. */
2303 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2306 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2307 ASM_OUTPUT_ALIGN (FILE, 1); \
2311 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2316 if (is_called_in_ARM_mode (DECL) \
2317 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2318 && cfun->is_thunk)) \
2319 fprintf (STREAM, "\t.code 32\n") ; \
2320 else if (TARGET_THUMB1) \
2321 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2323 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2325 if (TARGET_POKE_FUNCTION_NAME) \
2326 arm_poke_function_name (STREAM, (const char *) NAME); \
2330 /* For aliases of functions we use .thumb_set instead. */
2331 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2334 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2335 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2337 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2339 fprintf (FILE, "\t.thumb_set "); \
2340 assemble_name (FILE, LABEL1); \
2341 fprintf (FILE, ","); \
2342 assemble_name (FILE, LABEL2); \
2343 fprintf (FILE, "\n"); \
2346 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2350 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2351 /* To support -falign-* switches we need to use .p2align so
2352 that alignment directives in code sections will be padded
2353 with no-op instructions, rather than zeroes. */
2354 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2357 if ((MAX_SKIP) == 0) \
2358 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2360 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2361 (int) (LOG), (int) (MAX_SKIP)); \
2365 /* Add two bytes to the length of conditionally executed Thumb-2
2366 instructions for the IT instruction. */
2367 #define ADJUST_INSN_LENGTH(insn, length) \
2368 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2371 /* Only perform branch elimination (by making instructions conditional) if
2372 we're optimizing. For Thumb-2 check if any IT instructions need
2374 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2375 if (TARGET_ARM && optimize) \
2376 arm_final_prescan_insn (INSN); \
2377 else if (TARGET_THUMB2) \
2378 thumb2_final_prescan_insn (INSN); \
2379 else if (TARGET_THUMB1) \
2380 thumb1_final_prescan_insn (INSN)
2382 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2383 (CODE == '@' || CODE == '|' || CODE == '.' \
2384 || CODE == '(' || CODE == ')' || CODE == '#' \
2385 || (TARGET_32BIT && (CODE == '?')) \
2386 || (TARGET_THUMB2 && (CODE == '!')) \
2387 || (TARGET_THUMB && (CODE == '_')))
2389 /* Output an operand of an instruction. */
2390 #define PRINT_OPERAND(STREAM, X, CODE) \
2391 arm_print_operand (STREAM, X, CODE)
2393 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2394 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2395 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2396 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2397 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2398 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2401 /* Output the address of an operand. */
2402 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2404 int is_minus = GET_CODE (X) == MINUS; \
2406 if (GET_CODE (X) == REG) \
2407 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2408 else if (GET_CODE (X) == PLUS || is_minus) \
2410 rtx base = XEXP (X, 0); \
2411 rtx index = XEXP (X, 1); \
2412 HOST_WIDE_INT offset = 0; \
2413 if (GET_CODE (base) != REG \
2414 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2416 /* Ensure that BASE is a register. */ \
2417 /* (one of them must be). */ \
2418 /* Also ensure the SP is not used as in index register. */ \
2423 switch (GET_CODE (index)) \
2426 offset = INTVAL (index); \
2429 asm_fprintf (STREAM, "[%r, #%wd]", \
2430 REGNO (base), offset); \
2434 asm_fprintf (STREAM, "[%r, %s%r]", \
2435 REGNO (base), is_minus ? "-" : "", \
2445 asm_fprintf (STREAM, "[%r, %s%r", \
2446 REGNO (base), is_minus ? "-" : "", \
2447 REGNO (XEXP (index, 0))); \
2448 arm_print_operand (STREAM, index, 'S'); \
2449 fputs ("]", STREAM); \
2454 gcc_unreachable (); \
2457 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2458 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2460 extern enum machine_mode output_memory_reference_mode; \
2462 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2464 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2465 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2466 REGNO (XEXP (X, 0)), \
2467 GET_CODE (X) == PRE_DEC ? "-" : "", \
2468 GET_MODE_SIZE (output_memory_reference_mode)); \
2470 asm_fprintf (STREAM, "[%r], #%s%d", \
2471 REGNO (XEXP (X, 0)), \
2472 GET_CODE (X) == POST_DEC ? "-" : "", \
2473 GET_MODE_SIZE (output_memory_reference_mode)); \
2475 else if (GET_CODE (X) == PRE_MODIFY) \
2477 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2478 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2479 asm_fprintf (STREAM, "#%wd]!", \
2480 INTVAL (XEXP (XEXP (X, 1), 1))); \
2482 asm_fprintf (STREAM, "%r]!", \
2483 REGNO (XEXP (XEXP (X, 1), 1))); \
2485 else if (GET_CODE (X) == POST_MODIFY) \
2487 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2488 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2489 asm_fprintf (STREAM, "#%wd", \
2490 INTVAL (XEXP (XEXP (X, 1), 1))); \
2492 asm_fprintf (STREAM, "%r", \
2493 REGNO (XEXP (XEXP (X, 1), 1))); \
2495 else output_addr_const (STREAM, X); \
2498 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2500 if (GET_CODE (X) == REG) \
2501 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2502 else if (GET_CODE (X) == POST_INC) \
2503 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2504 else if (GET_CODE (X) == PLUS) \
2506 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2507 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2508 asm_fprintf (STREAM, "[%r, #%wd]", \
2509 REGNO (XEXP (X, 0)), \
2510 INTVAL (XEXP (X, 1))); \
2512 asm_fprintf (STREAM, "[%r, %r]", \
2513 REGNO (XEXP (X, 0)), \
2514 REGNO (XEXP (X, 1))); \
2517 output_addr_const (STREAM, X); \
2520 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2522 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2524 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2526 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2527 if (arm_output_addr_const_extra (file, x) == FALSE) \
2530 /* A C expression whose value is RTL representing the value of the return
2531 address for the frame COUNT steps up from the current frame. */
2533 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2534 arm_return_addr (COUNT, FRAME)
2536 /* Mask of the bits in the PC that contain the real return address
2537 when running in 26-bit mode. */
2538 #define RETURN_ADDR_MASK26 (0x03fffffc)
2540 /* Pick up the return address upon entry to a procedure. Used for
2541 dwarf2 unwind information. This also enables the table driven
2543 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2544 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2546 /* Used to mask out junk bits from the return address, such as
2547 processor state, interrupt status, condition codes and the like. */
2548 #define MASK_RETURN_ADDR \
2549 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2550 in 26 bit mode, the condition codes must be masked out of the \
2551 return address. This does not apply to ARM6 and later processors \
2552 when running in 32 bit mode. */ \
2553 ((arm_arch4 || TARGET_THUMB) \
2554 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2555 : arm_gen_return_addr_mask ())
2558 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2559 symbolic names defined here (which would require too much duplication).
2568 ARM_BUILTIN_WAVG2BR,
2569 ARM_BUILTIN_WAVG2HR,
2596 ARM_BUILTIN_TMOVMSKB,
2597 ARM_BUILTIN_TMOVMSKH,
2598 ARM_BUILTIN_TMOVMSKW,
2607 ARM_BUILTIN_WPACKHSS,
2608 ARM_BUILTIN_WPACKWSS,
2609 ARM_BUILTIN_WPACKDSS,
2610 ARM_BUILTIN_WPACKHUS,
2611 ARM_BUILTIN_WPACKWUS,
2612 ARM_BUILTIN_WPACKDUS,
2617 ARM_BUILTIN_WADDSSB,
2618 ARM_BUILTIN_WADDSSH,
2619 ARM_BUILTIN_WADDSSW,
2620 ARM_BUILTIN_WADDUSB,
2621 ARM_BUILTIN_WADDUSH,
2622 ARM_BUILTIN_WADDUSW,
2626 ARM_BUILTIN_WSUBSSB,
2627 ARM_BUILTIN_WSUBSSH,
2628 ARM_BUILTIN_WSUBSSW,
2629 ARM_BUILTIN_WSUBUSB,
2630 ARM_BUILTIN_WSUBUSH,
2631 ARM_BUILTIN_WSUBUSW,
2638 ARM_BUILTIN_WCMPEQB,
2639 ARM_BUILTIN_WCMPEQH,
2640 ARM_BUILTIN_WCMPEQW,
2641 ARM_BUILTIN_WCMPGTUB,
2642 ARM_BUILTIN_WCMPGTUH,
2643 ARM_BUILTIN_WCMPGTUW,
2644 ARM_BUILTIN_WCMPGTSB,
2645 ARM_BUILTIN_WCMPGTSH,
2646 ARM_BUILTIN_WCMPGTSW,
2648 ARM_BUILTIN_TEXTRMSB,
2649 ARM_BUILTIN_TEXTRMSH,
2650 ARM_BUILTIN_TEXTRMSW,
2651 ARM_BUILTIN_TEXTRMUB,
2652 ARM_BUILTIN_TEXTRMUH,
2653 ARM_BUILTIN_TEXTRMUW,
2703 ARM_BUILTIN_WUNPCKIHB,
2704 ARM_BUILTIN_WUNPCKIHH,
2705 ARM_BUILTIN_WUNPCKIHW,
2706 ARM_BUILTIN_WUNPCKILB,
2707 ARM_BUILTIN_WUNPCKILH,
2708 ARM_BUILTIN_WUNPCKILW,
2710 ARM_BUILTIN_WUNPCKEHSB,
2711 ARM_BUILTIN_WUNPCKEHSH,
2712 ARM_BUILTIN_WUNPCKEHSW,
2713 ARM_BUILTIN_WUNPCKEHUB,
2714 ARM_BUILTIN_WUNPCKEHUH,
2715 ARM_BUILTIN_WUNPCKEHUW,
2716 ARM_BUILTIN_WUNPCKELSB,
2717 ARM_BUILTIN_WUNPCKELSH,
2718 ARM_BUILTIN_WUNPCKELSW,
2719 ARM_BUILTIN_WUNPCKELUB,
2720 ARM_BUILTIN_WUNPCKELUH,
2721 ARM_BUILTIN_WUNPCKELUW,
2723 ARM_BUILTIN_THREAD_POINTER,
2725 ARM_BUILTIN_NEON_BASE,
2727 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2730 /* Do not emit .note.GNU-stack by default. */
2731 #ifndef NEED_INDICATE_EXEC_STACK
2732 #define NEED_INDICATE_EXEC_STACK 0
2735 #endif /* ! GCC_ARM_H */
OSDN Git Service
