1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx, int, int, int *);
132 static int arm_address_cost (rtx);
133 static bool arm_memory_load_p (rtx);
134 static bool arm_cirrus_insn_p (rtx);
135 static void cirrus_reorg (rtx);
136 static void arm_init_builtins (void);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx safe_vector_operand (rtx, enum machine_mode);
140 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
141 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
142 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
143 static void emit_constant_insn (rtx cond, rtx pattern);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree, rtx, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx arm_struct_value_rtx (tree, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
161 static bool arm_promote_prototypes (tree);
162 static bool arm_default_short_enums (void);
163 static bool arm_align_anon_bitfield (void);
166 /* Initialize the GCC target structure. */
167 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
168 #undef TARGET_MERGE_DECL_ATTRIBUTES
169 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
172 #undef TARGET_ATTRIBUTE_TABLE
173 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
176 #undef TARGET_ASM_BYTE_OP
177 #define TARGET_ASM_BYTE_OP "\tDCB\t"
178 #undef TARGET_ASM_ALIGNED_HI_OP
179 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
180 #undef TARGET_ASM_ALIGNED_SI_OP
181 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
182 #undef TARGET_ASM_GLOBALIZE_LABEL
183 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
184 #undef TARGET_ASM_FILE_START
185 #define TARGET_ASM_FILE_START aof_file_start
186 #undef TARGET_ASM_FILE_END
187 #define TARGET_ASM_FILE_END aof_file_end
189 #undef TARGET_ASM_ALIGNED_SI_OP
190 #define TARGET_ASM_ALIGNED_SI_OP NULL
191 #undef TARGET_ASM_INTEGER
192 #define TARGET_ASM_INTEGER arm_assemble_integer
195 #undef TARGET_ASM_FUNCTION_PROLOGUE
196 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
198 #undef TARGET_ASM_FUNCTION_EPILOGUE
199 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
201 #undef TARGET_COMP_TYPE_ATTRIBUTES
202 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
204 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
205 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
207 #undef TARGET_SCHED_ADJUST_COST
208 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
210 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
211 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
213 #undef TARGET_ENCODE_SECTION_INFO
215 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
217 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
220 #undef TARGET_STRIP_NAME_ENCODING
221 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
223 #undef TARGET_ASM_INTERNAL_LABEL
224 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
226 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
227 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
229 #undef TARGET_ASM_OUTPUT_MI_THUNK
230 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
231 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
232 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
234 /* This will be overridden in arm_override_options. */
235 #undef TARGET_RTX_COSTS
236 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
237 #undef TARGET_ADDRESS_COST
238 #define TARGET_ADDRESS_COST arm_address_cost
240 #undef TARGET_MACHINE_DEPENDENT_REORG
241 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
243 #undef TARGET_INIT_BUILTINS
244 #define TARGET_INIT_BUILTINS arm_init_builtins
245 #undef TARGET_EXPAND_BUILTIN
246 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
248 #undef TARGET_PROMOTE_FUNCTION_ARGS
249 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
250 #undef TARGET_PROMOTE_FUNCTION_RETURN
251 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
252 #undef TARGET_PROMOTE_PROTOTYPES
253 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
255 #undef TARGET_STRUCT_VALUE_RTX
256 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
258 #undef TARGET_SETUP_INCOMING_VARARGS
259 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
261 #undef TARGET_DEFAULT_SHORT_ENUMS
262 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
264 #undef TARGET_ALIGN_ANON_BITFIELD
265 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
267 struct gcc_target targetm = TARGET_INITIALIZER;
269 /* Obstack for minipool constant handling. */
270 static struct obstack minipool_obstack;
271 static char * minipool_startobj;
273 /* The maximum number of insns skipped which
274 will be conditionalised if possible. */
275 static int max_insns_skipped = 5;
277 extern FILE * asm_out_file;
279 /* True if we are currently building a constant table. */
280 int making_const_table;
282 /* Define the information needed to generate branch insns. This is
283 stored from the compare operation. */
284 rtx arm_compare_op0, arm_compare_op1;
286 /* The processor for which instructions should be scheduled. */
287 enum processor_type arm_tune = arm_none;
289 /* Which floating point model to use. */
290 enum arm_fp_model arm_fp_model;
292 /* Which floating point hardware is available. */
293 enum fputype arm_fpu_arch;
295 /* Which floating point hardware to schedule for. */
296 enum fputype arm_fpu_tune;
298 /* Whether to use floating point hardware. */
299 enum float_abi_type arm_float_abi;
301 /* Which ABI to use. */
302 enum arm_abi_type arm_abi;
304 /* Set by the -mfpu=... option. */
305 const char * target_fpu_name = NULL;
307 /* Set by the -mfpe=... option. */
308 const char * target_fpe_name = NULL;
310 /* Set by the -mfloat-abi=... option. */
311 const char * target_float_abi_name = NULL;
313 /* Set by the -mabi=... option. */
314 const char * target_abi_name = NULL;
316 /* Used to parse -mstructure_size_boundary command line option. */
317 const char * structure_size_string = NULL;
318 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
320 /* Bit values used to identify processor capabilities. */
321 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
322 #define FL_ARCH3M (1 << 1) /* Extended multiply */
323 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
324 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
325 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
326 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
327 #define FL_THUMB (1 << 6) /* Thumb aware */
328 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
329 #define FL_STRONG (1 << 8) /* StrongARM */
330 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
331 #define FL_XSCALE (1 << 10) /* XScale */
332 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
333 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
334 media instructions. */
335 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
337 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
339 #define FL_FOR_ARCH2 0
340 #define FL_FOR_ARCH3 FL_MODE32
341 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
342 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
343 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
344 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
345 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
346 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
347 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
348 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
349 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
350 #define FL_FOR_ARCH6J FL_FOR_ARCH6
352 /* The bits in this mask specify which
353 instructions we are allowed to generate. */
354 static unsigned long insn_flags = 0;
356 /* The bits in this mask specify which instruction scheduling options should
358 static unsigned long tune_flags = 0;
360 /* The following are used in the arm.md file as equivalents to bits
361 in the above two flag variables. */
363 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
366 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
369 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
372 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
375 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
378 /* Nonzero if this chip can benefit from load scheduling. */
379 int arm_ld_sched = 0;
381 /* Nonzero if this chip is a StrongARM. */
382 int arm_is_strong = 0;
384 /* Nonzero if this chip is a Cirrus variant. */
385 int arm_arch_cirrus = 0;
387 /* Nonzero if this chip supports Intel Wireless MMX technology. */
388 int arm_arch_iwmmxt = 0;
390 /* Nonzero if this chip is an XScale. */
391 int arm_arch_xscale = 0;
393 /* Nonzero if tuning for XScale */
394 int arm_tune_xscale = 0;
396 /* Nonzero if this chip is an ARM6 or an ARM7. */
397 int arm_is_6_or_7 = 0;
399 /* Nonzero if generating Thumb instructions. */
402 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
403 must report the mode of the memory reference from PRINT_OPERAND to
404 PRINT_OPERAND_ADDRESS. */
405 enum machine_mode output_memory_reference_mode;
407 /* The register number to be used for the PIC offset register. */
408 const char * arm_pic_register_string = NULL;
409 int arm_pic_register = INVALID_REGNUM;
411 /* Set to 1 when a return insn is output, this means that the epilogue
413 int return_used_this_function;
415 /* Set to 1 after arm_reorg has started. Reset to start at the start of
416 the next function. */
417 static int after_arm_reorg = 0;
419 /* The maximum number of insns to be used when loading a constant. */
420 static int arm_constant_limit = 3;
422 /* For an explanation of these variables, see final_prescan_insn below. */
424 enum arm_cond_code arm_current_cc;
426 int arm_target_label;
428 /* The condition codes of the ARM, and the inverse function. */
429 static const char * const arm_condition_codes[] =
431 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
432 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
435 #define streq(string1, string2) (strcmp (string1, string2) == 0)
437 /* Initialization code. */
441 const char *const name;
442 enum processor_type core;
444 const unsigned long flags;
445 bool (* rtx_costs) (rtx, int, int, int *);
448 /* Not all of these give usefully different compilation alternatives,
449 but there is no simple way of generalizing them. */
450 static const struct processors all_cores[] =
453 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
454 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
455 #include "arm-cores.def"
457 {NULL, arm_none, NULL, 0, NULL}
460 static const struct processors all_architectures[] =
462 /* ARM Architectures */
463 /* We don't specify rtx_costs here as it will be figured out
466 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
467 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
468 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
469 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
470 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
471 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
472 implementations that support it, so we will leave it out for now. */
473 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
474 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
475 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
476 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
477 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
478 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
479 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
480 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
481 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
482 {NULL, arm_none, NULL, 0 , NULL}
485 /* This is a magic structure. The 'string' field is magically filled in
486 with a pointer to the value specified by the user on the command line
487 assuming that the user has specified such a value. */
489 struct arm_cpu_select arm_select[] =
491 /* string name processors */
492 { NULL, "-mcpu=", all_cores },
493 { NULL, "-march=", all_architectures },
494 { NULL, "-mtune=", all_cores }
498 /* The name of the proprocessor macro to define for this architecture. */
500 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
509 /* Available values for for -mfpu=. */
511 static const struct fpu_desc all_fpus[] =
513 {"fpa", FPUTYPE_FPA},
514 {"fpe2", FPUTYPE_FPA_EMU2},
515 {"fpe3", FPUTYPE_FPA_EMU2},
516 {"maverick", FPUTYPE_MAVERICK},
521 /* Floating point models used by the different hardware.
522 See fputype in arm.h. */
524 static const enum fputype fp_model_for_fpu[] =
526 /* No FP hardware. */
527 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
528 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
529 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
530 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
531 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
532 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
539 enum float_abi_type abi_type;
543 /* Available values for -mfloat-abi=. */
545 static const struct float_abi all_float_abis[] =
547 {"soft", ARM_FLOAT_ABI_SOFT},
548 {"softfp", ARM_FLOAT_ABI_SOFTFP},
549 {"hard", ARM_FLOAT_ABI_HARD}
556 enum arm_abi_type abi_type;
560 /* Available values for -mabi=. */
562 static const struct abi_name arm_all_abis[] =
564 {"apcs-gnu", ARM_ABI_APCS},
565 {"atpcs", ARM_ABI_ATPCS},
566 {"aapcs", ARM_ABI_AAPCS},
567 {"iwmmxt", ARM_ABI_IWMMXT}
570 /* Return the number of bits set in VALUE. */
572 bit_count (unsigned long value)
574 unsigned long count = 0;
579 value &= value - 1; /* Clear the least-significant set bit. */
585 /* Fix up any incompatible options that the user has specified.
586 This has now turned into a maze. */
588 arm_override_options (void)
592 /* Set up the flags based on the cpu/architecture selected by the user. */
593 for (i = ARRAY_SIZE (arm_select); i--;)
595 struct arm_cpu_select * ptr = arm_select + i;
597 if (ptr->string != NULL && ptr->string[0] != '\0')
599 const struct processors * sel;
601 for (sel = ptr->processors; sel->name != NULL; sel++)
602 if (streq (ptr->string, sel->name))
604 /* Set the architecture define. */
606 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
608 /* Determine the processor core for which we should
609 tune code-generation. */
610 if (/* -mcpu= is a sensible default. */
612 /* If -march= is used, and -mcpu= has not been used,
613 assume that we should tune for a representative
614 CPU from that architecture. */
616 /* -mtune= overrides -mcpu= and -march=. */
618 arm_tune = (enum processor_type) (sel - ptr->processors);
622 /* If we have been given an architecture and a processor
623 make sure that they are compatible. We only generate
624 a warning though, and we prefer the CPU over the
626 if (insn_flags != 0 && (insn_flags ^ sel->flags))
627 warning ("switch -mcpu=%s conflicts with -march= switch",
630 insn_flags = sel->flags;
636 if (sel->name == NULL)
637 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
641 /* If the user did not specify a processor, choose one for them. */
644 const struct processors * sel;
646 enum processor_type cpu;
648 cpu = TARGET_CPU_DEFAULT;
651 #ifdef SUBTARGET_CPU_DEFAULT
652 /* Use the subtarget default CPU if none was specified by
654 cpu = SUBTARGET_CPU_DEFAULT;
656 /* Default to ARM6. */
660 sel = &all_cores[cpu];
662 insn_flags = sel->flags;
664 /* Now check to see if the user has specified some command line
665 switch that require certain abilities from the cpu. */
668 if (TARGET_INTERWORK || TARGET_THUMB)
670 sought |= (FL_THUMB | FL_MODE32);
672 /* There are no ARM processors that support both APCS-26 and
673 interworking. Therefore we force FL_MODE26 to be removed
674 from insn_flags here (if it was set), so that the search
675 below will always be able to find a compatible processor. */
676 insn_flags &= ~FL_MODE26;
679 if (sought != 0 && ((sought & insn_flags) != sought))
681 /* Try to locate a CPU type that supports all of the abilities
682 of the default CPU, plus the extra abilities requested by
684 for (sel = all_cores; sel->name != NULL; sel++)
685 if ((sel->flags & sought) == (sought | insn_flags))
688 if (sel->name == NULL)
690 unsigned current_bit_count = 0;
691 const struct processors * best_fit = NULL;
693 /* Ideally we would like to issue an error message here
694 saying that it was not possible to find a CPU compatible
695 with the default CPU, but which also supports the command
696 line options specified by the programmer, and so they
697 ought to use the -mcpu=<name> command line option to
698 override the default CPU type.
700 If we cannot find a cpu that has both the
701 characteristics of the default cpu and the given
702 command line options we scan the array again looking
704 for (sel = all_cores; sel->name != NULL; sel++)
705 if ((sel->flags & sought) == sought)
709 count = bit_count (sel->flags & insn_flags);
711 if (count >= current_bit_count)
714 current_bit_count = count;
718 if (best_fit == NULL)
724 insn_flags = sel->flags;
726 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
727 if (arm_tune == arm_none)
728 arm_tune = (enum processor_type) (sel - all_cores);
731 /* The processor for which we should tune should now have been
733 if (arm_tune == arm_none)
736 tune_flags = all_cores[(int)arm_tune].flags;
737 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
739 /* Make sure that the processor choice does not conflict with any of the
740 other command line choices. */
741 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
743 warning ("target CPU does not support interworking" );
744 target_flags &= ~ARM_FLAG_INTERWORK;
747 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
749 warning ("target CPU does not support THUMB instructions");
750 target_flags &= ~ARM_FLAG_THUMB;
753 if (TARGET_APCS_FRAME && TARGET_THUMB)
755 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
756 target_flags &= ~ARM_FLAG_APCS_FRAME;
759 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
760 from here where no function is being compiled currently. */
761 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
763 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
765 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
766 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
768 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
769 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
771 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
773 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
774 target_flags |= ARM_FLAG_APCS_FRAME;
777 if (TARGET_POKE_FUNCTION_NAME)
778 target_flags |= ARM_FLAG_APCS_FRAME;
780 if (TARGET_APCS_REENT && flag_pic)
781 error ("-fpic and -mapcs-reent are incompatible");
783 if (TARGET_APCS_REENT)
784 warning ("APCS reentrant code not supported. Ignored");
786 /* If this target is normally configured to use APCS frames, warn if they
787 are turned off and debugging is turned on. */
789 && write_symbols != NO_DEBUG
790 && !TARGET_APCS_FRAME
791 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
792 warning ("-g with -mno-apcs-frame may not give sensible debugging");
794 /* If stack checking is disabled, we can use r10 as the PIC register,
795 which keeps r9 available. */
797 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
799 if (TARGET_APCS_FLOAT)
800 warning ("passing floating point arguments in fp regs not yet supported");
802 /* Initialize boolean versions of the flags, for use in the arm.md file. */
803 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
804 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
805 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
806 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
807 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
808 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
809 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
811 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
812 arm_is_strong = (tune_flags & FL_STRONG) != 0;
813 thumb_code = (TARGET_ARM == 0);
814 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
815 && !(tune_flags & FL_ARCH4))) != 0;
816 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
817 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
821 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
823 if (streq (arm_all_abis[i].name, target_abi_name))
825 arm_abi = arm_all_abis[i].abi_type;
829 if (i == ARRAY_SIZE (arm_all_abis))
830 error ("invalid ABI option: -mabi=%s", target_abi_name);
833 arm_abi = ARM_DEFAULT_ABI;
835 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
836 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
838 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
839 error ("iwmmxt abi requires an iwmmxt capable cpu");
841 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
842 if (target_fpu_name == NULL && target_fpe_name != NULL)
844 if (streq (target_fpe_name, "2"))
845 target_fpu_name = "fpe2";
846 else if (streq (target_fpe_name, "3"))
847 target_fpu_name = "fpe3";
849 error ("invalid floating point emulation option: -mfpe=%s",
852 if (target_fpu_name != NULL)
854 /* The user specified a FPU. */
855 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
857 if (streq (all_fpus[i].name, target_fpu_name))
859 arm_fpu_arch = all_fpus[i].fpu;
860 arm_fpu_tune = arm_fpu_arch;
861 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
865 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
866 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
870 #ifdef FPUTYPE_DEFAULT
871 /* Use the default if it is specified for this platform. */
872 arm_fpu_arch = FPUTYPE_DEFAULT;
873 arm_fpu_tune = FPUTYPE_DEFAULT;
875 /* Pick one based on CPU type. */
876 /* ??? Some targets assume FPA is the default.
877 if ((insn_flags & FL_VFP) != 0)
878 arm_fpu_arch = FPUTYPE_VFP;
882 arm_fpu_arch = FPUTYPE_MAVERICK;
884 arm_fpu_arch = FPUTYPE_FPA_EMU2;
886 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
887 arm_fpu_tune = FPUTYPE_FPA;
889 arm_fpu_tune = arm_fpu_arch;
890 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
891 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
895 if (target_float_abi_name != NULL)
897 /* The user specified a FP ABI. */
898 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
900 if (streq (all_float_abis[i].name, target_float_abi_name))
902 arm_float_abi = all_float_abis[i].abi_type;
906 if (i == ARRAY_SIZE (all_float_abis))
907 error ("invalid floating point abi: -mfloat-abi=%s",
908 target_float_abi_name);
912 /* Use soft-float target flag. */
913 if (target_flags & ARM_FLAG_SOFT_FLOAT)
914 arm_float_abi = ARM_FLOAT_ABI_SOFT;
916 arm_float_abi = ARM_FLOAT_ABI_HARD;
919 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
920 sorry ("-mfloat-abi=softfp");
921 /* If soft-float is specified then don't use FPU. */
922 if (TARGET_SOFT_FLOAT)
923 arm_fpu_arch = FPUTYPE_NONE;
925 /* For arm2/3 there is no need to do any scheduling if there is only
926 a floating point emulator, or we are doing software floating-point. */
927 if ((TARGET_SOFT_FLOAT
928 || arm_fpu_tune == FPUTYPE_FPA_EMU2
929 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
930 && (tune_flags & FL_MODE32) == 0)
931 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
933 /* Override the default structure alignment for AAPCS ABI. */
934 if (arm_abi == ARM_ABI_AAPCS)
935 arm_structure_size_boundary = 8;
937 if (structure_size_string != NULL)
939 int size = strtol (structure_size_string, NULL, 0);
941 if (size == 8 || size == 32
942 || (ARM_DOUBLEWORD_ALIGN && size == 64))
943 arm_structure_size_boundary = size;
945 warning ("structure size boundary can only be set to %s",
946 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
949 if (arm_pic_register_string != NULL)
951 int pic_register = decode_reg_name (arm_pic_register_string);
954 warning ("-mpic-register= is useless without -fpic");
956 /* Prevent the user from choosing an obviously stupid PIC register. */
957 else if (pic_register < 0 || call_used_regs[pic_register]
958 || pic_register == HARD_FRAME_POINTER_REGNUM
959 || pic_register == STACK_POINTER_REGNUM
960 || pic_register >= PC_REGNUM)
961 error ("unable to use '%s' for PIC register", arm_pic_register_string);
963 arm_pic_register = pic_register;
966 if (TARGET_THUMB && flag_schedule_insns)
968 /* Don't warn since it's on by default in -O2. */
969 flag_schedule_insns = 0;
974 /* There's some dispute as to whether this should be 1 or 2. However,
975 experiments seem to show that in pathological cases a setting of
976 1 degrades less severely than a setting of 2. This could change if
977 other parts of the compiler change their behavior. */
978 arm_constant_limit = 1;
980 /* If optimizing for size, bump the number of instructions that we
981 are prepared to conditionally execute (even on a StrongARM). */
982 max_insns_skipped = 6;
986 /* For processors with load scheduling, it never costs more than
987 2 cycles to load a constant, and the load scheduler may well
989 if (tune_flags & FL_LDSCHED)
990 arm_constant_limit = 1;
992 /* On XScale the longer latency of a load makes it more difficult
993 to achieve a good schedule, so it's faster to synthesize
994 constants that can be done in two insns. */
996 arm_constant_limit = 2;
998 /* StrongARM has early execution of branches, so a sequence
999 that is worth skipping is shorter. */
1001 max_insns_skipped = 3;
1004 /* Register global variables with the garbage collector. */
1005 arm_add_gc_roots ();
1009 arm_add_gc_roots (void)
1011 gcc_obstack_init(&minipool_obstack);
1012 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1015 /* A table of known ARM exception types.
1016 For use with the interrupt function attribute. */
1020 const char *const arg;
1021 const unsigned long return_value;
1025 static const isr_attribute_arg isr_attribute_args [] =
1027 { "IRQ", ARM_FT_ISR },
1028 { "irq", ARM_FT_ISR },
1029 { "FIQ", ARM_FT_FIQ },
1030 { "fiq", ARM_FT_FIQ },
1031 { "ABORT", ARM_FT_ISR },
1032 { "abort", ARM_FT_ISR },
1033 { "ABORT", ARM_FT_ISR },
1034 { "abort", ARM_FT_ISR },
1035 { "UNDEF", ARM_FT_EXCEPTION },
1036 { "undef", ARM_FT_EXCEPTION },
1037 { "SWI", ARM_FT_EXCEPTION },
1038 { "swi", ARM_FT_EXCEPTION },
1039 { NULL, ARM_FT_NORMAL }
1042 /* Returns the (interrupt) function type of the current
1043 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1045 static unsigned long
1046 arm_isr_value (tree argument)
1048 const isr_attribute_arg * ptr;
1051 /* No argument - default to IRQ. */
1052 if (argument == NULL_TREE)
1055 /* Get the value of the argument. */
1056 if (TREE_VALUE (argument) == NULL_TREE
1057 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1058 return ARM_FT_UNKNOWN;
1060 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1062 /* Check it against the list of known arguments. */
1063 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1064 if (streq (arg, ptr->arg))
1065 return ptr->return_value;
1067 /* An unrecognized interrupt type. */
1068 return ARM_FT_UNKNOWN;
1071 /* Computes the type of the current function. */
1073 static unsigned long
1074 arm_compute_func_type (void)
1076 unsigned long type = ARM_FT_UNKNOWN;
1080 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1083 /* Decide if the current function is volatile. Such functions
1084 never return, and many memory cycles can be saved by not storing
1085 register values that will never be needed again. This optimization
1086 was added to speed up context switching in a kernel application. */
1088 && current_function_nothrow
1089 && TREE_THIS_VOLATILE (current_function_decl))
1090 type |= ARM_FT_VOLATILE;
1092 if (cfun->static_chain_decl != NULL)
1093 type |= ARM_FT_NESTED;
1095 attr = DECL_ATTRIBUTES (current_function_decl);
1097 a = lookup_attribute ("naked", attr);
1099 type |= ARM_FT_NAKED;
1101 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1102 type |= ARM_FT_EXCEPTION_HANDLER;
1105 a = lookup_attribute ("isr", attr);
1107 a = lookup_attribute ("interrupt", attr);
1110 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1112 type |= arm_isr_value (TREE_VALUE (a));
1118 /* Returns the type of the current function. */
1121 arm_current_func_type (void)
1123 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1124 cfun->machine->func_type = arm_compute_func_type ();
1126 return cfun->machine->func_type;
1129 /* Return 1 if it is possible to return using a single instruction.
1130 If SIBLING is non-null, this is a test for a return before a sibling
1131 call. SIBLING is the call insn, so we can examine its register usage. */
1134 use_return_insn (int iscond, rtx sibling)
1137 unsigned int func_type;
1138 unsigned long saved_int_regs;
1139 unsigned HOST_WIDE_INT stack_adjust;
1140 arm_stack_offsets *offsets;
1142 /* Never use a return instruction before reload has run. */
1143 if (!reload_completed)
1146 func_type = arm_current_func_type ();
1148 /* Naked functions and volatile functions need special
1150 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1153 /* So do interrupt functions that use the frame pointer. */
1154 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1157 offsets = arm_get_frame_offsets ();
1158 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1160 /* As do variadic functions. */
1161 if (current_function_pretend_args_size
1162 || cfun->machine->uses_anonymous_args
1163 /* Or if the function calls __builtin_eh_return () */
1164 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1165 /* Or if the function calls alloca */
1166 || current_function_calls_alloca
1167 /* Or if there is a stack adjustment. However, if the stack pointer
1168 is saved on the stack, we can use a pre-incrementing stack load. */
1169 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1172 saved_int_regs = arm_compute_save_reg_mask ();
1174 /* Unfortunately, the insn
1176 ldmib sp, {..., sp, ...}
1178 triggers a bug on most SA-110 based devices, such that the stack
1179 pointer won't be correctly restored if the instruction takes a
1180 page fault. We work around this problem by popping r3 along with
1181 the other registers, since that is never slower than executing
1182 another instruction.
1184 We test for !arm_arch5 here, because code for any architecture
1185 less than this could potentially be run on one of the buggy
1187 if (stack_adjust == 4 && !arm_arch5)
1189 /* Validate that r3 is a call-clobbered register (always true in
1190 the default abi) ... */
1191 if (!call_used_regs[3])
1194 /* ... that it isn't being used for a return value (always true
1195 until we implement return-in-regs), or for a tail-call
1199 if (GET_CODE (sibling) != CALL_INSN)
1202 if (find_regno_fusage (sibling, USE, 3))
1206 /* ... and that there are no call-saved registers in r0-r2
1207 (always true in the default ABI). */
1208 if (saved_int_regs & 0x7)
1212 /* Can't be done if interworking with Thumb, and any registers have been
1214 if (TARGET_INTERWORK && saved_int_regs != 0)
1217 /* On StrongARM, conditional returns are expensive if they aren't
1218 taken and multiple registers have been stacked. */
1219 if (iscond && arm_is_strong)
1221 /* Conditional return when just the LR is stored is a simple
1222 conditional-load instruction, that's not expensive. */
1223 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1226 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1230 /* If there are saved registers but the LR isn't saved, then we need
1231 two instructions for the return. */
1232 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1235 /* Can't be done if any of the FPA regs are pushed,
1236 since this also requires an insn. */
1237 if (TARGET_HARD_FLOAT && TARGET_FPA)
1238 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1239 if (regs_ever_live[regno] && !call_used_regs[regno])
1242 /* Likewise VFP regs. */
1243 if (TARGET_HARD_FLOAT && TARGET_VFP)
1244 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1245 if (regs_ever_live[regno] && !call_used_regs[regno])
1248 if (TARGET_REALLY_IWMMXT)
1249 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1250 if (regs_ever_live[regno] && ! call_used_regs [regno])
1256 /* Return TRUE if int I is a valid immediate ARM constant. */
1259 const_ok_for_arm (HOST_WIDE_INT i)
1261 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1263 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1264 be all zero, or all one. */
1265 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1266 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1267 != ((~(unsigned HOST_WIDE_INT) 0)
1268 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1271 /* Fast return for 0 and powers of 2 */
1272 if ((i & (i - 1)) == 0)
1277 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1280 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1281 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1283 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1288 /* Return true if I is a valid constant for the operation CODE. */
1290 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1292 if (const_ok_for_arm (i))
1298 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1300 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1306 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1313 /* Emit a sequence of insns to handle a large constant.
1314 CODE is the code of the operation required, it can be any of SET, PLUS,
1315 IOR, AND, XOR, MINUS;
1316 MODE is the mode in which the operation is being performed;
1317 VAL is the integer to operate on;
1318 SOURCE is the other operand (a register, or a null-pointer for SET);
1319 SUBTARGETS means it is safe to create scratch registers if that will
1320 either produce a simpler sequence, or we will want to cse the values.
1321 Return value is the number of insns emitted. */
1324 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1325 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1329 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1330 cond = COND_EXEC_TEST (PATTERN (insn));
1334 if (subtargets || code == SET
1335 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1336 && REGNO (target) != REGNO (source)))
1338 /* After arm_reorg has been called, we can't fix up expensive
1339 constants by pushing them into memory so we must synthesize
1340 them in-line, regardless of the cost. This is only likely to
1341 be more costly on chips that have load delay slots and we are
1342 compiling without running the scheduler (so no splitting
1343 occurred before the final instruction emission).
1345 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1347 if (!after_arm_reorg
1349 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1351 > arm_constant_limit + (code != SET)))
1355 /* Currently SET is the only monadic value for CODE, all
1356 the rest are diadic. */
1357 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1362 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1364 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1365 /* For MINUS, the value is subtracted from, since we never
1366 have subtraction of a constant. */
1368 emit_insn (gen_rtx_SET (VOIDmode, target,
1369 gen_rtx_MINUS (mode, temp, source)));
1371 emit_insn (gen_rtx_SET (VOIDmode, target,
1372 gen_rtx_fmt_ee (code, mode, source, temp)));
1378 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1383 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1385 HOST_WIDE_INT temp1;
1393 if (remainder & (3 << (i - 2)))
1398 temp1 = remainder & ((0x0ff << end)
1399 | ((i < end) ? (0xff >> (32 - end)) : 0));
1400 remainder &= ~temp1;
1405 } while (remainder);
1409 /* Emit an instruction with the indicated PATTERN. If COND is
1410 non-NULL, conditionalize the execution of the instruction on COND
1414 emit_constant_insn (rtx cond, rtx pattern)
1417 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1418 emit_insn (pattern);
1421 /* As above, but extra parameter GENERATE which, if clear, suppresses
1425 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1426 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1431 int can_negate_initial = 0;
1434 int num_bits_set = 0;
1435 int set_sign_bit_copies = 0;
1436 int clear_sign_bit_copies = 0;
1437 int clear_zero_bit_copies = 0;
1438 int set_zero_bit_copies = 0;
1440 unsigned HOST_WIDE_INT temp1, temp2;
1441 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1443 /* Find out which operations are safe for a given CODE. Also do a quick
1444 check for degenerate cases; these can occur when DImode operations
1456 can_negate_initial = 1;
1460 if (remainder == 0xffffffff)
1463 emit_constant_insn (cond,
1464 gen_rtx_SET (VOIDmode, target,
1465 GEN_INT (ARM_SIGN_EXTEND (val))));
1470 if (reload_completed && rtx_equal_p (target, source))
1473 emit_constant_insn (cond,
1474 gen_rtx_SET (VOIDmode, target, source));
1483 emit_constant_insn (cond,
1484 gen_rtx_SET (VOIDmode, target, const0_rtx));
1487 if (remainder == 0xffffffff)
1489 if (reload_completed && rtx_equal_p (target, source))
1492 emit_constant_insn (cond,
1493 gen_rtx_SET (VOIDmode, target, source));
1502 if (reload_completed && rtx_equal_p (target, source))
1505 emit_constant_insn (cond,
1506 gen_rtx_SET (VOIDmode, target, source));
1509 if (remainder == 0xffffffff)
1512 emit_constant_insn (cond,
1513 gen_rtx_SET (VOIDmode, target,
1514 gen_rtx_NOT (mode, source)));
1518 /* We don't know how to handle this yet below. */
1522 /* We treat MINUS as (val - source), since (source - val) is always
1523 passed as (source + (-val)). */
1527 emit_constant_insn (cond,
1528 gen_rtx_SET (VOIDmode, target,
1529 gen_rtx_NEG (mode, source)));
1532 if (const_ok_for_arm (val))
1535 emit_constant_insn (cond,
1536 gen_rtx_SET (VOIDmode, target,
1537 gen_rtx_MINUS (mode, GEN_INT (val),
1549 /* If we can do it in one insn get out quickly. */
1550 if (const_ok_for_arm (val)
1551 || (can_negate_initial && const_ok_for_arm (-val))
1552 || (can_invert && const_ok_for_arm (~val)))
1555 emit_constant_insn (cond,
1556 gen_rtx_SET (VOIDmode, target,
1558 ? gen_rtx_fmt_ee (code, mode, source,
1564 /* Calculate a few attributes that may be useful for specific
1566 for (i = 31; i >= 0; i--)
1568 if ((remainder & (1 << i)) == 0)
1569 clear_sign_bit_copies++;
1574 for (i = 31; i >= 0; i--)
1576 if ((remainder & (1 << i)) != 0)
1577 set_sign_bit_copies++;
1582 for (i = 0; i <= 31; i++)
1584 if ((remainder & (1 << i)) == 0)
1585 clear_zero_bit_copies++;
1590 for (i = 0; i <= 31; i++)
1592 if ((remainder & (1 << i)) != 0)
1593 set_zero_bit_copies++;
1601 /* See if we can do this by sign_extending a constant that is known
1602 to be negative. This is a good, way of doing it, since the shift
1603 may well merge into a subsequent insn. */
1604 if (set_sign_bit_copies > 1)
1606 if (const_ok_for_arm
1607 (temp1 = ARM_SIGN_EXTEND (remainder
1608 << (set_sign_bit_copies - 1))))
1612 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1613 emit_constant_insn (cond,
1614 gen_rtx_SET (VOIDmode, new_src,
1616 emit_constant_insn (cond,
1617 gen_ashrsi3 (target, new_src,
1618 GEN_INT (set_sign_bit_copies - 1)));
1622 /* For an inverted constant, we will need to set the low bits,
1623 these will be shifted out of harm's way. */
1624 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1625 if (const_ok_for_arm (~temp1))
1629 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1630 emit_constant_insn (cond,
1631 gen_rtx_SET (VOIDmode, new_src,
1633 emit_constant_insn (cond,
1634 gen_ashrsi3 (target, new_src,
1635 GEN_INT (set_sign_bit_copies - 1)));
1641 /* See if we can generate this by setting the bottom (or the top)
1642 16 bits, and then shifting these into the other half of the
1643 word. We only look for the simplest cases, to do more would cost
1644 too much. Be careful, however, not to generate this when the
1645 alternative would take fewer insns. */
1646 if (val & 0xffff0000)
1648 temp1 = remainder & 0xffff0000;
1649 temp2 = remainder & 0x0000ffff;
1651 /* Overlaps outside this range are best done using other methods. */
1652 for (i = 9; i < 24; i++)
1654 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1655 && !const_ok_for_arm (temp2))
1657 rtx new_src = (subtargets
1658 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1660 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1661 source, subtargets, generate);
1669 gen_rtx_ASHIFT (mode, source,
1676 /* Don't duplicate cases already considered. */
1677 for (i = 17; i < 24; i++)
1679 if (((temp1 | (temp1 >> i)) == remainder)
1680 && !const_ok_for_arm (temp1))
1682 rtx new_src = (subtargets
1683 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1685 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1686 source, subtargets, generate);
1691 gen_rtx_SET (VOIDmode, target,
1694 gen_rtx_LSHIFTRT (mode, source,
1705 /* If we have IOR or XOR, and the constant can be loaded in a
1706 single instruction, and we can find a temporary to put it in,
1707 then this can be done in two instructions instead of 3-4. */
1709 /* TARGET can't be NULL if SUBTARGETS is 0 */
1710 || (reload_completed && !reg_mentioned_p (target, source)))
1712 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1716 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1718 emit_constant_insn (cond,
1719 gen_rtx_SET (VOIDmode, sub,
1721 emit_constant_insn (cond,
1722 gen_rtx_SET (VOIDmode, target,
1723 gen_rtx_fmt_ee (code, mode,
1733 if (set_sign_bit_copies > 8
1734 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1738 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1739 rtx shift = GEN_INT (set_sign_bit_copies);
1743 gen_rtx_SET (VOIDmode, sub,
1745 gen_rtx_ASHIFT (mode,
1750 gen_rtx_SET (VOIDmode, target,
1752 gen_rtx_LSHIFTRT (mode, sub,
1758 if (set_zero_bit_copies > 8
1759 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1763 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1764 rtx shift = GEN_INT (set_zero_bit_copies);
1768 gen_rtx_SET (VOIDmode, sub,
1770 gen_rtx_LSHIFTRT (mode,
1775 gen_rtx_SET (VOIDmode, target,
1777 gen_rtx_ASHIFT (mode, sub,
1783 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1787 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1788 emit_constant_insn (cond,
1789 gen_rtx_SET (VOIDmode, sub,
1790 gen_rtx_NOT (mode, source)));
1793 sub = gen_reg_rtx (mode);
1794 emit_constant_insn (cond,
1795 gen_rtx_SET (VOIDmode, sub,
1796 gen_rtx_AND (mode, source,
1798 emit_constant_insn (cond,
1799 gen_rtx_SET (VOIDmode, target,
1800 gen_rtx_NOT (mode, sub)));
1807 /* See if two shifts will do 2 or more insn's worth of work. */
1808 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1810 HOST_WIDE_INT shift_mask = ((0xffffffff
1811 << (32 - clear_sign_bit_copies))
1814 if ((remainder | shift_mask) != 0xffffffff)
1818 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1819 insns = arm_gen_constant (AND, mode, cond,
1820 remainder | shift_mask,
1821 new_src, source, subtargets, 1);
1826 rtx targ = subtargets ? NULL_RTX : target;
1827 insns = arm_gen_constant (AND, mode, cond,
1828 remainder | shift_mask,
1829 targ, source, subtargets, 0);
1835 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1836 rtx shift = GEN_INT (clear_sign_bit_copies);
1838 emit_insn (gen_ashlsi3 (new_src, source, shift));
1839 emit_insn (gen_lshrsi3 (target, new_src, shift));
1845 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1847 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1849 if ((remainder | shift_mask) != 0xffffffff)
1853 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1855 insns = arm_gen_constant (AND, mode, cond,
1856 remainder | shift_mask,
1857 new_src, source, subtargets, 1);
1862 rtx targ = subtargets ? NULL_RTX : target;
1864 insns = arm_gen_constant (AND, mode, cond,
1865 remainder | shift_mask,
1866 targ, source, subtargets, 0);
1872 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1873 rtx shift = GEN_INT (clear_zero_bit_copies);
1875 emit_insn (gen_lshrsi3 (new_src, source, shift));
1876 emit_insn (gen_ashlsi3 (target, new_src, shift));
1888 for (i = 0; i < 32; i++)
1889 if (remainder & (1 << i))
1892 if (code == AND || (can_invert && num_bits_set > 16))
1893 remainder = (~remainder) & 0xffffffff;
1894 else if (code == PLUS && num_bits_set > 16)
1895 remainder = (-remainder) & 0xffffffff;
1902 /* Now try and find a way of doing the job in either two or three
1904 We start by looking for the largest block of zeros that are aligned on
1905 a 2-bit boundary, we then fill up the temps, wrapping around to the
1906 top of the word when we drop off the bottom.
1907 In the worst case this code should produce no more than four insns. */
1910 int best_consecutive_zeros = 0;
1912 for (i = 0; i < 32; i += 2)
1914 int consecutive_zeros = 0;
1916 if (!(remainder & (3 << i)))
1918 while ((i < 32) && !(remainder & (3 << i)))
1920 consecutive_zeros += 2;
1923 if (consecutive_zeros > best_consecutive_zeros)
1925 best_consecutive_zeros = consecutive_zeros;
1926 best_start = i - consecutive_zeros;
1932 /* So long as it won't require any more insns to do so, it's
1933 desirable to emit a small constant (in bits 0...9) in the last
1934 insn. This way there is more chance that it can be combined with
1935 a later addressing insn to form a pre-indexed load or store
1936 operation. Consider:
1938 *((volatile int *)0xe0000100) = 1;
1939 *((volatile int *)0xe0000110) = 2;
1941 We want this to wind up as:
1945 str rB, [rA, #0x100]
1947 str rB, [rA, #0x110]
1949 rather than having to synthesize both large constants from scratch.
1951 Therefore, we calculate how many insns would be required to emit
1952 the constant starting from `best_start', and also starting from
1953 zero (ie with bit 31 first to be output). If `best_start' doesn't
1954 yield a shorter sequence, we may as well use zero. */
1956 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1957 && (count_insns_for_constant (remainder, 0) <=
1958 count_insns_for_constant (remainder, best_start)))
1961 /* Now start emitting the insns. */
1969 if (remainder & (3 << (i - 2)))
1974 temp1 = remainder & ((0x0ff << end)
1975 | ((i < end) ? (0xff >> (32 - end)) : 0));
1976 remainder &= ~temp1;
1980 rtx new_src, temp1_rtx;
1982 if (code == SET || code == MINUS)
1984 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1985 if (can_invert && code != MINUS)
1990 if (remainder && subtargets)
1991 new_src = gen_reg_rtx (mode);
1996 else if (can_negate)
2000 temp1 = trunc_int_for_mode (temp1, mode);
2001 temp1_rtx = GEN_INT (temp1);
2005 else if (code == MINUS)
2006 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2008 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2010 emit_constant_insn (cond,
2011 gen_rtx_SET (VOIDmode, new_src,
2021 else if (code == MINUS)
2035 /* Canonicalize a comparison so that we are more likely to recognize it.
2036 This can be done for a few constant compares, where we can make the
2037 immediate value easier to load. */
2040 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2042 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2052 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2053 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2055 *op1 = GEN_INT (i + 1);
2056 return code == GT ? GE : LT;
2062 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2063 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2065 *op1 = GEN_INT (i - 1);
2066 return code == GE ? GT : LE;
2072 if (i != ~((unsigned HOST_WIDE_INT) 0)
2073 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2075 *op1 = GEN_INT (i + 1);
2076 return code == GTU ? GEU : LTU;
2083 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2085 *op1 = GEN_INT (i - 1);
2086 return code == GEU ? GTU : LEU;
2098 /* Define how to find the value returned by a function. */
2100 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2102 enum machine_mode mode;
2103 int unsignedp ATTRIBUTE_UNUSED;
2104 rtx r ATTRIBUTE_UNUSED;
2107 mode = TYPE_MODE (type);
2108 /* Promote integer types. */
2109 if (INTEGRAL_TYPE_P (type))
2110 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2111 return LIBCALL_VALUE(mode);
2115 /* Decide whether a type should be returned in memory (true)
2116 or in a register (false). This is called by the macro
2117 RETURN_IN_MEMORY. */
2119 arm_return_in_memory (tree type)
2123 if (!AGGREGATE_TYPE_P (type))
2124 /* All simple types are returned in registers. */
2127 size = int_size_in_bytes (type);
2129 if (arm_abi != ARM_ABI_APCS)
2131 /* ATPCS and later return aggregate types in memory only if they are
2132 larger than a word (or are variable size). */
2133 return (size < 0 || size > UNITS_PER_WORD);
2136 /* For the arm-wince targets we choose to be compatible with Microsoft's
2137 ARM and Thumb compilers, which always return aggregates in memory. */
2139 /* All structures/unions bigger than one word are returned in memory.
2140 Also catch the case where int_size_in_bytes returns -1. In this case
2141 the aggregate is either huge or of variable size, and in either case
2142 we will want to return it via memory and not in a register. */
2143 if (size < 0 || size > UNITS_PER_WORD)
2146 if (TREE_CODE (type) == RECORD_TYPE)
2150 /* For a struct the APCS says that we only return in a register
2151 if the type is 'integer like' and every addressable element
2152 has an offset of zero. For practical purposes this means
2153 that the structure can have at most one non bit-field element
2154 and that this element must be the first one in the structure. */
2156 /* Find the first field, ignoring non FIELD_DECL things which will
2157 have been created by C++. */
2158 for (field = TYPE_FIELDS (type);
2159 field && TREE_CODE (field) != FIELD_DECL;
2160 field = TREE_CHAIN (field))
2164 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2166 /* Check that the first field is valid for returning in a register. */
2168 /* ... Floats are not allowed */
2169 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2172 /* ... Aggregates that are not themselves valid for returning in
2173 a register are not allowed. */
2174 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2177 /* Now check the remaining fields, if any. Only bitfields are allowed,
2178 since they are not addressable. */
2179 for (field = TREE_CHAIN (field);
2181 field = TREE_CHAIN (field))
2183 if (TREE_CODE (field) != FIELD_DECL)
2186 if (!DECL_BIT_FIELD_TYPE (field))
2193 if (TREE_CODE (type) == UNION_TYPE)
2197 /* Unions can be returned in registers if every element is
2198 integral, or can be returned in an integer register. */
2199 for (field = TYPE_FIELDS (type);
2201 field = TREE_CHAIN (field))
2203 if (TREE_CODE (field) != FIELD_DECL)
2206 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2209 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2215 #endif /* not ARM_WINCE */
2217 /* Return all other types in memory. */
2221 /* Indicate whether or not words of a double are in big-endian order. */
2224 arm_float_words_big_endian (void)
2226 if (TARGET_MAVERICK)
2229 /* For FPA, float words are always big-endian. For VFP, floats words
2230 follow the memory system mode. */
2238 return (TARGET_BIG_END ? 1 : 0);
2243 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2244 for a call to a function whose data type is FNTYPE.
2245 For a library call, FNTYPE is NULL. */
2247 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2248 rtx libname ATTRIBUTE_UNUSED,
2249 tree fndecl ATTRIBUTE_UNUSED)
2251 /* On the ARM, the offset starts at 0. */
2252 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2253 pcum->iwmmxt_nregs = 0;
2254 pcum->can_split = true;
2256 pcum->call_cookie = CALL_NORMAL;
2258 if (TARGET_LONG_CALLS)
2259 pcum->call_cookie = CALL_LONG;
2261 /* Check for long call/short call attributes. The attributes
2262 override any command line option. */
2265 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2266 pcum->call_cookie = CALL_SHORT;
2267 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2268 pcum->call_cookie = CALL_LONG;
2271 /* Varargs vectors are treated the same as long long.
2272 named_count avoids having to change the way arm handles 'named' */
2273 pcum->named_count = 0;
2276 if (TARGET_REALLY_IWMMXT && fntype)
2280 for (fn_arg = TYPE_ARG_TYPES (fntype);
2282 fn_arg = TREE_CHAIN (fn_arg))
2283 pcum->named_count += 1;
2285 if (! pcum->named_count)
2286 pcum->named_count = INT_MAX;
2291 /* Return true if mode/type need doubleword alignment. */
2293 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2295 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2296 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2300 /* Determine where to put an argument to a function.
2301 Value is zero to push the argument on the stack,
2302 or a hard register in which to store the argument.
2304 MODE is the argument's machine mode.
2305 TYPE is the data type of the argument (as a tree).
2306 This is null for libcalls where that information may
2308 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2309 the preceding args and about the function being called.
2310 NAMED is nonzero if this argument is a named parameter
2311 (otherwise it is an extra parameter matching an ellipsis). */
2314 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2315 tree type, int named)
2319 /* Varargs vectors are treated the same as long long.
2320 named_count avoids having to change the way arm handles 'named' */
2321 if (TARGET_IWMMXT_ABI
2322 && VECTOR_MODE_SUPPORTED_P (mode)
2323 && pcum->named_count > pcum->nargs + 1)
2325 if (pcum->iwmmxt_nregs <= 9)
2326 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2329 pcum->can_split = false;
2334 /* Put doubleword aligned quantities in even register pairs. */
2336 && ARM_DOUBLEWORD_ALIGN
2337 && arm_needs_doubleword_align (mode, type))
2340 if (mode == VOIDmode)
2341 /* Compute operand 2 of the call insn. */
2342 return GEN_INT (pcum->call_cookie);
2344 /* Only allow splitting an arg between regs and memory if all preceding
2345 args were allocated to regs. For args passed by reference we only count
2346 the reference pointer. */
2347 if (pcum->can_split)
2350 nregs = ARM_NUM_REGS2 (mode, type);
2352 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2355 return gen_rtx_REG (mode, pcum->nregs);
2358 /* Variable sized types are passed by reference. This is a GCC
2359 extension to the ARM ABI. */
2362 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2363 enum machine_mode mode ATTRIBUTE_UNUSED,
2364 tree type, int named ATTRIBUTE_UNUSED)
2366 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2369 /* Implement va_arg. */
2372 arm_va_arg (tree valist, tree type)
2376 /* Variable sized types are passed by reference. */
2377 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2379 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2380 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2383 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2384 if (align > PARM_BOUNDARY)
2389 /* Maintain 64-bit alignment of the valist pointer by
2390 constructing: valist = ((valist + (8 - 1)) & -8). */
2391 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2392 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2393 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2394 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2395 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2396 TREE_SIDE_EFFECTS (t) = 1;
2397 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2399 /* This is to stop the combine pass optimizing
2400 away the alignment adjustment. */
2401 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2404 return std_expand_builtin_va_arg (valist, type);
2407 /* Encode the current state of the #pragma [no_]long_calls. */
2410 OFF, /* No #pramgma [no_]long_calls is in effect. */
2411 LONG, /* #pragma long_calls is in effect. */
2412 SHORT /* #pragma no_long_calls is in effect. */
2415 static arm_pragma_enum arm_pragma_long_calls = OFF;
2418 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2420 arm_pragma_long_calls = LONG;
2424 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2426 arm_pragma_long_calls = SHORT;
2430 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2432 arm_pragma_long_calls = OFF;
2435 /* Table of machine attributes. */
2436 const struct attribute_spec arm_attribute_table[] =
2438 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2439 /* Function calls made to this symbol must be done indirectly, because
2440 it may lie outside of the 26 bit addressing range of a normal function
2442 { "long_call", 0, 0, false, true, true, NULL },
2443 /* Whereas these functions are always known to reside within the 26 bit
2444 addressing range. */
2445 { "short_call", 0, 0, false, true, true, NULL },
2446 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2447 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2448 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2449 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2451 /* ARM/PE has three new attributes:
2453 dllexport - for exporting a function/variable that will live in a dll
2454 dllimport - for importing a function/variable from a dll
2456 Microsoft allows multiple declspecs in one __declspec, separating
2457 them with spaces. We do NOT support this. Instead, use __declspec
2460 { "dllimport", 0, 0, true, false, false, NULL },
2461 { "dllexport", 0, 0, true, false, false, NULL },
2462 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2464 { NULL, 0, 0, false, false, false, NULL }
2467 /* Handle an attribute requiring a FUNCTION_DECL;
2468 arguments as in struct attribute_spec.handler. */
2470 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2471 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2473 if (TREE_CODE (*node) != FUNCTION_DECL)
2475 warning ("`%s' attribute only applies to functions",
2476 IDENTIFIER_POINTER (name));
2477 *no_add_attrs = true;
2483 /* Handle an "interrupt" or "isr" attribute;
2484 arguments as in struct attribute_spec.handler. */
2486 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2491 if (TREE_CODE (*node) != FUNCTION_DECL)
2493 warning ("`%s' attribute only applies to functions",
2494 IDENTIFIER_POINTER (name));
2495 *no_add_attrs = true;
2497 /* FIXME: the argument if any is checked for type attributes;
2498 should it be checked for decl ones? */
2502 if (TREE_CODE (*node) == FUNCTION_TYPE
2503 || TREE_CODE (*node) == METHOD_TYPE)
2505 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2507 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2508 *no_add_attrs = true;
2511 else if (TREE_CODE (*node) == POINTER_TYPE
2512 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2513 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2514 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2516 *node = build_type_copy (*node);
2517 TREE_TYPE (*node) = build_type_attribute_variant
2519 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2520 *no_add_attrs = true;
2524 /* Possibly pass this attribute on from the type to a decl. */
2525 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2526 | (int) ATTR_FLAG_FUNCTION_NEXT
2527 | (int) ATTR_FLAG_ARRAY_NEXT))
2529 *no_add_attrs = true;
2530 return tree_cons (name, args, NULL_TREE);
2534 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2542 /* Return 0 if the attributes for two types are incompatible, 1 if they
2543 are compatible, and 2 if they are nearly compatible (which causes a
2544 warning to be generated). */
2546 arm_comp_type_attributes (tree type1, tree type2)
2550 /* Check for mismatch of non-default calling convention. */
2551 if (TREE_CODE (type1) != FUNCTION_TYPE)
2554 /* Check for mismatched call attributes. */
2555 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2556 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2557 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2558 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2560 /* Only bother to check if an attribute is defined. */
2561 if (l1 | l2 | s1 | s2)
2563 /* If one type has an attribute, the other must have the same attribute. */
2564 if ((l1 != l2) || (s1 != s2))
2567 /* Disallow mixed attributes. */
2568 if ((l1 & s2) || (l2 & s1))
2572 /* Check for mismatched ISR attribute. */
2573 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2575 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2576 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2578 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2585 /* Encode long_call or short_call attribute by prefixing
2586 symbol name in DECL with a special character FLAG. */
2588 arm_encode_call_attribute (tree decl, int flag)
2590 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2591 int len = strlen (str);
2594 /* Do not allow weak functions to be treated as short call. */
2595 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2598 newstr = alloca (len + 2);
2600 strcpy (newstr + 1, str);
2602 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2603 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2606 /* Assigns default attributes to newly defined type. This is used to
2607 set short_call/long_call attributes for function types of
2608 functions defined inside corresponding #pragma scopes. */
2610 arm_set_default_type_attributes (tree type)
2612 /* Add __attribute__ ((long_call)) to all functions, when
2613 inside #pragma long_calls or __attribute__ ((short_call)),
2614 when inside #pragma no_long_calls. */
2615 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2617 tree type_attr_list, attr_name;
2618 type_attr_list = TYPE_ATTRIBUTES (type);
2620 if (arm_pragma_long_calls == LONG)
2621 attr_name = get_identifier ("long_call");
2622 else if (arm_pragma_long_calls == SHORT)
2623 attr_name = get_identifier ("short_call");
2627 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2628 TYPE_ATTRIBUTES (type) = type_attr_list;
2632 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2633 defined within the current compilation unit. If this cannot be
2634 determined, then 0 is returned. */
2636 current_file_function_operand (rtx sym_ref)
2638 /* This is a bit of a fib. A function will have a short call flag
2639 applied to its name if it has the short call attribute, or it has
2640 already been defined within the current compilation unit. */
2641 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2644 /* The current function is always defined within the current compilation
2645 unit. if it s a weak definition however, then this may not be the real
2646 definition of the function, and so we have to say no. */
2647 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2648 && !DECL_WEAK (current_function_decl))
2651 /* We cannot make the determination - default to returning 0. */
2655 /* Return nonzero if a 32 bit "long_call" should be generated for
2656 this call. We generate a long_call if the function:
2658 a. has an __attribute__((long call))
2659 or b. is within the scope of a #pragma long_calls
2660 or c. the -mlong-calls command line switch has been specified
2662 However we do not generate a long call if the function:
2664 d. has an __attribute__ ((short_call))
2665 or e. is inside the scope of a #pragma no_long_calls
2666 or f. has an __attribute__ ((section))
2667 or g. is defined within the current compilation unit.
2669 This function will be called by C fragments contained in the machine
2670 description file. CALL_REF and CALL_COOKIE correspond to the matched
2671 rtl operands. CALL_SYMBOL is used to distinguish between
2672 two different callers of the function. It is set to 1 in the
2673 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2674 and "call_value" patterns. This is because of the difference in the
2675 SYM_REFs passed by these patterns. */
2677 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2681 if (GET_CODE (sym_ref) != MEM)
2684 sym_ref = XEXP (sym_ref, 0);
2687 if (GET_CODE (sym_ref) != SYMBOL_REF)
2690 if (call_cookie & CALL_SHORT)
2693 if (TARGET_LONG_CALLS && flag_function_sections)
2696 if (current_file_function_operand (sym_ref))
2699 return (call_cookie & CALL_LONG)
2700 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2701 || TARGET_LONG_CALLS;
2704 /* Return nonzero if it is ok to make a tail-call to DECL. */
2706 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2708 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2710 if (cfun->machine->sibcall_blocked)
2713 /* Never tailcall something for which we have no decl, or if we
2714 are in Thumb mode. */
2715 if (decl == NULL || TARGET_THUMB)
2718 /* Get the calling method. */
2719 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2720 call_type = CALL_SHORT;
2721 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2722 call_type = CALL_LONG;
2724 /* Cannot tail-call to long calls, since these are out of range of
2725 a branch instruction. However, if not compiling PIC, we know
2726 we can reach the symbol if it is in this compilation unit. */
2727 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2730 /* If we are interworking and the function is not declared static
2731 then we can't tail-call it unless we know that it exists in this
2732 compilation unit (since it might be a Thumb routine). */
2733 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2736 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2737 if (IS_INTERRUPT (arm_current_func_type ()))
2740 /* Everything else is ok. */
2745 /* Addressing mode support functions. */
2747 /* Return nonzero if X is a legitimate immediate operand when compiling
2750 legitimate_pic_operand_p (rtx x)
2754 && (GET_CODE (x) == SYMBOL_REF
2755 || (GET_CODE (x) == CONST
2756 && GET_CODE (XEXP (x, 0)) == PLUS
2757 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2764 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2766 if (GET_CODE (orig) == SYMBOL_REF
2767 || GET_CODE (orig) == LABEL_REF)
2769 #ifndef AOF_ASSEMBLER
2770 rtx pic_ref, address;
2780 reg = gen_reg_rtx (Pmode);
2785 #ifdef AOF_ASSEMBLER
2786 /* The AOF assembler can generate relocations for these directly, and
2787 understands that the PIC register has to be added into the offset. */
2788 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2791 address = gen_reg_rtx (Pmode);
2796 emit_insn (gen_pic_load_addr_arm (address, orig));
2798 emit_insn (gen_pic_load_addr_thumb (address, orig));
2800 if ((GET_CODE (orig) == LABEL_REF
2801 || (GET_CODE (orig) == SYMBOL_REF &&
2802 SYMBOL_REF_LOCAL_P (orig)))
2804 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2807 pic_ref = gen_rtx_MEM (Pmode,
2808 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2810 RTX_UNCHANGING_P (pic_ref) = 1;
2813 insn = emit_move_insn (reg, pic_ref);
2815 current_function_uses_pic_offset_table = 1;
2816 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2818 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2822 else if (GET_CODE (orig) == CONST)
2826 if (GET_CODE (XEXP (orig, 0)) == PLUS
2827 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2835 reg = gen_reg_rtx (Pmode);
2838 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2840 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2841 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2842 base == reg ? 0 : reg);
2847 if (GET_CODE (offset) == CONST_INT)
2849 /* The base register doesn't really matter, we only want to
2850 test the index for the appropriate mode. */
2851 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2853 if (!no_new_pseudos)
2854 offset = force_reg (Pmode, offset);
2859 if (GET_CODE (offset) == CONST_INT)
2860 return plus_constant (base, INTVAL (offset));
2863 if (GET_MODE_SIZE (mode) > 4
2864 && (GET_MODE_CLASS (mode) == MODE_INT
2865 || TARGET_SOFT_FLOAT))
2867 emit_insn (gen_addsi3 (reg, base, offset));
2871 return gen_rtx_PLUS (Pmode, base, offset);
2877 /* Generate code to load the PIC register. PROLOGUE is true if
2878 called from arm_expand_prologue (in which case we want the
2879 generated insns at the start of the function); false if called
2880 by an exception receiver that needs the PIC register reloaded
2881 (in which case the insns are just dumped at the current location). */
2883 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2885 #ifndef AOF_ASSEMBLER
2886 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2887 rtx global_offset_table;
2889 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2896 l1 = gen_label_rtx ();
2898 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2899 /* On the ARM the PC register contains 'dot + 8' at the time of the
2900 addition, on the Thumb it is 'dot + 4'. */
2901 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2903 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2904 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2906 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2908 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2912 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2913 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2917 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2918 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2924 emit_insn_after (seq, get_insns ());
2928 /* Need to emit this whether or not we obey regdecls,
2929 since setjmp/longjmp can cause life info to screw up. */
2930 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2931 #endif /* AOF_ASSEMBLER */
2934 /* Return nonzero if X is valid as an ARM state addressing register. */
2936 arm_address_register_rtx_p (rtx x, int strict_p)
2940 if (GET_CODE (x) != REG)
2946 return ARM_REGNO_OK_FOR_BASE_P (regno);
2948 return (regno <= LAST_ARM_REGNUM
2949 || regno >= FIRST_PSEUDO_REGISTER
2950 || regno == FRAME_POINTER_REGNUM
2951 || regno == ARG_POINTER_REGNUM);
2954 /* Return nonzero if X is a valid ARM state address operand. */
2956 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2960 enum rtx_code code = GET_CODE (x);
2962 if (arm_address_register_rtx_p (x, strict_p))
2965 use_ldrd = (TARGET_LDRD
2967 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
2969 if (code == POST_INC || code == PRE_DEC
2970 || ((code == PRE_INC || code == POST_DEC)
2971 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
2972 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2974 else if ((code == POST_MODIFY || code == PRE_MODIFY)
2975 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2976 && GET_CODE (XEXP (x, 1)) == PLUS
2977 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2979 rtx addend = XEXP (XEXP (x, 1), 1);
2981 /* Don't allow ldrd post increment by register becuase it's hard
2982 to fixup invalid register choices. */
2984 && GET_CODE (x) == POST_MODIFY
2985 && GET_CODE (addend) == REG)
2988 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
2989 && arm_legitimate_index_p (mode, addend, outer, strict_p));
2992 /* After reload constants split into minipools will have addresses
2993 from a LABEL_REF. */
2994 else if (reload_completed
2995 && (code == LABEL_REF
2997 && GET_CODE (XEXP (x, 0)) == PLUS
2998 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2999 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3002 else if (mode == TImode)
3005 else if (code == PLUS)
3007 rtx xop0 = XEXP (x, 0);
3008 rtx xop1 = XEXP (x, 1);
3010 return ((arm_address_register_rtx_p (xop0, strict_p)
3011 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3012 || (arm_address_register_rtx_p (xop1, strict_p)
3013 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3017 /* Reload currently can't handle MINUS, so disable this for now */
3018 else if (GET_CODE (x) == MINUS)
3020 rtx xop0 = XEXP (x, 0);
3021 rtx xop1 = XEXP (x, 1);
3023 return (arm_address_register_rtx_p (xop0, strict_p)
3024 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3028 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3029 && code == SYMBOL_REF
3030 && CONSTANT_POOL_ADDRESS_P (x)
3032 && symbol_mentioned_p (get_pool_constant (x))))
3038 /* Return nonzero if INDEX is valid for an address index operand in
3041 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3044 HOST_WIDE_INT range;
3045 enum rtx_code code = GET_CODE (index);
3047 /* Standard coprocessor addressing modes. */
3048 if (TARGET_HARD_FLOAT
3049 && (TARGET_FPA || TARGET_MAVERICK)
3050 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3051 || (TARGET_MAVERICK && mode == DImode)))
3052 return (code == CONST_INT && INTVAL (index) < 1024
3053 && INTVAL (index) > -1024
3054 && (INTVAL (index) & 3) == 0);
3056 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3057 return (code == CONST_INT
3058 && INTVAL (index) < 1024
3059 && INTVAL (index) > -1024
3060 && (INTVAL (index) & 3) == 0);
3062 if (arm_address_register_rtx_p (index, strict_p)
3063 && (GET_MODE_SIZE (mode) <= 4))
3066 if (mode == DImode || mode == DFmode)
3068 if (code == CONST_INT)
3070 HOST_WIDE_INT val = INTVAL (index);
3073 return val > -256 && val < 256;
3075 return val == 4 || val == -4 || val == -8;
3078 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3081 if (GET_MODE_SIZE (mode) <= 4
3084 || (mode == QImode && outer == SIGN_EXTEND))))
3088 rtx xiop0 = XEXP (index, 0);
3089 rtx xiop1 = XEXP (index, 1);
3091 return ((arm_address_register_rtx_p (xiop0, strict_p)
3092 && power_of_two_operand (xiop1, SImode))
3093 || (arm_address_register_rtx_p (xiop1, strict_p)
3094 && power_of_two_operand (xiop0, SImode)));
3096 else if (code == LSHIFTRT || code == ASHIFTRT
3097 || code == ASHIFT || code == ROTATERT)
3099 rtx op = XEXP (index, 1);
3101 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3102 && GET_CODE (op) == CONST_INT
3104 && INTVAL (op) <= 31);
3108 /* For ARM v4 we may be doing a sign-extend operation during the
3112 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3118 range = (mode == HImode) ? 4095 : 4096;
3120 return (code == CONST_INT
3121 && INTVAL (index) < range
3122 && INTVAL (index) > -range);
3125 /* Return nonzero if X is valid as a Thumb state base register. */
3127 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3131 if (GET_CODE (x) != REG)
3137 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3139 return (regno <= LAST_LO_REGNUM
3140 || regno > LAST_VIRTUAL_REGISTER
3141 || regno == FRAME_POINTER_REGNUM
3142 || (GET_MODE_SIZE (mode) >= 4
3143 && (regno == STACK_POINTER_REGNUM
3144 || regno >= FIRST_PSEUDO_REGISTER
3145 || x == hard_frame_pointer_rtx
3146 || x == arg_pointer_rtx)));
3149 /* Return nonzero if x is a legitimate index register. This is the case
3150 for any base register that can access a QImode object. */
3152 thumb_index_register_rtx_p (rtx x, int strict_p)
3154 return thumb_base_register_rtx_p (x, QImode, strict_p);
3157 /* Return nonzero if x is a legitimate Thumb-state address.
3159 The AP may be eliminated to either the SP or the FP, so we use the
3160 least common denominator, e.g. SImode, and offsets from 0 to 64.
3162 ??? Verify whether the above is the right approach.
3164 ??? Also, the FP may be eliminated to the SP, so perhaps that
3165 needs special handling also.
3167 ??? Look at how the mips16 port solves this problem. It probably uses
3168 better ways to solve some of these problems.
3170 Although it is not incorrect, we don't accept QImode and HImode
3171 addresses based on the frame pointer or arg pointer until the
3172 reload pass starts. This is so that eliminating such addresses
3173 into stack based ones won't produce impossible code. */
3175 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3177 /* ??? Not clear if this is right. Experiment. */
3178 if (GET_MODE_SIZE (mode) < 4
3179 && !(reload_in_progress || reload_completed)
3180 && (reg_mentioned_p (frame_pointer_rtx, x)
3181 || reg_mentioned_p (arg_pointer_rtx, x)
3182 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3183 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3184 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3185 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3188 /* Accept any base register. SP only in SImode or larger. */
3189 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3192 /* This is PC relative data before arm_reorg runs. */
3193 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3194 && GET_CODE (x) == SYMBOL_REF
3195 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3198 /* This is PC relative data after arm_reorg runs. */
3199 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3200 && (GET_CODE (x) == LABEL_REF
3201 || (GET_CODE (x) == CONST
3202 && GET_CODE (XEXP (x, 0)) == PLUS
3203 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3204 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3207 /* Post-inc indexing only supported for SImode and larger. */
3208 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3209 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3212 else if (GET_CODE (x) == PLUS)
3214 /* REG+REG address can be any two index registers. */
3215 /* We disallow FRAME+REG addressing since we know that FRAME
3216 will be replaced with STACK, and SP relative addressing only
3217 permits SP+OFFSET. */
3218 if (GET_MODE_SIZE (mode) <= 4
3219 && XEXP (x, 0) != frame_pointer_rtx
3220 && XEXP (x, 1) != frame_pointer_rtx
3221 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3222 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3225 /* REG+const has 5-7 bit offset for non-SP registers. */
3226 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3227 || XEXP (x, 0) == arg_pointer_rtx)
3228 && GET_CODE (XEXP (x, 1)) == CONST_INT
3229 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3232 /* REG+const has 10 bit offset for SP, but only SImode and
3233 larger is supported. */
3234 /* ??? Should probably check for DI/DFmode overflow here
3235 just like GO_IF_LEGITIMATE_OFFSET does. */
3236 else if (GET_CODE (XEXP (x, 0)) == REG
3237 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3238 && GET_MODE_SIZE (mode) >= 4
3239 && GET_CODE (XEXP (x, 1)) == CONST_INT
3240 && INTVAL (XEXP (x, 1)) >= 0
3241 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3242 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3245 else if (GET_CODE (XEXP (x, 0)) == REG
3246 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3247 && GET_MODE_SIZE (mode) >= 4
3248 && GET_CODE (XEXP (x, 1)) == CONST_INT
3249 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3253 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3254 && GET_MODE_SIZE (mode) == 4
3255 && GET_CODE (x) == SYMBOL_REF
3256 && CONSTANT_POOL_ADDRESS_P (x)
3258 && symbol_mentioned_p (get_pool_constant (x))))
3264 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3265 instruction of mode MODE. */
3267 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3269 switch (GET_MODE_SIZE (mode))
3272 return val >= 0 && val < 32;
3275 return val >= 0 && val < 64 && (val & 1) == 0;
3279 && (val + GET_MODE_SIZE (mode)) <= 128
3284 /* Try machine-dependent ways of modifying an illegitimate address
3285 to be legitimate. If we find one, return the new, valid address. */
3287 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3289 if (GET_CODE (x) == PLUS)
3291 rtx xop0 = XEXP (x, 0);
3292 rtx xop1 = XEXP (x, 1);
3294 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3295 xop0 = force_reg (SImode, xop0);
3297 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3298 xop1 = force_reg (SImode, xop1);
3300 if (ARM_BASE_REGISTER_RTX_P (xop0)
3301 && GET_CODE (xop1) == CONST_INT)
3303 HOST_WIDE_INT n, low_n;
3307 /* VFP addressing modes actually allow greater offsets, but for
3308 now we just stick with the lowest common denominator. */
3310 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3322 low_n = ((mode) == TImode ? 0
3323 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3327 base_reg = gen_reg_rtx (SImode);
3328 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3329 GEN_INT (n)), NULL_RTX);
3330 emit_move_insn (base_reg, val);
3331 x = (low_n == 0 ? base_reg
3332 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3334 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3335 x = gen_rtx_PLUS (SImode, xop0, xop1);
3338 /* XXX We don't allow MINUS any more -- see comment in
3339 arm_legitimate_address_p (). */
3340 else if (GET_CODE (x) == MINUS)
3342 rtx xop0 = XEXP (x, 0);
3343 rtx xop1 = XEXP (x, 1);
3345 if (CONSTANT_P (xop0))
3346 xop0 = force_reg (SImode, xop0);
3348 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3349 xop1 = force_reg (SImode, xop1);
3351 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3352 x = gen_rtx_MINUS (SImode, xop0, xop1);
3357 /* We need to find and carefully transform any SYMBOL and LABEL
3358 references; so go back to the original address expression. */
3359 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3361 if (new_x != orig_x)
3369 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3370 to be legitimate. If we find one, return the new, valid address. */
3372 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3374 if (GET_CODE (x) == PLUS
3375 && GET_CODE (XEXP (x, 1)) == CONST_INT
3376 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3377 || INTVAL (XEXP (x, 1)) < 0))
3379 rtx xop0 = XEXP (x, 0);
3380 rtx xop1 = XEXP (x, 1);
3381 HOST_WIDE_INT offset = INTVAL (xop1);
3383 /* Try and fold the offset into a biasing of the base register and
3384 then offsetting that. Don't do this when optimizing for space
3385 since it can cause too many CSEs. */
3386 if (optimize_size && offset >= 0
3387 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3389 HOST_WIDE_INT delta;
3392 delta = offset - (256 - GET_MODE_SIZE (mode));
3393 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3394 delta = 31 * GET_MODE_SIZE (mode);
3396 delta = offset & (~31 * GET_MODE_SIZE (mode));
3398 xop0 = force_operand (plus_constant (xop0, offset - delta),
3400 x = plus_constant (xop0, delta);
3402 else if (offset < 0 && offset > -256)
3403 /* Small negative offsets are best done with a subtract before the
3404 dereference, forcing these into a register normally takes two
3406 x = force_operand (x, NULL_RTX);
3409 /* For the remaining cases, force the constant into a register. */
3410 xop1 = force_reg (SImode, xop1);
3411 x = gen_rtx_PLUS (SImode, xop0, xop1);
3414 else if (GET_CODE (x) == PLUS
3415 && s_register_operand (XEXP (x, 1), SImode)
3416 && !s_register_operand (XEXP (x, 0), SImode))
3418 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3420 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3425 /* We need to find and carefully transform any SYMBOL and LABEL
3426 references; so go back to the original address expression. */
3427 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3429 if (new_x != orig_x)
3438 #define REG_OR_SUBREG_REG(X) \
3439 (GET_CODE (X) == REG \
3440 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3442 #define REG_OR_SUBREG_RTX(X) \
3443 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3445 #ifndef COSTS_N_INSNS
3446 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3449 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3451 enum machine_mode mode = GET_MODE (x);
3464 return COSTS_N_INSNS (1);
3467 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3470 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3477 return COSTS_N_INSNS (2) + cycles;
3479 return COSTS_N_INSNS (1) + 16;
3482 return (COSTS_N_INSNS (1)
3483 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3484 + GET_CODE (SET_DEST (x)) == MEM));
3489 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3491 if (thumb_shiftable_const (INTVAL (x)))
3492 return COSTS_N_INSNS (2);
3493 return COSTS_N_INSNS (3);
3495 else if ((outer == PLUS || outer == COMPARE)
3496 && INTVAL (x) < 256 && INTVAL (x) > -256)
3498 else if (outer == AND
3499 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3500 return COSTS_N_INSNS (1);
3501 else if (outer == ASHIFT || outer == ASHIFTRT
3502 || outer == LSHIFTRT)
3504 return COSTS_N_INSNS (2);
3510 return COSTS_N_INSNS (3);
3529 /* XXX another guess. */
3530 /* Memory costs quite a lot for the first word, but subsequent words
3531 load at the equivalent of a single insn each. */
3532 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3533 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3538 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3543 /* XXX still guessing. */
3544 switch (GET_MODE (XEXP (x, 0)))
3547 return (1 + (mode == DImode ? 4 : 0)
3548 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3551 return (4 + (mode == DImode ? 4 : 0)
3552 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3555 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3567 /* Worker routine for arm_rtx_costs. */
3569 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3571 enum machine_mode mode = GET_MODE (x);
3572 enum rtx_code subcode;
3578 /* Memory costs quite a lot for the first word, but subsequent words
3579 load at the equivalent of a single insn each. */
3580 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3581 + (GET_CODE (x) == SYMBOL_REF
3582 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3588 return optimize_size ? COSTS_N_INSNS (2) : 100;
3591 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3598 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3600 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3601 + ((GET_CODE (XEXP (x, 0)) == REG
3602 || (GET_CODE (XEXP (x, 0)) == SUBREG
3603 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3605 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3606 || (GET_CODE (XEXP (x, 0)) == SUBREG
3607 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3609 + ((GET_CODE (XEXP (x, 1)) == REG
3610 || (GET_CODE (XEXP (x, 1)) == SUBREG
3611 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3612 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3617 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3618 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3619 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3620 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3623 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3624 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3625 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3626 && arm_const_double_rtx (XEXP (x, 1))))
3628 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3629 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3630 && arm_const_double_rtx (XEXP (x, 0))))
3633 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3634 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3635 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3636 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3637 || subcode == ASHIFTRT || subcode == LSHIFTRT
3638 || subcode == ROTATE || subcode == ROTATERT
3640 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3641 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3642 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3643 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3644 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3645 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3646 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3651 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3652 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3653 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3654 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3655 && arm_const_double_rtx (XEXP (x, 1))))
3659 case AND: case XOR: case IOR:
3662 /* Normally the frame registers will be spilt into reg+const during
3663 reload, so it is a bad idea to combine them with other instructions,
3664 since then they might not be moved outside of loops. As a compromise
3665 we allow integration with ops that have a constant as their second
3667 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3668 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3669 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3670 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3671 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3675 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3676 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3677 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3678 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3681 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3682 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3683 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3684 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3685 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3688 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3689 return (1 + extra_cost
3690 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3691 || subcode == LSHIFTRT || subcode == ASHIFTRT
3692 || subcode == ROTATE || subcode == ROTATERT
3694 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3695 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3696 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3697 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3698 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3699 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3705 /* This should have been handled by the CPU specific routines. */
3709 if (arm_arch3m && mode == SImode
3710 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3711 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3712 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3713 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3714 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3715 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3720 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3721 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3725 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3727 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3730 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3738 return 4 + (mode == DImode ? 4 : 0);
3741 if (GET_MODE (XEXP (x, 0)) == QImode)
3742 return (4 + (mode == DImode ? 4 : 0)
3743 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3746 switch (GET_MODE (XEXP (x, 0)))
3749 return (1 + (mode == DImode ? 4 : 0)
3750 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3753 return (4 + (mode == DImode ? 4 : 0)
3754 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3757 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3772 if (const_ok_for_arm (INTVAL (x)))
3773 return outer == SET ? 2 : -1;
3774 else if (outer == AND
3775 && const_ok_for_arm (~INTVAL (x)))
3777 else if ((outer == COMPARE
3778 || outer == PLUS || outer == MINUS)
3779 && const_ok_for_arm (-INTVAL (x)))
3790 if (arm_const_double_rtx (x))
3791 return outer == SET ? 2 : -1;
3792 else if ((outer == COMPARE || outer == PLUS)
3793 && neg_const_double_rtx_ok_for_fpa (x))
3802 /* RTX costs for cores with a slow MUL implementation. */
3805 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3807 enum machine_mode mode = GET_MODE (x);
3811 *total = thumb_rtx_costs (x, code, outer_code);
3818 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3825 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3827 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3828 & (unsigned HOST_WIDE_INT) 0xffffffff);
3829 int cost, const_ok = const_ok_for_arm (i);
3830 int j, booth_unit_size;
3832 /* Tune as appropriate. */
3833 cost = const_ok ? 4 : 8;
3834 booth_unit_size = 2;
3835 for (j = 0; i && j < 32; j += booth_unit_size)
3837 i >>= booth_unit_size;
3845 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3846 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3850 *total = arm_rtx_costs_1 (x, code, outer_code);
3856 /* RTX cost for cores with a fast multiply unit (M variants). */
3859 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3861 enum machine_mode mode = GET_MODE (x);
3865 *total = thumb_rtx_costs (x, code, outer_code);
3872 /* There is no point basing this on the tuning, since it is always the
3873 fast variant if it exists at all. */
3875 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3876 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3877 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3884 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3891 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3893 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3894 & (unsigned HOST_WIDE_INT) 0xffffffff);
3895 int cost, const_ok = const_ok_for_arm (i);
3896 int j, booth_unit_size;
3898 /* Tune as appropriate. */
3899 cost = const_ok ? 4 : 8;
3900 booth_unit_size = 8;
3901 for (j = 0; i && j < 32; j += booth_unit_size)
3903 i >>= booth_unit_size;
3911 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3912 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3916 *total = arm_rtx_costs_1 (x, code, outer_code);
3922 /* RTX cost for XScale CPUs. */
3925 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3927 enum machine_mode mode = GET_MODE (x);
3931 *total = thumb_rtx_costs (x, code, outer_code);
3938 /* There is no point basing this on the tuning, since it is always the
3939 fast variant if it exists at all. */
3941 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3942 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3943 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3950 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3957 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3959 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3960 & (unsigned HOST_WIDE_INT) 0xffffffff);
3961 int cost, const_ok = const_ok_for_arm (i);
3962 unsigned HOST_WIDE_INT masked_const;
3964 /* The cost will be related to two insns.
3965 First a load of the constant (MOV or LDR), then a multiply. */
3968 cost += 1; /* LDR is probably more expensive because
3969 of longer result latency. */
3970 masked_const = i & 0xffff8000;
3971 if (masked_const != 0 && masked_const != 0xffff8000)
3973 masked_const = i & 0xf8000000;
3974 if (masked_const == 0 || masked_const == 0xf8000000)
3983 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3984 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3988 *total = arm_rtx_costs_1 (x, code, outer_code);
3994 /* RTX costs for 9e (and later) cores. */
3997 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
3999 enum machine_mode mode = GET_MODE (x);
4008 *total = COSTS_N_INSNS (3);
4012 *total = thumb_rtx_costs (x, code, outer_code);
4020 /* There is no point basing this on the tuning, since it is always the
4021 fast variant if it exists at all. */
4023 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4024 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4025 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4032 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4049 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4050 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4054 *total = arm_rtx_costs_1 (x, code, outer_code);
4058 /* All address computations that can be done are free, but rtx cost returns
4059 the same for practically all of them. So we weight the different types
4060 of address here in the order (most pref first):
4061 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4063 arm_arm_address_cost (rtx x)
4065 enum rtx_code c = GET_CODE (x);
4067 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4069 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4072 if (c == PLUS || c == MINUS)
4074 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4077 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4087 arm_thumb_address_cost (rtx x)
4089 enum rtx_code c = GET_CODE (x);
4094 && GET_CODE (XEXP (x, 0)) == REG
4095 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4102 arm_address_cost (rtx x)
4104 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4108 arm_use_dfa_pipeline_interface (void)
4114 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4118 /* Some true dependencies can have a higher cost depending
4119 on precisely how certain input operands are used. */
4121 && REG_NOTE_KIND (link) == 0
4122 && recog_memoized (insn) >= 0
4123 && recog_memoized (dep) >= 0)
4125 int shift_opnum = get_attr_shift (insn);
4126 enum attr_type attr_type = get_attr_type (dep);
4128 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4129 operand for INSN. If we have a shifted input operand and the
4130 instruction we depend on is another ALU instruction, then we may
4131 have to account for an additional stall. */
4132 if (shift_opnum != 0
4133 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4135 rtx shifted_operand;
4138 /* Get the shifted operand. */
4139 extract_insn (insn);
4140 shifted_operand = recog_data.operand[shift_opnum];
4142 /* Iterate over all the operands in DEP. If we write an operand
4143 that overlaps with SHIFTED_OPERAND, then we have increase the
4144 cost of this dependency. */
4146 preprocess_constraints ();
4147 for (opno = 0; opno < recog_data.n_operands; opno++)
4149 /* We can ignore strict inputs. */
4150 if (recog_data.operand_type[opno] == OP_IN)
4153 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4160 /* XXX This is not strictly true for the FPA. */
4161 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4162 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4165 /* Call insns don't incur a stall, even if they follow a load. */
4166 if (REG_NOTE_KIND (link) == 0
4167 && GET_CODE (insn) == CALL_INSN)
4170 if ((i_pat = single_set (insn)) != NULL
4171 && GET_CODE (SET_SRC (i_pat)) == MEM
4172 && (d_pat = single_set (dep)) != NULL
4173 && GET_CODE (SET_DEST (d_pat)) == MEM)
4175 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4176 /* This is a load after a store, there is no conflict if the load reads
4177 from a cached area. Assume that loads from the stack, and from the
4178 constant pool are cached, and that others will miss. This is a
4181 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4182 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4183 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4184 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4191 static int fp_consts_inited = 0;
4193 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4194 static const char * const strings_fp[8] =
4197 "4", "5", "0.5", "10"
4200 static REAL_VALUE_TYPE values_fp[8];
4203 init_fp_table (void)
4209 fp_consts_inited = 1;
4211 fp_consts_inited = 8;
4213 for (i = 0; i < fp_consts_inited; i++)
4215 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4220 /* Return TRUE if rtx X is a valid immediate FP constant. */
4222 arm_const_double_rtx (rtx x)
4227 if (!fp_consts_inited)
4230 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4231 if (REAL_VALUE_MINUS_ZERO (r))
4234 for (i = 0; i < fp_consts_inited; i++)
4235 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4241 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4243 neg_const_double_rtx_ok_for_fpa (rtx x)
4248 if (!fp_consts_inited)
4251 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4252 r = REAL_VALUE_NEGATE (r);
4253 if (REAL_VALUE_MINUS_ZERO (r))
4256 for (i = 0; i < 8; i++)
4257 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4263 /* Predicates for `match_operand' and `match_operator'. */
4265 /* s_register_operand is the same as register_operand, but it doesn't accept
4268 This function exists because at the time it was put in it led to better
4269 code. SUBREG(MEM) always needs a reload in the places where
4270 s_register_operand is used, and this seemed to lead to excessive
4273 s_register_operand (rtx op, enum machine_mode mode)
4275 if (GET_MODE (op) != mode && mode != VOIDmode)
4278 if (GET_CODE (op) == SUBREG)
4279 op = SUBREG_REG (op);
4281 /* We don't consider registers whose class is NO_REGS
4282 to be a register operand. */
4283 /* XXX might have to check for lo regs only for thumb ??? */
4284 return (GET_CODE (op) == REG
4285 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4286 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4289 /* A hard register operand (even before reload. */
4291 arm_hard_register_operand (rtx op, enum machine_mode mode)
4293 if (GET_MODE (op) != mode && mode != VOIDmode)
4296 return (GET_CODE (op) == REG
4297 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4300 /* An arm register operand. */
4302 arm_general_register_operand (rtx op, enum machine_mode mode)
4304 if (GET_MODE (op) != mode && mode != VOIDmode)
4307 if (GET_CODE (op) == SUBREG)
4308 op = SUBREG_REG (op);
4310 return (GET_CODE (op) == REG
4311 && (REGNO (op) <= LAST_ARM_REGNUM
4312 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4315 /* Only accept reg, subreg(reg), const_int. */
4317 reg_or_int_operand (rtx op, enum machine_mode mode)
4319 if (GET_CODE (op) == CONST_INT)
4322 if (GET_MODE (op) != mode && mode != VOIDmode)
4325 if (GET_CODE (op) == SUBREG)
4326 op = SUBREG_REG (op);
4328 /* We don't consider registers whose class is NO_REGS
4329 to be a register operand. */
4330 return (GET_CODE (op) == REG
4331 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4332 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4335 /* Return 1 if OP is an item in memory, given that we are in reload. */
4337 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4339 int regno = true_regnum (op);
4341 return (!CONSTANT_P (op)
4343 || (GET_CODE (op) == REG
4344 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4347 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4349 arm_rhs_operand (rtx op, enum machine_mode mode)
4351 return (s_register_operand (op, mode)
4352 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4355 /* Return TRUE for valid operands for the
4356 rhs of an ARM instruction, or a load. */
4358 arm_rhsm_operand (rtx op, enum machine_mode mode)
4360 return (s_register_operand (op, mode)
4361 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4362 || memory_operand (op, mode));
4365 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4366 constant that is valid when negated. */
4368 arm_add_operand (rtx op, enum machine_mode mode)
4371 return thumb_cmp_operand (op, mode);
4373 return (s_register_operand (op, mode)
4374 || (GET_CODE (op) == CONST_INT
4375 && (const_ok_for_arm (INTVAL (op))
4376 || const_ok_for_arm (-INTVAL (op)))));
4379 /* Return TRUE for valid ARM constants (or when valid if negated). */
4381 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4383 return (GET_CODE (op) == CONST_INT
4384 && (const_ok_for_arm (INTVAL (op))
4385 || const_ok_for_arm (-INTVAL (op))));
4389 arm_not_operand (rtx op, enum machine_mode mode)
4391 return (s_register_operand (op, mode)
4392 || (GET_CODE (op) == CONST_INT
4393 && (const_ok_for_arm (INTVAL (op))
4394 || const_ok_for_arm (~INTVAL (op)))));
4397 /* Return TRUE if the operand is a memory reference which contains an
4398 offsettable address. */
4400 offsettable_memory_operand (rtx op, enum machine_mode mode)
4402 if (mode == VOIDmode)
4403 mode = GET_MODE (op);
4405 return (mode == GET_MODE (op)
4406 && GET_CODE (op) == MEM
4407 && offsettable_address_p (reload_completed | reload_in_progress,
4408 mode, XEXP (op, 0)));
4411 /* Return TRUE if the operand is a memory reference which is, or can be
4412 made word aligned by adjusting the offset. */
4414 alignable_memory_operand (rtx op, enum machine_mode mode)
4418 if (mode == VOIDmode)
4419 mode = GET_MODE (op);
4421 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4426 return ((GET_CODE (reg = op) == REG
4427 || (GET_CODE (op) == SUBREG
4428 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4429 || (GET_CODE (op) == PLUS
4430 && GET_CODE (XEXP (op, 1)) == CONST_INT
4431 && (GET_CODE (reg = XEXP (op, 0)) == REG
4432 || (GET_CODE (XEXP (op, 0)) == SUBREG
4433 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4434 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4437 /* Similar to s_register_operand, but does not allow hard integer
4440 f_register_operand (rtx op, enum machine_mode mode)
4442 if (GET_MODE (op) != mode && mode != VOIDmode)
4445 if (GET_CODE (op) == SUBREG)
4446 op = SUBREG_REG (op);
4448 /* We don't consider registers whose class is NO_REGS
4449 to be a register operand. */
4450 return (GET_CODE (op) == REG
4451 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4452 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4455 /* Return TRUE for valid operands for the rhs of an floating point insns.
4456 Allows regs or certain consts on FPA, just regs for everything else. */
4458 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4460 if (s_register_operand (op, mode))
4463 if (GET_MODE (op) != mode && mode != VOIDmode)
4466 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4467 return arm_const_double_rtx (op);
4473 arm_float_add_operand (rtx op, enum machine_mode mode)
4475 if (s_register_operand (op, mode))
4478 if (GET_MODE (op) != mode && mode != VOIDmode)
4481 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4482 return (arm_const_double_rtx (op)
4483 || neg_const_double_rtx_ok_for_fpa (op));
4489 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4490 Depends which fpu we are targeting. */
4493 arm_float_compare_operand (rtx op, enum machine_mode mode)
4496 return vfp_compare_operand (op, mode);
4498 return arm_float_rhs_operand (op, mode);
4502 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4504 cirrus_memory_offset (rtx op)
4506 /* Reject eliminable registers. */
4507 if (! (reload_in_progress || reload_completed)
4508 && ( reg_mentioned_p (frame_pointer_rtx, op)
4509 || reg_mentioned_p (arg_pointer_rtx, op)
4510 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4511 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4512 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4513 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4516 if (GET_CODE (op) == MEM)
4522 /* Match: (mem (reg)). */
4523 if (GET_CODE (ind) == REG)
4529 if (GET_CODE (ind) == PLUS
4530 && GET_CODE (XEXP (ind, 0)) == REG
4531 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4532 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4540 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4542 if (!memory_operand (op, mode))
4545 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4548 /* Return nonzero if OP is a Cirrus or general register. */
4550 cirrus_register_operand (rtx op, enum machine_mode mode)
4552 if (GET_MODE (op) != mode && mode != VOIDmode)
4555 if (GET_CODE (op) == SUBREG)
4556 op = SUBREG_REG (op);
4558 return (GET_CODE (op) == REG
4559 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4560 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4563 /* Return nonzero if OP is a cirrus FP register. */
4565 cirrus_fp_register (rtx op, enum machine_mode mode)
4567 if (GET_MODE (op) != mode && mode != VOIDmode)
4570 if (GET_CODE (op) == SUBREG)
4571 op = SUBREG_REG (op);
4573 return (GET_CODE (op) == REG
4574 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4575 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4578 /* Return nonzero if OP is a 6bit constant (0..63). */
4580 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4582 return (GET_CODE (op) == CONST_INT
4584 && INTVAL (op) < 64);
4588 /* Return TRUE if OP is a valid VFP memory address pattern.
4589 WB if true if writeback address modes are allowed. */
4592 arm_coproc_mem_operand (rtx op, bool wb)
4596 /* Reject eliminable registers. */
4597 if (! (reload_in_progress || reload_completed)
4598 && ( reg_mentioned_p (frame_pointer_rtx, op)
4599 || reg_mentioned_p (arg_pointer_rtx, op)
4600 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4601 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4602 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4603 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4606 /* Constants are converted into offsets from labels. */
4607 if (GET_CODE (op) != MEM)
4612 if (reload_completed
4613 && (GET_CODE (ind) == LABEL_REF
4614 || (GET_CODE (ind) == CONST
4615 && GET_CODE (XEXP (ind, 0)) == PLUS
4616 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4617 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4620 /* Match: (mem (reg)). */
4621 if (GET_CODE (ind) == REG)
4622 return arm_address_register_rtx_p (ind, 0);
4624 /* Autoincremment addressing modes. */
4626 && (GET_CODE (ind) == PRE_INC
4627 || GET_CODE (ind) == POST_INC
4628 || GET_CODE (ind) == PRE_DEC
4629 || GET_CODE (ind) == POST_DEC))
4630 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4633 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4634 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4635 && GET_CODE (XEXP (ind, 1)) == PLUS
4636 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4637 ind = XEXP (ind, 1);
4642 if (GET_CODE (ind) == PLUS
4643 && GET_CODE (XEXP (ind, 0)) == REG
4644 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4645 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4646 && INTVAL (XEXP (ind, 1)) > -1024
4647 && INTVAL (XEXP (ind, 1)) < 1024
4648 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4655 /* Return TRUE if OP is a REG or constant zero. */
4657 vfp_compare_operand (rtx op, enum machine_mode mode)
4659 if (s_register_operand (op, mode))
4662 return (GET_CODE (op) == CONST_DOUBLE
4663 && arm_const_double_rtx (op));
4667 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4668 VFP registers. Otherwise return NO_REGS. */
4671 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4673 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4676 return GENERAL_REGS;
4680 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4681 Use by the Cirrus Maverick code which has to workaround
4682 a hardware bug triggered by such instructions. */
4684 arm_memory_load_p (rtx insn)
4686 rtx body, lhs, rhs;;
4688 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4691 body = PATTERN (insn);
4693 if (GET_CODE (body) != SET)
4696 lhs = XEXP (body, 0);
4697 rhs = XEXP (body, 1);
4699 lhs = REG_OR_SUBREG_RTX (lhs);
4701 /* If the destination is not a general purpose
4702 register we do not have to worry. */
4703 if (GET_CODE (lhs) != REG
4704 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4707 /* As well as loads from memory we also have to react
4708 to loads of invalid constants which will be turned
4709 into loads from the minipool. */
4710 return (GET_CODE (rhs) == MEM
4711 || GET_CODE (rhs) == SYMBOL_REF
4712 || note_invalid_constants (insn, -1, false));
4715 /* Return TRUE if INSN is a Cirrus instruction. */
4717 arm_cirrus_insn_p (rtx insn)
4719 enum attr_cirrus attr;
4721 /* get_attr aborts on USE and CLOBBER. */
4723 || GET_CODE (insn) != INSN
4724 || GET_CODE (PATTERN (insn)) == USE
4725 || GET_CODE (PATTERN (insn)) == CLOBBER)
4728 attr = get_attr_cirrus (insn);
4730 return attr != CIRRUS_NOT;
4733 /* Cirrus reorg for invalid instruction combinations. */
4735 cirrus_reorg (rtx first)
4737 enum attr_cirrus attr;
4738 rtx body = PATTERN (first);
4742 /* Any branch must be followed by 2 non Cirrus instructions. */
4743 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4746 t = next_nonnote_insn (first);
4748 if (arm_cirrus_insn_p (t))
4751 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4755 emit_insn_after (gen_nop (), first);
4760 /* (float (blah)) is in parallel with a clobber. */
4761 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4762 body = XVECEXP (body, 0, 0);
4764 if (GET_CODE (body) == SET)
4766 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4768 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4769 be followed by a non Cirrus insn. */
4770 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4772 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4773 emit_insn_after (gen_nop (), first);
4777 else if (arm_memory_load_p (first))
4779 unsigned int arm_regno;
4781 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4782 ldr/cfmv64hr combination where the Rd field is the same
4783 in both instructions must be split with a non Cirrus
4790 /* Get Arm register number for ldr insn. */
4791 if (GET_CODE (lhs) == REG)
4792 arm_regno = REGNO (lhs);
4793 else if (GET_CODE (rhs) == REG)
4794 arm_regno = REGNO (rhs);
4799 first = next_nonnote_insn (first);
4801 if (! arm_cirrus_insn_p (first))
4804 body = PATTERN (first);
4806 /* (float (blah)) is in parallel with a clobber. */
4807 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4808 body = XVECEXP (body, 0, 0);
4810 if (GET_CODE (body) == FLOAT)
4811 body = XEXP (body, 0);
4813 if (get_attr_cirrus (first) == CIRRUS_MOVE
4814 && GET_CODE (XEXP (body, 1)) == REG
4815 && arm_regno == REGNO (XEXP (body, 1)))
4816 emit_insn_after (gen_nop (), first);
4822 /* get_attr aborts on USE and CLOBBER. */
4824 || GET_CODE (first) != INSN
4825 || GET_CODE (PATTERN (first)) == USE
4826 || GET_CODE (PATTERN (first)) == CLOBBER)
4829 attr = get_attr_cirrus (first);
4831 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4832 must be followed by a non-coprocessor instruction. */
4833 if (attr == CIRRUS_COMPARE)
4837 t = next_nonnote_insn (first);
4839 if (arm_cirrus_insn_p (t))
4842 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4846 emit_insn_after (gen_nop (), first);
4852 /* Return nonzero if OP is a constant power of two. */
4854 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4856 if (GET_CODE (op) == CONST_INT)
4858 HOST_WIDE_INT value = INTVAL (op);
4860 return value != 0 && (value & (value - 1)) == 0;
4866 /* Return TRUE for a valid operand of a DImode operation.
4867 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4868 Note that this disallows MEM(REG+REG), but allows
4869 MEM(PRE/POST_INC/DEC(REG)). */
4871 di_operand (rtx op, enum machine_mode mode)
4873 if (s_register_operand (op, mode))
4876 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4879 if (GET_CODE (op) == SUBREG)
4880 op = SUBREG_REG (op);
4882 switch (GET_CODE (op))
4889 return memory_address_p (DImode, XEXP (op, 0));
4896 /* Like di_operand, but don't accept constants. */
4898 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4900 if (s_register_operand (op, mode))
4903 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4906 if (GET_CODE (op) == SUBREG)
4907 op = SUBREG_REG (op);
4909 if (GET_CODE (op) == MEM)
4910 return memory_address_p (DImode, XEXP (op, 0));
4915 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4916 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4917 Note that this disallows MEM(REG+REG), but allows
4918 MEM(PRE/POST_INC/DEC(REG)). */
4920 soft_df_operand (rtx op, enum machine_mode mode)
4922 if (s_register_operand (op, mode))
4925 if (mode != VOIDmode && GET_MODE (op) != mode)
4928 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4931 if (GET_CODE (op) == SUBREG)
4932 op = SUBREG_REG (op);
4934 switch (GET_CODE (op))
4940 return memory_address_p (DFmode, XEXP (op, 0));
4947 /* Like soft_df_operand, but don't accept constants. */
4949 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4951 if (s_register_operand (op, mode))
4954 if (mode != VOIDmode && GET_MODE (op) != mode)
4957 if (GET_CODE (op) == SUBREG)
4958 op = SUBREG_REG (op);
4960 if (GET_CODE (op) == MEM)
4961 return memory_address_p (DFmode, XEXP (op, 0));
4965 /* Return TRUE for valid index operands. */
4967 index_operand (rtx op, enum machine_mode mode)
4969 return (s_register_operand (op, mode)
4970 || (immediate_operand (op, mode)
4971 && (GET_CODE (op) != CONST_INT
4972 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4975 /* Return TRUE for valid shifts by a constant. This also accepts any
4976 power of two on the (somewhat overly relaxed) assumption that the
4977 shift operator in this case was a mult. */
4979 const_shift_operand (rtx op, enum machine_mode mode)
4981 return (power_of_two_operand (op, mode)
4982 || (immediate_operand (op, mode)
4983 && (GET_CODE (op) != CONST_INT
4984 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4987 /* Return TRUE for arithmetic operators which can be combined with a multiply
4990 shiftable_operator (rtx x, enum machine_mode mode)
4994 if (GET_MODE (x) != mode)
4997 code = GET_CODE (x);
4999 return (code == PLUS || code == MINUS
5000 || code == IOR || code == XOR || code == AND);
5003 /* Return TRUE for binary logical operators. */
5005 logical_binary_operator (rtx x, enum machine_mode mode)
5009 if (GET_MODE (x) != mode)
5012 code = GET_CODE (x);
5014 return (code == IOR || code == XOR || code == AND);
5017 /* Return TRUE for shift operators. */
5019 shift_operator (rtx x,enum machine_mode mode)
5023 if (GET_MODE (x) != mode)
5026 code = GET_CODE (x);
5029 return power_of_two_operand (XEXP (x, 1), mode);
5031 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5032 || code == ROTATERT);
5035 /* Return TRUE if x is EQ or NE. */
5037 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5039 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5042 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5044 arm_comparison_operator (rtx x, enum machine_mode mode)
5046 return (comparison_operator (x, mode)
5047 && GET_CODE (x) != LTGT
5048 && GET_CODE (x) != UNEQ);
5051 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5053 minmax_operator (rtx x, enum machine_mode mode)
5055 enum rtx_code code = GET_CODE (x);
5057 if (GET_MODE (x) != mode)
5060 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5063 /* Return TRUE if this is the condition code register, if we aren't given
5064 a mode, accept any class CCmode register. */
5066 cc_register (rtx x, enum machine_mode mode)
5068 if (mode == VOIDmode)
5070 mode = GET_MODE (x);
5072 if (GET_MODE_CLASS (mode) != MODE_CC)
5076 if ( GET_MODE (x) == mode
5077 && GET_CODE (x) == REG
5078 && REGNO (x) == CC_REGNUM)
5084 /* Return TRUE if this is the condition code register, if we aren't given
5085 a mode, accept any class CCmode register which indicates a dominance
5088 dominant_cc_register (rtx x, enum machine_mode mode)
5090 if (mode == VOIDmode)
5092 mode = GET_MODE (x);
5094 if (GET_MODE_CLASS (mode) != MODE_CC)
5098 if (mode != CC_DNEmode && mode != CC_DEQmode
5099 && mode != CC_DLEmode && mode != CC_DLTmode
5100 && mode != CC_DGEmode && mode != CC_DGTmode
5101 && mode != CC_DLEUmode && mode != CC_DLTUmode
5102 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5105 return cc_register (x, mode);
5108 /* Return TRUE if X references a SYMBOL_REF. */
5110 symbol_mentioned_p (rtx x)
5115 if (GET_CODE (x) == SYMBOL_REF)
5118 fmt = GET_RTX_FORMAT (GET_CODE (x));
5120 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5126 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5127 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5130 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5137 /* Return TRUE if X references a LABEL_REF. */
5139 label_mentioned_p (rtx x)
5144 if (GET_CODE (x) == LABEL_REF)
5147 fmt = GET_RTX_FORMAT (GET_CODE (x));
5148 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5154 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5155 if (label_mentioned_p (XVECEXP (x, i, j)))
5158 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5168 enum rtx_code code = GET_CODE (x);
5172 else if (code == SMIN)
5174 else if (code == UMIN)
5176 else if (code == UMAX)
5182 /* Return 1 if memory locations are adjacent. */
5184 adjacent_mem_locations (rtx a, rtx b)
5186 if ((GET_CODE (XEXP (a, 0)) == REG
5187 || (GET_CODE (XEXP (a, 0)) == PLUS
5188 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5189 && (GET_CODE (XEXP (b, 0)) == REG
5190 || (GET_CODE (XEXP (b, 0)) == PLUS
5191 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5193 int val0 = 0, val1 = 0;
5196 if (GET_CODE (XEXP (a, 0)) == PLUS)
5198 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5199 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5202 reg0 = REGNO (XEXP (a, 0));
5204 if (GET_CODE (XEXP (b, 0)) == PLUS)
5206 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5207 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5210 reg1 = REGNO (XEXP (b, 0));
5212 /* Don't accept any offset that will require multiple
5213 instructions to handle, since this would cause the
5214 arith_adjacentmem pattern to output an overlong sequence. */
5215 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5218 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5223 /* Return 1 if OP is a load multiple operation. It is known to be
5224 parallel and the first section will be tested. */
5226 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5228 HOST_WIDE_INT count = XVECLEN (op, 0);
5231 HOST_WIDE_INT i = 1, base = 0;
5235 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5238 /* Check to see if this might be a write-back. */
5239 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5244 /* Now check it more carefully. */
5245 if (GET_CODE (SET_DEST (elt)) != REG
5246 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5247 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5248 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5252 /* Perform a quick check so we don't blow up below. */
5254 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5255 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5256 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5259 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5260 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5262 for (; i < count; i++)
5264 elt = XVECEXP (op, 0, i);
5266 if (GET_CODE (elt) != SET
5267 || GET_CODE (SET_DEST (elt)) != REG
5268 || GET_MODE (SET_DEST (elt)) != SImode
5269 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5270 || GET_CODE (SET_SRC (elt)) != MEM
5271 || GET_MODE (SET_SRC (elt)) != SImode
5272 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5273 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5274 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5275 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5282 /* Return 1 if OP is a store multiple operation. It is known to be
5283 parallel and the first section will be tested. */
5285 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5287 HOST_WIDE_INT count = XVECLEN (op, 0);
5290 HOST_WIDE_INT i = 1, base = 0;
5294 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5297 /* Check to see if this might be a write-back. */
5298 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5303 /* Now check it more carefully. */
5304 if (GET_CODE (SET_DEST (elt)) != REG
5305 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5306 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5307 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5311 /* Perform a quick check so we don't blow up below. */
5313 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5314 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5315 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5318 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5319 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5321 for (; i < count; i++)
5323 elt = XVECEXP (op, 0, i);
5325 if (GET_CODE (elt) != SET
5326 || GET_CODE (SET_SRC (elt)) != REG
5327 || GET_MODE (SET_SRC (elt)) != SImode
5328 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5329 || GET_CODE (SET_DEST (elt)) != MEM
5330 || GET_MODE (SET_DEST (elt)) != SImode
5331 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5332 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5333 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5334 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5342 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5343 HOST_WIDE_INT *load_offset)
5345 int unsorted_regs[4];
5346 HOST_WIDE_INT unsorted_offsets[4];
5351 /* Can only handle 2, 3, or 4 insns at present,
5352 though could be easily extended if required. */
5353 if (nops < 2 || nops > 4)
5356 /* Loop over the operands and check that the memory references are
5357 suitable (ie immediate offsets from the same base register). At
5358 the same time, extract the target register, and the memory
5360 for (i = 0; i < nops; i++)
5365 /* Convert a subreg of a mem into the mem itself. */
5366 if (GET_CODE (operands[nops + i]) == SUBREG)
5367 operands[nops + i] = alter_subreg (operands + (nops + i));
5369 if (GET_CODE (operands[nops + i]) != MEM)
5372 /* Don't reorder volatile memory references; it doesn't seem worth
5373 looking for the case where the order is ok anyway. */
5374 if (MEM_VOLATILE_P (operands[nops + i]))
5377 offset = const0_rtx;
5379 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5380 || (GET_CODE (reg) == SUBREG
5381 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5382 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5383 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5385 || (GET_CODE (reg) == SUBREG
5386 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5387 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5392 base_reg = REGNO (reg);
5393 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5394 ? REGNO (operands[i])
5395 : REGNO (SUBREG_REG (operands[i])));
5400 if (base_reg != (int) REGNO (reg))
5401 /* Not addressed from the same base register. */
5404 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5405 ? REGNO (operands[i])
5406 : REGNO (SUBREG_REG (operands[i])));
5407 if (unsorted_regs[i] < unsorted_regs[order[0]])
5411 /* If it isn't an integer register, or if it overwrites the
5412 base register but isn't the last insn in the list, then
5413 we can't do this. */
5414 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5415 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5418 unsorted_offsets[i] = INTVAL (offset);
5421 /* Not a suitable memory address. */
5425 /* All the useful information has now been extracted from the
5426 operands into unsorted_regs and unsorted_offsets; additionally,
5427 order[0] has been set to the lowest numbered register in the
5428 list. Sort the registers into order, and check that the memory
5429 offsets are ascending and adjacent. */
5431 for (i = 1; i < nops; i++)
5435 order[i] = order[i - 1];
5436 for (j = 0; j < nops; j++)
5437 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5438 && (order[i] == order[i - 1]
5439 || unsorted_regs[j] < unsorted_regs[order[i]]))
5442 /* Have we found a suitable register? if not, one must be used more
5444 if (order[i] == order[i - 1])
5447 /* Is the memory address adjacent and ascending? */
5448 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5456 for (i = 0; i < nops; i++)
5457 regs[i] = unsorted_regs[order[i]];
5459 *load_offset = unsorted_offsets[order[0]];
5462 if (unsorted_offsets[order[0]] == 0)
5463 return 1; /* ldmia */
5465 if (unsorted_offsets[order[0]] == 4)
5466 return 2; /* ldmib */
5468 if (unsorted_offsets[order[nops - 1]] == 0)
5469 return 3; /* ldmda */
5471 if (unsorted_offsets[order[nops - 1]] == -4)
5472 return 4; /* ldmdb */
5474 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5475 if the offset isn't small enough. The reason 2 ldrs are faster
5476 is because these ARMs are able to do more than one cache access
5477 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5478 whilst the ARM8 has a double bandwidth cache. This means that
5479 these cores can do both an instruction fetch and a data fetch in
5480 a single cycle, so the trick of calculating the address into a
5481 scratch register (one of the result regs) and then doing a load
5482 multiple actually becomes slower (and no smaller in code size).
5483 That is the transformation
5485 ldr rd1, [rbase + offset]
5486 ldr rd2, [rbase + offset + 4]
5490 add rd1, rbase, offset
5491 ldmia rd1, {rd1, rd2}
5493 produces worse code -- '3 cycles + any stalls on rd2' instead of
5494 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5495 access per cycle, the first sequence could never complete in less
5496 than 6 cycles, whereas the ldm sequence would only take 5 and
5497 would make better use of sequential accesses if not hitting the
5500 We cheat here and test 'arm_ld_sched' which we currently know to
5501 only be true for the ARM8, ARM9 and StrongARM. If this ever
5502 changes, then the test below needs to be reworked. */
5503 if (nops == 2 && arm_ld_sched)
5506 /* Can't do it without setting up the offset, only do this if it takes
5507 no more than one insn. */
5508 return (const_ok_for_arm (unsorted_offsets[order[0]])
5509 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5513 emit_ldm_seq (rtx *operands, int nops)
5517 HOST_WIDE_INT offset;
5521 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5524 strcpy (buf, "ldm%?ia\t");
5528 strcpy (buf, "ldm%?ib\t");
5532 strcpy (buf, "ldm%?da\t");
5536 strcpy (buf, "ldm%?db\t");
5541 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5542 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5545 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5546 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5548 output_asm_insn (buf, operands);
5550 strcpy (buf, "ldm%?ia\t");
5557 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5558 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5560 for (i = 1; i < nops; i++)
5561 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5562 reg_names[regs[i]]);
5564 strcat (buf, "}\t%@ phole ldm");
5566 output_asm_insn (buf, operands);
5571 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5572 HOST_WIDE_INT * load_offset)
5574 int unsorted_regs[4];
5575 HOST_WIDE_INT unsorted_offsets[4];
5580 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5581 extended if required. */
5582 if (nops < 2 || nops > 4)
5585 /* Loop over the operands and check that the memory references are
5586 suitable (ie immediate offsets from the same base register). At
5587 the same time, extract the target register, and the memory
5589 for (i = 0; i < nops; i++)
5594 /* Convert a subreg of a mem into the mem itself. */
5595 if (GET_CODE (operands[nops + i]) == SUBREG)
5596 operands[nops + i] = alter_subreg (operands + (nops + i));
5598 if (GET_CODE (operands[nops + i]) != MEM)
5601 /* Don't reorder volatile memory references; it doesn't seem worth
5602 looking for the case where the order is ok anyway. */
5603 if (MEM_VOLATILE_P (operands[nops + i]))
5606 offset = const0_rtx;
5608 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5609 || (GET_CODE (reg) == SUBREG
5610 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5611 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5612 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5614 || (GET_CODE (reg) == SUBREG
5615 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5616 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5621 base_reg = REGNO (reg);
5622 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5623 ? REGNO (operands[i])
5624 : REGNO (SUBREG_REG (operands[i])));
5629 if (base_reg != (int) REGNO (reg))
5630 /* Not addressed from the same base register. */
5633 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5634 ? REGNO (operands[i])
5635 : REGNO (SUBREG_REG (operands[i])));
5636 if (unsorted_regs[i] < unsorted_regs[order[0]])
5640 /* If it isn't an integer register, then we can't do this. */
5641 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5644 unsorted_offsets[i] = INTVAL (offset);
5647 /* Not a suitable memory address. */
5651 /* All the useful information has now been extracted from the
5652 operands into unsorted_regs and unsorted_offsets; additionally,
5653 order[0] has been set to the lowest numbered register in the
5654 list. Sort the registers into order, and check that the memory
5655 offsets are ascending and adjacent. */
5657 for (i = 1; i < nops; i++)
5661 order[i] = order[i - 1];
5662 for (j = 0; j < nops; j++)
5663 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5664 && (order[i] == order[i - 1]
5665 || unsorted_regs[j] < unsorted_regs[order[i]]))
5668 /* Have we found a suitable register? if not, one must be used more
5670 if (order[i] == order[i - 1])
5673 /* Is the memory address adjacent and ascending? */
5674 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5682 for (i = 0; i < nops; i++)
5683 regs[i] = unsorted_regs[order[i]];
5685 *load_offset = unsorted_offsets[order[0]];
5688 if (unsorted_offsets[order[0]] == 0)
5689 return 1; /* stmia */
5691 if (unsorted_offsets[order[0]] == 4)
5692 return 2; /* stmib */
5694 if (unsorted_offsets[order[nops - 1]] == 0)
5695 return 3; /* stmda */
5697 if (unsorted_offsets[order[nops - 1]] == -4)
5698 return 4; /* stmdb */
5704 emit_stm_seq (rtx *operands, int nops)
5708 HOST_WIDE_INT offset;
5712 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5715 strcpy (buf, "stm%?ia\t");
5719 strcpy (buf, "stm%?ib\t");
5723 strcpy (buf, "stm%?da\t");
5727 strcpy (buf, "stm%?db\t");
5734 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5735 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5737 for (i = 1; i < nops; i++)
5738 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5739 reg_names[regs[i]]);
5741 strcat (buf, "}\t%@ phole stm");
5743 output_asm_insn (buf, operands);
5748 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5750 if (GET_CODE (op) != PARALLEL
5751 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5752 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5753 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5759 /* Routines for use in generating RTL. */
5762 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5763 int write_back, int unchanging_p, int in_struct_p,
5768 int sign = up ? 1 : -1;
5771 /* XScale has load-store double instructions, but they have stricter
5772 alignment requirements than load-store multiple, so we can not
5775 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5776 the pipeline until completion.
5784 An ldr instruction takes 1-3 cycles, but does not block the
5793 Best case ldr will always win. However, the more ldr instructions
5794 we issue, the less likely we are to be able to schedule them well.
5795 Using ldr instructions also increases code size.
5797 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5798 for counts of 3 or 4 regs. */
5799 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5805 for (i = 0; i < count; i++)
5807 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5808 RTX_UNCHANGING_P (mem) = unchanging_p;
5809 MEM_IN_STRUCT_P (mem) = in_struct_p;
5810 MEM_SCALAR_P (mem) = scalar_p;
5811 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5815 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5823 result = gen_rtx_PARALLEL (VOIDmode,
5824 rtvec_alloc (count + (write_back ? 1 : 0)));
5827 XVECEXP (result, 0, 0)
5828 = gen_rtx_SET (GET_MODE (from), from,
5829 plus_constant (from, count * 4 * sign));
5834 for (j = 0; i < count; i++, j++)
5836 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5837 RTX_UNCHANGING_P (mem) = unchanging_p;
5838 MEM_IN_STRUCT_P (mem) = in_struct_p;
5839 MEM_SCALAR_P (mem) = scalar_p;
5840 XVECEXP (result, 0, i)
5841 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5848 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5849 int write_back, int unchanging_p, int in_struct_p,
5854 int sign = up ? 1 : -1;
5857 /* See arm_gen_load_multiple for discussion of
5858 the pros/cons of ldm/stm usage for XScale. */
5859 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5865 for (i = 0; i < count; i++)
5867 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5868 RTX_UNCHANGING_P (mem) = unchanging_p;
5869 MEM_IN_STRUCT_P (mem) = in_struct_p;
5870 MEM_SCALAR_P (mem) = scalar_p;
5871 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5875 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5883 result = gen_rtx_PARALLEL (VOIDmode,
5884 rtvec_alloc (count + (write_back ? 1 : 0)));
5887 XVECEXP (result, 0, 0)
5888 = gen_rtx_SET (GET_MODE (to), to,
5889 plus_constant (to, count * 4 * sign));
5894 for (j = 0; i < count; i++, j++)
5896 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5897 RTX_UNCHANGING_P (mem) = unchanging_p;
5898 MEM_IN_STRUCT_P (mem) = in_struct_p;
5899 MEM_SCALAR_P (mem) = scalar_p;
5901 XVECEXP (result, 0, i)
5902 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5909 arm_gen_movstrqi (rtx *operands)
5911 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5914 rtx st_src, st_dst, fin_src, fin_dst;
5915 rtx part_bytes_reg = NULL;
5917 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5918 int dst_scalar_p, src_scalar_p;
5920 if (GET_CODE (operands[2]) != CONST_INT
5921 || GET_CODE (operands[3]) != CONST_INT
5922 || INTVAL (operands[2]) > 64
5923 || INTVAL (operands[3]) & 3)
5926 st_dst = XEXP (operands[0], 0);
5927 st_src = XEXP (operands[1], 0);
5929 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5930 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5931 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5932 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5933 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5934 src_scalar_p = MEM_SCALAR_P (operands[1]);
5936 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5937 fin_src = src = copy_to_mode_reg (SImode, st_src);
5939 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5940 out_words_to_go = INTVAL (operands[2]) / 4;
5941 last_bytes = INTVAL (operands[2]) & 3;
5943 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5944 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5946 for (i = 0; in_words_to_go >= 2; i+=4)
5948 if (in_words_to_go > 4)
5949 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5954 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5955 FALSE, src_unchanging_p,
5956 src_in_struct_p, src_scalar_p));
5958 if (out_words_to_go)
5960 if (out_words_to_go > 4)
5961 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5965 else if (out_words_to_go != 1)
5966 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5975 mem = gen_rtx_MEM (SImode, dst);
5976 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5977 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5978 MEM_SCALAR_P (mem) = dst_scalar_p;
5979 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5980 if (last_bytes != 0)
5981 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5985 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5986 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5989 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5990 if (out_words_to_go)
5994 mem = gen_rtx_MEM (SImode, src);
5995 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5996 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5997 MEM_SCALAR_P (mem) = src_scalar_p;
5998 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5999 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6001 mem = gen_rtx_MEM (SImode, dst);
6002 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6003 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6004 MEM_SCALAR_P (mem) = dst_scalar_p;
6005 emit_move_insn (mem, sreg);
6006 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6009 if (in_words_to_go) /* Sanity check */
6015 if (in_words_to_go < 0)
6018 mem = gen_rtx_MEM (SImode, src);
6019 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6020 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6021 MEM_SCALAR_P (mem) = src_scalar_p;
6022 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6025 if (last_bytes && part_bytes_reg == NULL)
6028 if (BYTES_BIG_ENDIAN && last_bytes)
6030 rtx tmp = gen_reg_rtx (SImode);
6032 /* The bytes we want are in the top end of the word. */
6033 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6034 GEN_INT (8 * (4 - last_bytes))));
6035 part_bytes_reg = tmp;
6039 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6040 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6041 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6042 MEM_SCALAR_P (mem) = dst_scalar_p;
6043 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6047 tmp = gen_reg_rtx (SImode);
6048 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6049 part_bytes_reg = tmp;
6058 mem = gen_rtx_MEM (HImode, dst);
6059 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6060 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6061 MEM_SCALAR_P (mem) = dst_scalar_p;
6062 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6066 rtx tmp = gen_reg_rtx (SImode);
6068 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6069 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6070 part_bytes_reg = tmp;
6076 mem = gen_rtx_MEM (QImode, dst);
6077 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6078 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6079 MEM_SCALAR_P (mem) = dst_scalar_p;
6080 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6087 /* Generate a memory reference for a half word, such that it will be loaded
6088 into the top 16 bits of the word. We can assume that the address is
6089 known to be alignable and of the form reg, or plus (reg, const). */
6092 arm_gen_rotated_half_load (rtx memref)
6094 HOST_WIDE_INT offset = 0;
6095 rtx base = XEXP (memref, 0);
6097 if (GET_CODE (base) == PLUS)
6099 offset = INTVAL (XEXP (base, 1));
6100 base = XEXP (base, 0);
6103 /* If we aren't allowed to generate unaligned addresses, then fail. */
6104 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6107 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6109 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6112 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6115 /* Select a dominance comparison mode if possible for a test of the general
6116 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6117 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6118 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6119 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6120 In all cases OP will be either EQ or NE, but we don't need to know which
6121 here. If we are unable to support a dominance comparison we return
6122 CC mode. This will then fail to match for the RTL expressions that
6123 generate this call. */
6125 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6127 enum rtx_code cond1, cond2;
6130 /* Currently we will probably get the wrong result if the individual
6131 comparisons are not simple. This also ensures that it is safe to
6132 reverse a comparison if necessary. */
6133 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6135 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6139 /* The if_then_else variant of this tests the second condition if the
6140 first passes, but is true if the first fails. Reverse the first
6141 condition to get a true "inclusive-or" expression. */
6142 if (cond_or == DOM_CC_NX_OR_Y)
6143 cond1 = reverse_condition (cond1);
6145 /* If the comparisons are not equal, and one doesn't dominate the other,
6146 then we can't do this. */
6148 && !comparison_dominates_p (cond1, cond2)
6149 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6154 enum rtx_code temp = cond1;
6162 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6167 case LE: return CC_DLEmode;
6168 case LEU: return CC_DLEUmode;
6169 case GE: return CC_DGEmode;
6170 case GEU: return CC_DGEUmode;
6177 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6186 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6195 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6204 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6212 /* The remaining cases only occur when both comparisons are the
6237 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6239 /* All floating point compares return CCFP if it is an equality
6240 comparison, and CCFPE otherwise. */
6241 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6261 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6270 /* A compare with a shifted operand. Because of canonicalization, the
6271 comparison will have to be swapped when we emit the assembler. */
6272 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6273 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6274 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6275 || GET_CODE (x) == ROTATERT))
6278 /* This is a special case that is used by combine to allow a
6279 comparison of a shifted byte load to be split into a zero-extend
6280 followed by a comparison of the shifted integer (only valid for
6281 equalities and unsigned inequalities). */
6282 if (GET_MODE (x) == SImode
6283 && GET_CODE (x) == ASHIFT
6284 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6285 && GET_CODE (XEXP (x, 0)) == SUBREG
6286 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6287 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6288 && (op == EQ || op == NE
6289 || op == GEU || op == GTU || op == LTU || op == LEU)
6290 && GET_CODE (y) == CONST_INT)
6293 /* A construct for a conditional compare, if the false arm contains
6294 0, then both conditions must be true, otherwise either condition
6295 must be true. Not all conditions are possible, so CCmode is
6296 returned if it can't be done. */
6297 if (GET_CODE (x) == IF_THEN_ELSE
6298 && (XEXP (x, 2) == const0_rtx
6299 || XEXP (x, 2) == const1_rtx)
6300 && COMPARISON_P (XEXP (x, 0))
6301 && COMPARISON_P (XEXP (x, 1)))
6302 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6303 INTVAL (XEXP (x, 2)));
6305 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6306 if (GET_CODE (x) == AND
6307 && COMPARISON_P (XEXP (x, 0))
6308 && COMPARISON_P (XEXP (x, 1)))
6309 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6312 if (GET_CODE (x) == IOR
6313 && COMPARISON_P (XEXP (x, 0))
6314 && COMPARISON_P (XEXP (x, 1)))
6315 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6318 /* An operation (on Thumb) where we want to test for a single bit.
6319 This is done by shifting that bit up into the top bit of a
6320 scratch register; we can then branch on the sign bit. */
6322 && GET_MODE (x) == SImode
6323 && (op == EQ || op == NE)
6324 && (GET_CODE (x) == ZERO_EXTRACT))
6327 /* An operation that sets the condition codes as a side-effect, the
6328 V flag is not set correctly, so we can only use comparisons where
6329 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6331 if (GET_MODE (x) == SImode
6333 && (op == EQ || op == NE || op == LT || op == GE)
6334 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6335 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6336 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6337 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6338 || GET_CODE (x) == LSHIFTRT
6339 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6340 || GET_CODE (x) == ROTATERT
6341 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6344 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6347 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6348 && GET_CODE (x) == PLUS
6349 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6355 /* X and Y are two things to compare using CODE. Emit the compare insn and
6356 return the rtx for register 0 in the proper mode. FP means this is a
6357 floating point compare: I don't think that it is needed on the arm. */
6359 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6361 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6362 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6364 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6365 gen_rtx_COMPARE (mode, x, y)));
6370 /* Generate a sequence of insns that will generate the correct return
6371 address mask depending on the physical architecture that the program
6374 arm_gen_return_addr_mask (void)
6376 rtx reg = gen_reg_rtx (Pmode);
6378 emit_insn (gen_return_addr_mask (reg));
6383 arm_reload_in_hi (rtx *operands)
6385 rtx ref = operands[1];
6387 HOST_WIDE_INT offset = 0;
6389 if (GET_CODE (ref) == SUBREG)
6391 offset = SUBREG_BYTE (ref);
6392 ref = SUBREG_REG (ref);
6395 if (GET_CODE (ref) == REG)
6397 /* We have a pseudo which has been spilt onto the stack; there
6398 are two cases here: the first where there is a simple
6399 stack-slot replacement and a second where the stack-slot is
6400 out of range, or is used as a subreg. */
6401 if (reg_equiv_mem[REGNO (ref)])
6403 ref = reg_equiv_mem[REGNO (ref)];
6404 base = find_replacement (&XEXP (ref, 0));
6407 /* The slot is out of range, or was dressed up in a SUBREG. */
6408 base = reg_equiv_address[REGNO (ref)];
6411 base = find_replacement (&XEXP (ref, 0));
6413 /* Handle the case where the address is too complex to be offset by 1. */
6414 if (GET_CODE (base) == MINUS
6415 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6417 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6419 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6422 else if (GET_CODE (base) == PLUS)
6424 /* The addend must be CONST_INT, or we would have dealt with it above. */
6425 HOST_WIDE_INT hi, lo;
6427 offset += INTVAL (XEXP (base, 1));
6428 base = XEXP (base, 0);
6430 /* Rework the address into a legal sequence of insns. */
6431 /* Valid range for lo is -4095 -> 4095 */
6434 : -((-offset) & 0xfff));
6436 /* Corner case, if lo is the max offset then we would be out of range
6437 once we have added the additional 1 below, so bump the msb into the
6438 pre-loading insn(s). */
6442 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6443 ^ (HOST_WIDE_INT) 0x80000000)
6444 - (HOST_WIDE_INT) 0x80000000);
6446 if (hi + lo != offset)
6451 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6453 /* Get the base address; addsi3 knows how to handle constants
6454 that require more than one insn. */
6455 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6461 /* Operands[2] may overlap operands[0] (though it won't overlap
6462 operands[1]), that's why we asked for a DImode reg -- so we can
6463 use the bit that does not overlap. */
6464 if (REGNO (operands[2]) == REGNO (operands[0]))
6465 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6467 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6469 emit_insn (gen_zero_extendqisi2 (scratch,
6470 gen_rtx_MEM (QImode,
6471 plus_constant (base,
6473 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6474 gen_rtx_MEM (QImode,
6475 plus_constant (base,
6477 if (!BYTES_BIG_ENDIAN)
6478 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6479 gen_rtx_IOR (SImode,
6482 gen_rtx_SUBREG (SImode, operands[0], 0),
6486 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6487 gen_rtx_IOR (SImode,
6488 gen_rtx_ASHIFT (SImode, scratch,
6490 gen_rtx_SUBREG (SImode, operands[0],
6494 /* Handle storing a half-word to memory during reload by synthesizing as two
6495 byte stores. Take care not to clobber the input values until after we
6496 have moved them somewhere safe. This code assumes that if the DImode
6497 scratch in operands[2] overlaps either the input value or output address
6498 in some way, then that value must die in this insn (we absolutely need
6499 two scratch registers for some corner cases). */
6501 arm_reload_out_hi (rtx *operands)
6503 rtx ref = operands[0];
6504 rtx outval = operands[1];
6506 HOST_WIDE_INT offset = 0;
6508 if (GET_CODE (ref) == SUBREG)
6510 offset = SUBREG_BYTE (ref);
6511 ref = SUBREG_REG (ref);
6514 if (GET_CODE (ref) == REG)
6516 /* We have a pseudo which has been spilt onto the stack; there
6517 are two cases here: the first where there is a simple
6518 stack-slot replacement and a second where the stack-slot is
6519 out of range, or is used as a subreg. */
6520 if (reg_equiv_mem[REGNO (ref)])
6522 ref = reg_equiv_mem[REGNO (ref)];
6523 base = find_replacement (&XEXP (ref, 0));
6526 /* The slot is out of range, or was dressed up in a SUBREG. */
6527 base = reg_equiv_address[REGNO (ref)];
6530 base = find_replacement (&XEXP (ref, 0));
6532 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6534 /* Handle the case where the address is too complex to be offset by 1. */
6535 if (GET_CODE (base) == MINUS
6536 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6538 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6540 /* Be careful not to destroy OUTVAL. */
6541 if (reg_overlap_mentioned_p (base_plus, outval))
6543 /* Updating base_plus might destroy outval, see if we can
6544 swap the scratch and base_plus. */
6545 if (!reg_overlap_mentioned_p (scratch, outval))
6548 scratch = base_plus;
6553 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6555 /* Be conservative and copy OUTVAL into the scratch now,
6556 this should only be necessary if outval is a subreg
6557 of something larger than a word. */
6558 /* XXX Might this clobber base? I can't see how it can,
6559 since scratch is known to overlap with OUTVAL, and
6560 must be wider than a word. */
6561 emit_insn (gen_movhi (scratch_hi, outval));
6562 outval = scratch_hi;
6566 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6569 else if (GET_CODE (base) == PLUS)
6571 /* The addend must be CONST_INT, or we would have dealt with it above. */
6572 HOST_WIDE_INT hi, lo;
6574 offset += INTVAL (XEXP (base, 1));
6575 base = XEXP (base, 0);
6577 /* Rework the address into a legal sequence of insns. */
6578 /* Valid range for lo is -4095 -> 4095 */
6581 : -((-offset) & 0xfff));
6583 /* Corner case, if lo is the max offset then we would be out of range
6584 once we have added the additional 1 below, so bump the msb into the
6585 pre-loading insn(s). */
6589 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6590 ^ (HOST_WIDE_INT) 0x80000000)
6591 - (HOST_WIDE_INT) 0x80000000);
6593 if (hi + lo != offset)
6598 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6600 /* Be careful not to destroy OUTVAL. */
6601 if (reg_overlap_mentioned_p (base_plus, outval))
6603 /* Updating base_plus might destroy outval, see if we
6604 can swap the scratch and base_plus. */
6605 if (!reg_overlap_mentioned_p (scratch, outval))
6608 scratch = base_plus;
6613 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6615 /* Be conservative and copy outval into scratch now,
6616 this should only be necessary if outval is a
6617 subreg of something larger than a word. */
6618 /* XXX Might this clobber base? I can't see how it
6619 can, since scratch is known to overlap with
6621 emit_insn (gen_movhi (scratch_hi, outval));
6622 outval = scratch_hi;
6626 /* Get the base address; addsi3 knows how to handle constants
6627 that require more than one insn. */
6628 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6634 if (BYTES_BIG_ENDIAN)
6636 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6637 plus_constant (base, offset + 1)),
6638 gen_lowpart (QImode, outval)));
6639 emit_insn (gen_lshrsi3 (scratch,
6640 gen_rtx_SUBREG (SImode, outval, 0),
6642 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6643 gen_lowpart (QImode, scratch)));
6647 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6648 gen_lowpart (QImode, outval)));
6649 emit_insn (gen_lshrsi3 (scratch,
6650 gen_rtx_SUBREG (SImode, outval, 0),
6652 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6653 plus_constant (base, offset + 1)),
6654 gen_lowpart (QImode, scratch)));
6658 /* Print a symbolic form of X to the debug file, F. */
6660 arm_print_value (FILE *f, rtx x)
6662 switch (GET_CODE (x))
6665 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6669 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6677 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6679 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6680 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6688 fprintf (f, "\"%s\"", XSTR (x, 0));
6692 fprintf (f, "`%s'", XSTR (x, 0));
6696 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6700 arm_print_value (f, XEXP (x, 0));
6704 arm_print_value (f, XEXP (x, 0));
6706 arm_print_value (f, XEXP (x, 1));
6714 fprintf (f, "????");
6719 /* Routines for manipulation of the constant pool. */
6721 /* Arm instructions cannot load a large constant directly into a
6722 register; they have to come from a pc relative load. The constant
6723 must therefore be placed in the addressable range of the pc
6724 relative load. Depending on the precise pc relative load
6725 instruction the range is somewhere between 256 bytes and 4k. This
6726 means that we often have to dump a constant inside a function, and
6727 generate code to branch around it.
6729 It is important to minimize this, since the branches will slow
6730 things down and make the code larger.
6732 Normally we can hide the table after an existing unconditional
6733 branch so that there is no interruption of the flow, but in the
6734 worst case the code looks like this:
6752 We fix this by performing a scan after scheduling, which notices
6753 which instructions need to have their operands fetched from the
6754 constant table and builds the table.
6756 The algorithm starts by building a table of all the constants that
6757 need fixing up and all the natural barriers in the function (places
6758 where a constant table can be dropped without breaking the flow).
6759 For each fixup we note how far the pc-relative replacement will be
6760 able to reach and the offset of the instruction into the function.
6762 Having built the table we then group the fixes together to form
6763 tables that are as large as possible (subject to addressing
6764 constraints) and emit each table of constants after the last
6765 barrier that is within range of all the instructions in the group.
6766 If a group does not contain a barrier, then we forcibly create one
6767 by inserting a jump instruction into the flow. Once the table has
6768 been inserted, the insns are then modified to reference the
6769 relevant entry in the pool.
6771 Possible enhancements to the algorithm (not implemented) are:
6773 1) For some processors and object formats, there may be benefit in
6774 aligning the pools to the start of cache lines; this alignment
6775 would need to be taken into account when calculating addressability
6778 /* These typedefs are located at the start of this file, so that
6779 they can be used in the prototypes there. This comment is to
6780 remind readers of that fact so that the following structures
6781 can be understood more easily.
6783 typedef struct minipool_node Mnode;
6784 typedef struct minipool_fixup Mfix; */
6786 struct minipool_node
6788 /* Doubly linked chain of entries. */
6791 /* The maximum offset into the code that this entry can be placed. While
6792 pushing fixes for forward references, all entries are sorted in order
6793 of increasing max_address. */
6794 HOST_WIDE_INT max_address;
6795 /* Similarly for an entry inserted for a backwards ref. */
6796 HOST_WIDE_INT min_address;
6797 /* The number of fixes referencing this entry. This can become zero
6798 if we "unpush" an entry. In this case we ignore the entry when we
6799 come to emit the code. */
6801 /* The offset from the start of the minipool. */
6802 HOST_WIDE_INT offset;
6803 /* The value in table. */
6805 /* The mode of value. */
6806 enum machine_mode mode;
6807 /* The size of the value. With iWMMXt enabled
6808 sizes > 4 also imply an alignment of 8-bytes. */
6812 struct minipool_fixup
6816 HOST_WIDE_INT address;
6818 enum machine_mode mode;
6822 HOST_WIDE_INT forwards;
6823 HOST_WIDE_INT backwards;
6826 /* Fixes less than a word need padding out to a word boundary. */
6827 #define MINIPOOL_FIX_SIZE(mode) \
6828 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6830 static Mnode * minipool_vector_head;
6831 static Mnode * minipool_vector_tail;
6832 static rtx minipool_vector_label;
6834 /* The linked list of all minipool fixes required for this function. */
6835 Mfix * minipool_fix_head;
6836 Mfix * minipool_fix_tail;
6837 /* The fix entry for the current minipool, once it has been placed. */
6838 Mfix * minipool_barrier;
6840 /* Determines if INSN is the start of a jump table. Returns the end
6841 of the TABLE or NULL_RTX. */
6843 is_jump_table (rtx insn)
6847 if (GET_CODE (insn) == JUMP_INSN
6848 && JUMP_LABEL (insn) != NULL
6849 && ((table = next_real_insn (JUMP_LABEL (insn)))
6850 == next_real_insn (insn))
6852 && GET_CODE (table) == JUMP_INSN
6853 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6854 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6860 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6861 #define JUMP_TABLES_IN_TEXT_SECTION 0
6864 static HOST_WIDE_INT
6865 get_jump_table_size (rtx insn)
6867 /* ADDR_VECs only take room if read-only data does into the text
6869 if (JUMP_TABLES_IN_TEXT_SECTION
6870 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6875 rtx body = PATTERN (insn);
6876 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6878 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6884 /* Move a minipool fix MP from its current location to before MAX_MP.
6885 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6886 constraints may need updating. */
6888 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6889 HOST_WIDE_INT max_address)
6891 /* This should never be true and the code below assumes these are
6898 if (max_address < mp->max_address)
6899 mp->max_address = max_address;
6903 if (max_address > max_mp->max_address - mp->fix_size)
6904 mp->max_address = max_mp->max_address - mp->fix_size;
6906 mp->max_address = max_address;
6908 /* Unlink MP from its current position. Since max_mp is non-null,
6909 mp->prev must be non-null. */
6910 mp->prev->next = mp->next;
6911 if (mp->next != NULL)
6912 mp->next->prev = mp->prev;
6914 minipool_vector_tail = mp->prev;
6916 /* Re-insert it before MAX_MP. */
6918 mp->prev = max_mp->prev;
6921 if (mp->prev != NULL)
6922 mp->prev->next = mp;
6924 minipool_vector_head = mp;
6927 /* Save the new entry. */
6930 /* Scan over the preceding entries and adjust their addresses as
6932 while (mp->prev != NULL
6933 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6935 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6942 /* Add a constant to the minipool for a forward reference. Returns the
6943 node added or NULL if the constant will not fit in this pool. */
6945 add_minipool_forward_ref (Mfix *fix)
6947 /* If set, max_mp is the first pool_entry that has a lower
6948 constraint than the one we are trying to add. */
6949 Mnode * max_mp = NULL;
6950 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6953 /* If this fix's address is greater than the address of the first
6954 entry, then we can't put the fix in this pool. We subtract the
6955 size of the current fix to ensure that if the table is fully
6956 packed we still have enough room to insert this value by suffling
6957 the other fixes forwards. */
6958 if (minipool_vector_head &&
6959 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6962 /* Scan the pool to see if a constant with the same value has
6963 already been added. While we are doing this, also note the
6964 location where we must insert the constant if it doesn't already
6966 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6968 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6969 && fix->mode == mp->mode
6970 && (GET_CODE (fix->value) != CODE_LABEL
6971 || (CODE_LABEL_NUMBER (fix->value)
6972 == CODE_LABEL_NUMBER (mp->value)))
6973 && rtx_equal_p (fix->value, mp->value))
6975 /* More than one fix references this entry. */
6977 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6980 /* Note the insertion point if necessary. */
6982 && mp->max_address > max_address)
6985 /* If we are inserting an 8-bytes aligned quantity and
6986 we have not already found an insertion point, then
6987 make sure that all such 8-byte aligned quantities are
6988 placed at the start of the pool. */
6989 if (ARM_DOUBLEWORD_ALIGN
6991 && fix->fix_size == 8
6992 && mp->fix_size != 8)
6995 max_address = mp->max_address;
6999 /* The value is not currently in the minipool, so we need to create
7000 a new entry for it. If MAX_MP is NULL, the entry will be put on
7001 the end of the list since the placement is less constrained than
7002 any existing entry. Otherwise, we insert the new fix before
7003 MAX_MP and, if necessary, adjust the constraints on the other
7005 mp = xmalloc (sizeof (* mp));
7006 mp->fix_size = fix->fix_size;
7007 mp->mode = fix->mode;
7008 mp->value = fix->value;
7010 /* Not yet required for a backwards ref. */
7011 mp->min_address = -65536;
7015 mp->max_address = max_address;
7017 mp->prev = minipool_vector_tail;
7019 if (mp->prev == NULL)
7021 minipool_vector_head = mp;
7022 minipool_vector_label = gen_label_rtx ();
7025 mp->prev->next = mp;
7027 minipool_vector_tail = mp;
7031 if (max_address > max_mp->max_address - mp->fix_size)
7032 mp->max_address = max_mp->max_address - mp->fix_size;
7034 mp->max_address = max_address;
7037 mp->prev = max_mp->prev;
7039 if (mp->prev != NULL)
7040 mp->prev->next = mp;
7042 minipool_vector_head = mp;
7045 /* Save the new entry. */
7048 /* Scan over the preceding entries and adjust their addresses as
7050 while (mp->prev != NULL
7051 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7053 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7061 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7062 HOST_WIDE_INT min_address)
7064 HOST_WIDE_INT offset;
7066 /* This should never be true, and the code below assumes these are
7073 if (min_address > mp->min_address)
7074 mp->min_address = min_address;
7078 /* We will adjust this below if it is too loose. */
7079 mp->min_address = min_address;
7081 /* Unlink MP from its current position. Since min_mp is non-null,
7082 mp->next must be non-null. */
7083 mp->next->prev = mp->prev;
7084 if (mp->prev != NULL)
7085 mp->prev->next = mp->next;
7087 minipool_vector_head = mp->next;
7089 /* Reinsert it after MIN_MP. */
7091 mp->next = min_mp->next;
7093 if (mp->next != NULL)
7094 mp->next->prev = mp;
7096 minipool_vector_tail = mp;
7102 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7104 mp->offset = offset;
7105 if (mp->refcount > 0)
7106 offset += mp->fix_size;
7108 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7109 mp->next->min_address = mp->min_address + mp->fix_size;
7115 /* Add a constant to the minipool for a backward reference. Returns the
7116 node added or NULL if the constant will not fit in this pool.
7118 Note that the code for insertion for a backwards reference can be
7119 somewhat confusing because the calculated offsets for each fix do
7120 not take into account the size of the pool (which is still under
7123 add_minipool_backward_ref (Mfix *fix)
7125 /* If set, min_mp is the last pool_entry that has a lower constraint
7126 than the one we are trying to add. */
7127 Mnode *min_mp = NULL;
7128 /* This can be negative, since it is only a constraint. */
7129 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7132 /* If we can't reach the current pool from this insn, or if we can't
7133 insert this entry at the end of the pool without pushing other
7134 fixes out of range, then we don't try. This ensures that we
7135 can't fail later on. */
7136 if (min_address >= minipool_barrier->address
7137 || (minipool_vector_tail->min_address + fix->fix_size
7138 >= minipool_barrier->address))
7141 /* Scan the pool to see if a constant with the same value has
7142 already been added. While we are doing this, also note the
7143 location where we must insert the constant if it doesn't already
7145 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7147 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7148 && fix->mode == mp->mode
7149 && (GET_CODE (fix->value) != CODE_LABEL
7150 || (CODE_LABEL_NUMBER (fix->value)
7151 == CODE_LABEL_NUMBER (mp->value)))
7152 && rtx_equal_p (fix->value, mp->value)
7153 /* Check that there is enough slack to move this entry to the
7154 end of the table (this is conservative). */
7156 > (minipool_barrier->address
7157 + minipool_vector_tail->offset
7158 + minipool_vector_tail->fix_size)))
7161 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7165 mp->min_address += fix->fix_size;
7168 /* Note the insertion point if necessary. */
7169 if (mp->min_address < min_address)
7171 /* For now, we do not allow the insertion of 8-byte alignment
7172 requiring nodes anywhere but at the start of the pool. */
7173 if (ARM_DOUBLEWORD_ALIGN
7174 && fix->fix_size == 8 && mp->fix_size != 8)
7179 else if (mp->max_address
7180 < minipool_barrier->address + mp->offset + fix->fix_size)
7182 /* Inserting before this entry would push the fix beyond
7183 its maximum address (which can happen if we have
7184 re-located a forwards fix); force the new fix to come
7187 min_address = mp->min_address + fix->fix_size;
7189 /* If we are inserting an 8-bytes aligned quantity and
7190 we have not already found an insertion point, then
7191 make sure that all such 8-byte aligned quantities are
7192 placed at the start of the pool. */
7193 else if (ARM_DOUBLEWORD_ALIGN
7195 && fix->fix_size == 8
7196 && mp->fix_size < 8)
7199 min_address = mp->min_address + fix->fix_size;
7204 /* We need to create a new entry. */
7205 mp = xmalloc (sizeof (* mp));
7206 mp->fix_size = fix->fix_size;
7207 mp->mode = fix->mode;
7208 mp->value = fix->value;
7210 mp->max_address = minipool_barrier->address + 65536;
7212 mp->min_address = min_address;
7217 mp->next = minipool_vector_head;
7219 if (mp->next == NULL)
7221 minipool_vector_tail = mp;
7222 minipool_vector_label = gen_label_rtx ();
7225 mp->next->prev = mp;
7227 minipool_vector_head = mp;
7231 mp->next = min_mp->next;
7235 if (mp->next != NULL)
7236 mp->next->prev = mp;
7238 minipool_vector_tail = mp;
7241 /* Save the new entry. */
7249 /* Scan over the following entries and adjust their offsets. */
7250 while (mp->next != NULL)
7252 if (mp->next->min_address < mp->min_address + mp->fix_size)
7253 mp->next->min_address = mp->min_address + mp->fix_size;
7256 mp->next->offset = mp->offset + mp->fix_size;
7258 mp->next->offset = mp->offset;
7267 assign_minipool_offsets (Mfix *barrier)
7269 HOST_WIDE_INT offset = 0;
7272 minipool_barrier = barrier;
7274 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7276 mp->offset = offset;
7278 if (mp->refcount > 0)
7279 offset += mp->fix_size;
7283 /* Output the literal table */
7285 dump_minipool (rtx scan)
7291 if (ARM_DOUBLEWORD_ALIGN)
7292 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7293 if (mp->refcount > 0 && mp->fix_size == 8)
7301 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7302 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7304 scan = emit_label_after (gen_label_rtx (), scan);
7305 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7306 scan = emit_label_after (minipool_vector_label, scan);
7308 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7310 if (mp->refcount > 0)
7315 ";; Offset %u, min %ld, max %ld ",
7316 (unsigned) mp->offset, (unsigned long) mp->min_address,
7317 (unsigned long) mp->max_address);
7318 arm_print_value (dump_file, mp->value);
7319 fputc ('\n', dump_file);
7322 switch (mp->fix_size)
7324 #ifdef HAVE_consttable_1
7326 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7330 #ifdef HAVE_consttable_2
7332 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7336 #ifdef HAVE_consttable_4
7338 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7342 #ifdef HAVE_consttable_8
7344 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7358 minipool_vector_head = minipool_vector_tail = NULL;
7359 scan = emit_insn_after (gen_consttable_end (), scan);
7360 scan = emit_barrier_after (scan);
7363 /* Return the cost of forcibly inserting a barrier after INSN. */
7365 arm_barrier_cost (rtx insn)
7367 /* Basing the location of the pool on the loop depth is preferable,
7368 but at the moment, the basic block information seems to be
7369 corrupt by this stage of the compilation. */
7371 rtx next = next_nonnote_insn (insn);
7373 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7376 switch (GET_CODE (insn))
7379 /* It will always be better to place the table before the label, rather
7388 return base_cost - 10;
7391 return base_cost + 10;
7395 /* Find the best place in the insn stream in the range
7396 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7397 Create the barrier by inserting a jump and add a new fix entry for
7400 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7402 HOST_WIDE_INT count = 0;
7404 rtx from = fix->insn;
7405 rtx selected = from;
7407 HOST_WIDE_INT selected_address;
7409 HOST_WIDE_INT max_count = max_address - fix->address;
7410 rtx label = gen_label_rtx ();
7412 selected_cost = arm_barrier_cost (from);
7413 selected_address = fix->address;
7415 while (from && count < max_count)
7420 /* This code shouldn't have been called if there was a natural barrier
7422 if (GET_CODE (from) == BARRIER)
7425 /* Count the length of this insn. */
7426 count += get_attr_length (from);
7428 /* If there is a jump table, add its length. */
7429 tmp = is_jump_table (from);
7432 count += get_jump_table_size (tmp);
7434 /* Jump tables aren't in a basic block, so base the cost on
7435 the dispatch insn. If we select this location, we will
7436 still put the pool after the table. */
7437 new_cost = arm_barrier_cost (from);
7439 if (count < max_count && new_cost <= selected_cost)
7442 selected_cost = new_cost;
7443 selected_address = fix->address + count;
7446 /* Continue after the dispatch table. */
7447 from = NEXT_INSN (tmp);
7451 new_cost = arm_barrier_cost (from);
7453 if (count < max_count && new_cost <= selected_cost)
7456 selected_cost = new_cost;
7457 selected_address = fix->address + count;
7460 from = NEXT_INSN (from);
7463 /* Create a new JUMP_INSN that branches around a barrier. */
7464 from = emit_jump_insn_after (gen_jump (label), selected);
7465 JUMP_LABEL (from) = label;
7466 barrier = emit_barrier_after (from);
7467 emit_label_after (label, barrier);
7469 /* Create a minipool barrier entry for the new barrier. */
7470 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7471 new_fix->insn = barrier;
7472 new_fix->address = selected_address;
7473 new_fix->next = fix->next;
7474 fix->next = new_fix;
7479 /* Record that there is a natural barrier in the insn stream at
7482 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7484 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7487 fix->address = address;
7490 if (minipool_fix_head != NULL)
7491 minipool_fix_tail->next = fix;
7493 minipool_fix_head = fix;
7495 minipool_fix_tail = fix;
7498 /* Record INSN, which will need fixing up to load a value from the
7499 minipool. ADDRESS is the offset of the insn since the start of the
7500 function; LOC is a pointer to the part of the insn which requires
7501 fixing; VALUE is the constant that must be loaded, which is of type
7504 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7505 enum machine_mode mode, rtx value)
7507 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7509 #ifdef AOF_ASSEMBLER
7510 /* PIC symbol references need to be converted into offsets into the
7512 /* XXX This shouldn't be done here. */
7513 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7514 value = aof_pic_entry (value);
7515 #endif /* AOF_ASSEMBLER */
7518 fix->address = address;
7521 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7523 fix->forwards = get_attr_pool_range (insn);
7524 fix->backwards = get_attr_neg_pool_range (insn);
7525 fix->minipool = NULL;
7527 /* If an insn doesn't have a range defined for it, then it isn't
7528 expecting to be reworked by this code. Better to abort now than
7529 to generate duff assembly code. */
7530 if (fix->forwards == 0 && fix->backwards == 0)
7533 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7534 So there might be an empty word before the start of the pool.
7535 Hence we reduce the forward range by 4 to allow for this
7537 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7543 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7544 GET_MODE_NAME (mode),
7545 INSN_UID (insn), (unsigned long) address,
7546 -1 * (long)fix->backwards, (long)fix->forwards);
7547 arm_print_value (dump_file, fix->value);
7548 fprintf (dump_file, "\n");
7551 /* Add it to the chain of fixes. */
7554 if (minipool_fix_head != NULL)
7555 minipool_fix_tail->next = fix;
7557 minipool_fix_head = fix;
7559 minipool_fix_tail = fix;
7562 /* Scan INSN and note any of its operands that need fixing.
7563 If DO_PUSHES is false we do not actually push any of the fixups
7564 needed. The function returns TRUE is any fixups were needed/pushed.
7565 This is used by arm_memory_load_p() which needs to know about loads
7566 of constants that will be converted into minipool loads. */
7568 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7570 bool result = false;
7573 extract_insn (insn);
7575 if (!constrain_operands (1))
7576 fatal_insn_not_found (insn);
7578 if (recog_data.n_alternatives == 0)
7581 /* Fill in recog_op_alt with information about the constraints of this insn. */
7582 preprocess_constraints ();
7584 for (opno = 0; opno < recog_data.n_operands; opno++)
7586 /* Things we need to fix can only occur in inputs. */
7587 if (recog_data.operand_type[opno] != OP_IN)
7590 /* If this alternative is a memory reference, then any mention
7591 of constants in this alternative is really to fool reload
7592 into allowing us to accept one there. We need to fix them up
7593 now so that we output the right code. */
7594 if (recog_op_alt[opno][which_alternative].memory_ok)
7596 rtx op = recog_data.operand[opno];
7598 if (CONSTANT_P (op))
7601 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7602 recog_data.operand_mode[opno], op);
7605 else if (GET_CODE (op) == MEM
7606 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7607 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7611 rtx cop = avoid_constant_pool_reference (op);
7613 /* Casting the address of something to a mode narrower
7614 than a word can cause avoid_constant_pool_reference()
7615 to return the pool reference itself. That's no good to
7616 us here. Lets just hope that we can use the
7617 constant pool value directly. */
7619 cop = get_pool_constant (XEXP (op, 0));
7621 push_minipool_fix (insn, address,
7622 recog_data.operand_loc[opno],
7623 recog_data.operand_mode[opno], cop);
7634 /* Gcc puts the pool in the wrong place for ARM, since we can only
7635 load addresses a limited distance around the pc. We do some
7636 special munging to move the constant pool values to the correct
7637 point in the code. */
7642 HOST_WIDE_INT address = 0;
7645 minipool_fix_head = minipool_fix_tail = NULL;
7647 /* The first insn must always be a note, or the code below won't
7648 scan it properly. */
7649 insn = get_insns ();
7650 if (GET_CODE (insn) != NOTE)
7653 /* Scan all the insns and record the operands that will need fixing. */
7654 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7656 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7657 && (arm_cirrus_insn_p (insn)
7658 || GET_CODE (insn) == JUMP_INSN
7659 || arm_memory_load_p (insn)))
7660 cirrus_reorg (insn);
7662 if (GET_CODE (insn) == BARRIER)
7663 push_minipool_barrier (insn, address);
7664 else if (INSN_P (insn))
7668 note_invalid_constants (insn, address, true);
7669 address += get_attr_length (insn);
7671 /* If the insn is a vector jump, add the size of the table
7672 and skip the table. */
7673 if ((table = is_jump_table (insn)) != NULL)
7675 address += get_jump_table_size (table);
7681 fix = minipool_fix_head;
7683 /* Now scan the fixups and perform the required changes. */
7688 Mfix * last_added_fix;
7689 Mfix * last_barrier = NULL;
7692 /* Skip any further barriers before the next fix. */
7693 while (fix && GET_CODE (fix->insn) == BARRIER)
7696 /* No more fixes. */
7700 last_added_fix = NULL;
7702 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7704 if (GET_CODE (ftmp->insn) == BARRIER)
7706 if (ftmp->address >= minipool_vector_head->max_address)
7709 last_barrier = ftmp;
7711 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7714 last_added_fix = ftmp; /* Keep track of the last fix added. */
7717 /* If we found a barrier, drop back to that; any fixes that we
7718 could have reached but come after the barrier will now go in
7719 the next mini-pool. */
7720 if (last_barrier != NULL)
7722 /* Reduce the refcount for those fixes that won't go into this
7724 for (fdel = last_barrier->next;
7725 fdel && fdel != ftmp;
7728 fdel->minipool->refcount--;
7729 fdel->minipool = NULL;
7732 ftmp = last_barrier;
7736 /* ftmp is first fix that we can't fit into this pool and
7737 there no natural barriers that we could use. Insert a
7738 new barrier in the code somewhere between the previous
7739 fix and this one, and arrange to jump around it. */
7740 HOST_WIDE_INT max_address;
7742 /* The last item on the list of fixes must be a barrier, so
7743 we can never run off the end of the list of fixes without
7744 last_barrier being set. */
7748 max_address = minipool_vector_head->max_address;
7749 /* Check that there isn't another fix that is in range that
7750 we couldn't fit into this pool because the pool was
7751 already too large: we need to put the pool before such an
7753 if (ftmp->address < max_address)
7754 max_address = ftmp->address;
7756 last_barrier = create_fix_barrier (last_added_fix, max_address);
7759 assign_minipool_offsets (last_barrier);
7763 if (GET_CODE (ftmp->insn) != BARRIER
7764 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7771 /* Scan over the fixes we have identified for this pool, fixing them
7772 up and adding the constants to the pool itself. */
7773 for (this_fix = fix; this_fix && ftmp != this_fix;
7774 this_fix = this_fix->next)
7775 if (GET_CODE (this_fix->insn) != BARRIER)
7778 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7779 minipool_vector_label),
7780 this_fix->minipool->offset);
7781 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7784 dump_minipool (last_barrier->insn);
7788 /* From now on we must synthesize any constants that we can't handle
7789 directly. This can happen if the RTL gets split during final
7790 instruction generation. */
7791 after_arm_reorg = 1;
7793 /* Free the minipool memory. */
7794 obstack_free (&minipool_obstack, minipool_startobj);
7797 /* Routines to output assembly language. */
7799 /* If the rtx is the correct value then return the string of the number.
7800 In this way we can ensure that valid double constants are generated even
7801 when cross compiling. */
7803 fp_immediate_constant (rtx x)
7808 if (!fp_consts_inited)
7811 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7812 for (i = 0; i < 8; i++)
7813 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7814 return strings_fp[i];
7819 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7821 fp_const_from_val (REAL_VALUE_TYPE *r)
7825 if (!fp_consts_inited)
7828 for (i = 0; i < 8; i++)
7829 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7830 return strings_fp[i];
7835 /* Output the operands of a LDM/STM instruction to STREAM.
7836 MASK is the ARM register set mask of which only bits 0-15 are important.
7837 REG is the base register, either the frame pointer or the stack pointer,
7838 INSTR is the possibly suffixed load or store instruction. */
7840 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7843 int not_first = FALSE;
7845 fputc ('\t', stream);
7846 asm_fprintf (stream, instr, reg);
7847 fputs (", {", stream);
7849 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7850 if (mask & (1 << i))
7853 fprintf (stream, ", ");
7855 asm_fprintf (stream, "%r", i);
7859 fprintf (stream, "}\n");
7863 /* Output a FLDMX instruction to STREAM.
7864 BASE if the register containing the address.
7865 REG and COUNT specify the register range.
7866 Extra registers may be added to avoid hardware bugs. */
7869 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7873 /* Workaround ARM10 VFPr1 bug. */
7874 if (count == 2 && !arm_arch6)
7881 fputc ('\t', stream);
7882 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7884 for (i = reg; i < reg + count; i++)
7887 fputs (", ", stream);
7888 asm_fprintf (stream, "d%d", i);
7890 fputs ("}\n", stream);
7895 /* Output the assembly for a store multiple. */
7898 vfp_output_fstmx (rtx * operands)
7905 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7906 p = strlen (pattern);
7908 if (GET_CODE (operands[1]) != REG)
7911 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7912 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7914 p += sprintf (&pattern[p], ", d%d", base + i);
7916 strcpy (&pattern[p], "}");
7918 output_asm_insn (pattern, operands);
7923 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7924 number of bytes pushed. */
7927 vfp_emit_fstmx (int base_reg, int count)
7934 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7935 register pairs are stored by a store multiple insn. We avoid this
7936 by pushing an extra pair. */
7937 if (count == 2 && !arm_arch6)
7939 if (base_reg == LAST_VFP_REGNUM - 3)
7944 /* ??? The frame layout is implementation defined. We describe
7945 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7946 We really need some way of representing the whole block so that the
7947 unwinder can figure it out at runtime. */
7948 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7949 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7951 reg = gen_rtx_REG (DFmode, base_reg);
7955 = gen_rtx_SET (VOIDmode,
7956 gen_rtx_MEM (BLKmode,
7957 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7958 gen_rtx_UNSPEC (BLKmode,
7962 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7963 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7964 GEN_INT (-(count * 8 + 4))));
7965 RTX_FRAME_RELATED_P (tmp) = 1;
7966 XVECEXP (dwarf, 0, 0) = tmp;
7968 tmp = gen_rtx_SET (VOIDmode,
7969 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7971 RTX_FRAME_RELATED_P (tmp) = 1;
7972 XVECEXP (dwarf, 0, 1) = tmp;
7974 for (i = 1; i < count; i++)
7976 reg = gen_rtx_REG (DFmode, base_reg);
7978 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7980 tmp = gen_rtx_SET (VOIDmode,
7981 gen_rtx_MEM (DFmode,
7982 gen_rtx_PLUS (SImode,
7986 RTX_FRAME_RELATED_P (tmp) = 1;
7987 XVECEXP (dwarf, 0, i + 1) = tmp;
7990 par = emit_insn (par);
7991 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7993 RTX_FRAME_RELATED_P (par) = 1;
7995 return count * 8 + 4;
7999 /* Output a 'call' insn. */
8001 output_call (rtx *operands)
8003 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8005 if (REGNO (operands[0]) == LR_REGNUM)
8007 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8008 output_asm_insn ("mov%?\t%0, %|lr", operands);
8011 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8013 if (TARGET_INTERWORK)
8014 output_asm_insn ("bx%?\t%0", operands);
8016 output_asm_insn ("mov%?\t%|pc, %0", operands);
8021 /* Output a 'call' insn that is a reference in memory. */
8023 output_call_mem (rtx *operands)
8025 if (TARGET_INTERWORK)
8027 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8028 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8029 output_asm_insn ("bx%?\t%|ip", operands);
8031 else if (regno_use_in (LR_REGNUM, operands[0]))
8033 /* LR is used in the memory address. We load the address in the
8034 first instruction. It's safe to use IP as the target of the
8035 load since the call will kill it anyway. */
8036 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8037 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8038 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8042 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8043 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8050 /* Output a move from arm registers to an fpa registers.
8051 OPERANDS[0] is an fpa register.
8052 OPERANDS[1] is the first registers of an arm register pair. */
8054 output_mov_long_double_fpa_from_arm (rtx *operands)
8056 int arm_reg0 = REGNO (operands[1]);
8059 if (arm_reg0 == IP_REGNUM)
8062 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8063 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8064 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8066 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8067 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8072 /* Output a move from an fpa register to arm registers.
8073 OPERANDS[0] is the first registers of an arm register pair.
8074 OPERANDS[1] is an fpa register. */
8076 output_mov_long_double_arm_from_fpa (rtx *operands)
8078 int arm_reg0 = REGNO (operands[0]);
8081 if (arm_reg0 == IP_REGNUM)
8084 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8085 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8086 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8088 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8089 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8093 /* Output a move from arm registers to arm registers of a long double
8094 OPERANDS[0] is the destination.
8095 OPERANDS[1] is the source. */
8097 output_mov_long_double_arm_from_arm (rtx *operands)
8099 /* We have to be careful here because the two might overlap. */
8100 int dest_start = REGNO (operands[0]);
8101 int src_start = REGNO (operands[1]);
8105 if (dest_start < src_start)
8107 for (i = 0; i < 3; i++)
8109 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8110 ops[1] = gen_rtx_REG (SImode, src_start + i);
8111 output_asm_insn ("mov%?\t%0, %1", ops);
8116 for (i = 2; i >= 0; i--)
8118 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8119 ops[1] = gen_rtx_REG (SImode, src_start + i);
8120 output_asm_insn ("mov%?\t%0, %1", ops);
8128 /* Output a move from arm registers to an fpa registers.
8129 OPERANDS[0] is an fpa register.
8130 OPERANDS[1] is the first registers of an arm register pair. */
8132 output_mov_double_fpa_from_arm (rtx *operands)
8134 int arm_reg0 = REGNO (operands[1]);
8137 if (arm_reg0 == IP_REGNUM)
8140 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8141 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8142 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8143 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8147 /* Output a move from an fpa register to arm registers.
8148 OPERANDS[0] is the first registers of an arm register pair.
8149 OPERANDS[1] is an fpa register. */
8151 output_mov_double_arm_from_fpa (rtx *operands)
8153 int arm_reg0 = REGNO (operands[0]);
8156 if (arm_reg0 == IP_REGNUM)
8159 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8160 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8161 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8162 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8166 /* Output a move between double words.
8167 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8168 or MEM<-REG and all MEMs must be offsettable addresses. */
8170 output_move_double (rtx *operands)
8172 enum rtx_code code0 = GET_CODE (operands[0]);
8173 enum rtx_code code1 = GET_CODE (operands[1]);
8178 int reg0 = REGNO (operands[0]);
8180 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8184 int reg1 = REGNO (operands[1]);
8185 if (reg1 == IP_REGNUM)
8188 /* Ensure the second source is not overwritten. */
8189 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8190 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8192 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8194 else if (code1 == CONST_VECTOR)
8196 HOST_WIDE_INT hint = 0;
8198 switch (GET_MODE (operands[1]))
8201 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8202 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8206 if (BYTES_BIG_ENDIAN)
8208 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8210 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8214 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8216 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8219 otherops[1] = GEN_INT (hint);
8222 if (BYTES_BIG_ENDIAN)
8224 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8226 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8230 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8232 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8235 operands[1] = GEN_INT (hint);
8239 if (BYTES_BIG_ENDIAN)
8241 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8243 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8245 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8247 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8251 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8253 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8255 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8257 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8260 otherops[1] = GEN_INT (hint);
8263 if (BYTES_BIG_ENDIAN)
8265 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8267 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8269 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8271 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8275 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8277 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8279 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8281 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8284 operands[1] = GEN_INT (hint);
8290 output_mov_immediate (operands);
8291 output_mov_immediate (otherops);
8293 else if (code1 == CONST_DOUBLE)
8295 if (GET_MODE (operands[1]) == DFmode)
8300 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8301 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8302 otherops[1] = GEN_INT (l[1]);
8303 operands[1] = GEN_INT (l[0]);
8305 else if (GET_MODE (operands[1]) != VOIDmode)
8307 else if (WORDS_BIG_ENDIAN)
8309 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8310 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8314 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8315 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8318 output_mov_immediate (operands);
8319 output_mov_immediate (otherops);
8321 else if (code1 == CONST_INT)
8323 #if HOST_BITS_PER_WIDE_INT > 32
8324 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8325 what the upper word is. */
8326 if (WORDS_BIG_ENDIAN)
8328 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8329 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8333 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8334 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8337 /* Sign extend the intval into the high-order word. */
8338 if (WORDS_BIG_ENDIAN)
8340 otherops[1] = operands[1];
8341 operands[1] = (INTVAL (operands[1]) < 0
8342 ? constm1_rtx : const0_rtx);
8345 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8347 output_mov_immediate (otherops);
8348 output_mov_immediate (operands);
8350 else if (code1 == MEM)
8352 switch (GET_CODE (XEXP (operands[1], 0)))
8355 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8360 abort (); /* Should never happen now. */
8361 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8365 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8369 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8374 abort (); /* Should never happen now. */
8375 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8380 otherops[0] = operands[0];
8381 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8382 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8384 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8386 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8388 /* Registers overlap so split out the increment. */
8389 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8390 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8393 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8397 /* We only allow constant increments, so this is safe. */
8398 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8404 output_asm_insn ("adr%?\t%0, %1", operands);
8405 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8409 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8410 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8412 otherops[0] = operands[0];
8413 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8414 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8416 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8418 if (GET_CODE (otherops[2]) == CONST_INT)
8420 switch ((int) INTVAL (otherops[2]))
8423 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8426 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8429 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8434 && (GET_CODE (otherops[2]) == REG
8435 || (GET_CODE (otherops[2]) == CONST_INT
8436 && INTVAL (otherops[2]) > -256
8437 && INTVAL (otherops[2]) < 256)))
8439 if (reg_overlap_mentioned_p (otherops[0],
8442 /* Swap base and index registers over to
8443 avoid a conflict. */
8444 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8445 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8448 /* If both registers conflict, it will usually
8449 have been fixed by a splitter. */
8450 if (reg_overlap_mentioned_p (otherops[0],
8453 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8454 output_asm_insn ("ldr%?d\t%0, [%1]",
8460 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8465 if (GET_CODE (otherops[2]) == CONST_INT)
8467 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8468 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8470 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8473 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8476 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8478 return "ldm%?ia\t%0, %M0";
8482 otherops[1] = adjust_address (operands[1], SImode, 4);
8483 /* Take care of overlapping base/data reg. */
8484 if (reg_mentioned_p (operands[0], operands[1]))
8486 output_asm_insn ("ldr%?\t%0, %1", otherops);
8487 output_asm_insn ("ldr%?\t%0, %1", operands);
8491 output_asm_insn ("ldr%?\t%0, %1", operands);
8492 output_asm_insn ("ldr%?\t%0, %1", otherops);
8498 abort (); /* Constraints should prevent this. */
8500 else if (code0 == MEM && code1 == REG)
8502 if (REGNO (operands[1]) == IP_REGNUM)
8505 switch (GET_CODE (XEXP (operands[0], 0)))
8508 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8513 abort (); /* Should never happen now. */
8514 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8518 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8522 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8527 abort (); /* Should never happen now. */
8528 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8533 otherops[0] = operands[1];
8534 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8535 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8537 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8538 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8540 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8544 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8545 if (GET_CODE (otherops[2]) == CONST_INT)
8547 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8550 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8554 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8558 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8563 && (GET_CODE (otherops[2]) == REG
8564 || (GET_CODE (otherops[2]) == CONST_INT
8565 && INTVAL (otherops[2]) > -256
8566 && INTVAL (otherops[2]) < 256)))
8568 otherops[0] = operands[1];
8569 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8570 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8576 otherops[0] = adjust_address (operands[0], SImode, 4);
8577 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8578 output_asm_insn ("str%?\t%1, %0", operands);
8579 output_asm_insn ("str%?\t%1, %0", otherops);
8583 /* Constraints should prevent this. */
8590 /* Output an arbitrary MOV reg, #n.
8591 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8593 output_mov_immediate (rtx *operands)
8595 HOST_WIDE_INT n = INTVAL (operands[1]);
8597 /* Try to use one MOV. */
8598 if (const_ok_for_arm (n))
8599 output_asm_insn ("mov%?\t%0, %1", operands);
8601 /* Try to use one MVN. */
8602 else if (const_ok_for_arm (~n))
8604 operands[1] = GEN_INT (~n);
8605 output_asm_insn ("mvn%?\t%0, %1", operands);
8612 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8613 for (i = 0; i < 32; i++)
8617 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8618 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8620 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8626 /* Output an ADD r, s, #n where n may be too big for one instruction.
8627 If adding zero to one register, output nothing. */
8629 output_add_immediate (rtx *operands)
8631 HOST_WIDE_INT n = INTVAL (operands[2]);
8633 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8636 output_multi_immediate (operands,
8637 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8640 output_multi_immediate (operands,
8641 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8648 /* Output a multiple immediate operation.
8649 OPERANDS is the vector of operands referred to in the output patterns.
8650 INSTR1 is the output pattern to use for the first constant.
8651 INSTR2 is the output pattern to use for subsequent constants.
8652 IMMED_OP is the index of the constant slot in OPERANDS.
8653 N is the constant value. */
8655 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8656 int immed_op, HOST_WIDE_INT n)
8658 #if HOST_BITS_PER_WIDE_INT > 32
8664 /* Quick and easy output. */
8665 operands[immed_op] = const0_rtx;
8666 output_asm_insn (instr1, operands);
8671 const char * instr = instr1;
8673 /* Note that n is never zero here (which would give no output). */
8674 for (i = 0; i < 32; i += 2)
8678 operands[immed_op] = GEN_INT (n & (255 << i));
8679 output_asm_insn (instr, operands);
8689 /* Return the appropriate ARM instruction for the operation code.
8690 The returned result should not be overwritten. OP is the rtx of the
8691 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8694 arithmetic_instr (rtx op, int shift_first_arg)
8696 switch (GET_CODE (op))
8702 return shift_first_arg ? "rsb" : "sub";
8718 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8719 for the operation code. The returned result should not be overwritten.
8720 OP is the rtx code of the shift.
8721 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8724 shift_op (rtx op, HOST_WIDE_INT *amountp)
8727 enum rtx_code code = GET_CODE (op);
8729 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8731 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8732 *amountp = INTVAL (XEXP (op, 1));
8755 /* We never have to worry about the amount being other than a
8756 power of 2, since this case can never be reloaded from a reg. */
8758 *amountp = int_log2 (*amountp);
8769 /* This is not 100% correct, but follows from the desire to merge
8770 multiplication by a power of 2 with the recognizer for a
8771 shift. >=32 is not a valid shift for "asl", so we must try and
8772 output a shift that produces the correct arithmetical result.
8773 Using lsr #32 is identical except for the fact that the carry bit
8774 is not set correctly if we set the flags; but we never use the
8775 carry bit from such an operation, so we can ignore that. */
8776 if (code == ROTATERT)
8777 /* Rotate is just modulo 32. */
8779 else if (*amountp != (*amountp & 31))
8786 /* Shifts of 0 are no-ops. */
8794 /* Obtain the shift from the POWER of two. */
8796 static HOST_WIDE_INT
8797 int_log2 (HOST_WIDE_INT power)
8799 HOST_WIDE_INT shift = 0;
8801 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8811 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8812 /bin/as is horribly restrictive. */
8813 #define MAX_ASCII_LEN 51
8816 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8821 fputs ("\t.ascii\t\"", stream);
8823 for (i = 0; i < len; i++)
8827 if (len_so_far >= MAX_ASCII_LEN)
8829 fputs ("\"\n\t.ascii\t\"", stream);
8836 fputs ("\\t", stream);
8841 fputs ("\\f", stream);
8846 fputs ("\\b", stream);
8851 fputs ("\\r", stream);
8855 case TARGET_NEWLINE:
8856 fputs ("\\n", stream);
8858 if ((c >= ' ' && c <= '~')
8860 /* This is a good place for a line break. */
8861 len_so_far = MAX_ASCII_LEN;
8868 putc ('\\', stream);
8873 if (c >= ' ' && c <= '~')
8880 fprintf (stream, "\\%03o", c);
8887 fputs ("\"\n", stream);
8890 /* Compute the register sabe mask for registers 0 through 12
8891 inclusive. This code is used by arm_compute_save_reg_mask. */
8892 static unsigned long
8893 arm_compute_save_reg0_reg12_mask (void)
8895 unsigned long func_type = arm_current_func_type ();
8896 unsigned int save_reg_mask = 0;
8899 if (IS_INTERRUPT (func_type))
8901 unsigned int max_reg;
8902 /* Interrupt functions must not corrupt any registers,
8903 even call clobbered ones. If this is a leaf function
8904 we can just examine the registers used by the RTL, but
8905 otherwise we have to assume that whatever function is
8906 called might clobber anything, and so we have to save
8907 all the call-clobbered registers as well. */
8908 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8909 /* FIQ handlers have registers r8 - r12 banked, so
8910 we only need to check r0 - r7, Normal ISRs only
8911 bank r14 and r15, so we must check up to r12.
8912 r13 is the stack pointer which is always preserved,
8913 so we do not need to consider it here. */
8918 for (reg = 0; reg <= max_reg; reg++)
8919 if (regs_ever_live[reg]
8920 || (! current_function_is_leaf && call_used_regs [reg]))
8921 save_reg_mask |= (1 << reg);
8925 /* In the normal case we only need to save those registers
8926 which are call saved and which are used by this function. */
8927 for (reg = 0; reg <= 10; reg++)
8928 if (regs_ever_live[reg] && ! call_used_regs [reg])
8929 save_reg_mask |= (1 << reg);
8931 /* Handle the frame pointer as a special case. */
8932 if (! TARGET_APCS_FRAME
8933 && ! frame_pointer_needed
8934 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8935 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8936 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8938 /* If we aren't loading the PIC register,
8939 don't stack it even though it may be live. */
8941 && ! TARGET_SINGLE_PIC_BASE
8942 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8943 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8946 return save_reg_mask;
8949 /* Compute a bit mask of which registers need to be
8950 saved on the stack for the current function. */
8952 static unsigned long
8953 arm_compute_save_reg_mask (void)
8955 unsigned int save_reg_mask = 0;
8956 unsigned long func_type = arm_current_func_type ();
8958 if (IS_NAKED (func_type))
8959 /* This should never really happen. */
8962 /* If we are creating a stack frame, then we must save the frame pointer,
8963 IP (which will hold the old stack pointer), LR and the PC. */
8964 if (frame_pointer_needed)
8966 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8971 /* Volatile functions do not return, so there
8972 is no need to save any other registers. */
8973 if (IS_VOLATILE (func_type))
8974 return save_reg_mask;
8976 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8978 /* Decide if we need to save the link register.
8979 Interrupt routines have their own banked link register,
8980 so they never need to save it.
8981 Otherwise if we do not use the link register we do not need to save
8982 it. If we are pushing other registers onto the stack however, we
8983 can save an instruction in the epilogue by pushing the link register
8984 now and then popping it back into the PC. This incurs extra memory
8985 accesses though, so we only do it when optimizing for size, and only
8986 if we know that we will not need a fancy return sequence. */
8987 if (regs_ever_live [LR_REGNUM]
8990 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8991 save_reg_mask |= 1 << LR_REGNUM;
8993 if (cfun->machine->lr_save_eliminated)
8994 save_reg_mask &= ~ (1 << LR_REGNUM);
8996 if (TARGET_REALLY_IWMMXT
8997 && ((bit_count (save_reg_mask)
8998 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9002 /* The total number of registers that are going to be pushed
9003 onto the stack is odd. We need to ensure that the stack
9004 is 64-bit aligned before we start to save iWMMXt registers,
9005 and also before we start to create locals. (A local variable
9006 might be a double or long long which we will load/store using
9007 an iWMMXt instruction). Therefore we need to push another
9008 ARM register, so that the stack will be 64-bit aligned. We
9009 try to avoid using the arg registers (r0 -r3) as they might be
9010 used to pass values in a tail call. */
9011 for (reg = 4; reg <= 12; reg++)
9012 if ((save_reg_mask & (1 << reg)) == 0)
9016 save_reg_mask |= (1 << reg);
9019 cfun->machine->sibcall_blocked = 1;
9020 save_reg_mask |= (1 << 3);
9024 return save_reg_mask;
9028 /* Return the number of bytes required to save VFP registers. */
9030 arm_get_vfp_saved_size (void)
9037 /* Space for saved VFP registers. */
9038 if (TARGET_HARD_FLOAT && TARGET_VFP)
9041 for (regno = FIRST_VFP_REGNUM;
9042 regno < LAST_VFP_REGNUM;
9045 if ((!regs_ever_live[regno] || call_used_regs[regno])
9046 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9050 /* Workaround ARM10 VFPr1 bug. */
9051 if (count == 2 && !arm_arch6)
9053 saved += count * 8 + 4;
9062 if (count == 2 && !arm_arch6)
9064 saved += count * 8 + 4;
9071 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9072 everything bar the final return instruction. */
9074 output_return_instruction (rtx operand, int really_return, int reverse)
9076 char conditional[10];
9079 unsigned long live_regs_mask;
9080 unsigned long func_type;
9081 arm_stack_offsets *offsets;
9083 func_type = arm_current_func_type ();
9085 if (IS_NAKED (func_type))
9088 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9090 /* If this function was declared non-returning, and we have
9091 found a tail call, then we have to trust that the called
9092 function won't return. */
9097 /* Otherwise, trap an attempted return by aborting. */
9099 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9101 assemble_external_libcall (ops[1]);
9102 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9108 if (current_function_calls_alloca && !really_return)
9111 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9113 return_used_this_function = 1;
9115 live_regs_mask = arm_compute_save_reg_mask ();
9119 const char * return_reg;
9121 /* If we do not have any special requirements for function exit
9122 (eg interworking, or ISR) then we can load the return address
9123 directly into the PC. Otherwise we must load it into LR. */
9125 && ! TARGET_INTERWORK)
9126 return_reg = reg_names[PC_REGNUM];
9128 return_reg = reg_names[LR_REGNUM];
9130 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9132 /* There are three possible reasons for the IP register
9133 being saved. 1) a stack frame was created, in which case
9134 IP contains the old stack pointer, or 2) an ISR routine
9135 corrupted it, or 3) it was saved to align the stack on
9136 iWMMXt. In case 1, restore IP into SP, otherwise just
9138 if (frame_pointer_needed)
9140 live_regs_mask &= ~ (1 << IP_REGNUM);
9141 live_regs_mask |= (1 << SP_REGNUM);
9145 if (! IS_INTERRUPT (func_type)
9146 && ! TARGET_REALLY_IWMMXT)
9151 /* On some ARM architectures it is faster to use LDR rather than
9152 LDM to load a single register. On other architectures, the
9153 cost is the same. In 26 bit mode, or for exception handlers,
9154 we have to use LDM to load the PC so that the CPSR is also
9156 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9158 if (live_regs_mask == (unsigned int)(1 << reg))
9161 if (reg <= LAST_ARM_REGNUM
9162 && (reg != LR_REGNUM
9164 || ! IS_INTERRUPT (func_type)))
9166 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9167 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9174 /* Generate the load multiple instruction to restore the
9175 registers. Note we can get here, even if
9176 frame_pointer_needed is true, but only if sp already
9177 points to the base of the saved core registers. */
9178 if (live_regs_mask & (1 << SP_REGNUM))
9180 unsigned HOST_WIDE_INT stack_adjust;
9182 offsets = arm_get_frame_offsets ();
9183 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9184 if (stack_adjust != 0 && stack_adjust != 4)
9187 if (stack_adjust && arm_arch5)
9188 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9191 /* If we can't use ldmib (SA110 bug), then try to pop r3
9194 live_regs_mask |= 1 << 3;
9195 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9199 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9201 p = instr + strlen (instr);
9203 for (reg = 0; reg <= SP_REGNUM; reg++)
9204 if (live_regs_mask & (1 << reg))
9206 int l = strlen (reg_names[reg]);
9212 memcpy (p, ", ", 2);
9216 memcpy (p, "%|", 2);
9217 memcpy (p + 2, reg_names[reg], l);
9221 if (live_regs_mask & (1 << LR_REGNUM))
9223 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9224 /* If returning from an interrupt, restore the CPSR. */
9225 if (IS_INTERRUPT (func_type))
9232 output_asm_insn (instr, & operand);
9234 /* See if we need to generate an extra instruction to
9235 perform the actual function return. */
9237 && func_type != ARM_FT_INTERWORKED
9238 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9240 /* The return has already been handled
9241 by loading the LR into the PC. */
9248 switch ((int) ARM_FUNC_TYPE (func_type))
9252 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9255 case ARM_FT_INTERWORKED:
9256 sprintf (instr, "bx%s\t%%|lr", conditional);
9259 case ARM_FT_EXCEPTION:
9260 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9264 /* ARMv5 implementations always provide BX, so interworking
9266 if ((insn_flags & FL_ARCH5) != 0)
9267 sprintf (instr, "bx%s\t%%|lr", conditional);
9269 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9273 output_asm_insn (instr, & operand);
9279 /* Write the function name into the code section, directly preceding
9280 the function prologue.
9282 Code will be output similar to this:
9284 .ascii "arm_poke_function_name", 0
9287 .word 0xff000000 + (t1 - t0)
9288 arm_poke_function_name
9290 stmfd sp!, {fp, ip, lr, pc}
9293 When performing a stack backtrace, code can inspect the value
9294 of 'pc' stored at 'fp' + 0. If the trace function then looks
9295 at location pc - 12 and the top 8 bits are set, then we know
9296 that there is a function name embedded immediately preceding this
9297 location and has length ((pc[-3]) & 0xff000000).
9299 We assume that pc is declared as a pointer to an unsigned long.
9301 It is of no benefit to output the function name if we are assembling
9302 a leaf function. These function types will not contain a stack
9303 backtrace structure, therefore it is not possible to determine the
9306 arm_poke_function_name (FILE *stream, const char *name)
9308 unsigned long alignlength;
9309 unsigned long length;
9312 length = strlen (name) + 1;
9313 alignlength = ROUND_UP_WORD (length);
9315 ASM_OUTPUT_ASCII (stream, name, length);
9316 ASM_OUTPUT_ALIGN (stream, 2);
9317 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9318 assemble_aligned_integer (UNITS_PER_WORD, x);
9321 /* Place some comments into the assembler stream
9322 describing the current function. */
9324 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9326 unsigned long func_type;
9330 thumb_output_function_prologue (f, frame_size);
9335 if (arm_ccfsm_state || arm_target_insn)
9338 func_type = arm_current_func_type ();
9340 switch ((int) ARM_FUNC_TYPE (func_type))
9345 case ARM_FT_INTERWORKED:
9346 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9348 case ARM_FT_EXCEPTION_HANDLER:
9349 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9352 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9355 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9357 case ARM_FT_EXCEPTION:
9358 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9362 if (IS_NAKED (func_type))
9363 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9365 if (IS_VOLATILE (func_type))
9366 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9368 if (IS_NESTED (func_type))
9369 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9371 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9372 current_function_args_size,
9373 current_function_pretend_args_size, frame_size);
9375 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9376 frame_pointer_needed,
9377 cfun->machine->uses_anonymous_args);
9379 if (cfun->machine->lr_save_eliminated)
9380 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9382 #ifdef AOF_ASSEMBLER
9384 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9387 return_used_this_function = 0;
9391 arm_output_epilogue (rtx sibling)
9394 unsigned long saved_regs_mask;
9395 unsigned long func_type;
9396 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9397 frame that is $fp + 4 for a non-variadic function. */
9398 int floats_offset = 0;
9400 FILE * f = asm_out_file;
9401 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9402 unsigned int lrm_count = 0;
9403 int really_return = (sibling == NULL);
9405 arm_stack_offsets *offsets;
9407 /* If we have already generated the return instruction
9408 then it is futile to generate anything else. */
9409 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9412 func_type = arm_current_func_type ();
9414 if (IS_NAKED (func_type))
9415 /* Naked functions don't have epilogues. */
9418 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9422 /* A volatile function should never return. Call abort. */
9423 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9424 assemble_external_libcall (op);
9425 output_asm_insn ("bl\t%a0", &op);
9430 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9432 /* If we are throwing an exception, then we really must
9433 be doing a return, so we can't tail-call. */
9436 offsets = arm_get_frame_offsets ();
9437 saved_regs_mask = arm_compute_save_reg_mask ();
9440 lrm_count = bit_count (saved_regs_mask);
9442 floats_offset = offsets->saved_args;
9443 /* Compute how far away the floats will be. */
9444 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9445 if (saved_regs_mask & (1 << reg))
9448 if (frame_pointer_needed)
9450 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9451 int vfp_offset = offsets->frame;
9453 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9455 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9456 if (regs_ever_live[reg] && !call_used_regs[reg])
9458 floats_offset += 12;
9459 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9460 reg, FP_REGNUM, floats_offset - vfp_offset);
9465 start_reg = LAST_FPA_REGNUM;
9467 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9469 if (regs_ever_live[reg] && !call_used_regs[reg])
9471 floats_offset += 12;
9473 /* We can't unstack more than four registers at once. */
9474 if (start_reg - reg == 3)
9476 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9477 reg, FP_REGNUM, floats_offset - vfp_offset);
9478 start_reg = reg - 1;
9483 if (reg != start_reg)
9484 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9485 reg + 1, start_reg - reg,
9486 FP_REGNUM, floats_offset - vfp_offset);
9487 start_reg = reg - 1;
9491 /* Just in case the last register checked also needs unstacking. */
9492 if (reg != start_reg)
9493 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9494 reg + 1, start_reg - reg,
9495 FP_REGNUM, floats_offset - vfp_offset);
9498 if (TARGET_HARD_FLOAT && TARGET_VFP)
9502 /* The fldmx insn does not have base+offset addressing modes,
9503 so we use IP to hold the address. */
9504 saved_size = arm_get_vfp_saved_size ();
9508 floats_offset += saved_size;
9509 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9510 FP_REGNUM, floats_offset - vfp_offset);
9512 start_reg = FIRST_VFP_REGNUM;
9513 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9515 if ((!regs_ever_live[reg] || call_used_regs[reg])
9516 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9518 if (start_reg != reg)
9519 arm_output_fldmx (f, IP_REGNUM,
9520 (start_reg - FIRST_VFP_REGNUM) / 2,
9521 (reg - start_reg) / 2);
9522 start_reg = reg + 2;
9525 if (start_reg != reg)
9526 arm_output_fldmx (f, IP_REGNUM,
9527 (start_reg - FIRST_VFP_REGNUM) / 2,
9528 (reg - start_reg) / 2);
9533 /* The frame pointer is guaranteed to be non-double-word aligned.
9534 This is because it is set to (old_stack_pointer - 4) and the
9535 old_stack_pointer was double word aligned. Thus the offset to
9536 the iWMMXt registers to be loaded must also be non-double-word
9537 sized, so that the resultant address *is* double-word aligned.
9538 We can ignore floats_offset since that was already included in
9539 the live_regs_mask. */
9540 lrm_count += (lrm_count % 2 ? 2 : 1);
9542 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9543 if (regs_ever_live[reg] && !call_used_regs[reg])
9545 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9546 reg, FP_REGNUM, lrm_count * 4);
9551 /* saved_regs_mask should contain the IP, which at the time of stack
9552 frame generation actually contains the old stack pointer. So a
9553 quick way to unwind the stack is just pop the IP register directly
9554 into the stack pointer. */
9555 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9557 saved_regs_mask &= ~ (1 << IP_REGNUM);
9558 saved_regs_mask |= (1 << SP_REGNUM);
9560 /* There are two registers left in saved_regs_mask - LR and PC. We
9561 only need to restore the LR register (the return address), but to
9562 save time we can load it directly into the PC, unless we need a
9563 special function exit sequence, or we are not really returning. */
9564 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9565 /* Delete the LR from the register mask, so that the LR on
9566 the stack is loaded into the PC in the register mask. */
9567 saved_regs_mask &= ~ (1 << LR_REGNUM);
9569 saved_regs_mask &= ~ (1 << PC_REGNUM);
9571 /* We must use SP as the base register, because SP is one of the
9572 registers being restored. If an interrupt or page fault
9573 happens in the ldm instruction, the SP might or might not
9574 have been restored. That would be bad, as then SP will no
9575 longer indicate the safe area of stack, and we can get stack
9576 corruption. Using SP as the base register means that it will
9577 be reset correctly to the original value, should an interrupt
9578 occur. If the stack pointer already points at the right
9579 place, then omit the subtraction. */
9580 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9581 || current_function_calls_alloca)
9582 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9583 4 * bit_count (saved_regs_mask));
9584 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9586 if (IS_INTERRUPT (func_type))
9587 /* Interrupt handlers will have pushed the
9588 IP onto the stack, so restore it now. */
9589 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9593 /* Restore stack pointer if necessary. */
9594 if (offsets->outgoing_args != offsets->saved_regs)
9596 operands[0] = operands[1] = stack_pointer_rtx;
9597 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9598 output_add_immediate (operands);
9601 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9603 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9604 if (regs_ever_live[reg] && !call_used_regs[reg])
9605 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9610 start_reg = FIRST_FPA_REGNUM;
9612 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9614 if (regs_ever_live[reg] && !call_used_regs[reg])
9616 if (reg - start_reg == 3)
9618 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9619 start_reg, SP_REGNUM);
9620 start_reg = reg + 1;
9625 if (reg != start_reg)
9626 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9627 start_reg, reg - start_reg,
9630 start_reg = reg + 1;
9634 /* Just in case the last register checked also needs unstacking. */
9635 if (reg != start_reg)
9636 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9637 start_reg, reg - start_reg, SP_REGNUM);
9640 if (TARGET_HARD_FLOAT && TARGET_VFP)
9642 start_reg = FIRST_VFP_REGNUM;
9643 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9645 if ((!regs_ever_live[reg] || call_used_regs[reg])
9646 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9648 if (start_reg != reg)
9649 arm_output_fldmx (f, SP_REGNUM,
9650 (start_reg - FIRST_VFP_REGNUM) / 2,
9651 (reg - start_reg) / 2);
9652 start_reg = reg + 2;
9655 if (start_reg != reg)
9656 arm_output_fldmx (f, SP_REGNUM,
9657 (start_reg - FIRST_VFP_REGNUM) / 2,
9658 (reg - start_reg) / 2);
9661 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9662 if (regs_ever_live[reg] && !call_used_regs[reg])
9663 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9665 /* If we can, restore the LR into the PC. */
9666 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9668 && current_function_pretend_args_size == 0
9669 && saved_regs_mask & (1 << LR_REGNUM))
9671 saved_regs_mask &= ~ (1 << LR_REGNUM);
9672 saved_regs_mask |= (1 << PC_REGNUM);
9675 /* Load the registers off the stack. If we only have one register
9676 to load use the LDR instruction - it is faster. */
9677 if (saved_regs_mask == (1 << LR_REGNUM))
9679 /* The exception handler ignores the LR, so we do
9680 not really need to load it off the stack. */
9682 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9684 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9686 else if (saved_regs_mask)
9688 if (saved_regs_mask & (1 << SP_REGNUM))
9689 /* Note - write back to the stack register is not enabled
9690 (ie "ldmfd sp!..."). We know that the stack pointer is
9691 in the list of registers and if we add writeback the
9692 instruction becomes UNPREDICTABLE. */
9693 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9695 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9698 if (current_function_pretend_args_size)
9700 /* Unwind the pre-pushed regs. */
9701 operands[0] = operands[1] = stack_pointer_rtx;
9702 operands[2] = GEN_INT (current_function_pretend_args_size);
9703 output_add_immediate (operands);
9708 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9709 && current_function_pretend_args_size == 0
9710 && saved_regs_mask & (1 << PC_REGNUM)))
9713 /* Generate the return instruction. */
9714 switch ((int) ARM_FUNC_TYPE (func_type))
9716 case ARM_FT_EXCEPTION_HANDLER:
9717 /* Even in 26-bit mode we do a mov (rather than a movs)
9718 because we don't have the PSR bits set in the address. */
9719 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9724 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9727 case ARM_FT_EXCEPTION:
9728 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9731 case ARM_FT_INTERWORKED:
9732 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9736 if (frame_pointer_needed)
9737 /* If we used the frame pointer then the return address
9738 will have been loaded off the stack directly into the
9739 PC, so there is no need to issue a MOV instruction
9742 else if (current_function_pretend_args_size == 0
9743 && (saved_regs_mask & (1 << LR_REGNUM)))
9744 /* Similarly we may have been able to load LR into the PC
9745 even if we did not create a stack frame. */
9748 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9756 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9757 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9759 arm_stack_offsets *offsets;
9763 /* ??? Probably not safe to set this here, since it assumes that a
9764 function will be emitted as assembly immediately after we generate
9765 RTL for it. This does not happen for inline functions. */
9766 return_used_this_function = 0;
9770 /* We need to take into account any stack-frame rounding. */
9771 offsets = arm_get_frame_offsets ();
9773 if (use_return_insn (FALSE, NULL)
9774 && return_used_this_function
9775 && offsets->saved_regs != offsets->outgoing_args
9776 && !frame_pointer_needed)
9779 /* Reset the ARM-specific per-function variables. */
9780 after_arm_reorg = 0;
9784 /* Generate and emit an insn that we will recognize as a push_multi.
9785 Unfortunately, since this insn does not reflect very well the actual
9786 semantics of the operation, we need to annotate the insn for the benefit
9787 of DWARF2 frame unwind information. */
9789 emit_multi_reg_push (int mask)
9796 int dwarf_par_index;
9799 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9800 if (mask & (1 << i))
9803 if (num_regs == 0 || num_regs > 16)
9806 /* We don't record the PC in the dwarf frame information. */
9807 num_dwarf_regs = num_regs;
9808 if (mask & (1 << PC_REGNUM))
9811 /* For the body of the insn we are going to generate an UNSPEC in
9812 parallel with several USEs. This allows the insn to be recognized
9813 by the push_multi pattern in the arm.md file. The insn looks
9814 something like this:
9817 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9818 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9819 (use (reg:SI 11 fp))
9820 (use (reg:SI 12 ip))
9821 (use (reg:SI 14 lr))
9822 (use (reg:SI 15 pc))
9825 For the frame note however, we try to be more explicit and actually
9826 show each register being stored into the stack frame, plus a (single)
9827 decrement of the stack pointer. We do it this way in order to be
9828 friendly to the stack unwinding code, which only wants to see a single
9829 stack decrement per instruction. The RTL we generate for the note looks
9830 something like this:
9833 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9834 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9835 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9836 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9837 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9840 This sequence is used both by the code to support stack unwinding for
9841 exceptions handlers and the code to generate dwarf2 frame debugging. */
9843 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9844 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9845 dwarf_par_index = 1;
9847 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9849 if (mask & (1 << i))
9851 reg = gen_rtx_REG (SImode, i);
9854 = gen_rtx_SET (VOIDmode,
9855 gen_rtx_MEM (BLKmode,
9856 gen_rtx_PRE_DEC (BLKmode,
9857 stack_pointer_rtx)),
9858 gen_rtx_UNSPEC (BLKmode,
9864 tmp = gen_rtx_SET (VOIDmode,
9865 gen_rtx_MEM (SImode, stack_pointer_rtx),
9867 RTX_FRAME_RELATED_P (tmp) = 1;
9868 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9876 for (j = 1, i++; j < num_regs; i++)
9878 if (mask & (1 << i))
9880 reg = gen_rtx_REG (SImode, i);
9882 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9886 tmp = gen_rtx_SET (VOIDmode,
9887 gen_rtx_MEM (SImode,
9888 plus_constant (stack_pointer_rtx,
9891 RTX_FRAME_RELATED_P (tmp) = 1;
9892 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9899 par = emit_insn (par);
9901 tmp = gen_rtx_SET (SImode,
9903 gen_rtx_PLUS (SImode,
9905 GEN_INT (-4 * num_regs)));
9906 RTX_FRAME_RELATED_P (tmp) = 1;
9907 XVECEXP (dwarf, 0, 0) = tmp;
9909 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9915 emit_sfm (int base_reg, int count)
9922 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9923 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9925 reg = gen_rtx_REG (XFmode, base_reg++);
9928 = gen_rtx_SET (VOIDmode,
9929 gen_rtx_MEM (BLKmode,
9930 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9931 gen_rtx_UNSPEC (BLKmode,
9935 = gen_rtx_SET (VOIDmode,
9936 gen_rtx_MEM (XFmode,
9937 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9939 RTX_FRAME_RELATED_P (tmp) = 1;
9940 XVECEXP (dwarf, 0, count - 1) = tmp;
9942 for (i = 1; i < count; i++)
9944 reg = gen_rtx_REG (XFmode, base_reg++);
9945 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9947 tmp = gen_rtx_SET (VOIDmode,
9948 gen_rtx_MEM (XFmode,
9949 gen_rtx_PRE_DEC (BLKmode,
9950 stack_pointer_rtx)),
9952 RTX_FRAME_RELATED_P (tmp) = 1;
9953 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9956 par = emit_insn (par);
9957 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9963 /* Return true if the current function needs to save/restore LR. */
9966 thumb_force_lr_save (void)
9968 return !cfun->machine->lr_save_eliminated
9969 && (!leaf_function_p ()
9970 || thumb_far_jump_used_p ()
9971 || regs_ever_live [LR_REGNUM]);
9975 /* Compute the distance from register FROM to register TO.
9976 These can be the arg pointer (26), the soft frame pointer (25),
9977 the stack pointer (13) or the hard frame pointer (11).
9978 Typical stack layout looks like this:
9980 old stack pointer -> | |
9983 | | saved arguments for
9984 | | vararg functions
9987 hard FP & arg pointer -> | | \
9995 soft frame pointer -> | | /
10005 current stack pointer -> | | /
10008 For a given function some or all of these stack components
10009 may not be needed, giving rise to the possibility of
10010 eliminating some of the registers.
10012 The values returned by this function must reflect the behavior
10013 of arm_expand_prologue() and arm_compute_save_reg_mask().
10015 The sign of the number returned reflects the direction of stack
10016 growth, so the values are positive for all eliminations except
10017 from the soft frame pointer to the hard frame pointer.
10019 SFP may point just inside the local variables block to ensure correct
10023 /* Calculate stack offsets. These are used to calculate register elimination
10024 offsets and in prologue/epilogue code. */
10026 static arm_stack_offsets *
10027 arm_get_frame_offsets (void)
10029 struct arm_stack_offsets *offsets;
10030 unsigned long func_type;
10033 HOST_WIDE_INT frame_size;
10035 offsets = &cfun->machine->stack_offsets;
10037 /* We need to know if we are a leaf function. Unfortunately, it
10038 is possible to be called after start_sequence has been called,
10039 which causes get_insns to return the insns for the sequence,
10040 not the function, which will cause leaf_function_p to return
10041 the incorrect result.
10043 to know about leaf functions once reload has completed, and the
10044 frame size cannot be changed after that time, so we can safely
10045 use the cached value. */
10047 if (reload_completed)
10050 /* Initially this is the size of the local variables. It will translated
10051 into an offset once we have determined the size of preceding data. */
10052 frame_size = ROUND_UP_WORD (get_frame_size ());
10054 leaf = leaf_function_p ();
10056 /* Space for variadic functions. */
10057 offsets->saved_args = current_function_pretend_args_size;
10059 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10063 unsigned int regno;
10065 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10067 /* We know that SP will be doubleword aligned on entry, and we must
10068 preserve that condition at any subroutine call. We also require the
10069 soft frame pointer to be doubleword aligned. */
10071 if (TARGET_REALLY_IWMMXT)
10073 /* Check for the call-saved iWMMXt registers. */
10074 for (regno = FIRST_IWMMXT_REGNUM;
10075 regno <= LAST_IWMMXT_REGNUM;
10077 if (regs_ever_live [regno] && ! call_used_regs [regno])
10081 func_type = arm_current_func_type ();
10082 if (! IS_VOLATILE (func_type))
10084 /* Space for saved FPA registers. */
10085 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10086 if (regs_ever_live[regno] && ! call_used_regs[regno])
10089 /* Space for saved VFP registers. */
10090 if (TARGET_HARD_FLOAT && TARGET_VFP)
10091 saved += arm_get_vfp_saved_size ();
10094 else /* TARGET_THUMB */
10101 for (reg = 8; reg < 13; reg ++)
10102 if (THUMB_REG_PUSHED_P (reg))
10105 saved += 4 * count_regs;
10107 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10108 if (THUMB_REG_PUSHED_P (reg))
10110 if (count_regs || thumb_force_lr_save ())
10111 saved += 4 * (count_regs + 1);
10112 if (TARGET_BACKTRACE)
10114 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10121 /* Saved registers include the stack frame. */
10122 offsets->saved_regs = offsets->saved_args + saved;
10123 offsets->soft_frame = offsets->saved_regs;
10124 /* A leaf function does not need any stack alignment if it has nothing
10126 if (leaf && frame_size == 0)
10128 offsets->outgoing_args = offsets->soft_frame;
10132 /* Ensure SFP has the correct alignment. */
10133 if (ARM_DOUBLEWORD_ALIGN
10134 && (offsets->soft_frame & 7))
10135 offsets->soft_frame += 4;
10137 offsets->outgoing_args = offsets->soft_frame + frame_size
10138 + current_function_outgoing_args_size;
10140 if (ARM_DOUBLEWORD_ALIGN)
10142 /* Ensure SP remains doubleword aligned. */
10143 if (offsets->outgoing_args & 7)
10144 offsets->outgoing_args += 4;
10145 if (offsets->outgoing_args & 7)
10153 /* Calculate the relative offsets for the different stack pointers. Positive
10154 offsets are in the direction of stack growth. */
10157 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10159 arm_stack_offsets *offsets;
10161 offsets = arm_get_frame_offsets ();
10163 /* OK, now we have enough information to compute the distances.
10164 There must be an entry in these switch tables for each pair
10165 of registers in ELIMINABLE_REGS, even if some of the entries
10166 seem to be redundant or useless. */
10169 case ARG_POINTER_REGNUM:
10172 case THUMB_HARD_FRAME_POINTER_REGNUM:
10175 case FRAME_POINTER_REGNUM:
10176 /* This is the reverse of the soft frame pointer
10177 to hard frame pointer elimination below. */
10178 return offsets->soft_frame - offsets->saved_args;
10180 case ARM_HARD_FRAME_POINTER_REGNUM:
10181 /* If there is no stack frame then the hard
10182 frame pointer and the arg pointer coincide. */
10183 if (offsets->frame == offsets->saved_regs)
10185 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10186 return (frame_pointer_needed
10187 && cfun->static_chain_decl != NULL
10188 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10190 case STACK_POINTER_REGNUM:
10191 /* If nothing has been pushed on the stack at all
10192 then this will return -4. This *is* correct! */
10193 return offsets->outgoing_args - (offsets->saved_args + 4);
10200 case FRAME_POINTER_REGNUM:
10203 case THUMB_HARD_FRAME_POINTER_REGNUM:
10206 case ARM_HARD_FRAME_POINTER_REGNUM:
10207 /* The hard frame pointer points to the top entry in the
10208 stack frame. The soft frame pointer to the bottom entry
10209 in the stack frame. If there is no stack frame at all,
10210 then they are identical. */
10212 return offsets->frame - offsets->soft_frame;
10214 case STACK_POINTER_REGNUM:
10215 return offsets->outgoing_args - offsets->soft_frame;
10223 /* You cannot eliminate from the stack pointer.
10224 In theory you could eliminate from the hard frame
10225 pointer to the stack pointer, but this will never
10226 happen, since if a stack frame is not needed the
10227 hard frame pointer will never be used. */
10233 /* Generate the prologue instructions for entry into an ARM function. */
10235 arm_expand_prologue (void)
10241 unsigned long live_regs_mask;
10242 unsigned long func_type;
10244 int saved_pretend_args = 0;
10245 int saved_regs = 0;
10246 unsigned int args_to_push;
10247 arm_stack_offsets *offsets;
10249 func_type = arm_current_func_type ();
10251 /* Naked functions don't have prologues. */
10252 if (IS_NAKED (func_type))
10255 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10256 args_to_push = current_function_pretend_args_size;
10258 /* Compute which register we will have to save onto the stack. */
10259 live_regs_mask = arm_compute_save_reg_mask ();
10261 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10263 if (frame_pointer_needed)
10265 if (IS_INTERRUPT (func_type))
10267 /* Interrupt functions must not corrupt any registers.
10268 Creating a frame pointer however, corrupts the IP
10269 register, so we must push it first. */
10270 insn = emit_multi_reg_push (1 << IP_REGNUM);
10272 /* Do not set RTX_FRAME_RELATED_P on this insn.
10273 The dwarf stack unwinding code only wants to see one
10274 stack decrement per function, and this is not it. If
10275 this instruction is labeled as being part of the frame
10276 creation sequence then dwarf2out_frame_debug_expr will
10277 abort when it encounters the assignment of IP to FP
10278 later on, since the use of SP here establishes SP as
10279 the CFA register and not IP.
10281 Anyway this instruction is not really part of the stack
10282 frame creation although it is part of the prologue. */
10284 else if (IS_NESTED (func_type))
10286 /* The Static chain register is the same as the IP register
10287 used as a scratch register during stack frame creation.
10288 To get around this need to find somewhere to store IP
10289 whilst the frame is being created. We try the following
10292 1. The last argument register.
10293 2. A slot on the stack above the frame. (This only
10294 works if the function is not a varargs function).
10295 3. Register r3, after pushing the argument registers
10298 Note - we only need to tell the dwarf2 backend about the SP
10299 adjustment in the second variant; the static chain register
10300 doesn't need to be unwound, as it doesn't contain a value
10301 inherited from the caller. */
10303 if (regs_ever_live[3] == 0)
10305 insn = gen_rtx_REG (SImode, 3);
10306 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10307 insn = emit_insn (insn);
10309 else if (args_to_push == 0)
10312 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10313 insn = gen_rtx_MEM (SImode, insn);
10314 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10315 insn = emit_insn (insn);
10319 /* Just tell the dwarf backend that we adjusted SP. */
10320 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10321 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10322 GEN_INT (-fp_offset)));
10323 RTX_FRAME_RELATED_P (insn) = 1;
10324 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10325 dwarf, REG_NOTES (insn));
10329 /* Store the args on the stack. */
10330 if (cfun->machine->uses_anonymous_args)
10331 insn = emit_multi_reg_push
10332 ((0xf0 >> (args_to_push / 4)) & 0xf);
10335 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10336 GEN_INT (- args_to_push)));
10338 RTX_FRAME_RELATED_P (insn) = 1;
10340 saved_pretend_args = 1;
10341 fp_offset = args_to_push;
10344 /* Now reuse r3 to preserve IP. */
10345 insn = gen_rtx_REG (SImode, 3);
10346 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10347 (void) emit_insn (insn);
10353 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10354 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10357 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10359 insn = emit_insn (insn);
10360 RTX_FRAME_RELATED_P (insn) = 1;
10365 /* Push the argument registers, or reserve space for them. */
10366 if (cfun->machine->uses_anonymous_args)
10367 insn = emit_multi_reg_push
10368 ((0xf0 >> (args_to_push / 4)) & 0xf);
10371 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10372 GEN_INT (- args_to_push)));
10373 RTX_FRAME_RELATED_P (insn) = 1;
10376 /* If this is an interrupt service routine, and the link register
10377 is going to be pushed, and we are not creating a stack frame,
10378 (which would involve an extra push of IP and a pop in the epilogue)
10379 subtracting four from LR now will mean that the function return
10380 can be done with a single instruction. */
10381 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10382 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10383 && ! frame_pointer_needed)
10384 emit_insn (gen_rtx_SET (SImode,
10385 gen_rtx_REG (SImode, LR_REGNUM),
10386 gen_rtx_PLUS (SImode,
10387 gen_rtx_REG (SImode, LR_REGNUM),
10390 if (live_regs_mask)
10392 insn = emit_multi_reg_push (live_regs_mask);
10393 saved_regs += bit_count (live_regs_mask) * 4;
10394 RTX_FRAME_RELATED_P (insn) = 1;
10398 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10399 if (regs_ever_live[reg] && ! call_used_regs [reg])
10401 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10402 insn = gen_rtx_MEM (V2SImode, insn);
10403 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10404 gen_rtx_REG (V2SImode, reg)));
10405 RTX_FRAME_RELATED_P (insn) = 1;
10409 if (! IS_VOLATILE (func_type))
10413 /* Save any floating point call-saved registers used by this
10415 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10417 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10418 if (regs_ever_live[reg] && !call_used_regs[reg])
10420 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10421 insn = gen_rtx_MEM (XFmode, insn);
10422 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10423 gen_rtx_REG (XFmode, reg)));
10424 RTX_FRAME_RELATED_P (insn) = 1;
10430 start_reg = LAST_FPA_REGNUM;
10432 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10434 if (regs_ever_live[reg] && !call_used_regs[reg])
10436 if (start_reg - reg == 3)
10438 insn = emit_sfm (reg, 4);
10439 RTX_FRAME_RELATED_P (insn) = 1;
10441 start_reg = reg - 1;
10446 if (start_reg != reg)
10448 insn = emit_sfm (reg + 1, start_reg - reg);
10449 RTX_FRAME_RELATED_P (insn) = 1;
10450 saved_regs += (start_reg - reg) * 12;
10452 start_reg = reg - 1;
10456 if (start_reg != reg)
10458 insn = emit_sfm (reg + 1, start_reg - reg);
10459 saved_regs += (start_reg - reg) * 12;
10460 RTX_FRAME_RELATED_P (insn) = 1;
10463 if (TARGET_HARD_FLOAT && TARGET_VFP)
10465 start_reg = FIRST_VFP_REGNUM;
10467 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10469 if ((!regs_ever_live[reg] || call_used_regs[reg])
10470 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10472 if (start_reg != reg)
10473 saved_regs += vfp_emit_fstmx (start_reg,
10474 (reg - start_reg) / 2);
10475 start_reg = reg + 2;
10478 if (start_reg != reg)
10479 saved_regs += vfp_emit_fstmx (start_reg,
10480 (reg - start_reg) / 2);
10484 if (frame_pointer_needed)
10486 /* Create the new frame pointer. */
10487 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10488 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10489 RTX_FRAME_RELATED_P (insn) = 1;
10491 if (IS_NESTED (func_type))
10493 /* Recover the static chain register. */
10494 if (regs_ever_live [3] == 0
10495 || saved_pretend_args)
10496 insn = gen_rtx_REG (SImode, 3);
10497 else /* if (current_function_pretend_args_size == 0) */
10499 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10501 insn = gen_rtx_MEM (SImode, insn);
10504 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10505 /* Add a USE to stop propagate_one_insn() from barfing. */
10506 emit_insn (gen_prologue_use (ip_rtx));
10510 offsets = arm_get_frame_offsets ();
10511 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10513 /* This add can produce multiple insns for a large constant, so we
10514 need to get tricky. */
10515 rtx last = get_last_insn ();
10517 amount = GEN_INT (offsets->saved_args + saved_regs
10518 - offsets->outgoing_args);
10520 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10524 last = last ? NEXT_INSN (last) : get_insns ();
10525 RTX_FRAME_RELATED_P (last) = 1;
10527 while (last != insn);
10529 /* If the frame pointer is needed, emit a special barrier that
10530 will prevent the scheduler from moving stores to the frame
10531 before the stack adjustment. */
10532 if (frame_pointer_needed)
10533 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10534 hard_frame_pointer_rtx));
10537 /* If we are profiling, make sure no instructions are scheduled before
10538 the call to mcount. Similarly if the user has requested no
10539 scheduling in the prolog. */
10540 if (current_function_profile || TARGET_NO_SCHED_PRO)
10541 emit_insn (gen_blockage ());
10543 /* If the link register is being kept alive, with the return address in it,
10544 then make sure that it does not get reused by the ce2 pass. */
10545 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10547 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10548 cfun->machine->lr_save_eliminated = 1;
10552 /* If CODE is 'd', then the X is a condition operand and the instruction
10553 should only be executed if the condition is true.
10554 if CODE is 'D', then the X is a condition operand and the instruction
10555 should only be executed if the condition is false: however, if the mode
10556 of the comparison is CCFPEmode, then always execute the instruction -- we
10557 do this because in these circumstances !GE does not necessarily imply LT;
10558 in these cases the instruction pattern will take care to make sure that
10559 an instruction containing %d will follow, thereby undoing the effects of
10560 doing this instruction unconditionally.
10561 If CODE is 'N' then X is a floating point operand that must be negated
10563 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10564 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10566 arm_print_operand (FILE *stream, rtx x, int code)
10571 fputs (ASM_COMMENT_START, stream);
10575 fputs (user_label_prefix, stream);
10579 fputs (REGISTER_PREFIX, stream);
10583 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10585 if (TARGET_THUMB || current_insn_predicate != NULL)
10588 fputs (arm_condition_codes[arm_current_cc], stream);
10590 else if (current_insn_predicate)
10592 enum arm_cond_code code;
10597 code = get_arm_condition_code (current_insn_predicate);
10598 fputs (arm_condition_codes[code], stream);
10605 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10606 r = REAL_VALUE_NEGATE (r);
10607 fprintf (stream, "%s", fp_const_from_val (&r));
10612 if (GET_CODE (x) == CONST_INT)
10615 val = ARM_SIGN_EXTEND (~INTVAL (x));
10616 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10620 putc ('~', stream);
10621 output_addr_const (stream, x);
10626 fprintf (stream, "%s", arithmetic_instr (x, 1));
10629 /* Truncate Cirrus shift counts. */
10631 if (GET_CODE (x) == CONST_INT)
10633 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10636 arm_print_operand (stream, x, 0);
10640 fprintf (stream, "%s", arithmetic_instr (x, 0));
10646 const char * shift = shift_op (x, &val);
10650 fprintf (stream, ", %s ", shift_op (x, &val));
10652 arm_print_operand (stream, XEXP (x, 1), 0);
10654 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10659 /* An explanation of the 'Q', 'R' and 'H' register operands:
10661 In a pair of registers containing a DI or DF value the 'Q'
10662 operand returns the register number of the register containing
10663 the least significant part of the value. The 'R' operand returns
10664 the register number of the register containing the most
10665 significant part of the value.
10667 The 'H' operand returns the higher of the two register numbers.
10668 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10669 same as the 'Q' operand, since the most significant part of the
10670 value is held in the lower number register. The reverse is true
10671 on systems where WORDS_BIG_ENDIAN is false.
10673 The purpose of these operands is to distinguish between cases
10674 where the endian-ness of the values is important (for example
10675 when they are added together), and cases where the endian-ness
10676 is irrelevant, but the order of register operations is important.
10677 For example when loading a value from memory into a register
10678 pair, the endian-ness does not matter. Provided that the value
10679 from the lower memory address is put into the lower numbered
10680 register, and the value from the higher address is put into the
10681 higher numbered register, the load will work regardless of whether
10682 the value being loaded is big-wordian or little-wordian. The
10683 order of the two register loads can matter however, if the address
10684 of the memory location is actually held in one of the registers
10685 being overwritten by the load. */
10687 if (REGNO (x) > LAST_ARM_REGNUM)
10689 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10693 if (REGNO (x) > LAST_ARM_REGNUM)
10695 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10699 if (REGNO (x) > LAST_ARM_REGNUM)
10701 asm_fprintf (stream, "%r", REGNO (x) + 1);
10705 asm_fprintf (stream, "%r",
10706 GET_CODE (XEXP (x, 0)) == REG
10707 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10711 asm_fprintf (stream, "{%r-%r}",
10713 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10717 /* CONST_TRUE_RTX means always -- that's the default. */
10718 if (x == const_true_rtx)
10721 fputs (arm_condition_codes[get_arm_condition_code (x)],
10726 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10727 want to do that. */
10728 if (x == const_true_rtx)
10731 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10732 (get_arm_condition_code (x))],
10736 /* Cirrus registers can be accessed in a variety of ways:
10737 single floating point (f)
10738 double floating point (d)
10740 64bit integer (dx). */
10741 case 'W': /* Cirrus register in F mode. */
10742 case 'X': /* Cirrus register in D mode. */
10743 case 'Y': /* Cirrus register in FX mode. */
10744 case 'Z': /* Cirrus register in DX mode. */
10745 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10748 fprintf (stream, "mv%s%s",
10750 : code == 'X' ? "d"
10751 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10755 /* Print cirrus register in the mode specified by the register's mode. */
10758 int mode = GET_MODE (x);
10760 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10763 fprintf (stream, "mv%s%s",
10764 mode == DFmode ? "d"
10765 : mode == SImode ? "fx"
10766 : mode == DImode ? "dx"
10767 : "f", reg_names[REGNO (x)] + 2);
10773 if (GET_CODE (x) != REG
10774 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10775 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10776 /* Bad value for wCG register number. */
10779 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10782 /* Print an iWMMXt control register name. */
10784 if (GET_CODE (x) != CONST_INT
10786 || INTVAL (x) >= 16)
10787 /* Bad value for wC register number. */
10791 static const char * wc_reg_names [16] =
10793 "wCID", "wCon", "wCSSF", "wCASF",
10794 "wC4", "wC5", "wC6", "wC7",
10795 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10796 "wC12", "wC13", "wC14", "wC15"
10799 fprintf (stream, wc_reg_names [INTVAL (x)]);
10803 /* Print a VFP double precision register name. */
10806 int mode = GET_MODE (x);
10809 if (mode != DImode && mode != DFmode)
10812 if (GET_CODE (x) != REG
10813 || !IS_VFP_REGNUM (REGNO (x)))
10816 num = REGNO(x) - FIRST_VFP_REGNUM;
10820 fprintf (stream, "d%d", num >> 1);
10828 if (GET_CODE (x) == REG)
10829 asm_fprintf (stream, "%r", REGNO (x));
10830 else if (GET_CODE (x) == MEM)
10832 output_memory_reference_mode = GET_MODE (x);
10833 output_address (XEXP (x, 0));
10835 else if (GET_CODE (x) == CONST_DOUBLE)
10836 fprintf (stream, "#%s", fp_immediate_constant (x));
10837 else if (GET_CODE (x) == NEG)
10838 abort (); /* This should never happen now. */
10841 fputc ('#', stream);
10842 output_addr_const (stream, x);
10847 #ifndef AOF_ASSEMBLER
10848 /* Target hook for assembling integer objects. The ARM version needs to
10849 handle word-sized values specially. */
10851 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10853 if (size == UNITS_PER_WORD && aligned_p)
10855 fputs ("\t.word\t", asm_out_file);
10856 output_addr_const (asm_out_file, x);
10858 /* Mark symbols as position independent. We only do this in the
10859 .text segment, not in the .data segment. */
10860 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10861 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10863 if (GET_CODE (x) == SYMBOL_REF
10864 && (CONSTANT_POOL_ADDRESS_P (x)
10865 || SYMBOL_REF_LOCAL_P (x)))
10866 fputs ("(GOTOFF)", asm_out_file);
10867 else if (GET_CODE (x) == LABEL_REF)
10868 fputs ("(GOTOFF)", asm_out_file);
10870 fputs ("(GOT)", asm_out_file);
10872 fputc ('\n', asm_out_file);
10876 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10880 if (GET_CODE (x) != CONST_VECTOR)
10883 units = CONST_VECTOR_NUNITS (x);
10885 switch (GET_MODE (x))
10887 case V2SImode: size = 4; break;
10888 case V4HImode: size = 2; break;
10889 case V8QImode: size = 1; break;
10894 for (i = 0; i < units; i++)
10898 elt = CONST_VECTOR_ELT (x, i);
10900 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10906 return default_assemble_integer (x, size, aligned_p);
10910 /* A finite state machine takes care of noticing whether or not instructions
10911 can be conditionally executed, and thus decrease execution time and code
10912 size by deleting branch instructions. The fsm is controlled by
10913 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10915 /* The state of the fsm controlling condition codes are:
10916 0: normal, do nothing special
10917 1: make ASM_OUTPUT_OPCODE not output this instruction
10918 2: make ASM_OUTPUT_OPCODE not output this instruction
10919 3: make instructions conditional
10920 4: make instructions conditional
10922 State transitions (state->state by whom under condition):
10923 0 -> 1 final_prescan_insn if the `target' is a label
10924 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10925 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10926 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10927 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10928 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10929 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10930 (the target insn is arm_target_insn).
10932 If the jump clobbers the conditions then we use states 2 and 4.
10934 A similar thing can be done with conditional return insns.
10936 XXX In case the `target' is an unconditional branch, this conditionalising
10937 of the instructions always reduces code size, but not always execution
10938 time. But then, I want to reduce the code size to somewhere near what
10939 /bin/cc produces. */
10941 /* Returns the index of the ARM condition code string in
10942 `arm_condition_codes'. COMPARISON should be an rtx like
10943 `(eq (...) (...))'. */
10944 static enum arm_cond_code
10945 get_arm_condition_code (rtx comparison)
10947 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10949 enum rtx_code comp_code = GET_CODE (comparison);
10951 if (GET_MODE_CLASS (mode) != MODE_CC)
10952 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10953 XEXP (comparison, 1));
10957 case CC_DNEmode: code = ARM_NE; goto dominance;
10958 case CC_DEQmode: code = ARM_EQ; goto dominance;
10959 case CC_DGEmode: code = ARM_GE; goto dominance;
10960 case CC_DGTmode: code = ARM_GT; goto dominance;
10961 case CC_DLEmode: code = ARM_LE; goto dominance;
10962 case CC_DLTmode: code = ARM_LT; goto dominance;
10963 case CC_DGEUmode: code = ARM_CS; goto dominance;
10964 case CC_DGTUmode: code = ARM_HI; goto dominance;
10965 case CC_DLEUmode: code = ARM_LS; goto dominance;
10966 case CC_DLTUmode: code = ARM_CC;
10969 if (comp_code != EQ && comp_code != NE)
10972 if (comp_code == EQ)
10973 return ARM_INVERSE_CONDITION_CODE (code);
10979 case NE: return ARM_NE;
10980 case EQ: return ARM_EQ;
10981 case GE: return ARM_PL;
10982 case LT: return ARM_MI;
10989 case NE: return ARM_NE;
10990 case EQ: return ARM_EQ;
10997 case NE: return ARM_MI;
10998 case EQ: return ARM_PL;
11004 /* These encodings assume that AC=1 in the FPA system control
11005 byte. This allows us to handle all cases except UNEQ and
11009 case GE: return ARM_GE;
11010 case GT: return ARM_GT;
11011 case LE: return ARM_LS;
11012 case LT: return ARM_MI;
11013 case NE: return ARM_NE;
11014 case EQ: return ARM_EQ;
11015 case ORDERED: return ARM_VC;
11016 case UNORDERED: return ARM_VS;
11017 case UNLT: return ARM_LT;
11018 case UNLE: return ARM_LE;
11019 case UNGT: return ARM_HI;
11020 case UNGE: return ARM_PL;
11021 /* UNEQ and LTGT do not have a representation. */
11022 case UNEQ: /* Fall through. */
11023 case LTGT: /* Fall through. */
11030 case NE: return ARM_NE;
11031 case EQ: return ARM_EQ;
11032 case GE: return ARM_LE;
11033 case GT: return ARM_LT;
11034 case LE: return ARM_GE;
11035 case LT: return ARM_GT;
11036 case GEU: return ARM_LS;
11037 case GTU: return ARM_CC;
11038 case LEU: return ARM_CS;
11039 case LTU: return ARM_HI;
11046 case LTU: return ARM_CS;
11047 case GEU: return ARM_CC;
11054 case NE: return ARM_NE;
11055 case EQ: return ARM_EQ;
11056 case GE: return ARM_GE;
11057 case GT: return ARM_GT;
11058 case LE: return ARM_LE;
11059 case LT: return ARM_LT;
11060 case GEU: return ARM_CS;
11061 case GTU: return ARM_HI;
11062 case LEU: return ARM_LS;
11063 case LTU: return ARM_CC;
11074 arm_final_prescan_insn (rtx insn)
11076 /* BODY will hold the body of INSN. */
11077 rtx body = PATTERN (insn);
11079 /* This will be 1 if trying to repeat the trick, and things need to be
11080 reversed if it appears to fail. */
11083 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11084 taken are clobbered, even if the rtl suggests otherwise. It also
11085 means that we have to grub around within the jump expression to find
11086 out what the conditions are when the jump isn't taken. */
11087 int jump_clobbers = 0;
11089 /* If we start with a return insn, we only succeed if we find another one. */
11090 int seeking_return = 0;
11092 /* START_INSN will hold the insn from where we start looking. This is the
11093 first insn after the following code_label if REVERSE is true. */
11094 rtx start_insn = insn;
11096 /* If in state 4, check if the target branch is reached, in order to
11097 change back to state 0. */
11098 if (arm_ccfsm_state == 4)
11100 if (insn == arm_target_insn)
11102 arm_target_insn = NULL;
11103 arm_ccfsm_state = 0;
11108 /* If in state 3, it is possible to repeat the trick, if this insn is an
11109 unconditional branch to a label, and immediately following this branch
11110 is the previous target label which is only used once, and the label this
11111 branch jumps to is not too far off. */
11112 if (arm_ccfsm_state == 3)
11114 if (simplejump_p (insn))
11116 start_insn = next_nonnote_insn (start_insn);
11117 if (GET_CODE (start_insn) == BARRIER)
11119 /* XXX Isn't this always a barrier? */
11120 start_insn = next_nonnote_insn (start_insn);
11122 if (GET_CODE (start_insn) == CODE_LABEL
11123 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11124 && LABEL_NUSES (start_insn) == 1)
11129 else if (GET_CODE (body) == RETURN)
11131 start_insn = next_nonnote_insn (start_insn);
11132 if (GET_CODE (start_insn) == BARRIER)
11133 start_insn = next_nonnote_insn (start_insn);
11134 if (GET_CODE (start_insn) == CODE_LABEL
11135 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11136 && LABEL_NUSES (start_insn) == 1)
11139 seeking_return = 1;
11148 if (arm_ccfsm_state != 0 && !reverse)
11150 if (GET_CODE (insn) != JUMP_INSN)
11153 /* This jump might be paralleled with a clobber of the condition codes
11154 the jump should always come first */
11155 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11156 body = XVECEXP (body, 0, 0);
11159 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11160 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11163 int fail = FALSE, succeed = FALSE;
11164 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11165 int then_not_else = TRUE;
11166 rtx this_insn = start_insn, label = 0;
11168 /* If the jump cannot be done with one instruction, we cannot
11169 conditionally execute the instruction in the inverse case. */
11170 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11176 /* Register the insn jumped to. */
11179 if (!seeking_return)
11180 label = XEXP (SET_SRC (body), 0);
11182 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11183 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11184 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11186 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11187 then_not_else = FALSE;
11189 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11190 seeking_return = 1;
11191 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11193 seeking_return = 1;
11194 then_not_else = FALSE;
11199 /* See how many insns this branch skips, and what kind of insns. If all
11200 insns are okay, and the label or unconditional branch to the same
11201 label is not too far away, succeed. */
11202 for (insns_skipped = 0;
11203 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11207 this_insn = next_nonnote_insn (this_insn);
11211 switch (GET_CODE (this_insn))
11214 /* Succeed if it is the target label, otherwise fail since
11215 control falls in from somewhere else. */
11216 if (this_insn == label)
11220 arm_ccfsm_state = 2;
11221 this_insn = next_nonnote_insn (this_insn);
11224 arm_ccfsm_state = 1;
11232 /* Succeed if the following insn is the target label.
11234 If return insns are used then the last insn in a function
11235 will be a barrier. */
11236 this_insn = next_nonnote_insn (this_insn);
11237 if (this_insn && this_insn == label)
11241 arm_ccfsm_state = 2;
11242 this_insn = next_nonnote_insn (this_insn);
11245 arm_ccfsm_state = 1;
11253 /* Succeed if the following insn is the target label, or
11254 if the following two insns are a barrier and the
11256 this_insn = next_nonnote_insn (this_insn);
11257 if (this_insn && GET_CODE (this_insn) == BARRIER)
11258 this_insn = next_nonnote_insn (this_insn);
11260 if (this_insn && this_insn == label
11261 && insns_skipped < max_insns_skipped)
11265 arm_ccfsm_state = 2;
11266 this_insn = next_nonnote_insn (this_insn);
11269 arm_ccfsm_state = 1;
11277 /* If this is an unconditional branch to the same label, succeed.
11278 If it is to another label, do nothing. If it is conditional,
11280 /* XXX Probably, the tests for SET and the PC are
11283 scanbody = PATTERN (this_insn);
11284 if (GET_CODE (scanbody) == SET
11285 && GET_CODE (SET_DEST (scanbody)) == PC)
11287 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11288 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11290 arm_ccfsm_state = 2;
11293 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11296 /* Fail if a conditional return is undesirable (eg on a
11297 StrongARM), but still allow this if optimizing for size. */
11298 else if (GET_CODE (scanbody) == RETURN
11299 && !use_return_insn (TRUE, NULL)
11302 else if (GET_CODE (scanbody) == RETURN
11305 arm_ccfsm_state = 2;
11308 else if (GET_CODE (scanbody) == PARALLEL)
11310 switch (get_attr_conds (this_insn))
11320 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11325 /* Instructions using or affecting the condition codes make it
11327 scanbody = PATTERN (this_insn);
11328 if (!(GET_CODE (scanbody) == SET
11329 || GET_CODE (scanbody) == PARALLEL)
11330 || get_attr_conds (this_insn) != CONDS_NOCOND)
11333 /* A conditional cirrus instruction must be followed by
11334 a non Cirrus instruction. However, since we
11335 conditionalize instructions in this function and by
11336 the time we get here we can't add instructions
11337 (nops), because shorten_branches() has already been
11338 called, we will disable conditionalizing Cirrus
11339 instructions to be safe. */
11340 if (GET_CODE (scanbody) != USE
11341 && GET_CODE (scanbody) != CLOBBER
11342 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11352 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11353 arm_target_label = CODE_LABEL_NUMBER (label);
11354 else if (seeking_return || arm_ccfsm_state == 2)
11356 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11358 this_insn = next_nonnote_insn (this_insn);
11359 if (this_insn && (GET_CODE (this_insn) == BARRIER
11360 || GET_CODE (this_insn) == CODE_LABEL))
11365 /* Oh, dear! we ran off the end.. give up. */
11366 recog (PATTERN (insn), insn, NULL);
11367 arm_ccfsm_state = 0;
11368 arm_target_insn = NULL;
11371 arm_target_insn = this_insn;
11380 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11382 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11383 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11384 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11385 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11389 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11392 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11396 if (reverse || then_not_else)
11397 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11400 /* Restore recog_data (getting the attributes of other insns can
11401 destroy this array, but final.c assumes that it remains intact
11402 across this call; since the insn has been recognized already we
11403 call recog direct). */
11404 recog (PATTERN (insn), insn, NULL);
11408 /* Returns true if REGNO is a valid register
11409 for holding a quantity of tyoe MODE. */
11411 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11413 if (GET_MODE_CLASS (mode) == MODE_CC)
11414 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11417 /* For the Thumb we only allow values bigger than SImode in
11418 registers 0 - 6, so that there is always a second low
11419 register available to hold the upper part of the value.
11420 We probably we ought to ensure that the register is the
11421 start of an even numbered register pair. */
11422 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11424 if (IS_CIRRUS_REGNUM (regno))
11425 /* We have outlawed SI values in Cirrus registers because they
11426 reside in the lower 32 bits, but SF values reside in the
11427 upper 32 bits. This causes gcc all sorts of grief. We can't
11428 even split the registers into pairs because Cirrus SI values
11429 get sign extended to 64bits-- aldyh. */
11430 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11432 if (IS_VFP_REGNUM (regno))
11434 if (mode == SFmode || mode == SImode)
11437 /* DFmode values are only valid in even register pairs. */
11438 if (mode == DFmode)
11439 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11443 if (IS_IWMMXT_GR_REGNUM (regno))
11444 return mode == SImode;
11446 if (IS_IWMMXT_REGNUM (regno))
11447 return VALID_IWMMXT_REG_MODE (mode);
11449 /* We allow any value to be stored in the general registers.
11450 Restrict doubleword quantities to even register pairs so that we can
11452 if (regno <= LAST_ARM_REGNUM)
11453 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11455 if ( regno == FRAME_POINTER_REGNUM
11456 || regno == ARG_POINTER_REGNUM)
11457 /* We only allow integers in the fake hard registers. */
11458 return GET_MODE_CLASS (mode) == MODE_INT;
11460 /* The only registers left are the FPA registers
11461 which we only allow to hold FP values. */
11462 return GET_MODE_CLASS (mode) == MODE_FLOAT
11463 && regno >= FIRST_FPA_REGNUM
11464 && regno <= LAST_FPA_REGNUM;
11468 arm_regno_class (int regno)
11472 if (regno == STACK_POINTER_REGNUM)
11474 if (regno == CC_REGNUM)
11481 if ( regno <= LAST_ARM_REGNUM
11482 || regno == FRAME_POINTER_REGNUM
11483 || regno == ARG_POINTER_REGNUM)
11484 return GENERAL_REGS;
11486 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11489 if (IS_CIRRUS_REGNUM (regno))
11490 return CIRRUS_REGS;
11492 if (IS_VFP_REGNUM (regno))
11495 if (IS_IWMMXT_REGNUM (regno))
11496 return IWMMXT_REGS;
11498 if (IS_IWMMXT_GR_REGNUM (regno))
11499 return IWMMXT_GR_REGS;
11504 /* Handle a special case when computing the offset
11505 of an argument from the frame pointer. */
11507 arm_debugger_arg_offset (int value, rtx addr)
11511 /* We are only interested if dbxout_parms() failed to compute the offset. */
11515 /* We can only cope with the case where the address is held in a register. */
11516 if (GET_CODE (addr) != REG)
11519 /* If we are using the frame pointer to point at the argument, then
11520 an offset of 0 is correct. */
11521 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11524 /* If we are using the stack pointer to point at the
11525 argument, then an offset of 0 is correct. */
11526 if ((TARGET_THUMB || !frame_pointer_needed)
11527 && REGNO (addr) == SP_REGNUM)
11530 /* Oh dear. The argument is pointed to by a register rather
11531 than being held in a register, or being stored at a known
11532 offset from the frame pointer. Since GDB only understands
11533 those two kinds of argument we must translate the address
11534 held in the register into an offset from the frame pointer.
11535 We do this by searching through the insns for the function
11536 looking to see where this register gets its value. If the
11537 register is initialized from the frame pointer plus an offset
11538 then we are in luck and we can continue, otherwise we give up.
11540 This code is exercised by producing debugging information
11541 for a function with arguments like this:
11543 double func (double a, double b, int c, double d) {return d;}
11545 Without this code the stab for parameter 'd' will be set to
11546 an offset of 0 from the frame pointer, rather than 8. */
11548 /* The if() statement says:
11550 If the insn is a normal instruction
11551 and if the insn is setting the value in a register
11552 and if the register being set is the register holding the address of the argument
11553 and if the address is computing by an addition
11554 that involves adding to a register
11555 which is the frame pointer
11560 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11562 if ( GET_CODE (insn) == INSN
11563 && GET_CODE (PATTERN (insn)) == SET
11564 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11565 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11566 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11567 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11568 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11571 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11580 warning ("unable to compute real location of stacked parameter");
11581 value = 8; /* XXX magic hack */
11587 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11590 if ((MASK) & insn_flags) \
11591 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11595 struct builtin_description
11597 const unsigned int mask;
11598 const enum insn_code icode;
11599 const char * const name;
11600 const enum arm_builtins code;
11601 const enum rtx_code comparison;
11602 const unsigned int flag;
11605 static const struct builtin_description bdesc_2arg[] =
11607 #define IWMMXT_BUILTIN(code, string, builtin) \
11608 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11609 ARM_BUILTIN_##builtin, 0, 0 },
11611 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11612 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11613 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11614 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11615 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11616 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11617 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11618 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11619 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11620 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11621 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11622 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11623 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11624 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11625 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11626 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11627 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11628 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11629 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11630 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11631 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11632 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11633 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11634 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11635 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11636 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11637 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11638 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11639 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11640 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11641 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11642 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11643 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11644 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11645 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11646 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11647 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11648 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11649 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11650 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11651 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11652 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11653 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11654 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11655 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11656 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11657 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11658 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11659 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11660 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11661 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11662 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11663 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11664 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11665 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11666 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11667 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11668 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11670 #define IWMMXT_BUILTIN2(code, builtin) \
11671 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11673 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11674 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11675 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11676 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11677 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11678 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11679 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11680 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11681 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11682 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11683 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11684 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11685 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11686 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11687 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11688 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11689 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11690 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11691 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11692 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11693 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11694 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11695 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11696 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11697 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11698 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11699 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11700 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11701 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11702 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11703 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11704 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11707 static const struct builtin_description bdesc_1arg[] =
11709 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11710 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11711 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11712 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11713 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11714 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11715 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11716 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11717 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11718 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11719 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11720 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11721 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11722 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11723 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11724 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11725 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11726 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11729 /* Set up all the iWMMXt builtins. This is
11730 not called if TARGET_IWMMXT is zero. */
11733 arm_init_iwmmxt_builtins (void)
11735 const struct builtin_description * d;
11737 tree endlink = void_list_node;
11739 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11740 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11741 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11744 = build_function_type (integer_type_node,
11745 tree_cons (NULL_TREE, integer_type_node, endlink));
11746 tree v8qi_ftype_v8qi_v8qi_int
11747 = build_function_type (V8QI_type_node,
11748 tree_cons (NULL_TREE, V8QI_type_node,
11749 tree_cons (NULL_TREE, V8QI_type_node,
11750 tree_cons (NULL_TREE,
11753 tree v4hi_ftype_v4hi_int
11754 = build_function_type (V4HI_type_node,
11755 tree_cons (NULL_TREE, V4HI_type_node,
11756 tree_cons (NULL_TREE, integer_type_node,
11758 tree v2si_ftype_v2si_int
11759 = build_function_type (V2SI_type_node,
11760 tree_cons (NULL_TREE, V2SI_type_node,
11761 tree_cons (NULL_TREE, integer_type_node,
11763 tree v2si_ftype_di_di
11764 = build_function_type (V2SI_type_node,
11765 tree_cons (NULL_TREE, long_long_integer_type_node,
11766 tree_cons (NULL_TREE, long_long_integer_type_node,
11768 tree di_ftype_di_int
11769 = build_function_type (long_long_integer_type_node,
11770 tree_cons (NULL_TREE, long_long_integer_type_node,
11771 tree_cons (NULL_TREE, integer_type_node,
11773 tree di_ftype_di_int_int
11774 = build_function_type (long_long_integer_type_node,
11775 tree_cons (NULL_TREE, long_long_integer_type_node,
11776 tree_cons (NULL_TREE, integer_type_node,
11777 tree_cons (NULL_TREE,
11780 tree int_ftype_v8qi
11781 = build_function_type (integer_type_node,
11782 tree_cons (NULL_TREE, V8QI_type_node,
11784 tree int_ftype_v4hi
11785 = build_function_type (integer_type_node,
11786 tree_cons (NULL_TREE, V4HI_type_node,
11788 tree int_ftype_v2si
11789 = build_function_type (integer_type_node,
11790 tree_cons (NULL_TREE, V2SI_type_node,
11792 tree int_ftype_v8qi_int
11793 = build_function_type (integer_type_node,
11794 tree_cons (NULL_TREE, V8QI_type_node,
11795 tree_cons (NULL_TREE, integer_type_node,
11797 tree int_ftype_v4hi_int
11798 = build_function_type (integer_type_node,
11799 tree_cons (NULL_TREE, V4HI_type_node,
11800 tree_cons (NULL_TREE, integer_type_node,
11802 tree int_ftype_v2si_int
11803 = build_function_type (integer_type_node,
11804 tree_cons (NULL_TREE, V2SI_type_node,
11805 tree_cons (NULL_TREE, integer_type_node,
11807 tree v8qi_ftype_v8qi_int_int
11808 = build_function_type (V8QI_type_node,
11809 tree_cons (NULL_TREE, V8QI_type_node,
11810 tree_cons (NULL_TREE, integer_type_node,
11811 tree_cons (NULL_TREE,
11814 tree v4hi_ftype_v4hi_int_int
11815 = build_function_type (V4HI_type_node,
11816 tree_cons (NULL_TREE, V4HI_type_node,
11817 tree_cons (NULL_TREE, integer_type_node,
11818 tree_cons (NULL_TREE,
11821 tree v2si_ftype_v2si_int_int
11822 = build_function_type (V2SI_type_node,
11823 tree_cons (NULL_TREE, V2SI_type_node,
11824 tree_cons (NULL_TREE, integer_type_node,
11825 tree_cons (NULL_TREE,
11828 /* Miscellaneous. */
11829 tree v8qi_ftype_v4hi_v4hi
11830 = build_function_type (V8QI_type_node,
11831 tree_cons (NULL_TREE, V4HI_type_node,
11832 tree_cons (NULL_TREE, V4HI_type_node,
11834 tree v4hi_ftype_v2si_v2si
11835 = build_function_type (V4HI_type_node,
11836 tree_cons (NULL_TREE, V2SI_type_node,
11837 tree_cons (NULL_TREE, V2SI_type_node,
11839 tree v2si_ftype_v4hi_v4hi
11840 = build_function_type (V2SI_type_node,
11841 tree_cons (NULL_TREE, V4HI_type_node,
11842 tree_cons (NULL_TREE, V4HI_type_node,
11844 tree v2si_ftype_v8qi_v8qi
11845 = build_function_type (V2SI_type_node,
11846 tree_cons (NULL_TREE, V8QI_type_node,
11847 tree_cons (NULL_TREE, V8QI_type_node,
11849 tree v4hi_ftype_v4hi_di
11850 = build_function_type (V4HI_type_node,
11851 tree_cons (NULL_TREE, V4HI_type_node,
11852 tree_cons (NULL_TREE,
11853 long_long_integer_type_node,
11855 tree v2si_ftype_v2si_di
11856 = build_function_type (V2SI_type_node,
11857 tree_cons (NULL_TREE, V2SI_type_node,
11858 tree_cons (NULL_TREE,
11859 long_long_integer_type_node,
11861 tree void_ftype_int_int
11862 = build_function_type (void_type_node,
11863 tree_cons (NULL_TREE, integer_type_node,
11864 tree_cons (NULL_TREE, integer_type_node,
11867 = build_function_type (long_long_unsigned_type_node, endlink);
11869 = build_function_type (long_long_integer_type_node,
11870 tree_cons (NULL_TREE, V8QI_type_node,
11873 = build_function_type (long_long_integer_type_node,
11874 tree_cons (NULL_TREE, V4HI_type_node,
11877 = build_function_type (long_long_integer_type_node,
11878 tree_cons (NULL_TREE, V2SI_type_node,
11880 tree v2si_ftype_v4hi
11881 = build_function_type (V2SI_type_node,
11882 tree_cons (NULL_TREE, V4HI_type_node,
11884 tree v4hi_ftype_v8qi
11885 = build_function_type (V4HI_type_node,
11886 tree_cons (NULL_TREE, V8QI_type_node,
11889 tree di_ftype_di_v4hi_v4hi
11890 = build_function_type (long_long_unsigned_type_node,
11891 tree_cons (NULL_TREE,
11892 long_long_unsigned_type_node,
11893 tree_cons (NULL_TREE, V4HI_type_node,
11894 tree_cons (NULL_TREE,
11898 tree di_ftype_v4hi_v4hi
11899 = build_function_type (long_long_unsigned_type_node,
11900 tree_cons (NULL_TREE, V4HI_type_node,
11901 tree_cons (NULL_TREE, V4HI_type_node,
11904 /* Normal vector binops. */
11905 tree v8qi_ftype_v8qi_v8qi
11906 = build_function_type (V8QI_type_node,
11907 tree_cons (NULL_TREE, V8QI_type_node,
11908 tree_cons (NULL_TREE, V8QI_type_node,
11910 tree v4hi_ftype_v4hi_v4hi
11911 = build_function_type (V4HI_type_node,
11912 tree_cons (NULL_TREE, V4HI_type_node,
11913 tree_cons (NULL_TREE, V4HI_type_node,
11915 tree v2si_ftype_v2si_v2si
11916 = build_function_type (V2SI_type_node,
11917 tree_cons (NULL_TREE, V2SI_type_node,
11918 tree_cons (NULL_TREE, V2SI_type_node,
11920 tree di_ftype_di_di
11921 = build_function_type (long_long_unsigned_type_node,
11922 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11923 tree_cons (NULL_TREE,
11924 long_long_unsigned_type_node,
11927 /* Add all builtins that are more or less simple operations on two
11929 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11931 /* Use one of the operands; the target can have a different mode for
11932 mask-generating compares. */
11933 enum machine_mode mode;
11939 mode = insn_data[d->icode].operand[1].mode;
11944 type = v8qi_ftype_v8qi_v8qi;
11947 type = v4hi_ftype_v4hi_v4hi;
11950 type = v2si_ftype_v2si_v2si;
11953 type = di_ftype_di_di;
11960 def_mbuiltin (d->mask, d->name, type, d->code);
11963 /* Add the remaining MMX insns with somewhat more complicated types. */
11964 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11965 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11966 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11968 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11969 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11970 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11971 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11972 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11973 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11977 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11978 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11983 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11984 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11985 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11991 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11998 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12005 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12006 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12013 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12015 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12019 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12022 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12026 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12056 arm_init_builtins (void)
12058 if (TARGET_REALLY_IWMMXT)
12059 arm_init_iwmmxt_builtins ();
12062 /* Errors in the source file can cause expand_expr to return const0_rtx
12063 where we expect a vector. To avoid crashing, use one of the vector
12064 clear instructions. */
12067 safe_vector_operand (rtx x, enum machine_mode mode)
12069 if (x != const0_rtx)
12071 x = gen_reg_rtx (mode);
12073 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12074 : gen_rtx_SUBREG (DImode, x, 0)));
12078 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12081 arm_expand_binop_builtin (enum insn_code icode,
12082 tree arglist, rtx target)
12085 tree arg0 = TREE_VALUE (arglist);
12086 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12087 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12088 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12089 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12090 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12091 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12093 if (VECTOR_MODE_P (mode0))
12094 op0 = safe_vector_operand (op0, mode0);
12095 if (VECTOR_MODE_P (mode1))
12096 op1 = safe_vector_operand (op1, mode1);
12099 || GET_MODE (target) != tmode
12100 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12101 target = gen_reg_rtx (tmode);
12103 /* In case the insn wants input operands in modes different from
12104 the result, abort. */
12105 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12108 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12109 op0 = copy_to_mode_reg (mode0, op0);
12110 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12111 op1 = copy_to_mode_reg (mode1, op1);
12113 pat = GEN_FCN (icode) (target, op0, op1);
12120 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12123 arm_expand_unop_builtin (enum insn_code icode,
12124 tree arglist, rtx target, int do_load)
12127 tree arg0 = TREE_VALUE (arglist);
12128 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12129 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12130 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12133 || GET_MODE (target) != tmode
12134 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12135 target = gen_reg_rtx (tmode);
12137 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12140 if (VECTOR_MODE_P (mode0))
12141 op0 = safe_vector_operand (op0, mode0);
12143 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12144 op0 = copy_to_mode_reg (mode0, op0);
12147 pat = GEN_FCN (icode) (target, op0);
12154 /* Expand an expression EXP that calls a built-in function,
12155 with result going to TARGET if that's convenient
12156 (and in mode MODE if that's convenient).
12157 SUBTARGET may be used as the target for computing one of EXP's operands.
12158 IGNORE is nonzero if the value is to be ignored. */
12161 arm_expand_builtin (tree exp,
12163 rtx subtarget ATTRIBUTE_UNUSED,
12164 enum machine_mode mode ATTRIBUTE_UNUSED,
12165 int ignore ATTRIBUTE_UNUSED)
12167 const struct builtin_description * d;
12168 enum insn_code icode;
12169 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12170 tree arglist = TREE_OPERAND (exp, 1);
12178 int fcode = DECL_FUNCTION_CODE (fndecl);
12180 enum machine_mode tmode;
12181 enum machine_mode mode0;
12182 enum machine_mode mode1;
12183 enum machine_mode mode2;
12187 case ARM_BUILTIN_TEXTRMSB:
12188 case ARM_BUILTIN_TEXTRMUB:
12189 case ARM_BUILTIN_TEXTRMSH:
12190 case ARM_BUILTIN_TEXTRMUH:
12191 case ARM_BUILTIN_TEXTRMSW:
12192 case ARM_BUILTIN_TEXTRMUW:
12193 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12194 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12195 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12196 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12197 : CODE_FOR_iwmmxt_textrmw);
12199 arg0 = TREE_VALUE (arglist);
12200 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12201 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12202 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12203 tmode = insn_data[icode].operand[0].mode;
12204 mode0 = insn_data[icode].operand[1].mode;
12205 mode1 = insn_data[icode].operand[2].mode;
12207 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12208 op0 = copy_to_mode_reg (mode0, op0);
12209 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12211 /* @@@ better error message */
12212 error ("selector must be an immediate");
12213 return gen_reg_rtx (tmode);
12216 || GET_MODE (target) != tmode
12217 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12218 target = gen_reg_rtx (tmode);
12219 pat = GEN_FCN (icode) (target, op0, op1);
12225 case ARM_BUILTIN_TINSRB:
12226 case ARM_BUILTIN_TINSRH:
12227 case ARM_BUILTIN_TINSRW:
12228 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12229 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12230 : CODE_FOR_iwmmxt_tinsrw);
12231 arg0 = TREE_VALUE (arglist);
12232 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12233 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12234 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12235 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12236 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12237 tmode = insn_data[icode].operand[0].mode;
12238 mode0 = insn_data[icode].operand[1].mode;
12239 mode1 = insn_data[icode].operand[2].mode;
12240 mode2 = insn_data[icode].operand[3].mode;
12242 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12243 op0 = copy_to_mode_reg (mode0, op0);
12244 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12245 op1 = copy_to_mode_reg (mode1, op1);
12246 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12248 /* @@@ better error message */
12249 error ("selector must be an immediate");
12253 || GET_MODE (target) != tmode
12254 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12255 target = gen_reg_rtx (tmode);
12256 pat = GEN_FCN (icode) (target, op0, op1, op2);
12262 case ARM_BUILTIN_SETWCX:
12263 arg0 = TREE_VALUE (arglist);
12264 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12265 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12266 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12267 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12270 case ARM_BUILTIN_GETWCX:
12271 arg0 = TREE_VALUE (arglist);
12272 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12273 target = gen_reg_rtx (SImode);
12274 emit_insn (gen_iwmmxt_tmrc (target, op0));
12277 case ARM_BUILTIN_WSHUFH:
12278 icode = CODE_FOR_iwmmxt_wshufh;
12279 arg0 = TREE_VALUE (arglist);
12280 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12281 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12282 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12283 tmode = insn_data[icode].operand[0].mode;
12284 mode1 = insn_data[icode].operand[1].mode;
12285 mode2 = insn_data[icode].operand[2].mode;
12287 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12288 op0 = copy_to_mode_reg (mode1, op0);
12289 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12291 /* @@@ better error message */
12292 error ("mask must be an immediate");
12296 || GET_MODE (target) != tmode
12297 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12298 target = gen_reg_rtx (tmode);
12299 pat = GEN_FCN (icode) (target, op0, op1);
12305 case ARM_BUILTIN_WSADB:
12306 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12307 case ARM_BUILTIN_WSADH:
12308 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12309 case ARM_BUILTIN_WSADBZ:
12310 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12311 case ARM_BUILTIN_WSADHZ:
12312 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12314 /* Several three-argument builtins. */
12315 case ARM_BUILTIN_WMACS:
12316 case ARM_BUILTIN_WMACU:
12317 case ARM_BUILTIN_WALIGN:
12318 case ARM_BUILTIN_TMIA:
12319 case ARM_BUILTIN_TMIAPH:
12320 case ARM_BUILTIN_TMIATT:
12321 case ARM_BUILTIN_TMIATB:
12322 case ARM_BUILTIN_TMIABT:
12323 case ARM_BUILTIN_TMIABB:
12324 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12325 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12326 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12327 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12328 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12329 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12330 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12331 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12332 : CODE_FOR_iwmmxt_walign);
12333 arg0 = TREE_VALUE (arglist);
12334 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12335 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12336 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12337 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12338 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12339 tmode = insn_data[icode].operand[0].mode;
12340 mode0 = insn_data[icode].operand[1].mode;
12341 mode1 = insn_data[icode].operand[2].mode;
12342 mode2 = insn_data[icode].operand[3].mode;
12344 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12345 op0 = copy_to_mode_reg (mode0, op0);
12346 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12347 op1 = copy_to_mode_reg (mode1, op1);
12348 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12349 op2 = copy_to_mode_reg (mode2, op2);
12351 || GET_MODE (target) != tmode
12352 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12353 target = gen_reg_rtx (tmode);
12354 pat = GEN_FCN (icode) (target, op0, op1, op2);
12360 case ARM_BUILTIN_WZERO:
12361 target = gen_reg_rtx (DImode);
12362 emit_insn (gen_iwmmxt_clrdi (target));
12369 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12370 if (d->code == (const enum arm_builtins) fcode)
12371 return arm_expand_binop_builtin (d->icode, arglist, target);
12373 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12374 if (d->code == (const enum arm_builtins) fcode)
12375 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12377 /* @@@ Should really do something sensible here. */
12381 /* Recursively search through all of the blocks in a function
12382 checking to see if any of the variables created in that
12383 function match the RTX called 'orig'. If they do then
12384 replace them with the RTX called 'new'. */
12386 replace_symbols_in_block (tree block, rtx orig, rtx new)
12388 for (; block; block = BLOCK_CHAIN (block))
12392 if (!TREE_USED (block))
12395 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12397 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12398 || DECL_IGNORED_P (sym)
12399 || TREE_CODE (sym) != VAR_DECL
12400 || DECL_EXTERNAL (sym)
12401 || !rtx_equal_p (DECL_RTL (sym), orig)
12405 SET_DECL_RTL (sym, new);
12408 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12412 /* Return the number (counting from 0) of
12413 the least significant set bit in MASK. */
12416 number_of_first_bit_set (int mask)
12421 (mask & (1 << bit)) == 0;
12428 /* Generate code to return from a thumb function.
12429 If 'reg_containing_return_addr' is -1, then the return address is
12430 actually on the stack, at the stack pointer. */
12432 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12434 unsigned regs_available_for_popping;
12435 unsigned regs_to_pop;
12437 unsigned available;
12441 int restore_a4 = FALSE;
12443 /* Compute the registers we need to pop. */
12447 /* There is an assumption here, that if eh_ofs is not NULL, the
12448 normal return address will have been pushed. */
12449 if (reg_containing_return_addr == -1 || eh_ofs)
12451 /* When we are generating a return for __builtin_eh_return,
12452 reg_containing_return_addr must specify the return regno. */
12453 if (eh_ofs && reg_containing_return_addr == -1)
12456 regs_to_pop |= 1 << LR_REGNUM;
12460 if (TARGET_BACKTRACE)
12462 /* Restore the (ARM) frame pointer and stack pointer. */
12463 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12467 /* If there is nothing to pop then just emit the BX instruction and
12469 if (pops_needed == 0)
12472 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12474 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12477 /* Otherwise if we are not supporting interworking and we have not created
12478 a backtrace structure and the function was not entered in ARM mode then
12479 just pop the return address straight into the PC. */
12480 else if (!TARGET_INTERWORK
12481 && !TARGET_BACKTRACE
12482 && !is_called_in_ARM_mode (current_function_decl))
12486 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12487 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12488 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12491 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12496 /* Find out how many of the (return) argument registers we can corrupt. */
12497 regs_available_for_popping = 0;
12499 /* If returning via __builtin_eh_return, the bottom three registers
12500 all contain information needed for the return. */
12505 /* If we can deduce the registers used from the function's
12506 return value. This is more reliable that examining
12507 regs_ever_live[] because that will be set if the register is
12508 ever used in the function, not just if the register is used
12509 to hold a return value. */
12511 if (current_function_return_rtx != 0)
12512 mode = GET_MODE (current_function_return_rtx);
12514 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12516 size = GET_MODE_SIZE (mode);
12520 /* In a void function we can use any argument register.
12521 In a function that returns a structure on the stack
12522 we can use the second and third argument registers. */
12523 if (mode == VOIDmode)
12524 regs_available_for_popping =
12525 (1 << ARG_REGISTER (1))
12526 | (1 << ARG_REGISTER (2))
12527 | (1 << ARG_REGISTER (3));
12529 regs_available_for_popping =
12530 (1 << ARG_REGISTER (2))
12531 | (1 << ARG_REGISTER (3));
12533 else if (size <= 4)
12534 regs_available_for_popping =
12535 (1 << ARG_REGISTER (2))
12536 | (1 << ARG_REGISTER (3));
12537 else if (size <= 8)
12538 regs_available_for_popping =
12539 (1 << ARG_REGISTER (3));
12542 /* Match registers to be popped with registers into which we pop them. */
12543 for (available = regs_available_for_popping,
12544 required = regs_to_pop;
12545 required != 0 && available != 0;
12546 available &= ~(available & - available),
12547 required &= ~(required & - required))
12550 /* If we have any popping registers left over, remove them. */
12552 regs_available_for_popping &= ~available;
12554 /* Otherwise if we need another popping register we can use
12555 the fourth argument register. */
12556 else if (pops_needed)
12558 /* If we have not found any free argument registers and
12559 reg a4 contains the return address, we must move it. */
12560 if (regs_available_for_popping == 0
12561 && reg_containing_return_addr == LAST_ARG_REGNUM)
12563 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12564 reg_containing_return_addr = LR_REGNUM;
12566 else if (size > 12)
12568 /* Register a4 is being used to hold part of the return value,
12569 but we have dire need of a free, low register. */
12572 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12575 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12577 /* The fourth argument register is available. */
12578 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12584 /* Pop as many registers as we can. */
12585 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12586 regs_available_for_popping);
12588 /* Process the registers we popped. */
12589 if (reg_containing_return_addr == -1)
12591 /* The return address was popped into the lowest numbered register. */
12592 regs_to_pop &= ~(1 << LR_REGNUM);
12594 reg_containing_return_addr =
12595 number_of_first_bit_set (regs_available_for_popping);
12597 /* Remove this register for the mask of available registers, so that
12598 the return address will not be corrupted by further pops. */
12599 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12602 /* If we popped other registers then handle them here. */
12603 if (regs_available_for_popping)
12607 /* Work out which register currently contains the frame pointer. */
12608 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12610 /* Move it into the correct place. */
12611 asm_fprintf (f, "\tmov\t%r, %r\n",
12612 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12614 /* (Temporarily) remove it from the mask of popped registers. */
12615 regs_available_for_popping &= ~(1 << frame_pointer);
12616 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12618 if (regs_available_for_popping)
12622 /* We popped the stack pointer as well,
12623 find the register that contains it. */
12624 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12626 /* Move it into the stack register. */
12627 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12629 /* At this point we have popped all necessary registers, so
12630 do not worry about restoring regs_available_for_popping
12631 to its correct value:
12633 assert (pops_needed == 0)
12634 assert (regs_available_for_popping == (1 << frame_pointer))
12635 assert (regs_to_pop == (1 << STACK_POINTER)) */
12639 /* Since we have just move the popped value into the frame
12640 pointer, the popping register is available for reuse, and
12641 we know that we still have the stack pointer left to pop. */
12642 regs_available_for_popping |= (1 << frame_pointer);
12646 /* If we still have registers left on the stack, but we no longer have
12647 any registers into which we can pop them, then we must move the return
12648 address into the link register and make available the register that
12650 if (regs_available_for_popping == 0 && pops_needed > 0)
12652 regs_available_for_popping |= 1 << reg_containing_return_addr;
12654 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12655 reg_containing_return_addr);
12657 reg_containing_return_addr = LR_REGNUM;
12660 /* If we have registers left on the stack then pop some more.
12661 We know that at most we will want to pop FP and SP. */
12662 if (pops_needed > 0)
12667 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12668 regs_available_for_popping);
12670 /* We have popped either FP or SP.
12671 Move whichever one it is into the correct register. */
12672 popped_into = number_of_first_bit_set (regs_available_for_popping);
12673 move_to = number_of_first_bit_set (regs_to_pop);
12675 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12677 regs_to_pop &= ~(1 << move_to);
12682 /* If we still have not popped everything then we must have only
12683 had one register available to us and we are now popping the SP. */
12684 if (pops_needed > 0)
12688 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12689 regs_available_for_popping);
12691 popped_into = number_of_first_bit_set (regs_available_for_popping);
12693 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12695 assert (regs_to_pop == (1 << STACK_POINTER))
12696 assert (pops_needed == 1)
12700 /* If necessary restore the a4 register. */
12703 if (reg_containing_return_addr != LR_REGNUM)
12705 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12706 reg_containing_return_addr = LR_REGNUM;
12709 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12713 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12715 /* Return to caller. */
12716 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12719 /* Emit code to push or pop registers to or from the stack. F is the
12720 assembly file. MASK is the registers to push or pop. PUSH is
12721 nonzero if we should push, and zero if we should pop. For debugging
12722 output, if pushing, adjust CFA_OFFSET by the amount of space added
12723 to the stack. REAL_REGS should have the same number of bits set as
12724 MASK, and will be used instead (in the same order) to describe which
12725 registers were saved - this is used to mark the save slots when we
12726 push high registers after moving them to low registers. */
12728 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12731 int lo_mask = mask & 0xFF;
12732 int pushed_words = 0;
12734 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12736 /* Special case. Do not generate a POP PC statement here, do it in
12738 thumb_exit (f, -1, NULL_RTX);
12742 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12744 /* Look at the low registers first. */
12745 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12749 asm_fprintf (f, "%r", regno);
12751 if ((lo_mask & ~1) != 0)
12758 if (push && (mask & (1 << LR_REGNUM)))
12760 /* Catch pushing the LR. */
12764 asm_fprintf (f, "%r", LR_REGNUM);
12768 else if (!push && (mask & (1 << PC_REGNUM)))
12770 /* Catch popping the PC. */
12771 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12773 /* The PC is never poped directly, instead
12774 it is popped into r3 and then BX is used. */
12775 fprintf (f, "}\n");
12777 thumb_exit (f, -1, NULL_RTX);
12786 asm_fprintf (f, "%r", PC_REGNUM);
12790 fprintf (f, "}\n");
12792 if (push && pushed_words && dwarf2out_do_frame ())
12794 char *l = dwarf2out_cfi_label ();
12795 int pushed_mask = real_regs;
12797 *cfa_offset += pushed_words * 4;
12798 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12801 pushed_mask = real_regs;
12802 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12804 if (pushed_mask & 1)
12805 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12811 thumb_final_prescan_insn (rtx insn)
12813 if (flag_print_asm_name)
12814 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12815 INSN_ADDRESSES (INSN_UID (insn)));
12819 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12821 unsigned HOST_WIDE_INT mask = 0xff;
12824 if (val == 0) /* XXX */
12827 for (i = 0; i < 25; i++)
12828 if ((val & (mask << i)) == val)
12834 /* Returns nonzero if the current function contains,
12835 or might contain a far jump. */
12837 thumb_far_jump_used_p (void)
12841 /* This test is only important for leaf functions. */
12842 /* assert (!leaf_function_p ()); */
12844 /* If we have already decided that far jumps may be used,
12845 do not bother checking again, and always return true even if
12846 it turns out that they are not being used. Once we have made
12847 the decision that far jumps are present (and that hence the link
12848 register will be pushed onto the stack) we cannot go back on it. */
12849 if (cfun->machine->far_jump_used)
12852 /* If this function is not being called from the prologue/epilogue
12853 generation code then it must be being called from the
12854 INITIAL_ELIMINATION_OFFSET macro. */
12855 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12857 /* In this case we know that we are being asked about the elimination
12858 of the arg pointer register. If that register is not being used,
12859 then there are no arguments on the stack, and we do not have to
12860 worry that a far jump might force the prologue to push the link
12861 register, changing the stack offsets. In this case we can just
12862 return false, since the presence of far jumps in the function will
12863 not affect stack offsets.
12865 If the arg pointer is live (or if it was live, but has now been
12866 eliminated and so set to dead) then we do have to test to see if
12867 the function might contain a far jump. This test can lead to some
12868 false negatives, since before reload is completed, then length of
12869 branch instructions is not known, so gcc defaults to returning their
12870 longest length, which in turn sets the far jump attribute to true.
12872 A false negative will not result in bad code being generated, but it
12873 will result in a needless push and pop of the link register. We
12874 hope that this does not occur too often.
12876 If we need doubleword stack alignment this could affect the other
12877 elimination offsets so we can't risk getting it wrong. */
12878 if (regs_ever_live [ARG_POINTER_REGNUM])
12879 cfun->machine->arg_pointer_live = 1;
12880 else if (!cfun->machine->arg_pointer_live)
12884 /* Check to see if the function contains a branch
12885 insn with the far jump attribute set. */
12886 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12888 if (GET_CODE (insn) == JUMP_INSN
12889 /* Ignore tablejump patterns. */
12890 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12891 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12892 && get_attr_far_jump (insn) == FAR_JUMP_YES
12895 /* Record the fact that we have decided that
12896 the function does use far jumps. */
12897 cfun->machine->far_jump_used = 1;
12905 /* Return nonzero if FUNC must be entered in ARM mode. */
12907 is_called_in_ARM_mode (tree func)
12909 if (TREE_CODE (func) != FUNCTION_DECL)
12912 /* Ignore the problem about functions whoes address is taken. */
12913 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12917 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12923 /* The bits which aren't usefully expanded as rtl. */
12925 thumb_unexpanded_epilogue (void)
12928 int live_regs_mask = 0;
12929 int high_regs_pushed = 0;
12930 int had_to_push_lr;
12931 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12933 if (return_used_this_function)
12936 if (IS_NAKED (arm_current_func_type ()))
12939 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12940 if (THUMB_REG_PUSHED_P (regno))
12941 live_regs_mask |= 1 << regno;
12943 for (regno = 8; regno < 13; regno++)
12944 if (THUMB_REG_PUSHED_P (regno))
12945 high_regs_pushed++;
12947 /* The prolog may have pushed some high registers to use as
12948 work registers. eg the testsuite file:
12949 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12950 compiles to produce:
12951 push {r4, r5, r6, r7, lr}
12955 as part of the prolog. We have to undo that pushing here. */
12957 if (high_regs_pushed)
12959 int mask = live_regs_mask;
12964 /* If we can deduce the registers used from the function's return value.
12965 This is more reliable that examining regs_ever_live[] because that
12966 will be set if the register is ever used in the function, not just if
12967 the register is used to hold a return value. */
12969 if (current_function_return_rtx != 0)
12970 mode = GET_MODE (current_function_return_rtx);
12972 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12974 size = GET_MODE_SIZE (mode);
12976 /* Unless we are returning a type of size > 12 register r3 is
12982 /* Oh dear! We have no low registers into which we can pop
12985 ("no low registers available for popping high registers");
12987 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12988 if (THUMB_REG_PUSHED_P (next_hi_reg))
12991 while (high_regs_pushed)
12993 /* Find lo register(s) into which the high register(s) can
12995 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12997 if (mask & (1 << regno))
12998 high_regs_pushed--;
12999 if (high_regs_pushed == 0)
13003 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13005 /* Pop the values into the low register(s). */
13006 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13008 /* Move the value(s) into the high registers. */
13009 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13011 if (mask & (1 << regno))
13013 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13016 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13017 if (THUMB_REG_PUSHED_P (next_hi_reg))
13024 had_to_push_lr = (live_regs_mask || thumb_force_lr_save ());
13026 if (TARGET_BACKTRACE
13027 && ((live_regs_mask & 0xFF) == 0)
13028 && regs_ever_live [LAST_ARG_REGNUM] != 0)
13030 /* The stack backtrace structure creation code had to
13031 push R7 in order to get a work register, so we pop
13033 live_regs_mask |= (1 << LAST_LO_REGNUM);
13036 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13039 && !is_called_in_ARM_mode (current_function_decl)
13041 live_regs_mask |= 1 << PC_REGNUM;
13043 /* Either no argument registers were pushed or a backtrace
13044 structure was created which includes an adjusted stack
13045 pointer, so just pop everything. */
13046 if (live_regs_mask)
13047 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13051 thumb_exit (asm_out_file, 2, eh_ofs);
13052 /* We have either just popped the return address into the
13053 PC or it is was kept in LR for the entire function or
13054 it is still on the stack because we do not want to
13055 return by doing a pop {pc}. */
13056 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13057 thumb_exit (asm_out_file,
13059 && is_called_in_ARM_mode (current_function_decl)) ?
13060 -1 : LR_REGNUM, NULL_RTX);
13064 /* Pop everything but the return address. */
13065 live_regs_mask &= ~(1 << PC_REGNUM);
13067 if (live_regs_mask)
13068 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13071 if (had_to_push_lr)
13072 /* Get the return address into a temporary register. */
13073 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13074 1 << LAST_ARG_REGNUM);
13076 /* Remove the argument registers that were pushed onto the stack. */
13077 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13078 SP_REGNUM, SP_REGNUM,
13079 current_function_pretend_args_size);
13082 thumb_exit (asm_out_file, 2, eh_ofs);
13084 thumb_exit (asm_out_file,
13085 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13091 /* Functions to save and restore machine-specific function data. */
13092 static struct machine_function *
13093 arm_init_machine_status (void)
13095 struct machine_function *machine;
13096 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13098 #if ARM_FT_UNKNOWN != 0
13099 machine->func_type = ARM_FT_UNKNOWN;
13104 /* Return an RTX indicating where the return address to the
13105 calling function can be found. */
13107 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13112 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13115 /* Do anything needed before RTL is emitted for each function. */
13117 arm_init_expanders (void)
13119 /* Arrange to initialize and mark the machine per-function status. */
13120 init_machine_status = arm_init_machine_status;
13124 /* Like arm_compute_initial_elimination offset. Simpler because
13125 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13128 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13130 arm_stack_offsets *offsets;
13132 offsets = arm_get_frame_offsets ();
13136 case ARG_POINTER_REGNUM:
13139 case STACK_POINTER_REGNUM:
13140 return offsets->outgoing_args - offsets->saved_args;
13142 case FRAME_POINTER_REGNUM:
13143 return offsets->soft_frame - offsets->saved_args;
13145 case THUMB_HARD_FRAME_POINTER_REGNUM:
13146 case ARM_HARD_FRAME_POINTER_REGNUM:
13147 return offsets->saved_regs - offsets->saved_args;
13154 case FRAME_POINTER_REGNUM:
13157 case STACK_POINTER_REGNUM:
13158 return offsets->outgoing_args - offsets->soft_frame;
13160 case THUMB_HARD_FRAME_POINTER_REGNUM:
13161 case ARM_HARD_FRAME_POINTER_REGNUM:
13162 return offsets->saved_regs - offsets->soft_frame;
13175 /* Generate the rest of a function's prologue. */
13177 thumb_expand_prologue (void)
13181 HOST_WIDE_INT amount;
13182 arm_stack_offsets *offsets;
13183 unsigned long func_type;
13186 func_type = arm_current_func_type ();
13188 /* Naked functions don't have prologues. */
13189 if (IS_NAKED (func_type))
13192 if (IS_INTERRUPT (func_type))
13194 error ("interrupt Service Routines cannot be coded in Thumb mode");
13198 offsets = arm_get_frame_offsets ();
13200 if (frame_pointer_needed)
13202 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13203 stack_pointer_rtx));
13204 RTX_FRAME_RELATED_P (insn) = 1;
13207 amount = offsets->outgoing_args - offsets->saved_regs;
13212 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13213 GEN_INT (- amount)));
13214 RTX_FRAME_RELATED_P (insn) = 1;
13220 /* The stack decrement is too big for an immediate value in a single
13221 insn. In theory we could issue multiple subtracts, but after
13222 three of them it becomes more space efficient to place the full
13223 value in the constant pool and load into a register. (Also the
13224 ARM debugger really likes to see only one stack decrement per
13225 function). So instead we look for a scratch register into which
13226 we can load the decrement, and then we subtract this from the
13227 stack pointer. Unfortunately on the thumb the only available
13228 scratch registers are the argument registers, and we cannot use
13229 these as they may hold arguments to the function. Instead we
13230 attempt to locate a call preserved register which is used by this
13231 function. If we can find one, then we know that it will have
13232 been pushed at the start of the prologue and so we can corrupt
13234 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13235 if (THUMB_REG_PUSHED_P (regno)
13236 && !(frame_pointer_needed
13237 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13240 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13242 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13244 /* Choose an arbitrary, non-argument low register. */
13245 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13247 /* Save it by copying it into a high, scratch register. */
13248 emit_insn (gen_movsi (spare, reg));
13249 /* Add a USE to stop propagate_one_insn() from barfing. */
13250 emit_insn (gen_prologue_use (spare));
13252 /* Decrement the stack. */
13253 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13254 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13255 stack_pointer_rtx, reg));
13256 RTX_FRAME_RELATED_P (insn) = 1;
13257 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13258 plus_constant (stack_pointer_rtx,
13259 GEN_INT (- amount)));
13260 RTX_FRAME_RELATED_P (dwarf) = 1;
13262 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13265 /* Restore the low register's original value. */
13266 emit_insn (gen_movsi (reg, spare));
13268 /* Emit a USE of the restored scratch register, so that flow
13269 analysis will not consider the restore redundant. The
13270 register won't be used again in this function and isn't
13271 restored by the epilogue. */
13272 emit_insn (gen_prologue_use (reg));
13276 reg = gen_rtx_REG (SImode, regno);
13278 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13280 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13281 stack_pointer_rtx, reg));
13282 RTX_FRAME_RELATED_P (insn) = 1;
13283 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13284 plus_constant (stack_pointer_rtx,
13285 GEN_INT (- amount)));
13286 RTX_FRAME_RELATED_P (dwarf) = 1;
13288 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13292 /* If the frame pointer is needed, emit a special barrier that
13293 will prevent the scheduler from moving stores to the frame
13294 before the stack adjustment. */
13295 if (frame_pointer_needed)
13296 emit_insn (gen_stack_tie (stack_pointer_rtx,
13297 hard_frame_pointer_rtx));
13300 if (current_function_profile || TARGET_NO_SCHED_PRO)
13301 emit_insn (gen_blockage ());
13303 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13304 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13306 if (THUMB_REG_PUSHED_P (regno))
13308 cfun->machine->lr_save_eliminated = 0;
13313 /* If the link register is being kept alive, with the return address in it,
13314 then make sure that it does not get reused by the ce2 pass. */
13315 if (cfun->machine->lr_save_eliminated)
13316 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13320 thumb_expand_epilogue (void)
13322 HOST_WIDE_INT amount;
13323 arm_stack_offsets *offsets;
13326 /* Naked functions don't have prologues. */
13327 if (IS_NAKED (arm_current_func_type ()))
13330 offsets = arm_get_frame_offsets ();
13331 amount = offsets->outgoing_args - offsets->saved_regs;
13333 if (frame_pointer_needed)
13334 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13338 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13339 GEN_INT (amount)));
13342 /* r3 is always free in the epilogue. */
13343 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13345 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13346 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13350 /* Emit a USE (stack_pointer_rtx), so that
13351 the stack adjustment will not be deleted. */
13352 emit_insn (gen_prologue_use (stack_pointer_rtx));
13354 if (current_function_profile || TARGET_NO_SCHED_PRO)
13355 emit_insn (gen_blockage ());
13357 /* Emit a clobber for each insn that will be restored in the epilogue,
13358 so that flow2 will get register lifetimes correct. */
13359 for (regno = 0; regno < 13; regno++)
13360 if (regs_ever_live[regno] && !call_used_regs[regno])
13361 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13363 if (! regs_ever_live[LR_REGNUM])
13364 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13368 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13370 int live_regs_mask = 0;
13371 int high_regs_pushed = 0;
13372 int cfa_offset = 0;
13375 if (IS_NAKED (arm_current_func_type ()))
13378 if (is_called_in_ARM_mode (current_function_decl))
13382 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13384 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13386 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13388 /* Generate code sequence to switch us into Thumb mode. */
13389 /* The .code 32 directive has already been emitted by
13390 ASM_DECLARE_FUNCTION_NAME. */
13391 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13392 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13394 /* Generate a label, so that the debugger will notice the
13395 change in instruction sets. This label is also used by
13396 the assembler to bypass the ARM code when this function
13397 is called from a Thumb encoded function elsewhere in the
13398 same file. Hence the definition of STUB_NAME here must
13399 agree with the definition in gas/config/tc-arm.c. */
13401 #define STUB_NAME ".real_start_of"
13403 fprintf (f, "\t.code\t16\n");
13405 if (arm_dllexport_name_p (name))
13406 name = arm_strip_name_encoding (name);
13408 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13409 fprintf (f, "\t.thumb_func\n");
13410 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13413 if (current_function_pretend_args_size)
13415 if (cfun->machine->uses_anonymous_args)
13419 fprintf (f, "\tpush\t{");
13421 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13423 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13424 regno <= LAST_ARG_REGNUM;
13426 asm_fprintf (f, "%r%s", regno,
13427 regno == LAST_ARG_REGNUM ? "" : ", ");
13429 fprintf (f, "}\n");
13432 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13433 SP_REGNUM, SP_REGNUM,
13434 current_function_pretend_args_size);
13436 /* We don't need to record the stores for unwinding (would it
13437 help the debugger any if we did?), but record the change in
13438 the stack pointer. */
13439 if (dwarf2out_do_frame ())
13441 char *l = dwarf2out_cfi_label ();
13442 cfa_offset = cfa_offset + current_function_pretend_args_size;
13443 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13447 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13448 if (THUMB_REG_PUSHED_P (regno))
13449 live_regs_mask |= 1 << regno;
13451 if (live_regs_mask || thumb_force_lr_save ())
13452 live_regs_mask |= 1 << LR_REGNUM;
13454 if (TARGET_BACKTRACE)
13457 int work_register = 0;
13460 /* We have been asked to create a stack backtrace structure.
13461 The code looks like this:
13465 0 sub SP, #16 Reserve space for 4 registers.
13466 2 push {R7} Get a work register.
13467 4 add R7, SP, #20 Get the stack pointer before the push.
13468 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13469 8 mov R7, PC Get hold of the start of this code plus 12.
13470 10 str R7, [SP, #16] Store it.
13471 12 mov R7, FP Get hold of the current frame pointer.
13472 14 str R7, [SP, #4] Store it.
13473 16 mov R7, LR Get hold of the current return address.
13474 18 str R7, [SP, #12] Store it.
13475 20 add R7, SP, #16 Point at the start of the backtrace structure.
13476 22 mov FP, R7 Put this value into the frame pointer. */
13478 if ((live_regs_mask & 0xFF) == 0)
13480 /* See if the a4 register is free. */
13482 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13483 work_register = LAST_ARG_REGNUM;
13484 else /* We must push a register of our own. */
13485 live_regs_mask |= (1 << LAST_LO_REGNUM);
13488 if (work_register == 0)
13490 /* Select a register from the list that will be pushed to
13491 use as our work register. */
13492 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13493 if ((1 << work_register) & live_regs_mask)
13498 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13499 SP_REGNUM, SP_REGNUM);
13501 if (dwarf2out_do_frame ())
13503 char *l = dwarf2out_cfi_label ();
13504 cfa_offset = cfa_offset + 16;
13505 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13508 if (live_regs_mask)
13509 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13511 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13512 if (wr & live_regs_mask)
13515 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13516 offset + 16 + current_function_pretend_args_size);
13518 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13521 /* Make sure that the instruction fetching the PC is in the right place
13522 to calculate "start of backtrace creation code + 12". */
13523 if (live_regs_mask)
13525 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13526 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13528 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13529 ARM_HARD_FRAME_POINTER_REGNUM);
13530 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13535 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13536 ARM_HARD_FRAME_POINTER_REGNUM);
13537 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13539 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13540 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13544 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13545 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13547 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13549 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13550 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13552 else if (live_regs_mask)
13553 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13555 for (regno = 8; regno < 13; regno++)
13556 if (THUMB_REG_PUSHED_P (regno))
13557 high_regs_pushed++;
13559 if (high_regs_pushed)
13561 int pushable_regs = 0;
13562 int mask = live_regs_mask & 0xff;
13565 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13566 if (THUMB_REG_PUSHED_P (next_hi_reg))
13569 pushable_regs = mask;
13571 if (pushable_regs == 0)
13573 /* Desperation time -- this probably will never happen. */
13574 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13575 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13576 mask = 1 << LAST_ARG_REGNUM;
13579 while (high_regs_pushed > 0)
13581 int real_regs_mask = 0;
13583 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13585 if (mask & (1 << regno))
13587 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13589 high_regs_pushed--;
13590 real_regs_mask |= (1 << next_hi_reg);
13592 if (high_regs_pushed)
13594 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13596 if (THUMB_REG_PUSHED_P (next_hi_reg))
13601 mask &= ~((1 << regno) - 1);
13607 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13610 if (pushable_regs == 0
13611 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13612 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13616 /* Handle the case of a double word load into a low register from
13617 a computed memory address. The computed address may involve a
13618 register which is overwritten by the load. */
13620 thumb_load_double_from_address (rtx *operands)
13628 if (GET_CODE (operands[0]) != REG)
13631 if (GET_CODE (operands[1]) != MEM)
13634 /* Get the memory address. */
13635 addr = XEXP (operands[1], 0);
13637 /* Work out how the memory address is computed. */
13638 switch (GET_CODE (addr))
13641 operands[2] = gen_rtx_MEM (SImode,
13642 plus_constant (XEXP (operands[1], 0), 4));
13644 if (REGNO (operands[0]) == REGNO (addr))
13646 output_asm_insn ("ldr\t%H0, %2", operands);
13647 output_asm_insn ("ldr\t%0, %1", operands);
13651 output_asm_insn ("ldr\t%0, %1", operands);
13652 output_asm_insn ("ldr\t%H0, %2", operands);
13657 /* Compute <address> + 4 for the high order load. */
13658 operands[2] = gen_rtx_MEM (SImode,
13659 plus_constant (XEXP (operands[1], 0), 4));
13661 output_asm_insn ("ldr\t%0, %1", operands);
13662 output_asm_insn ("ldr\t%H0, %2", operands);
13666 arg1 = XEXP (addr, 0);
13667 arg2 = XEXP (addr, 1);
13669 if (CONSTANT_P (arg1))
13670 base = arg2, offset = arg1;
13672 base = arg1, offset = arg2;
13674 if (GET_CODE (base) != REG)
13677 /* Catch the case of <address> = <reg> + <reg> */
13678 if (GET_CODE (offset) == REG)
13680 int reg_offset = REGNO (offset);
13681 int reg_base = REGNO (base);
13682 int reg_dest = REGNO (operands[0]);
13684 /* Add the base and offset registers together into the
13685 higher destination register. */
13686 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13687 reg_dest + 1, reg_base, reg_offset);
13689 /* Load the lower destination register from the address in
13690 the higher destination register. */
13691 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13692 reg_dest, reg_dest + 1);
13694 /* Load the higher destination register from its own address
13696 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13697 reg_dest + 1, reg_dest + 1);
13701 /* Compute <address> + 4 for the high order load. */
13702 operands[2] = gen_rtx_MEM (SImode,
13703 plus_constant (XEXP (operands[1], 0), 4));
13705 /* If the computed address is held in the low order register
13706 then load the high order register first, otherwise always
13707 load the low order register first. */
13708 if (REGNO (operands[0]) == REGNO (base))
13710 output_asm_insn ("ldr\t%H0, %2", operands);
13711 output_asm_insn ("ldr\t%0, %1", operands);
13715 output_asm_insn ("ldr\t%0, %1", operands);
13716 output_asm_insn ("ldr\t%H0, %2", operands);
13722 /* With no registers to worry about we can just load the value
13724 operands[2] = gen_rtx_MEM (SImode,
13725 plus_constant (XEXP (operands[1], 0), 4));
13727 output_asm_insn ("ldr\t%H0, %2", operands);
13728 output_asm_insn ("ldr\t%0, %1", operands);
13740 thumb_output_move_mem_multiple (int n, rtx *operands)
13747 if (REGNO (operands[4]) > REGNO (operands[5]))
13750 operands[4] = operands[5];
13753 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13754 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13758 if (REGNO (operands[4]) > REGNO (operands[5]))
13761 operands[4] = operands[5];
13764 if (REGNO (operands[5]) > REGNO (operands[6]))
13767 operands[5] = operands[6];
13770 if (REGNO (operands[4]) > REGNO (operands[5]))
13773 operands[4] = operands[5];
13777 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13778 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13788 /* Routines for generating rtl. */
13790 thumb_expand_movstrqi (rtx *operands)
13792 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13793 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13794 HOST_WIDE_INT len = INTVAL (operands[2]);
13795 HOST_WIDE_INT offset = 0;
13799 emit_insn (gen_movmem12b (out, in, out, in));
13805 emit_insn (gen_movmem8b (out, in, out, in));
13811 rtx reg = gen_reg_rtx (SImode);
13812 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13813 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13820 rtx reg = gen_reg_rtx (HImode);
13821 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13822 plus_constant (in, offset))));
13823 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13831 rtx reg = gen_reg_rtx (QImode);
13832 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13833 plus_constant (in, offset))));
13834 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13840 thumb_cmp_operand (rtx op, enum machine_mode mode)
13842 return ((GET_CODE (op) == CONST_INT
13843 && INTVAL (op) < 256
13844 && INTVAL (op) >= 0)
13845 || s_register_operand (op, mode));
13849 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13851 return (GET_CODE (op) == CONST_INT
13853 && INTVAL (op) > -256);
13856 /* Return TRUE if a result can be stored in OP without clobbering the
13857 condition code register. Prior to reload we only accept a
13858 register. After reload we have to be able to handle memory as
13859 well, since a pseudo may not get a hard reg and reload cannot
13860 handle output-reloads on jump insns.
13862 We could possibly handle mem before reload as well, but that might
13863 complicate things with the need to handle increment
13867 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13869 return (s_register_operand (op, mode)
13870 || ((reload_in_progress || reload_completed)
13871 && memory_operand (op, mode)));
13874 /* Handle storing a half-word to memory during reload. */
13876 thumb_reload_out_hi (rtx *operands)
13878 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13881 /* Handle reading a half-word from memory during reload. */
13883 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13888 /* Return the length of a function name prefix
13889 that starts with the character 'c'. */
13891 arm_get_strip_length (int c)
13895 ARM_NAME_ENCODING_LENGTHS
13900 /* Return a pointer to a function's name with any
13901 and all prefix encodings stripped from it. */
13903 arm_strip_name_encoding (const char *name)
13907 while ((skip = arm_get_strip_length (* name)))
13913 /* If there is a '*' anywhere in the name's prefix, then
13914 emit the stripped name verbatim, otherwise prepend an
13915 underscore if leading underscores are being used. */
13917 arm_asm_output_labelref (FILE *stream, const char *name)
13922 while ((skip = arm_get_strip_length (* name)))
13924 verbatim |= (*name == '*');
13929 fputs (name, stream);
13931 asm_fprintf (stream, "%U%s", name);
13936 #ifdef AOF_ASSEMBLER
13937 /* Special functions only needed when producing AOF syntax assembler. */
13941 struct pic_chain * next;
13942 const char * symname;
13945 static struct pic_chain * aof_pic_chain = NULL;
13948 aof_pic_entry (rtx x)
13950 struct pic_chain ** chainp;
13953 if (aof_pic_label == NULL_RTX)
13955 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13958 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13959 offset += 4, chainp = &(*chainp)->next)
13960 if ((*chainp)->symname == XSTR (x, 0))
13961 return plus_constant (aof_pic_label, offset);
13963 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13964 (*chainp)->next = NULL;
13965 (*chainp)->symname = XSTR (x, 0);
13966 return plus_constant (aof_pic_label, offset);
13970 aof_dump_pic_table (FILE *f)
13972 struct pic_chain * chain;
13974 if (aof_pic_chain == NULL)
13977 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13978 PIC_OFFSET_TABLE_REGNUM,
13979 PIC_OFFSET_TABLE_REGNUM);
13980 fputs ("|x$adcons|\n", f);
13982 for (chain = aof_pic_chain; chain; chain = chain->next)
13984 fputs ("\tDCD\t", f);
13985 assemble_name (f, chain->symname);
13990 int arm_text_section_count = 1;
13993 aof_text_section (void )
13995 static char buf[100];
13996 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13997 arm_text_section_count++);
13999 strcat (buf, ", PIC, REENTRANT");
14003 static int arm_data_section_count = 1;
14006 aof_data_section (void)
14008 static char buf[100];
14009 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14013 /* The AOF assembler is religiously strict about declarations of
14014 imported and exported symbols, so that it is impossible to declare
14015 a function as imported near the beginning of the file, and then to
14016 export it later on. It is, however, possible to delay the decision
14017 until all the functions in the file have been compiled. To get
14018 around this, we maintain a list of the imports and exports, and
14019 delete from it any that are subsequently defined. At the end of
14020 compilation we spit the remainder of the list out before the END
14025 struct import * next;
14029 static struct import * imports_list = NULL;
14032 aof_add_import (const char *name)
14034 struct import * new;
14036 for (new = imports_list; new; new = new->next)
14037 if (new->name == name)
14040 new = (struct import *) xmalloc (sizeof (struct import));
14041 new->next = imports_list;
14042 imports_list = new;
14047 aof_delete_import (const char *name)
14049 struct import ** old;
14051 for (old = &imports_list; *old; old = & (*old)->next)
14053 if ((*old)->name == name)
14055 *old = (*old)->next;
14061 int arm_main_function = 0;
14064 aof_dump_imports (FILE *f)
14066 /* The AOF assembler needs this to cause the startup code to be extracted
14067 from the library. Brining in __main causes the whole thing to work
14069 if (arm_main_function)
14072 fputs ("\tIMPORT __main\n", f);
14073 fputs ("\tDCD __main\n", f);
14076 /* Now dump the remaining imports. */
14077 while (imports_list)
14079 fprintf (f, "\tIMPORT\t");
14080 assemble_name (f, imports_list->name);
14082 imports_list = imports_list->next;
14087 aof_globalize_label (FILE *stream, const char *name)
14089 default_globalize_label (stream, name);
14090 if (! strcmp (name, "main"))
14091 arm_main_function = 1;
14095 aof_file_start (void)
14097 fputs ("__r0\tRN\t0\n", asm_out_file);
14098 fputs ("__a1\tRN\t0\n", asm_out_file);
14099 fputs ("__a2\tRN\t1\n", asm_out_file);
14100 fputs ("__a3\tRN\t2\n", asm_out_file);
14101 fputs ("__a4\tRN\t3\n", asm_out_file);
14102 fputs ("__v1\tRN\t4\n", asm_out_file);
14103 fputs ("__v2\tRN\t5\n", asm_out_file);
14104 fputs ("__v3\tRN\t6\n", asm_out_file);
14105 fputs ("__v4\tRN\t7\n", asm_out_file);
14106 fputs ("__v5\tRN\t8\n", asm_out_file);
14107 fputs ("__v6\tRN\t9\n", asm_out_file);
14108 fputs ("__sl\tRN\t10\n", asm_out_file);
14109 fputs ("__fp\tRN\t11\n", asm_out_file);
14110 fputs ("__ip\tRN\t12\n", asm_out_file);
14111 fputs ("__sp\tRN\t13\n", asm_out_file);
14112 fputs ("__lr\tRN\t14\n", asm_out_file);
14113 fputs ("__pc\tRN\t15\n", asm_out_file);
14114 fputs ("__f0\tFN\t0\n", asm_out_file);
14115 fputs ("__f1\tFN\t1\n", asm_out_file);
14116 fputs ("__f2\tFN\t2\n", asm_out_file);
14117 fputs ("__f3\tFN\t3\n", asm_out_file);
14118 fputs ("__f4\tFN\t4\n", asm_out_file);
14119 fputs ("__f5\tFN\t5\n", asm_out_file);
14120 fputs ("__f6\tFN\t6\n", asm_out_file);
14121 fputs ("__f7\tFN\t7\n", asm_out_file);
14126 aof_file_end (void)
14129 aof_dump_pic_table (asm_out_file);
14130 aof_dump_imports (asm_out_file);
14131 fputs ("\tEND\n", asm_out_file);
14133 #endif /* AOF_ASSEMBLER */
14135 #ifdef OBJECT_FORMAT_ELF
14136 /* Switch to an arbitrary section NAME with attributes as specified
14137 by FLAGS. ALIGN specifies any known alignment requirements for
14138 the section; 0 if the default should be used.
14140 Differs from the default elf version only in the prefix character
14141 used before the section type. */
14144 arm_elf_asm_named_section (const char *name, unsigned int flags)
14146 char flagchars[10], *f = flagchars;
14148 if (! named_section_first_declaration (name))
14150 fprintf (asm_out_file, "\t.section\t%s\n", name);
14154 if (!(flags & SECTION_DEBUG))
14156 if (flags & SECTION_WRITE)
14158 if (flags & SECTION_CODE)
14160 if (flags & SECTION_SMALL)
14162 if (flags & SECTION_MERGE)
14164 if (flags & SECTION_STRINGS)
14166 if (flags & SECTION_TLS)
14170 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14172 if (!(flags & SECTION_NOTYPE))
14176 if (flags & SECTION_BSS)
14181 fprintf (asm_out_file, ",%%%s", type);
14183 if (flags & SECTION_ENTSIZE)
14184 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14187 putc ('\n', asm_out_file);
14192 /* Symbols in the text segment can be accessed without indirecting via the
14193 constant pool; it may take an extra binary operation, but this is still
14194 faster than indirecting via memory. Don't do this when not optimizing,
14195 since we won't be calculating al of the offsets necessary to do this
14199 arm_encode_section_info (tree decl, rtx rtl, int first)
14201 /* This doesn't work with AOF syntax, since the string table may be in
14202 a different AREA. */
14203 #ifndef AOF_ASSEMBLER
14204 if (optimize > 0 && TREE_CONSTANT (decl))
14205 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14208 /* If we are referencing a function that is weak then encode a long call
14209 flag in the function name, otherwise if the function is static or
14210 or known to be defined in this file then encode a short call flag. */
14211 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14213 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14214 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14215 else if (! TREE_PUBLIC (decl))
14216 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14219 #endif /* !ARM_PE */
14222 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14224 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14225 && !strcmp (prefix, "L"))
14227 arm_ccfsm_state = 0;
14228 arm_target_insn = NULL;
14230 default_internal_label (stream, prefix, labelno);
14233 /* Output code to add DELTA to the first argument, and then jump
14234 to FUNCTION. Used for C++ multiple inheritance. */
14236 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14237 HOST_WIDE_INT delta,
14238 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14241 static int thunk_label = 0;
14243 int mi_delta = delta;
14244 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14246 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14249 mi_delta = - mi_delta;
14252 int labelno = thunk_label++;
14253 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14254 fputs ("\tldr\tr12, ", file);
14255 assemble_name (file, label);
14256 fputc ('\n', file);
14258 while (mi_delta != 0)
14260 if ((mi_delta & (3 << shift)) == 0)
14264 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14265 mi_op, this_regno, this_regno,
14266 mi_delta & (0xff << shift));
14267 mi_delta &= ~(0xff << shift);
14273 fprintf (file, "\tbx\tr12\n");
14274 ASM_OUTPUT_ALIGN (file, 2);
14275 assemble_name (file, label);
14276 fputs (":\n", file);
14277 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14281 fputs ("\tb\t", file);
14282 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14283 if (NEED_PLT_RELOC)
14284 fputs ("(PLT)", file);
14285 fputc ('\n', file);
14290 arm_emit_vector_const (FILE *file, rtx x)
14293 const char * pattern;
14295 if (GET_CODE (x) != CONST_VECTOR)
14298 switch (GET_MODE (x))
14300 case V2SImode: pattern = "%08x"; break;
14301 case V4HImode: pattern = "%04x"; break;
14302 case V8QImode: pattern = "%02x"; break;
14306 fprintf (file, "0x");
14307 for (i = CONST_VECTOR_NUNITS (x); i--;)
14311 element = CONST_VECTOR_ELT (x, i);
14312 fprintf (file, pattern, INTVAL (element));
14319 arm_output_load_gr (rtx *operands)
14326 if (GET_CODE (operands [1]) != MEM
14327 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14328 || GET_CODE (reg = XEXP (sum, 0)) != REG
14329 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14330 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14331 return "wldrw%?\t%0, %1";
14333 /* Fix up an out-of-range load of a GR register. */
14334 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14335 wcgr = operands[0];
14337 output_asm_insn ("ldr%?\t%0, %1", operands);
14339 operands[0] = wcgr;
14341 output_asm_insn ("tmcr%?\t%0, %1", operands);
14342 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14348 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14349 int incoming ATTRIBUTE_UNUSED)
14352 /* FIXME: The ARM backend has special code to handle structure
14353 returns, and will reserve its own hidden first argument. So
14354 if this macro is enabled a *second* hidden argument will be
14355 reserved, which will break binary compatibility with old
14356 toolchains and also thunk handling. One day this should be
14360 /* Register in which address to store a structure value
14361 is passed to a function. */
14362 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14366 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14368 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14369 named arg and all anonymous args onto the stack.
14370 XXX I know the prologue shouldn't be pushing registers, but it is faster
14374 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14375 enum machine_mode mode ATTRIBUTE_UNUSED,
14376 tree type ATTRIBUTE_UNUSED,
14378 int second_time ATTRIBUTE_UNUSED)
14380 cfun->machine->uses_anonymous_args = 1;
14381 if (cum->nregs < NUM_ARG_REGS)
14382 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14385 /* Return nonzero if the CONSUMER instruction (a store) does not need
14386 PRODUCER's value to calculate the address. */
14389 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14391 rtx value = PATTERN (producer);
14392 rtx addr = PATTERN (consumer);
14394 if (GET_CODE (value) == COND_EXEC)
14395 value = COND_EXEC_CODE (value);
14396 if (GET_CODE (value) == PARALLEL)
14397 value = XVECEXP (value, 0, 0);
14398 value = XEXP (value, 0);
14399 if (GET_CODE (addr) == COND_EXEC)
14400 addr = COND_EXEC_CODE (addr);
14401 if (GET_CODE (addr) == PARALLEL)
14402 addr = XVECEXP (addr, 0, 0);
14403 addr = XEXP (addr, 0);
14405 return !reg_overlap_mentioned_p (value, addr);
14408 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14409 have an early register shift value or amount dependency on the
14410 result of PRODUCER. */
14413 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14415 rtx value = PATTERN (producer);
14416 rtx op = PATTERN (consumer);
14419 if (GET_CODE (value) == COND_EXEC)
14420 value = COND_EXEC_CODE (value);
14421 if (GET_CODE (value) == PARALLEL)
14422 value = XVECEXP (value, 0, 0);
14423 value = XEXP (value, 0);
14424 if (GET_CODE (op) == COND_EXEC)
14425 op = COND_EXEC_CODE (op);
14426 if (GET_CODE (op) == PARALLEL)
14427 op = XVECEXP (op, 0, 0);
14430 early_op = XEXP (op, 0);
14431 /* This is either an actual independent shift, or a shift applied to
14432 the first operand of another operation. We want the whole shift
14434 if (GET_CODE (early_op) == REG)
14437 return !reg_overlap_mentioned_p (value, early_op);
14440 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14441 have an early register shift value dependency on the result of
14445 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14447 rtx value = PATTERN (producer);
14448 rtx op = PATTERN (consumer);
14451 if (GET_CODE (value) == COND_EXEC)
14452 value = COND_EXEC_CODE (value);
14453 if (GET_CODE (value) == PARALLEL)
14454 value = XVECEXP (value, 0, 0);
14455 value = XEXP (value, 0);
14456 if (GET_CODE (op) == COND_EXEC)
14457 op = COND_EXEC_CODE (op);
14458 if (GET_CODE (op) == PARALLEL)
14459 op = XVECEXP (op, 0, 0);
14462 early_op = XEXP (op, 0);
14464 /* This is either an actual independent shift, or a shift applied to
14465 the first operand of another operation. We want the value being
14466 shifted, in either case. */
14467 if (GET_CODE (early_op) != REG)
14468 early_op = XEXP (early_op, 0);
14470 return !reg_overlap_mentioned_p (value, early_op);
14473 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14474 have an early register mult dependency on the result of
14478 arm_no_early_mul_dep (rtx producer, rtx consumer)
14480 rtx value = PATTERN (producer);
14481 rtx op = PATTERN (consumer);
14483 if (GET_CODE (value) == COND_EXEC)
14484 value = COND_EXEC_CODE (value);
14485 if (GET_CODE (value) == PARALLEL)
14486 value = XVECEXP (value, 0, 0);
14487 value = XEXP (value, 0);
14488 if (GET_CODE (op) == COND_EXEC)
14489 op = COND_EXEC_CODE (op);
14490 if (GET_CODE (op) == PARALLEL)
14491 op = XVECEXP (op, 0, 0);
14494 return (GET_CODE (op) == PLUS
14495 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14499 /* We can't rely on the caller doing the proper promotion when
14500 using APCS or ATPCS. */
14503 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14505 return !TARGET_AAPCS_BASED;
14509 /* AAPCS based ABIs use short enums by default. */
14512 arm_default_short_enums (void)
14514 return TARGET_AAPCS_BASED;
14518 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14521 arm_align_anon_bitfield (void)
14523 return TARGET_AAPCS_BASED;