1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
75 static rtx emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
81 static arm_cc get_arm_condition_code (rtx);
82 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
83 static rtx is_jump_table (rtx);
84 static const char *output_multi_immediate (rtx *, const char *, const char *,
86 static const char *shift_op (rtx, HOST_WIDE_INT *);
87 static struct machine_function *arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static int arm_comp_type_attributes (tree, tree);
119 static void arm_set_default_type_attributes (tree);
120 static int arm_adjust_cost (rtx, rtx, rtx, int);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_size_rtx_costs (rtx, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx, int, int, int *);
133 static int arm_address_cost (rtx);
134 static bool arm_memory_load_p (rtx);
135 static bool arm_cirrus_insn_p (rtx);
136 static void cirrus_reorg (rtx);
137 static void arm_init_builtins (void);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx safe_vector_operand (rtx, enum machine_mode);
141 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
142 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void emit_constant_insn (rtx cond, rtx pattern);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx, int);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx arm_struct_value_rtx (tree, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
168 enum machine_mode, tree, bool);
169 static bool arm_promote_prototypes (tree);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree);
173 static bool arm_must_pass_in_stack (enum machine_mode, tree);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx);
176 static bool arm_output_ttype (rtx);
179 static tree arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree arm_get_cookie_size (tree);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
192 /* Initialize the GCC target structure. */
193 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
194 #undef TARGET_MERGE_DECL_ATTRIBUTES
195 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
198 #undef TARGET_ATTRIBUTE_TABLE
199 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
201 #undef TARGET_ASM_FILE_END
202 #define TARGET_ASM_FILE_END arm_file_end
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\tDCB\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
211 #undef TARGET_ASM_GLOBALIZE_LABEL
212 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START aof_file_start
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END aof_file_end
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP NULL
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER arm_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
230 #undef TARGET_DEFAULT_TARGET_FLAGS
231 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
232 #undef TARGET_HANDLE_OPTION
233 #define TARGET_HANDLE_OPTION arm_handle_option
235 #undef TARGET_COMP_TYPE_ATTRIBUTES
236 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
238 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
239 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
244 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
248 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
251 #undef TARGET_STRIP_NAME_ENCODING
252 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
254 #undef TARGET_ASM_INTERNAL_LABEL
255 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
260 #undef TARGET_ASM_OUTPUT_MI_THUNK
261 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
265 /* This will be overridden in arm_override_options. */
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST arm_address_cost
271 #undef TARGET_SHIFT_TRUNCATION_MASK
272 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
273 #undef TARGET_VECTOR_MODE_SUPPORTED_P
274 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
276 #undef TARGET_MACHINE_DEPENDENT_REORG
277 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS arm_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
287 #undef TARGET_PROMOTE_FUNCTION_ARGS
288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
289 #undef TARGET_PROMOTE_FUNCTION_RETURN
290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
295 #undef TARGET_ARG_PARTIAL_BYTES
296 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
298 #undef TARGET_STRUCT_VALUE_RTX
299 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
301 #undef TARGET_SETUP_INCOMING_VARARGS
302 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
304 #undef TARGET_DEFAULT_SHORT_ENUMS
305 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
307 #undef TARGET_ALIGN_ANON_BITFIELD
308 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
310 #undef TARGET_CXX_GUARD_TYPE
311 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
313 #undef TARGET_CXX_GUARD_MASK_BIT
314 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
316 #undef TARGET_CXX_GET_COOKIE_SIZE
317 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
319 #undef TARGET_CXX_COOKIE_HAS_SIZE
320 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
322 #undef TARGET_CXX_CDTOR_RETURNS_THIS
323 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
325 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
326 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
328 #undef TARGET_CXX_USE_AEABI_ATEXIT
329 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
331 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
332 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
333 arm_cxx_determine_class_data_visibility
335 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
336 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
338 #undef TARGET_RETURN_IN_MSB
339 #define TARGET_RETURN_IN_MSB arm_return_in_msb
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
344 #ifdef TARGET_UNWIND_INFO
345 #undef TARGET_UNWIND_EMIT
346 #define TARGET_UNWIND_EMIT arm_unwind_emit
348 /* EABI unwinding tables use a different format for the typeinfo tables. */
349 #undef TARGET_ASM_TTYPE
350 #define TARGET_ASM_TTYPE arm_output_ttype
352 #undef TARGET_ARM_EABI_UNWINDER
353 #define TARGET_ARM_EABI_UNWINDER true
354 #endif /* TARGET_UNWIND_INFO */
356 struct gcc_target targetm = TARGET_INITIALIZER;
358 /* Obstack for minipool constant handling. */
359 static struct obstack minipool_obstack;
360 static char * minipool_startobj;
362 /* The maximum number of insns skipped which
363 will be conditionalised if possible. */
364 static int max_insns_skipped = 5;
366 extern FILE * asm_out_file;
368 /* True if we are currently building a constant table. */
369 int making_const_table;
371 /* Define the information needed to generate branch insns. This is
372 stored from the compare operation. */
373 rtx arm_compare_op0, arm_compare_op1;
375 /* The processor for which instructions should be scheduled. */
376 enum processor_type arm_tune = arm_none;
378 /* Which floating point model to use. */
379 enum arm_fp_model arm_fp_model;
381 /* Which floating point hardware is available. */
382 enum fputype arm_fpu_arch;
384 /* Which floating point hardware to schedule for. */
385 enum fputype arm_fpu_tune;
387 /* Whether to use floating point hardware. */
388 enum float_abi_type arm_float_abi;
390 /* Which ABI to use. */
391 enum arm_abi_type arm_abi;
393 /* Used to parse -mstructure_size_boundary command line option. */
394 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
396 /* Used for Thumb call_via trampolines. */
397 rtx thumb_call_via_label[14];
398 static int thumb_call_reg_needed;
400 /* Bit values used to identify processor capabilities. */
401 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
402 #define FL_ARCH3M (1 << 1) /* Extended multiply */
403 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
404 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
405 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
406 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
407 #define FL_THUMB (1 << 6) /* Thumb aware */
408 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
409 #define FL_STRONG (1 << 8) /* StrongARM */
410 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
411 #define FL_XSCALE (1 << 10) /* XScale */
412 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
413 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
414 media instructions. */
415 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
416 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
417 Note: ARM6 & 7 derivatives only. */
419 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
421 #define FL_FOR_ARCH2 0
422 #define FL_FOR_ARCH3 FL_MODE32
423 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
424 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
425 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
426 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
427 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
428 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
429 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
430 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
431 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
432 #define FL_FOR_ARCH6J FL_FOR_ARCH6
433 #define FL_FOR_ARCH6K FL_FOR_ARCH6
434 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
435 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
437 /* The bits in this mask specify which
438 instructions we are allowed to generate. */
439 static unsigned long insn_flags = 0;
441 /* The bits in this mask specify which instruction scheduling options should
443 static unsigned long tune_flags = 0;
445 /* The following are used in the arm.md file as equivalents to bits
446 in the above two flag variables. */
448 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
451 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
454 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
457 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
460 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
463 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
466 /* Nonzero if this chip can benefit from load scheduling. */
467 int arm_ld_sched = 0;
469 /* Nonzero if this chip is a StrongARM. */
470 int arm_tune_strongarm = 0;
472 /* Nonzero if this chip is a Cirrus variant. */
473 int arm_arch_cirrus = 0;
475 /* Nonzero if this chip supports Intel Wireless MMX technology. */
476 int arm_arch_iwmmxt = 0;
478 /* Nonzero if this chip is an XScale. */
479 int arm_arch_xscale = 0;
481 /* Nonzero if tuning for XScale */
482 int arm_tune_xscale = 0;
484 /* Nonzero if we want to tune for stores that access the write-buffer.
485 This typically means an ARM6 or ARM7 with MMU or MPU. */
486 int arm_tune_wbuf = 0;
488 /* Nonzero if generating Thumb instructions. */
491 /* Nonzero if we should define __THUMB_INTERWORK__ in the
493 XXX This is a bit of a hack, it's intended to help work around
494 problems in GLD which doesn't understand that armv5t code is
495 interworking clean. */
496 int arm_cpp_interwork = 0;
498 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
499 must report the mode of the memory reference from PRINT_OPERAND to
500 PRINT_OPERAND_ADDRESS. */
501 enum machine_mode output_memory_reference_mode;
503 /* The register number to be used for the PIC offset register. */
504 int arm_pic_register = INVALID_REGNUM;
506 /* Set to 1 when a return insn is output, this means that the epilogue
508 int return_used_this_function;
510 /* Set to 1 after arm_reorg has started. Reset to start at the start of
511 the next function. */
512 static int after_arm_reorg = 0;
514 /* The maximum number of insns to be used when loading a constant. */
515 static int arm_constant_limit = 3;
517 /* For an explanation of these variables, see final_prescan_insn below. */
519 enum arm_cond_code arm_current_cc;
521 int arm_target_label;
523 /* The condition codes of the ARM, and the inverse function. */
524 static const char * const arm_condition_codes[] =
526 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
527 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
530 #define streq(string1, string2) (strcmp (string1, string2) == 0)
532 /* Initialization code. */
536 const char *const name;
537 enum processor_type core;
539 const unsigned long flags;
540 bool (* rtx_costs) (rtx, int, int, int *);
543 /* Not all of these give usefully different compilation alternatives,
544 but there is no simple way of generalizing them. */
545 static const struct processors all_cores[] =
548 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
549 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
550 #include "arm-cores.def"
552 {NULL, arm_none, NULL, 0, NULL}
555 static const struct processors all_architectures[] =
557 /* ARM Architectures */
558 /* We don't specify rtx_costs here as it will be figured out
561 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
562 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
563 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
564 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
565 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
566 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
567 implementations that support it, so we will leave it out for now. */
568 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
569 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
570 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
571 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
572 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
573 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
574 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
575 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
576 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
577 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
578 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
579 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
580 {NULL, arm_none, NULL, 0 , NULL}
583 struct arm_cpu_select
587 const struct processors * processors;
590 /* This is a magic structure. The 'string' field is magically filled in
591 with a pointer to the value specified by the user on the command line
592 assuming that the user has specified such a value. */
594 static struct arm_cpu_select arm_select[] =
596 /* string name processors */
597 { NULL, "-mcpu=", all_cores },
598 { NULL, "-march=", all_architectures },
599 { NULL, "-mtune=", all_cores }
602 /* Defines representing the indexes into the above table. */
603 #define ARM_OPT_SET_CPU 0
604 #define ARM_OPT_SET_ARCH 1
605 #define ARM_OPT_SET_TUNE 2
607 /* The name of the proprocessor macro to define for this architecture. */
609 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
618 /* Available values for for -mfpu=. */
620 static const struct fpu_desc all_fpus[] =
622 {"fpa", FPUTYPE_FPA},
623 {"fpe2", FPUTYPE_FPA_EMU2},
624 {"fpe3", FPUTYPE_FPA_EMU2},
625 {"maverick", FPUTYPE_MAVERICK},
630 /* Floating point models used by the different hardware.
631 See fputype in arm.h. */
633 static const enum fputype fp_model_for_fpu[] =
635 /* No FP hardware. */
636 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
637 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
638 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
639 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
640 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
641 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
648 enum float_abi_type abi_type;
652 /* Available values for -mfloat-abi=. */
654 static const struct float_abi all_float_abis[] =
656 {"soft", ARM_FLOAT_ABI_SOFT},
657 {"softfp", ARM_FLOAT_ABI_SOFTFP},
658 {"hard", ARM_FLOAT_ABI_HARD}
665 enum arm_abi_type abi_type;
669 /* Available values for -mabi=. */
671 static const struct abi_name arm_all_abis[] =
673 {"apcs-gnu", ARM_ABI_APCS},
674 {"atpcs", ARM_ABI_ATPCS},
675 {"aapcs", ARM_ABI_AAPCS},
676 {"iwmmxt", ARM_ABI_IWMMXT},
677 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
680 /* Return the number of bits set in VALUE. */
682 bit_count (unsigned long value)
684 unsigned long count = 0;
689 value &= value - 1; /* Clear the least-significant set bit. */
695 /* Set up library functions unique to ARM. */
698 arm_init_libfuncs (void)
700 /* There are no special library functions unless we are using the
705 /* The functions below are described in Section 4 of the "Run-Time
706 ABI for the ARM architecture", Version 1.0. */
708 /* Double-precision floating-point arithmetic. Table 2. */
709 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
710 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
711 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
712 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
713 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
715 /* Double-precision comparisons. Table 3. */
716 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
717 set_optab_libfunc (ne_optab, DFmode, NULL);
718 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
719 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
720 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
721 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
722 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
724 /* Single-precision floating-point arithmetic. Table 4. */
725 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
726 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
727 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
728 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
729 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
731 /* Single-precision comparisons. Table 5. */
732 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
733 set_optab_libfunc (ne_optab, SFmode, NULL);
734 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
735 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
736 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
737 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
738 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
740 /* Floating-point to integer conversions. Table 6. */
741 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
742 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
743 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
744 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
745 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
746 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
747 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
748 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
750 /* Conversions between floating types. Table 7. */
751 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
752 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
754 /* Integer to floating-point conversions. Table 8. */
755 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
756 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
757 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
758 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
759 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
760 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
761 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
762 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
764 /* Long long. Table 9. */
765 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
766 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
767 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
768 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
769 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
770 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
771 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
772 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
774 /* Integer (32/32->32) division. \S 4.3.1. */
775 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
776 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
778 /* The divmod functions are designed so that they can be used for
779 plain division, even though they return both the quotient and the
780 remainder. The quotient is returned in the usual location (i.e.,
781 r0 for SImode, {r0, r1} for DImode), just as would be expected
782 for an ordinary division routine. Because the AAPCS calling
783 conventions specify that all of { r0, r1, r2, r3 } are
784 callee-saved registers, there is no need to tell the compiler
785 explicitly that those registers are clobbered by these
787 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
788 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
789 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
790 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
792 /* We don't have mod libcalls. Fortunately gcc knows how to use the
793 divmod libcalls instead. */
794 set_optab_libfunc (smod_optab, DImode, NULL);
795 set_optab_libfunc (umod_optab, DImode, NULL);
796 set_optab_libfunc (smod_optab, SImode, NULL);
797 set_optab_libfunc (umod_optab, SImode, NULL);
800 /* Implement TARGET_HANDLE_OPTION. */
803 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
808 arm_select[1].string = arg;
812 arm_select[0].string = arg;
815 case OPT_mhard_float:
816 target_float_abi_name = "hard";
819 case OPT_msoft_float:
820 target_float_abi_name = "soft";
824 arm_select[2].string = arg;
832 /* Fix up any incompatible options that the user has specified.
833 This has now turned into a maze. */
835 arm_override_options (void)
838 enum processor_type target_arch_cpu = arm_none;
840 /* Set up the flags based on the cpu/architecture selected by the user. */
841 for (i = ARRAY_SIZE (arm_select); i--;)
843 struct arm_cpu_select * ptr = arm_select + i;
845 if (ptr->string != NULL && ptr->string[0] != '\0')
847 const struct processors * sel;
849 for (sel = ptr->processors; sel->name != NULL; sel++)
850 if (streq (ptr->string, sel->name))
852 /* Set the architecture define. */
853 if (i != ARM_OPT_SET_TUNE)
854 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
856 /* Determine the processor core for which we should
857 tune code-generation. */
858 if (/* -mcpu= is a sensible default. */
860 /* -mtune= overrides -mcpu= and -march=. */
861 || i == ARM_OPT_SET_TUNE)
862 arm_tune = (enum processor_type) (sel - ptr->processors);
864 /* Remember the CPU associated with this architecture.
865 If no other option is used to set the CPU type,
866 we'll use this to guess the most suitable tuning
868 if (i == ARM_OPT_SET_ARCH)
869 target_arch_cpu = sel->core;
871 if (i != ARM_OPT_SET_TUNE)
873 /* If we have been given an architecture and a processor
874 make sure that they are compatible. We only generate
875 a warning though, and we prefer the CPU over the
877 if (insn_flags != 0 && (insn_flags ^ sel->flags))
878 warning (0, "switch -mcpu=%s conflicts with -march= switch",
881 insn_flags = sel->flags;
887 if (sel->name == NULL)
888 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
892 /* Guess the tuning options from the architecture if necessary. */
893 if (arm_tune == arm_none)
894 arm_tune = target_arch_cpu;
896 /* If the user did not specify a processor, choose one for them. */
899 const struct processors * sel;
901 enum processor_type cpu;
903 cpu = TARGET_CPU_DEFAULT;
906 #ifdef SUBTARGET_CPU_DEFAULT
907 /* Use the subtarget default CPU if none was specified by
909 cpu = SUBTARGET_CPU_DEFAULT;
911 /* Default to ARM6. */
915 sel = &all_cores[cpu];
917 insn_flags = sel->flags;
919 /* Now check to see if the user has specified some command line
920 switch that require certain abilities from the cpu. */
923 if (TARGET_INTERWORK || TARGET_THUMB)
925 sought |= (FL_THUMB | FL_MODE32);
927 /* There are no ARM processors that support both APCS-26 and
928 interworking. Therefore we force FL_MODE26 to be removed
929 from insn_flags here (if it was set), so that the search
930 below will always be able to find a compatible processor. */
931 insn_flags &= ~FL_MODE26;
934 if (sought != 0 && ((sought & insn_flags) != sought))
936 /* Try to locate a CPU type that supports all of the abilities
937 of the default CPU, plus the extra abilities requested by
939 for (sel = all_cores; sel->name != NULL; sel++)
940 if ((sel->flags & sought) == (sought | insn_flags))
943 if (sel->name == NULL)
945 unsigned current_bit_count = 0;
946 const struct processors * best_fit = NULL;
948 /* Ideally we would like to issue an error message here
949 saying that it was not possible to find a CPU compatible
950 with the default CPU, but which also supports the command
951 line options specified by the programmer, and so they
952 ought to use the -mcpu=<name> command line option to
953 override the default CPU type.
955 If we cannot find a cpu that has both the
956 characteristics of the default cpu and the given
957 command line options we scan the array again looking
959 for (sel = all_cores; sel->name != NULL; sel++)
960 if ((sel->flags & sought) == sought)
964 count = bit_count (sel->flags & insn_flags);
966 if (count >= current_bit_count)
969 current_bit_count = count;
973 gcc_assert (best_fit);
977 insn_flags = sel->flags;
979 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
980 if (arm_tune == arm_none)
981 arm_tune = (enum processor_type) (sel - all_cores);
984 /* The processor for which we should tune should now have been
986 gcc_assert (arm_tune != arm_none);
988 tune_flags = all_cores[(int)arm_tune].flags;
990 targetm.rtx_costs = arm_size_rtx_costs;
992 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
994 /* Make sure that the processor choice does not conflict with any of the
995 other command line choices. */
996 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
998 warning (0, "target CPU does not support interworking" );
999 target_flags &= ~MASK_INTERWORK;
1002 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1004 warning (0, "target CPU does not support THUMB instructions");
1005 target_flags &= ~MASK_THUMB;
1008 if (TARGET_APCS_FRAME && TARGET_THUMB)
1010 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1011 target_flags &= ~MASK_APCS_FRAME;
1014 /* Callee super interworking implies thumb interworking. Adding
1015 this to the flags here simplifies the logic elsewhere. */
1016 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1017 target_flags |= MASK_INTERWORK;
1019 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1020 from here where no function is being compiled currently. */
1021 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1022 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1024 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1025 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1027 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1028 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1030 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1032 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1033 target_flags |= MASK_APCS_FRAME;
1036 if (TARGET_POKE_FUNCTION_NAME)
1037 target_flags |= MASK_APCS_FRAME;
1039 if (TARGET_APCS_REENT && flag_pic)
1040 error ("-fpic and -mapcs-reent are incompatible");
1042 if (TARGET_APCS_REENT)
1043 warning (0, "APCS reentrant code not supported. Ignored");
1045 /* If this target is normally configured to use APCS frames, warn if they
1046 are turned off and debugging is turned on. */
1048 && write_symbols != NO_DEBUG
1049 && !TARGET_APCS_FRAME
1050 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1051 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1053 /* If stack checking is disabled, we can use r10 as the PIC register,
1054 which keeps r9 available. */
1056 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1058 if (TARGET_APCS_FLOAT)
1059 warning (0, "passing floating point arguments in fp regs not yet supported");
1061 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1062 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1063 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1064 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1065 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1066 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1067 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1068 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1069 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1071 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1072 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1073 thumb_code = (TARGET_ARM == 0);
1074 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1075 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1076 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1078 /* V5 code we generate is completely interworking capable, so we turn off
1079 TARGET_INTERWORK here to avoid many tests later on. */
1081 /* XXX However, we must pass the right pre-processor defines to CPP
1082 or GLD can get confused. This is a hack. */
1083 if (TARGET_INTERWORK)
1084 arm_cpp_interwork = 1;
1087 target_flags &= ~MASK_INTERWORK;
1089 if (target_abi_name)
1091 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1093 if (streq (arm_all_abis[i].name, target_abi_name))
1095 arm_abi = arm_all_abis[i].abi_type;
1099 if (i == ARRAY_SIZE (arm_all_abis))
1100 error ("invalid ABI option: -mabi=%s", target_abi_name);
1103 arm_abi = ARM_DEFAULT_ABI;
1105 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1106 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1108 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1109 error ("iwmmxt abi requires an iwmmxt capable cpu");
1111 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1112 if (target_fpu_name == NULL && target_fpe_name != NULL)
1114 if (streq (target_fpe_name, "2"))
1115 target_fpu_name = "fpe2";
1116 else if (streq (target_fpe_name, "3"))
1117 target_fpu_name = "fpe3";
1119 error ("invalid floating point emulation option: -mfpe=%s",
1122 if (target_fpu_name != NULL)
1124 /* The user specified a FPU. */
1125 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1127 if (streq (all_fpus[i].name, target_fpu_name))
1129 arm_fpu_arch = all_fpus[i].fpu;
1130 arm_fpu_tune = arm_fpu_arch;
1131 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1135 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1136 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1140 #ifdef FPUTYPE_DEFAULT
1141 /* Use the default if it is specified for this platform. */
1142 arm_fpu_arch = FPUTYPE_DEFAULT;
1143 arm_fpu_tune = FPUTYPE_DEFAULT;
1145 /* Pick one based on CPU type. */
1146 /* ??? Some targets assume FPA is the default.
1147 if ((insn_flags & FL_VFP) != 0)
1148 arm_fpu_arch = FPUTYPE_VFP;
1151 if (arm_arch_cirrus)
1152 arm_fpu_arch = FPUTYPE_MAVERICK;
1154 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1156 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1157 arm_fpu_tune = FPUTYPE_FPA;
1159 arm_fpu_tune = arm_fpu_arch;
1160 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1161 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1164 if (target_float_abi_name != NULL)
1166 /* The user specified a FP ABI. */
1167 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1169 if (streq (all_float_abis[i].name, target_float_abi_name))
1171 arm_float_abi = all_float_abis[i].abi_type;
1175 if (i == ARRAY_SIZE (all_float_abis))
1176 error ("invalid floating point abi: -mfloat-abi=%s",
1177 target_float_abi_name);
1180 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1182 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1183 sorry ("-mfloat-abi=hard and VFP");
1185 /* If soft-float is specified then don't use FPU. */
1186 if (TARGET_SOFT_FLOAT)
1187 arm_fpu_arch = FPUTYPE_NONE;
1189 /* For arm2/3 there is no need to do any scheduling if there is only
1190 a floating point emulator, or we are doing software floating-point. */
1191 if ((TARGET_SOFT_FLOAT
1192 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1193 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1194 && (tune_flags & FL_MODE32) == 0)
1195 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1197 /* Override the default structure alignment for AAPCS ABI. */
1198 if (TARGET_AAPCS_BASED)
1199 arm_structure_size_boundary = 8;
1201 if (structure_size_string != NULL)
1203 int size = strtol (structure_size_string, NULL, 0);
1205 if (size == 8 || size == 32
1206 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1207 arm_structure_size_boundary = size;
1209 warning (0, "structure size boundary can only be set to %s",
1210 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1213 if (arm_pic_register_string != NULL)
1215 int pic_register = decode_reg_name (arm_pic_register_string);
1218 warning (0, "-mpic-register= is useless without -fpic");
1220 /* Prevent the user from choosing an obviously stupid PIC register. */
1221 else if (pic_register < 0 || call_used_regs[pic_register]
1222 || pic_register == HARD_FRAME_POINTER_REGNUM
1223 || pic_register == STACK_POINTER_REGNUM
1224 || pic_register >= PC_REGNUM)
1225 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1227 arm_pic_register = pic_register;
1230 if (TARGET_THUMB && flag_schedule_insns)
1232 /* Don't warn since it's on by default in -O2. */
1233 flag_schedule_insns = 0;
1238 arm_constant_limit = 1;
1240 /* If optimizing for size, bump the number of instructions that we
1241 are prepared to conditionally execute (even on a StrongARM). */
1242 max_insns_skipped = 6;
1246 /* For processors with load scheduling, it never costs more than
1247 2 cycles to load a constant, and the load scheduler may well
1248 reduce that to 1. */
1250 arm_constant_limit = 1;
1252 /* On XScale the longer latency of a load makes it more difficult
1253 to achieve a good schedule, so it's faster to synthesize
1254 constants that can be done in two insns. */
1255 if (arm_tune_xscale)
1256 arm_constant_limit = 2;
1258 /* StrongARM has early execution of branches, so a sequence
1259 that is worth skipping is shorter. */
1260 if (arm_tune_strongarm)
1261 max_insns_skipped = 3;
1264 /* Register global variables with the garbage collector. */
1265 arm_add_gc_roots ();
1269 arm_add_gc_roots (void)
1271 gcc_obstack_init(&minipool_obstack);
1272 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1275 /* A table of known ARM exception types.
1276 For use with the interrupt function attribute. */
1280 const char *const arg;
1281 const unsigned long return_value;
1285 static const isr_attribute_arg isr_attribute_args [] =
1287 { "IRQ", ARM_FT_ISR },
1288 { "irq", ARM_FT_ISR },
1289 { "FIQ", ARM_FT_FIQ },
1290 { "fiq", ARM_FT_FIQ },
1291 { "ABORT", ARM_FT_ISR },
1292 { "abort", ARM_FT_ISR },
1293 { "ABORT", ARM_FT_ISR },
1294 { "abort", ARM_FT_ISR },
1295 { "UNDEF", ARM_FT_EXCEPTION },
1296 { "undef", ARM_FT_EXCEPTION },
1297 { "SWI", ARM_FT_EXCEPTION },
1298 { "swi", ARM_FT_EXCEPTION },
1299 { NULL, ARM_FT_NORMAL }
1302 /* Returns the (interrupt) function type of the current
1303 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1305 static unsigned long
1306 arm_isr_value (tree argument)
1308 const isr_attribute_arg * ptr;
1311 /* No argument - default to IRQ. */
1312 if (argument == NULL_TREE)
1315 /* Get the value of the argument. */
1316 if (TREE_VALUE (argument) == NULL_TREE
1317 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1318 return ARM_FT_UNKNOWN;
1320 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1322 /* Check it against the list of known arguments. */
1323 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1324 if (streq (arg, ptr->arg))
1325 return ptr->return_value;
1327 /* An unrecognized interrupt type. */
1328 return ARM_FT_UNKNOWN;
1331 /* Computes the type of the current function. */
1333 static unsigned long
1334 arm_compute_func_type (void)
1336 unsigned long type = ARM_FT_UNKNOWN;
1340 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1342 /* Decide if the current function is volatile. Such functions
1343 never return, and many memory cycles can be saved by not storing
1344 register values that will never be needed again. This optimization
1345 was added to speed up context switching in a kernel application. */
1347 && TREE_NOTHROW (current_function_decl)
1348 && TREE_THIS_VOLATILE (current_function_decl))
1349 type |= ARM_FT_VOLATILE;
1351 if (cfun->static_chain_decl != NULL)
1352 type |= ARM_FT_NESTED;
1354 attr = DECL_ATTRIBUTES (current_function_decl);
1356 a = lookup_attribute ("naked", attr);
1358 type |= ARM_FT_NAKED;
1360 a = lookup_attribute ("isr", attr);
1362 a = lookup_attribute ("interrupt", attr);
1365 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1367 type |= arm_isr_value (TREE_VALUE (a));
1372 /* Returns the type of the current function. */
1375 arm_current_func_type (void)
1377 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1378 cfun->machine->func_type = arm_compute_func_type ();
1380 return cfun->machine->func_type;
1383 /* Return 1 if it is possible to return using a single instruction.
1384 If SIBLING is non-null, this is a test for a return before a sibling
1385 call. SIBLING is the call insn, so we can examine its register usage. */
1388 use_return_insn (int iscond, rtx sibling)
1391 unsigned int func_type;
1392 unsigned long saved_int_regs;
1393 unsigned HOST_WIDE_INT stack_adjust;
1394 arm_stack_offsets *offsets;
1396 /* Never use a return instruction before reload has run. */
1397 if (!reload_completed)
1400 func_type = arm_current_func_type ();
1402 /* Naked functions and volatile functions need special
1404 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1407 /* So do interrupt functions that use the frame pointer. */
1408 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1411 offsets = arm_get_frame_offsets ();
1412 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1414 /* As do variadic functions. */
1415 if (current_function_pretend_args_size
1416 || cfun->machine->uses_anonymous_args
1417 /* Or if the function calls __builtin_eh_return () */
1418 || current_function_calls_eh_return
1419 /* Or if the function calls alloca */
1420 || current_function_calls_alloca
1421 /* Or if there is a stack adjustment. However, if the stack pointer
1422 is saved on the stack, we can use a pre-incrementing stack load. */
1423 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1426 saved_int_regs = arm_compute_save_reg_mask ();
1428 /* Unfortunately, the insn
1430 ldmib sp, {..., sp, ...}
1432 triggers a bug on most SA-110 based devices, such that the stack
1433 pointer won't be correctly restored if the instruction takes a
1434 page fault. We work around this problem by popping r3 along with
1435 the other registers, since that is never slower than executing
1436 another instruction.
1438 We test for !arm_arch5 here, because code for any architecture
1439 less than this could potentially be run on one of the buggy
1441 if (stack_adjust == 4 && !arm_arch5)
1443 /* Validate that r3 is a call-clobbered register (always true in
1444 the default abi) ... */
1445 if (!call_used_regs[3])
1448 /* ... that it isn't being used for a return value ... */
1449 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1452 /* ... or for a tail-call argument ... */
1455 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1457 if (find_regno_fusage (sibling, USE, 3))
1461 /* ... and that there are no call-saved registers in r0-r2
1462 (always true in the default ABI). */
1463 if (saved_int_regs & 0x7)
1467 /* Can't be done if interworking with Thumb, and any registers have been
1469 if (TARGET_INTERWORK && saved_int_regs != 0)
1472 /* On StrongARM, conditional returns are expensive if they aren't
1473 taken and multiple registers have been stacked. */
1474 if (iscond && arm_tune_strongarm)
1476 /* Conditional return when just the LR is stored is a simple
1477 conditional-load instruction, that's not expensive. */
1478 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1481 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1485 /* If there are saved registers but the LR isn't saved, then we need
1486 two instructions for the return. */
1487 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1490 /* Can't be done if any of the FPA regs are pushed,
1491 since this also requires an insn. */
1492 if (TARGET_HARD_FLOAT && TARGET_FPA)
1493 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1494 if (regs_ever_live[regno] && !call_used_regs[regno])
1497 /* Likewise VFP regs. */
1498 if (TARGET_HARD_FLOAT && TARGET_VFP)
1499 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1500 if (regs_ever_live[regno] && !call_used_regs[regno])
1503 if (TARGET_REALLY_IWMMXT)
1504 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1505 if (regs_ever_live[regno] && ! call_used_regs [regno])
1511 /* Return TRUE if int I is a valid immediate ARM constant. */
1514 const_ok_for_arm (HOST_WIDE_INT i)
1518 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1519 be all zero, or all one. */
1520 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1521 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1522 != ((~(unsigned HOST_WIDE_INT) 0)
1523 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1526 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1528 /* Fast return for 0 and small values. We must do this for zero, since
1529 the code below can't handle that one case. */
1530 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1533 /* Get the number of trailing zeros, rounded down to the nearest even
1535 lowbit = (ffs ((int) i) - 1) & ~1;
1537 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1539 else if (lowbit <= 4
1540 && ((i & ~0xc000003f) == 0
1541 || (i & ~0xf000000f) == 0
1542 || (i & ~0xfc000003) == 0))
1548 /* Return true if I is a valid constant for the operation CODE. */
1550 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1552 if (const_ok_for_arm (i))
1558 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1560 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1566 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1573 /* Emit a sequence of insns to handle a large constant.
1574 CODE is the code of the operation required, it can be any of SET, PLUS,
1575 IOR, AND, XOR, MINUS;
1576 MODE is the mode in which the operation is being performed;
1577 VAL is the integer to operate on;
1578 SOURCE is the other operand (a register, or a null-pointer for SET);
1579 SUBTARGETS means it is safe to create scratch registers if that will
1580 either produce a simpler sequence, or we will want to cse the values.
1581 Return value is the number of insns emitted. */
1584 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1585 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1589 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1590 cond = COND_EXEC_TEST (PATTERN (insn));
1594 if (subtargets || code == SET
1595 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1596 && REGNO (target) != REGNO (source)))
1598 /* After arm_reorg has been called, we can't fix up expensive
1599 constants by pushing them into memory so we must synthesize
1600 them in-line, regardless of the cost. This is only likely to
1601 be more costly on chips that have load delay slots and we are
1602 compiling without running the scheduler (so no splitting
1603 occurred before the final instruction emission).
1605 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1607 if (!after_arm_reorg
1609 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1611 > arm_constant_limit + (code != SET)))
1615 /* Currently SET is the only monadic value for CODE, all
1616 the rest are diadic. */
1617 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1622 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1624 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1625 /* For MINUS, the value is subtracted from, since we never
1626 have subtraction of a constant. */
1628 emit_insn (gen_rtx_SET (VOIDmode, target,
1629 gen_rtx_MINUS (mode, temp, source)));
1631 emit_insn (gen_rtx_SET (VOIDmode, target,
1632 gen_rtx_fmt_ee (code, mode, source, temp)));
1638 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1643 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1645 HOST_WIDE_INT temp1;
1653 if (remainder & (3 << (i - 2)))
1658 temp1 = remainder & ((0x0ff << end)
1659 | ((i < end) ? (0xff >> (32 - end)) : 0));
1660 remainder &= ~temp1;
1665 } while (remainder);
1669 /* Emit an instruction with the indicated PATTERN. If COND is
1670 non-NULL, conditionalize the execution of the instruction on COND
1674 emit_constant_insn (rtx cond, rtx pattern)
1677 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1678 emit_insn (pattern);
1681 /* As above, but extra parameter GENERATE which, if clear, suppresses
1685 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1686 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1691 int can_negate_initial = 0;
1694 int num_bits_set = 0;
1695 int set_sign_bit_copies = 0;
1696 int clear_sign_bit_copies = 0;
1697 int clear_zero_bit_copies = 0;
1698 int set_zero_bit_copies = 0;
1700 unsigned HOST_WIDE_INT temp1, temp2;
1701 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1703 /* Find out which operations are safe for a given CODE. Also do a quick
1704 check for degenerate cases; these can occur when DImode operations
1716 can_negate_initial = 1;
1720 if (remainder == 0xffffffff)
1723 emit_constant_insn (cond,
1724 gen_rtx_SET (VOIDmode, target,
1725 GEN_INT (ARM_SIGN_EXTEND (val))));
1730 if (reload_completed && rtx_equal_p (target, source))
1733 emit_constant_insn (cond,
1734 gen_rtx_SET (VOIDmode, target, source));
1743 emit_constant_insn (cond,
1744 gen_rtx_SET (VOIDmode, target, const0_rtx));
1747 if (remainder == 0xffffffff)
1749 if (reload_completed && rtx_equal_p (target, source))
1752 emit_constant_insn (cond,
1753 gen_rtx_SET (VOIDmode, target, source));
1762 if (reload_completed && rtx_equal_p (target, source))
1765 emit_constant_insn (cond,
1766 gen_rtx_SET (VOIDmode, target, source));
1770 /* We don't know how to handle other cases yet. */
1771 gcc_assert (remainder == 0xffffffff);
1774 emit_constant_insn (cond,
1775 gen_rtx_SET (VOIDmode, target,
1776 gen_rtx_NOT (mode, source)));
1780 /* We treat MINUS as (val - source), since (source - val) is always
1781 passed as (source + (-val)). */
1785 emit_constant_insn (cond,
1786 gen_rtx_SET (VOIDmode, target,
1787 gen_rtx_NEG (mode, source)));
1790 if (const_ok_for_arm (val))
1793 emit_constant_insn (cond,
1794 gen_rtx_SET (VOIDmode, target,
1795 gen_rtx_MINUS (mode, GEN_INT (val),
1807 /* If we can do it in one insn get out quickly. */
1808 if (const_ok_for_arm (val)
1809 || (can_negate_initial && const_ok_for_arm (-val))
1810 || (can_invert && const_ok_for_arm (~val)))
1813 emit_constant_insn (cond,
1814 gen_rtx_SET (VOIDmode, target,
1816 ? gen_rtx_fmt_ee (code, mode, source,
1822 /* Calculate a few attributes that may be useful for specific
1824 for (i = 31; i >= 0; i--)
1826 if ((remainder & (1 << i)) == 0)
1827 clear_sign_bit_copies++;
1832 for (i = 31; i >= 0; i--)
1834 if ((remainder & (1 << i)) != 0)
1835 set_sign_bit_copies++;
1840 for (i = 0; i <= 31; i++)
1842 if ((remainder & (1 << i)) == 0)
1843 clear_zero_bit_copies++;
1848 for (i = 0; i <= 31; i++)
1850 if ((remainder & (1 << i)) != 0)
1851 set_zero_bit_copies++;
1859 /* See if we can do this by sign_extending a constant that is known
1860 to be negative. This is a good, way of doing it, since the shift
1861 may well merge into a subsequent insn. */
1862 if (set_sign_bit_copies > 1)
1864 if (const_ok_for_arm
1865 (temp1 = ARM_SIGN_EXTEND (remainder
1866 << (set_sign_bit_copies - 1))))
1870 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1871 emit_constant_insn (cond,
1872 gen_rtx_SET (VOIDmode, new_src,
1874 emit_constant_insn (cond,
1875 gen_ashrsi3 (target, new_src,
1876 GEN_INT (set_sign_bit_copies - 1)));
1880 /* For an inverted constant, we will need to set the low bits,
1881 these will be shifted out of harm's way. */
1882 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1883 if (const_ok_for_arm (~temp1))
1887 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1888 emit_constant_insn (cond,
1889 gen_rtx_SET (VOIDmode, new_src,
1891 emit_constant_insn (cond,
1892 gen_ashrsi3 (target, new_src,
1893 GEN_INT (set_sign_bit_copies - 1)));
1899 /* See if we can calculate the value as the difference between two
1900 valid immediates. */
1901 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
1903 int topshift = clear_sign_bit_copies & ~1;
1905 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
1906 & (0xff000000 >> topshift));
1908 /* If temp1 is zero, then that means the 9 most significant
1909 bits of remainder were 1 and we've caused it to overflow.
1910 When topshift is 0 we don't need to do anything since we
1911 can borrow from 'bit 32'. */
1912 if (temp1 == 0 && topshift != 0)
1913 temp1 = 0x80000000 >> (topshift - 1);
1915 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
1917 if (const_ok_for_arm (temp2))
1921 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1922 emit_constant_insn (cond,
1923 gen_rtx_SET (VOIDmode, new_src,
1925 emit_constant_insn (cond,
1926 gen_addsi3 (target, new_src,
1934 /* See if we can generate this by setting the bottom (or the top)
1935 16 bits, and then shifting these into the other half of the
1936 word. We only look for the simplest cases, to do more would cost
1937 too much. Be careful, however, not to generate this when the
1938 alternative would take fewer insns. */
1939 if (val & 0xffff0000)
1941 temp1 = remainder & 0xffff0000;
1942 temp2 = remainder & 0x0000ffff;
1944 /* Overlaps outside this range are best done using other methods. */
1945 for (i = 9; i < 24; i++)
1947 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1948 && !const_ok_for_arm (temp2))
1950 rtx new_src = (subtargets
1951 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1953 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1954 source, subtargets, generate);
1962 gen_rtx_ASHIFT (mode, source,
1969 /* Don't duplicate cases already considered. */
1970 for (i = 17; i < 24; i++)
1972 if (((temp1 | (temp1 >> i)) == remainder)
1973 && !const_ok_for_arm (temp1))
1975 rtx new_src = (subtargets
1976 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1978 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1979 source, subtargets, generate);
1984 gen_rtx_SET (VOIDmode, target,
1987 gen_rtx_LSHIFTRT (mode, source,
1998 /* If we have IOR or XOR, and the constant can be loaded in a
1999 single instruction, and we can find a temporary to put it in,
2000 then this can be done in two instructions instead of 3-4. */
2002 /* TARGET can't be NULL if SUBTARGETS is 0 */
2003 || (reload_completed && !reg_mentioned_p (target, source)))
2005 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2009 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2011 emit_constant_insn (cond,
2012 gen_rtx_SET (VOIDmode, sub,
2014 emit_constant_insn (cond,
2015 gen_rtx_SET (VOIDmode, target,
2016 gen_rtx_fmt_ee (code, mode,
2026 if (set_sign_bit_copies > 8
2027 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2031 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2032 rtx shift = GEN_INT (set_sign_bit_copies);
2036 gen_rtx_SET (VOIDmode, sub,
2038 gen_rtx_ASHIFT (mode,
2043 gen_rtx_SET (VOIDmode, target,
2045 gen_rtx_LSHIFTRT (mode, sub,
2051 if (set_zero_bit_copies > 8
2052 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2056 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2057 rtx shift = GEN_INT (set_zero_bit_copies);
2061 gen_rtx_SET (VOIDmode, sub,
2063 gen_rtx_LSHIFTRT (mode,
2068 gen_rtx_SET (VOIDmode, target,
2070 gen_rtx_ASHIFT (mode, sub,
2076 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2080 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2081 emit_constant_insn (cond,
2082 gen_rtx_SET (VOIDmode, sub,
2083 gen_rtx_NOT (mode, source)));
2086 sub = gen_reg_rtx (mode);
2087 emit_constant_insn (cond,
2088 gen_rtx_SET (VOIDmode, sub,
2089 gen_rtx_AND (mode, source,
2091 emit_constant_insn (cond,
2092 gen_rtx_SET (VOIDmode, target,
2093 gen_rtx_NOT (mode, sub)));
2100 /* See if two shifts will do 2 or more insn's worth of work. */
2101 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2103 HOST_WIDE_INT shift_mask = ((0xffffffff
2104 << (32 - clear_sign_bit_copies))
2107 if ((remainder | shift_mask) != 0xffffffff)
2111 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2112 insns = arm_gen_constant (AND, mode, cond,
2113 remainder | shift_mask,
2114 new_src, source, subtargets, 1);
2119 rtx targ = subtargets ? NULL_RTX : target;
2120 insns = arm_gen_constant (AND, mode, cond,
2121 remainder | shift_mask,
2122 targ, source, subtargets, 0);
2128 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2129 rtx shift = GEN_INT (clear_sign_bit_copies);
2131 emit_insn (gen_ashlsi3 (new_src, source, shift));
2132 emit_insn (gen_lshrsi3 (target, new_src, shift));
2138 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2140 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2142 if ((remainder | shift_mask) != 0xffffffff)
2146 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2148 insns = arm_gen_constant (AND, mode, cond,
2149 remainder | shift_mask,
2150 new_src, source, subtargets, 1);
2155 rtx targ = subtargets ? NULL_RTX : target;
2157 insns = arm_gen_constant (AND, mode, cond,
2158 remainder | shift_mask,
2159 targ, source, subtargets, 0);
2165 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2166 rtx shift = GEN_INT (clear_zero_bit_copies);
2168 emit_insn (gen_lshrsi3 (new_src, source, shift));
2169 emit_insn (gen_ashlsi3 (target, new_src, shift));
2181 for (i = 0; i < 32; i++)
2182 if (remainder & (1 << i))
2185 if (code == AND || (can_invert && num_bits_set > 16))
2186 remainder = (~remainder) & 0xffffffff;
2187 else if (code == PLUS && num_bits_set > 16)
2188 remainder = (-remainder) & 0xffffffff;
2195 /* Now try and find a way of doing the job in either two or three
2197 We start by looking for the largest block of zeros that are aligned on
2198 a 2-bit boundary, we then fill up the temps, wrapping around to the
2199 top of the word when we drop off the bottom.
2200 In the worst case this code should produce no more than four insns. */
2203 int best_consecutive_zeros = 0;
2205 for (i = 0; i < 32; i += 2)
2207 int consecutive_zeros = 0;
2209 if (!(remainder & (3 << i)))
2211 while ((i < 32) && !(remainder & (3 << i)))
2213 consecutive_zeros += 2;
2216 if (consecutive_zeros > best_consecutive_zeros)
2218 best_consecutive_zeros = consecutive_zeros;
2219 best_start = i - consecutive_zeros;
2225 /* So long as it won't require any more insns to do so, it's
2226 desirable to emit a small constant (in bits 0...9) in the last
2227 insn. This way there is more chance that it can be combined with
2228 a later addressing insn to form a pre-indexed load or store
2229 operation. Consider:
2231 *((volatile int *)0xe0000100) = 1;
2232 *((volatile int *)0xe0000110) = 2;
2234 We want this to wind up as:
2238 str rB, [rA, #0x100]
2240 str rB, [rA, #0x110]
2242 rather than having to synthesize both large constants from scratch.
2244 Therefore, we calculate how many insns would be required to emit
2245 the constant starting from `best_start', and also starting from
2246 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2247 yield a shorter sequence, we may as well use zero. */
2249 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2250 && (count_insns_for_constant (remainder, 0) <=
2251 count_insns_for_constant (remainder, best_start)))
2254 /* Now start emitting the insns. */
2262 if (remainder & (3 << (i - 2)))
2267 temp1 = remainder & ((0x0ff << end)
2268 | ((i < end) ? (0xff >> (32 - end)) : 0));
2269 remainder &= ~temp1;
2273 rtx new_src, temp1_rtx;
2275 if (code == SET || code == MINUS)
2277 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2278 if (can_invert && code != MINUS)
2283 if (remainder && subtargets)
2284 new_src = gen_reg_rtx (mode);
2289 else if (can_negate)
2293 temp1 = trunc_int_for_mode (temp1, mode);
2294 temp1_rtx = GEN_INT (temp1);
2298 else if (code == MINUS)
2299 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2301 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2303 emit_constant_insn (cond,
2304 gen_rtx_SET (VOIDmode, new_src,
2314 else if (code == MINUS)
2328 /* Canonicalize a comparison so that we are more likely to recognize it.
2329 This can be done for a few constant compares, where we can make the
2330 immediate value easier to load. */
2333 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2336 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2337 unsigned HOST_WIDE_INT maxval;
2338 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2349 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2351 *op1 = GEN_INT (i + 1);
2352 return code == GT ? GE : LT;
2359 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2361 *op1 = GEN_INT (i - 1);
2362 return code == GE ? GT : LE;
2368 if (i != ~((unsigned HOST_WIDE_INT) 0)
2369 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2371 *op1 = GEN_INT (i + 1);
2372 return code == GTU ? GEU : LTU;
2379 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2381 *op1 = GEN_INT (i - 1);
2382 return code == GEU ? GTU : LEU;
2394 /* Define how to find the value returned by a function. */
2397 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2399 enum machine_mode mode;
2400 int unsignedp ATTRIBUTE_UNUSED;
2401 rtx r ATTRIBUTE_UNUSED;
2403 mode = TYPE_MODE (type);
2404 /* Promote integer types. */
2405 if (INTEGRAL_TYPE_P (type))
2406 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2408 /* Promotes small structs returned in a register to full-word size
2409 for big-endian AAPCS. */
2410 if (arm_return_in_msb (type))
2412 HOST_WIDE_INT size = int_size_in_bytes (type);
2413 if (size % UNITS_PER_WORD != 0)
2415 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2416 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2420 return LIBCALL_VALUE(mode);
2423 /* Determine the amount of memory needed to store the possible return
2424 registers of an untyped call. */
2426 arm_apply_result_size (void)
2432 if (TARGET_HARD_FLOAT_ABI)
2436 if (TARGET_MAVERICK)
2439 if (TARGET_IWMMXT_ABI)
2446 /* Decide whether a type should be returned in memory (true)
2447 or in a register (false). This is called by the macro
2448 RETURN_IN_MEMORY. */
2450 arm_return_in_memory (tree type)
2454 if (!AGGREGATE_TYPE_P (type) &&
2455 (TREE_CODE (type) != VECTOR_TYPE) &&
2456 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2457 /* All simple types are returned in registers.
2458 For AAPCS, complex types are treated the same as aggregates. */
2461 size = int_size_in_bytes (type);
2463 if (arm_abi != ARM_ABI_APCS)
2465 /* ATPCS and later return aggregate types in memory only if they are
2466 larger than a word (or are variable size). */
2467 return (size < 0 || size > UNITS_PER_WORD);
2470 /* To maximize backwards compatibility with previous versions of gcc,
2471 return vectors up to 4 words in registers. */
2472 if (TREE_CODE (type) == VECTOR_TYPE)
2473 return (size < 0 || size > (4 * UNITS_PER_WORD));
2475 /* For the arm-wince targets we choose to be compatible with Microsoft's
2476 ARM and Thumb compilers, which always return aggregates in memory. */
2478 /* All structures/unions bigger than one word are returned in memory.
2479 Also catch the case where int_size_in_bytes returns -1. In this case
2480 the aggregate is either huge or of variable size, and in either case
2481 we will want to return it via memory and not in a register. */
2482 if (size < 0 || size > UNITS_PER_WORD)
2485 if (TREE_CODE (type) == RECORD_TYPE)
2489 /* For a struct the APCS says that we only return in a register
2490 if the type is 'integer like' and every addressable element
2491 has an offset of zero. For practical purposes this means
2492 that the structure can have at most one non bit-field element
2493 and that this element must be the first one in the structure. */
2495 /* Find the first field, ignoring non FIELD_DECL things which will
2496 have been created by C++. */
2497 for (field = TYPE_FIELDS (type);
2498 field && TREE_CODE (field) != FIELD_DECL;
2499 field = TREE_CHAIN (field))
2503 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2505 /* Check that the first field is valid for returning in a register. */
2507 /* ... Floats are not allowed */
2508 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2511 /* ... Aggregates that are not themselves valid for returning in
2512 a register are not allowed. */
2513 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2516 /* Now check the remaining fields, if any. Only bitfields are allowed,
2517 since they are not addressable. */
2518 for (field = TREE_CHAIN (field);
2520 field = TREE_CHAIN (field))
2522 if (TREE_CODE (field) != FIELD_DECL)
2525 if (!DECL_BIT_FIELD_TYPE (field))
2532 if (TREE_CODE (type) == UNION_TYPE)
2536 /* Unions can be returned in registers if every element is
2537 integral, or can be returned in an integer register. */
2538 for (field = TYPE_FIELDS (type);
2540 field = TREE_CHAIN (field))
2542 if (TREE_CODE (field) != FIELD_DECL)
2545 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2548 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2554 #endif /* not ARM_WINCE */
2556 /* Return all other types in memory. */
2560 /* Indicate whether or not words of a double are in big-endian order. */
2563 arm_float_words_big_endian (void)
2565 if (TARGET_MAVERICK)
2568 /* For FPA, float words are always big-endian. For VFP, floats words
2569 follow the memory system mode. */
2577 return (TARGET_BIG_END ? 1 : 0);
2582 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2583 for a call to a function whose data type is FNTYPE.
2584 For a library call, FNTYPE is NULL. */
2586 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2587 rtx libname ATTRIBUTE_UNUSED,
2588 tree fndecl ATTRIBUTE_UNUSED)
2590 /* On the ARM, the offset starts at 0. */
2591 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2592 pcum->iwmmxt_nregs = 0;
2593 pcum->can_split = true;
2595 pcum->call_cookie = CALL_NORMAL;
2597 if (TARGET_LONG_CALLS)
2598 pcum->call_cookie = CALL_LONG;
2600 /* Check for long call/short call attributes. The attributes
2601 override any command line option. */
2604 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2605 pcum->call_cookie = CALL_SHORT;
2606 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2607 pcum->call_cookie = CALL_LONG;
2610 /* Varargs vectors are treated the same as long long.
2611 named_count avoids having to change the way arm handles 'named' */
2612 pcum->named_count = 0;
2615 if (TARGET_REALLY_IWMMXT && fntype)
2619 for (fn_arg = TYPE_ARG_TYPES (fntype);
2621 fn_arg = TREE_CHAIN (fn_arg))
2622 pcum->named_count += 1;
2624 if (! pcum->named_count)
2625 pcum->named_count = INT_MAX;
2630 /* Return true if mode/type need doubleword alignment. */
2632 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2634 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2635 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2639 /* Determine where to put an argument to a function.
2640 Value is zero to push the argument on the stack,
2641 or a hard register in which to store the argument.
2643 MODE is the argument's machine mode.
2644 TYPE is the data type of the argument (as a tree).
2645 This is null for libcalls where that information may
2647 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2648 the preceding args and about the function being called.
2649 NAMED is nonzero if this argument is a named parameter
2650 (otherwise it is an extra parameter matching an ellipsis). */
2653 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2654 tree type, int named)
2658 /* Varargs vectors are treated the same as long long.
2659 named_count avoids having to change the way arm handles 'named' */
2660 if (TARGET_IWMMXT_ABI
2661 && arm_vector_mode_supported_p (mode)
2662 && pcum->named_count > pcum->nargs + 1)
2664 if (pcum->iwmmxt_nregs <= 9)
2665 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2668 pcum->can_split = false;
2673 /* Put doubleword aligned quantities in even register pairs. */
2675 && ARM_DOUBLEWORD_ALIGN
2676 && arm_needs_doubleword_align (mode, type))
2679 if (mode == VOIDmode)
2680 /* Compute operand 2 of the call insn. */
2681 return GEN_INT (pcum->call_cookie);
2683 /* Only allow splitting an arg between regs and memory if all preceding
2684 args were allocated to regs. For args passed by reference we only count
2685 the reference pointer. */
2686 if (pcum->can_split)
2689 nregs = ARM_NUM_REGS2 (mode, type);
2691 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2694 return gen_rtx_REG (mode, pcum->nregs);
2698 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2699 tree type, bool named ATTRIBUTE_UNUSED)
2701 int nregs = pcum->nregs;
2703 if (arm_vector_mode_supported_p (mode))
2706 if (NUM_ARG_REGS > nregs
2707 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2709 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2714 /* Variable sized types are passed by reference. This is a GCC
2715 extension to the ARM ABI. */
2718 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2719 enum machine_mode mode ATTRIBUTE_UNUSED,
2720 tree type, bool named ATTRIBUTE_UNUSED)
2722 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2725 /* Encode the current state of the #pragma [no_]long_calls. */
2728 OFF, /* No #pramgma [no_]long_calls is in effect. */
2729 LONG, /* #pragma long_calls is in effect. */
2730 SHORT /* #pragma no_long_calls is in effect. */
2733 static arm_pragma_enum arm_pragma_long_calls = OFF;
2736 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2738 arm_pragma_long_calls = LONG;
2742 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2744 arm_pragma_long_calls = SHORT;
2748 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2750 arm_pragma_long_calls = OFF;
2753 /* Table of machine attributes. */
2754 const struct attribute_spec arm_attribute_table[] =
2756 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2757 /* Function calls made to this symbol must be done indirectly, because
2758 it may lie outside of the 26 bit addressing range of a normal function
2760 { "long_call", 0, 0, false, true, true, NULL },
2761 /* Whereas these functions are always known to reside within the 26 bit
2762 addressing range. */
2763 { "short_call", 0, 0, false, true, true, NULL },
2764 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2765 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2766 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2767 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2769 /* ARM/PE has three new attributes:
2771 dllexport - for exporting a function/variable that will live in a dll
2772 dllimport - for importing a function/variable from a dll
2774 Microsoft allows multiple declspecs in one __declspec, separating
2775 them with spaces. We do NOT support this. Instead, use __declspec
2778 { "dllimport", 0, 0, true, false, false, NULL },
2779 { "dllexport", 0, 0, true, false, false, NULL },
2780 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2781 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2782 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2783 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2784 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2786 { NULL, 0, 0, false, false, false, NULL }
2789 /* Handle an attribute requiring a FUNCTION_DECL;
2790 arguments as in struct attribute_spec.handler. */
2792 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2793 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2795 if (TREE_CODE (*node) != FUNCTION_DECL)
2797 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2798 IDENTIFIER_POINTER (name));
2799 *no_add_attrs = true;
2805 /* Handle an "interrupt" or "isr" attribute;
2806 arguments as in struct attribute_spec.handler. */
2808 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2813 if (TREE_CODE (*node) != FUNCTION_DECL)
2815 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2816 IDENTIFIER_POINTER (name));
2817 *no_add_attrs = true;
2819 /* FIXME: the argument if any is checked for type attributes;
2820 should it be checked for decl ones? */
2824 if (TREE_CODE (*node) == FUNCTION_TYPE
2825 || TREE_CODE (*node) == METHOD_TYPE)
2827 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2829 warning (OPT_Wattributes, "%qs attribute ignored",
2830 IDENTIFIER_POINTER (name));
2831 *no_add_attrs = true;
2834 else if (TREE_CODE (*node) == POINTER_TYPE
2835 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2836 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2837 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2839 *node = build_variant_type_copy (*node);
2840 TREE_TYPE (*node) = build_type_attribute_variant
2842 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2843 *no_add_attrs = true;
2847 /* Possibly pass this attribute on from the type to a decl. */
2848 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2849 | (int) ATTR_FLAG_FUNCTION_NEXT
2850 | (int) ATTR_FLAG_ARRAY_NEXT))
2852 *no_add_attrs = true;
2853 return tree_cons (name, args, NULL_TREE);
2857 warning (OPT_Wattributes, "%qs attribute ignored",
2858 IDENTIFIER_POINTER (name));
2866 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2867 /* Handle the "notshared" attribute. This attribute is another way of
2868 requesting hidden visibility. ARM's compiler supports
2869 "__declspec(notshared)"; we support the same thing via an
2873 arm_handle_notshared_attribute (tree *node,
2874 tree name ATTRIBUTE_UNUSED,
2875 tree args ATTRIBUTE_UNUSED,
2876 int flags ATTRIBUTE_UNUSED,
2879 tree decl = TYPE_NAME (*node);
2883 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2884 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2885 *no_add_attrs = false;
2891 /* Return 0 if the attributes for two types are incompatible, 1 if they
2892 are compatible, and 2 if they are nearly compatible (which causes a
2893 warning to be generated). */
2895 arm_comp_type_attributes (tree type1, tree type2)
2899 /* Check for mismatch of non-default calling convention. */
2900 if (TREE_CODE (type1) != FUNCTION_TYPE)
2903 /* Check for mismatched call attributes. */
2904 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2905 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2906 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2907 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2909 /* Only bother to check if an attribute is defined. */
2910 if (l1 | l2 | s1 | s2)
2912 /* If one type has an attribute, the other must have the same attribute. */
2913 if ((l1 != l2) || (s1 != s2))
2916 /* Disallow mixed attributes. */
2917 if ((l1 & s2) || (l2 & s1))
2921 /* Check for mismatched ISR attribute. */
2922 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2924 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2925 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2927 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2934 /* Encode long_call or short_call attribute by prefixing
2935 symbol name in DECL with a special character FLAG. */
2937 arm_encode_call_attribute (tree decl, int flag)
2939 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2940 int len = strlen (str);
2943 /* Do not allow weak functions to be treated as short call. */
2944 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2947 newstr = alloca (len + 2);
2949 strcpy (newstr + 1, str);
2951 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2952 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2955 /* Assigns default attributes to newly defined type. This is used to
2956 set short_call/long_call attributes for function types of
2957 functions defined inside corresponding #pragma scopes. */
2959 arm_set_default_type_attributes (tree type)
2961 /* Add __attribute__ ((long_call)) to all functions, when
2962 inside #pragma long_calls or __attribute__ ((short_call)),
2963 when inside #pragma no_long_calls. */
2964 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2966 tree type_attr_list, attr_name;
2967 type_attr_list = TYPE_ATTRIBUTES (type);
2969 if (arm_pragma_long_calls == LONG)
2970 attr_name = get_identifier ("long_call");
2971 else if (arm_pragma_long_calls == SHORT)
2972 attr_name = get_identifier ("short_call");
2976 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2977 TYPE_ATTRIBUTES (type) = type_attr_list;
2981 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2982 defined within the current compilation unit. If this cannot be
2983 determined, then 0 is returned. */
2985 current_file_function_operand (rtx sym_ref)
2987 /* This is a bit of a fib. A function will have a short call flag
2988 applied to its name if it has the short call attribute, or it has
2989 already been defined within the current compilation unit. */
2990 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2993 /* The current function is always defined within the current compilation
2994 unit. If it s a weak definition however, then this may not be the real
2995 definition of the function, and so we have to say no. */
2996 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2997 && !DECL_WEAK (current_function_decl))
3000 /* We cannot make the determination - default to returning 0. */
3004 /* Return nonzero if a 32 bit "long_call" should be generated for
3005 this call. We generate a long_call if the function:
3007 a. has an __attribute__((long call))
3008 or b. is within the scope of a #pragma long_calls
3009 or c. the -mlong-calls command line switch has been specified
3011 1. -ffunction-sections is in effect
3012 or 2. the current function has __attribute__ ((section))
3013 or 3. the target function has __attribute__ ((section))
3015 However we do not generate a long call if the function:
3017 d. has an __attribute__ ((short_call))
3018 or e. is inside the scope of a #pragma no_long_calls
3019 or f. is defined within the current compilation unit.
3021 This function will be called by C fragments contained in the machine
3022 description file. SYM_REF and CALL_COOKIE correspond to the matched
3023 rtl operands. CALL_SYMBOL is used to distinguish between
3024 two different callers of the function. It is set to 1 in the
3025 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3026 and "call_value" patterns. This is because of the difference in the
3027 SYM_REFs passed by these patterns. */
3029 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3033 if (GET_CODE (sym_ref) != MEM)
3036 sym_ref = XEXP (sym_ref, 0);
3039 if (GET_CODE (sym_ref) != SYMBOL_REF)
3042 if (call_cookie & CALL_SHORT)
3045 if (TARGET_LONG_CALLS)
3047 if (flag_function_sections
3048 || DECL_SECTION_NAME (current_function_decl))
3049 /* c.3 is handled by the definition of the
3050 ARM_DECLARE_FUNCTION_SIZE macro. */
3054 if (current_file_function_operand (sym_ref))
3057 return (call_cookie & CALL_LONG)
3058 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3059 || TARGET_LONG_CALLS;
3062 /* Return nonzero if it is ok to make a tail-call to DECL. */
3064 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3066 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3068 if (cfun->machine->sibcall_blocked)
3071 /* Never tailcall something for which we have no decl, or if we
3072 are in Thumb mode. */
3073 if (decl == NULL || TARGET_THUMB)
3076 /* Get the calling method. */
3077 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3078 call_type = CALL_SHORT;
3079 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3080 call_type = CALL_LONG;
3082 /* Cannot tail-call to long calls, since these are out of range of
3083 a branch instruction. However, if not compiling PIC, we know
3084 we can reach the symbol if it is in this compilation unit. */
3085 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3088 /* If we are interworking and the function is not declared static
3089 then we can't tail-call it unless we know that it exists in this
3090 compilation unit (since it might be a Thumb routine). */
3091 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3094 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3095 if (IS_INTERRUPT (arm_current_func_type ()))
3098 /* Everything else is ok. */
3103 /* Addressing mode support functions. */
3105 /* Return nonzero if X is a legitimate immediate operand when compiling
3108 legitimate_pic_operand_p (rtx x)
3112 && (GET_CODE (x) == SYMBOL_REF
3113 || (GET_CODE (x) == CONST
3114 && GET_CODE (XEXP (x, 0)) == PLUS
3115 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
3122 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3124 if (GET_CODE (orig) == SYMBOL_REF
3125 || GET_CODE (orig) == LABEL_REF)
3127 #ifndef AOF_ASSEMBLER
3128 rtx pic_ref, address;
3135 gcc_assert (!no_new_pseudos);
3136 reg = gen_reg_rtx (Pmode);
3141 #ifdef AOF_ASSEMBLER
3142 /* The AOF assembler can generate relocations for these directly, and
3143 understands that the PIC register has to be added into the offset. */
3144 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3147 address = gen_reg_rtx (Pmode);
3152 emit_insn (gen_pic_load_addr_arm (address, orig));
3154 emit_insn (gen_pic_load_addr_thumb (address, orig));
3156 if ((GET_CODE (orig) == LABEL_REF
3157 || (GET_CODE (orig) == SYMBOL_REF &&
3158 SYMBOL_REF_LOCAL_P (orig)))
3160 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
3163 pic_ref = gen_const_mem (Pmode,
3164 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3168 insn = emit_move_insn (reg, pic_ref);
3170 current_function_uses_pic_offset_table = 1;
3171 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3173 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3177 else if (GET_CODE (orig) == CONST)
3181 if (GET_CODE (XEXP (orig, 0)) == PLUS
3182 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3187 gcc_assert (!no_new_pseudos);
3188 reg = gen_reg_rtx (Pmode);
3191 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3193 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3194 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3195 base == reg ? 0 : reg);
3197 if (GET_CODE (offset) == CONST_INT)
3199 /* The base register doesn't really matter, we only want to
3200 test the index for the appropriate mode. */
3201 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3203 gcc_assert (!no_new_pseudos);
3204 offset = force_reg (Pmode, offset);
3207 if (GET_CODE (offset) == CONST_INT)
3208 return plus_constant (base, INTVAL (offset));
3211 if (GET_MODE_SIZE (mode) > 4
3212 && (GET_MODE_CLASS (mode) == MODE_INT
3213 || TARGET_SOFT_FLOAT))
3215 emit_insn (gen_addsi3 (reg, base, offset));
3219 return gen_rtx_PLUS (Pmode, base, offset);
3226 /* Find a spare low register to use during the prolog of a function. */
3229 thumb_find_work_register (unsigned long pushed_regs_mask)
3233 /* Check the argument registers first as these are call-used. The
3234 register allocation order means that sometimes r3 might be used
3235 but earlier argument registers might not, so check them all. */
3236 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3237 if (!regs_ever_live[reg])
3240 /* Before going on to check the call-saved registers we can try a couple
3241 more ways of deducing that r3 is available. The first is when we are
3242 pushing anonymous arguments onto the stack and we have less than 4
3243 registers worth of fixed arguments(*). In this case r3 will be part of
3244 the variable argument list and so we can be sure that it will be
3245 pushed right at the start of the function. Hence it will be available
3246 for the rest of the prologue.
3247 (*): ie current_function_pretend_args_size is greater than 0. */
3248 if (cfun->machine->uses_anonymous_args
3249 && current_function_pretend_args_size > 0)
3250 return LAST_ARG_REGNUM;
3252 /* The other case is when we have fixed arguments but less than 4 registers
3253 worth. In this case r3 might be used in the body of the function, but
3254 it is not being used to convey an argument into the function. In theory
3255 we could just check current_function_args_size to see how many bytes are
3256 being passed in argument registers, but it seems that it is unreliable.
3257 Sometimes it will have the value 0 when in fact arguments are being
3258 passed. (See testcase execute/20021111-1.c for an example). So we also
3259 check the args_info.nregs field as well. The problem with this field is
3260 that it makes no allowances for arguments that are passed to the
3261 function but which are not used. Hence we could miss an opportunity
3262 when a function has an unused argument in r3. But it is better to be
3263 safe than to be sorry. */
3264 if (! cfun->machine->uses_anonymous_args
3265 && current_function_args_size >= 0
3266 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3267 && cfun->args_info.nregs < 4)
3268 return LAST_ARG_REGNUM;
3270 /* Otherwise look for a call-saved register that is going to be pushed. */
3271 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3272 if (pushed_regs_mask & (1 << reg))
3275 /* Something went wrong - thumb_compute_save_reg_mask()
3276 should have arranged for a suitable register to be pushed. */
3281 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3285 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3287 #ifndef AOF_ASSEMBLER
3288 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3289 rtx global_offset_table;
3291 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3294 gcc_assert (flag_pic);
3296 l1 = gen_label_rtx ();
3298 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3299 /* On the ARM the PC register contains 'dot + 8' at the time of the
3300 addition, on the Thumb it is 'dot + 4'. */
3301 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3303 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3304 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3306 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3308 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3312 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3313 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3317 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3319 /* We will have pushed the pic register, so we should always be
3320 able to find a work register. */
3321 pic_tmp = gen_rtx_REG (SImode,
3322 thumb_find_work_register (saved_regs));
3323 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3324 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3327 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3328 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3331 /* Need to emit this whether or not we obey regdecls,
3332 since setjmp/longjmp can cause life info to screw up. */
3333 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3334 #endif /* AOF_ASSEMBLER */
3338 /* Return nonzero if X is valid as an ARM state addressing register. */
3340 arm_address_register_rtx_p (rtx x, int strict_p)
3344 if (GET_CODE (x) != REG)
3350 return ARM_REGNO_OK_FOR_BASE_P (regno);
3352 return (regno <= LAST_ARM_REGNUM
3353 || regno >= FIRST_PSEUDO_REGISTER
3354 || regno == FRAME_POINTER_REGNUM
3355 || regno == ARG_POINTER_REGNUM);
3358 /* Return nonzero if X is a valid ARM state address operand. */
3360 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3364 enum rtx_code code = GET_CODE (x);
3366 if (arm_address_register_rtx_p (x, strict_p))
3369 use_ldrd = (TARGET_LDRD
3371 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3373 if (code == POST_INC || code == PRE_DEC
3374 || ((code == PRE_INC || code == POST_DEC)
3375 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3376 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3378 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3379 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3380 && GET_CODE (XEXP (x, 1)) == PLUS
3381 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3383 rtx addend = XEXP (XEXP (x, 1), 1);
3385 /* Don't allow ldrd post increment by register because it's hard
3386 to fixup invalid register choices. */
3388 && GET_CODE (x) == POST_MODIFY
3389 && GET_CODE (addend) == REG)
3392 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3393 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3396 /* After reload constants split into minipools will have addresses
3397 from a LABEL_REF. */
3398 else if (reload_completed
3399 && (code == LABEL_REF
3401 && GET_CODE (XEXP (x, 0)) == PLUS
3402 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3403 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3406 else if (mode == TImode)
3409 else if (code == PLUS)
3411 rtx xop0 = XEXP (x, 0);
3412 rtx xop1 = XEXP (x, 1);
3414 return ((arm_address_register_rtx_p (xop0, strict_p)
3415 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3416 || (arm_address_register_rtx_p (xop1, strict_p)
3417 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3421 /* Reload currently can't handle MINUS, so disable this for now */
3422 else if (GET_CODE (x) == MINUS)
3424 rtx xop0 = XEXP (x, 0);
3425 rtx xop1 = XEXP (x, 1);
3427 return (arm_address_register_rtx_p (xop0, strict_p)
3428 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3432 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3433 && code == SYMBOL_REF
3434 && CONSTANT_POOL_ADDRESS_P (x)
3436 && symbol_mentioned_p (get_pool_constant (x))))
3442 /* Return nonzero if INDEX is valid for an address index operand in
3445 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3448 HOST_WIDE_INT range;
3449 enum rtx_code code = GET_CODE (index);
3451 /* Standard coprocessor addressing modes. */
3452 if (TARGET_HARD_FLOAT
3453 && (TARGET_FPA || TARGET_MAVERICK)
3454 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3455 || (TARGET_MAVERICK && mode == DImode)))
3456 return (code == CONST_INT && INTVAL (index) < 1024
3457 && INTVAL (index) > -1024
3458 && (INTVAL (index) & 3) == 0);
3460 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3461 return (code == CONST_INT
3462 && INTVAL (index) < 1024
3463 && INTVAL (index) > -1024
3464 && (INTVAL (index) & 3) == 0);
3466 if (arm_address_register_rtx_p (index, strict_p)
3467 && (GET_MODE_SIZE (mode) <= 4))
3470 if (mode == DImode || mode == DFmode)
3472 if (code == CONST_INT)
3474 HOST_WIDE_INT val = INTVAL (index);
3477 return val > -256 && val < 256;
3479 return val > -4096 && val < 4092;
3482 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3485 if (GET_MODE_SIZE (mode) <= 4
3488 || (mode == QImode && outer == SIGN_EXTEND))))
3492 rtx xiop0 = XEXP (index, 0);
3493 rtx xiop1 = XEXP (index, 1);
3495 return ((arm_address_register_rtx_p (xiop0, strict_p)
3496 && power_of_two_operand (xiop1, SImode))
3497 || (arm_address_register_rtx_p (xiop1, strict_p)
3498 && power_of_two_operand (xiop0, SImode)));
3500 else if (code == LSHIFTRT || code == ASHIFTRT
3501 || code == ASHIFT || code == ROTATERT)
3503 rtx op = XEXP (index, 1);
3505 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3506 && GET_CODE (op) == CONST_INT
3508 && INTVAL (op) <= 31);
3512 /* For ARM v4 we may be doing a sign-extend operation during the
3516 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3522 range = (mode == HImode) ? 4095 : 4096;
3524 return (code == CONST_INT
3525 && INTVAL (index) < range
3526 && INTVAL (index) > -range);
3529 /* Return nonzero if X is valid as a Thumb state base register. */
3531 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3535 if (GET_CODE (x) != REG)
3541 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3543 return (regno <= LAST_LO_REGNUM
3544 || regno > LAST_VIRTUAL_REGISTER
3545 || regno == FRAME_POINTER_REGNUM
3546 || (GET_MODE_SIZE (mode) >= 4
3547 && (regno == STACK_POINTER_REGNUM
3548 || regno >= FIRST_PSEUDO_REGISTER
3549 || x == hard_frame_pointer_rtx
3550 || x == arg_pointer_rtx)));
3553 /* Return nonzero if x is a legitimate index register. This is the case
3554 for any base register that can access a QImode object. */
3556 thumb_index_register_rtx_p (rtx x, int strict_p)
3558 return thumb_base_register_rtx_p (x, QImode, strict_p);
3561 /* Return nonzero if x is a legitimate Thumb-state address.
3563 The AP may be eliminated to either the SP or the FP, so we use the
3564 least common denominator, e.g. SImode, and offsets from 0 to 64.
3566 ??? Verify whether the above is the right approach.
3568 ??? Also, the FP may be eliminated to the SP, so perhaps that
3569 needs special handling also.
3571 ??? Look at how the mips16 port solves this problem. It probably uses
3572 better ways to solve some of these problems.
3574 Although it is not incorrect, we don't accept QImode and HImode
3575 addresses based on the frame pointer or arg pointer until the
3576 reload pass starts. This is so that eliminating such addresses
3577 into stack based ones won't produce impossible code. */
3579 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3581 /* ??? Not clear if this is right. Experiment. */
3582 if (GET_MODE_SIZE (mode) < 4
3583 && !(reload_in_progress || reload_completed)
3584 && (reg_mentioned_p (frame_pointer_rtx, x)
3585 || reg_mentioned_p (arg_pointer_rtx, x)
3586 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3587 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3588 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3589 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3592 /* Accept any base register. SP only in SImode or larger. */
3593 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3596 /* This is PC relative data before arm_reorg runs. */
3597 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3598 && GET_CODE (x) == SYMBOL_REF
3599 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3602 /* This is PC relative data after arm_reorg runs. */
3603 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3604 && (GET_CODE (x) == LABEL_REF
3605 || (GET_CODE (x) == CONST
3606 && GET_CODE (XEXP (x, 0)) == PLUS
3607 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3608 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3611 /* Post-inc indexing only supported for SImode and larger. */
3612 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3613 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3616 else if (GET_CODE (x) == PLUS)
3618 /* REG+REG address can be any two index registers. */
3619 /* We disallow FRAME+REG addressing since we know that FRAME
3620 will be replaced with STACK, and SP relative addressing only
3621 permits SP+OFFSET. */
3622 if (GET_MODE_SIZE (mode) <= 4
3623 && XEXP (x, 0) != frame_pointer_rtx
3624 && XEXP (x, 1) != frame_pointer_rtx
3625 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3626 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3629 /* REG+const has 5-7 bit offset for non-SP registers. */
3630 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3631 || XEXP (x, 0) == arg_pointer_rtx)
3632 && GET_CODE (XEXP (x, 1)) == CONST_INT
3633 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3636 /* REG+const has 10 bit offset for SP, but only SImode and
3637 larger is supported. */
3638 /* ??? Should probably check for DI/DFmode overflow here
3639 just like GO_IF_LEGITIMATE_OFFSET does. */
3640 else if (GET_CODE (XEXP (x, 0)) == REG
3641 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3642 && GET_MODE_SIZE (mode) >= 4
3643 && GET_CODE (XEXP (x, 1)) == CONST_INT
3644 && INTVAL (XEXP (x, 1)) >= 0
3645 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3646 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3649 else if (GET_CODE (XEXP (x, 0)) == REG
3650 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3651 && GET_MODE_SIZE (mode) >= 4
3652 && GET_CODE (XEXP (x, 1)) == CONST_INT
3653 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3657 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3658 && GET_MODE_SIZE (mode) == 4
3659 && GET_CODE (x) == SYMBOL_REF
3660 && CONSTANT_POOL_ADDRESS_P (x)
3662 && symbol_mentioned_p (get_pool_constant (x))))
3668 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3669 instruction of mode MODE. */
3671 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3673 switch (GET_MODE_SIZE (mode))
3676 return val >= 0 && val < 32;
3679 return val >= 0 && val < 64 && (val & 1) == 0;
3683 && (val + GET_MODE_SIZE (mode)) <= 128
3688 /* Try machine-dependent ways of modifying an illegitimate address
3689 to be legitimate. If we find one, return the new, valid address. */
3691 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3693 if (GET_CODE (x) == PLUS)
3695 rtx xop0 = XEXP (x, 0);
3696 rtx xop1 = XEXP (x, 1);
3698 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3699 xop0 = force_reg (SImode, xop0);
3701 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3702 xop1 = force_reg (SImode, xop1);
3704 if (ARM_BASE_REGISTER_RTX_P (xop0)
3705 && GET_CODE (xop1) == CONST_INT)
3707 HOST_WIDE_INT n, low_n;
3711 /* VFP addressing modes actually allow greater offsets, but for
3712 now we just stick with the lowest common denominator. */
3714 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3726 low_n = ((mode) == TImode ? 0
3727 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3731 base_reg = gen_reg_rtx (SImode);
3732 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3733 GEN_INT (n)), NULL_RTX);
3734 emit_move_insn (base_reg, val);
3735 x = (low_n == 0 ? base_reg
3736 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3738 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3739 x = gen_rtx_PLUS (SImode, xop0, xop1);
3742 /* XXX We don't allow MINUS any more -- see comment in
3743 arm_legitimate_address_p (). */
3744 else if (GET_CODE (x) == MINUS)
3746 rtx xop0 = XEXP (x, 0);
3747 rtx xop1 = XEXP (x, 1);
3749 if (CONSTANT_P (xop0))
3750 xop0 = force_reg (SImode, xop0);
3752 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3753 xop1 = force_reg (SImode, xop1);
3755 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3756 x = gen_rtx_MINUS (SImode, xop0, xop1);
3759 /* Make sure to take full advantage of the pre-indexed addressing mode
3760 with absolute addresses which often allows for the base register to
3761 be factorized for multiple adjacent memory references, and it might
3762 even allows for the mini pool to be avoided entirely. */
3763 else if (GET_CODE (x) == CONST_INT && optimize > 0)
3766 HOST_WIDE_INT mask, base, index;
3769 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
3770 use a 8 bit index. So let's use a 12 bit index for SImode only and
3771 hope that arm_gen_constant will enable ldrb to use more bits. */
3772 bits = (mode == SImode) ? 12 : 8;
3773 mask = (1 << bits) - 1;
3774 base = INTVAL (x) & ~mask;
3775 index = INTVAL (x) & mask;
3776 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
3778 /* It'll most probably be more efficient to generate the base
3779 with more bits set and use a negative index instead. */
3783 base_reg = force_reg (SImode, GEN_INT (base));
3784 x = gen_rtx_PLUS (SImode, base_reg, GEN_INT (index));
3789 /* We need to find and carefully transform any SYMBOL and LABEL
3790 references; so go back to the original address expression. */
3791 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3793 if (new_x != orig_x)
3801 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3802 to be legitimate. If we find one, return the new, valid address. */
3804 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3806 if (GET_CODE (x) == PLUS
3807 && GET_CODE (XEXP (x, 1)) == CONST_INT
3808 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3809 || INTVAL (XEXP (x, 1)) < 0))
3811 rtx xop0 = XEXP (x, 0);
3812 rtx xop1 = XEXP (x, 1);
3813 HOST_WIDE_INT offset = INTVAL (xop1);
3815 /* Try and fold the offset into a biasing of the base register and
3816 then offsetting that. Don't do this when optimizing for space
3817 since it can cause too many CSEs. */
3818 if (optimize_size && offset >= 0
3819 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3821 HOST_WIDE_INT delta;
3824 delta = offset - (256 - GET_MODE_SIZE (mode));
3825 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3826 delta = 31 * GET_MODE_SIZE (mode);
3828 delta = offset & (~31 * GET_MODE_SIZE (mode));
3830 xop0 = force_operand (plus_constant (xop0, offset - delta),
3832 x = plus_constant (xop0, delta);
3834 else if (offset < 0 && offset > -256)
3835 /* Small negative offsets are best done with a subtract before the
3836 dereference, forcing these into a register normally takes two
3838 x = force_operand (x, NULL_RTX);
3841 /* For the remaining cases, force the constant into a register. */
3842 xop1 = force_reg (SImode, xop1);
3843 x = gen_rtx_PLUS (SImode, xop0, xop1);
3846 else if (GET_CODE (x) == PLUS
3847 && s_register_operand (XEXP (x, 1), SImode)
3848 && !s_register_operand (XEXP (x, 0), SImode))
3850 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3852 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3857 /* We need to find and carefully transform any SYMBOL and LABEL
3858 references; so go back to the original address expression. */
3859 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3861 if (new_x != orig_x)
3869 thumb_legitimize_reload_address (rtx *x_p,
3870 enum machine_mode mode,
3871 int opnum, int type,
3872 int ind_levels ATTRIBUTE_UNUSED)
3876 if (GET_CODE (x) == PLUS
3877 && GET_MODE_SIZE (mode) < 4
3878 && REG_P (XEXP (x, 0))
3879 && XEXP (x, 0) == stack_pointer_rtx
3880 && GET_CODE (XEXP (x, 1)) == CONST_INT
3881 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3886 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
3887 Pmode, VOIDmode, 0, 0, opnum, type);
3891 /* If both registers are hi-regs, then it's better to reload the
3892 entire expression rather than each register individually. That
3893 only requires one reload register rather than two. */
3894 if (GET_CODE (x) == PLUS
3895 && REG_P (XEXP (x, 0))
3896 && REG_P (XEXP (x, 1))
3897 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
3898 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
3903 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
3904 Pmode, VOIDmode, 0, 0, opnum, type);
3911 #define REG_OR_SUBREG_REG(X) \
3912 (GET_CODE (X) == REG \
3913 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3915 #define REG_OR_SUBREG_RTX(X) \
3916 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3918 #ifndef COSTS_N_INSNS
3919 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3922 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3924 enum machine_mode mode = GET_MODE (x);
3937 return COSTS_N_INSNS (1);
3940 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3943 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3950 return COSTS_N_INSNS (2) + cycles;
3952 return COSTS_N_INSNS (1) + 16;
3955 return (COSTS_N_INSNS (1)
3956 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3957 + GET_CODE (SET_DEST (x)) == MEM));
3962 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3964 if (thumb_shiftable_const (INTVAL (x)))
3965 return COSTS_N_INSNS (2);
3966 return COSTS_N_INSNS (3);
3968 else if ((outer == PLUS || outer == COMPARE)
3969 && INTVAL (x) < 256 && INTVAL (x) > -256)
3971 else if (outer == AND
3972 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3973 return COSTS_N_INSNS (1);
3974 else if (outer == ASHIFT || outer == ASHIFTRT
3975 || outer == LSHIFTRT)
3977 return COSTS_N_INSNS (2);
3983 return COSTS_N_INSNS (3);
4001 /* XXX another guess. */
4002 /* Memory costs quite a lot for the first word, but subsequent words
4003 load at the equivalent of a single insn each. */
4004 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4005 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4010 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4015 /* XXX still guessing. */
4016 switch (GET_MODE (XEXP (x, 0)))
4019 return (1 + (mode == DImode ? 4 : 0)
4020 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4023 return (4 + (mode == DImode ? 4 : 0)
4024 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4027 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4039 /* Worker routine for arm_rtx_costs. */
4041 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4043 enum machine_mode mode = GET_MODE (x);
4044 enum rtx_code subcode;
4050 /* Memory costs quite a lot for the first word, but subsequent words
4051 load at the equivalent of a single insn each. */
4052 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4053 + (GET_CODE (x) == SYMBOL_REF
4054 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4060 return optimize_size ? COSTS_N_INSNS (2) : 100;
4063 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4070 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4072 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4073 + ((GET_CODE (XEXP (x, 0)) == REG
4074 || (GET_CODE (XEXP (x, 0)) == SUBREG
4075 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4077 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4078 || (GET_CODE (XEXP (x, 0)) == SUBREG
4079 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4081 + ((GET_CODE (XEXP (x, 1)) == REG
4082 || (GET_CODE (XEXP (x, 1)) == SUBREG
4083 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4084 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4089 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4090 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4091 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4092 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4095 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4096 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4097 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4098 && arm_const_double_rtx (XEXP (x, 1))))
4100 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4101 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4102 && arm_const_double_rtx (XEXP (x, 0))))
4105 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4106 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4107 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4108 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4109 || subcode == ASHIFTRT || subcode == LSHIFTRT
4110 || subcode == ROTATE || subcode == ROTATERT
4112 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4113 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4114 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4115 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4116 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4117 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4118 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4123 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4124 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4125 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4126 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4127 && arm_const_double_rtx (XEXP (x, 1))))
4131 case AND: case XOR: case IOR:
4134 /* Normally the frame registers will be spilt into reg+const during
4135 reload, so it is a bad idea to combine them with other instructions,
4136 since then they might not be moved outside of loops. As a compromise
4137 we allow integration with ops that have a constant as their second
4139 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4140 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4141 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4142 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4143 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4147 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4148 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4149 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4150 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4153 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4154 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4155 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4156 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4157 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4160 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4161 return (1 + extra_cost
4162 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4163 || subcode == LSHIFTRT || subcode == ASHIFTRT
4164 || subcode == ROTATE || subcode == ROTATERT
4166 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4167 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4168 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4169 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4170 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4171 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4177 /* This should have been handled by the CPU specific routines. */
4181 if (arm_arch3m && mode == SImode
4182 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4183 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4184 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4185 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4186 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4187 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4192 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4193 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4197 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4199 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4202 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4210 return 4 + (mode == DImode ? 4 : 0);
4213 if (GET_MODE (XEXP (x, 0)) == QImode)
4214 return (4 + (mode == DImode ? 4 : 0)
4215 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4218 switch (GET_MODE (XEXP (x, 0)))
4221 return (1 + (mode == DImode ? 4 : 0)
4222 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4225 return (4 + (mode == DImode ? 4 : 0)
4226 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4229 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4244 if (const_ok_for_arm (INTVAL (x)))
4245 return outer == SET ? 2 : -1;
4246 else if (outer == AND
4247 && const_ok_for_arm (~INTVAL (x)))
4249 else if ((outer == COMPARE
4250 || outer == PLUS || outer == MINUS)
4251 && const_ok_for_arm (-INTVAL (x)))
4262 if (arm_const_double_rtx (x))
4263 return outer == SET ? 2 : -1;
4264 else if ((outer == COMPARE || outer == PLUS)
4265 && neg_const_double_rtx_ok_for_fpa (x))
4274 /* RTX costs when optimizing for size. */
4276 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4278 enum machine_mode mode = GET_MODE (x);
4282 /* XXX TBD. For now, use the standard costs. */
4283 *total = thumb_rtx_costs (x, code, outer_code);
4290 /* A memory access costs 1 insn if the mode is small, or the address is
4291 a single register, otherwise it costs one insn per word. */
4292 if (REG_P (XEXP (x, 0)))
4293 *total = COSTS_N_INSNS (1);
4295 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4302 /* Needs a libcall, so it costs about this. */
4303 *total = COSTS_N_INSNS (2);
4307 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4309 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4317 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4319 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4322 else if (mode == SImode)
4324 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4325 /* Slightly disparage register shifts, but not by much. */
4326 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4327 *total += 1 + rtx_cost (XEXP (x, 1), code);
4331 /* Needs a libcall. */
4332 *total = COSTS_N_INSNS (2);
4336 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4338 *total = COSTS_N_INSNS (1);
4344 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4345 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4347 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4348 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4349 || subcode1 == ROTATE || subcode1 == ROTATERT
4350 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4351 || subcode1 == ASHIFTRT)
4353 /* It's just the cost of the two operands. */
4358 *total = COSTS_N_INSNS (1);
4362 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4366 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4368 *total = COSTS_N_INSNS (1);
4373 case AND: case XOR: case IOR:
4376 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4378 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4379 || subcode == LSHIFTRT || subcode == ASHIFTRT
4380 || (code == AND && subcode == NOT))
4382 /* It's just the cost of the two operands. */
4388 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4392 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4396 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4397 *total = COSTS_N_INSNS (1);
4400 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4409 if (cc_register (XEXP (x, 0), VOIDmode))
4412 *total = COSTS_N_INSNS (1);
4416 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4417 *total = COSTS_N_INSNS (1);
4419 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4424 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4426 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4427 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4430 *total += COSTS_N_INSNS (1);
4435 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4437 switch (GET_MODE (XEXP (x, 0)))
4440 *total += COSTS_N_INSNS (1);
4444 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4450 *total += COSTS_N_INSNS (2);
4455 *total += COSTS_N_INSNS (1);
4460 if (const_ok_for_arm (INTVAL (x)))
4461 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4462 else if (const_ok_for_arm (~INTVAL (x)))
4463 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4464 else if (const_ok_for_arm (-INTVAL (x)))
4466 if (outer_code == COMPARE || outer_code == PLUS
4467 || outer_code == MINUS)
4470 *total = COSTS_N_INSNS (1);
4473 *total = COSTS_N_INSNS (2);
4479 *total = COSTS_N_INSNS (2);
4483 *total = COSTS_N_INSNS (4);
4487 if (mode != VOIDmode)
4488 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4490 *total = COSTS_N_INSNS (4); /* How knows? */
4495 /* RTX costs for cores with a slow MUL implementation. */
4498 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4500 enum machine_mode mode = GET_MODE (x);
4504 *total = thumb_rtx_costs (x, code, outer_code);
4511 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4518 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4520 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4521 & (unsigned HOST_WIDE_INT) 0xffffffff);
4522 int cost, const_ok = const_ok_for_arm (i);
4523 int j, booth_unit_size;
4525 /* Tune as appropriate. */
4526 cost = const_ok ? 4 : 8;
4527 booth_unit_size = 2;
4528 for (j = 0; i && j < 32; j += booth_unit_size)
4530 i >>= booth_unit_size;
4538 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4539 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4543 *total = arm_rtx_costs_1 (x, code, outer_code);
4549 /* RTX cost for cores with a fast multiply unit (M variants). */
4552 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4554 enum machine_mode mode = GET_MODE (x);
4558 *total = thumb_rtx_costs (x, code, outer_code);
4565 /* There is no point basing this on the tuning, since it is always the
4566 fast variant if it exists at all. */
4568 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4569 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4570 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4577 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4584 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4586 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4587 & (unsigned HOST_WIDE_INT) 0xffffffff);
4588 int cost, const_ok = const_ok_for_arm (i);
4589 int j, booth_unit_size;
4591 /* Tune as appropriate. */
4592 cost = const_ok ? 4 : 8;
4593 booth_unit_size = 8;
4594 for (j = 0; i && j < 32; j += booth_unit_size)
4596 i >>= booth_unit_size;
4604 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4605 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4609 *total = arm_rtx_costs_1 (x, code, outer_code);
4615 /* RTX cost for XScale CPUs. */
4618 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4620 enum machine_mode mode = GET_MODE (x);
4624 *total = thumb_rtx_costs (x, code, outer_code);
4631 /* There is no point basing this on the tuning, since it is always the
4632 fast variant if it exists at all. */
4634 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4635 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4636 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4643 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4650 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4652 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4653 & (unsigned HOST_WIDE_INT) 0xffffffff);
4654 int cost, const_ok = const_ok_for_arm (i);
4655 unsigned HOST_WIDE_INT masked_const;
4657 /* The cost will be related to two insns.
4658 First a load of the constant (MOV or LDR), then a multiply. */
4661 cost += 1; /* LDR is probably more expensive because
4662 of longer result latency. */
4663 masked_const = i & 0xffff8000;
4664 if (masked_const != 0 && masked_const != 0xffff8000)
4666 masked_const = i & 0xf8000000;
4667 if (masked_const == 0 || masked_const == 0xf8000000)
4676 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4677 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4681 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4682 will stall until the multiplication is complete. */
4683 if (GET_CODE (XEXP (x, 0)) == MULT)
4684 *total = 4 + rtx_cost (XEXP (x, 0), code);
4686 *total = arm_rtx_costs_1 (x, code, outer_code);
4690 *total = arm_rtx_costs_1 (x, code, outer_code);
4696 /* RTX costs for 9e (and later) cores. */
4699 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4701 enum machine_mode mode = GET_MODE (x);
4710 *total = COSTS_N_INSNS (3);
4714 *total = thumb_rtx_costs (x, code, outer_code);
4722 /* There is no point basing this on the tuning, since it is always the
4723 fast variant if it exists at all. */
4725 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4726 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4727 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4734 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4751 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4752 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4756 *total = arm_rtx_costs_1 (x, code, outer_code);
4760 /* All address computations that can be done are free, but rtx cost returns
4761 the same for practically all of them. So we weight the different types
4762 of address here in the order (most pref first):
4763 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4765 arm_arm_address_cost (rtx x)
4767 enum rtx_code c = GET_CODE (x);
4769 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4771 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4774 if (c == PLUS || c == MINUS)
4776 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4779 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4789 arm_thumb_address_cost (rtx x)
4791 enum rtx_code c = GET_CODE (x);
4796 && GET_CODE (XEXP (x, 0)) == REG
4797 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4804 arm_address_cost (rtx x)
4806 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4810 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4814 /* Some true dependencies can have a higher cost depending
4815 on precisely how certain input operands are used. */
4817 && REG_NOTE_KIND (link) == 0
4818 && recog_memoized (insn) >= 0
4819 && recog_memoized (dep) >= 0)
4821 int shift_opnum = get_attr_shift (insn);
4822 enum attr_type attr_type = get_attr_type (dep);
4824 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4825 operand for INSN. If we have a shifted input operand and the
4826 instruction we depend on is another ALU instruction, then we may
4827 have to account for an additional stall. */
4828 if (shift_opnum != 0
4829 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4831 rtx shifted_operand;
4834 /* Get the shifted operand. */
4835 extract_insn (insn);
4836 shifted_operand = recog_data.operand[shift_opnum];
4838 /* Iterate over all the operands in DEP. If we write an operand
4839 that overlaps with SHIFTED_OPERAND, then we have increase the
4840 cost of this dependency. */
4842 preprocess_constraints ();
4843 for (opno = 0; opno < recog_data.n_operands; opno++)
4845 /* We can ignore strict inputs. */
4846 if (recog_data.operand_type[opno] == OP_IN)
4849 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4856 /* XXX This is not strictly true for the FPA. */
4857 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4858 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4861 /* Call insns don't incur a stall, even if they follow a load. */
4862 if (REG_NOTE_KIND (link) == 0
4863 && GET_CODE (insn) == CALL_INSN)
4866 if ((i_pat = single_set (insn)) != NULL
4867 && GET_CODE (SET_SRC (i_pat)) == MEM
4868 && (d_pat = single_set (dep)) != NULL
4869 && GET_CODE (SET_DEST (d_pat)) == MEM)
4871 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4872 /* This is a load after a store, there is no conflict if the load reads
4873 from a cached area. Assume that loads from the stack, and from the
4874 constant pool are cached, and that others will miss. This is a
4877 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4878 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4879 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4880 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4887 static int fp_consts_inited = 0;
4889 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4890 static const char * const strings_fp[8] =
4893 "4", "5", "0.5", "10"
4896 static REAL_VALUE_TYPE values_fp[8];
4899 init_fp_table (void)
4905 fp_consts_inited = 1;
4907 fp_consts_inited = 8;
4909 for (i = 0; i < fp_consts_inited; i++)
4911 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4916 /* Return TRUE if rtx X is a valid immediate FP constant. */
4918 arm_const_double_rtx (rtx x)
4923 if (!fp_consts_inited)
4926 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4927 if (REAL_VALUE_MINUS_ZERO (r))
4930 for (i = 0; i < fp_consts_inited; i++)
4931 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4937 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4939 neg_const_double_rtx_ok_for_fpa (rtx x)
4944 if (!fp_consts_inited)
4947 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4948 r = REAL_VALUE_NEGATE (r);
4949 if (REAL_VALUE_MINUS_ZERO (r))
4952 for (i = 0; i < 8; i++)
4953 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4959 /* Predicates for `match_operand' and `match_operator'. */
4961 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4963 cirrus_memory_offset (rtx op)
4965 /* Reject eliminable registers. */
4966 if (! (reload_in_progress || reload_completed)
4967 && ( reg_mentioned_p (frame_pointer_rtx, op)
4968 || reg_mentioned_p (arg_pointer_rtx, op)
4969 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4970 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4971 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4972 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4975 if (GET_CODE (op) == MEM)
4981 /* Match: (mem (reg)). */
4982 if (GET_CODE (ind) == REG)
4988 if (GET_CODE (ind) == PLUS
4989 && GET_CODE (XEXP (ind, 0)) == REG
4990 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4991 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4998 /* Return TRUE if OP is a valid coprocessor memory address pattern.
4999 WB if true if writeback address modes are allowed. */
5002 arm_coproc_mem_operand (rtx op, bool wb)
5006 /* Reject eliminable registers. */
5007 if (! (reload_in_progress || reload_completed)
5008 && ( reg_mentioned_p (frame_pointer_rtx, op)
5009 || reg_mentioned_p (arg_pointer_rtx, op)
5010 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5011 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5012 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5013 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5016 /* Constants are converted into offsets from labels. */
5017 if (GET_CODE (op) != MEM)
5022 if (reload_completed
5023 && (GET_CODE (ind) == LABEL_REF
5024 || (GET_CODE (ind) == CONST
5025 && GET_CODE (XEXP (ind, 0)) == PLUS
5026 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5027 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5030 /* Match: (mem (reg)). */
5031 if (GET_CODE (ind) == REG)
5032 return arm_address_register_rtx_p (ind, 0);
5034 /* Autoincremment addressing modes. */
5036 && (GET_CODE (ind) == PRE_INC
5037 || GET_CODE (ind) == POST_INC
5038 || GET_CODE (ind) == PRE_DEC
5039 || GET_CODE (ind) == POST_DEC))
5040 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5043 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5044 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5045 && GET_CODE (XEXP (ind, 1)) == PLUS
5046 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5047 ind = XEXP (ind, 1);
5052 if (GET_CODE (ind) == PLUS
5053 && GET_CODE (XEXP (ind, 0)) == REG
5054 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5055 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5056 && INTVAL (XEXP (ind, 1)) > -1024
5057 && INTVAL (XEXP (ind, 1)) < 1024
5058 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5064 /* Return true if X is a register that will be eliminated later on. */
5066 arm_eliminable_register (rtx x)
5068 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5069 || REGNO (x) == ARG_POINTER_REGNUM
5070 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5071 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5074 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5075 VFP registers. Otherwise return NO_REGS. */
5078 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
5080 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
5083 return GENERAL_REGS;
5086 /* Values which must be returned in the most-significant end of the return
5090 arm_return_in_msb (tree valtype)
5092 return (TARGET_AAPCS_BASED
5094 && (AGGREGATE_TYPE_P (valtype)
5095 || TREE_CODE (valtype) == COMPLEX_TYPE));
5098 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5099 Use by the Cirrus Maverick code which has to workaround
5100 a hardware bug triggered by such instructions. */
5102 arm_memory_load_p (rtx insn)
5104 rtx body, lhs, rhs;;
5106 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5109 body = PATTERN (insn);
5111 if (GET_CODE (body) != SET)
5114 lhs = XEXP (body, 0);
5115 rhs = XEXP (body, 1);
5117 lhs = REG_OR_SUBREG_RTX (lhs);
5119 /* If the destination is not a general purpose
5120 register we do not have to worry. */
5121 if (GET_CODE (lhs) != REG
5122 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5125 /* As well as loads from memory we also have to react
5126 to loads of invalid constants which will be turned
5127 into loads from the minipool. */
5128 return (GET_CODE (rhs) == MEM
5129 || GET_CODE (rhs) == SYMBOL_REF
5130 || note_invalid_constants (insn, -1, false));
5133 /* Return TRUE if INSN is a Cirrus instruction. */
5135 arm_cirrus_insn_p (rtx insn)
5137 enum attr_cirrus attr;
5139 /* get_attr cannot accept USE or CLOBBER. */
5141 || GET_CODE (insn) != INSN
5142 || GET_CODE (PATTERN (insn)) == USE
5143 || GET_CODE (PATTERN (insn)) == CLOBBER)
5146 attr = get_attr_cirrus (insn);
5148 return attr != CIRRUS_NOT;
5151 /* Cirrus reorg for invalid instruction combinations. */
5153 cirrus_reorg (rtx first)
5155 enum attr_cirrus attr;
5156 rtx body = PATTERN (first);
5160 /* Any branch must be followed by 2 non Cirrus instructions. */
5161 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5164 t = next_nonnote_insn (first);
5166 if (arm_cirrus_insn_p (t))
5169 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5173 emit_insn_after (gen_nop (), first);
5178 /* (float (blah)) is in parallel with a clobber. */
5179 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5180 body = XVECEXP (body, 0, 0);
5182 if (GET_CODE (body) == SET)
5184 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5186 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5187 be followed by a non Cirrus insn. */
5188 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5190 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5191 emit_insn_after (gen_nop (), first);
5195 else if (arm_memory_load_p (first))
5197 unsigned int arm_regno;
5199 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5200 ldr/cfmv64hr combination where the Rd field is the same
5201 in both instructions must be split with a non Cirrus
5208 /* Get Arm register number for ldr insn. */
5209 if (GET_CODE (lhs) == REG)
5210 arm_regno = REGNO (lhs);
5213 gcc_assert (GET_CODE (rhs) == REG);
5214 arm_regno = REGNO (rhs);
5218 first = next_nonnote_insn (first);
5220 if (! arm_cirrus_insn_p (first))
5223 body = PATTERN (first);
5225 /* (float (blah)) is in parallel with a clobber. */
5226 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5227 body = XVECEXP (body, 0, 0);
5229 if (GET_CODE (body) == FLOAT)
5230 body = XEXP (body, 0);
5232 if (get_attr_cirrus (first) == CIRRUS_MOVE
5233 && GET_CODE (XEXP (body, 1)) == REG
5234 && arm_regno == REGNO (XEXP (body, 1)))
5235 emit_insn_after (gen_nop (), first);
5241 /* get_attr cannot accept USE or CLOBBER. */
5243 || GET_CODE (first) != INSN
5244 || GET_CODE (PATTERN (first)) == USE
5245 || GET_CODE (PATTERN (first)) == CLOBBER)
5248 attr = get_attr_cirrus (first);
5250 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5251 must be followed by a non-coprocessor instruction. */
5252 if (attr == CIRRUS_COMPARE)
5256 t = next_nonnote_insn (first);
5258 if (arm_cirrus_insn_p (t))
5261 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5265 emit_insn_after (gen_nop (), first);
5271 /* Return TRUE if X references a SYMBOL_REF. */
5273 symbol_mentioned_p (rtx x)
5278 if (GET_CODE (x) == SYMBOL_REF)
5281 fmt = GET_RTX_FORMAT (GET_CODE (x));
5283 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5289 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5290 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5293 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5300 /* Return TRUE if X references a LABEL_REF. */
5302 label_mentioned_p (rtx x)
5307 if (GET_CODE (x) == LABEL_REF)
5310 fmt = GET_RTX_FORMAT (GET_CODE (x));
5311 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5317 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5318 if (label_mentioned_p (XVECEXP (x, i, j)))
5321 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5331 enum rtx_code code = GET_CODE (x);
5348 /* Return 1 if memory locations are adjacent. */
5350 adjacent_mem_locations (rtx a, rtx b)
5352 /* We don't guarantee to preserve the order of these memory refs. */
5353 if (volatile_refs_p (a) || volatile_refs_p (b))
5356 if ((GET_CODE (XEXP (a, 0)) == REG
5357 || (GET_CODE (XEXP (a, 0)) == PLUS
5358 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5359 && (GET_CODE (XEXP (b, 0)) == REG
5360 || (GET_CODE (XEXP (b, 0)) == PLUS
5361 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5363 HOST_WIDE_INT val0 = 0, val1 = 0;
5367 if (GET_CODE (XEXP (a, 0)) == PLUS)
5369 reg0 = XEXP (XEXP (a, 0), 0);
5370 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5375 if (GET_CODE (XEXP (b, 0)) == PLUS)
5377 reg1 = XEXP (XEXP (b, 0), 0);
5378 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5383 /* Don't accept any offset that will require multiple
5384 instructions to handle, since this would cause the
5385 arith_adjacentmem pattern to output an overlong sequence. */
5386 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5389 /* Don't allow an eliminable register: register elimination can make
5390 the offset too large. */
5391 if (arm_eliminable_register (reg0))
5394 val_diff = val1 - val0;
5398 /* If the target has load delay slots, then there's no benefit
5399 to using an ldm instruction unless the offset is zero and
5400 we are optimizing for size. */
5401 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
5402 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
5403 && (val_diff == 4 || val_diff == -4));
5406 return ((REGNO (reg0) == REGNO (reg1))
5407 && (val_diff == 4 || val_diff == -4));
5414 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5415 HOST_WIDE_INT *load_offset)
5417 int unsorted_regs[4];
5418 HOST_WIDE_INT unsorted_offsets[4];
5423 /* Can only handle 2, 3, or 4 insns at present,
5424 though could be easily extended if required. */
5425 gcc_assert (nops >= 2 && nops <= 4);
5427 /* Loop over the operands and check that the memory references are
5428 suitable (i.e. immediate offsets from the same base register). At
5429 the same time, extract the target register, and the memory
5431 for (i = 0; i < nops; i++)
5436 /* Convert a subreg of a mem into the mem itself. */
5437 if (GET_CODE (operands[nops + i]) == SUBREG)
5438 operands[nops + i] = alter_subreg (operands + (nops + i));
5440 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5442 /* Don't reorder volatile memory references; it doesn't seem worth
5443 looking for the case where the order is ok anyway. */
5444 if (MEM_VOLATILE_P (operands[nops + i]))
5447 offset = const0_rtx;
5449 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5450 || (GET_CODE (reg) == SUBREG
5451 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5452 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5453 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5455 || (GET_CODE (reg) == SUBREG
5456 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5457 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5462 base_reg = REGNO (reg);
5463 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5464 ? REGNO (operands[i])
5465 : REGNO (SUBREG_REG (operands[i])));
5470 if (base_reg != (int) REGNO (reg))
5471 /* Not addressed from the same base register. */
5474 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5475 ? REGNO (operands[i])
5476 : REGNO (SUBREG_REG (operands[i])));
5477 if (unsorted_regs[i] < unsorted_regs[order[0]])
5481 /* If it isn't an integer register, or if it overwrites the
5482 base register but isn't the last insn in the list, then
5483 we can't do this. */
5484 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5485 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5488 unsorted_offsets[i] = INTVAL (offset);
5491 /* Not a suitable memory address. */
5495 /* All the useful information has now been extracted from the
5496 operands into unsorted_regs and unsorted_offsets; additionally,
5497 order[0] has been set to the lowest numbered register in the
5498 list. Sort the registers into order, and check that the memory
5499 offsets are ascending and adjacent. */
5501 for (i = 1; i < nops; i++)
5505 order[i] = order[i - 1];
5506 for (j = 0; j < nops; j++)
5507 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5508 && (order[i] == order[i - 1]
5509 || unsorted_regs[j] < unsorted_regs[order[i]]))
5512 /* Have we found a suitable register? if not, one must be used more
5514 if (order[i] == order[i - 1])
5517 /* Is the memory address adjacent and ascending? */
5518 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5526 for (i = 0; i < nops; i++)
5527 regs[i] = unsorted_regs[order[i]];
5529 *load_offset = unsorted_offsets[order[0]];
5532 if (unsorted_offsets[order[0]] == 0)
5533 return 1; /* ldmia */
5535 if (unsorted_offsets[order[0]] == 4)
5536 return 2; /* ldmib */
5538 if (unsorted_offsets[order[nops - 1]] == 0)
5539 return 3; /* ldmda */
5541 if (unsorted_offsets[order[nops - 1]] == -4)
5542 return 4; /* ldmdb */
5544 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5545 if the offset isn't small enough. The reason 2 ldrs are faster
5546 is because these ARMs are able to do more than one cache access
5547 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5548 whilst the ARM8 has a double bandwidth cache. This means that
5549 these cores can do both an instruction fetch and a data fetch in
5550 a single cycle, so the trick of calculating the address into a
5551 scratch register (one of the result regs) and then doing a load
5552 multiple actually becomes slower (and no smaller in code size).
5553 That is the transformation
5555 ldr rd1, [rbase + offset]
5556 ldr rd2, [rbase + offset + 4]
5560 add rd1, rbase, offset
5561 ldmia rd1, {rd1, rd2}
5563 produces worse code -- '3 cycles + any stalls on rd2' instead of
5564 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5565 access per cycle, the first sequence could never complete in less
5566 than 6 cycles, whereas the ldm sequence would only take 5 and
5567 would make better use of sequential accesses if not hitting the
5570 We cheat here and test 'arm_ld_sched' which we currently know to
5571 only be true for the ARM8, ARM9 and StrongARM. If this ever
5572 changes, then the test below needs to be reworked. */
5573 if (nops == 2 && arm_ld_sched)
5576 /* Can't do it without setting up the offset, only do this if it takes
5577 no more than one insn. */
5578 return (const_ok_for_arm (unsorted_offsets[order[0]])
5579 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5583 emit_ldm_seq (rtx *operands, int nops)
5587 HOST_WIDE_INT offset;
5591 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5594 strcpy (buf, "ldm%?ia\t");
5598 strcpy (buf, "ldm%?ib\t");
5602 strcpy (buf, "ldm%?da\t");
5606 strcpy (buf, "ldm%?db\t");
5611 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5612 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5615 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5616 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5618 output_asm_insn (buf, operands);
5620 strcpy (buf, "ldm%?ia\t");
5627 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5628 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5630 for (i = 1; i < nops; i++)
5631 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5632 reg_names[regs[i]]);
5634 strcat (buf, "}\t%@ phole ldm");
5636 output_asm_insn (buf, operands);
5641 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5642 HOST_WIDE_INT * load_offset)
5644 int unsorted_regs[4];
5645 HOST_WIDE_INT unsorted_offsets[4];
5650 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5651 extended if required. */
5652 gcc_assert (nops >= 2 && nops <= 4);
5654 /* Loop over the operands and check that the memory references are
5655 suitable (i.e. immediate offsets from the same base register). At
5656 the same time, extract the target register, and the memory
5658 for (i = 0; i < nops; i++)
5663 /* Convert a subreg of a mem into the mem itself. */
5664 if (GET_CODE (operands[nops + i]) == SUBREG)
5665 operands[nops + i] = alter_subreg (operands + (nops + i));
5667 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5669 /* Don't reorder volatile memory references; it doesn't seem worth
5670 looking for the case where the order is ok anyway. */
5671 if (MEM_VOLATILE_P (operands[nops + i]))
5674 offset = const0_rtx;
5676 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5677 || (GET_CODE (reg) == SUBREG
5678 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5679 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5680 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5682 || (GET_CODE (reg) == SUBREG
5683 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5684 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5689 base_reg = REGNO (reg);
5690 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5691 ? REGNO (operands[i])
5692 : REGNO (SUBREG_REG (operands[i])));
5697 if (base_reg != (int) REGNO (reg))
5698 /* Not addressed from the same base register. */
5701 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5702 ? REGNO (operands[i])
5703 : REGNO (SUBREG_REG (operands[i])));
5704 if (unsorted_regs[i] < unsorted_regs[order[0]])
5708 /* If it isn't an integer register, then we can't do this. */
5709 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5712 unsorted_offsets[i] = INTVAL (offset);
5715 /* Not a suitable memory address. */
5719 /* All the useful information has now been extracted from the
5720 operands into unsorted_regs and unsorted_offsets; additionally,
5721 order[0] has been set to the lowest numbered register in the
5722 list. Sort the registers into order, and check that the memory
5723 offsets are ascending and adjacent. */
5725 for (i = 1; i < nops; i++)
5729 order[i] = order[i - 1];
5730 for (j = 0; j < nops; j++)
5731 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5732 && (order[i] == order[i - 1]
5733 || unsorted_regs[j] < unsorted_regs[order[i]]))
5736 /* Have we found a suitable register? if not, one must be used more
5738 if (order[i] == order[i - 1])
5741 /* Is the memory address adjacent and ascending? */
5742 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5750 for (i = 0; i < nops; i++)
5751 regs[i] = unsorted_regs[order[i]];
5753 *load_offset = unsorted_offsets[order[0]];
5756 if (unsorted_offsets[order[0]] == 0)
5757 return 1; /* stmia */
5759 if (unsorted_offsets[order[0]] == 4)
5760 return 2; /* stmib */
5762 if (unsorted_offsets[order[nops - 1]] == 0)
5763 return 3; /* stmda */
5765 if (unsorted_offsets[order[nops - 1]] == -4)
5766 return 4; /* stmdb */
5772 emit_stm_seq (rtx *operands, int nops)
5776 HOST_WIDE_INT offset;
5780 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5783 strcpy (buf, "stm%?ia\t");
5787 strcpy (buf, "stm%?ib\t");
5791 strcpy (buf, "stm%?da\t");
5795 strcpy (buf, "stm%?db\t");
5802 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5803 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5805 for (i = 1; i < nops; i++)
5806 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5807 reg_names[regs[i]]);
5809 strcat (buf, "}\t%@ phole stm");
5811 output_asm_insn (buf, operands);
5816 /* Routines for use in generating RTL. */
5819 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5820 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5822 HOST_WIDE_INT offset = *offsetp;
5825 int sign = up ? 1 : -1;
5828 /* XScale has load-store double instructions, but they have stricter
5829 alignment requirements than load-store multiple, so we cannot
5832 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5833 the pipeline until completion.
5841 An ldr instruction takes 1-3 cycles, but does not block the
5850 Best case ldr will always win. However, the more ldr instructions
5851 we issue, the less likely we are to be able to schedule them well.
5852 Using ldr instructions also increases code size.
5854 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5855 for counts of 3 or 4 regs. */
5856 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5862 for (i = 0; i < count; i++)
5864 addr = plus_constant (from, i * 4 * sign);
5865 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5866 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5872 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5882 result = gen_rtx_PARALLEL (VOIDmode,
5883 rtvec_alloc (count + (write_back ? 1 : 0)));
5886 XVECEXP (result, 0, 0)
5887 = gen_rtx_SET (GET_MODE (from), from,
5888 plus_constant (from, count * 4 * sign));
5893 for (j = 0; i < count; i++, j++)
5895 addr = plus_constant (from, j * 4 * sign);
5896 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5897 XVECEXP (result, 0, i)
5898 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5909 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5910 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5912 HOST_WIDE_INT offset = *offsetp;
5915 int sign = up ? 1 : -1;
5918 /* See arm_gen_load_multiple for discussion of
5919 the pros/cons of ldm/stm usage for XScale. */
5920 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5926 for (i = 0; i < count; i++)
5928 addr = plus_constant (to, i * 4 * sign);
5929 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5930 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5936 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5946 result = gen_rtx_PARALLEL (VOIDmode,
5947 rtvec_alloc (count + (write_back ? 1 : 0)));
5950 XVECEXP (result, 0, 0)
5951 = gen_rtx_SET (GET_MODE (to), to,
5952 plus_constant (to, count * 4 * sign));
5957 for (j = 0; i < count; i++, j++)
5959 addr = plus_constant (to, j * 4 * sign);
5960 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5961 XVECEXP (result, 0, i)
5962 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5973 arm_gen_movmemqi (rtx *operands)
5975 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5976 HOST_WIDE_INT srcoffset, dstoffset;
5978 rtx src, dst, srcbase, dstbase;
5979 rtx part_bytes_reg = NULL;
5982 if (GET_CODE (operands[2]) != CONST_INT
5983 || GET_CODE (operands[3]) != CONST_INT
5984 || INTVAL (operands[2]) > 64
5985 || INTVAL (operands[3]) & 3)
5988 dstbase = operands[0];
5989 srcbase = operands[1];
5991 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5992 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5994 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5995 out_words_to_go = INTVAL (operands[2]) / 4;
5996 last_bytes = INTVAL (operands[2]) & 3;
5997 dstoffset = srcoffset = 0;
5999 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6000 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6002 for (i = 0; in_words_to_go >= 2; i+=4)
6004 if (in_words_to_go > 4)
6005 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6006 srcbase, &srcoffset));
6008 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6009 FALSE, srcbase, &srcoffset));
6011 if (out_words_to_go)
6013 if (out_words_to_go > 4)
6014 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6015 dstbase, &dstoffset));
6016 else if (out_words_to_go != 1)
6017 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6021 dstbase, &dstoffset));
6024 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6025 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6026 if (last_bytes != 0)
6028 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6034 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6035 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6038 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6039 if (out_words_to_go)
6043 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6044 sreg = copy_to_reg (mem);
6046 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6047 emit_move_insn (mem, sreg);
6050 gcc_assert (!in_words_to_go); /* Sanity check */
6055 gcc_assert (in_words_to_go > 0);
6057 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6058 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6061 gcc_assert (!last_bytes || part_bytes_reg);
6063 if (BYTES_BIG_ENDIAN && last_bytes)
6065 rtx tmp = gen_reg_rtx (SImode);
6067 /* The bytes we want are in the top end of the word. */
6068 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6069 GEN_INT (8 * (4 - last_bytes))));
6070 part_bytes_reg = tmp;
6074 mem = adjust_automodify_address (dstbase, QImode,
6075 plus_constant (dst, last_bytes - 1),
6076 dstoffset + last_bytes - 1);
6077 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6081 tmp = gen_reg_rtx (SImode);
6082 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6083 part_bytes_reg = tmp;
6092 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6093 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6097 rtx tmp = gen_reg_rtx (SImode);
6098 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6099 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6100 part_bytes_reg = tmp;
6107 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6108 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6115 /* Select a dominance comparison mode if possible for a test of the general
6116 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6117 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6118 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6119 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6120 In all cases OP will be either EQ or NE, but we don't need to know which
6121 here. If we are unable to support a dominance comparison we return
6122 CC mode. This will then fail to match for the RTL expressions that
6123 generate this call. */
6125 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6127 enum rtx_code cond1, cond2;
6130 /* Currently we will probably get the wrong result if the individual
6131 comparisons are not simple. This also ensures that it is safe to
6132 reverse a comparison if necessary. */
6133 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6135 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6139 /* The if_then_else variant of this tests the second condition if the
6140 first passes, but is true if the first fails. Reverse the first
6141 condition to get a true "inclusive-or" expression. */
6142 if (cond_or == DOM_CC_NX_OR_Y)
6143 cond1 = reverse_condition (cond1);
6145 /* If the comparisons are not equal, and one doesn't dominate the other,
6146 then we can't do this. */
6148 && !comparison_dominates_p (cond1, cond2)
6149 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6154 enum rtx_code temp = cond1;
6162 if (cond_or == DOM_CC_X_AND_Y)
6167 case EQ: return CC_DEQmode;
6168 case LE: return CC_DLEmode;
6169 case LEU: return CC_DLEUmode;
6170 case GE: return CC_DGEmode;
6171 case GEU: return CC_DGEUmode;
6172 default: gcc_unreachable ();
6176 if (cond_or == DOM_CC_X_AND_Y)
6192 if (cond_or == DOM_CC_X_AND_Y)
6208 if (cond_or == DOM_CC_X_AND_Y)
6224 if (cond_or == DOM_CC_X_AND_Y)
6239 /* The remaining cases only occur when both comparisons are the
6242 gcc_assert (cond1 == cond2);
6246 gcc_assert (cond1 == cond2);
6250 gcc_assert (cond1 == cond2);
6254 gcc_assert (cond1 == cond2);
6258 gcc_assert (cond1 == cond2);
6267 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6269 /* All floating point compares return CCFP if it is an equality
6270 comparison, and CCFPE otherwise. */
6271 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6291 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6300 /* A compare with a shifted operand. Because of canonicalization, the
6301 comparison will have to be swapped when we emit the assembler. */
6302 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6303 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6304 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6305 || GET_CODE (x) == ROTATERT))
6308 /* This operation is performed swapped, but since we only rely on the Z
6309 flag we don't need an additional mode. */
6310 if (GET_MODE (y) == SImode && REG_P (y)
6311 && GET_CODE (x) == NEG
6312 && (op == EQ || op == NE))
6315 /* This is a special case that is used by combine to allow a
6316 comparison of a shifted byte load to be split into a zero-extend
6317 followed by a comparison of the shifted integer (only valid for
6318 equalities and unsigned inequalities). */
6319 if (GET_MODE (x) == SImode
6320 && GET_CODE (x) == ASHIFT
6321 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6322 && GET_CODE (XEXP (x, 0)) == SUBREG
6323 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6324 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6325 && (op == EQ || op == NE
6326 || op == GEU || op == GTU || op == LTU || op == LEU)
6327 && GET_CODE (y) == CONST_INT)
6330 /* A construct for a conditional compare, if the false arm contains
6331 0, then both conditions must be true, otherwise either condition
6332 must be true. Not all conditions are possible, so CCmode is
6333 returned if it can't be done. */
6334 if (GET_CODE (x) == IF_THEN_ELSE
6335 && (XEXP (x, 2) == const0_rtx
6336 || XEXP (x, 2) == const1_rtx)
6337 && COMPARISON_P (XEXP (x, 0))
6338 && COMPARISON_P (XEXP (x, 1)))
6339 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6340 INTVAL (XEXP (x, 2)));
6342 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6343 if (GET_CODE (x) == AND
6344 && COMPARISON_P (XEXP (x, 0))
6345 && COMPARISON_P (XEXP (x, 1)))
6346 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6349 if (GET_CODE (x) == IOR
6350 && COMPARISON_P (XEXP (x, 0))
6351 && COMPARISON_P (XEXP (x, 1)))
6352 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6355 /* An operation (on Thumb) where we want to test for a single bit.
6356 This is done by shifting that bit up into the top bit of a
6357 scratch register; we can then branch on the sign bit. */
6359 && GET_MODE (x) == SImode
6360 && (op == EQ || op == NE)
6361 && (GET_CODE (x) == ZERO_EXTRACT))
6364 /* An operation that sets the condition codes as a side-effect, the
6365 V flag is not set correctly, so we can only use comparisons where
6366 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6368 if (GET_MODE (x) == SImode
6370 && (op == EQ || op == NE || op == LT || op == GE)
6371 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6372 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6373 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6374 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6375 || GET_CODE (x) == LSHIFTRT
6376 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6377 || GET_CODE (x) == ROTATERT
6378 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6381 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6384 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6385 && GET_CODE (x) == PLUS
6386 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6392 /* X and Y are two things to compare using CODE. Emit the compare insn and
6393 return the rtx for register 0 in the proper mode. FP means this is a
6394 floating point compare: I don't think that it is needed on the arm. */
6396 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6398 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6399 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6401 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6402 gen_rtx_COMPARE (mode, x, y)));
6407 /* Generate a sequence of insns that will generate the correct return
6408 address mask depending on the physical architecture that the program
6411 arm_gen_return_addr_mask (void)
6413 rtx reg = gen_reg_rtx (Pmode);
6415 emit_insn (gen_return_addr_mask (reg));
6420 arm_reload_in_hi (rtx *operands)
6422 rtx ref = operands[1];
6424 HOST_WIDE_INT offset = 0;
6426 if (GET_CODE (ref) == SUBREG)
6428 offset = SUBREG_BYTE (ref);
6429 ref = SUBREG_REG (ref);
6432 if (GET_CODE (ref) == REG)
6434 /* We have a pseudo which has been spilt onto the stack; there
6435 are two cases here: the first where there is a simple
6436 stack-slot replacement and a second where the stack-slot is
6437 out of range, or is used as a subreg. */
6438 if (reg_equiv_mem[REGNO (ref)])
6440 ref = reg_equiv_mem[REGNO (ref)];
6441 base = find_replacement (&XEXP (ref, 0));
6444 /* The slot is out of range, or was dressed up in a SUBREG. */
6445 base = reg_equiv_address[REGNO (ref)];
6448 base = find_replacement (&XEXP (ref, 0));
6450 /* Handle the case where the address is too complex to be offset by 1. */
6451 if (GET_CODE (base) == MINUS
6452 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6454 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6456 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6459 else if (GET_CODE (base) == PLUS)
6461 /* The addend must be CONST_INT, or we would have dealt with it above. */
6462 HOST_WIDE_INT hi, lo;
6464 offset += INTVAL (XEXP (base, 1));
6465 base = XEXP (base, 0);
6467 /* Rework the address into a legal sequence of insns. */
6468 /* Valid range for lo is -4095 -> 4095 */
6471 : -((-offset) & 0xfff));
6473 /* Corner case, if lo is the max offset then we would be out of range
6474 once we have added the additional 1 below, so bump the msb into the
6475 pre-loading insn(s). */
6479 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6480 ^ (HOST_WIDE_INT) 0x80000000)
6481 - (HOST_WIDE_INT) 0x80000000);
6483 gcc_assert (hi + lo == offset);
6487 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6489 /* Get the base address; addsi3 knows how to handle constants
6490 that require more than one insn. */
6491 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6497 /* Operands[2] may overlap operands[0] (though it won't overlap
6498 operands[1]), that's why we asked for a DImode reg -- so we can
6499 use the bit that does not overlap. */
6500 if (REGNO (operands[2]) == REGNO (operands[0]))
6501 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6503 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6505 emit_insn (gen_zero_extendqisi2 (scratch,
6506 gen_rtx_MEM (QImode,
6507 plus_constant (base,
6509 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6510 gen_rtx_MEM (QImode,
6511 plus_constant (base,
6513 if (!BYTES_BIG_ENDIAN)
6514 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6515 gen_rtx_IOR (SImode,
6518 gen_rtx_SUBREG (SImode, operands[0], 0),
6522 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6523 gen_rtx_IOR (SImode,
6524 gen_rtx_ASHIFT (SImode, scratch,
6526 gen_rtx_SUBREG (SImode, operands[0],
6530 /* Handle storing a half-word to memory during reload by synthesizing as two
6531 byte stores. Take care not to clobber the input values until after we
6532 have moved them somewhere safe. This code assumes that if the DImode
6533 scratch in operands[2] overlaps either the input value or output address
6534 in some way, then that value must die in this insn (we absolutely need
6535 two scratch registers for some corner cases). */
6537 arm_reload_out_hi (rtx *operands)
6539 rtx ref = operands[0];
6540 rtx outval = operands[1];
6542 HOST_WIDE_INT offset = 0;
6544 if (GET_CODE (ref) == SUBREG)
6546 offset = SUBREG_BYTE (ref);
6547 ref = SUBREG_REG (ref);
6550 if (GET_CODE (ref) == REG)
6552 /* We have a pseudo which has been spilt onto the stack; there
6553 are two cases here: the first where there is a simple
6554 stack-slot replacement and a second where the stack-slot is
6555 out of range, or is used as a subreg. */
6556 if (reg_equiv_mem[REGNO (ref)])
6558 ref = reg_equiv_mem[REGNO (ref)];
6559 base = find_replacement (&XEXP (ref, 0));
6562 /* The slot is out of range, or was dressed up in a SUBREG. */
6563 base = reg_equiv_address[REGNO (ref)];
6566 base = find_replacement (&XEXP (ref, 0));
6568 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6570 /* Handle the case where the address is too complex to be offset by 1. */
6571 if (GET_CODE (base) == MINUS
6572 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6574 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6576 /* Be careful not to destroy OUTVAL. */
6577 if (reg_overlap_mentioned_p (base_plus, outval))
6579 /* Updating base_plus might destroy outval, see if we can
6580 swap the scratch and base_plus. */
6581 if (!reg_overlap_mentioned_p (scratch, outval))
6584 scratch = base_plus;
6589 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6591 /* Be conservative and copy OUTVAL into the scratch now,
6592 this should only be necessary if outval is a subreg
6593 of something larger than a word. */
6594 /* XXX Might this clobber base? I can't see how it can,
6595 since scratch is known to overlap with OUTVAL, and
6596 must be wider than a word. */
6597 emit_insn (gen_movhi (scratch_hi, outval));
6598 outval = scratch_hi;
6602 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6605 else if (GET_CODE (base) == PLUS)
6607 /* The addend must be CONST_INT, or we would have dealt with it above. */
6608 HOST_WIDE_INT hi, lo;
6610 offset += INTVAL (XEXP (base, 1));
6611 base = XEXP (base, 0);
6613 /* Rework the address into a legal sequence of insns. */
6614 /* Valid range for lo is -4095 -> 4095 */
6617 : -((-offset) & 0xfff));
6619 /* Corner case, if lo is the max offset then we would be out of range
6620 once we have added the additional 1 below, so bump the msb into the
6621 pre-loading insn(s). */
6625 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6626 ^ (HOST_WIDE_INT) 0x80000000)
6627 - (HOST_WIDE_INT) 0x80000000);
6629 gcc_assert (hi + lo == offset);
6633 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6635 /* Be careful not to destroy OUTVAL. */
6636 if (reg_overlap_mentioned_p (base_plus, outval))
6638 /* Updating base_plus might destroy outval, see if we
6639 can swap the scratch and base_plus. */
6640 if (!reg_overlap_mentioned_p (scratch, outval))
6643 scratch = base_plus;
6648 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6650 /* Be conservative and copy outval into scratch now,
6651 this should only be necessary if outval is a
6652 subreg of something larger than a word. */
6653 /* XXX Might this clobber base? I can't see how it
6654 can, since scratch is known to overlap with
6656 emit_insn (gen_movhi (scratch_hi, outval));
6657 outval = scratch_hi;
6661 /* Get the base address; addsi3 knows how to handle constants
6662 that require more than one insn. */
6663 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6669 if (BYTES_BIG_ENDIAN)
6671 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6672 plus_constant (base, offset + 1)),
6673 gen_lowpart (QImode, outval)));
6674 emit_insn (gen_lshrsi3 (scratch,
6675 gen_rtx_SUBREG (SImode, outval, 0),
6677 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6678 gen_lowpart (QImode, scratch)));
6682 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6683 gen_lowpart (QImode, outval)));
6684 emit_insn (gen_lshrsi3 (scratch,
6685 gen_rtx_SUBREG (SImode, outval, 0),
6687 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6688 plus_constant (base, offset + 1)),
6689 gen_lowpart (QImode, scratch)));
6693 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
6694 (padded to the size of a word) should be passed in a register. */
6697 arm_must_pass_in_stack (enum machine_mode mode, tree type)
6699 if (TARGET_AAPCS_BASED)
6700 return must_pass_in_stack_var_size (mode, type);
6702 return must_pass_in_stack_var_size_or_pad (mode, type);
6706 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
6707 Return true if an argument passed on the stack should be padded upwards,
6708 i.e. if the least-significant byte has useful data.
6709 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
6710 aggregate types are placed in the lowest memory address. */
6713 arm_pad_arg_upward (enum machine_mode mode, tree type)
6715 if (!TARGET_AAPCS_BASED)
6716 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
6718 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
6725 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6726 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
6727 byte of the register has useful data, and return the opposite if the
6728 most significant byte does.
6729 For AAPCS, small aggregates and small complex types are always padded
6733 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
6734 tree type, int first ATTRIBUTE_UNUSED)
6736 if (TARGET_AAPCS_BASED
6738 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
6739 && int_size_in_bytes (type) <= 4)
6742 /* Otherwise, use default padding. */
6743 return !BYTES_BIG_ENDIAN;
6747 /* Print a symbolic form of X to the debug file, F. */
6749 arm_print_value (FILE *f, rtx x)
6751 switch (GET_CODE (x))
6754 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6758 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6766 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6768 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6769 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6777 fprintf (f, "\"%s\"", XSTR (x, 0));
6781 fprintf (f, "`%s'", XSTR (x, 0));
6785 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6789 arm_print_value (f, XEXP (x, 0));
6793 arm_print_value (f, XEXP (x, 0));
6795 arm_print_value (f, XEXP (x, 1));
6803 fprintf (f, "????");
6808 /* Routines for manipulation of the constant pool. */
6810 /* Arm instructions cannot load a large constant directly into a
6811 register; they have to come from a pc relative load. The constant
6812 must therefore be placed in the addressable range of the pc
6813 relative load. Depending on the precise pc relative load
6814 instruction the range is somewhere between 256 bytes and 4k. This
6815 means that we often have to dump a constant inside a function, and
6816 generate code to branch around it.
6818 It is important to minimize this, since the branches will slow
6819 things down and make the code larger.
6821 Normally we can hide the table after an existing unconditional
6822 branch so that there is no interruption of the flow, but in the
6823 worst case the code looks like this:
6841 We fix this by performing a scan after scheduling, which notices
6842 which instructions need to have their operands fetched from the
6843 constant table and builds the table.
6845 The algorithm starts by building a table of all the constants that
6846 need fixing up and all the natural barriers in the function (places
6847 where a constant table can be dropped without breaking the flow).
6848 For each fixup we note how far the pc-relative replacement will be
6849 able to reach and the offset of the instruction into the function.
6851 Having built the table we then group the fixes together to form
6852 tables that are as large as possible (subject to addressing
6853 constraints) and emit each table of constants after the last
6854 barrier that is within range of all the instructions in the group.
6855 If a group does not contain a barrier, then we forcibly create one
6856 by inserting a jump instruction into the flow. Once the table has
6857 been inserted, the insns are then modified to reference the
6858 relevant entry in the pool.
6860 Possible enhancements to the algorithm (not implemented) are:
6862 1) For some processors and object formats, there may be benefit in
6863 aligning the pools to the start of cache lines; this alignment
6864 would need to be taken into account when calculating addressability
6867 /* These typedefs are located at the start of this file, so that
6868 they can be used in the prototypes there. This comment is to
6869 remind readers of that fact so that the following structures
6870 can be understood more easily.
6872 typedef struct minipool_node Mnode;
6873 typedef struct minipool_fixup Mfix; */
6875 struct minipool_node
6877 /* Doubly linked chain of entries. */
6880 /* The maximum offset into the code that this entry can be placed. While
6881 pushing fixes for forward references, all entries are sorted in order
6882 of increasing max_address. */
6883 HOST_WIDE_INT max_address;
6884 /* Similarly for an entry inserted for a backwards ref. */
6885 HOST_WIDE_INT min_address;
6886 /* The number of fixes referencing this entry. This can become zero
6887 if we "unpush" an entry. In this case we ignore the entry when we
6888 come to emit the code. */
6890 /* The offset from the start of the minipool. */
6891 HOST_WIDE_INT offset;
6892 /* The value in table. */
6894 /* The mode of value. */
6895 enum machine_mode mode;
6896 /* The size of the value. With iWMMXt enabled
6897 sizes > 4 also imply an alignment of 8-bytes. */
6901 struct minipool_fixup
6905 HOST_WIDE_INT address;
6907 enum machine_mode mode;
6911 HOST_WIDE_INT forwards;
6912 HOST_WIDE_INT backwards;
6915 /* Fixes less than a word need padding out to a word boundary. */
6916 #define MINIPOOL_FIX_SIZE(mode) \
6917 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6919 static Mnode * minipool_vector_head;
6920 static Mnode * minipool_vector_tail;
6921 static rtx minipool_vector_label;
6923 /* The linked list of all minipool fixes required for this function. */
6924 Mfix * minipool_fix_head;
6925 Mfix * minipool_fix_tail;
6926 /* The fix entry for the current minipool, once it has been placed. */
6927 Mfix * minipool_barrier;
6929 /* Determines if INSN is the start of a jump table. Returns the end
6930 of the TABLE or NULL_RTX. */
6932 is_jump_table (rtx insn)
6936 if (GET_CODE (insn) == JUMP_INSN
6937 && JUMP_LABEL (insn) != NULL
6938 && ((table = next_real_insn (JUMP_LABEL (insn)))
6939 == next_real_insn (insn))
6941 && GET_CODE (table) == JUMP_INSN
6942 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6943 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6949 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6950 #define JUMP_TABLES_IN_TEXT_SECTION 0
6953 static HOST_WIDE_INT
6954 get_jump_table_size (rtx insn)
6956 /* ADDR_VECs only take room if read-only data does into the text
6958 if (JUMP_TABLES_IN_TEXT_SECTION
6959 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6964 rtx body = PATTERN (insn);
6965 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6967 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6973 /* Move a minipool fix MP from its current location to before MAX_MP.
6974 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6975 constraints may need updating. */
6977 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6978 HOST_WIDE_INT max_address)
6980 /* The code below assumes these are different. */
6981 gcc_assert (mp != max_mp);
6985 if (max_address < mp->max_address)
6986 mp->max_address = max_address;
6990 if (max_address > max_mp->max_address - mp->fix_size)
6991 mp->max_address = max_mp->max_address - mp->fix_size;
6993 mp->max_address = max_address;
6995 /* Unlink MP from its current position. Since max_mp is non-null,
6996 mp->prev must be non-null. */
6997 mp->prev->next = mp->next;
6998 if (mp->next != NULL)
6999 mp->next->prev = mp->prev;
7001 minipool_vector_tail = mp->prev;
7003 /* Re-insert it before MAX_MP. */
7005 mp->prev = max_mp->prev;
7008 if (mp->prev != NULL)
7009 mp->prev->next = mp;
7011 minipool_vector_head = mp;
7014 /* Save the new entry. */
7017 /* Scan over the preceding entries and adjust their addresses as
7019 while (mp->prev != NULL
7020 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7022 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7029 /* Add a constant to the minipool for a forward reference. Returns the
7030 node added or NULL if the constant will not fit in this pool. */
7032 add_minipool_forward_ref (Mfix *fix)
7034 /* If set, max_mp is the first pool_entry that has a lower
7035 constraint than the one we are trying to add. */
7036 Mnode * max_mp = NULL;
7037 HOST_WIDE_INT max_address = fix->address + fix->forwards;
7040 /* If this fix's address is greater than the address of the first
7041 entry, then we can't put the fix in this pool. We subtract the
7042 size of the current fix to ensure that if the table is fully
7043 packed we still have enough room to insert this value by shuffling
7044 the other fixes forwards. */
7045 if (minipool_vector_head &&
7046 fix->address >= minipool_vector_head->max_address - fix->fix_size)
7049 /* Scan the pool to see if a constant with the same value has
7050 already been added. While we are doing this, also note the
7051 location where we must insert the constant if it doesn't already
7053 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7055 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7056 && fix->mode == mp->mode
7057 && (GET_CODE (fix->value) != CODE_LABEL
7058 || (CODE_LABEL_NUMBER (fix->value)
7059 == CODE_LABEL_NUMBER (mp->value)))
7060 && rtx_equal_p (fix->value, mp->value))
7062 /* More than one fix references this entry. */
7064 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7067 /* Note the insertion point if necessary. */
7069 && mp->max_address > max_address)
7072 /* If we are inserting an 8-bytes aligned quantity and
7073 we have not already found an insertion point, then
7074 make sure that all such 8-byte aligned quantities are
7075 placed at the start of the pool. */
7076 if (ARM_DOUBLEWORD_ALIGN
7078 && fix->fix_size == 8
7079 && mp->fix_size != 8)
7082 max_address = mp->max_address;
7086 /* The value is not currently in the minipool, so we need to create
7087 a new entry for it. If MAX_MP is NULL, the entry will be put on
7088 the end of the list since the placement is less constrained than
7089 any existing entry. Otherwise, we insert the new fix before
7090 MAX_MP and, if necessary, adjust the constraints on the other
7092 mp = xmalloc (sizeof (* mp));
7093 mp->fix_size = fix->fix_size;
7094 mp->mode = fix->mode;
7095 mp->value = fix->value;
7097 /* Not yet required for a backwards ref. */
7098 mp->min_address = -65536;
7102 mp->max_address = max_address;
7104 mp->prev = minipool_vector_tail;
7106 if (mp->prev == NULL)
7108 minipool_vector_head = mp;
7109 minipool_vector_label = gen_label_rtx ();
7112 mp->prev->next = mp;
7114 minipool_vector_tail = mp;
7118 if (max_address > max_mp->max_address - mp->fix_size)
7119 mp->max_address = max_mp->max_address - mp->fix_size;
7121 mp->max_address = max_address;
7124 mp->prev = max_mp->prev;
7126 if (mp->prev != NULL)
7127 mp->prev->next = mp;
7129 minipool_vector_head = mp;
7132 /* Save the new entry. */
7135 /* Scan over the preceding entries and adjust their addresses as
7137 while (mp->prev != NULL
7138 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7140 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7148 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7149 HOST_WIDE_INT min_address)
7151 HOST_WIDE_INT offset;
7153 /* The code below assumes these are different. */
7154 gcc_assert (mp != min_mp);
7158 if (min_address > mp->min_address)
7159 mp->min_address = min_address;
7163 /* We will adjust this below if it is too loose. */
7164 mp->min_address = min_address;
7166 /* Unlink MP from its current position. Since min_mp is non-null,
7167 mp->next must be non-null. */
7168 mp->next->prev = mp->prev;
7169 if (mp->prev != NULL)
7170 mp->prev->next = mp->next;
7172 minipool_vector_head = mp->next;
7174 /* Reinsert it after MIN_MP. */
7176 mp->next = min_mp->next;
7178 if (mp->next != NULL)
7179 mp->next->prev = mp;
7181 minipool_vector_tail = mp;
7187 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7189 mp->offset = offset;
7190 if (mp->refcount > 0)
7191 offset += mp->fix_size;
7193 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7194 mp->next->min_address = mp->min_address + mp->fix_size;
7200 /* Add a constant to the minipool for a backward reference. Returns the
7201 node added or NULL if the constant will not fit in this pool.
7203 Note that the code for insertion for a backwards reference can be
7204 somewhat confusing because the calculated offsets for each fix do
7205 not take into account the size of the pool (which is still under
7208 add_minipool_backward_ref (Mfix *fix)
7210 /* If set, min_mp is the last pool_entry that has a lower constraint
7211 than the one we are trying to add. */
7212 Mnode *min_mp = NULL;
7213 /* This can be negative, since it is only a constraint. */
7214 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7217 /* If we can't reach the current pool from this insn, or if we can't
7218 insert this entry at the end of the pool without pushing other
7219 fixes out of range, then we don't try. This ensures that we
7220 can't fail later on. */
7221 if (min_address >= minipool_barrier->address
7222 || (minipool_vector_tail->min_address + fix->fix_size
7223 >= minipool_barrier->address))
7226 /* Scan the pool to see if a constant with the same value has
7227 already been added. While we are doing this, also note the
7228 location where we must insert the constant if it doesn't already
7230 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7232 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7233 && fix->mode == mp->mode
7234 && (GET_CODE (fix->value) != CODE_LABEL
7235 || (CODE_LABEL_NUMBER (fix->value)
7236 == CODE_LABEL_NUMBER (mp->value)))
7237 && rtx_equal_p (fix->value, mp->value)
7238 /* Check that there is enough slack to move this entry to the
7239 end of the table (this is conservative). */
7241 > (minipool_barrier->address
7242 + minipool_vector_tail->offset
7243 + minipool_vector_tail->fix_size)))
7246 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7250 mp->min_address += fix->fix_size;
7253 /* Note the insertion point if necessary. */
7254 if (mp->min_address < min_address)
7256 /* For now, we do not allow the insertion of 8-byte alignment
7257 requiring nodes anywhere but at the start of the pool. */
7258 if (ARM_DOUBLEWORD_ALIGN
7259 && fix->fix_size == 8 && mp->fix_size != 8)
7264 else if (mp->max_address
7265 < minipool_barrier->address + mp->offset + fix->fix_size)
7267 /* Inserting before this entry would push the fix beyond
7268 its maximum address (which can happen if we have
7269 re-located a forwards fix); force the new fix to come
7272 min_address = mp->min_address + fix->fix_size;
7274 /* If we are inserting an 8-bytes aligned quantity and
7275 we have not already found an insertion point, then
7276 make sure that all such 8-byte aligned quantities are
7277 placed at the start of the pool. */
7278 else if (ARM_DOUBLEWORD_ALIGN
7280 && fix->fix_size == 8
7281 && mp->fix_size < 8)
7284 min_address = mp->min_address + fix->fix_size;
7289 /* We need to create a new entry. */
7290 mp = xmalloc (sizeof (* mp));
7291 mp->fix_size = fix->fix_size;
7292 mp->mode = fix->mode;
7293 mp->value = fix->value;
7295 mp->max_address = minipool_barrier->address + 65536;
7297 mp->min_address = min_address;
7302 mp->next = minipool_vector_head;
7304 if (mp->next == NULL)
7306 minipool_vector_tail = mp;
7307 minipool_vector_label = gen_label_rtx ();
7310 mp->next->prev = mp;
7312 minipool_vector_head = mp;
7316 mp->next = min_mp->next;
7320 if (mp->next != NULL)
7321 mp->next->prev = mp;
7323 minipool_vector_tail = mp;
7326 /* Save the new entry. */
7334 /* Scan over the following entries and adjust their offsets. */
7335 while (mp->next != NULL)
7337 if (mp->next->min_address < mp->min_address + mp->fix_size)
7338 mp->next->min_address = mp->min_address + mp->fix_size;
7341 mp->next->offset = mp->offset + mp->fix_size;
7343 mp->next->offset = mp->offset;
7352 assign_minipool_offsets (Mfix *barrier)
7354 HOST_WIDE_INT offset = 0;
7357 minipool_barrier = barrier;
7359 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7361 mp->offset = offset;
7363 if (mp->refcount > 0)
7364 offset += mp->fix_size;
7368 /* Output the literal table */
7370 dump_minipool (rtx scan)
7376 if (ARM_DOUBLEWORD_ALIGN)
7377 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7378 if (mp->refcount > 0 && mp->fix_size == 8)
7386 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7387 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7389 scan = emit_label_after (gen_label_rtx (), scan);
7390 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7391 scan = emit_label_after (minipool_vector_label, scan);
7393 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7395 if (mp->refcount > 0)
7400 ";; Offset %u, min %ld, max %ld ",
7401 (unsigned) mp->offset, (unsigned long) mp->min_address,
7402 (unsigned long) mp->max_address);
7403 arm_print_value (dump_file, mp->value);
7404 fputc ('\n', dump_file);
7407 switch (mp->fix_size)
7409 #ifdef HAVE_consttable_1
7411 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7415 #ifdef HAVE_consttable_2
7417 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7421 #ifdef HAVE_consttable_4
7423 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7427 #ifdef HAVE_consttable_8
7429 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7442 minipool_vector_head = minipool_vector_tail = NULL;
7443 scan = emit_insn_after (gen_consttable_end (), scan);
7444 scan = emit_barrier_after (scan);
7447 /* Return the cost of forcibly inserting a barrier after INSN. */
7449 arm_barrier_cost (rtx insn)
7451 /* Basing the location of the pool on the loop depth is preferable,
7452 but at the moment, the basic block information seems to be
7453 corrupt by this stage of the compilation. */
7455 rtx next = next_nonnote_insn (insn);
7457 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7460 switch (GET_CODE (insn))
7463 /* It will always be better to place the table before the label, rather
7472 return base_cost - 10;
7475 return base_cost + 10;
7479 /* Find the best place in the insn stream in the range
7480 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7481 Create the barrier by inserting a jump and add a new fix entry for
7484 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7486 HOST_WIDE_INT count = 0;
7488 rtx from = fix->insn;
7489 rtx selected = from;
7491 HOST_WIDE_INT selected_address;
7493 HOST_WIDE_INT max_count = max_address - fix->address;
7494 rtx label = gen_label_rtx ();
7496 selected_cost = arm_barrier_cost (from);
7497 selected_address = fix->address;
7499 while (from && count < max_count)
7504 /* This code shouldn't have been called if there was a natural barrier
7506 gcc_assert (GET_CODE (from) != BARRIER);
7508 /* Count the length of this insn. */
7509 count += get_attr_length (from);
7511 /* If there is a jump table, add its length. */
7512 tmp = is_jump_table (from);
7515 count += get_jump_table_size (tmp);
7517 /* Jump tables aren't in a basic block, so base the cost on
7518 the dispatch insn. If we select this location, we will
7519 still put the pool after the table. */
7520 new_cost = arm_barrier_cost (from);
7522 if (count < max_count && new_cost <= selected_cost)
7525 selected_cost = new_cost;
7526 selected_address = fix->address + count;
7529 /* Continue after the dispatch table. */
7530 from = NEXT_INSN (tmp);
7534 new_cost = arm_barrier_cost (from);
7536 if (count < max_count && new_cost <= selected_cost)
7539 selected_cost = new_cost;
7540 selected_address = fix->address + count;
7543 from = NEXT_INSN (from);
7546 /* Create a new JUMP_INSN that branches around a barrier. */
7547 from = emit_jump_insn_after (gen_jump (label), selected);
7548 JUMP_LABEL (from) = label;
7549 barrier = emit_barrier_after (from);
7550 emit_label_after (label, barrier);
7552 /* Create a minipool barrier entry for the new barrier. */
7553 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7554 new_fix->insn = barrier;
7555 new_fix->address = selected_address;
7556 new_fix->next = fix->next;
7557 fix->next = new_fix;
7562 /* Record that there is a natural barrier in the insn stream at
7565 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7567 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7570 fix->address = address;
7573 if (minipool_fix_head != NULL)
7574 minipool_fix_tail->next = fix;
7576 minipool_fix_head = fix;
7578 minipool_fix_tail = fix;
7581 /* Record INSN, which will need fixing up to load a value from the
7582 minipool. ADDRESS is the offset of the insn since the start of the
7583 function; LOC is a pointer to the part of the insn which requires
7584 fixing; VALUE is the constant that must be loaded, which is of type
7587 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7588 enum machine_mode mode, rtx value)
7590 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7592 #ifdef AOF_ASSEMBLER
7593 /* PIC symbol references need to be converted into offsets into the
7595 /* XXX This shouldn't be done here. */
7596 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7597 value = aof_pic_entry (value);
7598 #endif /* AOF_ASSEMBLER */
7601 fix->address = address;
7604 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7606 fix->forwards = get_attr_pool_range (insn);
7607 fix->backwards = get_attr_neg_pool_range (insn);
7608 fix->minipool = NULL;
7610 /* If an insn doesn't have a range defined for it, then it isn't
7611 expecting to be reworked by this code. Better to stop now than
7612 to generate duff assembly code. */
7613 gcc_assert (fix->forwards || fix->backwards);
7615 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7616 So there might be an empty word before the start of the pool.
7617 Hence we reduce the forward range by 4 to allow for this
7619 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7625 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7626 GET_MODE_NAME (mode),
7627 INSN_UID (insn), (unsigned long) address,
7628 -1 * (long)fix->backwards, (long)fix->forwards);
7629 arm_print_value (dump_file, fix->value);
7630 fprintf (dump_file, "\n");
7633 /* Add it to the chain of fixes. */
7636 if (minipool_fix_head != NULL)
7637 minipool_fix_tail->next = fix;
7639 minipool_fix_head = fix;
7641 minipool_fix_tail = fix;
7644 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7645 Returns the number of insns needed, or 99 if we don't know how to
7648 arm_const_double_inline_cost (rtx val)
7650 rtx lowpart, highpart;
7651 enum machine_mode mode;
7653 mode = GET_MODE (val);
7655 if (mode == VOIDmode)
7658 gcc_assert (GET_MODE_SIZE (mode) == 8);
7660 lowpart = gen_lowpart (SImode, val);
7661 highpart = gen_highpart_mode (SImode, mode, val);
7663 gcc_assert (GET_CODE (lowpart) == CONST_INT);
7664 gcc_assert (GET_CODE (highpart) == CONST_INT);
7666 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
7667 NULL_RTX, NULL_RTX, 0, 0)
7668 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
7669 NULL_RTX, NULL_RTX, 0, 0));
7672 /* Return true if it is worthwhile to split a 64-bit constant into two
7673 32-bit operations. This is the case if optimizing for size, or
7674 if we have load delay slots, or if one 32-bit part can be done with
7675 a single data operation. */
7677 arm_const_double_by_parts (rtx val)
7679 enum machine_mode mode = GET_MODE (val);
7682 if (optimize_size || arm_ld_sched)
7685 if (mode == VOIDmode)
7688 part = gen_highpart_mode (SImode, mode, val);
7690 gcc_assert (GET_CODE (part) == CONST_INT);
7692 if (const_ok_for_arm (INTVAL (part))
7693 || const_ok_for_arm (~INTVAL (part)))
7696 part = gen_lowpart (SImode, val);
7698 gcc_assert (GET_CODE (part) == CONST_INT);
7700 if (const_ok_for_arm (INTVAL (part))
7701 || const_ok_for_arm (~INTVAL (part)))
7707 /* Scan INSN and note any of its operands that need fixing.
7708 If DO_PUSHES is false we do not actually push any of the fixups
7709 needed. The function returns TRUE if any fixups were needed/pushed.
7710 This is used by arm_memory_load_p() which needs to know about loads
7711 of constants that will be converted into minipool loads. */
7713 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7715 bool result = false;
7718 extract_insn (insn);
7720 if (!constrain_operands (1))
7721 fatal_insn_not_found (insn);
7723 if (recog_data.n_alternatives == 0)
7726 /* Fill in recog_op_alt with information about the constraints of
7728 preprocess_constraints ();
7730 for (opno = 0; opno < recog_data.n_operands; opno++)
7732 /* Things we need to fix can only occur in inputs. */
7733 if (recog_data.operand_type[opno] != OP_IN)
7736 /* If this alternative is a memory reference, then any mention
7737 of constants in this alternative is really to fool reload
7738 into allowing us to accept one there. We need to fix them up
7739 now so that we output the right code. */
7740 if (recog_op_alt[opno][which_alternative].memory_ok)
7742 rtx op = recog_data.operand[opno];
7744 if (CONSTANT_P (op))
7747 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7748 recog_data.operand_mode[opno], op);
7751 else if (GET_CODE (op) == MEM
7752 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7753 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7757 rtx cop = avoid_constant_pool_reference (op);
7759 /* Casting the address of something to a mode narrower
7760 than a word can cause avoid_constant_pool_reference()
7761 to return the pool reference itself. That's no good to
7762 us here. Lets just hope that we can use the
7763 constant pool value directly. */
7765 cop = get_pool_constant (XEXP (op, 0));
7767 push_minipool_fix (insn, address,
7768 recog_data.operand_loc[opno],
7769 recog_data.operand_mode[opno], cop);
7780 /* Gcc puts the pool in the wrong place for ARM, since we can only
7781 load addresses a limited distance around the pc. We do some
7782 special munging to move the constant pool values to the correct
7783 point in the code. */
7788 HOST_WIDE_INT address = 0;
7791 minipool_fix_head = minipool_fix_tail = NULL;
7793 /* The first insn must always be a note, or the code below won't
7794 scan it properly. */
7795 insn = get_insns ();
7796 gcc_assert (GET_CODE (insn) == NOTE);
7798 /* Scan all the insns and record the operands that will need fixing. */
7799 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7801 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7802 && (arm_cirrus_insn_p (insn)
7803 || GET_CODE (insn) == JUMP_INSN
7804 || arm_memory_load_p (insn)))
7805 cirrus_reorg (insn);
7807 if (GET_CODE (insn) == BARRIER)
7808 push_minipool_barrier (insn, address);
7809 else if (INSN_P (insn))
7813 note_invalid_constants (insn, address, true);
7814 address += get_attr_length (insn);
7816 /* If the insn is a vector jump, add the size of the table
7817 and skip the table. */
7818 if ((table = is_jump_table (insn)) != NULL)
7820 address += get_jump_table_size (table);
7826 fix = minipool_fix_head;
7828 /* Now scan the fixups and perform the required changes. */
7833 Mfix * last_added_fix;
7834 Mfix * last_barrier = NULL;
7837 /* Skip any further barriers before the next fix. */
7838 while (fix && GET_CODE (fix->insn) == BARRIER)
7841 /* No more fixes. */
7845 last_added_fix = NULL;
7847 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7849 if (GET_CODE (ftmp->insn) == BARRIER)
7851 if (ftmp->address >= minipool_vector_head->max_address)
7854 last_barrier = ftmp;
7856 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7859 last_added_fix = ftmp; /* Keep track of the last fix added. */
7862 /* If we found a barrier, drop back to that; any fixes that we
7863 could have reached but come after the barrier will now go in
7864 the next mini-pool. */
7865 if (last_barrier != NULL)
7867 /* Reduce the refcount for those fixes that won't go into this
7869 for (fdel = last_barrier->next;
7870 fdel && fdel != ftmp;
7873 fdel->minipool->refcount--;
7874 fdel->minipool = NULL;
7877 ftmp = last_barrier;
7881 /* ftmp is first fix that we can't fit into this pool and
7882 there no natural barriers that we could use. Insert a
7883 new barrier in the code somewhere between the previous
7884 fix and this one, and arrange to jump around it. */
7885 HOST_WIDE_INT max_address;
7887 /* The last item on the list of fixes must be a barrier, so
7888 we can never run off the end of the list of fixes without
7889 last_barrier being set. */
7892 max_address = minipool_vector_head->max_address;
7893 /* Check that there isn't another fix that is in range that
7894 we couldn't fit into this pool because the pool was
7895 already too large: we need to put the pool before such an
7897 if (ftmp->address < max_address)
7898 max_address = ftmp->address;
7900 last_barrier = create_fix_barrier (last_added_fix, max_address);
7903 assign_minipool_offsets (last_barrier);
7907 if (GET_CODE (ftmp->insn) != BARRIER
7908 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7915 /* Scan over the fixes we have identified for this pool, fixing them
7916 up and adding the constants to the pool itself. */
7917 for (this_fix = fix; this_fix && ftmp != this_fix;
7918 this_fix = this_fix->next)
7919 if (GET_CODE (this_fix->insn) != BARRIER)
7922 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7923 minipool_vector_label),
7924 this_fix->minipool->offset);
7925 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7928 dump_minipool (last_barrier->insn);
7932 /* From now on we must synthesize any constants that we can't handle
7933 directly. This can happen if the RTL gets split during final
7934 instruction generation. */
7935 after_arm_reorg = 1;
7937 /* Free the minipool memory. */
7938 obstack_free (&minipool_obstack, minipool_startobj);
7941 /* Routines to output assembly language. */
7943 /* If the rtx is the correct value then return the string of the number.
7944 In this way we can ensure that valid double constants are generated even
7945 when cross compiling. */
7947 fp_immediate_constant (rtx x)
7952 if (!fp_consts_inited)
7955 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7956 for (i = 0; i < 8; i++)
7957 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7958 return strings_fp[i];
7963 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7965 fp_const_from_val (REAL_VALUE_TYPE *r)
7969 if (!fp_consts_inited)
7972 for (i = 0; i < 8; i++)
7973 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7974 return strings_fp[i];
7979 /* Output the operands of a LDM/STM instruction to STREAM.
7980 MASK is the ARM register set mask of which only bits 0-15 are important.
7981 REG is the base register, either the frame pointer or the stack pointer,
7982 INSTR is the possibly suffixed load or store instruction. */
7985 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
7989 bool not_first = FALSE;
7991 fputc ('\t', stream);
7992 asm_fprintf (stream, instr, reg);
7993 fputs (", {", stream);
7995 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7996 if (mask & (1 << i))
7999 fprintf (stream, ", ");
8001 asm_fprintf (stream, "%r", i);
8005 fprintf (stream, "}\n");
8009 /* Output a FLDMX instruction to STREAM.
8010 BASE if the register containing the address.
8011 REG and COUNT specify the register range.
8012 Extra registers may be added to avoid hardware bugs. */
8015 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8019 /* Workaround ARM10 VFPr1 bug. */
8020 if (count == 2 && !arm_arch6)
8027 fputc ('\t', stream);
8028 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8030 for (i = reg; i < reg + count; i++)
8033 fputs (", ", stream);
8034 asm_fprintf (stream, "d%d", i);
8036 fputs ("}\n", stream);
8041 /* Output the assembly for a store multiple. */
8044 vfp_output_fstmx (rtx * operands)
8051 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8052 p = strlen (pattern);
8054 gcc_assert (GET_CODE (operands[1]) == REG);
8056 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8057 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8059 p += sprintf (&pattern[p], ", d%d", base + i);
8061 strcpy (&pattern[p], "}");
8063 output_asm_insn (pattern, operands);
8068 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8069 number of bytes pushed. */
8072 vfp_emit_fstmx (int base_reg, int count)
8079 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8080 register pairs are stored by a store multiple insn. We avoid this
8081 by pushing an extra pair. */
8082 if (count == 2 && !arm_arch6)
8084 if (base_reg == LAST_VFP_REGNUM - 3)
8089 /* ??? The frame layout is implementation defined. We describe
8090 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8091 We really need some way of representing the whole block so that the
8092 unwinder can figure it out at runtime. */
8093 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8094 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8096 reg = gen_rtx_REG (DFmode, base_reg);
8100 = gen_rtx_SET (VOIDmode,
8101 gen_frame_mem (BLKmode,
8102 gen_rtx_PRE_DEC (BLKmode,
8103 stack_pointer_rtx)),
8104 gen_rtx_UNSPEC (BLKmode,
8108 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8109 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8110 GEN_INT (-(count * 8 + 4))));
8111 RTX_FRAME_RELATED_P (tmp) = 1;
8112 XVECEXP (dwarf, 0, 0) = tmp;
8114 tmp = gen_rtx_SET (VOIDmode,
8115 gen_frame_mem (DFmode, stack_pointer_rtx),
8117 RTX_FRAME_RELATED_P (tmp) = 1;
8118 XVECEXP (dwarf, 0, 1) = tmp;
8120 for (i = 1; i < count; i++)
8122 reg = gen_rtx_REG (DFmode, base_reg);
8124 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8126 tmp = gen_rtx_SET (VOIDmode,
8127 gen_frame_mem (DFmode,
8128 gen_rtx_PLUS (SImode,
8132 RTX_FRAME_RELATED_P (tmp) = 1;
8133 XVECEXP (dwarf, 0, i + 1) = tmp;
8136 par = emit_insn (par);
8137 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8139 RTX_FRAME_RELATED_P (par) = 1;
8141 return count * 8 + 4;
8145 /* Output a 'call' insn. */
8147 output_call (rtx *operands)
8149 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8151 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8152 if (REGNO (operands[0]) == LR_REGNUM)
8154 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8155 output_asm_insn ("mov%?\t%0, %|lr", operands);
8158 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8160 if (TARGET_INTERWORK || arm_arch4t)
8161 output_asm_insn ("bx%?\t%0", operands);
8163 output_asm_insn ("mov%?\t%|pc, %0", operands);
8168 /* Output a 'call' insn that is a reference in memory. */
8170 output_call_mem (rtx *operands)
8172 if (TARGET_INTERWORK && !arm_arch5)
8174 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8175 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8176 output_asm_insn ("bx%?\t%|ip", operands);
8178 else if (regno_use_in (LR_REGNUM, operands[0]))
8180 /* LR is used in the memory address. We load the address in the
8181 first instruction. It's safe to use IP as the target of the
8182 load since the call will kill it anyway. */
8183 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8185 output_asm_insn ("blx%?\t%|ip", operands);
8188 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8190 output_asm_insn ("bx%?\t%|ip", operands);
8192 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8197 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8198 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8205 /* Output a move from arm registers to an fpa registers.
8206 OPERANDS[0] is an fpa register.
8207 OPERANDS[1] is the first registers of an arm register pair. */
8209 output_mov_long_double_fpa_from_arm (rtx *operands)
8211 int arm_reg0 = REGNO (operands[1]);
8214 gcc_assert (arm_reg0 != IP_REGNUM);
8216 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8217 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8218 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8220 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8221 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8226 /* Output a move from an fpa register to arm registers.
8227 OPERANDS[0] is the first registers of an arm register pair.
8228 OPERANDS[1] is an fpa register. */
8230 output_mov_long_double_arm_from_fpa (rtx *operands)
8232 int arm_reg0 = REGNO (operands[0]);
8235 gcc_assert (arm_reg0 != IP_REGNUM);
8237 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8238 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8239 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8241 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8242 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8246 /* Output a move from arm registers to arm registers of a long double
8247 OPERANDS[0] is the destination.
8248 OPERANDS[1] is the source. */
8250 output_mov_long_double_arm_from_arm (rtx *operands)
8252 /* We have to be careful here because the two might overlap. */
8253 int dest_start = REGNO (operands[0]);
8254 int src_start = REGNO (operands[1]);
8258 if (dest_start < src_start)
8260 for (i = 0; i < 3; i++)
8262 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8263 ops[1] = gen_rtx_REG (SImode, src_start + i);
8264 output_asm_insn ("mov%?\t%0, %1", ops);
8269 for (i = 2; i >= 0; i--)
8271 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8272 ops[1] = gen_rtx_REG (SImode, src_start + i);
8273 output_asm_insn ("mov%?\t%0, %1", ops);
8281 /* Output a move from arm registers to an fpa registers.
8282 OPERANDS[0] is an fpa register.
8283 OPERANDS[1] is the first registers of an arm register pair. */
8285 output_mov_double_fpa_from_arm (rtx *operands)
8287 int arm_reg0 = REGNO (operands[1]);
8290 gcc_assert (arm_reg0 != IP_REGNUM);
8292 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8293 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8294 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8295 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8299 /* Output a move from an fpa register to arm registers.
8300 OPERANDS[0] is the first registers of an arm register pair.
8301 OPERANDS[1] is an fpa register. */
8303 output_mov_double_arm_from_fpa (rtx *operands)
8305 int arm_reg0 = REGNO (operands[0]);
8308 gcc_assert (arm_reg0 != IP_REGNUM);
8310 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8311 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8312 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8313 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8317 /* Output a move between double words.
8318 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8319 or MEM<-REG and all MEMs must be offsettable addresses. */
8321 output_move_double (rtx *operands)
8323 enum rtx_code code0 = GET_CODE (operands[0]);
8324 enum rtx_code code1 = GET_CODE (operands[1]);
8329 int reg0 = REGNO (operands[0]);
8331 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8333 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
8335 switch (GET_CODE (XEXP (operands[1], 0)))
8338 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8342 gcc_assert (TARGET_LDRD);
8343 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8347 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8351 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8355 gcc_assert (TARGET_LDRD);
8356 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8361 otherops[0] = operands[0];
8362 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8363 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8365 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8367 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8369 /* Registers overlap so split out the increment. */
8370 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8371 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8374 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8378 /* We only allow constant increments, so this is safe. */
8379 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8385 output_asm_insn ("adr%?\t%0, %1", operands);
8386 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8390 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8391 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8393 otherops[0] = operands[0];
8394 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8395 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8397 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8399 if (GET_CODE (otherops[2]) == CONST_INT)
8401 switch ((int) INTVAL (otherops[2]))
8404 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8407 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8410 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8415 && (GET_CODE (otherops[2]) == REG
8416 || (GET_CODE (otherops[2]) == CONST_INT
8417 && INTVAL (otherops[2]) > -256
8418 && INTVAL (otherops[2]) < 256)))
8420 if (reg_overlap_mentioned_p (otherops[0],
8423 /* Swap base and index registers over to
8424 avoid a conflict. */
8425 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8426 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8428 /* If both registers conflict, it will usually
8429 have been fixed by a splitter. */
8430 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8432 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8433 output_asm_insn ("ldr%?d\t%0, [%1]",
8437 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
8441 if (GET_CODE (otherops[2]) == CONST_INT)
8443 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8444 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8446 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8449 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8452 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8454 return "ldm%?ia\t%0, %M0";
8458 otherops[1] = adjust_address (operands[1], SImode, 4);
8459 /* Take care of overlapping base/data reg. */
8460 if (reg_mentioned_p (operands[0], operands[1]))
8462 output_asm_insn ("ldr%?\t%0, %1", otherops);
8463 output_asm_insn ("ldr%?\t%0, %1", operands);
8467 output_asm_insn ("ldr%?\t%0, %1", operands);
8468 output_asm_insn ("ldr%?\t%0, %1", otherops);
8475 /* Constraints should ensure this. */
8476 gcc_assert (code0 == MEM && code1 == REG);
8477 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
8479 switch (GET_CODE (XEXP (operands[0], 0)))
8482 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8486 gcc_assert (TARGET_LDRD);
8487 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8491 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8495 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8499 gcc_assert (TARGET_LDRD);
8500 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8505 otherops[0] = operands[1];
8506 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8507 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8509 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8510 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8512 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8516 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8517 if (GET_CODE (otherops[2]) == CONST_INT)
8519 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8522 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8526 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8530 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8535 && (GET_CODE (otherops[2]) == REG
8536 || (GET_CODE (otherops[2]) == CONST_INT
8537 && INTVAL (otherops[2]) > -256
8538 && INTVAL (otherops[2]) < 256)))
8540 otherops[0] = operands[1];
8541 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8542 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8548 otherops[0] = adjust_address (operands[0], SImode, 4);
8549 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8550 output_asm_insn ("str%?\t%1, %0", operands);
8551 output_asm_insn ("str%?\t%1, %0", otherops);
8558 /* Output an ADD r, s, #n where n may be too big for one instruction.
8559 If adding zero to one register, output nothing. */
8561 output_add_immediate (rtx *operands)
8563 HOST_WIDE_INT n = INTVAL (operands[2]);
8565 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8568 output_multi_immediate (operands,
8569 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8572 output_multi_immediate (operands,
8573 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8580 /* Output a multiple immediate operation.
8581 OPERANDS is the vector of operands referred to in the output patterns.
8582 INSTR1 is the output pattern to use for the first constant.
8583 INSTR2 is the output pattern to use for subsequent constants.
8584 IMMED_OP is the index of the constant slot in OPERANDS.
8585 N is the constant value. */
8587 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8588 int immed_op, HOST_WIDE_INT n)
8590 #if HOST_BITS_PER_WIDE_INT > 32
8596 /* Quick and easy output. */
8597 operands[immed_op] = const0_rtx;
8598 output_asm_insn (instr1, operands);
8603 const char * instr = instr1;
8605 /* Note that n is never zero here (which would give no output). */
8606 for (i = 0; i < 32; i += 2)
8610 operands[immed_op] = GEN_INT (n & (255 << i));
8611 output_asm_insn (instr, operands);
8621 /* Return the appropriate ARM instruction for the operation code.
8622 The returned result should not be overwritten. OP is the rtx of the
8623 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8626 arithmetic_instr (rtx op, int shift_first_arg)
8628 switch (GET_CODE (op))
8634 return shift_first_arg ? "rsb" : "sub";
8650 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8651 for the operation code. The returned result should not be overwritten.
8652 OP is the rtx code of the shift.
8653 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8656 shift_op (rtx op, HOST_WIDE_INT *amountp)
8659 enum rtx_code code = GET_CODE (op);
8661 switch (GET_CODE (XEXP (op, 1)))
8669 *amountp = INTVAL (XEXP (op, 1));
8691 gcc_assert (*amountp != -1);
8692 *amountp = 32 - *amountp;
8701 /* We never have to worry about the amount being other than a
8702 power of 2, since this case can never be reloaded from a reg. */
8703 gcc_assert (*amountp != -1);
8704 *amountp = int_log2 (*amountp);
8713 /* This is not 100% correct, but follows from the desire to merge
8714 multiplication by a power of 2 with the recognizer for a
8715 shift. >=32 is not a valid shift for "asl", so we must try and
8716 output a shift that produces the correct arithmetical result.
8717 Using lsr #32 is identical except for the fact that the carry bit
8718 is not set correctly if we set the flags; but we never use the
8719 carry bit from such an operation, so we can ignore that. */
8720 if (code == ROTATERT)
8721 /* Rotate is just modulo 32. */
8723 else if (*amountp != (*amountp & 31))
8730 /* Shifts of 0 are no-ops. */
8738 /* Obtain the shift from the POWER of two. */
8740 static HOST_WIDE_INT
8741 int_log2 (HOST_WIDE_INT power)
8743 HOST_WIDE_INT shift = 0;
8745 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8747 gcc_assert (shift <= 31);
8754 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8755 because /bin/as is horribly restrictive. The judgement about
8756 whether or not each character is 'printable' (and can be output as
8757 is) or not (and must be printed with an octal escape) must be made
8758 with reference to the *host* character set -- the situation is
8759 similar to that discussed in the comments above pp_c_char in
8760 c-pretty-print.c. */
8762 #define MAX_ASCII_LEN 51
8765 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8770 fputs ("\t.ascii\t\"", stream);
8772 for (i = 0; i < len; i++)
8776 if (len_so_far >= MAX_ASCII_LEN)
8778 fputs ("\"\n\t.ascii\t\"", stream);
8784 if (c == '\\' || c == '\"')
8786 putc ('\\', stream);
8794 fprintf (stream, "\\%03o", c);
8799 fputs ("\"\n", stream);
8802 /* Compute the register save mask for registers 0 through 12
8803 inclusive. This code is used by arm_compute_save_reg_mask. */
8805 static unsigned long
8806 arm_compute_save_reg0_reg12_mask (void)
8808 unsigned long func_type = arm_current_func_type ();
8809 unsigned long save_reg_mask = 0;
8812 if (IS_INTERRUPT (func_type))
8814 unsigned int max_reg;
8815 /* Interrupt functions must not corrupt any registers,
8816 even call clobbered ones. If this is a leaf function
8817 we can just examine the registers used by the RTL, but
8818 otherwise we have to assume that whatever function is
8819 called might clobber anything, and so we have to save
8820 all the call-clobbered registers as well. */
8821 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8822 /* FIQ handlers have registers r8 - r12 banked, so
8823 we only need to check r0 - r7, Normal ISRs only
8824 bank r14 and r15, so we must check up to r12.
8825 r13 is the stack pointer which is always preserved,
8826 so we do not need to consider it here. */
8831 for (reg = 0; reg <= max_reg; reg++)
8832 if (regs_ever_live[reg]
8833 || (! current_function_is_leaf && call_used_regs [reg]))
8834 save_reg_mask |= (1 << reg);
8836 /* Also save the pic base register if necessary. */
8838 && !TARGET_SINGLE_PIC_BASE
8839 && current_function_uses_pic_offset_table)
8840 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8844 /* In the normal case we only need to save those registers
8845 which are call saved and which are used by this function. */
8846 for (reg = 0; reg <= 10; reg++)
8847 if (regs_ever_live[reg] && ! call_used_regs [reg])
8848 save_reg_mask |= (1 << reg);
8850 /* Handle the frame pointer as a special case. */
8851 if (! TARGET_APCS_FRAME
8852 && ! frame_pointer_needed
8853 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8854 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8855 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8857 /* If we aren't loading the PIC register,
8858 don't stack it even though it may be live. */
8860 && !TARGET_SINGLE_PIC_BASE
8861 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
8862 || current_function_uses_pic_offset_table))
8863 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8866 /* Save registers so the exception handler can modify them. */
8867 if (current_function_calls_eh_return)
8873 reg = EH_RETURN_DATA_REGNO (i);
8874 if (reg == INVALID_REGNUM)
8876 save_reg_mask |= 1 << reg;
8880 return save_reg_mask;
8883 /* Compute a bit mask of which registers need to be
8884 saved on the stack for the current function. */
8886 static unsigned long
8887 arm_compute_save_reg_mask (void)
8889 unsigned int save_reg_mask = 0;
8890 unsigned long func_type = arm_current_func_type ();
8892 if (IS_NAKED (func_type))
8893 /* This should never really happen. */
8896 /* If we are creating a stack frame, then we must save the frame pointer,
8897 IP (which will hold the old stack pointer), LR and the PC. */
8898 if (frame_pointer_needed)
8900 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8905 /* Volatile functions do not return, so there
8906 is no need to save any other registers. */
8907 if (IS_VOLATILE (func_type))
8908 return save_reg_mask;
8910 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8912 /* Decide if we need to save the link register.
8913 Interrupt routines have their own banked link register,
8914 so they never need to save it.
8915 Otherwise if we do not use the link register we do not need to save
8916 it. If we are pushing other registers onto the stack however, we
8917 can save an instruction in the epilogue by pushing the link register
8918 now and then popping it back into the PC. This incurs extra memory
8919 accesses though, so we only do it when optimizing for size, and only
8920 if we know that we will not need a fancy return sequence. */
8921 if (regs_ever_live [LR_REGNUM]
8924 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8925 && !current_function_calls_eh_return))
8926 save_reg_mask |= 1 << LR_REGNUM;
8928 if (cfun->machine->lr_save_eliminated)
8929 save_reg_mask &= ~ (1 << LR_REGNUM);
8931 if (TARGET_REALLY_IWMMXT
8932 && ((bit_count (save_reg_mask)
8933 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8937 /* The total number of registers that are going to be pushed
8938 onto the stack is odd. We need to ensure that the stack
8939 is 64-bit aligned before we start to save iWMMXt registers,
8940 and also before we start to create locals. (A local variable
8941 might be a double or long long which we will load/store using
8942 an iWMMXt instruction). Therefore we need to push another
8943 ARM register, so that the stack will be 64-bit aligned. We
8944 try to avoid using the arg registers (r0 -r3) as they might be
8945 used to pass values in a tail call. */
8946 for (reg = 4; reg <= 12; reg++)
8947 if ((save_reg_mask & (1 << reg)) == 0)
8951 save_reg_mask |= (1 << reg);
8954 cfun->machine->sibcall_blocked = 1;
8955 save_reg_mask |= (1 << 3);
8959 return save_reg_mask;
8963 /* Compute a bit mask of which registers need to be
8964 saved on the stack for the current function. */
8965 static unsigned long
8966 thumb_compute_save_reg_mask (void)
8972 for (reg = 0; reg < 12; reg ++)
8973 if (regs_ever_live[reg] && !call_used_regs[reg])
8977 && !TARGET_SINGLE_PIC_BASE
8978 && current_function_uses_pic_offset_table)
8979 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8981 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8982 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
8983 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
8985 /* LR will also be pushed if any lo regs are pushed. */
8986 if (mask & 0xff || thumb_force_lr_save ())
8987 mask |= (1 << LR_REGNUM);
8989 /* Make sure we have a low work register if we need one.
8990 We will need one if we are going to push a high register,
8991 but we are not currently intending to push a low register. */
8992 if ((mask & 0xff) == 0
8993 && ((mask & 0x0f00) || TARGET_BACKTRACE))
8995 /* Use thumb_find_work_register to choose which register
8996 we will use. If the register is live then we will
8997 have to push it. Use LAST_LO_REGNUM as our fallback
8998 choice for the register to select. */
8999 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9001 if (! call_used_regs[reg])
9009 /* Return the number of bytes required to save VFP registers. */
9011 arm_get_vfp_saved_size (void)
9018 /* Space for saved VFP registers. */
9019 if (TARGET_HARD_FLOAT && TARGET_VFP)
9022 for (regno = FIRST_VFP_REGNUM;
9023 regno < LAST_VFP_REGNUM;
9026 if ((!regs_ever_live[regno] || call_used_regs[regno])
9027 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9031 /* Workaround ARM10 VFPr1 bug. */
9032 if (count == 2 && !arm_arch6)
9034 saved += count * 8 + 4;
9043 if (count == 2 && !arm_arch6)
9045 saved += count * 8 + 4;
9052 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9053 everything bar the final return instruction. */
9055 output_return_instruction (rtx operand, int really_return, int reverse)
9057 char conditional[10];
9060 unsigned long live_regs_mask;
9061 unsigned long func_type;
9062 arm_stack_offsets *offsets;
9064 func_type = arm_current_func_type ();
9066 if (IS_NAKED (func_type))
9069 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9071 /* If this function was declared non-returning, and we have
9072 found a tail call, then we have to trust that the called
9073 function won't return. */
9078 /* Otherwise, trap an attempted return by aborting. */
9080 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9082 assemble_external_libcall (ops[1]);
9083 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9089 gcc_assert (!current_function_calls_alloca || really_return);
9091 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9093 return_used_this_function = 1;
9095 live_regs_mask = arm_compute_save_reg_mask ();
9099 const char * return_reg;
9101 /* If we do not have any special requirements for function exit
9102 (e.g. interworking, or ISR) then we can load the return address
9103 directly into the PC. Otherwise we must load it into LR. */
9105 && ! TARGET_INTERWORK)
9106 return_reg = reg_names[PC_REGNUM];
9108 return_reg = reg_names[LR_REGNUM];
9110 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9112 /* There are three possible reasons for the IP register
9113 being saved. 1) a stack frame was created, in which case
9114 IP contains the old stack pointer, or 2) an ISR routine
9115 corrupted it, or 3) it was saved to align the stack on
9116 iWMMXt. In case 1, restore IP into SP, otherwise just
9118 if (frame_pointer_needed)
9120 live_regs_mask &= ~ (1 << IP_REGNUM);
9121 live_regs_mask |= (1 << SP_REGNUM);
9124 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
9127 /* On some ARM architectures it is faster to use LDR rather than
9128 LDM to load a single register. On other architectures, the
9129 cost is the same. In 26 bit mode, or for exception handlers,
9130 we have to use LDM to load the PC so that the CPSR is also
9132 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9133 if (live_regs_mask == (1U << reg))
9136 if (reg <= LAST_ARM_REGNUM
9137 && (reg != LR_REGNUM
9139 || ! IS_INTERRUPT (func_type)))
9141 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9142 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9149 /* Generate the load multiple instruction to restore the
9150 registers. Note we can get here, even if
9151 frame_pointer_needed is true, but only if sp already
9152 points to the base of the saved core registers. */
9153 if (live_regs_mask & (1 << SP_REGNUM))
9155 unsigned HOST_WIDE_INT stack_adjust;
9157 offsets = arm_get_frame_offsets ();
9158 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9159 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
9161 if (stack_adjust && arm_arch5)
9162 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9165 /* If we can't use ldmib (SA110 bug),
9166 then try to pop r3 instead. */
9168 live_regs_mask |= 1 << 3;
9169 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9173 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9175 p = instr + strlen (instr);
9177 for (reg = 0; reg <= SP_REGNUM; reg++)
9178 if (live_regs_mask & (1 << reg))
9180 int l = strlen (reg_names[reg]);
9186 memcpy (p, ", ", 2);
9190 memcpy (p, "%|", 2);
9191 memcpy (p + 2, reg_names[reg], l);
9195 if (live_regs_mask & (1 << LR_REGNUM))
9197 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9198 /* If returning from an interrupt, restore the CPSR. */
9199 if (IS_INTERRUPT (func_type))
9206 output_asm_insn (instr, & operand);
9208 /* See if we need to generate an extra instruction to
9209 perform the actual function return. */
9211 && func_type != ARM_FT_INTERWORKED
9212 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9214 /* The return has already been handled
9215 by loading the LR into the PC. */
9222 switch ((int) ARM_FUNC_TYPE (func_type))
9226 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9229 case ARM_FT_INTERWORKED:
9230 sprintf (instr, "bx%s\t%%|lr", conditional);
9233 case ARM_FT_EXCEPTION:
9234 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9238 /* Use bx if it's available. */
9239 if (arm_arch5 || arm_arch4t)
9240 sprintf (instr, "bx%s\t%%|lr", conditional);
9242 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9246 output_asm_insn (instr, & operand);
9252 /* Write the function name into the code section, directly preceding
9253 the function prologue.
9255 Code will be output similar to this:
9257 .ascii "arm_poke_function_name", 0
9260 .word 0xff000000 + (t1 - t0)
9261 arm_poke_function_name
9263 stmfd sp!, {fp, ip, lr, pc}
9266 When performing a stack backtrace, code can inspect the value
9267 of 'pc' stored at 'fp' + 0. If the trace function then looks
9268 at location pc - 12 and the top 8 bits are set, then we know
9269 that there is a function name embedded immediately preceding this
9270 location and has length ((pc[-3]) & 0xff000000).
9272 We assume that pc is declared as a pointer to an unsigned long.
9274 It is of no benefit to output the function name if we are assembling
9275 a leaf function. These function types will not contain a stack
9276 backtrace structure, therefore it is not possible to determine the
9279 arm_poke_function_name (FILE *stream, const char *name)
9281 unsigned long alignlength;
9282 unsigned long length;
9285 length = strlen (name) + 1;
9286 alignlength = ROUND_UP_WORD (length);
9288 ASM_OUTPUT_ASCII (stream, name, length);
9289 ASM_OUTPUT_ALIGN (stream, 2);
9290 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9291 assemble_aligned_integer (UNITS_PER_WORD, x);
9294 /* Place some comments into the assembler stream
9295 describing the current function. */
9297 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9299 unsigned long func_type;
9303 thumb_output_function_prologue (f, frame_size);
9308 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9310 func_type = arm_current_func_type ();
9312 switch ((int) ARM_FUNC_TYPE (func_type))
9317 case ARM_FT_INTERWORKED:
9318 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9321 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9324 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9326 case ARM_FT_EXCEPTION:
9327 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9331 if (IS_NAKED (func_type))
9332 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9334 if (IS_VOLATILE (func_type))
9335 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9337 if (IS_NESTED (func_type))
9338 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9340 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9341 current_function_args_size,
9342 current_function_pretend_args_size, frame_size);
9344 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9345 frame_pointer_needed,
9346 cfun->machine->uses_anonymous_args);
9348 if (cfun->machine->lr_save_eliminated)
9349 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9351 if (current_function_calls_eh_return)
9352 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9354 #ifdef AOF_ASSEMBLER
9356 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9359 return_used_this_function = 0;
9363 arm_output_epilogue (rtx sibling)
9366 unsigned long saved_regs_mask;
9367 unsigned long func_type;
9368 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9369 frame that is $fp + 4 for a non-variadic function. */
9370 int floats_offset = 0;
9372 FILE * f = asm_out_file;
9373 unsigned int lrm_count = 0;
9374 int really_return = (sibling == NULL);
9376 arm_stack_offsets *offsets;
9378 /* If we have already generated the return instruction
9379 then it is futile to generate anything else. */
9380 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9383 func_type = arm_current_func_type ();
9385 if (IS_NAKED (func_type))
9386 /* Naked functions don't have epilogues. */
9389 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9393 /* A volatile function should never return. Call abort. */
9394 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9395 assemble_external_libcall (op);
9396 output_asm_insn ("bl\t%a0", &op);
9401 /* If we are throwing an exception, then we really must be doing a
9402 return, so we can't tail-call. */
9403 gcc_assert (!current_function_calls_eh_return || really_return);
9405 offsets = arm_get_frame_offsets ();
9406 saved_regs_mask = arm_compute_save_reg_mask ();
9409 lrm_count = bit_count (saved_regs_mask);
9411 floats_offset = offsets->saved_args;
9412 /* Compute how far away the floats will be. */
9413 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9414 if (saved_regs_mask & (1 << reg))
9417 if (frame_pointer_needed)
9419 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9420 int vfp_offset = offsets->frame;
9422 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9424 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9425 if (regs_ever_live[reg] && !call_used_regs[reg])
9427 floats_offset += 12;
9428 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9429 reg, FP_REGNUM, floats_offset - vfp_offset);
9434 start_reg = LAST_FPA_REGNUM;
9436 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9438 if (regs_ever_live[reg] && !call_used_regs[reg])
9440 floats_offset += 12;
9442 /* We can't unstack more than four registers at once. */
9443 if (start_reg - reg == 3)
9445 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9446 reg, FP_REGNUM, floats_offset - vfp_offset);
9447 start_reg = reg - 1;
9452 if (reg != start_reg)
9453 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9454 reg + 1, start_reg - reg,
9455 FP_REGNUM, floats_offset - vfp_offset);
9456 start_reg = reg - 1;
9460 /* Just in case the last register checked also needs unstacking. */
9461 if (reg != start_reg)
9462 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9463 reg + 1, start_reg - reg,
9464 FP_REGNUM, floats_offset - vfp_offset);
9467 if (TARGET_HARD_FLOAT && TARGET_VFP)
9471 /* The fldmx insn does not have base+offset addressing modes,
9472 so we use IP to hold the address. */
9473 saved_size = arm_get_vfp_saved_size ();
9477 floats_offset += saved_size;
9478 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9479 FP_REGNUM, floats_offset - vfp_offset);
9481 start_reg = FIRST_VFP_REGNUM;
9482 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9484 if ((!regs_ever_live[reg] || call_used_regs[reg])
9485 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9487 if (start_reg != reg)
9488 arm_output_fldmx (f, IP_REGNUM,
9489 (start_reg - FIRST_VFP_REGNUM) / 2,
9490 (reg - start_reg) / 2);
9491 start_reg = reg + 2;
9494 if (start_reg != reg)
9495 arm_output_fldmx (f, IP_REGNUM,
9496 (start_reg - FIRST_VFP_REGNUM) / 2,
9497 (reg - start_reg) / 2);
9502 /* The frame pointer is guaranteed to be non-double-word aligned.
9503 This is because it is set to (old_stack_pointer - 4) and the
9504 old_stack_pointer was double word aligned. Thus the offset to
9505 the iWMMXt registers to be loaded must also be non-double-word
9506 sized, so that the resultant address *is* double-word aligned.
9507 We can ignore floats_offset since that was already included in
9508 the live_regs_mask. */
9509 lrm_count += (lrm_count % 2 ? 2 : 1);
9511 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9512 if (regs_ever_live[reg] && !call_used_regs[reg])
9514 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9515 reg, FP_REGNUM, lrm_count * 4);
9520 /* saved_regs_mask should contain the IP, which at the time of stack
9521 frame generation actually contains the old stack pointer. So a
9522 quick way to unwind the stack is just pop the IP register directly
9523 into the stack pointer. */
9524 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
9525 saved_regs_mask &= ~ (1 << IP_REGNUM);
9526 saved_regs_mask |= (1 << SP_REGNUM);
9528 /* There are two registers left in saved_regs_mask - LR and PC. We
9529 only need to restore the LR register (the return address), but to
9530 save time we can load it directly into the PC, unless we need a
9531 special function exit sequence, or we are not really returning. */
9533 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9534 && !current_function_calls_eh_return)
9535 /* Delete the LR from the register mask, so that the LR on
9536 the stack is loaded into the PC in the register mask. */
9537 saved_regs_mask &= ~ (1 << LR_REGNUM);
9539 saved_regs_mask &= ~ (1 << PC_REGNUM);
9541 /* We must use SP as the base register, because SP is one of the
9542 registers being restored. If an interrupt or page fault
9543 happens in the ldm instruction, the SP might or might not
9544 have been restored. That would be bad, as then SP will no
9545 longer indicate the safe area of stack, and we can get stack
9546 corruption. Using SP as the base register means that it will
9547 be reset correctly to the original value, should an interrupt
9548 occur. If the stack pointer already points at the right
9549 place, then omit the subtraction. */
9550 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9551 || current_function_calls_alloca)
9552 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9553 4 * bit_count (saved_regs_mask));
9554 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9556 if (IS_INTERRUPT (func_type))
9557 /* Interrupt handlers will have pushed the
9558 IP onto the stack, so restore it now. */
9559 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9563 /* Restore stack pointer if necessary. */
9564 if (offsets->outgoing_args != offsets->saved_regs)
9566 operands[0] = operands[1] = stack_pointer_rtx;
9567 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9568 output_add_immediate (operands);
9571 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9573 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9574 if (regs_ever_live[reg] && !call_used_regs[reg])
9575 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9580 start_reg = FIRST_FPA_REGNUM;
9582 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9584 if (regs_ever_live[reg] && !call_used_regs[reg])
9586 if (reg - start_reg == 3)
9588 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9589 start_reg, SP_REGNUM);
9590 start_reg = reg + 1;
9595 if (reg != start_reg)
9596 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9597 start_reg, reg - start_reg,
9600 start_reg = reg + 1;
9604 /* Just in case the last register checked also needs unstacking. */
9605 if (reg != start_reg)
9606 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9607 start_reg, reg - start_reg, SP_REGNUM);
9610 if (TARGET_HARD_FLOAT && TARGET_VFP)
9612 start_reg = FIRST_VFP_REGNUM;
9613 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9615 if ((!regs_ever_live[reg] || call_used_regs[reg])
9616 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9618 if (start_reg != reg)
9619 arm_output_fldmx (f, SP_REGNUM,
9620 (start_reg - FIRST_VFP_REGNUM) / 2,
9621 (reg - start_reg) / 2);
9622 start_reg = reg + 2;
9625 if (start_reg != reg)
9626 arm_output_fldmx (f, SP_REGNUM,
9627 (start_reg - FIRST_VFP_REGNUM) / 2,
9628 (reg - start_reg) / 2);
9631 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9632 if (regs_ever_live[reg] && !call_used_regs[reg])
9633 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9635 /* If we can, restore the LR into the PC. */
9636 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9638 && current_function_pretend_args_size == 0
9639 && saved_regs_mask & (1 << LR_REGNUM)
9640 && !current_function_calls_eh_return)
9642 saved_regs_mask &= ~ (1 << LR_REGNUM);
9643 saved_regs_mask |= (1 << PC_REGNUM);
9646 /* Load the registers off the stack. If we only have one register
9647 to load use the LDR instruction - it is faster. */
9648 if (saved_regs_mask == (1 << LR_REGNUM))
9650 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9652 else if (saved_regs_mask)
9654 if (saved_regs_mask & (1 << SP_REGNUM))
9655 /* Note - write back to the stack register is not enabled
9656 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9657 in the list of registers and if we add writeback the
9658 instruction becomes UNPREDICTABLE. */
9659 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9661 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9664 if (current_function_pretend_args_size)
9666 /* Unwind the pre-pushed regs. */
9667 operands[0] = operands[1] = stack_pointer_rtx;
9668 operands[2] = GEN_INT (current_function_pretend_args_size);
9669 output_add_immediate (operands);
9673 /* We may have already restored PC directly from the stack. */
9674 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9677 /* Stack adjustment for exception handler. */
9678 if (current_function_calls_eh_return)
9679 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9680 ARM_EH_STACKADJ_REGNUM);
9682 /* Generate the return instruction. */
9683 switch ((int) ARM_FUNC_TYPE (func_type))
9687 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9690 case ARM_FT_EXCEPTION:
9691 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9694 case ARM_FT_INTERWORKED:
9695 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9699 if (arm_arch5 || arm_arch4t)
9700 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9702 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9710 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9711 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9713 arm_stack_offsets *offsets;
9719 /* Emit any call-via-reg trampolines that are needed for v4t support
9720 of call_reg and call_value_reg type insns. */
9721 for (regno = 0; regno < LR_REGNUM; regno++)
9723 rtx label = cfun->machine->call_via[regno];
9727 function_section (current_function_decl);
9728 targetm.asm_out.internal_label (asm_out_file, "L",
9729 CODE_LABEL_NUMBER (label));
9730 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
9734 /* ??? Probably not safe to set this here, since it assumes that a
9735 function will be emitted as assembly immediately after we generate
9736 RTL for it. This does not happen for inline functions. */
9737 return_used_this_function = 0;
9741 /* We need to take into account any stack-frame rounding. */
9742 offsets = arm_get_frame_offsets ();
9744 gcc_assert (!use_return_insn (FALSE, NULL)
9745 || !return_used_this_function
9746 || offsets->saved_regs == offsets->outgoing_args
9747 || frame_pointer_needed);
9749 /* Reset the ARM-specific per-function variables. */
9750 after_arm_reorg = 0;
9754 /* Generate and emit an insn that we will recognize as a push_multi.
9755 Unfortunately, since this insn does not reflect very well the actual
9756 semantics of the operation, we need to annotate the insn for the benefit
9757 of DWARF2 frame unwind information. */
9759 emit_multi_reg_push (unsigned long mask)
9766 int dwarf_par_index;
9769 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9770 if (mask & (1 << i))
9773 gcc_assert (num_regs && num_regs <= 16);
9775 /* We don't record the PC in the dwarf frame information. */
9776 num_dwarf_regs = num_regs;
9777 if (mask & (1 << PC_REGNUM))
9780 /* For the body of the insn we are going to generate an UNSPEC in
9781 parallel with several USEs. This allows the insn to be recognized
9782 by the push_multi pattern in the arm.md file. The insn looks
9783 something like this:
9786 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9787 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9788 (use (reg:SI 11 fp))
9789 (use (reg:SI 12 ip))
9790 (use (reg:SI 14 lr))
9791 (use (reg:SI 15 pc))
9794 For the frame note however, we try to be more explicit and actually
9795 show each register being stored into the stack frame, plus a (single)
9796 decrement of the stack pointer. We do it this way in order to be
9797 friendly to the stack unwinding code, which only wants to see a single
9798 stack decrement per instruction. The RTL we generate for the note looks
9799 something like this:
9802 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9803 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9804 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9805 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9806 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9809 This sequence is used both by the code to support stack unwinding for
9810 exceptions handlers and the code to generate dwarf2 frame debugging. */
9812 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9813 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9814 dwarf_par_index = 1;
9816 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9818 if (mask & (1 << i))
9820 reg = gen_rtx_REG (SImode, i);
9823 = gen_rtx_SET (VOIDmode,
9824 gen_frame_mem (BLKmode,
9825 gen_rtx_PRE_DEC (BLKmode,
9826 stack_pointer_rtx)),
9827 gen_rtx_UNSPEC (BLKmode,
9833 tmp = gen_rtx_SET (VOIDmode,
9834 gen_frame_mem (SImode, stack_pointer_rtx),
9836 RTX_FRAME_RELATED_P (tmp) = 1;
9837 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9845 for (j = 1, i++; j < num_regs; i++)
9847 if (mask & (1 << i))
9849 reg = gen_rtx_REG (SImode, i);
9851 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9856 = gen_rtx_SET (VOIDmode,
9857 gen_frame_mem (SImode,
9858 plus_constant (stack_pointer_rtx,
9861 RTX_FRAME_RELATED_P (tmp) = 1;
9862 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9869 par = emit_insn (par);
9871 tmp = gen_rtx_SET (SImode,
9873 gen_rtx_PLUS (SImode,
9875 GEN_INT (-4 * num_regs)));
9876 RTX_FRAME_RELATED_P (tmp) = 1;
9877 XVECEXP (dwarf, 0, 0) = tmp;
9879 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9884 /* Calculate the size of the return value that is passed in registers. */
9886 arm_size_return_regs (void)
9888 enum machine_mode mode;
9890 if (current_function_return_rtx != 0)
9891 mode = GET_MODE (current_function_return_rtx);
9893 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9895 return GET_MODE_SIZE (mode);
9899 emit_sfm (int base_reg, int count)
9906 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9907 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9909 reg = gen_rtx_REG (XFmode, base_reg++);
9912 = gen_rtx_SET (VOIDmode,
9913 gen_frame_mem (BLKmode,
9914 gen_rtx_PRE_DEC (BLKmode,
9915 stack_pointer_rtx)),
9916 gen_rtx_UNSPEC (BLKmode,
9919 tmp = gen_rtx_SET (VOIDmode,
9920 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
9921 RTX_FRAME_RELATED_P (tmp) = 1;
9922 XVECEXP (dwarf, 0, 1) = tmp;
9924 for (i = 1; i < count; i++)
9926 reg = gen_rtx_REG (XFmode, base_reg++);
9927 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9929 tmp = gen_rtx_SET (VOIDmode,
9930 gen_frame_mem (XFmode,
9931 plus_constant (stack_pointer_rtx,
9934 RTX_FRAME_RELATED_P (tmp) = 1;
9935 XVECEXP (dwarf, 0, i + 1) = tmp;
9938 tmp = gen_rtx_SET (VOIDmode,
9940 gen_rtx_PLUS (SImode,
9942 GEN_INT (-12 * count)));
9943 RTX_FRAME_RELATED_P (tmp) = 1;
9944 XVECEXP (dwarf, 0, 0) = tmp;
9946 par = emit_insn (par);
9947 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9953 /* Return true if the current function needs to save/restore LR. */
9956 thumb_force_lr_save (void)
9958 return !cfun->machine->lr_save_eliminated
9959 && (!leaf_function_p ()
9960 || thumb_far_jump_used_p ()
9961 || regs_ever_live [LR_REGNUM]);
9965 /* Compute the distance from register FROM to register TO.
9966 These can be the arg pointer (26), the soft frame pointer (25),
9967 the stack pointer (13) or the hard frame pointer (11).
9968 In thumb mode r7 is used as the soft frame pointer, if needed.
9969 Typical stack layout looks like this:
9971 old stack pointer -> | |
9974 | | saved arguments for
9975 | | vararg functions
9978 hard FP & arg pointer -> | | \
9986 soft frame pointer -> | | /
9991 locals base pointer -> | | /
9996 current stack pointer -> | | /
9999 For a given function some or all of these stack components
10000 may not be needed, giving rise to the possibility of
10001 eliminating some of the registers.
10003 The values returned by this function must reflect the behavior
10004 of arm_expand_prologue() and arm_compute_save_reg_mask().
10006 The sign of the number returned reflects the direction of stack
10007 growth, so the values are positive for all eliminations except
10008 from the soft frame pointer to the hard frame pointer.
10010 SFP may point just inside the local variables block to ensure correct
10014 /* Calculate stack offsets. These are used to calculate register elimination
10015 offsets and in prologue/epilogue code. */
10017 static arm_stack_offsets *
10018 arm_get_frame_offsets (void)
10020 struct arm_stack_offsets *offsets;
10021 unsigned long func_type;
10024 HOST_WIDE_INT frame_size;
10026 offsets = &cfun->machine->stack_offsets;
10028 /* We need to know if we are a leaf function. Unfortunately, it
10029 is possible to be called after start_sequence has been called,
10030 which causes get_insns to return the insns for the sequence,
10031 not the function, which will cause leaf_function_p to return
10032 the incorrect result.
10034 to know about leaf functions once reload has completed, and the
10035 frame size cannot be changed after that time, so we can safely
10036 use the cached value. */
10038 if (reload_completed)
10041 /* Initially this is the size of the local variables. It will translated
10042 into an offset once we have determined the size of preceding data. */
10043 frame_size = ROUND_UP_WORD (get_frame_size ());
10045 leaf = leaf_function_p ();
10047 /* Space for variadic functions. */
10048 offsets->saved_args = current_function_pretend_args_size;
10050 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10054 unsigned int regno;
10056 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10058 /* We know that SP will be doubleword aligned on entry, and we must
10059 preserve that condition at any subroutine call. We also require the
10060 soft frame pointer to be doubleword aligned. */
10062 if (TARGET_REALLY_IWMMXT)
10064 /* Check for the call-saved iWMMXt registers. */
10065 for (regno = FIRST_IWMMXT_REGNUM;
10066 regno <= LAST_IWMMXT_REGNUM;
10068 if (regs_ever_live [regno] && ! call_used_regs [regno])
10072 func_type = arm_current_func_type ();
10073 if (! IS_VOLATILE (func_type))
10075 /* Space for saved FPA registers. */
10076 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10077 if (regs_ever_live[regno] && ! call_used_regs[regno])
10080 /* Space for saved VFP registers. */
10081 if (TARGET_HARD_FLOAT && TARGET_VFP)
10082 saved += arm_get_vfp_saved_size ();
10085 else /* TARGET_THUMB */
10087 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10088 if (TARGET_BACKTRACE)
10092 /* Saved registers include the stack frame. */
10093 offsets->saved_regs = offsets->saved_args + saved;
10094 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
10095 /* A leaf function does not need any stack alignment if it has nothing
10097 if (leaf && frame_size == 0)
10099 offsets->outgoing_args = offsets->soft_frame;
10103 /* Ensure SFP has the correct alignment. */
10104 if (ARM_DOUBLEWORD_ALIGN
10105 && (offsets->soft_frame & 7))
10106 offsets->soft_frame += 4;
10108 offsets->locals_base = offsets->soft_frame + frame_size;
10109 offsets->outgoing_args = (offsets->locals_base
10110 + current_function_outgoing_args_size);
10112 if (ARM_DOUBLEWORD_ALIGN)
10114 /* Ensure SP remains doubleword aligned. */
10115 if (offsets->outgoing_args & 7)
10116 offsets->outgoing_args += 4;
10117 gcc_assert (!(offsets->outgoing_args & 7));
10124 /* Calculate the relative offsets for the different stack pointers. Positive
10125 offsets are in the direction of stack growth. */
10128 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10130 arm_stack_offsets *offsets;
10132 offsets = arm_get_frame_offsets ();
10134 /* OK, now we have enough information to compute the distances.
10135 There must be an entry in these switch tables for each pair
10136 of registers in ELIMINABLE_REGS, even if some of the entries
10137 seem to be redundant or useless. */
10140 case ARG_POINTER_REGNUM:
10143 case THUMB_HARD_FRAME_POINTER_REGNUM:
10146 case FRAME_POINTER_REGNUM:
10147 /* This is the reverse of the soft frame pointer
10148 to hard frame pointer elimination below. */
10149 return offsets->soft_frame - offsets->saved_args;
10151 case ARM_HARD_FRAME_POINTER_REGNUM:
10152 /* If there is no stack frame then the hard
10153 frame pointer and the arg pointer coincide. */
10154 if (offsets->frame == offsets->saved_regs)
10156 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10157 return (frame_pointer_needed
10158 && cfun->static_chain_decl != NULL
10159 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10161 case STACK_POINTER_REGNUM:
10162 /* If nothing has been pushed on the stack at all
10163 then this will return -4. This *is* correct! */
10164 return offsets->outgoing_args - (offsets->saved_args + 4);
10167 gcc_unreachable ();
10169 gcc_unreachable ();
10171 case FRAME_POINTER_REGNUM:
10174 case THUMB_HARD_FRAME_POINTER_REGNUM:
10177 case ARM_HARD_FRAME_POINTER_REGNUM:
10178 /* The hard frame pointer points to the top entry in the
10179 stack frame. The soft frame pointer to the bottom entry
10180 in the stack frame. If there is no stack frame at all,
10181 then they are identical. */
10183 return offsets->frame - offsets->soft_frame;
10185 case STACK_POINTER_REGNUM:
10186 return offsets->outgoing_args - offsets->soft_frame;
10189 gcc_unreachable ();
10191 gcc_unreachable ();
10194 /* You cannot eliminate from the stack pointer.
10195 In theory you could eliminate from the hard frame
10196 pointer to the stack pointer, but this will never
10197 happen, since if a stack frame is not needed the
10198 hard frame pointer will never be used. */
10199 gcc_unreachable ();
10204 /* Generate the prologue instructions for entry into an ARM function. */
10206 arm_expand_prologue (void)
10212 unsigned long live_regs_mask;
10213 unsigned long func_type;
10215 int saved_pretend_args = 0;
10216 int saved_regs = 0;
10217 unsigned HOST_WIDE_INT args_to_push;
10218 arm_stack_offsets *offsets;
10220 func_type = arm_current_func_type ();
10222 /* Naked functions don't have prologues. */
10223 if (IS_NAKED (func_type))
10226 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10227 args_to_push = current_function_pretend_args_size;
10229 /* Compute which register we will have to save onto the stack. */
10230 live_regs_mask = arm_compute_save_reg_mask ();
10232 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10234 if (frame_pointer_needed)
10236 if (IS_INTERRUPT (func_type))
10238 /* Interrupt functions must not corrupt any registers.
10239 Creating a frame pointer however, corrupts the IP
10240 register, so we must push it first. */
10241 insn = emit_multi_reg_push (1 << IP_REGNUM);
10243 /* Do not set RTX_FRAME_RELATED_P on this insn.
10244 The dwarf stack unwinding code only wants to see one
10245 stack decrement per function, and this is not it. If
10246 this instruction is labeled as being part of the frame
10247 creation sequence then dwarf2out_frame_debug_expr will
10248 die when it encounters the assignment of IP to FP
10249 later on, since the use of SP here establishes SP as
10250 the CFA register and not IP.
10252 Anyway this instruction is not really part of the stack
10253 frame creation although it is part of the prologue. */
10255 else if (IS_NESTED (func_type))
10257 /* The Static chain register is the same as the IP register
10258 used as a scratch register during stack frame creation.
10259 To get around this need to find somewhere to store IP
10260 whilst the frame is being created. We try the following
10263 1. The last argument register.
10264 2. A slot on the stack above the frame. (This only
10265 works if the function is not a varargs function).
10266 3. Register r3, after pushing the argument registers
10269 Note - we only need to tell the dwarf2 backend about the SP
10270 adjustment in the second variant; the static chain register
10271 doesn't need to be unwound, as it doesn't contain a value
10272 inherited from the caller. */
10274 if (regs_ever_live[3] == 0)
10276 insn = gen_rtx_REG (SImode, 3);
10277 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10278 insn = emit_insn (insn);
10280 else if (args_to_push == 0)
10283 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10284 insn = gen_frame_mem (SImode, insn);
10285 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10286 insn = emit_insn (insn);
10290 /* Just tell the dwarf backend that we adjusted SP. */
10291 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10292 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10293 GEN_INT (-fp_offset)));
10294 RTX_FRAME_RELATED_P (insn) = 1;
10295 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10296 dwarf, REG_NOTES (insn));
10300 /* Store the args on the stack. */
10301 if (cfun->machine->uses_anonymous_args)
10302 insn = emit_multi_reg_push
10303 ((0xf0 >> (args_to_push / 4)) & 0xf);
10306 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10307 GEN_INT (- args_to_push)));
10309 RTX_FRAME_RELATED_P (insn) = 1;
10311 saved_pretend_args = 1;
10312 fp_offset = args_to_push;
10315 /* Now reuse r3 to preserve IP. */
10316 insn = gen_rtx_REG (SImode, 3);
10317 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10318 (void) emit_insn (insn);
10324 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10325 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10328 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10330 insn = emit_insn (insn);
10331 RTX_FRAME_RELATED_P (insn) = 1;
10336 /* Push the argument registers, or reserve space for them. */
10337 if (cfun->machine->uses_anonymous_args)
10338 insn = emit_multi_reg_push
10339 ((0xf0 >> (args_to_push / 4)) & 0xf);
10342 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10343 GEN_INT (- args_to_push)));
10344 RTX_FRAME_RELATED_P (insn) = 1;
10347 /* If this is an interrupt service routine, and the link register
10348 is going to be pushed, and we are not creating a stack frame,
10349 (which would involve an extra push of IP and a pop in the epilogue)
10350 subtracting four from LR now will mean that the function return
10351 can be done with a single instruction. */
10352 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10353 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10354 && ! frame_pointer_needed)
10355 emit_insn (gen_rtx_SET (SImode,
10356 gen_rtx_REG (SImode, LR_REGNUM),
10357 gen_rtx_PLUS (SImode,
10358 gen_rtx_REG (SImode, LR_REGNUM),
10361 if (live_regs_mask)
10363 insn = emit_multi_reg_push (live_regs_mask);
10364 saved_regs += bit_count (live_regs_mask) * 4;
10365 RTX_FRAME_RELATED_P (insn) = 1;
10369 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10370 if (regs_ever_live[reg] && ! call_used_regs [reg])
10372 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10373 insn = gen_frame_mem (V2SImode, insn);
10374 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10375 gen_rtx_REG (V2SImode, reg)));
10376 RTX_FRAME_RELATED_P (insn) = 1;
10380 if (! IS_VOLATILE (func_type))
10384 /* Save any floating point call-saved registers used by this
10386 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10388 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10389 if (regs_ever_live[reg] && !call_used_regs[reg])
10391 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10392 insn = gen_frame_mem (XFmode, insn);
10393 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10394 gen_rtx_REG (XFmode, reg)));
10395 RTX_FRAME_RELATED_P (insn) = 1;
10401 start_reg = LAST_FPA_REGNUM;
10403 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10405 if (regs_ever_live[reg] && !call_used_regs[reg])
10407 if (start_reg - reg == 3)
10409 insn = emit_sfm (reg, 4);
10410 RTX_FRAME_RELATED_P (insn) = 1;
10412 start_reg = reg - 1;
10417 if (start_reg != reg)
10419 insn = emit_sfm (reg + 1, start_reg - reg);
10420 RTX_FRAME_RELATED_P (insn) = 1;
10421 saved_regs += (start_reg - reg) * 12;
10423 start_reg = reg - 1;
10427 if (start_reg != reg)
10429 insn = emit_sfm (reg + 1, start_reg - reg);
10430 saved_regs += (start_reg - reg) * 12;
10431 RTX_FRAME_RELATED_P (insn) = 1;
10434 if (TARGET_HARD_FLOAT && TARGET_VFP)
10436 start_reg = FIRST_VFP_REGNUM;
10438 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10440 if ((!regs_ever_live[reg] || call_used_regs[reg])
10441 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10443 if (start_reg != reg)
10444 saved_regs += vfp_emit_fstmx (start_reg,
10445 (reg - start_reg) / 2);
10446 start_reg = reg + 2;
10449 if (start_reg != reg)
10450 saved_regs += vfp_emit_fstmx (start_reg,
10451 (reg - start_reg) / 2);
10455 if (frame_pointer_needed)
10457 /* Create the new frame pointer. */
10458 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10459 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10460 RTX_FRAME_RELATED_P (insn) = 1;
10462 if (IS_NESTED (func_type))
10464 /* Recover the static chain register. */
10465 if (regs_ever_live [3] == 0
10466 || saved_pretend_args)
10467 insn = gen_rtx_REG (SImode, 3);
10468 else /* if (current_function_pretend_args_size == 0) */
10470 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10472 insn = gen_frame_mem (SImode, insn);
10475 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10476 /* Add a USE to stop propagate_one_insn() from barfing. */
10477 emit_insn (gen_prologue_use (ip_rtx));
10481 offsets = arm_get_frame_offsets ();
10482 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10484 /* This add can produce multiple insns for a large constant, so we
10485 need to get tricky. */
10486 rtx last = get_last_insn ();
10488 amount = GEN_INT (offsets->saved_args + saved_regs
10489 - offsets->outgoing_args);
10491 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10495 last = last ? NEXT_INSN (last) : get_insns ();
10496 RTX_FRAME_RELATED_P (last) = 1;
10498 while (last != insn);
10500 /* If the frame pointer is needed, emit a special barrier that
10501 will prevent the scheduler from moving stores to the frame
10502 before the stack adjustment. */
10503 if (frame_pointer_needed)
10504 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10505 hard_frame_pointer_rtx));
10510 arm_load_pic_register (0UL);
10512 /* If we are profiling, make sure no instructions are scheduled before
10513 the call to mcount. Similarly if the user has requested no
10514 scheduling in the prolog. */
10515 if (current_function_profile || !TARGET_SCHED_PROLOG)
10516 emit_insn (gen_blockage ());
10518 /* If the link register is being kept alive, with the return address in it,
10519 then make sure that it does not get reused by the ce2 pass. */
10520 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10522 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10523 cfun->machine->lr_save_eliminated = 1;
10527 /* If CODE is 'd', then the X is a condition operand and the instruction
10528 should only be executed if the condition is true.
10529 if CODE is 'D', then the X is a condition operand and the instruction
10530 should only be executed if the condition is false: however, if the mode
10531 of the comparison is CCFPEmode, then always execute the instruction -- we
10532 do this because in these circumstances !GE does not necessarily imply LT;
10533 in these cases the instruction pattern will take care to make sure that
10534 an instruction containing %d will follow, thereby undoing the effects of
10535 doing this instruction unconditionally.
10536 If CODE is 'N' then X is a floating point operand that must be negated
10538 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10539 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10541 arm_print_operand (FILE *stream, rtx x, int code)
10546 fputs (ASM_COMMENT_START, stream);
10550 fputs (user_label_prefix, stream);
10554 fputs (REGISTER_PREFIX, stream);
10558 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10562 output_operand_lossage ("predicated Thumb instruction");
10565 if (current_insn_predicate != NULL)
10567 output_operand_lossage
10568 ("predicated instruction in conditional sequence");
10572 fputs (arm_condition_codes[arm_current_cc], stream);
10574 else if (current_insn_predicate)
10576 enum arm_cond_code code;
10580 output_operand_lossage ("predicated Thumb instruction");
10584 code = get_arm_condition_code (current_insn_predicate);
10585 fputs (arm_condition_codes[code], stream);
10592 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10593 r = REAL_VALUE_NEGATE (r);
10594 fprintf (stream, "%s", fp_const_from_val (&r));
10599 if (GET_CODE (x) == CONST_INT)
10602 val = ARM_SIGN_EXTEND (~INTVAL (x));
10603 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10607 putc ('~', stream);
10608 output_addr_const (stream, x);
10613 fprintf (stream, "%s", arithmetic_instr (x, 1));
10616 /* Truncate Cirrus shift counts. */
10618 if (GET_CODE (x) == CONST_INT)
10620 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10623 arm_print_operand (stream, x, 0);
10627 fprintf (stream, "%s", arithmetic_instr (x, 0));
10633 const char * shift = shift_op (x, &val);
10637 fprintf (stream, ", %s ", shift_op (x, &val));
10639 arm_print_operand (stream, XEXP (x, 1), 0);
10641 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10646 /* An explanation of the 'Q', 'R' and 'H' register operands:
10648 In a pair of registers containing a DI or DF value the 'Q'
10649 operand returns the register number of the register containing
10650 the least significant part of the value. The 'R' operand returns
10651 the register number of the register containing the most
10652 significant part of the value.
10654 The 'H' operand returns the higher of the two register numbers.
10655 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10656 same as the 'Q' operand, since the most significant part of the
10657 value is held in the lower number register. The reverse is true
10658 on systems where WORDS_BIG_ENDIAN is false.
10660 The purpose of these operands is to distinguish between cases
10661 where the endian-ness of the values is important (for example
10662 when they are added together), and cases where the endian-ness
10663 is irrelevant, but the order of register operations is important.
10664 For example when loading a value from memory into a register
10665 pair, the endian-ness does not matter. Provided that the value
10666 from the lower memory address is put into the lower numbered
10667 register, and the value from the higher address is put into the
10668 higher numbered register, the load will work regardless of whether
10669 the value being loaded is big-wordian or little-wordian. The
10670 order of the two register loads can matter however, if the address
10671 of the memory location is actually held in one of the registers
10672 being overwritten by the load. */
10674 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10676 output_operand_lossage ("invalid operand for code '%c'", code);
10680 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10684 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10686 output_operand_lossage ("invalid operand for code '%c'", code);
10690 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10694 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10696 output_operand_lossage ("invalid operand for code '%c'", code);
10700 asm_fprintf (stream, "%r", REGNO (x) + 1);
10704 asm_fprintf (stream, "%r",
10705 GET_CODE (XEXP (x, 0)) == REG
10706 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10710 asm_fprintf (stream, "{%r-%r}",
10712 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10716 /* CONST_TRUE_RTX means always -- that's the default. */
10717 if (x == const_true_rtx)
10720 if (!COMPARISON_P (x))
10722 output_operand_lossage ("invalid operand for code '%c'", code);
10726 fputs (arm_condition_codes[get_arm_condition_code (x)],
10731 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10732 want to do that. */
10733 if (x == const_true_rtx)
10735 output_operand_lossage ("instruction never exectued");
10738 if (!COMPARISON_P (x))
10740 output_operand_lossage ("invalid operand for code '%c'", code);
10744 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10745 (get_arm_condition_code (x))],
10749 /* Cirrus registers can be accessed in a variety of ways:
10750 single floating point (f)
10751 double floating point (d)
10753 64bit integer (dx). */
10754 case 'W': /* Cirrus register in F mode. */
10755 case 'X': /* Cirrus register in D mode. */
10756 case 'Y': /* Cirrus register in FX mode. */
10757 case 'Z': /* Cirrus register in DX mode. */
10758 gcc_assert (GET_CODE (x) == REG
10759 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
10761 fprintf (stream, "mv%s%s",
10763 : code == 'X' ? "d"
10764 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10768 /* Print cirrus register in the mode specified by the register's mode. */
10771 int mode = GET_MODE (x);
10773 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10775 output_operand_lossage ("invalid operand for code '%c'", code);
10779 fprintf (stream, "mv%s%s",
10780 mode == DFmode ? "d"
10781 : mode == SImode ? "fx"
10782 : mode == DImode ? "dx"
10783 : "f", reg_names[REGNO (x)] + 2);
10789 if (GET_CODE (x) != REG
10790 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10791 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10792 /* Bad value for wCG register number. */
10794 output_operand_lossage ("invalid operand for code '%c'", code);
10799 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10802 /* Print an iWMMXt control register name. */
10804 if (GET_CODE (x) != CONST_INT
10806 || INTVAL (x) >= 16)
10807 /* Bad value for wC register number. */
10809 output_operand_lossage ("invalid operand for code '%c'", code);
10815 static const char * wc_reg_names [16] =
10817 "wCID", "wCon", "wCSSF", "wCASF",
10818 "wC4", "wC5", "wC6", "wC7",
10819 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10820 "wC12", "wC13", "wC14", "wC15"
10823 fprintf (stream, wc_reg_names [INTVAL (x)]);
10827 /* Print a VFP double precision register name. */
10830 int mode = GET_MODE (x);
10833 if (mode != DImode && mode != DFmode)
10835 output_operand_lossage ("invalid operand for code '%c'", code);
10839 if (GET_CODE (x) != REG
10840 || !IS_VFP_REGNUM (REGNO (x)))
10842 output_operand_lossage ("invalid operand for code '%c'", code);
10846 num = REGNO(x) - FIRST_VFP_REGNUM;
10849 output_operand_lossage ("invalid operand for code '%c'", code);
10853 fprintf (stream, "d%d", num >> 1);
10860 output_operand_lossage ("missing operand");
10864 switch (GET_CODE (x))
10867 asm_fprintf (stream, "%r", REGNO (x));
10871 output_memory_reference_mode = GET_MODE (x);
10872 output_address (XEXP (x, 0));
10876 fprintf (stream, "#%s", fp_immediate_constant (x));
10880 gcc_assert (GET_CODE (x) != NEG);
10881 fputc ('#', stream);
10882 output_addr_const (stream, x);
10888 #ifndef AOF_ASSEMBLER
10889 /* Target hook for assembling integer objects. The ARM version needs to
10890 handle word-sized values specially. */
10892 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10894 if (size == UNITS_PER_WORD && aligned_p)
10896 fputs ("\t.word\t", asm_out_file);
10897 output_addr_const (asm_out_file, x);
10899 /* Mark symbols as position independent. We only do this in the
10900 .text segment, not in the .data segment. */
10901 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10902 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10904 if (GET_CODE (x) == SYMBOL_REF
10905 && (CONSTANT_POOL_ADDRESS_P (x)
10906 || SYMBOL_REF_LOCAL_P (x)))
10907 fputs ("(GOTOFF)", asm_out_file);
10908 else if (GET_CODE (x) == LABEL_REF)
10909 fputs ("(GOTOFF)", asm_out_file);
10911 fputs ("(GOT)", asm_out_file);
10913 fputc ('\n', asm_out_file);
10917 if (arm_vector_mode_supported_p (GET_MODE (x)))
10921 gcc_assert (GET_CODE (x) == CONST_VECTOR);
10923 units = CONST_VECTOR_NUNITS (x);
10925 switch (GET_MODE (x))
10927 case V2SImode: size = 4; break;
10928 case V4HImode: size = 2; break;
10929 case V8QImode: size = 1; break;
10931 gcc_unreachable ();
10934 for (i = 0; i < units; i++)
10938 elt = CONST_VECTOR_ELT (x, i);
10940 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10946 return default_assemble_integer (x, size, aligned_p);
10950 /* Add a function to the list of static constructors. */
10953 arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10955 if (!TARGET_AAPCS_BASED)
10957 default_named_section_asm_out_constructor (symbol, priority);
10961 /* Put these in the .init_array section, using a special relocation. */
10963 assemble_align (POINTER_SIZE);
10964 fputs ("\t.word\t", asm_out_file);
10965 output_addr_const (asm_out_file, symbol);
10966 fputs ("(target1)\n", asm_out_file);
10970 /* A finite state machine takes care of noticing whether or not instructions
10971 can be conditionally executed, and thus decrease execution time and code
10972 size by deleting branch instructions. The fsm is controlled by
10973 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10975 /* The state of the fsm controlling condition codes are:
10976 0: normal, do nothing special
10977 1: make ASM_OUTPUT_OPCODE not output this instruction
10978 2: make ASM_OUTPUT_OPCODE not output this instruction
10979 3: make instructions conditional
10980 4: make instructions conditional
10982 State transitions (state->state by whom under condition):
10983 0 -> 1 final_prescan_insn if the `target' is a label
10984 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10985 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10986 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10987 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10988 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10989 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10990 (the target insn is arm_target_insn).
10992 If the jump clobbers the conditions then we use states 2 and 4.
10994 A similar thing can be done with conditional return insns.
10996 XXX In case the `target' is an unconditional branch, this conditionalising
10997 of the instructions always reduces code size, but not always execution
10998 time. But then, I want to reduce the code size to somewhere near what
10999 /bin/cc produces. */
11001 /* Returns the index of the ARM condition code string in
11002 `arm_condition_codes'. COMPARISON should be an rtx like
11003 `(eq (...) (...))'. */
11004 static enum arm_cond_code
11005 get_arm_condition_code (rtx comparison)
11007 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11009 enum rtx_code comp_code = GET_CODE (comparison);
11011 if (GET_MODE_CLASS (mode) != MODE_CC)
11012 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11013 XEXP (comparison, 1));
11017 case CC_DNEmode: code = ARM_NE; goto dominance;
11018 case CC_DEQmode: code = ARM_EQ; goto dominance;
11019 case CC_DGEmode: code = ARM_GE; goto dominance;
11020 case CC_DGTmode: code = ARM_GT; goto dominance;
11021 case CC_DLEmode: code = ARM_LE; goto dominance;
11022 case CC_DLTmode: code = ARM_LT; goto dominance;
11023 case CC_DGEUmode: code = ARM_CS; goto dominance;
11024 case CC_DGTUmode: code = ARM_HI; goto dominance;
11025 case CC_DLEUmode: code = ARM_LS; goto dominance;
11026 case CC_DLTUmode: code = ARM_CC;
11029 gcc_assert (comp_code == EQ || comp_code == NE);
11031 if (comp_code == EQ)
11032 return ARM_INVERSE_CONDITION_CODE (code);
11038 case NE: return ARM_NE;
11039 case EQ: return ARM_EQ;
11040 case GE: return ARM_PL;
11041 case LT: return ARM_MI;
11042 default: gcc_unreachable ();
11048 case NE: return ARM_NE;
11049 case EQ: return ARM_EQ;
11050 default: gcc_unreachable ();
11056 case NE: return ARM_MI;
11057 case EQ: return ARM_PL;
11058 default: gcc_unreachable ();
11063 /* These encodings assume that AC=1 in the FPA system control
11064 byte. This allows us to handle all cases except UNEQ and
11068 case GE: return ARM_GE;
11069 case GT: return ARM_GT;
11070 case LE: return ARM_LS;
11071 case LT: return ARM_MI;
11072 case NE: return ARM_NE;
11073 case EQ: return ARM_EQ;
11074 case ORDERED: return ARM_VC;
11075 case UNORDERED: return ARM_VS;
11076 case UNLT: return ARM_LT;
11077 case UNLE: return ARM_LE;
11078 case UNGT: return ARM_HI;
11079 case UNGE: return ARM_PL;
11080 /* UNEQ and LTGT do not have a representation. */
11081 case UNEQ: /* Fall through. */
11082 case LTGT: /* Fall through. */
11083 default: gcc_unreachable ();
11089 case NE: return ARM_NE;
11090 case EQ: return ARM_EQ;
11091 case GE: return ARM_LE;
11092 case GT: return ARM_LT;
11093 case LE: return ARM_GE;
11094 case LT: return ARM_GT;
11095 case GEU: return ARM_LS;
11096 case GTU: return ARM_CC;
11097 case LEU: return ARM_CS;
11098 case LTU: return ARM_HI;
11099 default: gcc_unreachable ();
11105 case LTU: return ARM_CS;
11106 case GEU: return ARM_CC;
11107 default: gcc_unreachable ();
11113 case NE: return ARM_NE;
11114 case EQ: return ARM_EQ;
11115 case GE: return ARM_GE;
11116 case GT: return ARM_GT;
11117 case LE: return ARM_LE;
11118 case LT: return ARM_LT;
11119 case GEU: return ARM_CS;
11120 case GTU: return ARM_HI;
11121 case LEU: return ARM_LS;
11122 case LTU: return ARM_CC;
11123 default: gcc_unreachable ();
11126 default: gcc_unreachable ();
11131 arm_final_prescan_insn (rtx insn)
11133 /* BODY will hold the body of INSN. */
11134 rtx body = PATTERN (insn);
11136 /* This will be 1 if trying to repeat the trick, and things need to be
11137 reversed if it appears to fail. */
11140 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11141 taken are clobbered, even if the rtl suggests otherwise. It also
11142 means that we have to grub around within the jump expression to find
11143 out what the conditions are when the jump isn't taken. */
11144 int jump_clobbers = 0;
11146 /* If we start with a return insn, we only succeed if we find another one. */
11147 int seeking_return = 0;
11149 /* START_INSN will hold the insn from where we start looking. This is the
11150 first insn after the following code_label if REVERSE is true. */
11151 rtx start_insn = insn;
11153 /* If in state 4, check if the target branch is reached, in order to
11154 change back to state 0. */
11155 if (arm_ccfsm_state == 4)
11157 if (insn == arm_target_insn)
11159 arm_target_insn = NULL;
11160 arm_ccfsm_state = 0;
11165 /* If in state 3, it is possible to repeat the trick, if this insn is an
11166 unconditional branch to a label, and immediately following this branch
11167 is the previous target label which is only used once, and the label this
11168 branch jumps to is not too far off. */
11169 if (arm_ccfsm_state == 3)
11171 if (simplejump_p (insn))
11173 start_insn = next_nonnote_insn (start_insn);
11174 if (GET_CODE (start_insn) == BARRIER)
11176 /* XXX Isn't this always a barrier? */
11177 start_insn = next_nonnote_insn (start_insn);
11179 if (GET_CODE (start_insn) == CODE_LABEL
11180 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11181 && LABEL_NUSES (start_insn) == 1)
11186 else if (GET_CODE (body) == RETURN)
11188 start_insn = next_nonnote_insn (start_insn);
11189 if (GET_CODE (start_insn) == BARRIER)
11190 start_insn = next_nonnote_insn (start_insn);
11191 if (GET_CODE (start_insn) == CODE_LABEL
11192 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11193 && LABEL_NUSES (start_insn) == 1)
11196 seeking_return = 1;
11205 gcc_assert (!arm_ccfsm_state || reverse);
11206 if (GET_CODE (insn) != JUMP_INSN)
11209 /* This jump might be paralleled with a clobber of the condition codes
11210 the jump should always come first */
11211 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11212 body = XVECEXP (body, 0, 0);
11215 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11216 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11219 int fail = FALSE, succeed = FALSE;
11220 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11221 int then_not_else = TRUE;
11222 rtx this_insn = start_insn, label = 0;
11224 /* If the jump cannot be done with one instruction, we cannot
11225 conditionally execute the instruction in the inverse case. */
11226 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11232 /* Register the insn jumped to. */
11235 if (!seeking_return)
11236 label = XEXP (SET_SRC (body), 0);
11238 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11239 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11240 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11242 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11243 then_not_else = FALSE;
11245 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11246 seeking_return = 1;
11247 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11249 seeking_return = 1;
11250 then_not_else = FALSE;
11253 gcc_unreachable ();
11255 /* See how many insns this branch skips, and what kind of insns. If all
11256 insns are okay, and the label or unconditional branch to the same
11257 label is not too far away, succeed. */
11258 for (insns_skipped = 0;
11259 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11263 this_insn = next_nonnote_insn (this_insn);
11267 switch (GET_CODE (this_insn))
11270 /* Succeed if it is the target label, otherwise fail since
11271 control falls in from somewhere else. */
11272 if (this_insn == label)
11276 arm_ccfsm_state = 2;
11277 this_insn = next_nonnote_insn (this_insn);
11280 arm_ccfsm_state = 1;
11288 /* Succeed if the following insn is the target label.
11290 If return insns are used then the last insn in a function
11291 will be a barrier. */
11292 this_insn = next_nonnote_insn (this_insn);
11293 if (this_insn && this_insn == label)
11297 arm_ccfsm_state = 2;
11298 this_insn = next_nonnote_insn (this_insn);
11301 arm_ccfsm_state = 1;
11309 /* The AAPCS says that conditional calls should not be
11310 used since they make interworking inefficient (the
11311 linker can't transform BL<cond> into BLX). That's
11312 only a problem if the machine has BLX. */
11319 /* Succeed if the following insn is the target label, or
11320 if the following two insns are a barrier and the
11322 this_insn = next_nonnote_insn (this_insn);
11323 if (this_insn && GET_CODE (this_insn) == BARRIER)
11324 this_insn = next_nonnote_insn (this_insn);
11326 if (this_insn && this_insn == label
11327 && insns_skipped < max_insns_skipped)
11331 arm_ccfsm_state = 2;
11332 this_insn = next_nonnote_insn (this_insn);
11335 arm_ccfsm_state = 1;
11343 /* If this is an unconditional branch to the same label, succeed.
11344 If it is to another label, do nothing. If it is conditional,
11346 /* XXX Probably, the tests for SET and the PC are
11349 scanbody = PATTERN (this_insn);
11350 if (GET_CODE (scanbody) == SET
11351 && GET_CODE (SET_DEST (scanbody)) == PC)
11353 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11354 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11356 arm_ccfsm_state = 2;
11359 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11362 /* Fail if a conditional return is undesirable (e.g. on a
11363 StrongARM), but still allow this if optimizing for size. */
11364 else if (GET_CODE (scanbody) == RETURN
11365 && !use_return_insn (TRUE, NULL)
11368 else if (GET_CODE (scanbody) == RETURN
11371 arm_ccfsm_state = 2;
11374 else if (GET_CODE (scanbody) == PARALLEL)
11376 switch (get_attr_conds (this_insn))
11386 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11391 /* Instructions using or affecting the condition codes make it
11393 scanbody = PATTERN (this_insn);
11394 if (!(GET_CODE (scanbody) == SET
11395 || GET_CODE (scanbody) == PARALLEL)
11396 || get_attr_conds (this_insn) != CONDS_NOCOND)
11399 /* A conditional cirrus instruction must be followed by
11400 a non Cirrus instruction. However, since we
11401 conditionalize instructions in this function and by
11402 the time we get here we can't add instructions
11403 (nops), because shorten_branches() has already been
11404 called, we will disable conditionalizing Cirrus
11405 instructions to be safe. */
11406 if (GET_CODE (scanbody) != USE
11407 && GET_CODE (scanbody) != CLOBBER
11408 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11418 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11419 arm_target_label = CODE_LABEL_NUMBER (label);
11422 gcc_assert (seeking_return || arm_ccfsm_state == 2);
11424 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11426 this_insn = next_nonnote_insn (this_insn);
11427 gcc_assert (!this_insn
11428 || (GET_CODE (this_insn) != BARRIER
11429 && GET_CODE (this_insn) != CODE_LABEL));
11433 /* Oh, dear! we ran off the end.. give up. */
11434 recog (PATTERN (insn), insn, NULL);
11435 arm_ccfsm_state = 0;
11436 arm_target_insn = NULL;
11439 arm_target_insn = this_insn;
11443 gcc_assert (!reverse);
11445 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11447 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11448 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11449 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11450 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11454 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11457 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11461 if (reverse || then_not_else)
11462 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11465 /* Restore recog_data (getting the attributes of other insns can
11466 destroy this array, but final.c assumes that it remains intact
11467 across this call; since the insn has been recognized already we
11468 call recog direct). */
11469 recog (PATTERN (insn), insn, NULL);
11473 /* Returns true if REGNO is a valid register
11474 for holding a quantity of type MODE. */
11476 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11478 if (GET_MODE_CLASS (mode) == MODE_CC)
11479 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11482 /* For the Thumb we only allow values bigger than SImode in
11483 registers 0 - 6, so that there is always a second low
11484 register available to hold the upper part of the value.
11485 We probably we ought to ensure that the register is the
11486 start of an even numbered register pair. */
11487 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11489 if (IS_CIRRUS_REGNUM (regno))
11490 /* We have outlawed SI values in Cirrus registers because they
11491 reside in the lower 32 bits, but SF values reside in the
11492 upper 32 bits. This causes gcc all sorts of grief. We can't
11493 even split the registers into pairs because Cirrus SI values
11494 get sign extended to 64bits-- aldyh. */
11495 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11497 if (IS_VFP_REGNUM (regno))
11499 if (mode == SFmode || mode == SImode)
11502 /* DFmode values are only valid in even register pairs. */
11503 if (mode == DFmode)
11504 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11508 if (IS_IWMMXT_GR_REGNUM (regno))
11509 return mode == SImode;
11511 if (IS_IWMMXT_REGNUM (regno))
11512 return VALID_IWMMXT_REG_MODE (mode);
11514 /* We allow any value to be stored in the general registers.
11515 Restrict doubleword quantities to even register pairs so that we can
11517 if (regno <= LAST_ARM_REGNUM)
11518 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11520 if ( regno == FRAME_POINTER_REGNUM
11521 || regno == ARG_POINTER_REGNUM)
11522 /* We only allow integers in the fake hard registers. */
11523 return GET_MODE_CLASS (mode) == MODE_INT;
11525 /* The only registers left are the FPA registers
11526 which we only allow to hold FP values. */
11527 return GET_MODE_CLASS (mode) == MODE_FLOAT
11528 && regno >= FIRST_FPA_REGNUM
11529 && regno <= LAST_FPA_REGNUM;
11533 arm_regno_class (int regno)
11537 if (regno == STACK_POINTER_REGNUM)
11539 if (regno == CC_REGNUM)
11546 if ( regno <= LAST_ARM_REGNUM
11547 || regno == FRAME_POINTER_REGNUM
11548 || regno == ARG_POINTER_REGNUM)
11549 return GENERAL_REGS;
11551 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11554 if (IS_CIRRUS_REGNUM (regno))
11555 return CIRRUS_REGS;
11557 if (IS_VFP_REGNUM (regno))
11560 if (IS_IWMMXT_REGNUM (regno))
11561 return IWMMXT_REGS;
11563 if (IS_IWMMXT_GR_REGNUM (regno))
11564 return IWMMXT_GR_REGS;
11569 /* Handle a special case when computing the offset
11570 of an argument from the frame pointer. */
11572 arm_debugger_arg_offset (int value, rtx addr)
11576 /* We are only interested if dbxout_parms() failed to compute the offset. */
11580 /* We can only cope with the case where the address is held in a register. */
11581 if (GET_CODE (addr) != REG)
11584 /* If we are using the frame pointer to point at the argument, then
11585 an offset of 0 is correct. */
11586 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11589 /* If we are using the stack pointer to point at the
11590 argument, then an offset of 0 is correct. */
11591 if ((TARGET_THUMB || !frame_pointer_needed)
11592 && REGNO (addr) == SP_REGNUM)
11595 /* Oh dear. The argument is pointed to by a register rather
11596 than being held in a register, or being stored at a known
11597 offset from the frame pointer. Since GDB only understands
11598 those two kinds of argument we must translate the address
11599 held in the register into an offset from the frame pointer.
11600 We do this by searching through the insns for the function
11601 looking to see where this register gets its value. If the
11602 register is initialized from the frame pointer plus an offset
11603 then we are in luck and we can continue, otherwise we give up.
11605 This code is exercised by producing debugging information
11606 for a function with arguments like this:
11608 double func (double a, double b, int c, double d) {return d;}
11610 Without this code the stab for parameter 'd' will be set to
11611 an offset of 0 from the frame pointer, rather than 8. */
11613 /* The if() statement says:
11615 If the insn is a normal instruction
11616 and if the insn is setting the value in a register
11617 and if the register being set is the register holding the address of the argument
11618 and if the address is computing by an addition
11619 that involves adding to a register
11620 which is the frame pointer
11625 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11627 if ( GET_CODE (insn) == INSN
11628 && GET_CODE (PATTERN (insn)) == SET
11629 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11630 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11631 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11632 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11633 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11636 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11645 warning (0, "unable to compute real location of stacked parameter");
11646 value = 8; /* XXX magic hack */
11652 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11655 if ((MASK) & insn_flags) \
11656 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11657 BUILT_IN_MD, NULL, NULL_TREE); \
11661 struct builtin_description
11663 const unsigned int mask;
11664 const enum insn_code icode;
11665 const char * const name;
11666 const enum arm_builtins code;
11667 const enum rtx_code comparison;
11668 const unsigned int flag;
11671 static const struct builtin_description bdesc_2arg[] =
11673 #define IWMMXT_BUILTIN(code, string, builtin) \
11674 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11675 ARM_BUILTIN_##builtin, 0, 0 },
11677 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11678 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11679 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11680 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11681 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11682 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11683 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11684 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11685 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11686 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11687 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11688 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11689 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11690 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11691 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11692 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11693 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11694 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11695 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11696 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11697 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11698 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11699 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11700 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11701 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11702 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11703 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11704 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11705 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11706 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11707 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11708 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11709 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11710 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11711 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11712 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11713 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11714 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11715 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11716 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11717 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11718 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11719 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11720 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11721 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11722 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11723 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11724 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11725 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11726 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11727 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11728 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11729 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11730 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11731 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11732 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11733 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11734 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11736 #define IWMMXT_BUILTIN2(code, builtin) \
11737 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11739 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11740 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11741 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11742 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11743 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11744 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11745 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11746 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11747 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11748 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11749 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11750 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11751 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11752 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11753 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11754 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11755 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11756 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11757 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11758 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11759 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11760 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11761 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11762 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11763 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11764 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11765 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11766 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11767 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11768 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11769 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11770 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11773 static const struct builtin_description bdesc_1arg[] =
11775 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11776 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11777 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11778 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11779 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11780 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11781 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11782 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11783 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11784 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11785 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11786 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11787 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11788 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11789 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11790 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11791 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11792 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11795 /* Set up all the iWMMXt builtins. This is
11796 not called if TARGET_IWMMXT is zero. */
11799 arm_init_iwmmxt_builtins (void)
11801 const struct builtin_description * d;
11803 tree endlink = void_list_node;
11805 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11806 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11807 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11810 = build_function_type (integer_type_node,
11811 tree_cons (NULL_TREE, integer_type_node, endlink));
11812 tree v8qi_ftype_v8qi_v8qi_int
11813 = build_function_type (V8QI_type_node,
11814 tree_cons (NULL_TREE, V8QI_type_node,
11815 tree_cons (NULL_TREE, V8QI_type_node,
11816 tree_cons (NULL_TREE,
11819 tree v4hi_ftype_v4hi_int
11820 = build_function_type (V4HI_type_node,
11821 tree_cons (NULL_TREE, V4HI_type_node,
11822 tree_cons (NULL_TREE, integer_type_node,
11824 tree v2si_ftype_v2si_int
11825 = build_function_type (V2SI_type_node,
11826 tree_cons (NULL_TREE, V2SI_type_node,
11827 tree_cons (NULL_TREE, integer_type_node,
11829 tree v2si_ftype_di_di
11830 = build_function_type (V2SI_type_node,
11831 tree_cons (NULL_TREE, long_long_integer_type_node,
11832 tree_cons (NULL_TREE, long_long_integer_type_node,
11834 tree di_ftype_di_int
11835 = build_function_type (long_long_integer_type_node,
11836 tree_cons (NULL_TREE, long_long_integer_type_node,
11837 tree_cons (NULL_TREE, integer_type_node,
11839 tree di_ftype_di_int_int
11840 = build_function_type (long_long_integer_type_node,
11841 tree_cons (NULL_TREE, long_long_integer_type_node,
11842 tree_cons (NULL_TREE, integer_type_node,
11843 tree_cons (NULL_TREE,
11846 tree int_ftype_v8qi
11847 = build_function_type (integer_type_node,
11848 tree_cons (NULL_TREE, V8QI_type_node,
11850 tree int_ftype_v4hi
11851 = build_function_type (integer_type_node,
11852 tree_cons (NULL_TREE, V4HI_type_node,
11854 tree int_ftype_v2si
11855 = build_function_type (integer_type_node,
11856 tree_cons (NULL_TREE, V2SI_type_node,
11858 tree int_ftype_v8qi_int
11859 = build_function_type (integer_type_node,
11860 tree_cons (NULL_TREE, V8QI_type_node,
11861 tree_cons (NULL_TREE, integer_type_node,
11863 tree int_ftype_v4hi_int
11864 = build_function_type (integer_type_node,
11865 tree_cons (NULL_TREE, V4HI_type_node,
11866 tree_cons (NULL_TREE, integer_type_node,
11868 tree int_ftype_v2si_int
11869 = build_function_type (integer_type_node,
11870 tree_cons (NULL_TREE, V2SI_type_node,
11871 tree_cons (NULL_TREE, integer_type_node,
11873 tree v8qi_ftype_v8qi_int_int
11874 = build_function_type (V8QI_type_node,
11875 tree_cons (NULL_TREE, V8QI_type_node,
11876 tree_cons (NULL_TREE, integer_type_node,
11877 tree_cons (NULL_TREE,
11880 tree v4hi_ftype_v4hi_int_int
11881 = build_function_type (V4HI_type_node,
11882 tree_cons (NULL_TREE, V4HI_type_node,
11883 tree_cons (NULL_TREE, integer_type_node,
11884 tree_cons (NULL_TREE,
11887 tree v2si_ftype_v2si_int_int
11888 = build_function_type (V2SI_type_node,
11889 tree_cons (NULL_TREE, V2SI_type_node,
11890 tree_cons (NULL_TREE, integer_type_node,
11891 tree_cons (NULL_TREE,
11894 /* Miscellaneous. */
11895 tree v8qi_ftype_v4hi_v4hi
11896 = build_function_type (V8QI_type_node,
11897 tree_cons (NULL_TREE, V4HI_type_node,
11898 tree_cons (NULL_TREE, V4HI_type_node,
11900 tree v4hi_ftype_v2si_v2si
11901 = build_function_type (V4HI_type_node,
11902 tree_cons (NULL_TREE, V2SI_type_node,
11903 tree_cons (NULL_TREE, V2SI_type_node,
11905 tree v2si_ftype_v4hi_v4hi
11906 = build_function_type (V2SI_type_node,
11907 tree_cons (NULL_TREE, V4HI_type_node,
11908 tree_cons (NULL_TREE, V4HI_type_node,
11910 tree v2si_ftype_v8qi_v8qi
11911 = build_function_type (V2SI_type_node,
11912 tree_cons (NULL_TREE, V8QI_type_node,
11913 tree_cons (NULL_TREE, V8QI_type_node,
11915 tree v4hi_ftype_v4hi_di
11916 = build_function_type (V4HI_type_node,
11917 tree_cons (NULL_TREE, V4HI_type_node,
11918 tree_cons (NULL_TREE,
11919 long_long_integer_type_node,
11921 tree v2si_ftype_v2si_di
11922 = build_function_type (V2SI_type_node,
11923 tree_cons (NULL_TREE, V2SI_type_node,
11924 tree_cons (NULL_TREE,
11925 long_long_integer_type_node,
11927 tree void_ftype_int_int
11928 = build_function_type (void_type_node,
11929 tree_cons (NULL_TREE, integer_type_node,
11930 tree_cons (NULL_TREE, integer_type_node,
11933 = build_function_type (long_long_unsigned_type_node, endlink);
11935 = build_function_type (long_long_integer_type_node,
11936 tree_cons (NULL_TREE, V8QI_type_node,
11939 = build_function_type (long_long_integer_type_node,
11940 tree_cons (NULL_TREE, V4HI_type_node,
11943 = build_function_type (long_long_integer_type_node,
11944 tree_cons (NULL_TREE, V2SI_type_node,
11946 tree v2si_ftype_v4hi
11947 = build_function_type (V2SI_type_node,
11948 tree_cons (NULL_TREE, V4HI_type_node,
11950 tree v4hi_ftype_v8qi
11951 = build_function_type (V4HI_type_node,
11952 tree_cons (NULL_TREE, V8QI_type_node,
11955 tree di_ftype_di_v4hi_v4hi
11956 = build_function_type (long_long_unsigned_type_node,
11957 tree_cons (NULL_TREE,
11958 long_long_unsigned_type_node,
11959 tree_cons (NULL_TREE, V4HI_type_node,
11960 tree_cons (NULL_TREE,
11964 tree di_ftype_v4hi_v4hi
11965 = build_function_type (long_long_unsigned_type_node,
11966 tree_cons (NULL_TREE, V4HI_type_node,
11967 tree_cons (NULL_TREE, V4HI_type_node,
11970 /* Normal vector binops. */
11971 tree v8qi_ftype_v8qi_v8qi
11972 = build_function_type (V8QI_type_node,
11973 tree_cons (NULL_TREE, V8QI_type_node,
11974 tree_cons (NULL_TREE, V8QI_type_node,
11976 tree v4hi_ftype_v4hi_v4hi
11977 = build_function_type (V4HI_type_node,
11978 tree_cons (NULL_TREE, V4HI_type_node,
11979 tree_cons (NULL_TREE, V4HI_type_node,
11981 tree v2si_ftype_v2si_v2si
11982 = build_function_type (V2SI_type_node,
11983 tree_cons (NULL_TREE, V2SI_type_node,
11984 tree_cons (NULL_TREE, V2SI_type_node,
11986 tree di_ftype_di_di
11987 = build_function_type (long_long_unsigned_type_node,
11988 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11989 tree_cons (NULL_TREE,
11990 long_long_unsigned_type_node,
11993 /* Add all builtins that are more or less simple operations on two
11995 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11997 /* Use one of the operands; the target can have a different mode for
11998 mask-generating compares. */
11999 enum machine_mode mode;
12005 mode = insn_data[d->icode].operand[1].mode;
12010 type = v8qi_ftype_v8qi_v8qi;
12013 type = v4hi_ftype_v4hi_v4hi;
12016 type = v2si_ftype_v2si_v2si;
12019 type = di_ftype_di_di;
12023 gcc_unreachable ();
12026 def_mbuiltin (d->mask, d->name, type, d->code);
12029 /* Add the remaining MMX insns with somewhat more complicated types. */
12030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12056 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12057 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12064 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12065 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12066 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12067 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12069 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12070 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12071 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12072 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12073 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12074 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12075 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12076 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12077 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12079 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12080 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12081 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12083 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12084 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12085 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12087 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12088 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12089 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12090 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12091 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12092 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12094 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12095 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12096 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12097 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12098 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12099 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12100 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12101 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12102 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12103 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12104 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12105 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12107 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12108 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12109 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12110 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12112 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12113 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12114 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12115 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12116 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12117 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12118 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12122 arm_init_builtins (void)
12124 if (TARGET_REALLY_IWMMXT)
12125 arm_init_iwmmxt_builtins ();
12128 /* Errors in the source file can cause expand_expr to return const0_rtx
12129 where we expect a vector. To avoid crashing, use one of the vector
12130 clear instructions. */
12133 safe_vector_operand (rtx x, enum machine_mode mode)
12135 if (x != const0_rtx)
12137 x = gen_reg_rtx (mode);
12139 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12140 : gen_rtx_SUBREG (DImode, x, 0)));
12144 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12147 arm_expand_binop_builtin (enum insn_code icode,
12148 tree arglist, rtx target)
12151 tree arg0 = TREE_VALUE (arglist);
12152 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12153 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12154 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12155 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12156 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12157 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12159 if (VECTOR_MODE_P (mode0))
12160 op0 = safe_vector_operand (op0, mode0);
12161 if (VECTOR_MODE_P (mode1))
12162 op1 = safe_vector_operand (op1, mode1);
12165 || GET_MODE (target) != tmode
12166 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12167 target = gen_reg_rtx (tmode);
12169 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
12171 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12172 op0 = copy_to_mode_reg (mode0, op0);
12173 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12174 op1 = copy_to_mode_reg (mode1, op1);
12176 pat = GEN_FCN (icode) (target, op0, op1);
12183 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12186 arm_expand_unop_builtin (enum insn_code icode,
12187 tree arglist, rtx target, int do_load)
12190 tree arg0 = TREE_VALUE (arglist);
12191 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12192 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12193 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12196 || GET_MODE (target) != tmode
12197 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12198 target = gen_reg_rtx (tmode);
12200 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12203 if (VECTOR_MODE_P (mode0))
12204 op0 = safe_vector_operand (op0, mode0);
12206 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12207 op0 = copy_to_mode_reg (mode0, op0);
12210 pat = GEN_FCN (icode) (target, op0);
12217 /* Expand an expression EXP that calls a built-in function,
12218 with result going to TARGET if that's convenient
12219 (and in mode MODE if that's convenient).
12220 SUBTARGET may be used as the target for computing one of EXP's operands.
12221 IGNORE is nonzero if the value is to be ignored. */
12224 arm_expand_builtin (tree exp,
12226 rtx subtarget ATTRIBUTE_UNUSED,
12227 enum machine_mode mode ATTRIBUTE_UNUSED,
12228 int ignore ATTRIBUTE_UNUSED)
12230 const struct builtin_description * d;
12231 enum insn_code icode;
12232 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12233 tree arglist = TREE_OPERAND (exp, 1);
12241 int fcode = DECL_FUNCTION_CODE (fndecl);
12243 enum machine_mode tmode;
12244 enum machine_mode mode0;
12245 enum machine_mode mode1;
12246 enum machine_mode mode2;
12250 case ARM_BUILTIN_TEXTRMSB:
12251 case ARM_BUILTIN_TEXTRMUB:
12252 case ARM_BUILTIN_TEXTRMSH:
12253 case ARM_BUILTIN_TEXTRMUH:
12254 case ARM_BUILTIN_TEXTRMSW:
12255 case ARM_BUILTIN_TEXTRMUW:
12256 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12257 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12258 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12259 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12260 : CODE_FOR_iwmmxt_textrmw);
12262 arg0 = TREE_VALUE (arglist);
12263 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12264 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12265 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12266 tmode = insn_data[icode].operand[0].mode;
12267 mode0 = insn_data[icode].operand[1].mode;
12268 mode1 = insn_data[icode].operand[2].mode;
12270 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12271 op0 = copy_to_mode_reg (mode0, op0);
12272 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12274 /* @@@ better error message */
12275 error ("selector must be an immediate");
12276 return gen_reg_rtx (tmode);
12279 || GET_MODE (target) != tmode
12280 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12281 target = gen_reg_rtx (tmode);
12282 pat = GEN_FCN (icode) (target, op0, op1);
12288 case ARM_BUILTIN_TINSRB:
12289 case ARM_BUILTIN_TINSRH:
12290 case ARM_BUILTIN_TINSRW:
12291 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12292 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12293 : CODE_FOR_iwmmxt_tinsrw);
12294 arg0 = TREE_VALUE (arglist);
12295 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12296 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12297 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12298 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12299 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12300 tmode = insn_data[icode].operand[0].mode;
12301 mode0 = insn_data[icode].operand[1].mode;
12302 mode1 = insn_data[icode].operand[2].mode;
12303 mode2 = insn_data[icode].operand[3].mode;
12305 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12306 op0 = copy_to_mode_reg (mode0, op0);
12307 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12308 op1 = copy_to_mode_reg (mode1, op1);
12309 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12311 /* @@@ better error message */
12312 error ("selector must be an immediate");
12316 || GET_MODE (target) != tmode
12317 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12318 target = gen_reg_rtx (tmode);
12319 pat = GEN_FCN (icode) (target, op0, op1, op2);
12325 case ARM_BUILTIN_SETWCX:
12326 arg0 = TREE_VALUE (arglist);
12327 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12328 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12329 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12330 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12333 case ARM_BUILTIN_GETWCX:
12334 arg0 = TREE_VALUE (arglist);
12335 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12336 target = gen_reg_rtx (SImode);
12337 emit_insn (gen_iwmmxt_tmrc (target, op0));
12340 case ARM_BUILTIN_WSHUFH:
12341 icode = CODE_FOR_iwmmxt_wshufh;
12342 arg0 = TREE_VALUE (arglist);
12343 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12344 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12345 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12346 tmode = insn_data[icode].operand[0].mode;
12347 mode1 = insn_data[icode].operand[1].mode;
12348 mode2 = insn_data[icode].operand[2].mode;
12350 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12351 op0 = copy_to_mode_reg (mode1, op0);
12352 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12354 /* @@@ better error message */
12355 error ("mask must be an immediate");
12359 || GET_MODE (target) != tmode
12360 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12361 target = gen_reg_rtx (tmode);
12362 pat = GEN_FCN (icode) (target, op0, op1);
12368 case ARM_BUILTIN_WSADB:
12369 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12370 case ARM_BUILTIN_WSADH:
12371 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12372 case ARM_BUILTIN_WSADBZ:
12373 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12374 case ARM_BUILTIN_WSADHZ:
12375 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12377 /* Several three-argument builtins. */
12378 case ARM_BUILTIN_WMACS:
12379 case ARM_BUILTIN_WMACU:
12380 case ARM_BUILTIN_WALIGN:
12381 case ARM_BUILTIN_TMIA:
12382 case ARM_BUILTIN_TMIAPH:
12383 case ARM_BUILTIN_TMIATT:
12384 case ARM_BUILTIN_TMIATB:
12385 case ARM_BUILTIN_TMIABT:
12386 case ARM_BUILTIN_TMIABB:
12387 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12388 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12389 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12390 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12391 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12392 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12393 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12394 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12395 : CODE_FOR_iwmmxt_walign);
12396 arg0 = TREE_VALUE (arglist);
12397 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12398 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12399 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12400 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12401 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12402 tmode = insn_data[icode].operand[0].mode;
12403 mode0 = insn_data[icode].operand[1].mode;
12404 mode1 = insn_data[icode].operand[2].mode;
12405 mode2 = insn_data[icode].operand[3].mode;
12407 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12408 op0 = copy_to_mode_reg (mode0, op0);
12409 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12410 op1 = copy_to_mode_reg (mode1, op1);
12411 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12412 op2 = copy_to_mode_reg (mode2, op2);
12414 || GET_MODE (target) != tmode
12415 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12416 target = gen_reg_rtx (tmode);
12417 pat = GEN_FCN (icode) (target, op0, op1, op2);
12423 case ARM_BUILTIN_WZERO:
12424 target = gen_reg_rtx (DImode);
12425 emit_insn (gen_iwmmxt_clrdi (target));
12432 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12433 if (d->code == (const enum arm_builtins) fcode)
12434 return arm_expand_binop_builtin (d->icode, arglist, target);
12436 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12437 if (d->code == (const enum arm_builtins) fcode)
12438 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12440 /* @@@ Should really do something sensible here. */
12444 /* Return the number (counting from 0) of
12445 the least significant set bit in MASK. */
12448 number_of_first_bit_set (unsigned mask)
12453 (mask & (1 << bit)) == 0;
12460 /* Emit code to push or pop registers to or from the stack. F is the
12461 assembly file. MASK is the registers to push or pop. PUSH is
12462 nonzero if we should push, and zero if we should pop. For debugging
12463 output, if pushing, adjust CFA_OFFSET by the amount of space added
12464 to the stack. REAL_REGS should have the same number of bits set as
12465 MASK, and will be used instead (in the same order) to describe which
12466 registers were saved - this is used to mark the save slots when we
12467 push high registers after moving them to low registers. */
12469 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
12470 unsigned long real_regs)
12473 int lo_mask = mask & 0xFF;
12474 int pushed_words = 0;
12478 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12480 /* Special case. Do not generate a POP PC statement here, do it in
12482 thumb_exit (f, -1);
12486 if (ARM_EABI_UNWIND_TABLES && push)
12488 fprintf (f, "\t.save\t{");
12489 for (regno = 0; regno < 15; regno++)
12491 if (real_regs & (1 << regno))
12493 if (real_regs & ((1 << regno) -1))
12495 asm_fprintf (f, "%r", regno);
12498 fprintf (f, "}\n");
12501 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12503 /* Look at the low registers first. */
12504 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12508 asm_fprintf (f, "%r", regno);
12510 if ((lo_mask & ~1) != 0)
12517 if (push && (mask & (1 << LR_REGNUM)))
12519 /* Catch pushing the LR. */
12523 asm_fprintf (f, "%r", LR_REGNUM);
12527 else if (!push && (mask & (1 << PC_REGNUM)))
12529 /* Catch popping the PC. */
12530 if (TARGET_INTERWORK || TARGET_BACKTRACE
12531 || current_function_calls_eh_return)
12533 /* The PC is never poped directly, instead
12534 it is popped into r3 and then BX is used. */
12535 fprintf (f, "}\n");
12537 thumb_exit (f, -1);
12546 asm_fprintf (f, "%r", PC_REGNUM);
12550 fprintf (f, "}\n");
12552 if (push && pushed_words && dwarf2out_do_frame ())
12554 char *l = dwarf2out_cfi_label ();
12555 int pushed_mask = real_regs;
12557 *cfa_offset += pushed_words * 4;
12558 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12561 pushed_mask = real_regs;
12562 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12564 if (pushed_mask & 1)
12565 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12570 /* Generate code to return from a thumb function.
12571 If 'reg_containing_return_addr' is -1, then the return address is
12572 actually on the stack, at the stack pointer. */
12574 thumb_exit (FILE *f, int reg_containing_return_addr)
12576 unsigned regs_available_for_popping;
12577 unsigned regs_to_pop;
12579 unsigned available;
12583 int restore_a4 = FALSE;
12585 /* Compute the registers we need to pop. */
12589 if (reg_containing_return_addr == -1)
12591 regs_to_pop |= 1 << LR_REGNUM;
12595 if (TARGET_BACKTRACE)
12597 /* Restore the (ARM) frame pointer and stack pointer. */
12598 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12602 /* If there is nothing to pop then just emit the BX instruction and
12604 if (pops_needed == 0)
12606 if (current_function_calls_eh_return)
12607 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12609 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12612 /* Otherwise if we are not supporting interworking and we have not created
12613 a backtrace structure and the function was not entered in ARM mode then
12614 just pop the return address straight into the PC. */
12615 else if (!TARGET_INTERWORK
12616 && !TARGET_BACKTRACE
12617 && !is_called_in_ARM_mode (current_function_decl)
12618 && !current_function_calls_eh_return)
12620 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12624 /* Find out how many of the (return) argument registers we can corrupt. */
12625 regs_available_for_popping = 0;
12627 /* If returning via __builtin_eh_return, the bottom three registers
12628 all contain information needed for the return. */
12629 if (current_function_calls_eh_return)
12633 /* If we can deduce the registers used from the function's
12634 return value. This is more reliable that examining
12635 regs_ever_live[] because that will be set if the register is
12636 ever used in the function, not just if the register is used
12637 to hold a return value. */
12639 if (current_function_return_rtx != 0)
12640 mode = GET_MODE (current_function_return_rtx);
12642 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12644 size = GET_MODE_SIZE (mode);
12648 /* In a void function we can use any argument register.
12649 In a function that returns a structure on the stack
12650 we can use the second and third argument registers. */
12651 if (mode == VOIDmode)
12652 regs_available_for_popping =
12653 (1 << ARG_REGISTER (1))
12654 | (1 << ARG_REGISTER (2))
12655 | (1 << ARG_REGISTER (3));
12657 regs_available_for_popping =
12658 (1 << ARG_REGISTER (2))
12659 | (1 << ARG_REGISTER (3));
12661 else if (size <= 4)
12662 regs_available_for_popping =
12663 (1 << ARG_REGISTER (2))
12664 | (1 << ARG_REGISTER (3));
12665 else if (size <= 8)
12666 regs_available_for_popping =
12667 (1 << ARG_REGISTER (3));
12670 /* Match registers to be popped with registers into which we pop them. */
12671 for (available = regs_available_for_popping,
12672 required = regs_to_pop;
12673 required != 0 && available != 0;
12674 available &= ~(available & - available),
12675 required &= ~(required & - required))
12678 /* If we have any popping registers left over, remove them. */
12680 regs_available_for_popping &= ~available;
12682 /* Otherwise if we need another popping register we can use
12683 the fourth argument register. */
12684 else if (pops_needed)
12686 /* If we have not found any free argument registers and
12687 reg a4 contains the return address, we must move it. */
12688 if (regs_available_for_popping == 0
12689 && reg_containing_return_addr == LAST_ARG_REGNUM)
12691 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12692 reg_containing_return_addr = LR_REGNUM;
12694 else if (size > 12)
12696 /* Register a4 is being used to hold part of the return value,
12697 but we have dire need of a free, low register. */
12700 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12703 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12705 /* The fourth argument register is available. */
12706 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12712 /* Pop as many registers as we can. */
12713 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12714 regs_available_for_popping);
12716 /* Process the registers we popped. */
12717 if (reg_containing_return_addr == -1)
12719 /* The return address was popped into the lowest numbered register. */
12720 regs_to_pop &= ~(1 << LR_REGNUM);
12722 reg_containing_return_addr =
12723 number_of_first_bit_set (regs_available_for_popping);
12725 /* Remove this register for the mask of available registers, so that
12726 the return address will not be corrupted by further pops. */
12727 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12730 /* If we popped other registers then handle them here. */
12731 if (regs_available_for_popping)
12735 /* Work out which register currently contains the frame pointer. */
12736 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12738 /* Move it into the correct place. */
12739 asm_fprintf (f, "\tmov\t%r, %r\n",
12740 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12742 /* (Temporarily) remove it from the mask of popped registers. */
12743 regs_available_for_popping &= ~(1 << frame_pointer);
12744 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12746 if (regs_available_for_popping)
12750 /* We popped the stack pointer as well,
12751 find the register that contains it. */
12752 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12754 /* Move it into the stack register. */
12755 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12757 /* At this point we have popped all necessary registers, so
12758 do not worry about restoring regs_available_for_popping
12759 to its correct value:
12761 assert (pops_needed == 0)
12762 assert (regs_available_for_popping == (1 << frame_pointer))
12763 assert (regs_to_pop == (1 << STACK_POINTER)) */
12767 /* Since we have just move the popped value into the frame
12768 pointer, the popping register is available for reuse, and
12769 we know that we still have the stack pointer left to pop. */
12770 regs_available_for_popping |= (1 << frame_pointer);
12774 /* If we still have registers left on the stack, but we no longer have
12775 any registers into which we can pop them, then we must move the return
12776 address into the link register and make available the register that
12778 if (regs_available_for_popping == 0 && pops_needed > 0)
12780 regs_available_for_popping |= 1 << reg_containing_return_addr;
12782 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12783 reg_containing_return_addr);
12785 reg_containing_return_addr = LR_REGNUM;
12788 /* If we have registers left on the stack then pop some more.
12789 We know that at most we will want to pop FP and SP. */
12790 if (pops_needed > 0)
12795 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12796 regs_available_for_popping);
12798 /* We have popped either FP or SP.
12799 Move whichever one it is into the correct register. */
12800 popped_into = number_of_first_bit_set (regs_available_for_popping);
12801 move_to = number_of_first_bit_set (regs_to_pop);
12803 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12805 regs_to_pop &= ~(1 << move_to);
12810 /* If we still have not popped everything then we must have only
12811 had one register available to us and we are now popping the SP. */
12812 if (pops_needed > 0)
12816 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12817 regs_available_for_popping);
12819 popped_into = number_of_first_bit_set (regs_available_for_popping);
12821 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12823 assert (regs_to_pop == (1 << STACK_POINTER))
12824 assert (pops_needed == 1)
12828 /* If necessary restore the a4 register. */
12831 if (reg_containing_return_addr != LR_REGNUM)
12833 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12834 reg_containing_return_addr = LR_REGNUM;
12837 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12840 if (current_function_calls_eh_return)
12841 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12843 /* Return to caller. */
12844 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12849 thumb_final_prescan_insn (rtx insn)
12851 if (flag_print_asm_name)
12852 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12853 INSN_ADDRESSES (INSN_UID (insn)));
12857 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12859 unsigned HOST_WIDE_INT mask = 0xff;
12862 if (val == 0) /* XXX */
12865 for (i = 0; i < 25; i++)
12866 if ((val & (mask << i)) == val)
12872 /* Returns nonzero if the current function contains,
12873 or might contain a far jump. */
12875 thumb_far_jump_used_p (void)
12879 /* This test is only important for leaf functions. */
12880 /* assert (!leaf_function_p ()); */
12882 /* If we have already decided that far jumps may be used,
12883 do not bother checking again, and always return true even if
12884 it turns out that they are not being used. Once we have made
12885 the decision that far jumps are present (and that hence the link
12886 register will be pushed onto the stack) we cannot go back on it. */
12887 if (cfun->machine->far_jump_used)
12890 /* If this function is not being called from the prologue/epilogue
12891 generation code then it must be being called from the
12892 INITIAL_ELIMINATION_OFFSET macro. */
12893 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12895 /* In this case we know that we are being asked about the elimination
12896 of the arg pointer register. If that register is not being used,
12897 then there are no arguments on the stack, and we do not have to
12898 worry that a far jump might force the prologue to push the link
12899 register, changing the stack offsets. In this case we can just
12900 return false, since the presence of far jumps in the function will
12901 not affect stack offsets.
12903 If the arg pointer is live (or if it was live, but has now been
12904 eliminated and so set to dead) then we do have to test to see if
12905 the function might contain a far jump. This test can lead to some
12906 false negatives, since before reload is completed, then length of
12907 branch instructions is not known, so gcc defaults to returning their
12908 longest length, which in turn sets the far jump attribute to true.
12910 A false negative will not result in bad code being generated, but it
12911 will result in a needless push and pop of the link register. We
12912 hope that this does not occur too often.
12914 If we need doubleword stack alignment this could affect the other
12915 elimination offsets so we can't risk getting it wrong. */
12916 if (regs_ever_live [ARG_POINTER_REGNUM])
12917 cfun->machine->arg_pointer_live = 1;
12918 else if (!cfun->machine->arg_pointer_live)
12922 /* Check to see if the function contains a branch
12923 insn with the far jump attribute set. */
12924 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12926 if (GET_CODE (insn) == JUMP_INSN
12927 /* Ignore tablejump patterns. */
12928 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12929 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12930 && get_attr_far_jump (insn) == FAR_JUMP_YES
12933 /* Record the fact that we have decided that
12934 the function does use far jumps. */
12935 cfun->machine->far_jump_used = 1;
12943 /* Return nonzero if FUNC must be entered in ARM mode. */
12945 is_called_in_ARM_mode (tree func)
12947 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
12949 /* Ignore the problem about functions whose address is taken. */
12950 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12954 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12960 /* The bits which aren't usefully expanded as rtl. */
12962 thumb_unexpanded_epilogue (void)
12965 unsigned long live_regs_mask = 0;
12966 int high_regs_pushed = 0;
12967 int had_to_push_lr;
12970 if (return_used_this_function)
12973 if (IS_NAKED (arm_current_func_type ()))
12976 live_regs_mask = thumb_compute_save_reg_mask ();
12977 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
12979 /* If we can deduce the registers used from the function's return value.
12980 This is more reliable that examining regs_ever_live[] because that
12981 will be set if the register is ever used in the function, not just if
12982 the register is used to hold a return value. */
12983 size = arm_size_return_regs ();
12985 /* The prolog may have pushed some high registers to use as
12986 work registers. e.g. the testsuite file:
12987 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12988 compiles to produce:
12989 push {r4, r5, r6, r7, lr}
12993 as part of the prolog. We have to undo that pushing here. */
12995 if (high_regs_pushed)
12997 unsigned long mask = live_regs_mask & 0xff;
13000 /* The available low registers depend on the size of the value we are
13008 /* Oh dear! We have no low registers into which we can pop
13011 ("no low registers available for popping high registers");
13013 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13014 if (live_regs_mask & (1 << next_hi_reg))
13017 while (high_regs_pushed)
13019 /* Find lo register(s) into which the high register(s) can
13021 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13023 if (mask & (1 << regno))
13024 high_regs_pushed--;
13025 if (high_regs_pushed == 0)
13029 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13031 /* Pop the values into the low register(s). */
13032 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13034 /* Move the value(s) into the high registers. */
13035 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13037 if (mask & (1 << regno))
13039 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13042 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13043 if (live_regs_mask & (1 << next_hi_reg))
13048 live_regs_mask &= ~0x0f00;
13051 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13052 live_regs_mask &= 0xff;
13054 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13056 /* Pop the return address into the PC. */
13057 if (had_to_push_lr)
13058 live_regs_mask |= 1 << PC_REGNUM;
13060 /* Either no argument registers were pushed or a backtrace
13061 structure was created which includes an adjusted stack
13062 pointer, so just pop everything. */
13063 if (live_regs_mask)
13064 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13067 /* We have either just popped the return address into the
13068 PC or it is was kept in LR for the entire function. */
13069 if (!had_to_push_lr)
13070 thumb_exit (asm_out_file, LR_REGNUM);
13074 /* Pop everything but the return address. */
13075 if (live_regs_mask)
13076 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13079 if (had_to_push_lr)
13083 /* We have no free low regs, so save one. */
13084 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13088 /* Get the return address into a temporary register. */
13089 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13090 1 << LAST_ARG_REGNUM);
13094 /* Move the return address to lr. */
13095 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13097 /* Restore the low register. */
13098 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13103 regno = LAST_ARG_REGNUM;
13108 /* Remove the argument registers that were pushed onto the stack. */
13109 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13110 SP_REGNUM, SP_REGNUM,
13111 current_function_pretend_args_size);
13113 thumb_exit (asm_out_file, regno);
13119 /* Functions to save and restore machine-specific function data. */
13120 static struct machine_function *
13121 arm_init_machine_status (void)
13123 struct machine_function *machine;
13124 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13126 #if ARM_FT_UNKNOWN != 0
13127 machine->func_type = ARM_FT_UNKNOWN;
13132 /* Return an RTX indicating where the return address to the
13133 calling function can be found. */
13135 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13140 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13143 /* Do anything needed before RTL is emitted for each function. */
13145 arm_init_expanders (void)
13147 /* Arrange to initialize and mark the machine per-function status. */
13148 init_machine_status = arm_init_machine_status;
13150 /* This is to stop the combine pass optimizing away the alignment
13151 adjustment of va_arg. */
13152 /* ??? It is claimed that this should not be necessary. */
13154 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13158 /* Like arm_compute_initial_elimination offset. Simpler because there
13159 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13160 to point at the base of the local variables after static stack
13161 space for a function has been allocated. */
13164 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13166 arm_stack_offsets *offsets;
13168 offsets = arm_get_frame_offsets ();
13172 case ARG_POINTER_REGNUM:
13175 case STACK_POINTER_REGNUM:
13176 return offsets->outgoing_args - offsets->saved_args;
13178 case FRAME_POINTER_REGNUM:
13179 return offsets->soft_frame - offsets->saved_args;
13181 case ARM_HARD_FRAME_POINTER_REGNUM:
13182 return offsets->saved_regs - offsets->saved_args;
13184 case THUMB_HARD_FRAME_POINTER_REGNUM:
13185 return offsets->locals_base - offsets->saved_args;
13188 gcc_unreachable ();
13192 case FRAME_POINTER_REGNUM:
13195 case STACK_POINTER_REGNUM:
13196 return offsets->outgoing_args - offsets->soft_frame;
13198 case ARM_HARD_FRAME_POINTER_REGNUM:
13199 return offsets->saved_regs - offsets->soft_frame;
13201 case THUMB_HARD_FRAME_POINTER_REGNUM:
13202 return offsets->locals_base - offsets->soft_frame;
13205 gcc_unreachable ();
13210 gcc_unreachable ();
13215 /* Generate the rest of a function's prologue. */
13217 thumb_expand_prologue (void)
13221 HOST_WIDE_INT amount;
13222 arm_stack_offsets *offsets;
13223 unsigned long func_type;
13225 unsigned long live_regs_mask;
13227 func_type = arm_current_func_type ();
13229 /* Naked functions don't have prologues. */
13230 if (IS_NAKED (func_type))
13233 if (IS_INTERRUPT (func_type))
13235 error ("interrupt Service Routines cannot be coded in Thumb mode");
13239 live_regs_mask = thumb_compute_save_reg_mask ();
13240 /* Load the pic register before setting the frame pointer,
13241 so we can use r7 as a temporary work register. */
13243 arm_load_pic_register (live_regs_mask);
13245 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
13246 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13247 stack_pointer_rtx);
13249 offsets = arm_get_frame_offsets ();
13250 amount = offsets->outgoing_args - offsets->saved_regs;
13255 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13256 GEN_INT (- amount)));
13257 RTX_FRAME_RELATED_P (insn) = 1;
13263 /* The stack decrement is too big for an immediate value in a single
13264 insn. In theory we could issue multiple subtracts, but after
13265 three of them it becomes more space efficient to place the full
13266 value in the constant pool and load into a register. (Also the
13267 ARM debugger really likes to see only one stack decrement per
13268 function). So instead we look for a scratch register into which
13269 we can load the decrement, and then we subtract this from the
13270 stack pointer. Unfortunately on the thumb the only available
13271 scratch registers are the argument registers, and we cannot use
13272 these as they may hold arguments to the function. Instead we
13273 attempt to locate a call preserved register which is used by this
13274 function. If we can find one, then we know that it will have
13275 been pushed at the start of the prologue and so we can corrupt
13277 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13278 if (live_regs_mask & (1 << regno)
13279 && !(frame_pointer_needed
13280 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13283 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13285 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13287 /* Choose an arbitrary, non-argument low register. */
13288 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13290 /* Save it by copying it into a high, scratch register. */
13291 emit_insn (gen_movsi (spare, reg));
13292 /* Add a USE to stop propagate_one_insn() from barfing. */
13293 emit_insn (gen_prologue_use (spare));
13295 /* Decrement the stack. */
13296 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13297 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13298 stack_pointer_rtx, reg));
13299 RTX_FRAME_RELATED_P (insn) = 1;
13300 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13301 plus_constant (stack_pointer_rtx,
13303 RTX_FRAME_RELATED_P (dwarf) = 1;
13305 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13308 /* Restore the low register's original value. */
13309 emit_insn (gen_movsi (reg, spare));
13311 /* Emit a USE of the restored scratch register, so that flow
13312 analysis will not consider the restore redundant. The
13313 register won't be used again in this function and isn't
13314 restored by the epilogue. */
13315 emit_insn (gen_prologue_use (reg));
13319 reg = gen_rtx_REG (SImode, regno);
13321 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13323 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13324 stack_pointer_rtx, reg));
13325 RTX_FRAME_RELATED_P (insn) = 1;
13326 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13327 plus_constant (stack_pointer_rtx,
13329 RTX_FRAME_RELATED_P (dwarf) = 1;
13331 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13337 if (frame_pointer_needed)
13339 amount = offsets->outgoing_args - offsets->locals_base;
13342 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13343 stack_pointer_rtx, GEN_INT (amount)));
13346 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
13347 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13348 hard_frame_pointer_rtx,
13349 stack_pointer_rtx));
13350 dwarf = gen_rtx_SET (SImode, hard_frame_pointer_rtx,
13351 plus_constant (stack_pointer_rtx, amount));
13352 RTX_FRAME_RELATED_P (dwarf) = 1;
13353 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13357 RTX_FRAME_RELATED_P (insn) = 1;
13360 if (current_function_profile || !TARGET_SCHED_PROLOG)
13361 emit_insn (gen_blockage ());
13363 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13364 if (live_regs_mask & 0xff)
13365 cfun->machine->lr_save_eliminated = 0;
13367 /* If the link register is being kept alive, with the return address in it,
13368 then make sure that it does not get reused by the ce2 pass. */
13369 if (cfun->machine->lr_save_eliminated)
13370 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13375 thumb_expand_epilogue (void)
13377 HOST_WIDE_INT amount;
13378 arm_stack_offsets *offsets;
13381 /* Naked functions don't have prologues. */
13382 if (IS_NAKED (arm_current_func_type ()))
13385 offsets = arm_get_frame_offsets ();
13386 amount = offsets->outgoing_args - offsets->saved_regs;
13388 if (frame_pointer_needed)
13390 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13391 amount = offsets->locals_base - offsets->saved_regs;
13397 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13398 GEN_INT (amount)));
13401 /* r3 is always free in the epilogue. */
13402 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13404 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13405 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13409 /* Emit a USE (stack_pointer_rtx), so that
13410 the stack adjustment will not be deleted. */
13411 emit_insn (gen_prologue_use (stack_pointer_rtx));
13413 if (current_function_profile || !TARGET_SCHED_PROLOG)
13414 emit_insn (gen_blockage ());
13416 /* Emit a clobber for each insn that will be restored in the epilogue,
13417 so that flow2 will get register lifetimes correct. */
13418 for (regno = 0; regno < 13; regno++)
13419 if (regs_ever_live[regno] && !call_used_regs[regno])
13420 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13422 if (! regs_ever_live[LR_REGNUM])
13423 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13427 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13429 unsigned long live_regs_mask = 0;
13430 unsigned long l_mask;
13431 unsigned high_regs_pushed = 0;
13432 int cfa_offset = 0;
13435 if (IS_NAKED (arm_current_func_type ()))
13438 if (is_called_in_ARM_mode (current_function_decl))
13442 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
13443 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
13445 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13447 /* Generate code sequence to switch us into Thumb mode. */
13448 /* The .code 32 directive has already been emitted by
13449 ASM_DECLARE_FUNCTION_NAME. */
13450 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13451 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13453 /* Generate a label, so that the debugger will notice the
13454 change in instruction sets. This label is also used by
13455 the assembler to bypass the ARM code when this function
13456 is called from a Thumb encoded function elsewhere in the
13457 same file. Hence the definition of STUB_NAME here must
13458 agree with the definition in gas/config/tc-arm.c. */
13460 #define STUB_NAME ".real_start_of"
13462 fprintf (f, "\t.code\t16\n");
13464 if (arm_dllexport_name_p (name))
13465 name = arm_strip_name_encoding (name);
13467 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13468 fprintf (f, "\t.thumb_func\n");
13469 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13472 if (current_function_pretend_args_size)
13474 /* Output unwind directive for the stack adjustment. */
13475 if (ARM_EABI_UNWIND_TABLES)
13476 fprintf (f, "\t.pad #%d\n",
13477 current_function_pretend_args_size);
13479 if (cfun->machine->uses_anonymous_args)
13483 fprintf (f, "\tpush\t{");
13485 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13487 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13488 regno <= LAST_ARG_REGNUM;
13490 asm_fprintf (f, "%r%s", regno,
13491 regno == LAST_ARG_REGNUM ? "" : ", ");
13493 fprintf (f, "}\n");
13496 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13497 SP_REGNUM, SP_REGNUM,
13498 current_function_pretend_args_size);
13500 /* We don't need to record the stores for unwinding (would it
13501 help the debugger any if we did?), but record the change in
13502 the stack pointer. */
13503 if (dwarf2out_do_frame ())
13505 char *l = dwarf2out_cfi_label ();
13507 cfa_offset = cfa_offset + current_function_pretend_args_size;
13508 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13512 /* Get the registers we are going to push. */
13513 live_regs_mask = thumb_compute_save_reg_mask ();
13514 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13515 l_mask = live_regs_mask & 0x40ff;
13516 /* Then count how many other high registers will need to be pushed. */
13517 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13519 if (TARGET_BACKTRACE)
13522 unsigned work_register;
13524 /* We have been asked to create a stack backtrace structure.
13525 The code looks like this:
13529 0 sub SP, #16 Reserve space for 4 registers.
13530 2 push {R7} Push low registers.
13531 4 add R7, SP, #20 Get the stack pointer before the push.
13532 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13533 8 mov R7, PC Get hold of the start of this code plus 12.
13534 10 str R7, [SP, #16] Store it.
13535 12 mov R7, FP Get hold of the current frame pointer.
13536 14 str R7, [SP, #4] Store it.
13537 16 mov R7, LR Get hold of the current return address.
13538 18 str R7, [SP, #12] Store it.
13539 20 add R7, SP, #16 Point at the start of the backtrace structure.
13540 22 mov FP, R7 Put this value into the frame pointer. */
13542 work_register = thumb_find_work_register (live_regs_mask);
13544 if (ARM_EABI_UNWIND_TABLES)
13545 asm_fprintf (f, "\t.pad #16\n");
13548 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13549 SP_REGNUM, SP_REGNUM);
13551 if (dwarf2out_do_frame ())
13553 char *l = dwarf2out_cfi_label ();
13555 cfa_offset = cfa_offset + 16;
13556 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13561 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13562 offset = bit_count (l_mask) * UNITS_PER_WORD;
13567 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13568 offset + 16 + current_function_pretend_args_size);
13570 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13573 /* Make sure that the instruction fetching the PC is in the right place
13574 to calculate "start of backtrace creation code + 12". */
13577 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13578 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13580 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13581 ARM_HARD_FRAME_POINTER_REGNUM);
13582 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13587 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13588 ARM_HARD_FRAME_POINTER_REGNUM);
13589 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13591 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13592 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13596 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13597 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13599 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13601 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13602 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13604 /* Optimization: If we are not pushing any low registers but we are going
13605 to push some high registers then delay our first push. This will just
13606 be a push of LR and we can combine it with the push of the first high
13608 else if ((l_mask & 0xff) != 0
13609 || (high_regs_pushed == 0 && l_mask))
13610 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13612 if (high_regs_pushed)
13614 unsigned pushable_regs;
13615 unsigned next_hi_reg;
13617 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13618 if (live_regs_mask & (1 << next_hi_reg))
13621 pushable_regs = l_mask & 0xff;
13623 if (pushable_regs == 0)
13624 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13626 while (high_regs_pushed > 0)
13628 unsigned long real_regs_mask = 0;
13630 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
13632 if (pushable_regs & (1 << regno))
13634 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13636 high_regs_pushed --;
13637 real_regs_mask |= (1 << next_hi_reg);
13639 if (high_regs_pushed)
13641 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
13643 if (live_regs_mask & (1 << next_hi_reg))
13648 pushable_regs &= ~((1 << regno) - 1);
13654 /* If we had to find a work register and we have not yet
13655 saved the LR then add it to the list of regs to push. */
13656 if (l_mask == (1 << LR_REGNUM))
13658 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
13660 real_regs_mask | (1 << LR_REGNUM));
13664 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13669 /* Handle the case of a double word load into a low register from
13670 a computed memory address. The computed address may involve a
13671 register which is overwritten by the load. */
13673 thumb_load_double_from_address (rtx *operands)
13681 gcc_assert (GET_CODE (operands[0]) == REG);
13682 gcc_assert (GET_CODE (operands[1]) == MEM);
13684 /* Get the memory address. */
13685 addr = XEXP (operands[1], 0);
13687 /* Work out how the memory address is computed. */
13688 switch (GET_CODE (addr))
13691 operands[2] = adjust_address (operands[1], SImode, 4);
13693 if (REGNO (operands[0]) == REGNO (addr))
13695 output_asm_insn ("ldr\t%H0, %2", operands);
13696 output_asm_insn ("ldr\t%0, %1", operands);
13700 output_asm_insn ("ldr\t%0, %1", operands);
13701 output_asm_insn ("ldr\t%H0, %2", operands);
13706 /* Compute <address> + 4 for the high order load. */
13707 operands[2] = adjust_address (operands[1], SImode, 4);
13709 output_asm_insn ("ldr\t%0, %1", operands);
13710 output_asm_insn ("ldr\t%H0, %2", operands);
13714 arg1 = XEXP (addr, 0);
13715 arg2 = XEXP (addr, 1);
13717 if (CONSTANT_P (arg1))
13718 base = arg2, offset = arg1;
13720 base = arg1, offset = arg2;
13722 gcc_assert (GET_CODE (base) == REG);
13724 /* Catch the case of <address> = <reg> + <reg> */
13725 if (GET_CODE (offset) == REG)
13727 int reg_offset = REGNO (offset);
13728 int reg_base = REGNO (base);
13729 int reg_dest = REGNO (operands[0]);
13731 /* Add the base and offset registers together into the
13732 higher destination register. */
13733 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13734 reg_dest + 1, reg_base, reg_offset);
13736 /* Load the lower destination register from the address in
13737 the higher destination register. */
13738 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13739 reg_dest, reg_dest + 1);
13741 /* Load the higher destination register from its own address
13743 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13744 reg_dest + 1, reg_dest + 1);
13748 /* Compute <address> + 4 for the high order load. */
13749 operands[2] = adjust_address (operands[1], SImode, 4);
13751 /* If the computed address is held in the low order register
13752 then load the high order register first, otherwise always
13753 load the low order register first. */
13754 if (REGNO (operands[0]) == REGNO (base))
13756 output_asm_insn ("ldr\t%H0, %2", operands);
13757 output_asm_insn ("ldr\t%0, %1", operands);
13761 output_asm_insn ("ldr\t%0, %1", operands);
13762 output_asm_insn ("ldr\t%H0, %2", operands);
13768 /* With no registers to worry about we can just load the value
13770 operands[2] = adjust_address (operands[1], SImode, 4);
13772 output_asm_insn ("ldr\t%H0, %2", operands);
13773 output_asm_insn ("ldr\t%0, %1", operands);
13777 gcc_unreachable ();
13784 thumb_output_move_mem_multiple (int n, rtx *operands)
13791 if (REGNO (operands[4]) > REGNO (operands[5]))
13794 operands[4] = operands[5];
13797 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13798 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13802 if (REGNO (operands[4]) > REGNO (operands[5]))
13805 operands[4] = operands[5];
13808 if (REGNO (operands[5]) > REGNO (operands[6]))
13811 operands[5] = operands[6];
13814 if (REGNO (operands[4]) > REGNO (operands[5]))
13817 operands[4] = operands[5];
13821 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13822 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13826 gcc_unreachable ();
13832 /* Output a call-via instruction for thumb state. */
13834 thumb_call_via_reg (rtx reg)
13836 int regno = REGNO (reg);
13839 gcc_assert (regno < LR_REGNUM);
13841 /* If we are in the normal text section we can use a single instance
13842 per compilation unit. If we are doing function sections, then we need
13843 an entry per section, since we can't rely on reachability. */
13844 if (in_text_section ())
13846 thumb_call_reg_needed = 1;
13848 if (thumb_call_via_label[regno] == NULL)
13849 thumb_call_via_label[regno] = gen_label_rtx ();
13850 labelp = thumb_call_via_label + regno;
13854 if (cfun->machine->call_via[regno] == NULL)
13855 cfun->machine->call_via[regno] = gen_label_rtx ();
13856 labelp = cfun->machine->call_via + regno;
13859 output_asm_insn ("bl\t%a0", labelp);
13863 /* Routines for generating rtl. */
13865 thumb_expand_movmemqi (rtx *operands)
13867 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13868 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13869 HOST_WIDE_INT len = INTVAL (operands[2]);
13870 HOST_WIDE_INT offset = 0;
13874 emit_insn (gen_movmem12b (out, in, out, in));
13880 emit_insn (gen_movmem8b (out, in, out, in));
13886 rtx reg = gen_reg_rtx (SImode);
13887 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13888 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13895 rtx reg = gen_reg_rtx (HImode);
13896 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13897 plus_constant (in, offset))));
13898 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13906 rtx reg = gen_reg_rtx (QImode);
13907 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13908 plus_constant (in, offset))));
13909 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13915 thumb_reload_out_hi (rtx *operands)
13917 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13920 /* Handle reading a half-word from memory during reload. */
13922 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13924 gcc_unreachable ();
13927 /* Return the length of a function name prefix
13928 that starts with the character 'c'. */
13930 arm_get_strip_length (int c)
13934 ARM_NAME_ENCODING_LENGTHS
13939 /* Return a pointer to a function's name with any
13940 and all prefix encodings stripped from it. */
13942 arm_strip_name_encoding (const char *name)
13946 while ((skip = arm_get_strip_length (* name)))
13952 /* If there is a '*' anywhere in the name's prefix, then
13953 emit the stripped name verbatim, otherwise prepend an
13954 underscore if leading underscores are being used. */
13956 arm_asm_output_labelref (FILE *stream, const char *name)
13961 while ((skip = arm_get_strip_length (* name)))
13963 verbatim |= (*name == '*');
13968 fputs (name, stream);
13970 asm_fprintf (stream, "%U%s", name);
13974 arm_file_end (void)
13978 if (! thumb_call_reg_needed)
13982 asm_fprintf (asm_out_file, "\t.code 16\n");
13983 ASM_OUTPUT_ALIGN (asm_out_file, 1);
13985 for (regno = 0; regno < LR_REGNUM; regno++)
13987 rtx label = thumb_call_via_label[regno];
13991 targetm.asm_out.internal_label (asm_out_file, "L",
13992 CODE_LABEL_NUMBER (label));
13993 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
14000 #ifdef AOF_ASSEMBLER
14001 /* Special functions only needed when producing AOF syntax assembler. */
14005 struct pic_chain * next;
14006 const char * symname;
14009 static struct pic_chain * aof_pic_chain = NULL;
14012 aof_pic_entry (rtx x)
14014 struct pic_chain ** chainp;
14017 if (aof_pic_label == NULL_RTX)
14019 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14022 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14023 offset += 4, chainp = &(*chainp)->next)
14024 if ((*chainp)->symname == XSTR (x, 0))
14025 return plus_constant (aof_pic_label, offset);
14027 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14028 (*chainp)->next = NULL;
14029 (*chainp)->symname = XSTR (x, 0);
14030 return plus_constant (aof_pic_label, offset);
14034 aof_dump_pic_table (FILE *f)
14036 struct pic_chain * chain;
14038 if (aof_pic_chain == NULL)
14041 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14042 PIC_OFFSET_TABLE_REGNUM,
14043 PIC_OFFSET_TABLE_REGNUM);
14044 fputs ("|x$adcons|\n", f);
14046 for (chain = aof_pic_chain; chain; chain = chain->next)
14048 fputs ("\tDCD\t", f);
14049 assemble_name (f, chain->symname);
14054 int arm_text_section_count = 1;
14057 aof_text_section (void )
14059 static char buf[100];
14060 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14061 arm_text_section_count++);
14063 strcat (buf, ", PIC, REENTRANT");
14067 static int arm_data_section_count = 1;
14070 aof_data_section (void)
14072 static char buf[100];
14073 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14077 /* The AOF assembler is religiously strict about declarations of
14078 imported and exported symbols, so that it is impossible to declare
14079 a function as imported near the beginning of the file, and then to
14080 export it later on. It is, however, possible to delay the decision
14081 until all the functions in the file have been compiled. To get
14082 around this, we maintain a list of the imports and exports, and
14083 delete from it any that are subsequently defined. At the end of
14084 compilation we spit the remainder of the list out before the END
14089 struct import * next;
14093 static struct import * imports_list = NULL;
14096 aof_add_import (const char *name)
14098 struct import * new;
14100 for (new = imports_list; new; new = new->next)
14101 if (new->name == name)
14104 new = (struct import *) xmalloc (sizeof (struct import));
14105 new->next = imports_list;
14106 imports_list = new;
14111 aof_delete_import (const char *name)
14113 struct import ** old;
14115 for (old = &imports_list; *old; old = & (*old)->next)
14117 if ((*old)->name == name)
14119 *old = (*old)->next;
14125 int arm_main_function = 0;
14128 aof_dump_imports (FILE *f)
14130 /* The AOF assembler needs this to cause the startup code to be extracted
14131 from the library. Brining in __main causes the whole thing to work
14133 if (arm_main_function)
14136 fputs ("\tIMPORT __main\n", f);
14137 fputs ("\tDCD __main\n", f);
14140 /* Now dump the remaining imports. */
14141 while (imports_list)
14143 fprintf (f, "\tIMPORT\t");
14144 assemble_name (f, imports_list->name);
14146 imports_list = imports_list->next;
14151 aof_globalize_label (FILE *stream, const char *name)
14153 default_globalize_label (stream, name);
14154 if (! strcmp (name, "main"))
14155 arm_main_function = 1;
14159 aof_file_start (void)
14161 fputs ("__r0\tRN\t0\n", asm_out_file);
14162 fputs ("__a1\tRN\t0\n", asm_out_file);
14163 fputs ("__a2\tRN\t1\n", asm_out_file);
14164 fputs ("__a3\tRN\t2\n", asm_out_file);
14165 fputs ("__a4\tRN\t3\n", asm_out_file);
14166 fputs ("__v1\tRN\t4\n", asm_out_file);
14167 fputs ("__v2\tRN\t5\n", asm_out_file);
14168 fputs ("__v3\tRN\t6\n", asm_out_file);
14169 fputs ("__v4\tRN\t7\n", asm_out_file);
14170 fputs ("__v5\tRN\t8\n", asm_out_file);
14171 fputs ("__v6\tRN\t9\n", asm_out_file);
14172 fputs ("__sl\tRN\t10\n", asm_out_file);
14173 fputs ("__fp\tRN\t11\n", asm_out_file);
14174 fputs ("__ip\tRN\t12\n", asm_out_file);
14175 fputs ("__sp\tRN\t13\n", asm_out_file);
14176 fputs ("__lr\tRN\t14\n", asm_out_file);
14177 fputs ("__pc\tRN\t15\n", asm_out_file);
14178 fputs ("__f0\tFN\t0\n", asm_out_file);
14179 fputs ("__f1\tFN\t1\n", asm_out_file);
14180 fputs ("__f2\tFN\t2\n", asm_out_file);
14181 fputs ("__f3\tFN\t3\n", asm_out_file);
14182 fputs ("__f4\tFN\t4\n", asm_out_file);
14183 fputs ("__f5\tFN\t5\n", asm_out_file);
14184 fputs ("__f6\tFN\t6\n", asm_out_file);
14185 fputs ("__f7\tFN\t7\n", asm_out_file);
14190 aof_file_end (void)
14193 aof_dump_pic_table (asm_out_file);
14195 aof_dump_imports (asm_out_file);
14196 fputs ("\tEND\n", asm_out_file);
14198 #endif /* AOF_ASSEMBLER */
14201 /* Symbols in the text segment can be accessed without indirecting via the
14202 constant pool; it may take an extra binary operation, but this is still
14203 faster than indirecting via memory. Don't do this when not optimizing,
14204 since we won't be calculating al of the offsets necessary to do this
14208 arm_encode_section_info (tree decl, rtx rtl, int first)
14210 /* This doesn't work with AOF syntax, since the string table may be in
14211 a different AREA. */
14212 #ifndef AOF_ASSEMBLER
14213 if (optimize > 0 && TREE_CONSTANT (decl))
14214 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14217 /* If we are referencing a function that is weak then encode a long call
14218 flag in the function name, otherwise if the function is static or
14219 or known to be defined in this file then encode a short call flag. */
14220 if (first && DECL_P (decl))
14222 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14223 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14224 else if (! TREE_PUBLIC (decl))
14225 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14228 #endif /* !ARM_PE */
14231 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14233 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14234 && !strcmp (prefix, "L"))
14236 arm_ccfsm_state = 0;
14237 arm_target_insn = NULL;
14239 default_internal_label (stream, prefix, labelno);
14242 /* Output code to add DELTA to the first argument, and then jump
14243 to FUNCTION. Used for C++ multiple inheritance. */
14245 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14246 HOST_WIDE_INT delta,
14247 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14250 static int thunk_label = 0;
14252 int mi_delta = delta;
14253 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14255 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14258 mi_delta = - mi_delta;
14261 int labelno = thunk_label++;
14262 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14263 fputs ("\tldr\tr12, ", file);
14264 assemble_name (file, label);
14265 fputc ('\n', file);
14267 while (mi_delta != 0)
14269 if ((mi_delta & (3 << shift)) == 0)
14273 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14274 mi_op, this_regno, this_regno,
14275 mi_delta & (0xff << shift));
14276 mi_delta &= ~(0xff << shift);
14282 fprintf (file, "\tbx\tr12\n");
14283 ASM_OUTPUT_ALIGN (file, 2);
14284 assemble_name (file, label);
14285 fputs (":\n", file);
14286 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14290 fputs ("\tb\t", file);
14291 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14292 if (NEED_PLT_RELOC)
14293 fputs ("(PLT)", file);
14294 fputc ('\n', file);
14299 arm_emit_vector_const (FILE *file, rtx x)
14302 const char * pattern;
14304 gcc_assert (GET_CODE (x) == CONST_VECTOR);
14306 switch (GET_MODE (x))
14308 case V2SImode: pattern = "%08x"; break;
14309 case V4HImode: pattern = "%04x"; break;
14310 case V8QImode: pattern = "%02x"; break;
14311 default: gcc_unreachable ();
14314 fprintf (file, "0x");
14315 for (i = CONST_VECTOR_NUNITS (x); i--;)
14319 element = CONST_VECTOR_ELT (x, i);
14320 fprintf (file, pattern, INTVAL (element));
14327 arm_output_load_gr (rtx *operands)
14334 if (GET_CODE (operands [1]) != MEM
14335 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14336 || GET_CODE (reg = XEXP (sum, 0)) != REG
14337 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14338 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14339 return "wldrw%?\t%0, %1";
14341 /* Fix up an out-of-range load of a GR register. */
14342 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14343 wcgr = operands[0];
14345 output_asm_insn ("ldr%?\t%0, %1", operands);
14347 operands[0] = wcgr;
14349 output_asm_insn ("tmcr%?\t%0, %1", operands);
14350 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14356 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14357 int incoming ATTRIBUTE_UNUSED)
14360 /* FIXME: The ARM backend has special code to handle structure
14361 returns, and will reserve its own hidden first argument. So
14362 if this macro is enabled a *second* hidden argument will be
14363 reserved, which will break binary compatibility with old
14364 toolchains and also thunk handling. One day this should be
14368 /* Register in which address to store a structure value
14369 is passed to a function. */
14370 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14374 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14376 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14377 named arg and all anonymous args onto the stack.
14378 XXX I know the prologue shouldn't be pushing registers, but it is faster
14382 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14383 enum machine_mode mode ATTRIBUTE_UNUSED,
14384 tree type ATTRIBUTE_UNUSED,
14386 int second_time ATTRIBUTE_UNUSED)
14388 cfun->machine->uses_anonymous_args = 1;
14389 if (cum->nregs < NUM_ARG_REGS)
14390 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14393 /* Return nonzero if the CONSUMER instruction (a store) does not need
14394 PRODUCER's value to calculate the address. */
14397 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14399 rtx value = PATTERN (producer);
14400 rtx addr = PATTERN (consumer);
14402 if (GET_CODE (value) == COND_EXEC)
14403 value = COND_EXEC_CODE (value);
14404 if (GET_CODE (value) == PARALLEL)
14405 value = XVECEXP (value, 0, 0);
14406 value = XEXP (value, 0);
14407 if (GET_CODE (addr) == COND_EXEC)
14408 addr = COND_EXEC_CODE (addr);
14409 if (GET_CODE (addr) == PARALLEL)
14410 addr = XVECEXP (addr, 0, 0);
14411 addr = XEXP (addr, 0);
14413 return !reg_overlap_mentioned_p (value, addr);
14416 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14417 have an early register shift value or amount dependency on the
14418 result of PRODUCER. */
14421 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14423 rtx value = PATTERN (producer);
14424 rtx op = PATTERN (consumer);
14427 if (GET_CODE (value) == COND_EXEC)
14428 value = COND_EXEC_CODE (value);
14429 if (GET_CODE (value) == PARALLEL)
14430 value = XVECEXP (value, 0, 0);
14431 value = XEXP (value, 0);
14432 if (GET_CODE (op) == COND_EXEC)
14433 op = COND_EXEC_CODE (op);
14434 if (GET_CODE (op) == PARALLEL)
14435 op = XVECEXP (op, 0, 0);
14438 early_op = XEXP (op, 0);
14439 /* This is either an actual independent shift, or a shift applied to
14440 the first operand of another operation. We want the whole shift
14442 if (GET_CODE (early_op) == REG)
14445 return !reg_overlap_mentioned_p (value, early_op);
14448 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14449 have an early register shift value dependency on the result of
14453 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14455 rtx value = PATTERN (producer);
14456 rtx op = PATTERN (consumer);
14459 if (GET_CODE (value) == COND_EXEC)
14460 value = COND_EXEC_CODE (value);
14461 if (GET_CODE (value) == PARALLEL)
14462 value = XVECEXP (value, 0, 0);
14463 value = XEXP (value, 0);
14464 if (GET_CODE (op) == COND_EXEC)
14465 op = COND_EXEC_CODE (op);
14466 if (GET_CODE (op) == PARALLEL)
14467 op = XVECEXP (op, 0, 0);
14470 early_op = XEXP (op, 0);
14472 /* This is either an actual independent shift, or a shift applied to
14473 the first operand of another operation. We want the value being
14474 shifted, in either case. */
14475 if (GET_CODE (early_op) != REG)
14476 early_op = XEXP (early_op, 0);
14478 return !reg_overlap_mentioned_p (value, early_op);
14481 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14482 have an early register mult dependency on the result of
14486 arm_no_early_mul_dep (rtx producer, rtx consumer)
14488 rtx value = PATTERN (producer);
14489 rtx op = PATTERN (consumer);
14491 if (GET_CODE (value) == COND_EXEC)
14492 value = COND_EXEC_CODE (value);
14493 if (GET_CODE (value) == PARALLEL)
14494 value = XVECEXP (value, 0, 0);
14495 value = XEXP (value, 0);
14496 if (GET_CODE (op) == COND_EXEC)
14497 op = COND_EXEC_CODE (op);
14498 if (GET_CODE (op) == PARALLEL)
14499 op = XVECEXP (op, 0, 0);
14502 return (GET_CODE (op) == PLUS
14503 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14507 /* We can't rely on the caller doing the proper promotion when
14508 using APCS or ATPCS. */
14511 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14513 return !TARGET_AAPCS_BASED;
14517 /* AAPCS based ABIs use short enums by default. */
14520 arm_default_short_enums (void)
14522 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
14526 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14529 arm_align_anon_bitfield (void)
14531 return TARGET_AAPCS_BASED;
14535 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14538 arm_cxx_guard_type (void)
14540 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14544 /* The EABI says test the least significant bit of a guard variable. */
14547 arm_cxx_guard_mask_bit (void)
14549 return TARGET_AAPCS_BASED;
14553 /* The EABI specifies that all array cookies are 8 bytes long. */
14556 arm_get_cookie_size (tree type)
14560 if (!TARGET_AAPCS_BASED)
14561 return default_cxx_get_cookie_size (type);
14563 size = build_int_cst (sizetype, 8);
14568 /* The EABI says that array cookies should also contain the element size. */
14571 arm_cookie_has_size (void)
14573 return TARGET_AAPCS_BASED;
14577 /* The EABI says constructors and destructors should return a pointer to
14578 the object constructed/destroyed. */
14581 arm_cxx_cdtor_returns_this (void)
14583 return TARGET_AAPCS_BASED;
14586 /* The EABI says that an inline function may never be the key
14590 arm_cxx_key_method_may_be_inline (void)
14592 return !TARGET_AAPCS_BASED;
14596 arm_cxx_determine_class_data_visibility (tree decl)
14598 if (!TARGET_AAPCS_BASED)
14601 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14602 is exported. However, on systems without dynamic vague linkage,
14603 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14604 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
14605 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
14607 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
14608 DECL_VISIBILITY_SPECIFIED (decl) = 1;
14612 arm_cxx_class_data_always_comdat (void)
14614 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14615 vague linkage if the class has no key function. */
14616 return !TARGET_AAPCS_BASED;
14620 /* The EABI says __aeabi_atexit should be used to register static
14624 arm_cxx_use_aeabi_atexit (void)
14626 return TARGET_AAPCS_BASED;
14631 arm_set_return_address (rtx source, rtx scratch)
14633 arm_stack_offsets *offsets;
14634 HOST_WIDE_INT delta;
14636 unsigned long saved_regs;
14638 saved_regs = arm_compute_save_reg_mask ();
14640 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14641 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14644 if (frame_pointer_needed)
14645 addr = plus_constant(hard_frame_pointer_rtx, -4);
14648 /* LR will be the first saved register. */
14649 offsets = arm_get_frame_offsets ();
14650 delta = offsets->outgoing_args - (offsets->frame + 4);
14655 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14656 GEN_INT (delta & ~4095)));
14661 addr = stack_pointer_rtx;
14663 addr = plus_constant (addr, delta);
14665 emit_move_insn (gen_frame_mem (Pmode, addr), source);
14671 thumb_set_return_address (rtx source, rtx scratch)
14673 arm_stack_offsets *offsets;
14674 HOST_WIDE_INT delta;
14677 unsigned long mask;
14679 emit_insn (gen_rtx_USE (VOIDmode, source));
14681 mask = thumb_compute_save_reg_mask ();
14682 if (mask & (1 << LR_REGNUM))
14684 offsets = arm_get_frame_offsets ();
14686 /* Find the saved regs. */
14687 if (frame_pointer_needed)
14689 delta = offsets->soft_frame - offsets->saved_args;
14690 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14694 delta = offsets->outgoing_args - offsets->saved_args;
14697 /* Allow for the stack frame. */
14698 if (TARGET_BACKTRACE)
14700 /* The link register is always the first saved register. */
14703 /* Construct the address. */
14704 addr = gen_rtx_REG (SImode, reg);
14705 if ((reg != SP_REGNUM && delta >= 128)
14708 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14709 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14713 addr = plus_constant (addr, delta);
14715 emit_move_insn (gen_frame_mem (Pmode, addr), source);
14718 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14721 /* Implements target hook vector_mode_supported_p. */
14723 arm_vector_mode_supported_p (enum machine_mode mode)
14725 if ((mode == V2SImode)
14726 || (mode == V4HImode)
14727 || (mode == V8QImode))
14733 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14734 ARM insns and therefore guarantee that the shift count is modulo 256.
14735 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14736 guarantee no particular behavior for out-of-range counts. */
14738 static unsigned HOST_WIDE_INT
14739 arm_shift_truncation_mask (enum machine_mode mode)
14741 return mode == SImode ? 255 : 0;
14745 /* Map internal gcc register numbers to DWARF2 register numbers. */
14748 arm_dbx_register_number (unsigned int regno)
14753 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14754 compatibility. The EABI defines them as registers 96-103. */
14755 if (IS_FPA_REGNUM (regno))
14756 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
14758 if (IS_VFP_REGNUM (regno))
14759 return 64 + regno - FIRST_VFP_REGNUM;
14761 if (IS_IWMMXT_GR_REGNUM (regno))
14762 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
14764 if (IS_IWMMXT_REGNUM (regno))
14765 return 112 + regno - FIRST_IWMMXT_REGNUM;
14767 gcc_unreachable ();
14771 #ifdef TARGET_UNWIND_INFO
14772 /* Emit unwind directives for a store-multiple instruction. This should
14773 only ever be generated by the function prologue code, so we expect it
14774 to have a particular form. */
14777 arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
14780 HOST_WIDE_INT offset;
14781 HOST_WIDE_INT nregs;
14787 /* First insn will adjust the stack pointer. */
14788 e = XVECEXP (p, 0, 0);
14789 if (GET_CODE (e) != SET
14790 || GET_CODE (XEXP (e, 0)) != REG
14791 || REGNO (XEXP (e, 0)) != SP_REGNUM
14792 || GET_CODE (XEXP (e, 1)) != PLUS)
14795 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
14796 nregs = XVECLEN (p, 0) - 1;
14798 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
14801 /* The function prologue may also push pc, but not annotate it as it is
14802 never restored. We turn this into a stack pointer adjustment. */
14803 if (nregs * 4 == offset - 4)
14805 fprintf (asm_out_file, "\t.pad #4\n");
14810 else if (IS_VFP_REGNUM (reg))
14812 /* FPA register saves use an additional word. */
14816 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
14818 /* FPA registers are done differently. */
14819 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
14823 /* Unknown register type. */
14826 /* If the stack increment doesn't match the size of the saved registers,
14827 something has gone horribly wrong. */
14828 if (offset != nregs * reg_size)
14831 fprintf (asm_out_file, "\t.save {");
14835 /* The remaining insns will describe the stores. */
14836 for (i = 1; i <= nregs; i++)
14838 /* Expect (set (mem <addr>) (reg)).
14839 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
14840 e = XVECEXP (p, 0, i);
14841 if (GET_CODE (e) != SET
14842 || GET_CODE (XEXP (e, 0)) != MEM
14843 || GET_CODE (XEXP (e, 1)) != REG)
14846 reg = REGNO (XEXP (e, 1));
14851 fprintf (asm_out_file, ", ");
14852 /* We can't use %r for vfp because we need to use the
14853 double precision register names. */
14854 if (IS_VFP_REGNUM (reg))
14855 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
14857 asm_fprintf (asm_out_file, "%r", reg);
14859 #ifdef ENABLE_CHECKING
14860 /* Check that the addresses are consecutive. */
14861 e = XEXP (XEXP (e, 0), 0);
14862 if (GET_CODE (e) == PLUS)
14864 offset += reg_size;
14865 if (GET_CODE (XEXP (e, 0)) != REG
14866 || REGNO (XEXP (e, 0)) != SP_REGNUM
14867 || GET_CODE (XEXP (e, 1)) != CONST_INT
14868 || offset != INTVAL (XEXP (e, 1)))
14872 || GET_CODE (e) != REG
14873 || REGNO (e) != SP_REGNUM)
14877 fprintf (asm_out_file, "}\n");
14880 /* Emit unwind directives for a SET. */
14883 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
14890 switch (GET_CODE (e0))
14893 /* Pushing a single register. */
14894 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
14895 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
14896 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
14899 asm_fprintf (asm_out_file, "\t.save ");
14900 if (IS_VFP_REGNUM (REGNO (e1)))
14901 asm_fprintf(asm_out_file, "{d%d}\n",
14902 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
14904 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
14908 if (REGNO (e0) == SP_REGNUM)
14910 /* A stack increment. */
14911 if (GET_CODE (e1) != PLUS
14912 || GET_CODE (XEXP (e1, 0)) != REG
14913 || REGNO (XEXP (e1, 0)) != SP_REGNUM
14914 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14917 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
14918 -INTVAL (XEXP (e1, 1)));
14920 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
14922 HOST_WIDE_INT offset;
14925 if (GET_CODE (e1) == PLUS)
14927 if (GET_CODE (XEXP (e1, 0)) != REG
14928 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14930 reg = REGNO (XEXP (e1, 0));
14931 offset = INTVAL (XEXP (e1, 1));
14932 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
14933 HARD_FRAME_POINTER_REGNUM, reg,
14934 INTVAL (XEXP (e1, 1)));
14936 else if (GET_CODE (e1) == REG)
14939 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
14940 HARD_FRAME_POINTER_REGNUM, reg);
14945 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
14947 /* Move from sp to reg. */
14948 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
14960 /* Emit unwind directives for the given insn. */
14963 arm_unwind_emit (FILE * asm_out_file, rtx insn)
14967 if (!ARM_EABI_UNWIND_TABLES)
14970 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
14973 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
14975 pat = XEXP (pat, 0);
14977 pat = PATTERN (insn);
14979 switch (GET_CODE (pat))
14982 arm_unwind_emit_set (asm_out_file, pat);
14986 /* Store multiple. */
14987 arm_unwind_emit_stm (asm_out_file, pat);
14996 /* Output a reference from a function exception table to the type_info
14997 object X. The EABI specifies that the symbol should be relocated by
14998 an R_ARM_TARGET2 relocation. */
15001 arm_output_ttype (rtx x)
15003 fputs ("\t.word\t", asm_out_file);
15004 output_addr_const (asm_out_file, x);
15005 /* Use special relocations for symbol references. */
15006 if (GET_CODE (x) != CONST_INT)
15007 fputs ("(TARGET2)", asm_out_file);
15008 fputc ('\n', asm_out_file);
15012 #endif /* TARGET_UNWIND_INFO */
15015 /* Output unwind directives for the start/end of a function. */
15018 arm_output_fn_unwind (FILE * f, bool prologue)
15020 if (!ARM_EABI_UNWIND_TABLES)
15024 fputs ("\t.fnstart\n", f);
15026 fputs ("\t.fnend\n", f);