1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static unsigned long thumb_compute_save_reg_mask (void);
75 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
76 static rtx emit_multi_reg_push (int);
77 static rtx emit_sfm (int, int);
79 static bool arm_assemble_integer (rtx, unsigned int, int);
81 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
82 static arm_cc get_arm_condition_code (rtx);
83 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
84 static rtx is_jump_table (rtx);
85 static const char *output_multi_immediate (rtx *, const char *, const char *,
87 static void print_multi_reg (FILE *, const char *, int, int);
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static int number_of_first_bit_set (int);
91 static void replace_symbols_in_block (tree, rtx, rtx);
92 static void thumb_exit (FILE *, int);
93 static void thumb_pushpop (FILE *, int, int, int *, int);
94 static rtx is_jump_table (rtx);
95 static HOST_WIDE_INT get_jump_table_size (rtx);
96 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_forward_ref (Mfix *);
98 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
99 static Mnode *add_minipool_backward_ref (Mfix *);
100 static void assign_minipool_offsets (Mfix *);
101 static void arm_print_value (FILE *, rtx);
102 static void dump_minipool (rtx);
103 static int arm_barrier_cost (rtx);
104 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
105 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
106 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
108 static void arm_reorg (void);
109 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
110 static int current_file_function_operand (rtx);
111 static unsigned long arm_compute_save_reg0_reg12_mask (void);
112 static unsigned long arm_compute_save_reg_mask (void);
113 static unsigned long arm_isr_value (tree);
114 static unsigned long arm_compute_func_type (void);
115 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
116 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_named_section (const char *, unsigned int);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void aof_globalize_label (FILE *, const char *);
156 static void aof_dump_imports (FILE *);
157 static void aof_dump_pic_table (FILE *);
158 static void aof_file_start (void);
159 static void aof_file_end (void);
161 static rtx arm_struct_value_rtx (tree, int);
162 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
164 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
165 enum machine_mode, tree, bool);
166 static bool arm_promote_prototypes (tree);
167 static bool arm_default_short_enums (void);
168 static bool arm_align_anon_bitfield (void);
170 static tree arm_cxx_guard_type (void);
171 static bool arm_cxx_guard_mask_bit (void);
172 static tree arm_get_cookie_size (tree);
173 static bool arm_cookie_has_size (void);
174 static bool arm_cxx_cdtor_returns_this (void);
175 static void arm_init_libfuncs (void);
178 /* Initialize the GCC target structure. */
179 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
180 #undef TARGET_MERGE_DECL_ATTRIBUTES
181 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
184 #undef TARGET_ATTRIBUTE_TABLE
185 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
188 #undef TARGET_ASM_BYTE_OP
189 #define TARGET_ASM_BYTE_OP "\tDCB\t"
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
194 #undef TARGET_ASM_GLOBALIZE_LABEL
195 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
196 #undef TARGET_ASM_FILE_START
197 #define TARGET_ASM_FILE_START aof_file_start
198 #undef TARGET_ASM_FILE_END
199 #define TARGET_ASM_FILE_END aof_file_end
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP NULL
203 #undef TARGET_ASM_INTEGER
204 #define TARGET_ASM_INTEGER arm_assemble_integer
207 #undef TARGET_ASM_FUNCTION_PROLOGUE
208 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
210 #undef TARGET_ASM_FUNCTION_EPILOGUE
211 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
213 #undef TARGET_COMP_TYPE_ATTRIBUTES
214 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
216 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
217 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
219 #undef TARGET_SCHED_ADJUST_COST
220 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
222 #undef TARGET_ENCODE_SECTION_INFO
224 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
226 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
229 #undef TARGET_STRIP_NAME_ENCODING
230 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
232 #undef TARGET_ASM_INTERNAL_LABEL
233 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
235 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
236 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
238 #undef TARGET_ASM_OUTPUT_MI_THUNK
239 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
240 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
241 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
243 /* This will be overridden in arm_override_options. */
244 #undef TARGET_RTX_COSTS
245 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
246 #undef TARGET_ADDRESS_COST
247 #define TARGET_ADDRESS_COST arm_address_cost
249 #undef TARGET_VECTOR_MODE_SUPPORTED_P
250 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
252 #undef TARGET_MACHINE_DEPENDENT_REORG
253 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
255 #undef TARGET_INIT_BUILTINS
256 #define TARGET_INIT_BUILTINS arm_init_builtins
257 #undef TARGET_EXPAND_BUILTIN
258 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
260 #undef TARGET_INIT_LIBFUNCS
261 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
263 #undef TARGET_PROMOTE_FUNCTION_ARGS
264 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
265 #undef TARGET_PROMOTE_FUNCTION_RETURN
266 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
267 #undef TARGET_PROMOTE_PROTOTYPES
268 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
269 #undef TARGET_PASS_BY_REFERENCE
270 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
272 #undef TARGET_STRUCT_VALUE_RTX
273 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
275 #undef TARGET_SETUP_INCOMING_VARARGS
276 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
278 #undef TARGET_DEFAULT_SHORT_ENUMS
279 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
281 #undef TARGET_ALIGN_ANON_BITFIELD
282 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
284 #undef TARGET_CXX_GUARD_TYPE
285 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
287 #undef TARGET_CXX_GUARD_MASK_BIT
288 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
290 #undef TARGET_CXX_GET_COOKIE_SIZE
291 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
293 #undef TARGET_CXX_COOKIE_HAS_SIZE
294 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
296 #undef TARGET_CXX_CDTOR_RETURNS_THIS
297 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
299 struct gcc_target targetm = TARGET_INITIALIZER;
301 /* Obstack for minipool constant handling. */
302 static struct obstack minipool_obstack;
303 static char * minipool_startobj;
305 /* The maximum number of insns skipped which
306 will be conditionalised if possible. */
307 static int max_insns_skipped = 5;
309 extern FILE * asm_out_file;
311 /* True if we are currently building a constant table. */
312 int making_const_table;
314 /* Define the information needed to generate branch insns. This is
315 stored from the compare operation. */
316 rtx arm_compare_op0, arm_compare_op1;
318 /* The processor for which instructions should be scheduled. */
319 enum processor_type arm_tune = arm_none;
321 /* Which floating point model to use. */
322 enum arm_fp_model arm_fp_model;
324 /* Which floating point hardware is available. */
325 enum fputype arm_fpu_arch;
327 /* Which floating point hardware to schedule for. */
328 enum fputype arm_fpu_tune;
330 /* Whether to use floating point hardware. */
331 enum float_abi_type arm_float_abi;
333 /* Which ABI to use. */
334 enum arm_abi_type arm_abi;
336 /* Set by the -mfpu=... option. */
337 const char * target_fpu_name = NULL;
339 /* Set by the -mfpe=... option. */
340 const char * target_fpe_name = NULL;
342 /* Set by the -mfloat-abi=... option. */
343 const char * target_float_abi_name = NULL;
345 /* Set by the -mabi=... option. */
346 const char * target_abi_name = NULL;
348 /* Used to parse -mstructure_size_boundary command line option. */
349 const char * structure_size_string = NULL;
350 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
352 /* Bit values used to identify processor capabilities. */
353 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
354 #define FL_ARCH3M (1 << 1) /* Extended multiply */
355 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
356 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
357 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
358 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
359 #define FL_THUMB (1 << 6) /* Thumb aware */
360 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
361 #define FL_STRONG (1 << 8) /* StrongARM */
362 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
363 #define FL_XSCALE (1 << 10) /* XScale */
364 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
365 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
366 media instructions. */
367 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
369 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
371 #define FL_FOR_ARCH2 0
372 #define FL_FOR_ARCH3 FL_MODE32
373 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
374 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
375 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
376 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
377 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
378 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
379 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
380 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
381 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
382 #define FL_FOR_ARCH6J FL_FOR_ARCH6
384 /* The bits in this mask specify which
385 instructions we are allowed to generate. */
386 static unsigned long insn_flags = 0;
388 /* The bits in this mask specify which instruction scheduling options should
390 static unsigned long tune_flags = 0;
392 /* The following are used in the arm.md file as equivalents to bits
393 in the above two flag variables. */
395 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
398 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
401 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
404 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
407 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
410 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
413 /* Nonzero if this chip can benefit from load scheduling. */
414 int arm_ld_sched = 0;
416 /* Nonzero if this chip is a StrongARM. */
417 int arm_is_strong = 0;
419 /* Nonzero if this chip is a Cirrus variant. */
420 int arm_arch_cirrus = 0;
422 /* Nonzero if this chip supports Intel Wireless MMX technology. */
423 int arm_arch_iwmmxt = 0;
425 /* Nonzero if this chip is an XScale. */
426 int arm_arch_xscale = 0;
428 /* Nonzero if tuning for XScale */
429 int arm_tune_xscale = 0;
431 /* Nonzero if this chip is an ARM6 or an ARM7. */
432 int arm_is_6_or_7 = 0;
434 /* Nonzero if generating Thumb instructions. */
437 /* Nonzero if we should define __THUMB_INTERWORK__ in the
439 XXX This is a bit of a hack, it's intended to help work around
440 problems in GLD which doesn't understand that armv5t code is
441 interworking clean. */
442 int arm_cpp_interwork = 0;
444 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
445 must report the mode of the memory reference from PRINT_OPERAND to
446 PRINT_OPERAND_ADDRESS. */
447 enum machine_mode output_memory_reference_mode;
449 /* The register number to be used for the PIC offset register. */
450 const char * arm_pic_register_string = NULL;
451 int arm_pic_register = INVALID_REGNUM;
453 /* Set to 1 when a return insn is output, this means that the epilogue
455 int return_used_this_function;
457 /* Set to 1 after arm_reorg has started. Reset to start at the start of
458 the next function. */
459 static int after_arm_reorg = 0;
461 /* The maximum number of insns to be used when loading a constant. */
462 static int arm_constant_limit = 3;
464 /* For an explanation of these variables, see final_prescan_insn below. */
466 enum arm_cond_code arm_current_cc;
468 int arm_target_label;
470 /* The condition codes of the ARM, and the inverse function. */
471 static const char * const arm_condition_codes[] =
473 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
474 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
477 #define streq(string1, string2) (strcmp (string1, string2) == 0)
479 /* Initialization code. */
483 const char *const name;
484 enum processor_type core;
486 const unsigned long flags;
487 bool (* rtx_costs) (rtx, int, int, int *);
490 /* Not all of these give usefully different compilation alternatives,
491 but there is no simple way of generalizing them. */
492 static const struct processors all_cores[] =
495 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
496 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
497 #include "arm-cores.def"
499 {NULL, arm_none, NULL, 0, NULL}
502 static const struct processors all_architectures[] =
504 /* ARM Architectures */
505 /* We don't specify rtx_costs here as it will be figured out
508 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
509 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
510 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
511 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
512 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
513 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
514 implementations that support it, so we will leave it out for now. */
515 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
516 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
517 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
518 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
519 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
520 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
521 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
522 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
523 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
524 {NULL, arm_none, NULL, 0 , NULL}
527 /* This is a magic structure. The 'string' field is magically filled in
528 with a pointer to the value specified by the user on the command line
529 assuming that the user has specified such a value. */
531 struct arm_cpu_select arm_select[] =
533 /* string name processors */
534 { NULL, "-mcpu=", all_cores },
535 { NULL, "-march=", all_architectures },
536 { NULL, "-mtune=", all_cores }
540 /* The name of the proprocessor macro to define for this architecture. */
542 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
551 /* Available values for for -mfpu=. */
553 static const struct fpu_desc all_fpus[] =
555 {"fpa", FPUTYPE_FPA},
556 {"fpe2", FPUTYPE_FPA_EMU2},
557 {"fpe3", FPUTYPE_FPA_EMU2},
558 {"maverick", FPUTYPE_MAVERICK},
563 /* Floating point models used by the different hardware.
564 See fputype in arm.h. */
566 static const enum fputype fp_model_for_fpu[] =
568 /* No FP hardware. */
569 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
570 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
571 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
572 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
573 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
574 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
581 enum float_abi_type abi_type;
585 /* Available values for -mfloat-abi=. */
587 static const struct float_abi all_float_abis[] =
589 {"soft", ARM_FLOAT_ABI_SOFT},
590 {"softfp", ARM_FLOAT_ABI_SOFTFP},
591 {"hard", ARM_FLOAT_ABI_HARD}
598 enum arm_abi_type abi_type;
602 /* Available values for -mabi=. */
604 static const struct abi_name arm_all_abis[] =
606 {"apcs-gnu", ARM_ABI_APCS},
607 {"atpcs", ARM_ABI_ATPCS},
608 {"aapcs", ARM_ABI_AAPCS},
609 {"iwmmxt", ARM_ABI_IWMMXT}
612 /* Return the number of bits set in VALUE. */
614 bit_count (unsigned long value)
616 unsigned long count = 0;
621 value &= value - 1; /* Clear the least-significant set bit. */
627 /* Set up library functions uqniue to ARM. */
630 arm_init_libfuncs (void)
632 /* There are no special library functions unless we are using the
637 /* The functions below are described in Section 4 of the "Run-Time
638 ABI for the ARM architecture", Version 1.0. */
640 /* Double-precision floating-point arithmetic. Table 2. */
641 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
642 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
643 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
644 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
645 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
647 /* Double-precision comparisions. Table 3. */
648 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
649 set_optab_libfunc (ne_optab, DFmode, NULL);
650 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
651 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
652 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
653 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
654 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
656 /* Single-precision floating-point arithmetic. Table 4. */
657 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
658 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
659 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
660 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
661 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
663 /* Single-precision comparisions. Table 5. */
664 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
665 set_optab_libfunc (ne_optab, SFmode, NULL);
666 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
667 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
668 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
669 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
670 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
672 /* Floating-point to integer conversions. Table 6. */
673 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
674 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
675 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
676 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
677 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
678 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
679 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
680 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
682 /* Conversions between floating types. Table 7. */
683 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
684 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
686 /* Integer to floating-point converisons. Table 8. */
687 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
688 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
689 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
690 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
691 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
692 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
693 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
694 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
696 /* Long long. Table 9. */
697 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
698 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
699 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
700 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
701 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
702 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
703 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
704 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
706 /* Integer (32/32->32) division. \S 4.3.1. */
707 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
708 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
710 /* The divmod functions are designed so that they can be used for
711 plain division, even though they return both the quotient and the
712 remainder. The quotient is returned in the usual location (i.e.,
713 r0 for SImode, {r0, r1} for DImode), just as would be expected
714 for an ordinary division routine. Because the AAPCS calling
715 conventions specify that all of { r0, r1, r2, r3 } are
716 callee-saved registers, there is no need to tell the compiler
717 explicitly that those registers are clobbered by these
719 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
720 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
721 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
722 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
725 /* Fix up any incompatible options that the user has specified.
726 This has now turned into a maze. */
728 arm_override_options (void)
732 /* Set up the flags based on the cpu/architecture selected by the user. */
733 for (i = ARRAY_SIZE (arm_select); i--;)
735 struct arm_cpu_select * ptr = arm_select + i;
737 if (ptr->string != NULL && ptr->string[0] != '\0')
739 const struct processors * sel;
741 for (sel = ptr->processors; sel->name != NULL; sel++)
742 if (streq (ptr->string, sel->name))
744 /* Set the architecture define. */
746 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
748 /* Determine the processor core for which we should
749 tune code-generation. */
750 if (/* -mcpu= is a sensible default. */
752 /* If -march= is used, and -mcpu= has not been used,
753 assume that we should tune for a representative
754 CPU from that architecture. */
756 /* -mtune= overrides -mcpu= and -march=. */
758 arm_tune = (enum processor_type) (sel - ptr->processors);
762 /* If we have been given an architecture and a processor
763 make sure that they are compatible. We only generate
764 a warning though, and we prefer the CPU over the
766 if (insn_flags != 0 && (insn_flags ^ sel->flags))
767 warning ("switch -mcpu=%s conflicts with -march= switch",
770 insn_flags = sel->flags;
776 if (sel->name == NULL)
777 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
781 /* If the user did not specify a processor, choose one for them. */
784 const struct processors * sel;
786 enum processor_type cpu;
788 cpu = TARGET_CPU_DEFAULT;
791 #ifdef SUBTARGET_CPU_DEFAULT
792 /* Use the subtarget default CPU if none was specified by
794 cpu = SUBTARGET_CPU_DEFAULT;
796 /* Default to ARM6. */
800 sel = &all_cores[cpu];
802 insn_flags = sel->flags;
804 /* Now check to see if the user has specified some command line
805 switch that require certain abilities from the cpu. */
808 if (TARGET_INTERWORK || TARGET_THUMB)
810 sought |= (FL_THUMB | FL_MODE32);
812 /* There are no ARM processors that support both APCS-26 and
813 interworking. Therefore we force FL_MODE26 to be removed
814 from insn_flags here (if it was set), so that the search
815 below will always be able to find a compatible processor. */
816 insn_flags &= ~FL_MODE26;
819 if (sought != 0 && ((sought & insn_flags) != sought))
821 /* Try to locate a CPU type that supports all of the abilities
822 of the default CPU, plus the extra abilities requested by
824 for (sel = all_cores; sel->name != NULL; sel++)
825 if ((sel->flags & sought) == (sought | insn_flags))
828 if (sel->name == NULL)
830 unsigned current_bit_count = 0;
831 const struct processors * best_fit = NULL;
833 /* Ideally we would like to issue an error message here
834 saying that it was not possible to find a CPU compatible
835 with the default CPU, but which also supports the command
836 line options specified by the programmer, and so they
837 ought to use the -mcpu=<name> command line option to
838 override the default CPU type.
840 If we cannot find a cpu that has both the
841 characteristics of the default cpu and the given
842 command line options we scan the array again looking
844 for (sel = all_cores; sel->name != NULL; sel++)
845 if ((sel->flags & sought) == sought)
849 count = bit_count (sel->flags & insn_flags);
851 if (count >= current_bit_count)
854 current_bit_count = count;
858 if (best_fit == NULL)
864 insn_flags = sel->flags;
866 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
867 if (arm_tune == arm_none)
868 arm_tune = (enum processor_type) (sel - all_cores);
871 /* The processor for which we should tune should now have been
873 if (arm_tune == arm_none)
876 tune_flags = all_cores[(int)arm_tune].flags;
878 targetm.rtx_costs = arm_size_rtx_costs;
880 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
882 /* Make sure that the processor choice does not conflict with any of the
883 other command line choices. */
884 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
886 warning ("target CPU does not support interworking" );
887 target_flags &= ~ARM_FLAG_INTERWORK;
890 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
892 warning ("target CPU does not support THUMB instructions");
893 target_flags &= ~ARM_FLAG_THUMB;
896 if (TARGET_APCS_FRAME && TARGET_THUMB)
898 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
899 target_flags &= ~ARM_FLAG_APCS_FRAME;
902 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
903 from here where no function is being compiled currently. */
904 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
906 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
908 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
909 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
911 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
912 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
914 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
916 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
917 target_flags |= ARM_FLAG_APCS_FRAME;
920 if (TARGET_POKE_FUNCTION_NAME)
921 target_flags |= ARM_FLAG_APCS_FRAME;
923 if (TARGET_APCS_REENT && flag_pic)
924 error ("-fpic and -mapcs-reent are incompatible");
926 if (TARGET_APCS_REENT)
927 warning ("APCS reentrant code not supported. Ignored");
929 /* If this target is normally configured to use APCS frames, warn if they
930 are turned off and debugging is turned on. */
932 && write_symbols != NO_DEBUG
933 && !TARGET_APCS_FRAME
934 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
935 warning ("-g with -mno-apcs-frame may not give sensible debugging");
937 /* If stack checking is disabled, we can use r10 as the PIC register,
938 which keeps r9 available. */
940 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
942 if (TARGET_APCS_FLOAT)
943 warning ("passing floating point arguments in fp regs not yet supported");
945 /* Initialize boolean versions of the flags, for use in the arm.md file. */
946 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
947 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
948 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
949 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
950 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
951 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
952 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
953 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
955 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
956 arm_is_strong = (tune_flags & FL_STRONG) != 0;
957 thumb_code = (TARGET_ARM == 0);
958 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
959 && !(tune_flags & FL_ARCH4))) != 0;
960 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
961 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
963 /* V5 code we generate is completely interworking capable, so we turn off
964 TARGET_INTERWORK here to avoid many tests later on. */
966 /* XXX However, we must pass the right pre-processor defines to CPP
967 or GLD can get confused. This is a hack. */
968 if (TARGET_INTERWORK)
969 arm_cpp_interwork = 1;
972 target_flags &= ~ARM_FLAG_INTERWORK;
976 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
978 if (streq (arm_all_abis[i].name, target_abi_name))
980 arm_abi = arm_all_abis[i].abi_type;
984 if (i == ARRAY_SIZE (arm_all_abis))
985 error ("invalid ABI option: -mabi=%s", target_abi_name);
988 arm_abi = ARM_DEFAULT_ABI;
990 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
991 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
993 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
994 error ("iwmmxt abi requires an iwmmxt capable cpu");
996 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
997 if (target_fpu_name == NULL && target_fpe_name != NULL)
999 if (streq (target_fpe_name, "2"))
1000 target_fpu_name = "fpe2";
1001 else if (streq (target_fpe_name, "3"))
1002 target_fpu_name = "fpe3";
1004 error ("invalid floating point emulation option: -mfpe=%s",
1007 if (target_fpu_name != NULL)
1009 /* The user specified a FPU. */
1010 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1012 if (streq (all_fpus[i].name, target_fpu_name))
1014 arm_fpu_arch = all_fpus[i].fpu;
1015 arm_fpu_tune = arm_fpu_arch;
1016 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1020 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1021 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1025 #ifdef FPUTYPE_DEFAULT
1026 /* Use the default if it is specified for this platform. */
1027 arm_fpu_arch = FPUTYPE_DEFAULT;
1028 arm_fpu_tune = FPUTYPE_DEFAULT;
1030 /* Pick one based on CPU type. */
1031 /* ??? Some targets assume FPA is the default.
1032 if ((insn_flags & FL_VFP) != 0)
1033 arm_fpu_arch = FPUTYPE_VFP;
1036 if (arm_arch_cirrus)
1037 arm_fpu_arch = FPUTYPE_MAVERICK;
1039 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1041 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1042 arm_fpu_tune = FPUTYPE_FPA;
1044 arm_fpu_tune = arm_fpu_arch;
1045 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1046 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1050 if (target_float_abi_name != NULL)
1052 /* The user specified a FP ABI. */
1053 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1055 if (streq (all_float_abis[i].name, target_float_abi_name))
1057 arm_float_abi = all_float_abis[i].abi_type;
1061 if (i == ARRAY_SIZE (all_float_abis))
1062 error ("invalid floating point abi: -mfloat-abi=%s",
1063 target_float_abi_name);
1067 /* Use soft-float target flag. */
1068 if (target_flags & ARM_FLAG_SOFT_FLOAT)
1069 arm_float_abi = ARM_FLOAT_ABI_SOFT;
1071 arm_float_abi = ARM_FLOAT_ABI_HARD;
1074 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1075 sorry ("-mfloat-abi=hard and VFP");
1077 /* If soft-float is specified then don't use FPU. */
1078 if (TARGET_SOFT_FLOAT)
1079 arm_fpu_arch = FPUTYPE_NONE;
1081 /* For arm2/3 there is no need to do any scheduling if there is only
1082 a floating point emulator, or we are doing software floating-point. */
1083 if ((TARGET_SOFT_FLOAT
1084 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1085 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1086 && (tune_flags & FL_MODE32) == 0)
1087 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1089 /* Override the default structure alignment for AAPCS ABI. */
1090 if (arm_abi == ARM_ABI_AAPCS)
1091 arm_structure_size_boundary = 8;
1093 if (structure_size_string != NULL)
1095 int size = strtol (structure_size_string, NULL, 0);
1097 if (size == 8 || size == 32
1098 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1099 arm_structure_size_boundary = size;
1101 warning ("structure size boundary can only be set to %s",
1102 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1105 if (arm_pic_register_string != NULL)
1107 int pic_register = decode_reg_name (arm_pic_register_string);
1110 warning ("-mpic-register= is useless without -fpic");
1112 /* Prevent the user from choosing an obviously stupid PIC register. */
1113 else if (pic_register < 0 || call_used_regs[pic_register]
1114 || pic_register == HARD_FRAME_POINTER_REGNUM
1115 || pic_register == STACK_POINTER_REGNUM
1116 || pic_register >= PC_REGNUM)
1117 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1119 arm_pic_register = pic_register;
1122 if (TARGET_THUMB && flag_schedule_insns)
1124 /* Don't warn since it's on by default in -O2. */
1125 flag_schedule_insns = 0;
1130 /* There's some dispute as to whether this should be 1 or 2. However,
1131 experiments seem to show that in pathological cases a setting of
1132 1 degrades less severely than a setting of 2. This could change if
1133 other parts of the compiler change their behavior. */
1134 arm_constant_limit = 1;
1136 /* If optimizing for size, bump the number of instructions that we
1137 are prepared to conditionally execute (even on a StrongARM). */
1138 max_insns_skipped = 6;
1142 /* For processors with load scheduling, it never costs more than
1143 2 cycles to load a constant, and the load scheduler may well
1144 reduce that to 1. */
1145 if (tune_flags & FL_LDSCHED)
1146 arm_constant_limit = 1;
1148 /* On XScale the longer latency of a load makes it more difficult
1149 to achieve a good schedule, so it's faster to synthesize
1150 constants that can be done in two insns. */
1151 if (arm_tune_xscale)
1152 arm_constant_limit = 2;
1154 /* StrongARM has early execution of branches, so a sequence
1155 that is worth skipping is shorter. */
1157 max_insns_skipped = 3;
1160 /* Register global variables with the garbage collector. */
1161 arm_add_gc_roots ();
1165 arm_add_gc_roots (void)
1167 gcc_obstack_init(&minipool_obstack);
1168 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1171 /* A table of known ARM exception types.
1172 For use with the interrupt function attribute. */
1176 const char *const arg;
1177 const unsigned long return_value;
1181 static const isr_attribute_arg isr_attribute_args [] =
1183 { "IRQ", ARM_FT_ISR },
1184 { "irq", ARM_FT_ISR },
1185 { "FIQ", ARM_FT_FIQ },
1186 { "fiq", ARM_FT_FIQ },
1187 { "ABORT", ARM_FT_ISR },
1188 { "abort", ARM_FT_ISR },
1189 { "ABORT", ARM_FT_ISR },
1190 { "abort", ARM_FT_ISR },
1191 { "UNDEF", ARM_FT_EXCEPTION },
1192 { "undef", ARM_FT_EXCEPTION },
1193 { "SWI", ARM_FT_EXCEPTION },
1194 { "swi", ARM_FT_EXCEPTION },
1195 { NULL, ARM_FT_NORMAL }
1198 /* Returns the (interrupt) function type of the current
1199 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1201 static unsigned long
1202 arm_isr_value (tree argument)
1204 const isr_attribute_arg * ptr;
1207 /* No argument - default to IRQ. */
1208 if (argument == NULL_TREE)
1211 /* Get the value of the argument. */
1212 if (TREE_VALUE (argument) == NULL_TREE
1213 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1214 return ARM_FT_UNKNOWN;
1216 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1218 /* Check it against the list of known arguments. */
1219 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1220 if (streq (arg, ptr->arg))
1221 return ptr->return_value;
1223 /* An unrecognized interrupt type. */
1224 return ARM_FT_UNKNOWN;
1227 /* Computes the type of the current function. */
1229 static unsigned long
1230 arm_compute_func_type (void)
1232 unsigned long type = ARM_FT_UNKNOWN;
1236 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1239 /* Decide if the current function is volatile. Such functions
1240 never return, and many memory cycles can be saved by not storing
1241 register values that will never be needed again. This optimization
1242 was added to speed up context switching in a kernel application. */
1244 && TREE_NOTHROW (current_function_decl)
1245 && TREE_THIS_VOLATILE (current_function_decl))
1246 type |= ARM_FT_VOLATILE;
1248 if (cfun->static_chain_decl != NULL)
1249 type |= ARM_FT_NESTED;
1251 attr = DECL_ATTRIBUTES (current_function_decl);
1253 a = lookup_attribute ("naked", attr);
1255 type |= ARM_FT_NAKED;
1257 a = lookup_attribute ("isr", attr);
1259 a = lookup_attribute ("interrupt", attr);
1262 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1264 type |= arm_isr_value (TREE_VALUE (a));
1269 /* Returns the type of the current function. */
1272 arm_current_func_type (void)
1274 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1275 cfun->machine->func_type = arm_compute_func_type ();
1277 return cfun->machine->func_type;
1280 /* Return 1 if it is possible to return using a single instruction.
1281 If SIBLING is non-null, this is a test for a return before a sibling
1282 call. SIBLING is the call insn, so we can examine its register usage. */
1285 use_return_insn (int iscond, rtx sibling)
1288 unsigned int func_type;
1289 unsigned long saved_int_regs;
1290 unsigned HOST_WIDE_INT stack_adjust;
1291 arm_stack_offsets *offsets;
1293 /* Never use a return instruction before reload has run. */
1294 if (!reload_completed)
1297 func_type = arm_current_func_type ();
1299 /* Naked functions and volatile functions need special
1301 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1304 /* So do interrupt functions that use the frame pointer. */
1305 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1308 offsets = arm_get_frame_offsets ();
1309 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1311 /* As do variadic functions. */
1312 if (current_function_pretend_args_size
1313 || cfun->machine->uses_anonymous_args
1314 /* Or if the function calls __builtin_eh_return () */
1315 || current_function_calls_eh_return
1316 /* Or if the function calls alloca */
1317 || current_function_calls_alloca
1318 /* Or if there is a stack adjustment. However, if the stack pointer
1319 is saved on the stack, we can use a pre-incrementing stack load. */
1320 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1323 saved_int_regs = arm_compute_save_reg_mask ();
1325 /* Unfortunately, the insn
1327 ldmib sp, {..., sp, ...}
1329 triggers a bug on most SA-110 based devices, such that the stack
1330 pointer won't be correctly restored if the instruction takes a
1331 page fault. We work around this problem by popping r3 along with
1332 the other registers, since that is never slower than executing
1333 another instruction.
1335 We test for !arm_arch5 here, because code for any architecture
1336 less than this could potentially be run on one of the buggy
1338 if (stack_adjust == 4 && !arm_arch5)
1340 /* Validate that r3 is a call-clobbered register (always true in
1341 the default abi) ... */
1342 if (!call_used_regs[3])
1345 /* ... that it isn't being used for a return value (always true
1346 until we implement return-in-regs), or for a tail-call
1350 if (GET_CODE (sibling) != CALL_INSN)
1353 if (find_regno_fusage (sibling, USE, 3))
1357 /* ... and that there are no call-saved registers in r0-r2
1358 (always true in the default ABI). */
1359 if (saved_int_regs & 0x7)
1363 /* Can't be done if interworking with Thumb, and any registers have been
1365 if (TARGET_INTERWORK && saved_int_regs != 0)
1368 /* On StrongARM, conditional returns are expensive if they aren't
1369 taken and multiple registers have been stacked. */
1370 if (iscond && arm_is_strong)
1372 /* Conditional return when just the LR is stored is a simple
1373 conditional-load instruction, that's not expensive. */
1374 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1377 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1381 /* If there are saved registers but the LR isn't saved, then we need
1382 two instructions for the return. */
1383 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1386 /* Can't be done if any of the FPA regs are pushed,
1387 since this also requires an insn. */
1388 if (TARGET_HARD_FLOAT && TARGET_FPA)
1389 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1390 if (regs_ever_live[regno] && !call_used_regs[regno])
1393 /* Likewise VFP regs. */
1394 if (TARGET_HARD_FLOAT && TARGET_VFP)
1395 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1396 if (regs_ever_live[regno] && !call_used_regs[regno])
1399 if (TARGET_REALLY_IWMMXT)
1400 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1401 if (regs_ever_live[regno] && ! call_used_regs [regno])
1407 /* Return TRUE if int I is a valid immediate ARM constant. */
1410 const_ok_for_arm (HOST_WIDE_INT i)
1412 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1414 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1415 be all zero, or all one. */
1416 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1417 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1418 != ((~(unsigned HOST_WIDE_INT) 0)
1419 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1422 /* Fast return for 0 and powers of 2 */
1423 if ((i & (i - 1)) == 0)
1428 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1431 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1432 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1434 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1439 /* Return true if I is a valid constant for the operation CODE. */
1441 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1443 if (const_ok_for_arm (i))
1449 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1451 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1457 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1464 /* Emit a sequence of insns to handle a large constant.
1465 CODE is the code of the operation required, it can be any of SET, PLUS,
1466 IOR, AND, XOR, MINUS;
1467 MODE is the mode in which the operation is being performed;
1468 VAL is the integer to operate on;
1469 SOURCE is the other operand (a register, or a null-pointer for SET);
1470 SUBTARGETS means it is safe to create scratch registers if that will
1471 either produce a simpler sequence, or we will want to cse the values.
1472 Return value is the number of insns emitted. */
1475 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1476 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1480 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1481 cond = COND_EXEC_TEST (PATTERN (insn));
1485 if (subtargets || code == SET
1486 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1487 && REGNO (target) != REGNO (source)))
1489 /* After arm_reorg has been called, we can't fix up expensive
1490 constants by pushing them into memory so we must synthesize
1491 them in-line, regardless of the cost. This is only likely to
1492 be more costly on chips that have load delay slots and we are
1493 compiling without running the scheduler (so no splitting
1494 occurred before the final instruction emission).
1496 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1498 if (!after_arm_reorg
1500 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1502 > arm_constant_limit + (code != SET)))
1506 /* Currently SET is the only monadic value for CODE, all
1507 the rest are diadic. */
1508 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1513 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1515 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1516 /* For MINUS, the value is subtracted from, since we never
1517 have subtraction of a constant. */
1519 emit_insn (gen_rtx_SET (VOIDmode, target,
1520 gen_rtx_MINUS (mode, temp, source)));
1522 emit_insn (gen_rtx_SET (VOIDmode, target,
1523 gen_rtx_fmt_ee (code, mode, source, temp)));
1529 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1534 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1536 HOST_WIDE_INT temp1;
1544 if (remainder & (3 << (i - 2)))
1549 temp1 = remainder & ((0x0ff << end)
1550 | ((i < end) ? (0xff >> (32 - end)) : 0));
1551 remainder &= ~temp1;
1556 } while (remainder);
1560 /* Emit an instruction with the indicated PATTERN. If COND is
1561 non-NULL, conditionalize the execution of the instruction on COND
1565 emit_constant_insn (rtx cond, rtx pattern)
1568 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1569 emit_insn (pattern);
1572 /* As above, but extra parameter GENERATE which, if clear, suppresses
1576 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1577 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1582 int can_negate_initial = 0;
1585 int num_bits_set = 0;
1586 int set_sign_bit_copies = 0;
1587 int clear_sign_bit_copies = 0;
1588 int clear_zero_bit_copies = 0;
1589 int set_zero_bit_copies = 0;
1591 unsigned HOST_WIDE_INT temp1, temp2;
1592 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1594 /* Find out which operations are safe for a given CODE. Also do a quick
1595 check for degenerate cases; these can occur when DImode operations
1607 can_negate_initial = 1;
1611 if (remainder == 0xffffffff)
1614 emit_constant_insn (cond,
1615 gen_rtx_SET (VOIDmode, target,
1616 GEN_INT (ARM_SIGN_EXTEND (val))));
1621 if (reload_completed && rtx_equal_p (target, source))
1624 emit_constant_insn (cond,
1625 gen_rtx_SET (VOIDmode, target, source));
1634 emit_constant_insn (cond,
1635 gen_rtx_SET (VOIDmode, target, const0_rtx));
1638 if (remainder == 0xffffffff)
1640 if (reload_completed && rtx_equal_p (target, source))
1643 emit_constant_insn (cond,
1644 gen_rtx_SET (VOIDmode, target, source));
1653 if (reload_completed && rtx_equal_p (target, source))
1656 emit_constant_insn (cond,
1657 gen_rtx_SET (VOIDmode, target, source));
1660 if (remainder == 0xffffffff)
1663 emit_constant_insn (cond,
1664 gen_rtx_SET (VOIDmode, target,
1665 gen_rtx_NOT (mode, source)));
1669 /* We don't know how to handle this yet below. */
1673 /* We treat MINUS as (val - source), since (source - val) is always
1674 passed as (source + (-val)). */
1678 emit_constant_insn (cond,
1679 gen_rtx_SET (VOIDmode, target,
1680 gen_rtx_NEG (mode, source)));
1683 if (const_ok_for_arm (val))
1686 emit_constant_insn (cond,
1687 gen_rtx_SET (VOIDmode, target,
1688 gen_rtx_MINUS (mode, GEN_INT (val),
1700 /* If we can do it in one insn get out quickly. */
1701 if (const_ok_for_arm (val)
1702 || (can_negate_initial && const_ok_for_arm (-val))
1703 || (can_invert && const_ok_for_arm (~val)))
1706 emit_constant_insn (cond,
1707 gen_rtx_SET (VOIDmode, target,
1709 ? gen_rtx_fmt_ee (code, mode, source,
1715 /* Calculate a few attributes that may be useful for specific
1717 for (i = 31; i >= 0; i--)
1719 if ((remainder & (1 << i)) == 0)
1720 clear_sign_bit_copies++;
1725 for (i = 31; i >= 0; i--)
1727 if ((remainder & (1 << i)) != 0)
1728 set_sign_bit_copies++;
1733 for (i = 0; i <= 31; i++)
1735 if ((remainder & (1 << i)) == 0)
1736 clear_zero_bit_copies++;
1741 for (i = 0; i <= 31; i++)
1743 if ((remainder & (1 << i)) != 0)
1744 set_zero_bit_copies++;
1752 /* See if we can do this by sign_extending a constant that is known
1753 to be negative. This is a good, way of doing it, since the shift
1754 may well merge into a subsequent insn. */
1755 if (set_sign_bit_copies > 1)
1757 if (const_ok_for_arm
1758 (temp1 = ARM_SIGN_EXTEND (remainder
1759 << (set_sign_bit_copies - 1))))
1763 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1764 emit_constant_insn (cond,
1765 gen_rtx_SET (VOIDmode, new_src,
1767 emit_constant_insn (cond,
1768 gen_ashrsi3 (target, new_src,
1769 GEN_INT (set_sign_bit_copies - 1)));
1773 /* For an inverted constant, we will need to set the low bits,
1774 these will be shifted out of harm's way. */
1775 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1776 if (const_ok_for_arm (~temp1))
1780 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1781 emit_constant_insn (cond,
1782 gen_rtx_SET (VOIDmode, new_src,
1784 emit_constant_insn (cond,
1785 gen_ashrsi3 (target, new_src,
1786 GEN_INT (set_sign_bit_copies - 1)));
1792 /* See if we can generate this by setting the bottom (or the top)
1793 16 bits, and then shifting these into the other half of the
1794 word. We only look for the simplest cases, to do more would cost
1795 too much. Be careful, however, not to generate this when the
1796 alternative would take fewer insns. */
1797 if (val & 0xffff0000)
1799 temp1 = remainder & 0xffff0000;
1800 temp2 = remainder & 0x0000ffff;
1802 /* Overlaps outside this range are best done using other methods. */
1803 for (i = 9; i < 24; i++)
1805 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1806 && !const_ok_for_arm (temp2))
1808 rtx new_src = (subtargets
1809 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1811 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1812 source, subtargets, generate);
1820 gen_rtx_ASHIFT (mode, source,
1827 /* Don't duplicate cases already considered. */
1828 for (i = 17; i < 24; i++)
1830 if (((temp1 | (temp1 >> i)) == remainder)
1831 && !const_ok_for_arm (temp1))
1833 rtx new_src = (subtargets
1834 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1836 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1837 source, subtargets, generate);
1842 gen_rtx_SET (VOIDmode, target,
1845 gen_rtx_LSHIFTRT (mode, source,
1856 /* If we have IOR or XOR, and the constant can be loaded in a
1857 single instruction, and we can find a temporary to put it in,
1858 then this can be done in two instructions instead of 3-4. */
1860 /* TARGET can't be NULL if SUBTARGETS is 0 */
1861 || (reload_completed && !reg_mentioned_p (target, source)))
1863 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1867 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1869 emit_constant_insn (cond,
1870 gen_rtx_SET (VOIDmode, sub,
1872 emit_constant_insn (cond,
1873 gen_rtx_SET (VOIDmode, target,
1874 gen_rtx_fmt_ee (code, mode,
1884 if (set_sign_bit_copies > 8
1885 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1889 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1890 rtx shift = GEN_INT (set_sign_bit_copies);
1894 gen_rtx_SET (VOIDmode, sub,
1896 gen_rtx_ASHIFT (mode,
1901 gen_rtx_SET (VOIDmode, target,
1903 gen_rtx_LSHIFTRT (mode, sub,
1909 if (set_zero_bit_copies > 8
1910 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1914 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1915 rtx shift = GEN_INT (set_zero_bit_copies);
1919 gen_rtx_SET (VOIDmode, sub,
1921 gen_rtx_LSHIFTRT (mode,
1926 gen_rtx_SET (VOIDmode, target,
1928 gen_rtx_ASHIFT (mode, sub,
1934 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1938 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1939 emit_constant_insn (cond,
1940 gen_rtx_SET (VOIDmode, sub,
1941 gen_rtx_NOT (mode, source)));
1944 sub = gen_reg_rtx (mode);
1945 emit_constant_insn (cond,
1946 gen_rtx_SET (VOIDmode, sub,
1947 gen_rtx_AND (mode, source,
1949 emit_constant_insn (cond,
1950 gen_rtx_SET (VOIDmode, target,
1951 gen_rtx_NOT (mode, sub)));
1958 /* See if two shifts will do 2 or more insn's worth of work. */
1959 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1961 HOST_WIDE_INT shift_mask = ((0xffffffff
1962 << (32 - clear_sign_bit_copies))
1965 if ((remainder | shift_mask) != 0xffffffff)
1969 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1970 insns = arm_gen_constant (AND, mode, cond,
1971 remainder | shift_mask,
1972 new_src, source, subtargets, 1);
1977 rtx targ = subtargets ? NULL_RTX : target;
1978 insns = arm_gen_constant (AND, mode, cond,
1979 remainder | shift_mask,
1980 targ, source, subtargets, 0);
1986 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1987 rtx shift = GEN_INT (clear_sign_bit_copies);
1989 emit_insn (gen_ashlsi3 (new_src, source, shift));
1990 emit_insn (gen_lshrsi3 (target, new_src, shift));
1996 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1998 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2000 if ((remainder | shift_mask) != 0xffffffff)
2004 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2006 insns = arm_gen_constant (AND, mode, cond,
2007 remainder | shift_mask,
2008 new_src, source, subtargets, 1);
2013 rtx targ = subtargets ? NULL_RTX : target;
2015 insns = arm_gen_constant (AND, mode, cond,
2016 remainder | shift_mask,
2017 targ, source, subtargets, 0);
2023 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2024 rtx shift = GEN_INT (clear_zero_bit_copies);
2026 emit_insn (gen_lshrsi3 (new_src, source, shift));
2027 emit_insn (gen_ashlsi3 (target, new_src, shift));
2039 for (i = 0; i < 32; i++)
2040 if (remainder & (1 << i))
2043 if (code == AND || (can_invert && num_bits_set > 16))
2044 remainder = (~remainder) & 0xffffffff;
2045 else if (code == PLUS && num_bits_set > 16)
2046 remainder = (-remainder) & 0xffffffff;
2053 /* Now try and find a way of doing the job in either two or three
2055 We start by looking for the largest block of zeros that are aligned on
2056 a 2-bit boundary, we then fill up the temps, wrapping around to the
2057 top of the word when we drop off the bottom.
2058 In the worst case this code should produce no more than four insns. */
2061 int best_consecutive_zeros = 0;
2063 for (i = 0; i < 32; i += 2)
2065 int consecutive_zeros = 0;
2067 if (!(remainder & (3 << i)))
2069 while ((i < 32) && !(remainder & (3 << i)))
2071 consecutive_zeros += 2;
2074 if (consecutive_zeros > best_consecutive_zeros)
2076 best_consecutive_zeros = consecutive_zeros;
2077 best_start = i - consecutive_zeros;
2083 /* So long as it won't require any more insns to do so, it's
2084 desirable to emit a small constant (in bits 0...9) in the last
2085 insn. This way there is more chance that it can be combined with
2086 a later addressing insn to form a pre-indexed load or store
2087 operation. Consider:
2089 *((volatile int *)0xe0000100) = 1;
2090 *((volatile int *)0xe0000110) = 2;
2092 We want this to wind up as:
2096 str rB, [rA, #0x100]
2098 str rB, [rA, #0x110]
2100 rather than having to synthesize both large constants from scratch.
2102 Therefore, we calculate how many insns would be required to emit
2103 the constant starting from `best_start', and also starting from
2104 zero (ie with bit 31 first to be output). If `best_start' doesn't
2105 yield a shorter sequence, we may as well use zero. */
2107 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2108 && (count_insns_for_constant (remainder, 0) <=
2109 count_insns_for_constant (remainder, best_start)))
2112 /* Now start emitting the insns. */
2120 if (remainder & (3 << (i - 2)))
2125 temp1 = remainder & ((0x0ff << end)
2126 | ((i < end) ? (0xff >> (32 - end)) : 0));
2127 remainder &= ~temp1;
2131 rtx new_src, temp1_rtx;
2133 if (code == SET || code == MINUS)
2135 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2136 if (can_invert && code != MINUS)
2141 if (remainder && subtargets)
2142 new_src = gen_reg_rtx (mode);
2147 else if (can_negate)
2151 temp1 = trunc_int_for_mode (temp1, mode);
2152 temp1_rtx = GEN_INT (temp1);
2156 else if (code == MINUS)
2157 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2159 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2161 emit_constant_insn (cond,
2162 gen_rtx_SET (VOIDmode, new_src,
2172 else if (code == MINUS)
2186 /* Canonicalize a comparison so that we are more likely to recognize it.
2187 This can be done for a few constant compares, where we can make the
2188 immediate value easier to load. */
2191 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2193 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2203 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2204 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2206 *op1 = GEN_INT (i + 1);
2207 return code == GT ? GE : LT;
2213 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2214 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2216 *op1 = GEN_INT (i - 1);
2217 return code == GE ? GT : LE;
2223 if (i != ~((unsigned HOST_WIDE_INT) 0)
2224 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2226 *op1 = GEN_INT (i + 1);
2227 return code == GTU ? GEU : LTU;
2234 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2236 *op1 = GEN_INT (i - 1);
2237 return code == GEU ? GTU : LEU;
2249 /* Define how to find the value returned by a function. */
2251 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2253 enum machine_mode mode;
2254 int unsignedp ATTRIBUTE_UNUSED;
2255 rtx r ATTRIBUTE_UNUSED;
2258 mode = TYPE_MODE (type);
2259 /* Promote integer types. */
2260 if (INTEGRAL_TYPE_P (type))
2261 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2262 return LIBCALL_VALUE(mode);
2266 /* Decide whether a type should be returned in memory (true)
2267 or in a register (false). This is called by the macro
2268 RETURN_IN_MEMORY. */
2270 arm_return_in_memory (tree type)
2274 if (!AGGREGATE_TYPE_P (type))
2275 /* All simple types are returned in registers. */
2278 size = int_size_in_bytes (type);
2280 if (arm_abi != ARM_ABI_APCS)
2282 /* ATPCS and later return aggregate types in memory only if they are
2283 larger than a word (or are variable size). */
2284 return (size < 0 || size > UNITS_PER_WORD);
2287 /* For the arm-wince targets we choose to be compatible with Microsoft's
2288 ARM and Thumb compilers, which always return aggregates in memory. */
2290 /* All structures/unions bigger than one word are returned in memory.
2291 Also catch the case where int_size_in_bytes returns -1. In this case
2292 the aggregate is either huge or of variable size, and in either case
2293 we will want to return it via memory and not in a register. */
2294 if (size < 0 || size > UNITS_PER_WORD)
2297 if (TREE_CODE (type) == RECORD_TYPE)
2301 /* For a struct the APCS says that we only return in a register
2302 if the type is 'integer like' and every addressable element
2303 has an offset of zero. For practical purposes this means
2304 that the structure can have at most one non bit-field element
2305 and that this element must be the first one in the structure. */
2307 /* Find the first field, ignoring non FIELD_DECL things which will
2308 have been created by C++. */
2309 for (field = TYPE_FIELDS (type);
2310 field && TREE_CODE (field) != FIELD_DECL;
2311 field = TREE_CHAIN (field))
2315 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2317 /* Check that the first field is valid for returning in a register. */
2319 /* ... Floats are not allowed */
2320 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2323 /* ... Aggregates that are not themselves valid for returning in
2324 a register are not allowed. */
2325 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2328 /* Now check the remaining fields, if any. Only bitfields are allowed,
2329 since they are not addressable. */
2330 for (field = TREE_CHAIN (field);
2332 field = TREE_CHAIN (field))
2334 if (TREE_CODE (field) != FIELD_DECL)
2337 if (!DECL_BIT_FIELD_TYPE (field))
2344 if (TREE_CODE (type) == UNION_TYPE)
2348 /* Unions can be returned in registers if every element is
2349 integral, or can be returned in an integer register. */
2350 for (field = TYPE_FIELDS (type);
2352 field = TREE_CHAIN (field))
2354 if (TREE_CODE (field) != FIELD_DECL)
2357 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2360 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2366 #endif /* not ARM_WINCE */
2368 /* Return all other types in memory. */
2372 /* Indicate whether or not words of a double are in big-endian order. */
2375 arm_float_words_big_endian (void)
2377 if (TARGET_MAVERICK)
2380 /* For FPA, float words are always big-endian. For VFP, floats words
2381 follow the memory system mode. */
2389 return (TARGET_BIG_END ? 1 : 0);
2394 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2395 for a call to a function whose data type is FNTYPE.
2396 For a library call, FNTYPE is NULL. */
2398 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2399 rtx libname ATTRIBUTE_UNUSED,
2400 tree fndecl ATTRIBUTE_UNUSED)
2402 /* On the ARM, the offset starts at 0. */
2403 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2404 pcum->iwmmxt_nregs = 0;
2405 pcum->can_split = true;
2407 pcum->call_cookie = CALL_NORMAL;
2409 if (TARGET_LONG_CALLS)
2410 pcum->call_cookie = CALL_LONG;
2412 /* Check for long call/short call attributes. The attributes
2413 override any command line option. */
2416 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2417 pcum->call_cookie = CALL_SHORT;
2418 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2419 pcum->call_cookie = CALL_LONG;
2422 /* Varargs vectors are treated the same as long long.
2423 named_count avoids having to change the way arm handles 'named' */
2424 pcum->named_count = 0;
2427 if (TARGET_REALLY_IWMMXT && fntype)
2431 for (fn_arg = TYPE_ARG_TYPES (fntype);
2433 fn_arg = TREE_CHAIN (fn_arg))
2434 pcum->named_count += 1;
2436 if (! pcum->named_count)
2437 pcum->named_count = INT_MAX;
2442 /* Return true if mode/type need doubleword alignment. */
2444 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2446 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2447 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2451 /* Determine where to put an argument to a function.
2452 Value is zero to push the argument on the stack,
2453 or a hard register in which to store the argument.
2455 MODE is the argument's machine mode.
2456 TYPE is the data type of the argument (as a tree).
2457 This is null for libcalls where that information may
2459 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2460 the preceding args and about the function being called.
2461 NAMED is nonzero if this argument is a named parameter
2462 (otherwise it is an extra parameter matching an ellipsis). */
2465 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2466 tree type, int named)
2470 /* Varargs vectors are treated the same as long long.
2471 named_count avoids having to change the way arm handles 'named' */
2472 if (TARGET_IWMMXT_ABI
2473 && arm_vector_mode_supported_p (mode)
2474 && pcum->named_count > pcum->nargs + 1)
2476 if (pcum->iwmmxt_nregs <= 9)
2477 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2480 pcum->can_split = false;
2485 /* Put doubleword aligned quantities in even register pairs. */
2487 && ARM_DOUBLEWORD_ALIGN
2488 && arm_needs_doubleword_align (mode, type))
2491 if (mode == VOIDmode)
2492 /* Compute operand 2 of the call insn. */
2493 return GEN_INT (pcum->call_cookie);
2495 /* Only allow splitting an arg between regs and memory if all preceding
2496 args were allocated to regs. For args passed by reference we only count
2497 the reference pointer. */
2498 if (pcum->can_split)
2501 nregs = ARM_NUM_REGS2 (mode, type);
2503 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2506 return gen_rtx_REG (mode, pcum->nregs);
2509 /* Variable sized types are passed by reference. This is a GCC
2510 extension to the ARM ABI. */
2513 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2514 enum machine_mode mode ATTRIBUTE_UNUSED,
2515 tree type, bool named ATTRIBUTE_UNUSED)
2517 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2520 /* Encode the current state of the #pragma [no_]long_calls. */
2523 OFF, /* No #pramgma [no_]long_calls is in effect. */
2524 LONG, /* #pragma long_calls is in effect. */
2525 SHORT /* #pragma no_long_calls is in effect. */
2528 static arm_pragma_enum arm_pragma_long_calls = OFF;
2531 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2533 arm_pragma_long_calls = LONG;
2537 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2539 arm_pragma_long_calls = SHORT;
2543 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2545 arm_pragma_long_calls = OFF;
2548 /* Table of machine attributes. */
2549 const struct attribute_spec arm_attribute_table[] =
2551 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2552 /* Function calls made to this symbol must be done indirectly, because
2553 it may lie outside of the 26 bit addressing range of a normal function
2555 { "long_call", 0, 0, false, true, true, NULL },
2556 /* Whereas these functions are always known to reside within the 26 bit
2557 addressing range. */
2558 { "short_call", 0, 0, false, true, true, NULL },
2559 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2560 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2561 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2562 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2564 /* ARM/PE has three new attributes:
2566 dllexport - for exporting a function/variable that will live in a dll
2567 dllimport - for importing a function/variable from a dll
2569 Microsoft allows multiple declspecs in one __declspec, separating
2570 them with spaces. We do NOT support this. Instead, use __declspec
2573 { "dllimport", 0, 0, true, false, false, NULL },
2574 { "dllexport", 0, 0, true, false, false, NULL },
2575 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2576 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2577 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2578 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2580 { NULL, 0, 0, false, false, false, NULL }
2583 /* Handle an attribute requiring a FUNCTION_DECL;
2584 arguments as in struct attribute_spec.handler. */
2586 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2587 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2589 if (TREE_CODE (*node) != FUNCTION_DECL)
2591 warning ("`%s' attribute only applies to functions",
2592 IDENTIFIER_POINTER (name));
2593 *no_add_attrs = true;
2599 /* Handle an "interrupt" or "isr" attribute;
2600 arguments as in struct attribute_spec.handler. */
2602 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2607 if (TREE_CODE (*node) != FUNCTION_DECL)
2609 warning ("`%s' attribute only applies to functions",
2610 IDENTIFIER_POINTER (name));
2611 *no_add_attrs = true;
2613 /* FIXME: the argument if any is checked for type attributes;
2614 should it be checked for decl ones? */
2618 if (TREE_CODE (*node) == FUNCTION_TYPE
2619 || TREE_CODE (*node) == METHOD_TYPE)
2621 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2623 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2624 *no_add_attrs = true;
2627 else if (TREE_CODE (*node) == POINTER_TYPE
2628 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2629 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2630 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2632 *node = build_variant_type_copy (*node);
2633 TREE_TYPE (*node) = build_type_attribute_variant
2635 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2636 *no_add_attrs = true;
2640 /* Possibly pass this attribute on from the type to a decl. */
2641 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2642 | (int) ATTR_FLAG_FUNCTION_NEXT
2643 | (int) ATTR_FLAG_ARRAY_NEXT))
2645 *no_add_attrs = true;
2646 return tree_cons (name, args, NULL_TREE);
2650 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2658 /* Return 0 if the attributes for two types are incompatible, 1 if they
2659 are compatible, and 2 if they are nearly compatible (which causes a
2660 warning to be generated). */
2662 arm_comp_type_attributes (tree type1, tree type2)
2666 /* Check for mismatch of non-default calling convention. */
2667 if (TREE_CODE (type1) != FUNCTION_TYPE)
2670 /* Check for mismatched call attributes. */
2671 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2672 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2673 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2674 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2676 /* Only bother to check if an attribute is defined. */
2677 if (l1 | l2 | s1 | s2)
2679 /* If one type has an attribute, the other must have the same attribute. */
2680 if ((l1 != l2) || (s1 != s2))
2683 /* Disallow mixed attributes. */
2684 if ((l1 & s2) || (l2 & s1))
2688 /* Check for mismatched ISR attribute. */
2689 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2691 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2692 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2694 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2701 /* Encode long_call or short_call attribute by prefixing
2702 symbol name in DECL with a special character FLAG. */
2704 arm_encode_call_attribute (tree decl, int flag)
2706 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2707 int len = strlen (str);
2710 /* Do not allow weak functions to be treated as short call. */
2711 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2714 newstr = alloca (len + 2);
2716 strcpy (newstr + 1, str);
2718 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2719 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2722 /* Assigns default attributes to newly defined type. This is used to
2723 set short_call/long_call attributes for function types of
2724 functions defined inside corresponding #pragma scopes. */
2726 arm_set_default_type_attributes (tree type)
2728 /* Add __attribute__ ((long_call)) to all functions, when
2729 inside #pragma long_calls or __attribute__ ((short_call)),
2730 when inside #pragma no_long_calls. */
2731 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2733 tree type_attr_list, attr_name;
2734 type_attr_list = TYPE_ATTRIBUTES (type);
2736 if (arm_pragma_long_calls == LONG)
2737 attr_name = get_identifier ("long_call");
2738 else if (arm_pragma_long_calls == SHORT)
2739 attr_name = get_identifier ("short_call");
2743 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2744 TYPE_ATTRIBUTES (type) = type_attr_list;
2748 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2749 defined within the current compilation unit. If this cannot be
2750 determined, then 0 is returned. */
2752 current_file_function_operand (rtx sym_ref)
2754 /* This is a bit of a fib. A function will have a short call flag
2755 applied to its name if it has the short call attribute, or it has
2756 already been defined within the current compilation unit. */
2757 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2760 /* The current function is always defined within the current compilation
2761 unit. If it s a weak definition however, then this may not be the real
2762 definition of the function, and so we have to say no. */
2763 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2764 && !DECL_WEAK (current_function_decl))
2767 /* We cannot make the determination - default to returning 0. */
2771 /* Return nonzero if a 32 bit "long_call" should be generated for
2772 this call. We generate a long_call if the function:
2774 a. has an __attribute__((long call))
2775 or b. is within the scope of a #pragma long_calls
2776 or c. the -mlong-calls command line switch has been specified
2778 1. -ffunction-sections is in effect
2779 or 2. the current function has __attribute__ ((section))
2780 or 3. the target function has __attribute__ ((section))
2782 However we do not generate a long call if the function:
2784 d. has an __attribute__ ((short_call))
2785 or e. is inside the scope of a #pragma no_long_calls
2786 or f. is defined within the current compilation unit.
2788 This function will be called by C fragments contained in the machine
2789 description file. SYM_REF and CALL_COOKIE correspond to the matched
2790 rtl operands. CALL_SYMBOL is used to distinguish between
2791 two different callers of the function. It is set to 1 in the
2792 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2793 and "call_value" patterns. This is because of the difference in the
2794 SYM_REFs passed by these patterns. */
2796 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2800 if (GET_CODE (sym_ref) != MEM)
2803 sym_ref = XEXP (sym_ref, 0);
2806 if (GET_CODE (sym_ref) != SYMBOL_REF)
2809 if (call_cookie & CALL_SHORT)
2812 if (TARGET_LONG_CALLS)
2814 if (flag_function_sections
2815 || DECL_SECTION_NAME (current_function_decl))
2816 /* c.3 is handled by the defintion of the
2817 ARM_DECLARE_FUNCTION_SIZE macro. */
2821 if (current_file_function_operand (sym_ref))
2824 return (call_cookie & CALL_LONG)
2825 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2826 || TARGET_LONG_CALLS;
2829 /* Return nonzero if it is ok to make a tail-call to DECL. */
2831 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2833 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2835 if (cfun->machine->sibcall_blocked)
2838 /* Never tailcall something for which we have no decl, or if we
2839 are in Thumb mode. */
2840 if (decl == NULL || TARGET_THUMB)
2843 /* Get the calling method. */
2844 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2845 call_type = CALL_SHORT;
2846 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2847 call_type = CALL_LONG;
2849 /* Cannot tail-call to long calls, since these are out of range of
2850 a branch instruction. However, if not compiling PIC, we know
2851 we can reach the symbol if it is in this compilation unit. */
2852 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2855 /* If we are interworking and the function is not declared static
2856 then we can't tail-call it unless we know that it exists in this
2857 compilation unit (since it might be a Thumb routine). */
2858 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2861 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2862 if (IS_INTERRUPT (arm_current_func_type ()))
2865 /* Everything else is ok. */
2870 /* Addressing mode support functions. */
2872 /* Return nonzero if X is a legitimate immediate operand when compiling
2875 legitimate_pic_operand_p (rtx x)
2879 && (GET_CODE (x) == SYMBOL_REF
2880 || (GET_CODE (x) == CONST
2881 && GET_CODE (XEXP (x, 0)) == PLUS
2882 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2889 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2891 if (GET_CODE (orig) == SYMBOL_REF
2892 || GET_CODE (orig) == LABEL_REF)
2894 #ifndef AOF_ASSEMBLER
2895 rtx pic_ref, address;
2905 reg = gen_reg_rtx (Pmode);
2910 #ifdef AOF_ASSEMBLER
2911 /* The AOF assembler can generate relocations for these directly, and
2912 understands that the PIC register has to be added into the offset. */
2913 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2916 address = gen_reg_rtx (Pmode);
2921 emit_insn (gen_pic_load_addr_arm (address, orig));
2923 emit_insn (gen_pic_load_addr_thumb (address, orig));
2925 if ((GET_CODE (orig) == LABEL_REF
2926 || (GET_CODE (orig) == SYMBOL_REF &&
2927 SYMBOL_REF_LOCAL_P (orig)))
2929 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2932 pic_ref = gen_const_mem (Pmode,
2933 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2937 insn = emit_move_insn (reg, pic_ref);
2939 current_function_uses_pic_offset_table = 1;
2940 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2942 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2946 else if (GET_CODE (orig) == CONST)
2950 if (GET_CODE (XEXP (orig, 0)) == PLUS
2951 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2959 reg = gen_reg_rtx (Pmode);
2962 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2964 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2965 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2966 base == reg ? 0 : reg);
2971 if (GET_CODE (offset) == CONST_INT)
2973 /* The base register doesn't really matter, we only want to
2974 test the index for the appropriate mode. */
2975 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2977 if (!no_new_pseudos)
2978 offset = force_reg (Pmode, offset);
2983 if (GET_CODE (offset) == CONST_INT)
2984 return plus_constant (base, INTVAL (offset));
2987 if (GET_MODE_SIZE (mode) > 4
2988 && (GET_MODE_CLASS (mode) == MODE_INT
2989 || TARGET_SOFT_FLOAT))
2991 emit_insn (gen_addsi3 (reg, base, offset));
2995 return gen_rtx_PLUS (Pmode, base, offset);
3002 /* Find a spare low register. */
3005 thumb_find_work_register (int live_regs_mask)
3009 /* Use a spare arg register. */
3010 if (!regs_ever_live[LAST_ARG_REGNUM])
3011 return LAST_ARG_REGNUM;
3013 /* Look for a pushed register. */
3014 for (reg = 0; reg < LAST_LO_REGNUM; reg++)
3015 if (live_regs_mask & (1 << reg))
3018 /* Something went wrong. */
3023 /* Generate code to load the PIC register. */
3026 arm_load_pic_register (void)
3028 #ifndef AOF_ASSEMBLER
3029 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3030 rtx global_offset_table;
3032 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3038 l1 = gen_label_rtx ();
3040 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3041 /* On the ARM the PC register contains 'dot + 8' at the time of the
3042 addition, on the Thumb it is 'dot + 4'. */
3043 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3045 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3046 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3048 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3050 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3054 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3055 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3059 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3063 /* We will have pushed the pic register, so should always be
3064 able to find a work register. */
3065 reg = thumb_find_work_register (thumb_compute_save_reg_mask ());
3066 pic_tmp = gen_rtx_REG (SImode, reg);
3067 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3068 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3071 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3072 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3075 /* Need to emit this whether or not we obey regdecls,
3076 since setjmp/longjmp can cause life info to screw up. */
3077 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3078 #endif /* AOF_ASSEMBLER */
3082 /* Return nonzero if X is valid as an ARM state addressing register. */
3084 arm_address_register_rtx_p (rtx x, int strict_p)
3088 if (GET_CODE (x) != REG)
3094 return ARM_REGNO_OK_FOR_BASE_P (regno);
3096 return (regno <= LAST_ARM_REGNUM
3097 || regno >= FIRST_PSEUDO_REGISTER
3098 || regno == FRAME_POINTER_REGNUM
3099 || regno == ARG_POINTER_REGNUM);
3102 /* Return nonzero if X is a valid ARM state address operand. */
3104 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3108 enum rtx_code code = GET_CODE (x);
3110 if (arm_address_register_rtx_p (x, strict_p))
3113 use_ldrd = (TARGET_LDRD
3115 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3117 if (code == POST_INC || code == PRE_DEC
3118 || ((code == PRE_INC || code == POST_DEC)
3119 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3120 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3122 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3123 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3124 && GET_CODE (XEXP (x, 1)) == PLUS
3125 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3127 rtx addend = XEXP (XEXP (x, 1), 1);
3129 /* Don't allow ldrd post increment by register becuase it's hard
3130 to fixup invalid register choices. */
3132 && GET_CODE (x) == POST_MODIFY
3133 && GET_CODE (addend) == REG)
3136 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3137 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3140 /* After reload constants split into minipools will have addresses
3141 from a LABEL_REF. */
3142 else if (reload_completed
3143 && (code == LABEL_REF
3145 && GET_CODE (XEXP (x, 0)) == PLUS
3146 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3147 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3150 else if (mode == TImode)
3153 else if (code == PLUS)
3155 rtx xop0 = XEXP (x, 0);
3156 rtx xop1 = XEXP (x, 1);
3158 return ((arm_address_register_rtx_p (xop0, strict_p)
3159 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3160 || (arm_address_register_rtx_p (xop1, strict_p)
3161 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3165 /* Reload currently can't handle MINUS, so disable this for now */
3166 else if (GET_CODE (x) == MINUS)
3168 rtx xop0 = XEXP (x, 0);
3169 rtx xop1 = XEXP (x, 1);
3171 return (arm_address_register_rtx_p (xop0, strict_p)
3172 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3176 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3177 && code == SYMBOL_REF
3178 && CONSTANT_POOL_ADDRESS_P (x)
3180 && symbol_mentioned_p (get_pool_constant (x))))
3186 /* Return nonzero if INDEX is valid for an address index operand in
3189 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3192 HOST_WIDE_INT range;
3193 enum rtx_code code = GET_CODE (index);
3195 /* Standard coprocessor addressing modes. */
3196 if (TARGET_HARD_FLOAT
3197 && (TARGET_FPA || TARGET_MAVERICK)
3198 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3199 || (TARGET_MAVERICK && mode == DImode)))
3200 return (code == CONST_INT && INTVAL (index) < 1024
3201 && INTVAL (index) > -1024
3202 && (INTVAL (index) & 3) == 0);
3204 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3205 return (code == CONST_INT
3206 && INTVAL (index) < 1024
3207 && INTVAL (index) > -1024
3208 && (INTVAL (index) & 3) == 0);
3210 if (arm_address_register_rtx_p (index, strict_p)
3211 && (GET_MODE_SIZE (mode) <= 4))
3214 if (mode == DImode || mode == DFmode)
3216 if (code == CONST_INT)
3218 HOST_WIDE_INT val = INTVAL (index);
3221 return val > -256 && val < 256;
3223 return val > -4096 && val < 4092;
3226 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3229 if (GET_MODE_SIZE (mode) <= 4
3232 || (mode == QImode && outer == SIGN_EXTEND))))
3236 rtx xiop0 = XEXP (index, 0);
3237 rtx xiop1 = XEXP (index, 1);
3239 return ((arm_address_register_rtx_p (xiop0, strict_p)
3240 && power_of_two_operand (xiop1, SImode))
3241 || (arm_address_register_rtx_p (xiop1, strict_p)
3242 && power_of_two_operand (xiop0, SImode)));
3244 else if (code == LSHIFTRT || code == ASHIFTRT
3245 || code == ASHIFT || code == ROTATERT)
3247 rtx op = XEXP (index, 1);
3249 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3250 && GET_CODE (op) == CONST_INT
3252 && INTVAL (op) <= 31);
3256 /* For ARM v4 we may be doing a sign-extend operation during the
3260 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3266 range = (mode == HImode) ? 4095 : 4096;
3268 return (code == CONST_INT
3269 && INTVAL (index) < range
3270 && INTVAL (index) > -range);
3273 /* Return nonzero if X is valid as a Thumb state base register. */
3275 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3279 if (GET_CODE (x) != REG)
3285 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3287 return (regno <= LAST_LO_REGNUM
3288 || regno > LAST_VIRTUAL_REGISTER
3289 || regno == FRAME_POINTER_REGNUM
3290 || (GET_MODE_SIZE (mode) >= 4
3291 && (regno == STACK_POINTER_REGNUM
3292 || regno >= FIRST_PSEUDO_REGISTER
3293 || x == hard_frame_pointer_rtx
3294 || x == arg_pointer_rtx)));
3297 /* Return nonzero if x is a legitimate index register. This is the case
3298 for any base register that can access a QImode object. */
3300 thumb_index_register_rtx_p (rtx x, int strict_p)
3302 return thumb_base_register_rtx_p (x, QImode, strict_p);
3305 /* Return nonzero if x is a legitimate Thumb-state address.
3307 The AP may be eliminated to either the SP or the FP, so we use the
3308 least common denominator, e.g. SImode, and offsets from 0 to 64.
3310 ??? Verify whether the above is the right approach.
3312 ??? Also, the FP may be eliminated to the SP, so perhaps that
3313 needs special handling also.
3315 ??? Look at how the mips16 port solves this problem. It probably uses
3316 better ways to solve some of these problems.
3318 Although it is not incorrect, we don't accept QImode and HImode
3319 addresses based on the frame pointer or arg pointer until the
3320 reload pass starts. This is so that eliminating such addresses
3321 into stack based ones won't produce impossible code. */
3323 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3325 /* ??? Not clear if this is right. Experiment. */
3326 if (GET_MODE_SIZE (mode) < 4
3327 && !(reload_in_progress || reload_completed)
3328 && (reg_mentioned_p (frame_pointer_rtx, x)
3329 || reg_mentioned_p (arg_pointer_rtx, x)
3330 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3331 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3332 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3333 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3336 /* Accept any base register. SP only in SImode or larger. */
3337 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3340 /* This is PC relative data before arm_reorg runs. */
3341 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3342 && GET_CODE (x) == SYMBOL_REF
3343 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3346 /* This is PC relative data after arm_reorg runs. */
3347 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3348 && (GET_CODE (x) == LABEL_REF
3349 || (GET_CODE (x) == CONST
3350 && GET_CODE (XEXP (x, 0)) == PLUS
3351 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3352 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3355 /* Post-inc indexing only supported for SImode and larger. */
3356 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3357 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3360 else if (GET_CODE (x) == PLUS)
3362 /* REG+REG address can be any two index registers. */
3363 /* We disallow FRAME+REG addressing since we know that FRAME
3364 will be replaced with STACK, and SP relative addressing only
3365 permits SP+OFFSET. */
3366 if (GET_MODE_SIZE (mode) <= 4
3367 && XEXP (x, 0) != frame_pointer_rtx
3368 && XEXP (x, 1) != frame_pointer_rtx
3369 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3370 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3373 /* REG+const has 5-7 bit offset for non-SP registers. */
3374 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3375 || XEXP (x, 0) == arg_pointer_rtx)
3376 && GET_CODE (XEXP (x, 1)) == CONST_INT
3377 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3380 /* REG+const has 10 bit offset for SP, but only SImode and
3381 larger is supported. */
3382 /* ??? Should probably check for DI/DFmode overflow here
3383 just like GO_IF_LEGITIMATE_OFFSET does. */
3384 else if (GET_CODE (XEXP (x, 0)) == REG
3385 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3386 && GET_MODE_SIZE (mode) >= 4
3387 && GET_CODE (XEXP (x, 1)) == CONST_INT
3388 && INTVAL (XEXP (x, 1)) >= 0
3389 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3390 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3393 else if (GET_CODE (XEXP (x, 0)) == REG
3394 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3395 && GET_MODE_SIZE (mode) >= 4
3396 && GET_CODE (XEXP (x, 1)) == CONST_INT
3397 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3401 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3402 && GET_MODE_SIZE (mode) == 4
3403 && GET_CODE (x) == SYMBOL_REF
3404 && CONSTANT_POOL_ADDRESS_P (x)
3406 && symbol_mentioned_p (get_pool_constant (x))))
3412 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3413 instruction of mode MODE. */
3415 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3417 switch (GET_MODE_SIZE (mode))
3420 return val >= 0 && val < 32;
3423 return val >= 0 && val < 64 && (val & 1) == 0;
3427 && (val + GET_MODE_SIZE (mode)) <= 128
3432 /* Try machine-dependent ways of modifying an illegitimate address
3433 to be legitimate. If we find one, return the new, valid address. */
3435 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3437 if (GET_CODE (x) == PLUS)
3439 rtx xop0 = XEXP (x, 0);
3440 rtx xop1 = XEXP (x, 1);
3442 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3443 xop0 = force_reg (SImode, xop0);
3445 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3446 xop1 = force_reg (SImode, xop1);
3448 if (ARM_BASE_REGISTER_RTX_P (xop0)
3449 && GET_CODE (xop1) == CONST_INT)
3451 HOST_WIDE_INT n, low_n;
3455 /* VFP addressing modes actually allow greater offsets, but for
3456 now we just stick with the lowest common denominator. */
3458 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3470 low_n = ((mode) == TImode ? 0
3471 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3475 base_reg = gen_reg_rtx (SImode);
3476 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3477 GEN_INT (n)), NULL_RTX);
3478 emit_move_insn (base_reg, val);
3479 x = (low_n == 0 ? base_reg
3480 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3482 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3483 x = gen_rtx_PLUS (SImode, xop0, xop1);
3486 /* XXX We don't allow MINUS any more -- see comment in
3487 arm_legitimate_address_p (). */
3488 else if (GET_CODE (x) == MINUS)
3490 rtx xop0 = XEXP (x, 0);
3491 rtx xop1 = XEXP (x, 1);
3493 if (CONSTANT_P (xop0))
3494 xop0 = force_reg (SImode, xop0);
3496 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3497 xop1 = force_reg (SImode, xop1);
3499 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3500 x = gen_rtx_MINUS (SImode, xop0, xop1);
3505 /* We need to find and carefully transform any SYMBOL and LABEL
3506 references; so go back to the original address expression. */
3507 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3509 if (new_x != orig_x)
3517 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3518 to be legitimate. If we find one, return the new, valid address. */
3520 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3522 if (GET_CODE (x) == PLUS
3523 && GET_CODE (XEXP (x, 1)) == CONST_INT
3524 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3525 || INTVAL (XEXP (x, 1)) < 0))
3527 rtx xop0 = XEXP (x, 0);
3528 rtx xop1 = XEXP (x, 1);
3529 HOST_WIDE_INT offset = INTVAL (xop1);
3531 /* Try and fold the offset into a biasing of the base register and
3532 then offsetting that. Don't do this when optimizing for space
3533 since it can cause too many CSEs. */
3534 if (optimize_size && offset >= 0
3535 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3537 HOST_WIDE_INT delta;
3540 delta = offset - (256 - GET_MODE_SIZE (mode));
3541 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3542 delta = 31 * GET_MODE_SIZE (mode);
3544 delta = offset & (~31 * GET_MODE_SIZE (mode));
3546 xop0 = force_operand (plus_constant (xop0, offset - delta),
3548 x = plus_constant (xop0, delta);
3550 else if (offset < 0 && offset > -256)
3551 /* Small negative offsets are best done with a subtract before the
3552 dereference, forcing these into a register normally takes two
3554 x = force_operand (x, NULL_RTX);
3557 /* For the remaining cases, force the constant into a register. */
3558 xop1 = force_reg (SImode, xop1);
3559 x = gen_rtx_PLUS (SImode, xop0, xop1);
3562 else if (GET_CODE (x) == PLUS
3563 && s_register_operand (XEXP (x, 1), SImode)
3564 && !s_register_operand (XEXP (x, 0), SImode))
3566 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3568 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3573 /* We need to find and carefully transform any SYMBOL and LABEL
3574 references; so go back to the original address expression. */
3575 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3577 if (new_x != orig_x)
3586 #define REG_OR_SUBREG_REG(X) \
3587 (GET_CODE (X) == REG \
3588 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3590 #define REG_OR_SUBREG_RTX(X) \
3591 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3593 #ifndef COSTS_N_INSNS
3594 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3597 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3599 enum machine_mode mode = GET_MODE (x);
3612 return COSTS_N_INSNS (1);
3615 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3618 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3625 return COSTS_N_INSNS (2) + cycles;
3627 return COSTS_N_INSNS (1) + 16;
3630 return (COSTS_N_INSNS (1)
3631 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3632 + GET_CODE (SET_DEST (x)) == MEM));
3637 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3639 if (thumb_shiftable_const (INTVAL (x)))
3640 return COSTS_N_INSNS (2);
3641 return COSTS_N_INSNS (3);
3643 else if ((outer == PLUS || outer == COMPARE)
3644 && INTVAL (x) < 256 && INTVAL (x) > -256)
3646 else if (outer == AND
3647 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3648 return COSTS_N_INSNS (1);
3649 else if (outer == ASHIFT || outer == ASHIFTRT
3650 || outer == LSHIFTRT)
3652 return COSTS_N_INSNS (2);
3658 return COSTS_N_INSNS (3);
3676 /* XXX another guess. */
3677 /* Memory costs quite a lot for the first word, but subsequent words
3678 load at the equivalent of a single insn each. */
3679 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3680 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3685 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3690 /* XXX still guessing. */
3691 switch (GET_MODE (XEXP (x, 0)))
3694 return (1 + (mode == DImode ? 4 : 0)
3695 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3698 return (4 + (mode == DImode ? 4 : 0)
3699 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3702 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3714 /* Worker routine for arm_rtx_costs. */
3716 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3718 enum machine_mode mode = GET_MODE (x);
3719 enum rtx_code subcode;
3725 /* Memory costs quite a lot for the first word, but subsequent words
3726 load at the equivalent of a single insn each. */
3727 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3728 + (GET_CODE (x) == SYMBOL_REF
3729 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3735 return optimize_size ? COSTS_N_INSNS (2) : 100;
3738 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3745 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3747 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3748 + ((GET_CODE (XEXP (x, 0)) == REG
3749 || (GET_CODE (XEXP (x, 0)) == SUBREG
3750 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3752 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3753 || (GET_CODE (XEXP (x, 0)) == SUBREG
3754 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3756 + ((GET_CODE (XEXP (x, 1)) == REG
3757 || (GET_CODE (XEXP (x, 1)) == SUBREG
3758 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3759 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3764 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3765 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3766 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3767 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3770 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3771 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3772 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3773 && arm_const_double_rtx (XEXP (x, 1))))
3775 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3776 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3777 && arm_const_double_rtx (XEXP (x, 0))))
3780 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3781 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3782 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3783 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3784 || subcode == ASHIFTRT || subcode == LSHIFTRT
3785 || subcode == ROTATE || subcode == ROTATERT
3787 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3788 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3789 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3790 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3791 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3792 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3793 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3798 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3799 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3800 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3801 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3802 && arm_const_double_rtx (XEXP (x, 1))))
3806 case AND: case XOR: case IOR:
3809 /* Normally the frame registers will be spilt into reg+const during
3810 reload, so it is a bad idea to combine them with other instructions,
3811 since then they might not be moved outside of loops. As a compromise
3812 we allow integration with ops that have a constant as their second
3814 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3815 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3816 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3817 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3818 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3822 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3823 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3824 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3825 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3828 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3829 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3830 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3831 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3832 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3835 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3836 return (1 + extra_cost
3837 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3838 || subcode == LSHIFTRT || subcode == ASHIFTRT
3839 || subcode == ROTATE || subcode == ROTATERT
3841 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3842 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3843 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3844 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3845 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3846 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3852 /* This should have been handled by the CPU specific routines. */
3856 if (arm_arch3m && mode == SImode
3857 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3858 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3859 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3860 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3861 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3862 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3867 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3868 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3872 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3874 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3877 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3885 return 4 + (mode == DImode ? 4 : 0);
3888 if (GET_MODE (XEXP (x, 0)) == QImode)
3889 return (4 + (mode == DImode ? 4 : 0)
3890 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3893 switch (GET_MODE (XEXP (x, 0)))
3896 return (1 + (mode == DImode ? 4 : 0)
3897 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3900 return (4 + (mode == DImode ? 4 : 0)
3901 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3904 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3919 if (const_ok_for_arm (INTVAL (x)))
3920 return outer == SET ? 2 : -1;
3921 else if (outer == AND
3922 && const_ok_for_arm (~INTVAL (x)))
3924 else if ((outer == COMPARE
3925 || outer == PLUS || outer == MINUS)
3926 && const_ok_for_arm (-INTVAL (x)))
3937 if (arm_const_double_rtx (x))
3938 return outer == SET ? 2 : -1;
3939 else if ((outer == COMPARE || outer == PLUS)
3940 && neg_const_double_rtx_ok_for_fpa (x))
3949 /* RTX costs when optimizing for size. */
3951 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
3953 enum machine_mode mode = GET_MODE (x);
3957 /* XXX TBD. For now, use the standard costs. */
3958 *total = thumb_rtx_costs (x, code, outer_code);
3965 /* A memory access costs 1 insn if the mode is small, or the address is
3966 a single register, otherwise it costs one insn per word. */
3967 if (REG_P (XEXP (x, 0)))
3968 *total = COSTS_N_INSNS (1);
3970 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
3977 /* Needs a libcall, so it costs about this. */
3978 *total = COSTS_N_INSNS (2);
3982 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3984 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
3992 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
3994 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
3997 else if (mode == SImode)
3999 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4000 /* Slightly disparage register shifts, but not by much. */
4001 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4002 *total += 1 + rtx_cost (XEXP (x, 1), code);
4006 /* Needs a libcall. */
4007 *total = COSTS_N_INSNS (2);
4011 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4013 *total = COSTS_N_INSNS (1);
4019 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4020 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4022 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4023 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4024 || subcode1 == ROTATE || subcode1 == ROTATERT
4025 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4026 || subcode1 == ASHIFTRT)
4028 /* It's just the cost of the two operands. */
4033 *total = COSTS_N_INSNS (1);
4037 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4041 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4043 *total = COSTS_N_INSNS (1);
4048 case AND: case XOR: case IOR:
4051 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4053 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4054 || subcode == LSHIFTRT || subcode == ASHIFTRT
4055 || (code == AND && subcode == NOT))
4057 /* It's just the cost of the two operands. */
4063 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4067 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4071 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4072 *total = COSTS_N_INSNS (1);
4075 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4084 if (cc_register (XEXP (x, 0), VOIDmode))
4087 *total = COSTS_N_INSNS (1);
4091 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4092 *total = COSTS_N_INSNS (1);
4094 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4099 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4101 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4102 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4105 *total += COSTS_N_INSNS (1);
4110 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4112 switch (GET_MODE (XEXP (x, 0)))
4115 *total += COSTS_N_INSNS (1);
4119 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4125 *total += COSTS_N_INSNS (2);
4130 *total += COSTS_N_INSNS (1);
4135 if (const_ok_for_arm (INTVAL (x)))
4136 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4137 else if (const_ok_for_arm (~INTVAL (x)))
4138 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4139 else if (const_ok_for_arm (-INTVAL (x)))
4141 if (outer_code == COMPARE || outer_code == PLUS
4142 || outer_code == MINUS)
4145 *total = COSTS_N_INSNS (1);
4148 *total = COSTS_N_INSNS (2);
4154 *total = COSTS_N_INSNS (2);
4158 *total = COSTS_N_INSNS (4);
4162 if (mode != VOIDmode)
4163 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4165 *total = COSTS_N_INSNS (4); /* How knows? */
4170 /* RTX costs for cores with a slow MUL implementation. */
4173 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4175 enum machine_mode mode = GET_MODE (x);
4179 *total = thumb_rtx_costs (x, code, outer_code);
4186 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4193 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4195 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4196 & (unsigned HOST_WIDE_INT) 0xffffffff);
4197 int cost, const_ok = const_ok_for_arm (i);
4198 int j, booth_unit_size;
4200 /* Tune as appropriate. */
4201 cost = const_ok ? 4 : 8;
4202 booth_unit_size = 2;
4203 for (j = 0; i && j < 32; j += booth_unit_size)
4205 i >>= booth_unit_size;
4213 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4214 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4218 *total = arm_rtx_costs_1 (x, code, outer_code);
4224 /* RTX cost for cores with a fast multiply unit (M variants). */
4227 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4229 enum machine_mode mode = GET_MODE (x);
4233 *total = thumb_rtx_costs (x, code, outer_code);
4240 /* There is no point basing this on the tuning, since it is always the
4241 fast variant if it exists at all. */
4243 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4244 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4245 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4252 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4259 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4261 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4262 & (unsigned HOST_WIDE_INT) 0xffffffff);
4263 int cost, const_ok = const_ok_for_arm (i);
4264 int j, booth_unit_size;
4266 /* Tune as appropriate. */
4267 cost = const_ok ? 4 : 8;
4268 booth_unit_size = 8;
4269 for (j = 0; i && j < 32; j += booth_unit_size)
4271 i >>= booth_unit_size;
4279 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4280 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4284 *total = arm_rtx_costs_1 (x, code, outer_code);
4290 /* RTX cost for XScale CPUs. */
4293 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4295 enum machine_mode mode = GET_MODE (x);
4299 *total = thumb_rtx_costs (x, code, outer_code);
4306 /* There is no point basing this on the tuning, since it is always the
4307 fast variant if it exists at all. */
4309 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4310 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4311 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4318 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4325 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4327 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4328 & (unsigned HOST_WIDE_INT) 0xffffffff);
4329 int cost, const_ok = const_ok_for_arm (i);
4330 unsigned HOST_WIDE_INT masked_const;
4332 /* The cost will be related to two insns.
4333 First a load of the constant (MOV or LDR), then a multiply. */
4336 cost += 1; /* LDR is probably more expensive because
4337 of longer result latency. */
4338 masked_const = i & 0xffff8000;
4339 if (masked_const != 0 && masked_const != 0xffff8000)
4341 masked_const = i & 0xf8000000;
4342 if (masked_const == 0 || masked_const == 0xf8000000)
4351 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4352 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4356 *total = arm_rtx_costs_1 (x, code, outer_code);
4362 /* RTX costs for 9e (and later) cores. */
4365 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4367 enum machine_mode mode = GET_MODE (x);
4376 *total = COSTS_N_INSNS (3);
4380 *total = thumb_rtx_costs (x, code, outer_code);
4388 /* There is no point basing this on the tuning, since it is always the
4389 fast variant if it exists at all. */
4391 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4392 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4393 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4400 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4417 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4418 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4422 *total = arm_rtx_costs_1 (x, code, outer_code);
4426 /* All address computations that can be done are free, but rtx cost returns
4427 the same for practically all of them. So we weight the different types
4428 of address here in the order (most pref first):
4429 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4431 arm_arm_address_cost (rtx x)
4433 enum rtx_code c = GET_CODE (x);
4435 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4437 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4440 if (c == PLUS || c == MINUS)
4442 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4445 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4455 arm_thumb_address_cost (rtx x)
4457 enum rtx_code c = GET_CODE (x);
4462 && GET_CODE (XEXP (x, 0)) == REG
4463 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4470 arm_address_cost (rtx x)
4472 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4476 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4480 /* Some true dependencies can have a higher cost depending
4481 on precisely how certain input operands are used. */
4483 && REG_NOTE_KIND (link) == 0
4484 && recog_memoized (insn) >= 0
4485 && recog_memoized (dep) >= 0)
4487 int shift_opnum = get_attr_shift (insn);
4488 enum attr_type attr_type = get_attr_type (dep);
4490 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4491 operand for INSN. If we have a shifted input operand and the
4492 instruction we depend on is another ALU instruction, then we may
4493 have to account for an additional stall. */
4494 if (shift_opnum != 0
4495 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4497 rtx shifted_operand;
4500 /* Get the shifted operand. */
4501 extract_insn (insn);
4502 shifted_operand = recog_data.operand[shift_opnum];
4504 /* Iterate over all the operands in DEP. If we write an operand
4505 that overlaps with SHIFTED_OPERAND, then we have increase the
4506 cost of this dependency. */
4508 preprocess_constraints ();
4509 for (opno = 0; opno < recog_data.n_operands; opno++)
4511 /* We can ignore strict inputs. */
4512 if (recog_data.operand_type[opno] == OP_IN)
4515 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4522 /* XXX This is not strictly true for the FPA. */
4523 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4524 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4527 /* Call insns don't incur a stall, even if they follow a load. */
4528 if (REG_NOTE_KIND (link) == 0
4529 && GET_CODE (insn) == CALL_INSN)
4532 if ((i_pat = single_set (insn)) != NULL
4533 && GET_CODE (SET_SRC (i_pat)) == MEM
4534 && (d_pat = single_set (dep)) != NULL
4535 && GET_CODE (SET_DEST (d_pat)) == MEM)
4537 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4538 /* This is a load after a store, there is no conflict if the load reads
4539 from a cached area. Assume that loads from the stack, and from the
4540 constant pool are cached, and that others will miss. This is a
4543 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4544 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4545 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4546 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4553 static int fp_consts_inited = 0;
4555 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4556 static const char * const strings_fp[8] =
4559 "4", "5", "0.5", "10"
4562 static REAL_VALUE_TYPE values_fp[8];
4565 init_fp_table (void)
4571 fp_consts_inited = 1;
4573 fp_consts_inited = 8;
4575 for (i = 0; i < fp_consts_inited; i++)
4577 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4582 /* Return TRUE if rtx X is a valid immediate FP constant. */
4584 arm_const_double_rtx (rtx x)
4589 if (!fp_consts_inited)
4592 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4593 if (REAL_VALUE_MINUS_ZERO (r))
4596 for (i = 0; i < fp_consts_inited; i++)
4597 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4603 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4605 neg_const_double_rtx_ok_for_fpa (rtx x)
4610 if (!fp_consts_inited)
4613 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4614 r = REAL_VALUE_NEGATE (r);
4615 if (REAL_VALUE_MINUS_ZERO (r))
4618 for (i = 0; i < 8; i++)
4619 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4625 /* Predicates for `match_operand' and `match_operator'. */
4627 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4629 cirrus_memory_offset (rtx op)
4631 /* Reject eliminable registers. */
4632 if (! (reload_in_progress || reload_completed)
4633 && ( reg_mentioned_p (frame_pointer_rtx, op)
4634 || reg_mentioned_p (arg_pointer_rtx, op)
4635 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4636 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4637 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4638 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4641 if (GET_CODE (op) == MEM)
4647 /* Match: (mem (reg)). */
4648 if (GET_CODE (ind) == REG)
4654 if (GET_CODE (ind) == PLUS
4655 && GET_CODE (XEXP (ind, 0)) == REG
4656 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4657 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4664 /* Return TRUE if OP is a valid VFP memory address pattern.
4665 WB if true if writeback address modes are allowed. */
4668 arm_coproc_mem_operand (rtx op, bool wb)
4672 /* Reject eliminable registers. */
4673 if (! (reload_in_progress || reload_completed)
4674 && ( reg_mentioned_p (frame_pointer_rtx, op)
4675 || reg_mentioned_p (arg_pointer_rtx, op)
4676 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4677 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4678 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4679 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4682 /* Constants are converted into offsets from labels. */
4683 if (GET_CODE (op) != MEM)
4688 if (reload_completed
4689 && (GET_CODE (ind) == LABEL_REF
4690 || (GET_CODE (ind) == CONST
4691 && GET_CODE (XEXP (ind, 0)) == PLUS
4692 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4693 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4696 /* Match: (mem (reg)). */
4697 if (GET_CODE (ind) == REG)
4698 return arm_address_register_rtx_p (ind, 0);
4700 /* Autoincremment addressing modes. */
4702 && (GET_CODE (ind) == PRE_INC
4703 || GET_CODE (ind) == POST_INC
4704 || GET_CODE (ind) == PRE_DEC
4705 || GET_CODE (ind) == POST_DEC))
4706 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4709 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4710 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4711 && GET_CODE (XEXP (ind, 1)) == PLUS
4712 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4713 ind = XEXP (ind, 1);
4718 if (GET_CODE (ind) == PLUS
4719 && GET_CODE (XEXP (ind, 0)) == REG
4720 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4721 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4722 && INTVAL (XEXP (ind, 1)) > -1024
4723 && INTVAL (XEXP (ind, 1)) < 1024
4724 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4731 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4732 VFP registers. Otherwise return NO_REGS. */
4735 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4737 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4740 return GENERAL_REGS;
4744 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4745 Use by the Cirrus Maverick code which has to workaround
4746 a hardware bug triggered by such instructions. */
4748 arm_memory_load_p (rtx insn)
4750 rtx body, lhs, rhs;;
4752 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4755 body = PATTERN (insn);
4757 if (GET_CODE (body) != SET)
4760 lhs = XEXP (body, 0);
4761 rhs = XEXP (body, 1);
4763 lhs = REG_OR_SUBREG_RTX (lhs);
4765 /* If the destination is not a general purpose
4766 register we do not have to worry. */
4767 if (GET_CODE (lhs) != REG
4768 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4771 /* As well as loads from memory we also have to react
4772 to loads of invalid constants which will be turned
4773 into loads from the minipool. */
4774 return (GET_CODE (rhs) == MEM
4775 || GET_CODE (rhs) == SYMBOL_REF
4776 || note_invalid_constants (insn, -1, false));
4779 /* Return TRUE if INSN is a Cirrus instruction. */
4781 arm_cirrus_insn_p (rtx insn)
4783 enum attr_cirrus attr;
4785 /* get_attr aborts on USE and CLOBBER. */
4787 || GET_CODE (insn) != INSN
4788 || GET_CODE (PATTERN (insn)) == USE
4789 || GET_CODE (PATTERN (insn)) == CLOBBER)
4792 attr = get_attr_cirrus (insn);
4794 return attr != CIRRUS_NOT;
4797 /* Cirrus reorg for invalid instruction combinations. */
4799 cirrus_reorg (rtx first)
4801 enum attr_cirrus attr;
4802 rtx body = PATTERN (first);
4806 /* Any branch must be followed by 2 non Cirrus instructions. */
4807 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4810 t = next_nonnote_insn (first);
4812 if (arm_cirrus_insn_p (t))
4815 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4819 emit_insn_after (gen_nop (), first);
4824 /* (float (blah)) is in parallel with a clobber. */
4825 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4826 body = XVECEXP (body, 0, 0);
4828 if (GET_CODE (body) == SET)
4830 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4832 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4833 be followed by a non Cirrus insn. */
4834 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4836 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4837 emit_insn_after (gen_nop (), first);
4841 else if (arm_memory_load_p (first))
4843 unsigned int arm_regno;
4845 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4846 ldr/cfmv64hr combination where the Rd field is the same
4847 in both instructions must be split with a non Cirrus
4854 /* Get Arm register number for ldr insn. */
4855 if (GET_CODE (lhs) == REG)
4856 arm_regno = REGNO (lhs);
4857 else if (GET_CODE (rhs) == REG)
4858 arm_regno = REGNO (rhs);
4863 first = next_nonnote_insn (first);
4865 if (! arm_cirrus_insn_p (first))
4868 body = PATTERN (first);
4870 /* (float (blah)) is in parallel with a clobber. */
4871 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4872 body = XVECEXP (body, 0, 0);
4874 if (GET_CODE (body) == FLOAT)
4875 body = XEXP (body, 0);
4877 if (get_attr_cirrus (first) == CIRRUS_MOVE
4878 && GET_CODE (XEXP (body, 1)) == REG
4879 && arm_regno == REGNO (XEXP (body, 1)))
4880 emit_insn_after (gen_nop (), first);
4886 /* get_attr aborts on USE and CLOBBER. */
4888 || GET_CODE (first) != INSN
4889 || GET_CODE (PATTERN (first)) == USE
4890 || GET_CODE (PATTERN (first)) == CLOBBER)
4893 attr = get_attr_cirrus (first);
4895 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4896 must be followed by a non-coprocessor instruction. */
4897 if (attr == CIRRUS_COMPARE)
4901 t = next_nonnote_insn (first);
4903 if (arm_cirrus_insn_p (t))
4906 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4910 emit_insn_after (gen_nop (), first);
4916 /* Return TRUE if X references a SYMBOL_REF. */
4918 symbol_mentioned_p (rtx x)
4923 if (GET_CODE (x) == SYMBOL_REF)
4926 fmt = GET_RTX_FORMAT (GET_CODE (x));
4928 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4934 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4935 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4938 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4945 /* Return TRUE if X references a LABEL_REF. */
4947 label_mentioned_p (rtx x)
4952 if (GET_CODE (x) == LABEL_REF)
4955 fmt = GET_RTX_FORMAT (GET_CODE (x));
4956 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4962 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4963 if (label_mentioned_p (XVECEXP (x, i, j)))
4966 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4976 enum rtx_code code = GET_CODE (x);
4980 else if (code == SMIN)
4982 else if (code == UMIN)
4984 else if (code == UMAX)
4990 /* Return 1 if memory locations are adjacent. */
4992 adjacent_mem_locations (rtx a, rtx b)
4994 if ((GET_CODE (XEXP (a, 0)) == REG
4995 || (GET_CODE (XEXP (a, 0)) == PLUS
4996 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4997 && (GET_CODE (XEXP (b, 0)) == REG
4998 || (GET_CODE (XEXP (b, 0)) == PLUS
4999 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5001 int val0 = 0, val1 = 0;
5004 if (GET_CODE (XEXP (a, 0)) == PLUS)
5006 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5007 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5010 reg0 = REGNO (XEXP (a, 0));
5012 if (GET_CODE (XEXP (b, 0)) == PLUS)
5014 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5015 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5018 reg1 = REGNO (XEXP (b, 0));
5020 /* Don't accept any offset that will require multiple
5021 instructions to handle, since this would cause the
5022 arith_adjacentmem pattern to output an overlong sequence. */
5023 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5026 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5032 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5033 HOST_WIDE_INT *load_offset)
5035 int unsorted_regs[4];
5036 HOST_WIDE_INT unsorted_offsets[4];
5041 /* Can only handle 2, 3, or 4 insns at present,
5042 though could be easily extended if required. */
5043 if (nops < 2 || nops > 4)
5046 /* Loop over the operands and check that the memory references are
5047 suitable (ie immediate offsets from the same base register). At
5048 the same time, extract the target register, and the memory
5050 for (i = 0; i < nops; i++)
5055 /* Convert a subreg of a mem into the mem itself. */
5056 if (GET_CODE (operands[nops + i]) == SUBREG)
5057 operands[nops + i] = alter_subreg (operands + (nops + i));
5059 if (GET_CODE (operands[nops + i]) != MEM)
5062 /* Don't reorder volatile memory references; it doesn't seem worth
5063 looking for the case where the order is ok anyway. */
5064 if (MEM_VOLATILE_P (operands[nops + i]))
5067 offset = const0_rtx;
5069 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5070 || (GET_CODE (reg) == SUBREG
5071 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5072 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5073 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5075 || (GET_CODE (reg) == SUBREG
5076 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5077 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5082 base_reg = REGNO (reg);
5083 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5084 ? REGNO (operands[i])
5085 : REGNO (SUBREG_REG (operands[i])));
5090 if (base_reg != (int) REGNO (reg))
5091 /* Not addressed from the same base register. */
5094 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5095 ? REGNO (operands[i])
5096 : REGNO (SUBREG_REG (operands[i])));
5097 if (unsorted_regs[i] < unsorted_regs[order[0]])
5101 /* If it isn't an integer register, or if it overwrites the
5102 base register but isn't the last insn in the list, then
5103 we can't do this. */
5104 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5105 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5108 unsorted_offsets[i] = INTVAL (offset);
5111 /* Not a suitable memory address. */
5115 /* All the useful information has now been extracted from the
5116 operands into unsorted_regs and unsorted_offsets; additionally,
5117 order[0] has been set to the lowest numbered register in the
5118 list. Sort the registers into order, and check that the memory
5119 offsets are ascending and adjacent. */
5121 for (i = 1; i < nops; i++)
5125 order[i] = order[i - 1];
5126 for (j = 0; j < nops; j++)
5127 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5128 && (order[i] == order[i - 1]
5129 || unsorted_regs[j] < unsorted_regs[order[i]]))
5132 /* Have we found a suitable register? if not, one must be used more
5134 if (order[i] == order[i - 1])
5137 /* Is the memory address adjacent and ascending? */
5138 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5146 for (i = 0; i < nops; i++)
5147 regs[i] = unsorted_regs[order[i]];
5149 *load_offset = unsorted_offsets[order[0]];
5152 if (unsorted_offsets[order[0]] == 0)
5153 return 1; /* ldmia */
5155 if (unsorted_offsets[order[0]] == 4)
5156 return 2; /* ldmib */
5158 if (unsorted_offsets[order[nops - 1]] == 0)
5159 return 3; /* ldmda */
5161 if (unsorted_offsets[order[nops - 1]] == -4)
5162 return 4; /* ldmdb */
5164 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5165 if the offset isn't small enough. The reason 2 ldrs are faster
5166 is because these ARMs are able to do more than one cache access
5167 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5168 whilst the ARM8 has a double bandwidth cache. This means that
5169 these cores can do both an instruction fetch and a data fetch in
5170 a single cycle, so the trick of calculating the address into a
5171 scratch register (one of the result regs) and then doing a load
5172 multiple actually becomes slower (and no smaller in code size).
5173 That is the transformation
5175 ldr rd1, [rbase + offset]
5176 ldr rd2, [rbase + offset + 4]
5180 add rd1, rbase, offset
5181 ldmia rd1, {rd1, rd2}
5183 produces worse code -- '3 cycles + any stalls on rd2' instead of
5184 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5185 access per cycle, the first sequence could never complete in less
5186 than 6 cycles, whereas the ldm sequence would only take 5 and
5187 would make better use of sequential accesses if not hitting the
5190 We cheat here and test 'arm_ld_sched' which we currently know to
5191 only be true for the ARM8, ARM9 and StrongARM. If this ever
5192 changes, then the test below needs to be reworked. */
5193 if (nops == 2 && arm_ld_sched)
5196 /* Can't do it without setting up the offset, only do this if it takes
5197 no more than one insn. */
5198 return (const_ok_for_arm (unsorted_offsets[order[0]])
5199 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5203 emit_ldm_seq (rtx *operands, int nops)
5207 HOST_WIDE_INT offset;
5211 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5214 strcpy (buf, "ldm%?ia\t");
5218 strcpy (buf, "ldm%?ib\t");
5222 strcpy (buf, "ldm%?da\t");
5226 strcpy (buf, "ldm%?db\t");
5231 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5232 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5235 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5236 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5238 output_asm_insn (buf, operands);
5240 strcpy (buf, "ldm%?ia\t");
5247 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5248 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5250 for (i = 1; i < nops; i++)
5251 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5252 reg_names[regs[i]]);
5254 strcat (buf, "}\t%@ phole ldm");
5256 output_asm_insn (buf, operands);
5261 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5262 HOST_WIDE_INT * load_offset)
5264 int unsorted_regs[4];
5265 HOST_WIDE_INT unsorted_offsets[4];
5270 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5271 extended if required. */
5272 if (nops < 2 || nops > 4)
5275 /* Loop over the operands and check that the memory references are
5276 suitable (ie immediate offsets from the same base register). At
5277 the same time, extract the target register, and the memory
5279 for (i = 0; i < nops; i++)
5284 /* Convert a subreg of a mem into the mem itself. */
5285 if (GET_CODE (operands[nops + i]) == SUBREG)
5286 operands[nops + i] = alter_subreg (operands + (nops + i));
5288 if (GET_CODE (operands[nops + i]) != MEM)
5291 /* Don't reorder volatile memory references; it doesn't seem worth
5292 looking for the case where the order is ok anyway. */
5293 if (MEM_VOLATILE_P (operands[nops + i]))
5296 offset = const0_rtx;
5298 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5299 || (GET_CODE (reg) == SUBREG
5300 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5301 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5302 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5304 || (GET_CODE (reg) == SUBREG
5305 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5306 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5311 base_reg = REGNO (reg);
5312 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5313 ? REGNO (operands[i])
5314 : REGNO (SUBREG_REG (operands[i])));
5319 if (base_reg != (int) REGNO (reg))
5320 /* Not addressed from the same base register. */
5323 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5324 ? REGNO (operands[i])
5325 : REGNO (SUBREG_REG (operands[i])));
5326 if (unsorted_regs[i] < unsorted_regs[order[0]])
5330 /* If it isn't an integer register, then we can't do this. */
5331 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5334 unsorted_offsets[i] = INTVAL (offset);
5337 /* Not a suitable memory address. */
5341 /* All the useful information has now been extracted from the
5342 operands into unsorted_regs and unsorted_offsets; additionally,
5343 order[0] has been set to the lowest numbered register in the
5344 list. Sort the registers into order, and check that the memory
5345 offsets are ascending and adjacent. */
5347 for (i = 1; i < nops; i++)
5351 order[i] = order[i - 1];
5352 for (j = 0; j < nops; j++)
5353 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5354 && (order[i] == order[i - 1]
5355 || unsorted_regs[j] < unsorted_regs[order[i]]))
5358 /* Have we found a suitable register? if not, one must be used more
5360 if (order[i] == order[i - 1])
5363 /* Is the memory address adjacent and ascending? */
5364 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5372 for (i = 0; i < nops; i++)
5373 regs[i] = unsorted_regs[order[i]];
5375 *load_offset = unsorted_offsets[order[0]];
5378 if (unsorted_offsets[order[0]] == 0)
5379 return 1; /* stmia */
5381 if (unsorted_offsets[order[0]] == 4)
5382 return 2; /* stmib */
5384 if (unsorted_offsets[order[nops - 1]] == 0)
5385 return 3; /* stmda */
5387 if (unsorted_offsets[order[nops - 1]] == -4)
5388 return 4; /* stmdb */
5394 emit_stm_seq (rtx *operands, int nops)
5398 HOST_WIDE_INT offset;
5402 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5405 strcpy (buf, "stm%?ia\t");
5409 strcpy (buf, "stm%?ib\t");
5413 strcpy (buf, "stm%?da\t");
5417 strcpy (buf, "stm%?db\t");
5424 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5425 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5427 for (i = 1; i < nops; i++)
5428 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5429 reg_names[regs[i]]);
5431 strcat (buf, "}\t%@ phole stm");
5433 output_asm_insn (buf, operands);
5438 /* Routines for use in generating RTL. */
5441 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5442 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5444 HOST_WIDE_INT offset = *offsetp;
5447 int sign = up ? 1 : -1;
5450 /* XScale has load-store double instructions, but they have stricter
5451 alignment requirements than load-store multiple, so we cannot
5454 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5455 the pipeline until completion.
5463 An ldr instruction takes 1-3 cycles, but does not block the
5472 Best case ldr will always win. However, the more ldr instructions
5473 we issue, the less likely we are to be able to schedule them well.
5474 Using ldr instructions also increases code size.
5476 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5477 for counts of 3 or 4 regs. */
5478 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5484 for (i = 0; i < count; i++)
5486 addr = plus_constant (from, i * 4 * sign);
5487 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5488 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5494 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5504 result = gen_rtx_PARALLEL (VOIDmode,
5505 rtvec_alloc (count + (write_back ? 1 : 0)));
5508 XVECEXP (result, 0, 0)
5509 = gen_rtx_SET (GET_MODE (from), from,
5510 plus_constant (from, count * 4 * sign));
5515 for (j = 0; i < count; i++, j++)
5517 addr = plus_constant (from, j * 4 * sign);
5518 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5519 XVECEXP (result, 0, i)
5520 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5531 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5532 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5534 HOST_WIDE_INT offset = *offsetp;
5537 int sign = up ? 1 : -1;
5540 /* See arm_gen_load_multiple for discussion of
5541 the pros/cons of ldm/stm usage for XScale. */
5542 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5548 for (i = 0; i < count; i++)
5550 addr = plus_constant (to, i * 4 * sign);
5551 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5552 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5558 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5568 result = gen_rtx_PARALLEL (VOIDmode,
5569 rtvec_alloc (count + (write_back ? 1 : 0)));
5572 XVECEXP (result, 0, 0)
5573 = gen_rtx_SET (GET_MODE (to), to,
5574 plus_constant (to, count * 4 * sign));
5579 for (j = 0; i < count; i++, j++)
5581 addr = plus_constant (to, j * 4 * sign);
5582 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5583 XVECEXP (result, 0, i)
5584 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5595 arm_gen_movmemqi (rtx *operands)
5597 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5598 HOST_WIDE_INT srcoffset, dstoffset;
5600 rtx src, dst, srcbase, dstbase;
5601 rtx part_bytes_reg = NULL;
5604 if (GET_CODE (operands[2]) != CONST_INT
5605 || GET_CODE (operands[3]) != CONST_INT
5606 || INTVAL (operands[2]) > 64
5607 || INTVAL (operands[3]) & 3)
5610 dstbase = operands[0];
5611 srcbase = operands[1];
5613 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5614 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5616 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5617 out_words_to_go = INTVAL (operands[2]) / 4;
5618 last_bytes = INTVAL (operands[2]) & 3;
5619 dstoffset = srcoffset = 0;
5621 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5622 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5624 for (i = 0; in_words_to_go >= 2; i+=4)
5626 if (in_words_to_go > 4)
5627 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5628 srcbase, &srcoffset));
5630 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5631 FALSE, srcbase, &srcoffset));
5633 if (out_words_to_go)
5635 if (out_words_to_go > 4)
5636 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5637 dstbase, &dstoffset));
5638 else if (out_words_to_go != 1)
5639 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5643 dstbase, &dstoffset));
5646 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5647 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5648 if (last_bytes != 0)
5650 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5656 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5657 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5660 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5661 if (out_words_to_go)
5665 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5666 sreg = copy_to_reg (mem);
5668 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5669 emit_move_insn (mem, sreg);
5672 if (in_words_to_go) /* Sanity check */
5678 if (in_words_to_go < 0)
5681 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5682 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5685 if (last_bytes && part_bytes_reg == NULL)
5688 if (BYTES_BIG_ENDIAN && last_bytes)
5690 rtx tmp = gen_reg_rtx (SImode);
5692 /* The bytes we want are in the top end of the word. */
5693 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5694 GEN_INT (8 * (4 - last_bytes))));
5695 part_bytes_reg = tmp;
5699 mem = adjust_automodify_address (dstbase, QImode,
5700 plus_constant (dst, last_bytes - 1),
5701 dstoffset + last_bytes - 1);
5702 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5706 tmp = gen_reg_rtx (SImode);
5707 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5708 part_bytes_reg = tmp;
5717 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
5718 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5722 rtx tmp = gen_reg_rtx (SImode);
5723 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
5724 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5725 part_bytes_reg = tmp;
5732 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
5733 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5740 /* Generate a memory reference for a half word, such that it will be loaded
5741 into the top 16 bits of the word. We can assume that the address is
5742 known to be alignable and of the form reg, or plus (reg, const). */
5745 arm_gen_rotated_half_load (rtx memref)
5747 HOST_WIDE_INT offset = 0;
5748 rtx base = XEXP (memref, 0);
5750 if (GET_CODE (base) == PLUS)
5752 offset = INTVAL (XEXP (base, 1));
5753 base = XEXP (base, 0);
5756 /* If we aren't allowed to generate unaligned addresses, then fail. */
5757 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
5760 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5762 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5765 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5768 /* Select a dominance comparison mode if possible for a test of the general
5769 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5770 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5771 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5772 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5773 In all cases OP will be either EQ or NE, but we don't need to know which
5774 here. If we are unable to support a dominance comparison we return
5775 CC mode. This will then fail to match for the RTL expressions that
5776 generate this call. */
5778 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5780 enum rtx_code cond1, cond2;
5783 /* Currently we will probably get the wrong result if the individual
5784 comparisons are not simple. This also ensures that it is safe to
5785 reverse a comparison if necessary. */
5786 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5788 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5792 /* The if_then_else variant of this tests the second condition if the
5793 first passes, but is true if the first fails. Reverse the first
5794 condition to get a true "inclusive-or" expression. */
5795 if (cond_or == DOM_CC_NX_OR_Y)
5796 cond1 = reverse_condition (cond1);
5798 /* If the comparisons are not equal, and one doesn't dominate the other,
5799 then we can't do this. */
5801 && !comparison_dominates_p (cond1, cond2)
5802 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5807 enum rtx_code temp = cond1;
5815 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5820 case LE: return CC_DLEmode;
5821 case LEU: return CC_DLEUmode;
5822 case GE: return CC_DGEmode;
5823 case GEU: return CC_DGEUmode;
5830 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5839 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5848 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5857 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5865 /* The remaining cases only occur when both comparisons are the
5890 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5892 /* All floating point compares return CCFP if it is an equality
5893 comparison, and CCFPE otherwise. */
5894 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5914 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
5923 /* A compare with a shifted operand. Because of canonicalization, the
5924 comparison will have to be swapped when we emit the assembler. */
5925 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5926 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5927 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5928 || GET_CODE (x) == ROTATERT))
5931 /* This is a special case that is used by combine to allow a
5932 comparison of a shifted byte load to be split into a zero-extend
5933 followed by a comparison of the shifted integer (only valid for
5934 equalities and unsigned inequalities). */
5935 if (GET_MODE (x) == SImode
5936 && GET_CODE (x) == ASHIFT
5937 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5938 && GET_CODE (XEXP (x, 0)) == SUBREG
5939 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5940 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5941 && (op == EQ || op == NE
5942 || op == GEU || op == GTU || op == LTU || op == LEU)
5943 && GET_CODE (y) == CONST_INT)
5946 /* A construct for a conditional compare, if the false arm contains
5947 0, then both conditions must be true, otherwise either condition
5948 must be true. Not all conditions are possible, so CCmode is
5949 returned if it can't be done. */
5950 if (GET_CODE (x) == IF_THEN_ELSE
5951 && (XEXP (x, 2) == const0_rtx
5952 || XEXP (x, 2) == const1_rtx)
5953 && COMPARISON_P (XEXP (x, 0))
5954 && COMPARISON_P (XEXP (x, 1)))
5955 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5956 INTVAL (XEXP (x, 2)));
5958 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5959 if (GET_CODE (x) == AND
5960 && COMPARISON_P (XEXP (x, 0))
5961 && COMPARISON_P (XEXP (x, 1)))
5962 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5965 if (GET_CODE (x) == IOR
5966 && COMPARISON_P (XEXP (x, 0))
5967 && COMPARISON_P (XEXP (x, 1)))
5968 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5971 /* An operation (on Thumb) where we want to test for a single bit.
5972 This is done by shifting that bit up into the top bit of a
5973 scratch register; we can then branch on the sign bit. */
5975 && GET_MODE (x) == SImode
5976 && (op == EQ || op == NE)
5977 && (GET_CODE (x) == ZERO_EXTRACT))
5980 /* An operation that sets the condition codes as a side-effect, the
5981 V flag is not set correctly, so we can only use comparisons where
5982 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5984 if (GET_MODE (x) == SImode
5986 && (op == EQ || op == NE || op == LT || op == GE)
5987 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5988 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5989 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5990 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5991 || GET_CODE (x) == LSHIFTRT
5992 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5993 || GET_CODE (x) == ROTATERT
5994 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
5997 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6000 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6001 && GET_CODE (x) == PLUS
6002 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6008 /* X and Y are two things to compare using CODE. Emit the compare insn and
6009 return the rtx for register 0 in the proper mode. FP means this is a
6010 floating point compare: I don't think that it is needed on the arm. */
6012 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6014 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6015 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6017 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6018 gen_rtx_COMPARE (mode, x, y)));
6023 /* Generate a sequence of insns that will generate the correct return
6024 address mask depending on the physical architecture that the program
6027 arm_gen_return_addr_mask (void)
6029 rtx reg = gen_reg_rtx (Pmode);
6031 emit_insn (gen_return_addr_mask (reg));
6036 arm_reload_in_hi (rtx *operands)
6038 rtx ref = operands[1];
6040 HOST_WIDE_INT offset = 0;
6042 if (GET_CODE (ref) == SUBREG)
6044 offset = SUBREG_BYTE (ref);
6045 ref = SUBREG_REG (ref);
6048 if (GET_CODE (ref) == REG)
6050 /* We have a pseudo which has been spilt onto the stack; there
6051 are two cases here: the first where there is a simple
6052 stack-slot replacement and a second where the stack-slot is
6053 out of range, or is used as a subreg. */
6054 if (reg_equiv_mem[REGNO (ref)])
6056 ref = reg_equiv_mem[REGNO (ref)];
6057 base = find_replacement (&XEXP (ref, 0));
6060 /* The slot is out of range, or was dressed up in a SUBREG. */
6061 base = reg_equiv_address[REGNO (ref)];
6064 base = find_replacement (&XEXP (ref, 0));
6066 /* Handle the case where the address is too complex to be offset by 1. */
6067 if (GET_CODE (base) == MINUS
6068 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6070 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6072 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6075 else if (GET_CODE (base) == PLUS)
6077 /* The addend must be CONST_INT, or we would have dealt with it above. */
6078 HOST_WIDE_INT hi, lo;
6080 offset += INTVAL (XEXP (base, 1));
6081 base = XEXP (base, 0);
6083 /* Rework the address into a legal sequence of insns. */
6084 /* Valid range for lo is -4095 -> 4095 */
6087 : -((-offset) & 0xfff));
6089 /* Corner case, if lo is the max offset then we would be out of range
6090 once we have added the additional 1 below, so bump the msb into the
6091 pre-loading insn(s). */
6095 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6096 ^ (HOST_WIDE_INT) 0x80000000)
6097 - (HOST_WIDE_INT) 0x80000000);
6099 if (hi + lo != offset)
6104 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6106 /* Get the base address; addsi3 knows how to handle constants
6107 that require more than one insn. */
6108 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6114 /* Operands[2] may overlap operands[0] (though it won't overlap
6115 operands[1]), that's why we asked for a DImode reg -- so we can
6116 use the bit that does not overlap. */
6117 if (REGNO (operands[2]) == REGNO (operands[0]))
6118 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6120 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6122 emit_insn (gen_zero_extendqisi2 (scratch,
6123 gen_rtx_MEM (QImode,
6124 plus_constant (base,
6126 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6127 gen_rtx_MEM (QImode,
6128 plus_constant (base,
6130 if (!BYTES_BIG_ENDIAN)
6131 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6132 gen_rtx_IOR (SImode,
6135 gen_rtx_SUBREG (SImode, operands[0], 0),
6139 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6140 gen_rtx_IOR (SImode,
6141 gen_rtx_ASHIFT (SImode, scratch,
6143 gen_rtx_SUBREG (SImode, operands[0],
6147 /* Handle storing a half-word to memory during reload by synthesizing as two
6148 byte stores. Take care not to clobber the input values until after we
6149 have moved them somewhere safe. This code assumes that if the DImode
6150 scratch in operands[2] overlaps either the input value or output address
6151 in some way, then that value must die in this insn (we absolutely need
6152 two scratch registers for some corner cases). */
6154 arm_reload_out_hi (rtx *operands)
6156 rtx ref = operands[0];
6157 rtx outval = operands[1];
6159 HOST_WIDE_INT offset = 0;
6161 if (GET_CODE (ref) == SUBREG)
6163 offset = SUBREG_BYTE (ref);
6164 ref = SUBREG_REG (ref);
6167 if (GET_CODE (ref) == REG)
6169 /* We have a pseudo which has been spilt onto the stack; there
6170 are two cases here: the first where there is a simple
6171 stack-slot replacement and a second where the stack-slot is
6172 out of range, or is used as a subreg. */
6173 if (reg_equiv_mem[REGNO (ref)])
6175 ref = reg_equiv_mem[REGNO (ref)];
6176 base = find_replacement (&XEXP (ref, 0));
6179 /* The slot is out of range, or was dressed up in a SUBREG. */
6180 base = reg_equiv_address[REGNO (ref)];
6183 base = find_replacement (&XEXP (ref, 0));
6185 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6187 /* Handle the case where the address is too complex to be offset by 1. */
6188 if (GET_CODE (base) == MINUS
6189 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6191 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6193 /* Be careful not to destroy OUTVAL. */
6194 if (reg_overlap_mentioned_p (base_plus, outval))
6196 /* Updating base_plus might destroy outval, see if we can
6197 swap the scratch and base_plus. */
6198 if (!reg_overlap_mentioned_p (scratch, outval))
6201 scratch = base_plus;
6206 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6208 /* Be conservative and copy OUTVAL into the scratch now,
6209 this should only be necessary if outval is a subreg
6210 of something larger than a word. */
6211 /* XXX Might this clobber base? I can't see how it can,
6212 since scratch is known to overlap with OUTVAL, and
6213 must be wider than a word. */
6214 emit_insn (gen_movhi (scratch_hi, outval));
6215 outval = scratch_hi;
6219 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6222 else if (GET_CODE (base) == PLUS)
6224 /* The addend must be CONST_INT, or we would have dealt with it above. */
6225 HOST_WIDE_INT hi, lo;
6227 offset += INTVAL (XEXP (base, 1));
6228 base = XEXP (base, 0);
6230 /* Rework the address into a legal sequence of insns. */
6231 /* Valid range for lo is -4095 -> 4095 */
6234 : -((-offset) & 0xfff));
6236 /* Corner case, if lo is the max offset then we would be out of range
6237 once we have added the additional 1 below, so bump the msb into the
6238 pre-loading insn(s). */
6242 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6243 ^ (HOST_WIDE_INT) 0x80000000)
6244 - (HOST_WIDE_INT) 0x80000000);
6246 if (hi + lo != offset)
6251 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6253 /* Be careful not to destroy OUTVAL. */
6254 if (reg_overlap_mentioned_p (base_plus, outval))
6256 /* Updating base_plus might destroy outval, see if we
6257 can swap the scratch and base_plus. */
6258 if (!reg_overlap_mentioned_p (scratch, outval))
6261 scratch = base_plus;
6266 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6268 /* Be conservative and copy outval into scratch now,
6269 this should only be necessary if outval is a
6270 subreg of something larger than a word. */
6271 /* XXX Might this clobber base? I can't see how it
6272 can, since scratch is known to overlap with
6274 emit_insn (gen_movhi (scratch_hi, outval));
6275 outval = scratch_hi;
6279 /* Get the base address; addsi3 knows how to handle constants
6280 that require more than one insn. */
6281 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6287 if (BYTES_BIG_ENDIAN)
6289 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6290 plus_constant (base, offset + 1)),
6291 gen_lowpart (QImode, outval)));
6292 emit_insn (gen_lshrsi3 (scratch,
6293 gen_rtx_SUBREG (SImode, outval, 0),
6295 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6296 gen_lowpart (QImode, scratch)));
6300 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6301 gen_lowpart (QImode, outval)));
6302 emit_insn (gen_lshrsi3 (scratch,
6303 gen_rtx_SUBREG (SImode, outval, 0),
6305 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6306 plus_constant (base, offset + 1)),
6307 gen_lowpart (QImode, scratch)));
6311 /* Print a symbolic form of X to the debug file, F. */
6313 arm_print_value (FILE *f, rtx x)
6315 switch (GET_CODE (x))
6318 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6322 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6330 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6332 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6333 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6341 fprintf (f, "\"%s\"", XSTR (x, 0));
6345 fprintf (f, "`%s'", XSTR (x, 0));
6349 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6353 arm_print_value (f, XEXP (x, 0));
6357 arm_print_value (f, XEXP (x, 0));
6359 arm_print_value (f, XEXP (x, 1));
6367 fprintf (f, "????");
6372 /* Routines for manipulation of the constant pool. */
6374 /* Arm instructions cannot load a large constant directly into a
6375 register; they have to come from a pc relative load. The constant
6376 must therefore be placed in the addressable range of the pc
6377 relative load. Depending on the precise pc relative load
6378 instruction the range is somewhere between 256 bytes and 4k. This
6379 means that we often have to dump a constant inside a function, and
6380 generate code to branch around it.
6382 It is important to minimize this, since the branches will slow
6383 things down and make the code larger.
6385 Normally we can hide the table after an existing unconditional
6386 branch so that there is no interruption of the flow, but in the
6387 worst case the code looks like this:
6405 We fix this by performing a scan after scheduling, which notices
6406 which instructions need to have their operands fetched from the
6407 constant table and builds the table.
6409 The algorithm starts by building a table of all the constants that
6410 need fixing up and all the natural barriers in the function (places
6411 where a constant table can be dropped without breaking the flow).
6412 For each fixup we note how far the pc-relative replacement will be
6413 able to reach and the offset of the instruction into the function.
6415 Having built the table we then group the fixes together to form
6416 tables that are as large as possible (subject to addressing
6417 constraints) and emit each table of constants after the last
6418 barrier that is within range of all the instructions in the group.
6419 If a group does not contain a barrier, then we forcibly create one
6420 by inserting a jump instruction into the flow. Once the table has
6421 been inserted, the insns are then modified to reference the
6422 relevant entry in the pool.
6424 Possible enhancements to the algorithm (not implemented) are:
6426 1) For some processors and object formats, there may be benefit in
6427 aligning the pools to the start of cache lines; this alignment
6428 would need to be taken into account when calculating addressability
6431 /* These typedefs are located at the start of this file, so that
6432 they can be used in the prototypes there. This comment is to
6433 remind readers of that fact so that the following structures
6434 can be understood more easily.
6436 typedef struct minipool_node Mnode;
6437 typedef struct minipool_fixup Mfix; */
6439 struct minipool_node
6441 /* Doubly linked chain of entries. */
6444 /* The maximum offset into the code that this entry can be placed. While
6445 pushing fixes for forward references, all entries are sorted in order
6446 of increasing max_address. */
6447 HOST_WIDE_INT max_address;
6448 /* Similarly for an entry inserted for a backwards ref. */
6449 HOST_WIDE_INT min_address;
6450 /* The number of fixes referencing this entry. This can become zero
6451 if we "unpush" an entry. In this case we ignore the entry when we
6452 come to emit the code. */
6454 /* The offset from the start of the minipool. */
6455 HOST_WIDE_INT offset;
6456 /* The value in table. */
6458 /* The mode of value. */
6459 enum machine_mode mode;
6460 /* The size of the value. With iWMMXt enabled
6461 sizes > 4 also imply an alignment of 8-bytes. */
6465 struct minipool_fixup
6469 HOST_WIDE_INT address;
6471 enum machine_mode mode;
6475 HOST_WIDE_INT forwards;
6476 HOST_WIDE_INT backwards;
6479 /* Fixes less than a word need padding out to a word boundary. */
6480 #define MINIPOOL_FIX_SIZE(mode) \
6481 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6483 static Mnode * minipool_vector_head;
6484 static Mnode * minipool_vector_tail;
6485 static rtx minipool_vector_label;
6487 /* The linked list of all minipool fixes required for this function. */
6488 Mfix * minipool_fix_head;
6489 Mfix * minipool_fix_tail;
6490 /* The fix entry for the current minipool, once it has been placed. */
6491 Mfix * minipool_barrier;
6493 /* Determines if INSN is the start of a jump table. Returns the end
6494 of the TABLE or NULL_RTX. */
6496 is_jump_table (rtx insn)
6500 if (GET_CODE (insn) == JUMP_INSN
6501 && JUMP_LABEL (insn) != NULL
6502 && ((table = next_real_insn (JUMP_LABEL (insn)))
6503 == next_real_insn (insn))
6505 && GET_CODE (table) == JUMP_INSN
6506 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6507 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6513 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6514 #define JUMP_TABLES_IN_TEXT_SECTION 0
6517 static HOST_WIDE_INT
6518 get_jump_table_size (rtx insn)
6520 /* ADDR_VECs only take room if read-only data does into the text
6522 if (JUMP_TABLES_IN_TEXT_SECTION
6523 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6528 rtx body = PATTERN (insn);
6529 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6531 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6537 /* Move a minipool fix MP from its current location to before MAX_MP.
6538 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6539 constraints may need updating. */
6541 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6542 HOST_WIDE_INT max_address)
6544 /* This should never be true and the code below assumes these are
6551 if (max_address < mp->max_address)
6552 mp->max_address = max_address;
6556 if (max_address > max_mp->max_address - mp->fix_size)
6557 mp->max_address = max_mp->max_address - mp->fix_size;
6559 mp->max_address = max_address;
6561 /* Unlink MP from its current position. Since max_mp is non-null,
6562 mp->prev must be non-null. */
6563 mp->prev->next = mp->next;
6564 if (mp->next != NULL)
6565 mp->next->prev = mp->prev;
6567 minipool_vector_tail = mp->prev;
6569 /* Re-insert it before MAX_MP. */
6571 mp->prev = max_mp->prev;
6574 if (mp->prev != NULL)
6575 mp->prev->next = mp;
6577 minipool_vector_head = mp;
6580 /* Save the new entry. */
6583 /* Scan over the preceding entries and adjust their addresses as
6585 while (mp->prev != NULL
6586 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6588 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6595 /* Add a constant to the minipool for a forward reference. Returns the
6596 node added or NULL if the constant will not fit in this pool. */
6598 add_minipool_forward_ref (Mfix *fix)
6600 /* If set, max_mp is the first pool_entry that has a lower
6601 constraint than the one we are trying to add. */
6602 Mnode * max_mp = NULL;
6603 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6606 /* If this fix's address is greater than the address of the first
6607 entry, then we can't put the fix in this pool. We subtract the
6608 size of the current fix to ensure that if the table is fully
6609 packed we still have enough room to insert this value by suffling
6610 the other fixes forwards. */
6611 if (minipool_vector_head &&
6612 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6615 /* Scan the pool to see if a constant with the same value has
6616 already been added. While we are doing this, also note the
6617 location where we must insert the constant if it doesn't already
6619 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6621 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6622 && fix->mode == mp->mode
6623 && (GET_CODE (fix->value) != CODE_LABEL
6624 || (CODE_LABEL_NUMBER (fix->value)
6625 == CODE_LABEL_NUMBER (mp->value)))
6626 && rtx_equal_p (fix->value, mp->value))
6628 /* More than one fix references this entry. */
6630 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6633 /* Note the insertion point if necessary. */
6635 && mp->max_address > max_address)
6638 /* If we are inserting an 8-bytes aligned quantity and
6639 we have not already found an insertion point, then
6640 make sure that all such 8-byte aligned quantities are
6641 placed at the start of the pool. */
6642 if (ARM_DOUBLEWORD_ALIGN
6644 && fix->fix_size == 8
6645 && mp->fix_size != 8)
6648 max_address = mp->max_address;
6652 /* The value is not currently in the minipool, so we need to create
6653 a new entry for it. If MAX_MP is NULL, the entry will be put on
6654 the end of the list since the placement is less constrained than
6655 any existing entry. Otherwise, we insert the new fix before
6656 MAX_MP and, if necessary, adjust the constraints on the other
6658 mp = xmalloc (sizeof (* mp));
6659 mp->fix_size = fix->fix_size;
6660 mp->mode = fix->mode;
6661 mp->value = fix->value;
6663 /* Not yet required for a backwards ref. */
6664 mp->min_address = -65536;
6668 mp->max_address = max_address;
6670 mp->prev = minipool_vector_tail;
6672 if (mp->prev == NULL)
6674 minipool_vector_head = mp;
6675 minipool_vector_label = gen_label_rtx ();
6678 mp->prev->next = mp;
6680 minipool_vector_tail = mp;
6684 if (max_address > max_mp->max_address - mp->fix_size)
6685 mp->max_address = max_mp->max_address - mp->fix_size;
6687 mp->max_address = max_address;
6690 mp->prev = max_mp->prev;
6692 if (mp->prev != NULL)
6693 mp->prev->next = mp;
6695 minipool_vector_head = mp;
6698 /* Save the new entry. */
6701 /* Scan over the preceding entries and adjust their addresses as
6703 while (mp->prev != NULL
6704 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6706 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6714 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6715 HOST_WIDE_INT min_address)
6717 HOST_WIDE_INT offset;
6719 /* This should never be true, and the code below assumes these are
6726 if (min_address > mp->min_address)
6727 mp->min_address = min_address;
6731 /* We will adjust this below if it is too loose. */
6732 mp->min_address = min_address;
6734 /* Unlink MP from its current position. Since min_mp is non-null,
6735 mp->next must be non-null. */
6736 mp->next->prev = mp->prev;
6737 if (mp->prev != NULL)
6738 mp->prev->next = mp->next;
6740 minipool_vector_head = mp->next;
6742 /* Reinsert it after MIN_MP. */
6744 mp->next = min_mp->next;
6746 if (mp->next != NULL)
6747 mp->next->prev = mp;
6749 minipool_vector_tail = mp;
6755 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6757 mp->offset = offset;
6758 if (mp->refcount > 0)
6759 offset += mp->fix_size;
6761 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6762 mp->next->min_address = mp->min_address + mp->fix_size;
6768 /* Add a constant to the minipool for a backward reference. Returns the
6769 node added or NULL if the constant will not fit in this pool.
6771 Note that the code for insertion for a backwards reference can be
6772 somewhat confusing because the calculated offsets for each fix do
6773 not take into account the size of the pool (which is still under
6776 add_minipool_backward_ref (Mfix *fix)
6778 /* If set, min_mp is the last pool_entry that has a lower constraint
6779 than the one we are trying to add. */
6780 Mnode *min_mp = NULL;
6781 /* This can be negative, since it is only a constraint. */
6782 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6785 /* If we can't reach the current pool from this insn, or if we can't
6786 insert this entry at the end of the pool without pushing other
6787 fixes out of range, then we don't try. This ensures that we
6788 can't fail later on. */
6789 if (min_address >= minipool_barrier->address
6790 || (minipool_vector_tail->min_address + fix->fix_size
6791 >= minipool_barrier->address))
6794 /* Scan the pool to see if a constant with the same value has
6795 already been added. While we are doing this, also note the
6796 location where we must insert the constant if it doesn't already
6798 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6800 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6801 && fix->mode == mp->mode
6802 && (GET_CODE (fix->value) != CODE_LABEL
6803 || (CODE_LABEL_NUMBER (fix->value)
6804 == CODE_LABEL_NUMBER (mp->value)))
6805 && rtx_equal_p (fix->value, mp->value)
6806 /* Check that there is enough slack to move this entry to the
6807 end of the table (this is conservative). */
6809 > (minipool_barrier->address
6810 + minipool_vector_tail->offset
6811 + minipool_vector_tail->fix_size)))
6814 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6818 mp->min_address += fix->fix_size;
6821 /* Note the insertion point if necessary. */
6822 if (mp->min_address < min_address)
6824 /* For now, we do not allow the insertion of 8-byte alignment
6825 requiring nodes anywhere but at the start of the pool. */
6826 if (ARM_DOUBLEWORD_ALIGN
6827 && fix->fix_size == 8 && mp->fix_size != 8)
6832 else if (mp->max_address
6833 < minipool_barrier->address + mp->offset + fix->fix_size)
6835 /* Inserting before this entry would push the fix beyond
6836 its maximum address (which can happen if we have
6837 re-located a forwards fix); force the new fix to come
6840 min_address = mp->min_address + fix->fix_size;
6842 /* If we are inserting an 8-bytes aligned quantity and
6843 we have not already found an insertion point, then
6844 make sure that all such 8-byte aligned quantities are
6845 placed at the start of the pool. */
6846 else if (ARM_DOUBLEWORD_ALIGN
6848 && fix->fix_size == 8
6849 && mp->fix_size < 8)
6852 min_address = mp->min_address + fix->fix_size;
6857 /* We need to create a new entry. */
6858 mp = xmalloc (sizeof (* mp));
6859 mp->fix_size = fix->fix_size;
6860 mp->mode = fix->mode;
6861 mp->value = fix->value;
6863 mp->max_address = minipool_barrier->address + 65536;
6865 mp->min_address = min_address;
6870 mp->next = minipool_vector_head;
6872 if (mp->next == NULL)
6874 minipool_vector_tail = mp;
6875 minipool_vector_label = gen_label_rtx ();
6878 mp->next->prev = mp;
6880 minipool_vector_head = mp;
6884 mp->next = min_mp->next;
6888 if (mp->next != NULL)
6889 mp->next->prev = mp;
6891 minipool_vector_tail = mp;
6894 /* Save the new entry. */
6902 /* Scan over the following entries and adjust their offsets. */
6903 while (mp->next != NULL)
6905 if (mp->next->min_address < mp->min_address + mp->fix_size)
6906 mp->next->min_address = mp->min_address + mp->fix_size;
6909 mp->next->offset = mp->offset + mp->fix_size;
6911 mp->next->offset = mp->offset;
6920 assign_minipool_offsets (Mfix *barrier)
6922 HOST_WIDE_INT offset = 0;
6925 minipool_barrier = barrier;
6927 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6929 mp->offset = offset;
6931 if (mp->refcount > 0)
6932 offset += mp->fix_size;
6936 /* Output the literal table */
6938 dump_minipool (rtx scan)
6944 if (ARM_DOUBLEWORD_ALIGN)
6945 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6946 if (mp->refcount > 0 && mp->fix_size == 8)
6954 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6955 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
6957 scan = emit_label_after (gen_label_rtx (), scan);
6958 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
6959 scan = emit_label_after (minipool_vector_label, scan);
6961 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6963 if (mp->refcount > 0)
6968 ";; Offset %u, min %ld, max %ld ",
6969 (unsigned) mp->offset, (unsigned long) mp->min_address,
6970 (unsigned long) mp->max_address);
6971 arm_print_value (dump_file, mp->value);
6972 fputc ('\n', dump_file);
6975 switch (mp->fix_size)
6977 #ifdef HAVE_consttable_1
6979 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6983 #ifdef HAVE_consttable_2
6985 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6989 #ifdef HAVE_consttable_4
6991 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6995 #ifdef HAVE_consttable_8
6997 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7011 minipool_vector_head = minipool_vector_tail = NULL;
7012 scan = emit_insn_after (gen_consttable_end (), scan);
7013 scan = emit_barrier_after (scan);
7016 /* Return the cost of forcibly inserting a barrier after INSN. */
7018 arm_barrier_cost (rtx insn)
7020 /* Basing the location of the pool on the loop depth is preferable,
7021 but at the moment, the basic block information seems to be
7022 corrupt by this stage of the compilation. */
7024 rtx next = next_nonnote_insn (insn);
7026 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7029 switch (GET_CODE (insn))
7032 /* It will always be better to place the table before the label, rather
7041 return base_cost - 10;
7044 return base_cost + 10;
7048 /* Find the best place in the insn stream in the range
7049 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7050 Create the barrier by inserting a jump and add a new fix entry for
7053 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7055 HOST_WIDE_INT count = 0;
7057 rtx from = fix->insn;
7058 rtx selected = from;
7060 HOST_WIDE_INT selected_address;
7062 HOST_WIDE_INT max_count = max_address - fix->address;
7063 rtx label = gen_label_rtx ();
7065 selected_cost = arm_barrier_cost (from);
7066 selected_address = fix->address;
7068 while (from && count < max_count)
7073 /* This code shouldn't have been called if there was a natural barrier
7075 if (GET_CODE (from) == BARRIER)
7078 /* Count the length of this insn. */
7079 count += get_attr_length (from);
7081 /* If there is a jump table, add its length. */
7082 tmp = is_jump_table (from);
7085 count += get_jump_table_size (tmp);
7087 /* Jump tables aren't in a basic block, so base the cost on
7088 the dispatch insn. If we select this location, we will
7089 still put the pool after the table. */
7090 new_cost = arm_barrier_cost (from);
7092 if (count < max_count && new_cost <= selected_cost)
7095 selected_cost = new_cost;
7096 selected_address = fix->address + count;
7099 /* Continue after the dispatch table. */
7100 from = NEXT_INSN (tmp);
7104 new_cost = arm_barrier_cost (from);
7106 if (count < max_count && new_cost <= selected_cost)
7109 selected_cost = new_cost;
7110 selected_address = fix->address + count;
7113 from = NEXT_INSN (from);
7116 /* Create a new JUMP_INSN that branches around a barrier. */
7117 from = emit_jump_insn_after (gen_jump (label), selected);
7118 JUMP_LABEL (from) = label;
7119 barrier = emit_barrier_after (from);
7120 emit_label_after (label, barrier);
7122 /* Create a minipool barrier entry for the new barrier. */
7123 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7124 new_fix->insn = barrier;
7125 new_fix->address = selected_address;
7126 new_fix->next = fix->next;
7127 fix->next = new_fix;
7132 /* Record that there is a natural barrier in the insn stream at
7135 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7137 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7140 fix->address = address;
7143 if (minipool_fix_head != NULL)
7144 minipool_fix_tail->next = fix;
7146 minipool_fix_head = fix;
7148 minipool_fix_tail = fix;
7151 /* Record INSN, which will need fixing up to load a value from the
7152 minipool. ADDRESS is the offset of the insn since the start of the
7153 function; LOC is a pointer to the part of the insn which requires
7154 fixing; VALUE is the constant that must be loaded, which is of type
7157 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7158 enum machine_mode mode, rtx value)
7160 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7162 #ifdef AOF_ASSEMBLER
7163 /* PIC symbol references need to be converted into offsets into the
7165 /* XXX This shouldn't be done here. */
7166 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7167 value = aof_pic_entry (value);
7168 #endif /* AOF_ASSEMBLER */
7171 fix->address = address;
7174 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7176 fix->forwards = get_attr_pool_range (insn);
7177 fix->backwards = get_attr_neg_pool_range (insn);
7178 fix->minipool = NULL;
7180 /* If an insn doesn't have a range defined for it, then it isn't
7181 expecting to be reworked by this code. Better to abort now than
7182 to generate duff assembly code. */
7183 if (fix->forwards == 0 && fix->backwards == 0)
7186 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7187 So there might be an empty word before the start of the pool.
7188 Hence we reduce the forward range by 4 to allow for this
7190 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7196 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7197 GET_MODE_NAME (mode),
7198 INSN_UID (insn), (unsigned long) address,
7199 -1 * (long)fix->backwards, (long)fix->forwards);
7200 arm_print_value (dump_file, fix->value);
7201 fprintf (dump_file, "\n");
7204 /* Add it to the chain of fixes. */
7207 if (minipool_fix_head != NULL)
7208 minipool_fix_tail->next = fix;
7210 minipool_fix_head = fix;
7212 minipool_fix_tail = fix;
7215 /* Scan INSN and note any of its operands that need fixing.
7216 If DO_PUSHES is false we do not actually push any of the fixups
7217 needed. The function returns TRUE is any fixups were needed/pushed.
7218 This is used by arm_memory_load_p() which needs to know about loads
7219 of constants that will be converted into minipool loads. */
7221 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7223 bool result = false;
7226 extract_insn (insn);
7228 if (!constrain_operands (1))
7229 fatal_insn_not_found (insn);
7231 if (recog_data.n_alternatives == 0)
7234 /* Fill in recog_op_alt with information about the constraints of this insn. */
7235 preprocess_constraints ();
7237 for (opno = 0; opno < recog_data.n_operands; opno++)
7239 /* Things we need to fix can only occur in inputs. */
7240 if (recog_data.operand_type[opno] != OP_IN)
7243 /* If this alternative is a memory reference, then any mention
7244 of constants in this alternative is really to fool reload
7245 into allowing us to accept one there. We need to fix them up
7246 now so that we output the right code. */
7247 if (recog_op_alt[opno][which_alternative].memory_ok)
7249 rtx op = recog_data.operand[opno];
7251 if (CONSTANT_P (op))
7254 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7255 recog_data.operand_mode[opno], op);
7258 else if (GET_CODE (op) == MEM
7259 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7260 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7264 rtx cop = avoid_constant_pool_reference (op);
7266 /* Casting the address of something to a mode narrower
7267 than a word can cause avoid_constant_pool_reference()
7268 to return the pool reference itself. That's no good to
7269 us here. Lets just hope that we can use the
7270 constant pool value directly. */
7272 cop = get_pool_constant (XEXP (op, 0));
7274 push_minipool_fix (insn, address,
7275 recog_data.operand_loc[opno],
7276 recog_data.operand_mode[opno], cop);
7287 /* Gcc puts the pool in the wrong place for ARM, since we can only
7288 load addresses a limited distance around the pc. We do some
7289 special munging to move the constant pool values to the correct
7290 point in the code. */
7295 HOST_WIDE_INT address = 0;
7298 minipool_fix_head = minipool_fix_tail = NULL;
7300 /* The first insn must always be a note, or the code below won't
7301 scan it properly. */
7302 insn = get_insns ();
7303 if (GET_CODE (insn) != NOTE)
7306 /* Scan all the insns and record the operands that will need fixing. */
7307 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7309 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7310 && (arm_cirrus_insn_p (insn)
7311 || GET_CODE (insn) == JUMP_INSN
7312 || arm_memory_load_p (insn)))
7313 cirrus_reorg (insn);
7315 if (GET_CODE (insn) == BARRIER)
7316 push_minipool_barrier (insn, address);
7317 else if (INSN_P (insn))
7321 note_invalid_constants (insn, address, true);
7322 address += get_attr_length (insn);
7324 /* If the insn is a vector jump, add the size of the table
7325 and skip the table. */
7326 if ((table = is_jump_table (insn)) != NULL)
7328 address += get_jump_table_size (table);
7334 fix = minipool_fix_head;
7336 /* Now scan the fixups and perform the required changes. */
7341 Mfix * last_added_fix;
7342 Mfix * last_barrier = NULL;
7345 /* Skip any further barriers before the next fix. */
7346 while (fix && GET_CODE (fix->insn) == BARRIER)
7349 /* No more fixes. */
7353 last_added_fix = NULL;
7355 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7357 if (GET_CODE (ftmp->insn) == BARRIER)
7359 if (ftmp->address >= minipool_vector_head->max_address)
7362 last_barrier = ftmp;
7364 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7367 last_added_fix = ftmp; /* Keep track of the last fix added. */
7370 /* If we found a barrier, drop back to that; any fixes that we
7371 could have reached but come after the barrier will now go in
7372 the next mini-pool. */
7373 if (last_barrier != NULL)
7375 /* Reduce the refcount for those fixes that won't go into this
7377 for (fdel = last_barrier->next;
7378 fdel && fdel != ftmp;
7381 fdel->minipool->refcount--;
7382 fdel->minipool = NULL;
7385 ftmp = last_barrier;
7389 /* ftmp is first fix that we can't fit into this pool and
7390 there no natural barriers that we could use. Insert a
7391 new barrier in the code somewhere between the previous
7392 fix and this one, and arrange to jump around it. */
7393 HOST_WIDE_INT max_address;
7395 /* The last item on the list of fixes must be a barrier, so
7396 we can never run off the end of the list of fixes without
7397 last_barrier being set. */
7401 max_address = minipool_vector_head->max_address;
7402 /* Check that there isn't another fix that is in range that
7403 we couldn't fit into this pool because the pool was
7404 already too large: we need to put the pool before such an
7406 if (ftmp->address < max_address)
7407 max_address = ftmp->address;
7409 last_barrier = create_fix_barrier (last_added_fix, max_address);
7412 assign_minipool_offsets (last_barrier);
7416 if (GET_CODE (ftmp->insn) != BARRIER
7417 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7424 /* Scan over the fixes we have identified for this pool, fixing them
7425 up and adding the constants to the pool itself. */
7426 for (this_fix = fix; this_fix && ftmp != this_fix;
7427 this_fix = this_fix->next)
7428 if (GET_CODE (this_fix->insn) != BARRIER)
7431 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7432 minipool_vector_label),
7433 this_fix->minipool->offset);
7434 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7437 dump_minipool (last_barrier->insn);
7441 /* From now on we must synthesize any constants that we can't handle
7442 directly. This can happen if the RTL gets split during final
7443 instruction generation. */
7444 after_arm_reorg = 1;
7446 /* Free the minipool memory. */
7447 obstack_free (&minipool_obstack, minipool_startobj);
7450 /* Routines to output assembly language. */
7452 /* If the rtx is the correct value then return the string of the number.
7453 In this way we can ensure that valid double constants are generated even
7454 when cross compiling. */
7456 fp_immediate_constant (rtx x)
7461 if (!fp_consts_inited)
7464 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7465 for (i = 0; i < 8; i++)
7466 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7467 return strings_fp[i];
7472 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7474 fp_const_from_val (REAL_VALUE_TYPE *r)
7478 if (!fp_consts_inited)
7481 for (i = 0; i < 8; i++)
7482 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7483 return strings_fp[i];
7488 /* Output the operands of a LDM/STM instruction to STREAM.
7489 MASK is the ARM register set mask of which only bits 0-15 are important.
7490 REG is the base register, either the frame pointer or the stack pointer,
7491 INSTR is the possibly suffixed load or store instruction. */
7493 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7496 int not_first = FALSE;
7498 fputc ('\t', stream);
7499 asm_fprintf (stream, instr, reg);
7500 fputs (", {", stream);
7502 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7503 if (mask & (1 << i))
7506 fprintf (stream, ", ");
7508 asm_fprintf (stream, "%r", i);
7512 fprintf (stream, "}\n");
7516 /* Output a FLDMX instruction to STREAM.
7517 BASE if the register containing the address.
7518 REG and COUNT specify the register range.
7519 Extra registers may be added to avoid hardware bugs. */
7522 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7526 /* Workaround ARM10 VFPr1 bug. */
7527 if (count == 2 && !arm_arch6)
7534 fputc ('\t', stream);
7535 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7537 for (i = reg; i < reg + count; i++)
7540 fputs (", ", stream);
7541 asm_fprintf (stream, "d%d", i);
7543 fputs ("}\n", stream);
7548 /* Output the assembly for a store multiple. */
7551 vfp_output_fstmx (rtx * operands)
7558 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7559 p = strlen (pattern);
7561 if (GET_CODE (operands[1]) != REG)
7564 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7565 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7567 p += sprintf (&pattern[p], ", d%d", base + i);
7569 strcpy (&pattern[p], "}");
7571 output_asm_insn (pattern, operands);
7576 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7577 number of bytes pushed. */
7580 vfp_emit_fstmx (int base_reg, int count)
7587 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7588 register pairs are stored by a store multiple insn. We avoid this
7589 by pushing an extra pair. */
7590 if (count == 2 && !arm_arch6)
7592 if (base_reg == LAST_VFP_REGNUM - 3)
7597 /* ??? The frame layout is implementation defined. We describe
7598 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7599 We really need some way of representing the whole block so that the
7600 unwinder can figure it out at runtime. */
7601 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7602 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7604 reg = gen_rtx_REG (DFmode, base_reg);
7608 = gen_rtx_SET (VOIDmode,
7609 gen_rtx_MEM (BLKmode,
7610 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7611 gen_rtx_UNSPEC (BLKmode,
7615 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7616 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7617 GEN_INT (-(count * 8 + 4))));
7618 RTX_FRAME_RELATED_P (tmp) = 1;
7619 XVECEXP (dwarf, 0, 0) = tmp;
7621 tmp = gen_rtx_SET (VOIDmode,
7622 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7624 RTX_FRAME_RELATED_P (tmp) = 1;
7625 XVECEXP (dwarf, 0, 1) = tmp;
7627 for (i = 1; i < count; i++)
7629 reg = gen_rtx_REG (DFmode, base_reg);
7631 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7633 tmp = gen_rtx_SET (VOIDmode,
7634 gen_rtx_MEM (DFmode,
7635 gen_rtx_PLUS (SImode,
7639 RTX_FRAME_RELATED_P (tmp) = 1;
7640 XVECEXP (dwarf, 0, i + 1) = tmp;
7643 par = emit_insn (par);
7644 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7646 RTX_FRAME_RELATED_P (par) = 1;
7648 return count * 8 + 4;
7652 /* Output a 'call' insn. */
7654 output_call (rtx *operands)
7657 abort (); /* Patterns should call blx <reg> directly. */
7659 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7660 if (REGNO (operands[0]) == LR_REGNUM)
7662 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7663 output_asm_insn ("mov%?\t%0, %|lr", operands);
7666 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7668 if (TARGET_INTERWORK || arm_arch4t)
7669 output_asm_insn ("bx%?\t%0", operands);
7671 output_asm_insn ("mov%?\t%|pc, %0", operands);
7676 /* Output a 'call' insn that is a reference in memory. */
7678 output_call_mem (rtx *operands)
7680 if (TARGET_INTERWORK && !arm_arch5)
7682 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7683 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7684 output_asm_insn ("bx%?\t%|ip", operands);
7686 else if (regno_use_in (LR_REGNUM, operands[0]))
7688 /* LR is used in the memory address. We load the address in the
7689 first instruction. It's safe to use IP as the target of the
7690 load since the call will kill it anyway. */
7691 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7693 output_asm_insn ("blx%?%|ip", operands);
7696 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7698 output_asm_insn ("bx%?\t%|ip", operands);
7700 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7705 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7706 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7713 /* Output a move from arm registers to an fpa registers.
7714 OPERANDS[0] is an fpa register.
7715 OPERANDS[1] is the first registers of an arm register pair. */
7717 output_mov_long_double_fpa_from_arm (rtx *operands)
7719 int arm_reg0 = REGNO (operands[1]);
7722 if (arm_reg0 == IP_REGNUM)
7725 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7726 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7727 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7729 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7730 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7735 /* Output a move from an fpa register to arm registers.
7736 OPERANDS[0] is the first registers of an arm register pair.
7737 OPERANDS[1] is an fpa register. */
7739 output_mov_long_double_arm_from_fpa (rtx *operands)
7741 int arm_reg0 = REGNO (operands[0]);
7744 if (arm_reg0 == IP_REGNUM)
7747 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7748 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7749 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7751 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7752 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7756 /* Output a move from arm registers to arm registers of a long double
7757 OPERANDS[0] is the destination.
7758 OPERANDS[1] is the source. */
7760 output_mov_long_double_arm_from_arm (rtx *operands)
7762 /* We have to be careful here because the two might overlap. */
7763 int dest_start = REGNO (operands[0]);
7764 int src_start = REGNO (operands[1]);
7768 if (dest_start < src_start)
7770 for (i = 0; i < 3; i++)
7772 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7773 ops[1] = gen_rtx_REG (SImode, src_start + i);
7774 output_asm_insn ("mov%?\t%0, %1", ops);
7779 for (i = 2; i >= 0; i--)
7781 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7782 ops[1] = gen_rtx_REG (SImode, src_start + i);
7783 output_asm_insn ("mov%?\t%0, %1", ops);
7791 /* Output a move from arm registers to an fpa registers.
7792 OPERANDS[0] is an fpa register.
7793 OPERANDS[1] is the first registers of an arm register pair. */
7795 output_mov_double_fpa_from_arm (rtx *operands)
7797 int arm_reg0 = REGNO (operands[1]);
7800 if (arm_reg0 == IP_REGNUM)
7803 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7804 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7805 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7806 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7810 /* Output a move from an fpa register to arm registers.
7811 OPERANDS[0] is the first registers of an arm register pair.
7812 OPERANDS[1] is an fpa register. */
7814 output_mov_double_arm_from_fpa (rtx *operands)
7816 int arm_reg0 = REGNO (operands[0]);
7819 if (arm_reg0 == IP_REGNUM)
7822 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7823 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7824 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7825 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7829 /* Output a move between double words.
7830 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7831 or MEM<-REG and all MEMs must be offsettable addresses. */
7833 output_move_double (rtx *operands)
7835 enum rtx_code code0 = GET_CODE (operands[0]);
7836 enum rtx_code code1 = GET_CODE (operands[1]);
7841 int reg0 = REGNO (operands[0]);
7843 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7847 int reg1 = REGNO (operands[1]);
7848 if (reg1 == IP_REGNUM)
7851 /* Ensure the second source is not overwritten. */
7852 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7853 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7855 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7857 else if (code1 == CONST_VECTOR)
7859 HOST_WIDE_INT hint = 0;
7861 switch (GET_MODE (operands[1]))
7864 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7865 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7869 if (BYTES_BIG_ENDIAN)
7871 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7873 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7877 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7879 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7882 otherops[1] = GEN_INT (hint);
7885 if (BYTES_BIG_ENDIAN)
7887 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7889 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7893 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7895 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7898 operands[1] = GEN_INT (hint);
7902 if (BYTES_BIG_ENDIAN)
7904 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7906 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7908 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7910 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7914 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7916 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7918 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7920 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7923 otherops[1] = GEN_INT (hint);
7926 if (BYTES_BIG_ENDIAN)
7928 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7930 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7932 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7934 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7938 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7940 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7942 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7944 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7947 operands[1] = GEN_INT (hint);
7953 output_mov_immediate (operands);
7954 output_mov_immediate (otherops);
7956 else if (code1 == CONST_DOUBLE)
7958 if (GET_MODE (operands[1]) == DFmode)
7963 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7964 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7965 otherops[1] = GEN_INT (l[1]);
7966 operands[1] = GEN_INT (l[0]);
7968 else if (GET_MODE (operands[1]) != VOIDmode)
7970 else if (WORDS_BIG_ENDIAN)
7972 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7973 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7977 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7978 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7981 output_mov_immediate (operands);
7982 output_mov_immediate (otherops);
7984 else if (code1 == CONST_INT)
7986 #if HOST_BITS_PER_WIDE_INT > 32
7987 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7988 what the upper word is. */
7989 if (WORDS_BIG_ENDIAN)
7991 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7992 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7996 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7997 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8000 /* Sign extend the intval into the high-order word. */
8001 if (WORDS_BIG_ENDIAN)
8003 otherops[1] = operands[1];
8004 operands[1] = (INTVAL (operands[1]) < 0
8005 ? constm1_rtx : const0_rtx);
8008 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8010 output_mov_immediate (otherops);
8011 output_mov_immediate (operands);
8013 else if (code1 == MEM)
8015 switch (GET_CODE (XEXP (operands[1], 0)))
8018 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8023 abort (); /* Should never happen now. */
8024 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8028 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8032 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8037 abort (); /* Should never happen now. */
8038 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8043 otherops[0] = operands[0];
8044 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8045 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8047 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8049 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8051 /* Registers overlap so split out the increment. */
8052 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8053 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8056 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8060 /* We only allow constant increments, so this is safe. */
8061 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8067 output_asm_insn ("adr%?\t%0, %1", operands);
8068 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8072 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8073 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8075 otherops[0] = operands[0];
8076 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8077 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8079 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8081 if (GET_CODE (otherops[2]) == CONST_INT)
8083 switch ((int) INTVAL (otherops[2]))
8086 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8089 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8092 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8097 && (GET_CODE (otherops[2]) == REG
8098 || (GET_CODE (otherops[2]) == CONST_INT
8099 && INTVAL (otherops[2]) > -256
8100 && INTVAL (otherops[2]) < 256)))
8102 if (reg_overlap_mentioned_p (otherops[0],
8105 /* Swap base and index registers over to
8106 avoid a conflict. */
8107 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8108 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8111 /* If both registers conflict, it will usually
8112 have been fixed by a splitter. */
8113 if (reg_overlap_mentioned_p (otherops[0],
8116 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8117 output_asm_insn ("ldr%?d\t%0, [%1]",
8123 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8128 if (GET_CODE (otherops[2]) == CONST_INT)
8130 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8131 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8133 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8136 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8139 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8141 return "ldm%?ia\t%0, %M0";
8145 otherops[1] = adjust_address (operands[1], SImode, 4);
8146 /* Take care of overlapping base/data reg. */
8147 if (reg_mentioned_p (operands[0], operands[1]))
8149 output_asm_insn ("ldr%?\t%0, %1", otherops);
8150 output_asm_insn ("ldr%?\t%0, %1", operands);
8154 output_asm_insn ("ldr%?\t%0, %1", operands);
8155 output_asm_insn ("ldr%?\t%0, %1", otherops);
8161 abort (); /* Constraints should prevent this. */
8163 else if (code0 == MEM && code1 == REG)
8165 if (REGNO (operands[1]) == IP_REGNUM)
8168 switch (GET_CODE (XEXP (operands[0], 0)))
8171 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8176 abort (); /* Should never happen now. */
8177 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8181 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8185 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8190 abort (); /* Should never happen now. */
8191 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8196 otherops[0] = operands[1];
8197 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8198 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8200 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8201 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8203 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8207 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8208 if (GET_CODE (otherops[2]) == CONST_INT)
8210 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8213 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8217 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8221 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8226 && (GET_CODE (otherops[2]) == REG
8227 || (GET_CODE (otherops[2]) == CONST_INT
8228 && INTVAL (otherops[2]) > -256
8229 && INTVAL (otherops[2]) < 256)))
8231 otherops[0] = operands[1];
8232 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8233 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8239 otherops[0] = adjust_address (operands[0], SImode, 4);
8240 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8241 output_asm_insn ("str%?\t%1, %0", operands);
8242 output_asm_insn ("str%?\t%1, %0", otherops);
8246 /* Constraints should prevent this. */
8253 /* Output an arbitrary MOV reg, #n.
8254 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8256 output_mov_immediate (rtx *operands)
8258 HOST_WIDE_INT n = INTVAL (operands[1]);
8260 /* Try to use one MOV. */
8261 if (const_ok_for_arm (n))
8262 output_asm_insn ("mov%?\t%0, %1", operands);
8264 /* Try to use one MVN. */
8265 else if (const_ok_for_arm (~n))
8267 operands[1] = GEN_INT (~n);
8268 output_asm_insn ("mvn%?\t%0, %1", operands);
8275 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8276 for (i = 0; i < 32; i++)
8280 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8281 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8283 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8289 /* Output an ADD r, s, #n where n may be too big for one instruction.
8290 If adding zero to one register, output nothing. */
8292 output_add_immediate (rtx *operands)
8294 HOST_WIDE_INT n = INTVAL (operands[2]);
8296 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8299 output_multi_immediate (operands,
8300 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8303 output_multi_immediate (operands,
8304 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8311 /* Output a multiple immediate operation.
8312 OPERANDS is the vector of operands referred to in the output patterns.
8313 INSTR1 is the output pattern to use for the first constant.
8314 INSTR2 is the output pattern to use for subsequent constants.
8315 IMMED_OP is the index of the constant slot in OPERANDS.
8316 N is the constant value. */
8318 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8319 int immed_op, HOST_WIDE_INT n)
8321 #if HOST_BITS_PER_WIDE_INT > 32
8327 /* Quick and easy output. */
8328 operands[immed_op] = const0_rtx;
8329 output_asm_insn (instr1, operands);
8334 const char * instr = instr1;
8336 /* Note that n is never zero here (which would give no output). */
8337 for (i = 0; i < 32; i += 2)
8341 operands[immed_op] = GEN_INT (n & (255 << i));
8342 output_asm_insn (instr, operands);
8352 /* Return the appropriate ARM instruction for the operation code.
8353 The returned result should not be overwritten. OP is the rtx of the
8354 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8357 arithmetic_instr (rtx op, int shift_first_arg)
8359 switch (GET_CODE (op))
8365 return shift_first_arg ? "rsb" : "sub";
8381 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8382 for the operation code. The returned result should not be overwritten.
8383 OP is the rtx code of the shift.
8384 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8387 shift_op (rtx op, HOST_WIDE_INT *amountp)
8390 enum rtx_code code = GET_CODE (op);
8392 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8394 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8395 *amountp = INTVAL (XEXP (op, 1));
8416 *amountp = 32 - *amountp;
8425 /* We never have to worry about the amount being other than a
8426 power of 2, since this case can never be reloaded from a reg. */
8428 *amountp = int_log2 (*amountp);
8439 /* This is not 100% correct, but follows from the desire to merge
8440 multiplication by a power of 2 with the recognizer for a
8441 shift. >=32 is not a valid shift for "asl", so we must try and
8442 output a shift that produces the correct arithmetical result.
8443 Using lsr #32 is identical except for the fact that the carry bit
8444 is not set correctly if we set the flags; but we never use the
8445 carry bit from such an operation, so we can ignore that. */
8446 if (code == ROTATERT)
8447 /* Rotate is just modulo 32. */
8449 else if (*amountp != (*amountp & 31))
8456 /* Shifts of 0 are no-ops. */
8464 /* Obtain the shift from the POWER of two. */
8466 static HOST_WIDE_INT
8467 int_log2 (HOST_WIDE_INT power)
8469 HOST_WIDE_INT shift = 0;
8471 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8481 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8482 /bin/as is horribly restrictive. */
8483 #define MAX_ASCII_LEN 51
8486 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8491 fputs ("\t.ascii\t\"", stream);
8493 for (i = 0; i < len; i++)
8497 if (len_so_far >= MAX_ASCII_LEN)
8499 fputs ("\"\n\t.ascii\t\"", stream);
8506 fputs ("\\t", stream);
8511 fputs ("\\f", stream);
8516 fputs ("\\b", stream);
8521 fputs ("\\r", stream);
8525 case TARGET_NEWLINE:
8526 fputs ("\\n", stream);
8528 if ((c >= ' ' && c <= '~')
8530 /* This is a good place for a line break. */
8531 len_so_far = MAX_ASCII_LEN;
8538 putc ('\\', stream);
8543 if (c >= ' ' && c <= '~')
8550 fprintf (stream, "\\%03o", c);
8557 fputs ("\"\n", stream);
8560 /* Compute the register save mask for registers 0 through 12
8561 inclusive. This code is used by arm_compute_save_reg_mask. */
8562 static unsigned long
8563 arm_compute_save_reg0_reg12_mask (void)
8565 unsigned long func_type = arm_current_func_type ();
8566 unsigned int save_reg_mask = 0;
8569 if (IS_INTERRUPT (func_type))
8571 unsigned int max_reg;
8572 /* Interrupt functions must not corrupt any registers,
8573 even call clobbered ones. If this is a leaf function
8574 we can just examine the registers used by the RTL, but
8575 otherwise we have to assume that whatever function is
8576 called might clobber anything, and so we have to save
8577 all the call-clobbered registers as well. */
8578 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8579 /* FIQ handlers have registers r8 - r12 banked, so
8580 we only need to check r0 - r7, Normal ISRs only
8581 bank r14 and r15, so we must check up to r12.
8582 r13 is the stack pointer which is always preserved,
8583 so we do not need to consider it here. */
8588 for (reg = 0; reg <= max_reg; reg++)
8589 if (regs_ever_live[reg]
8590 || (! current_function_is_leaf && call_used_regs [reg]))
8591 save_reg_mask |= (1 << reg);
8595 /* In the normal case we only need to save those registers
8596 which are call saved and which are used by this function. */
8597 for (reg = 0; reg <= 10; reg++)
8598 if (regs_ever_live[reg] && ! call_used_regs [reg])
8599 save_reg_mask |= (1 << reg);
8601 /* Handle the frame pointer as a special case. */
8602 if (! TARGET_APCS_FRAME
8603 && ! frame_pointer_needed
8604 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8605 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8606 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8608 /* If we aren't loading the PIC register,
8609 don't stack it even though it may be live. */
8611 && ! TARGET_SINGLE_PIC_BASE
8612 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8613 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8616 /* Save registers so the exception handler can modify them. */
8617 if (current_function_calls_eh_return)
8623 reg = EH_RETURN_DATA_REGNO (i);
8624 if (reg == INVALID_REGNUM)
8626 save_reg_mask |= 1 << reg;
8630 return save_reg_mask;
8633 /* Compute a bit mask of which registers need to be
8634 saved on the stack for the current function. */
8636 static unsigned long
8637 arm_compute_save_reg_mask (void)
8639 unsigned int save_reg_mask = 0;
8640 unsigned long func_type = arm_current_func_type ();
8642 if (IS_NAKED (func_type))
8643 /* This should never really happen. */
8646 /* If we are creating a stack frame, then we must save the frame pointer,
8647 IP (which will hold the old stack pointer), LR and the PC. */
8648 if (frame_pointer_needed)
8650 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8655 /* Volatile functions do not return, so there
8656 is no need to save any other registers. */
8657 if (IS_VOLATILE (func_type))
8658 return save_reg_mask;
8660 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8662 /* Decide if we need to save the link register.
8663 Interrupt routines have their own banked link register,
8664 so they never need to save it.
8665 Otherwise if we do not use the link register we do not need to save
8666 it. If we are pushing other registers onto the stack however, we
8667 can save an instruction in the epilogue by pushing the link register
8668 now and then popping it back into the PC. This incurs extra memory
8669 accesses though, so we only do it when optimizing for size, and only
8670 if we know that we will not need a fancy return sequence. */
8671 if (regs_ever_live [LR_REGNUM]
8674 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8675 && !current_function_calls_eh_return))
8676 save_reg_mask |= 1 << LR_REGNUM;
8678 if (cfun->machine->lr_save_eliminated)
8679 save_reg_mask &= ~ (1 << LR_REGNUM);
8681 if (TARGET_REALLY_IWMMXT
8682 && ((bit_count (save_reg_mask)
8683 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8687 /* The total number of registers that are going to be pushed
8688 onto the stack is odd. We need to ensure that the stack
8689 is 64-bit aligned before we start to save iWMMXt registers,
8690 and also before we start to create locals. (A local variable
8691 might be a double or long long which we will load/store using
8692 an iWMMXt instruction). Therefore we need to push another
8693 ARM register, so that the stack will be 64-bit aligned. We
8694 try to avoid using the arg registers (r0 -r3) as they might be
8695 used to pass values in a tail call. */
8696 for (reg = 4; reg <= 12; reg++)
8697 if ((save_reg_mask & (1 << reg)) == 0)
8701 save_reg_mask |= (1 << reg);
8704 cfun->machine->sibcall_blocked = 1;
8705 save_reg_mask |= (1 << 3);
8709 return save_reg_mask;
8713 /* Compute a bit mask of which registers need to be
8714 saved on the stack for the current function. */
8715 static unsigned long
8716 thumb_compute_save_reg_mask (void)
8722 for (reg = 0; reg < 12; reg ++)
8724 if (regs_ever_live[reg] && !call_used_regs[reg])
8728 if (flag_pic && !TARGET_SINGLE_PIC_BASE)
8729 mask |= PIC_OFFSET_TABLE_REGNUM;
8730 if (TARGET_SINGLE_PIC_BASE)
8731 mask &= ~(1 << arm_pic_register);
8733 /* lr will also be pushed if any lo regs are pushed. */
8734 if (mask & 0xff || thumb_force_lr_save ())
8735 mask |= (1 << LR_REGNUM);
8737 /* Make sure we have a low work register if we need one. */
8738 if (((mask & 0xff) == 0 && regs_ever_live[LAST_ARG_REGNUM])
8739 && ((mask & 0x0f00) || TARGET_BACKTRACE))
8740 mask |= 1 << LAST_LO_REGNUM;
8746 /* Return the number of bytes required to save VFP registers. */
8748 arm_get_vfp_saved_size (void)
8755 /* Space for saved VFP registers. */
8756 if (TARGET_HARD_FLOAT && TARGET_VFP)
8759 for (regno = FIRST_VFP_REGNUM;
8760 regno < LAST_VFP_REGNUM;
8763 if ((!regs_ever_live[regno] || call_used_regs[regno])
8764 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8768 /* Workaround ARM10 VFPr1 bug. */
8769 if (count == 2 && !arm_arch6)
8771 saved += count * 8 + 4;
8780 if (count == 2 && !arm_arch6)
8782 saved += count * 8 + 4;
8789 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8790 everything bar the final return instruction. */
8792 output_return_instruction (rtx operand, int really_return, int reverse)
8794 char conditional[10];
8797 unsigned long live_regs_mask;
8798 unsigned long func_type;
8799 arm_stack_offsets *offsets;
8801 func_type = arm_current_func_type ();
8803 if (IS_NAKED (func_type))
8806 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8808 /* If this function was declared non-returning, and we have
8809 found a tail call, then we have to trust that the called
8810 function won't return. */
8815 /* Otherwise, trap an attempted return by aborting. */
8817 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8819 assemble_external_libcall (ops[1]);
8820 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8826 if (current_function_calls_alloca && !really_return)
8829 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8831 return_used_this_function = 1;
8833 live_regs_mask = arm_compute_save_reg_mask ();
8837 const char * return_reg;
8839 /* If we do not have any special requirements for function exit
8840 (eg interworking, or ISR) then we can load the return address
8841 directly into the PC. Otherwise we must load it into LR. */
8843 && ! TARGET_INTERWORK)
8844 return_reg = reg_names[PC_REGNUM];
8846 return_reg = reg_names[LR_REGNUM];
8848 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8850 /* There are three possible reasons for the IP register
8851 being saved. 1) a stack frame was created, in which case
8852 IP contains the old stack pointer, or 2) an ISR routine
8853 corrupted it, or 3) it was saved to align the stack on
8854 iWMMXt. In case 1, restore IP into SP, otherwise just
8856 if (frame_pointer_needed)
8858 live_regs_mask &= ~ (1 << IP_REGNUM);
8859 live_regs_mask |= (1 << SP_REGNUM);
8863 if (! IS_INTERRUPT (func_type)
8864 && ! TARGET_REALLY_IWMMXT)
8869 /* On some ARM architectures it is faster to use LDR rather than
8870 LDM to load a single register. On other architectures, the
8871 cost is the same. In 26 bit mode, or for exception handlers,
8872 we have to use LDM to load the PC so that the CPSR is also
8874 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8876 if (live_regs_mask == (unsigned int)(1 << reg))
8879 if (reg <= LAST_ARM_REGNUM
8880 && (reg != LR_REGNUM
8882 || ! IS_INTERRUPT (func_type)))
8884 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8885 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8892 /* Generate the load multiple instruction to restore the
8893 registers. Note we can get here, even if
8894 frame_pointer_needed is true, but only if sp already
8895 points to the base of the saved core registers. */
8896 if (live_regs_mask & (1 << SP_REGNUM))
8898 unsigned HOST_WIDE_INT stack_adjust;
8900 offsets = arm_get_frame_offsets ();
8901 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
8902 if (stack_adjust != 0 && stack_adjust != 4)
8905 if (stack_adjust && arm_arch5)
8906 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
8909 /* If we can't use ldmib (SA110 bug), then try to pop r3
8912 live_regs_mask |= 1 << 3;
8913 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8917 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8919 p = instr + strlen (instr);
8921 for (reg = 0; reg <= SP_REGNUM; reg++)
8922 if (live_regs_mask & (1 << reg))
8924 int l = strlen (reg_names[reg]);
8930 memcpy (p, ", ", 2);
8934 memcpy (p, "%|", 2);
8935 memcpy (p + 2, reg_names[reg], l);
8939 if (live_regs_mask & (1 << LR_REGNUM))
8941 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8942 /* If returning from an interrupt, restore the CPSR. */
8943 if (IS_INTERRUPT (func_type))
8950 output_asm_insn (instr, & operand);
8952 /* See if we need to generate an extra instruction to
8953 perform the actual function return. */
8955 && func_type != ARM_FT_INTERWORKED
8956 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8958 /* The return has already been handled
8959 by loading the LR into the PC. */
8966 switch ((int) ARM_FUNC_TYPE (func_type))
8970 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8973 case ARM_FT_INTERWORKED:
8974 sprintf (instr, "bx%s\t%%|lr", conditional);
8977 case ARM_FT_EXCEPTION:
8978 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8982 /* Use bx if it's available. */
8983 if (arm_arch5 || arm_arch4t)
8984 sprintf (instr, "bx%s\t%%|lr", conditional);
8986 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
8990 output_asm_insn (instr, & operand);
8996 /* Write the function name into the code section, directly preceding
8997 the function prologue.
8999 Code will be output similar to this:
9001 .ascii "arm_poke_function_name", 0
9004 .word 0xff000000 + (t1 - t0)
9005 arm_poke_function_name
9007 stmfd sp!, {fp, ip, lr, pc}
9010 When performing a stack backtrace, code can inspect the value
9011 of 'pc' stored at 'fp' + 0. If the trace function then looks
9012 at location pc - 12 and the top 8 bits are set, then we know
9013 that there is a function name embedded immediately preceding this
9014 location and has length ((pc[-3]) & 0xff000000).
9016 We assume that pc is declared as a pointer to an unsigned long.
9018 It is of no benefit to output the function name if we are assembling
9019 a leaf function. These function types will not contain a stack
9020 backtrace structure, therefore it is not possible to determine the
9023 arm_poke_function_name (FILE *stream, const char *name)
9025 unsigned long alignlength;
9026 unsigned long length;
9029 length = strlen (name) + 1;
9030 alignlength = ROUND_UP_WORD (length);
9032 ASM_OUTPUT_ASCII (stream, name, length);
9033 ASM_OUTPUT_ALIGN (stream, 2);
9034 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9035 assemble_aligned_integer (UNITS_PER_WORD, x);
9038 /* Place some comments into the assembler stream
9039 describing the current function. */
9041 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9043 unsigned long func_type;
9047 thumb_output_function_prologue (f, frame_size);
9052 if (arm_ccfsm_state || arm_target_insn)
9055 func_type = arm_current_func_type ();
9057 switch ((int) ARM_FUNC_TYPE (func_type))
9062 case ARM_FT_INTERWORKED:
9063 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9066 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9069 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9071 case ARM_FT_EXCEPTION:
9072 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9076 if (IS_NAKED (func_type))
9077 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9079 if (IS_VOLATILE (func_type))
9080 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9082 if (IS_NESTED (func_type))
9083 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9085 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9086 current_function_args_size,
9087 current_function_pretend_args_size, frame_size);
9089 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9090 frame_pointer_needed,
9091 cfun->machine->uses_anonymous_args);
9093 if (cfun->machine->lr_save_eliminated)
9094 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9096 if (current_function_calls_eh_return)
9097 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9099 #ifdef AOF_ASSEMBLER
9101 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9104 return_used_this_function = 0;
9108 arm_output_epilogue (rtx sibling)
9111 unsigned long saved_regs_mask;
9112 unsigned long func_type;
9113 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9114 frame that is $fp + 4 for a non-variadic function. */
9115 int floats_offset = 0;
9117 FILE * f = asm_out_file;
9118 unsigned int lrm_count = 0;
9119 int really_return = (sibling == NULL);
9121 arm_stack_offsets *offsets;
9123 /* If we have already generated the return instruction
9124 then it is futile to generate anything else. */
9125 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9128 func_type = arm_current_func_type ();
9130 if (IS_NAKED (func_type))
9131 /* Naked functions don't have epilogues. */
9134 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9138 /* A volatile function should never return. Call abort. */
9139 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9140 assemble_external_libcall (op);
9141 output_asm_insn ("bl\t%a0", &op);
9146 if (current_function_calls_eh_return
9148 /* If we are throwing an exception, then we really must
9149 be doing a return, so we can't tail-call. */
9152 offsets = arm_get_frame_offsets ();
9153 saved_regs_mask = arm_compute_save_reg_mask ();
9156 lrm_count = bit_count (saved_regs_mask);
9158 floats_offset = offsets->saved_args;
9159 /* Compute how far away the floats will be. */
9160 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9161 if (saved_regs_mask & (1 << reg))
9164 if (frame_pointer_needed)
9166 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9167 int vfp_offset = offsets->frame;
9169 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9171 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9172 if (regs_ever_live[reg] && !call_used_regs[reg])
9174 floats_offset += 12;
9175 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9176 reg, FP_REGNUM, floats_offset - vfp_offset);
9181 start_reg = LAST_FPA_REGNUM;
9183 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9185 if (regs_ever_live[reg] && !call_used_regs[reg])
9187 floats_offset += 12;
9189 /* We can't unstack more than four registers at once. */
9190 if (start_reg - reg == 3)
9192 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9193 reg, FP_REGNUM, floats_offset - vfp_offset);
9194 start_reg = reg - 1;
9199 if (reg != start_reg)
9200 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9201 reg + 1, start_reg - reg,
9202 FP_REGNUM, floats_offset - vfp_offset);
9203 start_reg = reg - 1;
9207 /* Just in case the last register checked also needs unstacking. */
9208 if (reg != start_reg)
9209 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9210 reg + 1, start_reg - reg,
9211 FP_REGNUM, floats_offset - vfp_offset);
9214 if (TARGET_HARD_FLOAT && TARGET_VFP)
9218 /* The fldmx insn does not have base+offset addressing modes,
9219 so we use IP to hold the address. */
9220 saved_size = arm_get_vfp_saved_size ();
9224 floats_offset += saved_size;
9225 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9226 FP_REGNUM, floats_offset - vfp_offset);
9228 start_reg = FIRST_VFP_REGNUM;
9229 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9231 if ((!regs_ever_live[reg] || call_used_regs[reg])
9232 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9234 if (start_reg != reg)
9235 arm_output_fldmx (f, IP_REGNUM,
9236 (start_reg - FIRST_VFP_REGNUM) / 2,
9237 (reg - start_reg) / 2);
9238 start_reg = reg + 2;
9241 if (start_reg != reg)
9242 arm_output_fldmx (f, IP_REGNUM,
9243 (start_reg - FIRST_VFP_REGNUM) / 2,
9244 (reg - start_reg) / 2);
9249 /* The frame pointer is guaranteed to be non-double-word aligned.
9250 This is because it is set to (old_stack_pointer - 4) and the
9251 old_stack_pointer was double word aligned. Thus the offset to
9252 the iWMMXt registers to be loaded must also be non-double-word
9253 sized, so that the resultant address *is* double-word aligned.
9254 We can ignore floats_offset since that was already included in
9255 the live_regs_mask. */
9256 lrm_count += (lrm_count % 2 ? 2 : 1);
9258 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9259 if (regs_ever_live[reg] && !call_used_regs[reg])
9261 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9262 reg, FP_REGNUM, lrm_count * 4);
9267 /* saved_regs_mask should contain the IP, which at the time of stack
9268 frame generation actually contains the old stack pointer. So a
9269 quick way to unwind the stack is just pop the IP register directly
9270 into the stack pointer. */
9271 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9273 saved_regs_mask &= ~ (1 << IP_REGNUM);
9274 saved_regs_mask |= (1 << SP_REGNUM);
9276 /* There are two registers left in saved_regs_mask - LR and PC. We
9277 only need to restore the LR register (the return address), but to
9278 save time we can load it directly into the PC, unless we need a
9279 special function exit sequence, or we are not really returning. */
9281 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9282 && !current_function_calls_eh_return)
9283 /* Delete the LR from the register mask, so that the LR on
9284 the stack is loaded into the PC in the register mask. */
9285 saved_regs_mask &= ~ (1 << LR_REGNUM);
9287 saved_regs_mask &= ~ (1 << PC_REGNUM);
9289 /* We must use SP as the base register, because SP is one of the
9290 registers being restored. If an interrupt or page fault
9291 happens in the ldm instruction, the SP might or might not
9292 have been restored. That would be bad, as then SP will no
9293 longer indicate the safe area of stack, and we can get stack
9294 corruption. Using SP as the base register means that it will
9295 be reset correctly to the original value, should an interrupt
9296 occur. If the stack pointer already points at the right
9297 place, then omit the subtraction. */
9298 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9299 || current_function_calls_alloca)
9300 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9301 4 * bit_count (saved_regs_mask));
9302 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9304 if (IS_INTERRUPT (func_type))
9305 /* Interrupt handlers will have pushed the
9306 IP onto the stack, so restore it now. */
9307 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9311 /* Restore stack pointer if necessary. */
9312 if (offsets->outgoing_args != offsets->saved_regs)
9314 operands[0] = operands[1] = stack_pointer_rtx;
9315 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9316 output_add_immediate (operands);
9319 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9321 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9322 if (regs_ever_live[reg] && !call_used_regs[reg])
9323 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9328 start_reg = FIRST_FPA_REGNUM;
9330 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9332 if (regs_ever_live[reg] && !call_used_regs[reg])
9334 if (reg - start_reg == 3)
9336 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9337 start_reg, SP_REGNUM);
9338 start_reg = reg + 1;
9343 if (reg != start_reg)
9344 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9345 start_reg, reg - start_reg,
9348 start_reg = reg + 1;
9352 /* Just in case the last register checked also needs unstacking. */
9353 if (reg != start_reg)
9354 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9355 start_reg, reg - start_reg, SP_REGNUM);
9358 if (TARGET_HARD_FLOAT && TARGET_VFP)
9360 start_reg = FIRST_VFP_REGNUM;
9361 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9363 if ((!regs_ever_live[reg] || call_used_regs[reg])
9364 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9366 if (start_reg != reg)
9367 arm_output_fldmx (f, SP_REGNUM,
9368 (start_reg - FIRST_VFP_REGNUM) / 2,
9369 (reg - start_reg) / 2);
9370 start_reg = reg + 2;
9373 if (start_reg != reg)
9374 arm_output_fldmx (f, SP_REGNUM,
9375 (start_reg - FIRST_VFP_REGNUM) / 2,
9376 (reg - start_reg) / 2);
9379 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9380 if (regs_ever_live[reg] && !call_used_regs[reg])
9381 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9383 /* If we can, restore the LR into the PC. */
9384 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9386 && current_function_pretend_args_size == 0
9387 && saved_regs_mask & (1 << LR_REGNUM)
9388 && !current_function_calls_eh_return)
9390 saved_regs_mask &= ~ (1 << LR_REGNUM);
9391 saved_regs_mask |= (1 << PC_REGNUM);
9394 /* Load the registers off the stack. If we only have one register
9395 to load use the LDR instruction - it is faster. */
9396 if (saved_regs_mask == (1 << LR_REGNUM))
9398 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9400 else if (saved_regs_mask)
9402 if (saved_regs_mask & (1 << SP_REGNUM))
9403 /* Note - write back to the stack register is not enabled
9404 (ie "ldmfd sp!..."). We know that the stack pointer is
9405 in the list of registers and if we add writeback the
9406 instruction becomes UNPREDICTABLE. */
9407 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9409 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9412 if (current_function_pretend_args_size)
9414 /* Unwind the pre-pushed regs. */
9415 operands[0] = operands[1] = stack_pointer_rtx;
9416 operands[2] = GEN_INT (current_function_pretend_args_size);
9417 output_add_immediate (operands);
9421 /* We may have already restored PC directly from the stack. */
9422 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9425 /* Stack adjustment for exception handler. */
9426 if (current_function_calls_eh_return)
9427 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9428 ARM_EH_STACKADJ_REGNUM);
9430 /* Generate the return instruction. */
9431 switch ((int) ARM_FUNC_TYPE (func_type))
9435 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9438 case ARM_FT_EXCEPTION:
9439 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9442 case ARM_FT_INTERWORKED:
9443 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9447 if (arm_arch5 || arm_arch4t)
9448 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9450 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9458 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9459 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9461 arm_stack_offsets *offsets;
9465 /* ??? Probably not safe to set this here, since it assumes that a
9466 function will be emitted as assembly immediately after we generate
9467 RTL for it. This does not happen for inline functions. */
9468 return_used_this_function = 0;
9472 /* We need to take into account any stack-frame rounding. */
9473 offsets = arm_get_frame_offsets ();
9475 if (use_return_insn (FALSE, NULL)
9476 && return_used_this_function
9477 && offsets->saved_regs != offsets->outgoing_args
9478 && !frame_pointer_needed)
9481 /* Reset the ARM-specific per-function variables. */
9482 after_arm_reorg = 0;
9486 /* Generate and emit an insn that we will recognize as a push_multi.
9487 Unfortunately, since this insn does not reflect very well the actual
9488 semantics of the operation, we need to annotate the insn for the benefit
9489 of DWARF2 frame unwind information. */
9491 emit_multi_reg_push (int mask)
9498 int dwarf_par_index;
9501 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9502 if (mask & (1 << i))
9505 if (num_regs == 0 || num_regs > 16)
9508 /* We don't record the PC in the dwarf frame information. */
9509 num_dwarf_regs = num_regs;
9510 if (mask & (1 << PC_REGNUM))
9513 /* For the body of the insn we are going to generate an UNSPEC in
9514 parallel with several USEs. This allows the insn to be recognized
9515 by the push_multi pattern in the arm.md file. The insn looks
9516 something like this:
9519 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9520 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9521 (use (reg:SI 11 fp))
9522 (use (reg:SI 12 ip))
9523 (use (reg:SI 14 lr))
9524 (use (reg:SI 15 pc))
9527 For the frame note however, we try to be more explicit and actually
9528 show each register being stored into the stack frame, plus a (single)
9529 decrement of the stack pointer. We do it this way in order to be
9530 friendly to the stack unwinding code, which only wants to see a single
9531 stack decrement per instruction. The RTL we generate for the note looks
9532 something like this:
9535 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9536 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9537 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9538 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9539 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9542 This sequence is used both by the code to support stack unwinding for
9543 exceptions handlers and the code to generate dwarf2 frame debugging. */
9545 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9546 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9547 dwarf_par_index = 1;
9549 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9551 if (mask & (1 << i))
9553 reg = gen_rtx_REG (SImode, i);
9556 = gen_rtx_SET (VOIDmode,
9557 gen_rtx_MEM (BLKmode,
9558 gen_rtx_PRE_DEC (BLKmode,
9559 stack_pointer_rtx)),
9560 gen_rtx_UNSPEC (BLKmode,
9566 tmp = gen_rtx_SET (VOIDmode,
9567 gen_rtx_MEM (SImode, stack_pointer_rtx),
9569 RTX_FRAME_RELATED_P (tmp) = 1;
9570 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9578 for (j = 1, i++; j < num_regs; i++)
9580 if (mask & (1 << i))
9582 reg = gen_rtx_REG (SImode, i);
9584 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9588 tmp = gen_rtx_SET (VOIDmode,
9589 gen_rtx_MEM (SImode,
9590 plus_constant (stack_pointer_rtx,
9593 RTX_FRAME_RELATED_P (tmp) = 1;
9594 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9601 par = emit_insn (par);
9603 tmp = gen_rtx_SET (SImode,
9605 gen_rtx_PLUS (SImode,
9607 GEN_INT (-4 * num_regs)));
9608 RTX_FRAME_RELATED_P (tmp) = 1;
9609 XVECEXP (dwarf, 0, 0) = tmp;
9611 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9617 emit_sfm (int base_reg, int count)
9624 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9625 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9627 reg = gen_rtx_REG (XFmode, base_reg++);
9630 = gen_rtx_SET (VOIDmode,
9631 gen_rtx_MEM (BLKmode,
9632 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9633 gen_rtx_UNSPEC (BLKmode,
9636 tmp = gen_rtx_SET (VOIDmode,
9637 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
9638 RTX_FRAME_RELATED_P (tmp) = 1;
9639 XVECEXP (dwarf, 0, 1) = tmp;
9641 for (i = 1; i < count; i++)
9643 reg = gen_rtx_REG (XFmode, base_reg++);
9644 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9646 tmp = gen_rtx_SET (VOIDmode,
9647 gen_rtx_MEM (XFmode,
9648 plus_constant (stack_pointer_rtx,
9651 RTX_FRAME_RELATED_P (tmp) = 1;
9652 XVECEXP (dwarf, 0, i + 1) = tmp;
9655 tmp = gen_rtx_SET (VOIDmode,
9657 gen_rtx_PLUS (SImode,
9659 GEN_INT (-12 * count)));
9660 RTX_FRAME_RELATED_P (tmp) = 1;
9661 XVECEXP (dwarf, 0, 0) = tmp;
9663 par = emit_insn (par);
9664 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9670 /* Return true if the current function needs to save/restore LR. */
9673 thumb_force_lr_save (void)
9675 return !cfun->machine->lr_save_eliminated
9676 && (!leaf_function_p ()
9677 || thumb_far_jump_used_p ()
9678 || regs_ever_live [LR_REGNUM]);
9682 /* Compute the distance from register FROM to register TO.
9683 These can be the arg pointer (26), the soft frame pointer (25),
9684 the stack pointer (13) or the hard frame pointer (11).
9685 In thumb mode r7 is used as the soft frame pointer, if needed.
9686 Typical stack layout looks like this:
9688 old stack pointer -> | |
9691 | | saved arguments for
9692 | | vararg functions
9695 hard FP & arg pointer -> | | \
9703 soft frame pointer -> | | /
9713 current stack pointer -> | | /
9716 For a given function some or all of these stack components
9717 may not be needed, giving rise to the possibility of
9718 eliminating some of the registers.
9720 The values returned by this function must reflect the behavior
9721 of arm_expand_prologue() and arm_compute_save_reg_mask().
9723 The sign of the number returned reflects the direction of stack
9724 growth, so the values are positive for all eliminations except
9725 from the soft frame pointer to the hard frame pointer.
9727 SFP may point just inside the local variables block to ensure correct
9731 /* Calculate stack offsets. These are used to calculate register elimination
9732 offsets and in prologue/epilogue code. */
9734 static arm_stack_offsets *
9735 arm_get_frame_offsets (void)
9737 struct arm_stack_offsets *offsets;
9738 unsigned long func_type;
9741 HOST_WIDE_INT frame_size;
9743 offsets = &cfun->machine->stack_offsets;
9745 /* We need to know if we are a leaf function. Unfortunately, it
9746 is possible to be called after start_sequence has been called,
9747 which causes get_insns to return the insns for the sequence,
9748 not the function, which will cause leaf_function_p to return
9749 the incorrect result.
9751 to know about leaf functions once reload has completed, and the
9752 frame size cannot be changed after that time, so we can safely
9753 use the cached value. */
9755 if (reload_completed)
9758 /* Initially this is the size of the local variables. It will translated
9759 into an offset once we have determined the size of preceding data. */
9760 frame_size = ROUND_UP_WORD (get_frame_size ());
9762 leaf = leaf_function_p ();
9764 /* Space for variadic functions. */
9765 offsets->saved_args = current_function_pretend_args_size;
9767 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
9773 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
9775 /* We know that SP will be doubleword aligned on entry, and we must
9776 preserve that condition at any subroutine call. We also require the
9777 soft frame pointer to be doubleword aligned. */
9779 if (TARGET_REALLY_IWMMXT)
9781 /* Check for the call-saved iWMMXt registers. */
9782 for (regno = FIRST_IWMMXT_REGNUM;
9783 regno <= LAST_IWMMXT_REGNUM;
9785 if (regs_ever_live [regno] && ! call_used_regs [regno])
9789 func_type = arm_current_func_type ();
9790 if (! IS_VOLATILE (func_type))
9792 /* Space for saved FPA registers. */
9793 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
9794 if (regs_ever_live[regno] && ! call_used_regs[regno])
9797 /* Space for saved VFP registers. */
9798 if (TARGET_HARD_FLOAT && TARGET_VFP)
9799 saved += arm_get_vfp_saved_size ();
9802 else /* TARGET_THUMB */
9804 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
9805 if (TARGET_BACKTRACE)
9809 /* Saved registers include the stack frame. */
9810 offsets->saved_regs = offsets->saved_args + saved;
9811 offsets->soft_frame = offsets->saved_regs;
9812 /* A leaf function does not need any stack alignment if it has nothing
9814 if (leaf && frame_size == 0)
9816 offsets->outgoing_args = offsets->soft_frame;
9820 /* Ensure SFP has the correct alignment. */
9821 if (ARM_DOUBLEWORD_ALIGN
9822 && (offsets->soft_frame & 7))
9823 offsets->soft_frame += 4;
9825 offsets->outgoing_args = offsets->soft_frame + frame_size
9826 + current_function_outgoing_args_size;
9828 if (ARM_DOUBLEWORD_ALIGN)
9830 /* Ensure SP remains doubleword aligned. */
9831 if (offsets->outgoing_args & 7)
9832 offsets->outgoing_args += 4;
9833 if (offsets->outgoing_args & 7)
9841 /* Calculate the relative offsets for the different stack pointers. Positive
9842 offsets are in the direction of stack growth. */
9845 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
9847 arm_stack_offsets *offsets;
9849 offsets = arm_get_frame_offsets ();
9851 /* OK, now we have enough information to compute the distances.
9852 There must be an entry in these switch tables for each pair
9853 of registers in ELIMINABLE_REGS, even if some of the entries
9854 seem to be redundant or useless. */
9857 case ARG_POINTER_REGNUM:
9860 case THUMB_HARD_FRAME_POINTER_REGNUM:
9863 case FRAME_POINTER_REGNUM:
9864 /* This is the reverse of the soft frame pointer
9865 to hard frame pointer elimination below. */
9866 return offsets->soft_frame - offsets->saved_args;
9868 case ARM_HARD_FRAME_POINTER_REGNUM:
9869 /* If there is no stack frame then the hard
9870 frame pointer and the arg pointer coincide. */
9871 if (offsets->frame == offsets->saved_regs)
9873 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9874 return (frame_pointer_needed
9875 && cfun->static_chain_decl != NULL
9876 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9878 case STACK_POINTER_REGNUM:
9879 /* If nothing has been pushed on the stack at all
9880 then this will return -4. This *is* correct! */
9881 return offsets->outgoing_args - (offsets->saved_args + 4);
9888 case FRAME_POINTER_REGNUM:
9891 case THUMB_HARD_FRAME_POINTER_REGNUM:
9894 case ARM_HARD_FRAME_POINTER_REGNUM:
9895 /* The hard frame pointer points to the top entry in the
9896 stack frame. The soft frame pointer to the bottom entry
9897 in the stack frame. If there is no stack frame at all,
9898 then they are identical. */
9900 return offsets->frame - offsets->soft_frame;
9902 case STACK_POINTER_REGNUM:
9903 return offsets->outgoing_args - offsets->soft_frame;
9911 /* You cannot eliminate from the stack pointer.
9912 In theory you could eliminate from the hard frame
9913 pointer to the stack pointer, but this will never
9914 happen, since if a stack frame is not needed the
9915 hard frame pointer will never be used. */
9921 /* Generate the prologue instructions for entry into an ARM function. */
9923 arm_expand_prologue (void)
9929 unsigned long live_regs_mask;
9930 unsigned long func_type;
9932 int saved_pretend_args = 0;
9934 unsigned int args_to_push;
9935 arm_stack_offsets *offsets;
9937 func_type = arm_current_func_type ();
9939 /* Naked functions don't have prologues. */
9940 if (IS_NAKED (func_type))
9943 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9944 args_to_push = current_function_pretend_args_size;
9946 /* Compute which register we will have to save onto the stack. */
9947 live_regs_mask = arm_compute_save_reg_mask ();
9949 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9951 if (frame_pointer_needed)
9953 if (IS_INTERRUPT (func_type))
9955 /* Interrupt functions must not corrupt any registers.
9956 Creating a frame pointer however, corrupts the IP
9957 register, so we must push it first. */
9958 insn = emit_multi_reg_push (1 << IP_REGNUM);
9960 /* Do not set RTX_FRAME_RELATED_P on this insn.
9961 The dwarf stack unwinding code only wants to see one
9962 stack decrement per function, and this is not it. If
9963 this instruction is labeled as being part of the frame
9964 creation sequence then dwarf2out_frame_debug_expr will
9965 abort when it encounters the assignment of IP to FP
9966 later on, since the use of SP here establishes SP as
9967 the CFA register and not IP.
9969 Anyway this instruction is not really part of the stack
9970 frame creation although it is part of the prologue. */
9972 else if (IS_NESTED (func_type))
9974 /* The Static chain register is the same as the IP register
9975 used as a scratch register during stack frame creation.
9976 To get around this need to find somewhere to store IP
9977 whilst the frame is being created. We try the following
9980 1. The last argument register.
9981 2. A slot on the stack above the frame. (This only
9982 works if the function is not a varargs function).
9983 3. Register r3, after pushing the argument registers
9986 Note - we only need to tell the dwarf2 backend about the SP
9987 adjustment in the second variant; the static chain register
9988 doesn't need to be unwound, as it doesn't contain a value
9989 inherited from the caller. */
9991 if (regs_ever_live[3] == 0)
9993 insn = gen_rtx_REG (SImode, 3);
9994 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9995 insn = emit_insn (insn);
9997 else if (args_to_push == 0)
10000 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10001 insn = gen_rtx_MEM (SImode, insn);
10002 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10003 insn = emit_insn (insn);
10007 /* Just tell the dwarf backend that we adjusted SP. */
10008 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10009 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10010 GEN_INT (-fp_offset)));
10011 RTX_FRAME_RELATED_P (insn) = 1;
10012 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10013 dwarf, REG_NOTES (insn));
10017 /* Store the args on the stack. */
10018 if (cfun->machine->uses_anonymous_args)
10019 insn = emit_multi_reg_push
10020 ((0xf0 >> (args_to_push / 4)) & 0xf);
10023 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10024 GEN_INT (- args_to_push)));
10026 RTX_FRAME_RELATED_P (insn) = 1;
10028 saved_pretend_args = 1;
10029 fp_offset = args_to_push;
10032 /* Now reuse r3 to preserve IP. */
10033 insn = gen_rtx_REG (SImode, 3);
10034 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10035 (void) emit_insn (insn);
10041 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10042 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10045 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10047 insn = emit_insn (insn);
10048 RTX_FRAME_RELATED_P (insn) = 1;
10053 /* Push the argument registers, or reserve space for them. */
10054 if (cfun->machine->uses_anonymous_args)
10055 insn = emit_multi_reg_push
10056 ((0xf0 >> (args_to_push / 4)) & 0xf);
10059 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10060 GEN_INT (- args_to_push)));
10061 RTX_FRAME_RELATED_P (insn) = 1;
10064 /* If this is an interrupt service routine, and the link register
10065 is going to be pushed, and we are not creating a stack frame,
10066 (which would involve an extra push of IP and a pop in the epilogue)
10067 subtracting four from LR now will mean that the function return
10068 can be done with a single instruction. */
10069 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10070 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10071 && ! frame_pointer_needed)
10072 emit_insn (gen_rtx_SET (SImode,
10073 gen_rtx_REG (SImode, LR_REGNUM),
10074 gen_rtx_PLUS (SImode,
10075 gen_rtx_REG (SImode, LR_REGNUM),
10078 if (live_regs_mask)
10080 insn = emit_multi_reg_push (live_regs_mask);
10081 saved_regs += bit_count (live_regs_mask) * 4;
10082 RTX_FRAME_RELATED_P (insn) = 1;
10086 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10087 if (regs_ever_live[reg] && ! call_used_regs [reg])
10089 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10090 insn = gen_rtx_MEM (V2SImode, insn);
10091 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10092 gen_rtx_REG (V2SImode, reg)));
10093 RTX_FRAME_RELATED_P (insn) = 1;
10097 if (! IS_VOLATILE (func_type))
10101 /* Save any floating point call-saved registers used by this
10103 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10105 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10106 if (regs_ever_live[reg] && !call_used_regs[reg])
10108 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10109 insn = gen_rtx_MEM (XFmode, insn);
10110 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10111 gen_rtx_REG (XFmode, reg)));
10112 RTX_FRAME_RELATED_P (insn) = 1;
10118 start_reg = LAST_FPA_REGNUM;
10120 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10122 if (regs_ever_live[reg] && !call_used_regs[reg])
10124 if (start_reg - reg == 3)
10126 insn = emit_sfm (reg, 4);
10127 RTX_FRAME_RELATED_P (insn) = 1;
10129 start_reg = reg - 1;
10134 if (start_reg != reg)
10136 insn = emit_sfm (reg + 1, start_reg - reg);
10137 RTX_FRAME_RELATED_P (insn) = 1;
10138 saved_regs += (start_reg - reg) * 12;
10140 start_reg = reg - 1;
10144 if (start_reg != reg)
10146 insn = emit_sfm (reg + 1, start_reg - reg);
10147 saved_regs += (start_reg - reg) * 12;
10148 RTX_FRAME_RELATED_P (insn) = 1;
10151 if (TARGET_HARD_FLOAT && TARGET_VFP)
10153 start_reg = FIRST_VFP_REGNUM;
10155 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10157 if ((!regs_ever_live[reg] || call_used_regs[reg])
10158 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10160 if (start_reg != reg)
10161 saved_regs += vfp_emit_fstmx (start_reg,
10162 (reg - start_reg) / 2);
10163 start_reg = reg + 2;
10166 if (start_reg != reg)
10167 saved_regs += vfp_emit_fstmx (start_reg,
10168 (reg - start_reg) / 2);
10172 if (frame_pointer_needed)
10174 /* Create the new frame pointer. */
10175 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10176 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10177 RTX_FRAME_RELATED_P (insn) = 1;
10179 if (IS_NESTED (func_type))
10181 /* Recover the static chain register. */
10182 if (regs_ever_live [3] == 0
10183 || saved_pretend_args)
10184 insn = gen_rtx_REG (SImode, 3);
10185 else /* if (current_function_pretend_args_size == 0) */
10187 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10189 insn = gen_rtx_MEM (SImode, insn);
10192 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10193 /* Add a USE to stop propagate_one_insn() from barfing. */
10194 emit_insn (gen_prologue_use (ip_rtx));
10198 offsets = arm_get_frame_offsets ();
10199 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10201 /* This add can produce multiple insns for a large constant, so we
10202 need to get tricky. */
10203 rtx last = get_last_insn ();
10205 amount = GEN_INT (offsets->saved_args + saved_regs
10206 - offsets->outgoing_args);
10208 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10212 last = last ? NEXT_INSN (last) : get_insns ();
10213 RTX_FRAME_RELATED_P (last) = 1;
10215 while (last != insn);
10217 /* If the frame pointer is needed, emit a special barrier that
10218 will prevent the scheduler from moving stores to the frame
10219 before the stack adjustment. */
10220 if (frame_pointer_needed)
10221 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10222 hard_frame_pointer_rtx));
10227 arm_load_pic_register ();
10229 /* If we are profiling, make sure no instructions are scheduled before
10230 the call to mcount. Similarly if the user has requested no
10231 scheduling in the prolog. */
10232 if (current_function_profile || TARGET_NO_SCHED_PRO)
10233 emit_insn (gen_blockage ());
10235 /* If the link register is being kept alive, with the return address in it,
10236 then make sure that it does not get reused by the ce2 pass. */
10237 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10239 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10240 cfun->machine->lr_save_eliminated = 1;
10244 /* If CODE is 'd', then the X is a condition operand and the instruction
10245 should only be executed if the condition is true.
10246 if CODE is 'D', then the X is a condition operand and the instruction
10247 should only be executed if the condition is false: however, if the mode
10248 of the comparison is CCFPEmode, then always execute the instruction -- we
10249 do this because in these circumstances !GE does not necessarily imply LT;
10250 in these cases the instruction pattern will take care to make sure that
10251 an instruction containing %d will follow, thereby undoing the effects of
10252 doing this instruction unconditionally.
10253 If CODE is 'N' then X is a floating point operand that must be negated
10255 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10256 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10258 arm_print_operand (FILE *stream, rtx x, int code)
10263 fputs (ASM_COMMENT_START, stream);
10267 fputs (user_label_prefix, stream);
10271 fputs (REGISTER_PREFIX, stream);
10275 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10277 if (TARGET_THUMB || current_insn_predicate != NULL)
10280 fputs (arm_condition_codes[arm_current_cc], stream);
10282 else if (current_insn_predicate)
10284 enum arm_cond_code code;
10289 code = get_arm_condition_code (current_insn_predicate);
10290 fputs (arm_condition_codes[code], stream);
10297 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10298 r = REAL_VALUE_NEGATE (r);
10299 fprintf (stream, "%s", fp_const_from_val (&r));
10304 if (GET_CODE (x) == CONST_INT)
10307 val = ARM_SIGN_EXTEND (~INTVAL (x));
10308 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10312 putc ('~', stream);
10313 output_addr_const (stream, x);
10318 fprintf (stream, "%s", arithmetic_instr (x, 1));
10321 /* Truncate Cirrus shift counts. */
10323 if (GET_CODE (x) == CONST_INT)
10325 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10328 arm_print_operand (stream, x, 0);
10332 fprintf (stream, "%s", arithmetic_instr (x, 0));
10338 const char * shift = shift_op (x, &val);
10342 fprintf (stream, ", %s ", shift_op (x, &val));
10344 arm_print_operand (stream, XEXP (x, 1), 0);
10346 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10351 /* An explanation of the 'Q', 'R' and 'H' register operands:
10353 In a pair of registers containing a DI or DF value the 'Q'
10354 operand returns the register number of the register containing
10355 the least significant part of the value. The 'R' operand returns
10356 the register number of the register containing the most
10357 significant part of the value.
10359 The 'H' operand returns the higher of the two register numbers.
10360 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10361 same as the 'Q' operand, since the most significant part of the
10362 value is held in the lower number register. The reverse is true
10363 on systems where WORDS_BIG_ENDIAN is false.
10365 The purpose of these operands is to distinguish between cases
10366 where the endian-ness of the values is important (for example
10367 when they are added together), and cases where the endian-ness
10368 is irrelevant, but the order of register operations is important.
10369 For example when loading a value from memory into a register
10370 pair, the endian-ness does not matter. Provided that the value
10371 from the lower memory address is put into the lower numbered
10372 register, and the value from the higher address is put into the
10373 higher numbered register, the load will work regardless of whether
10374 the value being loaded is big-wordian or little-wordian. The
10375 order of the two register loads can matter however, if the address
10376 of the memory location is actually held in one of the registers
10377 being overwritten by the load. */
10379 if (REGNO (x) > LAST_ARM_REGNUM)
10381 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10385 if (REGNO (x) > LAST_ARM_REGNUM)
10387 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10391 if (REGNO (x) > LAST_ARM_REGNUM)
10393 asm_fprintf (stream, "%r", REGNO (x) + 1);
10397 asm_fprintf (stream, "%r",
10398 GET_CODE (XEXP (x, 0)) == REG
10399 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10403 asm_fprintf (stream, "{%r-%r}",
10405 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10409 /* CONST_TRUE_RTX means always -- that's the default. */
10410 if (x == const_true_rtx)
10413 fputs (arm_condition_codes[get_arm_condition_code (x)],
10418 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10419 want to do that. */
10420 if (x == const_true_rtx)
10423 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10424 (get_arm_condition_code (x))],
10428 /* Cirrus registers can be accessed in a variety of ways:
10429 single floating point (f)
10430 double floating point (d)
10432 64bit integer (dx). */
10433 case 'W': /* Cirrus register in F mode. */
10434 case 'X': /* Cirrus register in D mode. */
10435 case 'Y': /* Cirrus register in FX mode. */
10436 case 'Z': /* Cirrus register in DX mode. */
10437 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10440 fprintf (stream, "mv%s%s",
10442 : code == 'X' ? "d"
10443 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10447 /* Print cirrus register in the mode specified by the register's mode. */
10450 int mode = GET_MODE (x);
10452 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10455 fprintf (stream, "mv%s%s",
10456 mode == DFmode ? "d"
10457 : mode == SImode ? "fx"
10458 : mode == DImode ? "dx"
10459 : "f", reg_names[REGNO (x)] + 2);
10465 if (GET_CODE (x) != REG
10466 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10467 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10468 /* Bad value for wCG register number. */
10471 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10474 /* Print an iWMMXt control register name. */
10476 if (GET_CODE (x) != CONST_INT
10478 || INTVAL (x) >= 16)
10479 /* Bad value for wC register number. */
10483 static const char * wc_reg_names [16] =
10485 "wCID", "wCon", "wCSSF", "wCASF",
10486 "wC4", "wC5", "wC6", "wC7",
10487 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10488 "wC12", "wC13", "wC14", "wC15"
10491 fprintf (stream, wc_reg_names [INTVAL (x)]);
10495 /* Print a VFP double precision register name. */
10498 int mode = GET_MODE (x);
10501 if (mode != DImode && mode != DFmode)
10504 if (GET_CODE (x) != REG
10505 || !IS_VFP_REGNUM (REGNO (x)))
10508 num = REGNO(x) - FIRST_VFP_REGNUM;
10512 fprintf (stream, "d%d", num >> 1);
10520 if (GET_CODE (x) == REG)
10521 asm_fprintf (stream, "%r", REGNO (x));
10522 else if (GET_CODE (x) == MEM)
10524 output_memory_reference_mode = GET_MODE (x);
10525 output_address (XEXP (x, 0));
10527 else if (GET_CODE (x) == CONST_DOUBLE)
10528 fprintf (stream, "#%s", fp_immediate_constant (x));
10529 else if (GET_CODE (x) == NEG)
10530 abort (); /* This should never happen now. */
10533 fputc ('#', stream);
10534 output_addr_const (stream, x);
10539 #ifndef AOF_ASSEMBLER
10540 /* Target hook for assembling integer objects. The ARM version needs to
10541 handle word-sized values specially. */
10543 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10545 if (size == UNITS_PER_WORD && aligned_p)
10547 fputs ("\t.word\t", asm_out_file);
10548 output_addr_const (asm_out_file, x);
10550 /* Mark symbols as position independent. We only do this in the
10551 .text segment, not in the .data segment. */
10552 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10553 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10555 if (GET_CODE (x) == SYMBOL_REF
10556 && (CONSTANT_POOL_ADDRESS_P (x)
10557 || SYMBOL_REF_LOCAL_P (x)))
10558 fputs ("(GOTOFF)", asm_out_file);
10559 else if (GET_CODE (x) == LABEL_REF)
10560 fputs ("(GOTOFF)", asm_out_file);
10562 fputs ("(GOT)", asm_out_file);
10564 fputc ('\n', asm_out_file);
10568 if (arm_vector_mode_supported_p (GET_MODE (x)))
10572 if (GET_CODE (x) != CONST_VECTOR)
10575 units = CONST_VECTOR_NUNITS (x);
10577 switch (GET_MODE (x))
10579 case V2SImode: size = 4; break;
10580 case V4HImode: size = 2; break;
10581 case V8QImode: size = 1; break;
10586 for (i = 0; i < units; i++)
10590 elt = CONST_VECTOR_ELT (x, i);
10592 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10598 return default_assemble_integer (x, size, aligned_p);
10602 /* A finite state machine takes care of noticing whether or not instructions
10603 can be conditionally executed, and thus decrease execution time and code
10604 size by deleting branch instructions. The fsm is controlled by
10605 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10607 /* The state of the fsm controlling condition codes are:
10608 0: normal, do nothing special
10609 1: make ASM_OUTPUT_OPCODE not output this instruction
10610 2: make ASM_OUTPUT_OPCODE not output this instruction
10611 3: make instructions conditional
10612 4: make instructions conditional
10614 State transitions (state->state by whom under condition):
10615 0 -> 1 final_prescan_insn if the `target' is a label
10616 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10617 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10618 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10619 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10620 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10621 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10622 (the target insn is arm_target_insn).
10624 If the jump clobbers the conditions then we use states 2 and 4.
10626 A similar thing can be done with conditional return insns.
10628 XXX In case the `target' is an unconditional branch, this conditionalising
10629 of the instructions always reduces code size, but not always execution
10630 time. But then, I want to reduce the code size to somewhere near what
10631 /bin/cc produces. */
10633 /* Returns the index of the ARM condition code string in
10634 `arm_condition_codes'. COMPARISON should be an rtx like
10635 `(eq (...) (...))'. */
10636 static enum arm_cond_code
10637 get_arm_condition_code (rtx comparison)
10639 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10641 enum rtx_code comp_code = GET_CODE (comparison);
10643 if (GET_MODE_CLASS (mode) != MODE_CC)
10644 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10645 XEXP (comparison, 1));
10649 case CC_DNEmode: code = ARM_NE; goto dominance;
10650 case CC_DEQmode: code = ARM_EQ; goto dominance;
10651 case CC_DGEmode: code = ARM_GE; goto dominance;
10652 case CC_DGTmode: code = ARM_GT; goto dominance;
10653 case CC_DLEmode: code = ARM_LE; goto dominance;
10654 case CC_DLTmode: code = ARM_LT; goto dominance;
10655 case CC_DGEUmode: code = ARM_CS; goto dominance;
10656 case CC_DGTUmode: code = ARM_HI; goto dominance;
10657 case CC_DLEUmode: code = ARM_LS; goto dominance;
10658 case CC_DLTUmode: code = ARM_CC;
10661 if (comp_code != EQ && comp_code != NE)
10664 if (comp_code == EQ)
10665 return ARM_INVERSE_CONDITION_CODE (code);
10671 case NE: return ARM_NE;
10672 case EQ: return ARM_EQ;
10673 case GE: return ARM_PL;
10674 case LT: return ARM_MI;
10681 case NE: return ARM_NE;
10682 case EQ: return ARM_EQ;
10689 case NE: return ARM_MI;
10690 case EQ: return ARM_PL;
10696 /* These encodings assume that AC=1 in the FPA system control
10697 byte. This allows us to handle all cases except UNEQ and
10701 case GE: return ARM_GE;
10702 case GT: return ARM_GT;
10703 case LE: return ARM_LS;
10704 case LT: return ARM_MI;
10705 case NE: return ARM_NE;
10706 case EQ: return ARM_EQ;
10707 case ORDERED: return ARM_VC;
10708 case UNORDERED: return ARM_VS;
10709 case UNLT: return ARM_LT;
10710 case UNLE: return ARM_LE;
10711 case UNGT: return ARM_HI;
10712 case UNGE: return ARM_PL;
10713 /* UNEQ and LTGT do not have a representation. */
10714 case UNEQ: /* Fall through. */
10715 case LTGT: /* Fall through. */
10722 case NE: return ARM_NE;
10723 case EQ: return ARM_EQ;
10724 case GE: return ARM_LE;
10725 case GT: return ARM_LT;
10726 case LE: return ARM_GE;
10727 case LT: return ARM_GT;
10728 case GEU: return ARM_LS;
10729 case GTU: return ARM_CC;
10730 case LEU: return ARM_CS;
10731 case LTU: return ARM_HI;
10738 case LTU: return ARM_CS;
10739 case GEU: return ARM_CC;
10746 case NE: return ARM_NE;
10747 case EQ: return ARM_EQ;
10748 case GE: return ARM_GE;
10749 case GT: return ARM_GT;
10750 case LE: return ARM_LE;
10751 case LT: return ARM_LT;
10752 case GEU: return ARM_CS;
10753 case GTU: return ARM_HI;
10754 case LEU: return ARM_LS;
10755 case LTU: return ARM_CC;
10766 arm_final_prescan_insn (rtx insn)
10768 /* BODY will hold the body of INSN. */
10769 rtx body = PATTERN (insn);
10771 /* This will be 1 if trying to repeat the trick, and things need to be
10772 reversed if it appears to fail. */
10775 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10776 taken are clobbered, even if the rtl suggests otherwise. It also
10777 means that we have to grub around within the jump expression to find
10778 out what the conditions are when the jump isn't taken. */
10779 int jump_clobbers = 0;
10781 /* If we start with a return insn, we only succeed if we find another one. */
10782 int seeking_return = 0;
10784 /* START_INSN will hold the insn from where we start looking. This is the
10785 first insn after the following code_label if REVERSE is true. */
10786 rtx start_insn = insn;
10788 /* If in state 4, check if the target branch is reached, in order to
10789 change back to state 0. */
10790 if (arm_ccfsm_state == 4)
10792 if (insn == arm_target_insn)
10794 arm_target_insn = NULL;
10795 arm_ccfsm_state = 0;
10800 /* If in state 3, it is possible to repeat the trick, if this insn is an
10801 unconditional branch to a label, and immediately following this branch
10802 is the previous target label which is only used once, and the label this
10803 branch jumps to is not too far off. */
10804 if (arm_ccfsm_state == 3)
10806 if (simplejump_p (insn))
10808 start_insn = next_nonnote_insn (start_insn);
10809 if (GET_CODE (start_insn) == BARRIER)
10811 /* XXX Isn't this always a barrier? */
10812 start_insn = next_nonnote_insn (start_insn);
10814 if (GET_CODE (start_insn) == CODE_LABEL
10815 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10816 && LABEL_NUSES (start_insn) == 1)
10821 else if (GET_CODE (body) == RETURN)
10823 start_insn = next_nonnote_insn (start_insn);
10824 if (GET_CODE (start_insn) == BARRIER)
10825 start_insn = next_nonnote_insn (start_insn);
10826 if (GET_CODE (start_insn) == CODE_LABEL
10827 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10828 && LABEL_NUSES (start_insn) == 1)
10831 seeking_return = 1;
10840 if (arm_ccfsm_state != 0 && !reverse)
10842 if (GET_CODE (insn) != JUMP_INSN)
10845 /* This jump might be paralleled with a clobber of the condition codes
10846 the jump should always come first */
10847 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10848 body = XVECEXP (body, 0, 0);
10851 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10852 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10855 int fail = FALSE, succeed = FALSE;
10856 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10857 int then_not_else = TRUE;
10858 rtx this_insn = start_insn, label = 0;
10860 /* If the jump cannot be done with one instruction, we cannot
10861 conditionally execute the instruction in the inverse case. */
10862 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10868 /* Register the insn jumped to. */
10871 if (!seeking_return)
10872 label = XEXP (SET_SRC (body), 0);
10874 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10875 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10876 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10878 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10879 then_not_else = FALSE;
10881 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10882 seeking_return = 1;
10883 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10885 seeking_return = 1;
10886 then_not_else = FALSE;
10891 /* See how many insns this branch skips, and what kind of insns. If all
10892 insns are okay, and the label or unconditional branch to the same
10893 label is not too far away, succeed. */
10894 for (insns_skipped = 0;
10895 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10899 this_insn = next_nonnote_insn (this_insn);
10903 switch (GET_CODE (this_insn))
10906 /* Succeed if it is the target label, otherwise fail since
10907 control falls in from somewhere else. */
10908 if (this_insn == label)
10912 arm_ccfsm_state = 2;
10913 this_insn = next_nonnote_insn (this_insn);
10916 arm_ccfsm_state = 1;
10924 /* Succeed if the following insn is the target label.
10926 If return insns are used then the last insn in a function
10927 will be a barrier. */
10928 this_insn = next_nonnote_insn (this_insn);
10929 if (this_insn && this_insn == label)
10933 arm_ccfsm_state = 2;
10934 this_insn = next_nonnote_insn (this_insn);
10937 arm_ccfsm_state = 1;
10945 /* The AAPCS says that conditional calls should not be
10946 used since they make interworking inefficient (the
10947 linker can't transform BL<cond> into BLX). That's
10948 only a problem if the machine has BLX. */
10955 /* Succeed if the following insn is the target label, or
10956 if the following two insns are a barrier and the
10958 this_insn = next_nonnote_insn (this_insn);
10959 if (this_insn && GET_CODE (this_insn) == BARRIER)
10960 this_insn = next_nonnote_insn (this_insn);
10962 if (this_insn && this_insn == label
10963 && insns_skipped < max_insns_skipped)
10967 arm_ccfsm_state = 2;
10968 this_insn = next_nonnote_insn (this_insn);
10971 arm_ccfsm_state = 1;
10979 /* If this is an unconditional branch to the same label, succeed.
10980 If it is to another label, do nothing. If it is conditional,
10982 /* XXX Probably, the tests for SET and the PC are
10985 scanbody = PATTERN (this_insn);
10986 if (GET_CODE (scanbody) == SET
10987 && GET_CODE (SET_DEST (scanbody)) == PC)
10989 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10990 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10992 arm_ccfsm_state = 2;
10995 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10998 /* Fail if a conditional return is undesirable (eg on a
10999 StrongARM), but still allow this if optimizing for size. */
11000 else if (GET_CODE (scanbody) == RETURN
11001 && !use_return_insn (TRUE, NULL)
11004 else if (GET_CODE (scanbody) == RETURN
11007 arm_ccfsm_state = 2;
11010 else if (GET_CODE (scanbody) == PARALLEL)
11012 switch (get_attr_conds (this_insn))
11022 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11027 /* Instructions using or affecting the condition codes make it
11029 scanbody = PATTERN (this_insn);
11030 if (!(GET_CODE (scanbody) == SET
11031 || GET_CODE (scanbody) == PARALLEL)
11032 || get_attr_conds (this_insn) != CONDS_NOCOND)
11035 /* A conditional cirrus instruction must be followed by
11036 a non Cirrus instruction. However, since we
11037 conditionalize instructions in this function and by
11038 the time we get here we can't add instructions
11039 (nops), because shorten_branches() has already been
11040 called, we will disable conditionalizing Cirrus
11041 instructions to be safe. */
11042 if (GET_CODE (scanbody) != USE
11043 && GET_CODE (scanbody) != CLOBBER
11044 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11054 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11055 arm_target_label = CODE_LABEL_NUMBER (label);
11056 else if (seeking_return || arm_ccfsm_state == 2)
11058 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11060 this_insn = next_nonnote_insn (this_insn);
11061 if (this_insn && (GET_CODE (this_insn) == BARRIER
11062 || GET_CODE (this_insn) == CODE_LABEL))
11067 /* Oh, dear! we ran off the end.. give up. */
11068 recog (PATTERN (insn), insn, NULL);
11069 arm_ccfsm_state = 0;
11070 arm_target_insn = NULL;
11073 arm_target_insn = this_insn;
11082 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11084 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11085 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11086 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11087 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11091 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11094 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11098 if (reverse || then_not_else)
11099 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11102 /* Restore recog_data (getting the attributes of other insns can
11103 destroy this array, but final.c assumes that it remains intact
11104 across this call; since the insn has been recognized already we
11105 call recog direct). */
11106 recog (PATTERN (insn), insn, NULL);
11110 /* Returns true if REGNO is a valid register
11111 for holding a quantity of type MODE. */
11113 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11115 if (GET_MODE_CLASS (mode) == MODE_CC)
11116 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11119 /* For the Thumb we only allow values bigger than SImode in
11120 registers 0 - 6, so that there is always a second low
11121 register available to hold the upper part of the value.
11122 We probably we ought to ensure that the register is the
11123 start of an even numbered register pair. */
11124 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11126 if (IS_CIRRUS_REGNUM (regno))
11127 /* We have outlawed SI values in Cirrus registers because they
11128 reside in the lower 32 bits, but SF values reside in the
11129 upper 32 bits. This causes gcc all sorts of grief. We can't
11130 even split the registers into pairs because Cirrus SI values
11131 get sign extended to 64bits-- aldyh. */
11132 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11134 if (IS_VFP_REGNUM (regno))
11136 if (mode == SFmode || mode == SImode)
11139 /* DFmode values are only valid in even register pairs. */
11140 if (mode == DFmode)
11141 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11145 if (IS_IWMMXT_GR_REGNUM (regno))
11146 return mode == SImode;
11148 if (IS_IWMMXT_REGNUM (regno))
11149 return VALID_IWMMXT_REG_MODE (mode);
11151 /* We allow any value to be stored in the general registers.
11152 Restrict doubleword quantities to even register pairs so that we can
11154 if (regno <= LAST_ARM_REGNUM)
11155 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11157 if ( regno == FRAME_POINTER_REGNUM
11158 || regno == ARG_POINTER_REGNUM)
11159 /* We only allow integers in the fake hard registers. */
11160 return GET_MODE_CLASS (mode) == MODE_INT;
11162 /* The only registers left are the FPA registers
11163 which we only allow to hold FP values. */
11164 return GET_MODE_CLASS (mode) == MODE_FLOAT
11165 && regno >= FIRST_FPA_REGNUM
11166 && regno <= LAST_FPA_REGNUM;
11170 arm_regno_class (int regno)
11174 if (regno == STACK_POINTER_REGNUM)
11176 if (regno == CC_REGNUM)
11183 if ( regno <= LAST_ARM_REGNUM
11184 || regno == FRAME_POINTER_REGNUM
11185 || regno == ARG_POINTER_REGNUM)
11186 return GENERAL_REGS;
11188 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11191 if (IS_CIRRUS_REGNUM (regno))
11192 return CIRRUS_REGS;
11194 if (IS_VFP_REGNUM (regno))
11197 if (IS_IWMMXT_REGNUM (regno))
11198 return IWMMXT_REGS;
11200 if (IS_IWMMXT_GR_REGNUM (regno))
11201 return IWMMXT_GR_REGS;
11206 /* Handle a special case when computing the offset
11207 of an argument from the frame pointer. */
11209 arm_debugger_arg_offset (int value, rtx addr)
11213 /* We are only interested if dbxout_parms() failed to compute the offset. */
11217 /* We can only cope with the case where the address is held in a register. */
11218 if (GET_CODE (addr) != REG)
11221 /* If we are using the frame pointer to point at the argument, then
11222 an offset of 0 is correct. */
11223 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11226 /* If we are using the stack pointer to point at the
11227 argument, then an offset of 0 is correct. */
11228 if ((TARGET_THUMB || !frame_pointer_needed)
11229 && REGNO (addr) == SP_REGNUM)
11232 /* Oh dear. The argument is pointed to by a register rather
11233 than being held in a register, or being stored at a known
11234 offset from the frame pointer. Since GDB only understands
11235 those two kinds of argument we must translate the address
11236 held in the register into an offset from the frame pointer.
11237 We do this by searching through the insns for the function
11238 looking to see where this register gets its value. If the
11239 register is initialized from the frame pointer plus an offset
11240 then we are in luck and we can continue, otherwise we give up.
11242 This code is exercised by producing debugging information
11243 for a function with arguments like this:
11245 double func (double a, double b, int c, double d) {return d;}
11247 Without this code the stab for parameter 'd' will be set to
11248 an offset of 0 from the frame pointer, rather than 8. */
11250 /* The if() statement says:
11252 If the insn is a normal instruction
11253 and if the insn is setting the value in a register
11254 and if the register being set is the register holding the address of the argument
11255 and if the address is computing by an addition
11256 that involves adding to a register
11257 which is the frame pointer
11262 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11264 if ( GET_CODE (insn) == INSN
11265 && GET_CODE (PATTERN (insn)) == SET
11266 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11267 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11268 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11269 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11270 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11273 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11282 warning ("unable to compute real location of stacked parameter");
11283 value = 8; /* XXX magic hack */
11289 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11292 if ((MASK) & insn_flags) \
11293 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11294 BUILT_IN_MD, NULL, NULL_TREE); \
11298 struct builtin_description
11300 const unsigned int mask;
11301 const enum insn_code icode;
11302 const char * const name;
11303 const enum arm_builtins code;
11304 const enum rtx_code comparison;
11305 const unsigned int flag;
11308 static const struct builtin_description bdesc_2arg[] =
11310 #define IWMMXT_BUILTIN(code, string, builtin) \
11311 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11312 ARM_BUILTIN_##builtin, 0, 0 },
11314 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11315 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11316 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11317 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11318 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11319 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11320 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11321 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11322 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11323 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11324 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11325 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11326 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11327 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11328 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11329 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11330 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11331 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11332 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11333 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11334 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11335 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11336 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11337 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11338 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11339 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11340 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11341 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11342 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11343 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11344 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11345 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11346 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11347 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11348 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11349 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11350 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11351 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11352 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11353 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11354 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11355 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11356 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11357 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11358 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11359 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11360 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11361 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11362 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11363 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11364 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11365 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11366 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11367 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11368 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11369 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11370 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11371 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11373 #define IWMMXT_BUILTIN2(code, builtin) \
11374 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11376 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11377 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11378 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11379 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11380 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11381 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11382 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11383 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11384 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11385 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11386 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11387 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11388 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11389 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11390 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11391 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11392 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11393 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11394 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11395 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11396 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11397 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11398 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11399 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11400 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11401 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11402 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11403 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11404 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11405 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11406 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11407 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11410 static const struct builtin_description bdesc_1arg[] =
11412 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11413 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11414 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11415 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11416 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11417 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11418 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11419 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11420 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11421 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11422 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11423 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11424 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11425 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11426 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11427 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11428 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11429 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11432 /* Set up all the iWMMXt builtins. This is
11433 not called if TARGET_IWMMXT is zero. */
11436 arm_init_iwmmxt_builtins (void)
11438 const struct builtin_description * d;
11440 tree endlink = void_list_node;
11442 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11443 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11444 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11447 = build_function_type (integer_type_node,
11448 tree_cons (NULL_TREE, integer_type_node, endlink));
11449 tree v8qi_ftype_v8qi_v8qi_int
11450 = build_function_type (V8QI_type_node,
11451 tree_cons (NULL_TREE, V8QI_type_node,
11452 tree_cons (NULL_TREE, V8QI_type_node,
11453 tree_cons (NULL_TREE,
11456 tree v4hi_ftype_v4hi_int
11457 = build_function_type (V4HI_type_node,
11458 tree_cons (NULL_TREE, V4HI_type_node,
11459 tree_cons (NULL_TREE, integer_type_node,
11461 tree v2si_ftype_v2si_int
11462 = build_function_type (V2SI_type_node,
11463 tree_cons (NULL_TREE, V2SI_type_node,
11464 tree_cons (NULL_TREE, integer_type_node,
11466 tree v2si_ftype_di_di
11467 = build_function_type (V2SI_type_node,
11468 tree_cons (NULL_TREE, long_long_integer_type_node,
11469 tree_cons (NULL_TREE, long_long_integer_type_node,
11471 tree di_ftype_di_int
11472 = build_function_type (long_long_integer_type_node,
11473 tree_cons (NULL_TREE, long_long_integer_type_node,
11474 tree_cons (NULL_TREE, integer_type_node,
11476 tree di_ftype_di_int_int
11477 = build_function_type (long_long_integer_type_node,
11478 tree_cons (NULL_TREE, long_long_integer_type_node,
11479 tree_cons (NULL_TREE, integer_type_node,
11480 tree_cons (NULL_TREE,
11483 tree int_ftype_v8qi
11484 = build_function_type (integer_type_node,
11485 tree_cons (NULL_TREE, V8QI_type_node,
11487 tree int_ftype_v4hi
11488 = build_function_type (integer_type_node,
11489 tree_cons (NULL_TREE, V4HI_type_node,
11491 tree int_ftype_v2si
11492 = build_function_type (integer_type_node,
11493 tree_cons (NULL_TREE, V2SI_type_node,
11495 tree int_ftype_v8qi_int
11496 = build_function_type (integer_type_node,
11497 tree_cons (NULL_TREE, V8QI_type_node,
11498 tree_cons (NULL_TREE, integer_type_node,
11500 tree int_ftype_v4hi_int
11501 = build_function_type (integer_type_node,
11502 tree_cons (NULL_TREE, V4HI_type_node,
11503 tree_cons (NULL_TREE, integer_type_node,
11505 tree int_ftype_v2si_int
11506 = build_function_type (integer_type_node,
11507 tree_cons (NULL_TREE, V2SI_type_node,
11508 tree_cons (NULL_TREE, integer_type_node,
11510 tree v8qi_ftype_v8qi_int_int
11511 = build_function_type (V8QI_type_node,
11512 tree_cons (NULL_TREE, V8QI_type_node,
11513 tree_cons (NULL_TREE, integer_type_node,
11514 tree_cons (NULL_TREE,
11517 tree v4hi_ftype_v4hi_int_int
11518 = build_function_type (V4HI_type_node,
11519 tree_cons (NULL_TREE, V4HI_type_node,
11520 tree_cons (NULL_TREE, integer_type_node,
11521 tree_cons (NULL_TREE,
11524 tree v2si_ftype_v2si_int_int
11525 = build_function_type (V2SI_type_node,
11526 tree_cons (NULL_TREE, V2SI_type_node,
11527 tree_cons (NULL_TREE, integer_type_node,
11528 tree_cons (NULL_TREE,
11531 /* Miscellaneous. */
11532 tree v8qi_ftype_v4hi_v4hi
11533 = build_function_type (V8QI_type_node,
11534 tree_cons (NULL_TREE, V4HI_type_node,
11535 tree_cons (NULL_TREE, V4HI_type_node,
11537 tree v4hi_ftype_v2si_v2si
11538 = build_function_type (V4HI_type_node,
11539 tree_cons (NULL_TREE, V2SI_type_node,
11540 tree_cons (NULL_TREE, V2SI_type_node,
11542 tree v2si_ftype_v4hi_v4hi
11543 = build_function_type (V2SI_type_node,
11544 tree_cons (NULL_TREE, V4HI_type_node,
11545 tree_cons (NULL_TREE, V4HI_type_node,
11547 tree v2si_ftype_v8qi_v8qi
11548 = build_function_type (V2SI_type_node,
11549 tree_cons (NULL_TREE, V8QI_type_node,
11550 tree_cons (NULL_TREE, V8QI_type_node,
11552 tree v4hi_ftype_v4hi_di
11553 = build_function_type (V4HI_type_node,
11554 tree_cons (NULL_TREE, V4HI_type_node,
11555 tree_cons (NULL_TREE,
11556 long_long_integer_type_node,
11558 tree v2si_ftype_v2si_di
11559 = build_function_type (V2SI_type_node,
11560 tree_cons (NULL_TREE, V2SI_type_node,
11561 tree_cons (NULL_TREE,
11562 long_long_integer_type_node,
11564 tree void_ftype_int_int
11565 = build_function_type (void_type_node,
11566 tree_cons (NULL_TREE, integer_type_node,
11567 tree_cons (NULL_TREE, integer_type_node,
11570 = build_function_type (long_long_unsigned_type_node, endlink);
11572 = build_function_type (long_long_integer_type_node,
11573 tree_cons (NULL_TREE, V8QI_type_node,
11576 = build_function_type (long_long_integer_type_node,
11577 tree_cons (NULL_TREE, V4HI_type_node,
11580 = build_function_type (long_long_integer_type_node,
11581 tree_cons (NULL_TREE, V2SI_type_node,
11583 tree v2si_ftype_v4hi
11584 = build_function_type (V2SI_type_node,
11585 tree_cons (NULL_TREE, V4HI_type_node,
11587 tree v4hi_ftype_v8qi
11588 = build_function_type (V4HI_type_node,
11589 tree_cons (NULL_TREE, V8QI_type_node,
11592 tree di_ftype_di_v4hi_v4hi
11593 = build_function_type (long_long_unsigned_type_node,
11594 tree_cons (NULL_TREE,
11595 long_long_unsigned_type_node,
11596 tree_cons (NULL_TREE, V4HI_type_node,
11597 tree_cons (NULL_TREE,
11601 tree di_ftype_v4hi_v4hi
11602 = build_function_type (long_long_unsigned_type_node,
11603 tree_cons (NULL_TREE, V4HI_type_node,
11604 tree_cons (NULL_TREE, V4HI_type_node,
11607 /* Normal vector binops. */
11608 tree v8qi_ftype_v8qi_v8qi
11609 = build_function_type (V8QI_type_node,
11610 tree_cons (NULL_TREE, V8QI_type_node,
11611 tree_cons (NULL_TREE, V8QI_type_node,
11613 tree v4hi_ftype_v4hi_v4hi
11614 = build_function_type (V4HI_type_node,
11615 tree_cons (NULL_TREE, V4HI_type_node,
11616 tree_cons (NULL_TREE, V4HI_type_node,
11618 tree v2si_ftype_v2si_v2si
11619 = build_function_type (V2SI_type_node,
11620 tree_cons (NULL_TREE, V2SI_type_node,
11621 tree_cons (NULL_TREE, V2SI_type_node,
11623 tree di_ftype_di_di
11624 = build_function_type (long_long_unsigned_type_node,
11625 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11626 tree_cons (NULL_TREE,
11627 long_long_unsigned_type_node,
11630 /* Add all builtins that are more or less simple operations on two
11632 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11634 /* Use one of the operands; the target can have a different mode for
11635 mask-generating compares. */
11636 enum machine_mode mode;
11642 mode = insn_data[d->icode].operand[1].mode;
11647 type = v8qi_ftype_v8qi_v8qi;
11650 type = v4hi_ftype_v4hi_v4hi;
11653 type = v2si_ftype_v2si_v2si;
11656 type = di_ftype_di_di;
11663 def_mbuiltin (d->mask, d->name, type, d->code);
11666 /* Add the remaining MMX insns with somewhat more complicated types. */
11667 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11668 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11669 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11671 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11672 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11673 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11674 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11675 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11676 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11678 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11679 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11680 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11681 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11682 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11683 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11685 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11686 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11687 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11688 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11689 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11690 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11692 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11693 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11694 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11695 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11696 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11697 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11699 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11701 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11702 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11703 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11704 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11706 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11707 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11708 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11709 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11710 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11711 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11712 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11713 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11714 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11716 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11717 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11718 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11720 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11721 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11722 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11724 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11725 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11726 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11727 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11728 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11729 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11731 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11732 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11733 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11734 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11735 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11736 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11737 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11738 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11739 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11740 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11741 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11742 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11744 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11745 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11746 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11747 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11749 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11750 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11751 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11752 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11753 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11754 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11755 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11759 arm_init_builtins (void)
11761 if (TARGET_REALLY_IWMMXT)
11762 arm_init_iwmmxt_builtins ();
11765 /* Errors in the source file can cause expand_expr to return const0_rtx
11766 where we expect a vector. To avoid crashing, use one of the vector
11767 clear instructions. */
11770 safe_vector_operand (rtx x, enum machine_mode mode)
11772 if (x != const0_rtx)
11774 x = gen_reg_rtx (mode);
11776 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11777 : gen_rtx_SUBREG (DImode, x, 0)));
11781 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11784 arm_expand_binop_builtin (enum insn_code icode,
11785 tree arglist, rtx target)
11788 tree arg0 = TREE_VALUE (arglist);
11789 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11790 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11791 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11792 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11793 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11794 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11796 if (VECTOR_MODE_P (mode0))
11797 op0 = safe_vector_operand (op0, mode0);
11798 if (VECTOR_MODE_P (mode1))
11799 op1 = safe_vector_operand (op1, mode1);
11802 || GET_MODE (target) != tmode
11803 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11804 target = gen_reg_rtx (tmode);
11806 /* In case the insn wants input operands in modes different from
11807 the result, abort. */
11808 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11811 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11812 op0 = copy_to_mode_reg (mode0, op0);
11813 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11814 op1 = copy_to_mode_reg (mode1, op1);
11816 pat = GEN_FCN (icode) (target, op0, op1);
11823 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11826 arm_expand_unop_builtin (enum insn_code icode,
11827 tree arglist, rtx target, int do_load)
11830 tree arg0 = TREE_VALUE (arglist);
11831 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11832 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11833 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11836 || GET_MODE (target) != tmode
11837 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11838 target = gen_reg_rtx (tmode);
11840 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
11843 if (VECTOR_MODE_P (mode0))
11844 op0 = safe_vector_operand (op0, mode0);
11846 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11847 op0 = copy_to_mode_reg (mode0, op0);
11850 pat = GEN_FCN (icode) (target, op0);
11857 /* Expand an expression EXP that calls a built-in function,
11858 with result going to TARGET if that's convenient
11859 (and in mode MODE if that's convenient).
11860 SUBTARGET may be used as the target for computing one of EXP's operands.
11861 IGNORE is nonzero if the value is to be ignored. */
11864 arm_expand_builtin (tree exp,
11866 rtx subtarget ATTRIBUTE_UNUSED,
11867 enum machine_mode mode ATTRIBUTE_UNUSED,
11868 int ignore ATTRIBUTE_UNUSED)
11870 const struct builtin_description * d;
11871 enum insn_code icode;
11872 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11873 tree arglist = TREE_OPERAND (exp, 1);
11881 int fcode = DECL_FUNCTION_CODE (fndecl);
11883 enum machine_mode tmode;
11884 enum machine_mode mode0;
11885 enum machine_mode mode1;
11886 enum machine_mode mode2;
11890 case ARM_BUILTIN_TEXTRMSB:
11891 case ARM_BUILTIN_TEXTRMUB:
11892 case ARM_BUILTIN_TEXTRMSH:
11893 case ARM_BUILTIN_TEXTRMUH:
11894 case ARM_BUILTIN_TEXTRMSW:
11895 case ARM_BUILTIN_TEXTRMUW:
11896 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11897 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11898 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11899 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11900 : CODE_FOR_iwmmxt_textrmw);
11902 arg0 = TREE_VALUE (arglist);
11903 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11904 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11905 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11906 tmode = insn_data[icode].operand[0].mode;
11907 mode0 = insn_data[icode].operand[1].mode;
11908 mode1 = insn_data[icode].operand[2].mode;
11910 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11911 op0 = copy_to_mode_reg (mode0, op0);
11912 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11914 /* @@@ better error message */
11915 error ("selector must be an immediate");
11916 return gen_reg_rtx (tmode);
11919 || GET_MODE (target) != tmode
11920 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11921 target = gen_reg_rtx (tmode);
11922 pat = GEN_FCN (icode) (target, op0, op1);
11928 case ARM_BUILTIN_TINSRB:
11929 case ARM_BUILTIN_TINSRH:
11930 case ARM_BUILTIN_TINSRW:
11931 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11932 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11933 : CODE_FOR_iwmmxt_tinsrw);
11934 arg0 = TREE_VALUE (arglist);
11935 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11936 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11937 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11938 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11939 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11940 tmode = insn_data[icode].operand[0].mode;
11941 mode0 = insn_data[icode].operand[1].mode;
11942 mode1 = insn_data[icode].operand[2].mode;
11943 mode2 = insn_data[icode].operand[3].mode;
11945 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11946 op0 = copy_to_mode_reg (mode0, op0);
11947 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11948 op1 = copy_to_mode_reg (mode1, op1);
11949 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11951 /* @@@ better error message */
11952 error ("selector must be an immediate");
11956 || GET_MODE (target) != tmode
11957 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11958 target = gen_reg_rtx (tmode);
11959 pat = GEN_FCN (icode) (target, op0, op1, op2);
11965 case ARM_BUILTIN_SETWCX:
11966 arg0 = TREE_VALUE (arglist);
11967 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11968 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
11969 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11970 emit_insn (gen_iwmmxt_tmcr (op1, op0));
11973 case ARM_BUILTIN_GETWCX:
11974 arg0 = TREE_VALUE (arglist);
11975 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11976 target = gen_reg_rtx (SImode);
11977 emit_insn (gen_iwmmxt_tmrc (target, op0));
11980 case ARM_BUILTIN_WSHUFH:
11981 icode = CODE_FOR_iwmmxt_wshufh;
11982 arg0 = TREE_VALUE (arglist);
11983 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11984 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11985 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11986 tmode = insn_data[icode].operand[0].mode;
11987 mode1 = insn_data[icode].operand[1].mode;
11988 mode2 = insn_data[icode].operand[2].mode;
11990 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
11991 op0 = copy_to_mode_reg (mode1, op0);
11992 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
11994 /* @@@ better error message */
11995 error ("mask must be an immediate");
11999 || GET_MODE (target) != tmode
12000 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12001 target = gen_reg_rtx (tmode);
12002 pat = GEN_FCN (icode) (target, op0, op1);
12008 case ARM_BUILTIN_WSADB:
12009 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12010 case ARM_BUILTIN_WSADH:
12011 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12012 case ARM_BUILTIN_WSADBZ:
12013 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12014 case ARM_BUILTIN_WSADHZ:
12015 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12017 /* Several three-argument builtins. */
12018 case ARM_BUILTIN_WMACS:
12019 case ARM_BUILTIN_WMACU:
12020 case ARM_BUILTIN_WALIGN:
12021 case ARM_BUILTIN_TMIA:
12022 case ARM_BUILTIN_TMIAPH:
12023 case ARM_BUILTIN_TMIATT:
12024 case ARM_BUILTIN_TMIATB:
12025 case ARM_BUILTIN_TMIABT:
12026 case ARM_BUILTIN_TMIABB:
12027 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12028 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12029 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12030 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12031 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12032 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12033 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12034 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12035 : CODE_FOR_iwmmxt_walign);
12036 arg0 = TREE_VALUE (arglist);
12037 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12038 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12039 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12040 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12041 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12042 tmode = insn_data[icode].operand[0].mode;
12043 mode0 = insn_data[icode].operand[1].mode;
12044 mode1 = insn_data[icode].operand[2].mode;
12045 mode2 = insn_data[icode].operand[3].mode;
12047 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12048 op0 = copy_to_mode_reg (mode0, op0);
12049 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12050 op1 = copy_to_mode_reg (mode1, op1);
12051 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12052 op2 = copy_to_mode_reg (mode2, op2);
12054 || GET_MODE (target) != tmode
12055 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12056 target = gen_reg_rtx (tmode);
12057 pat = GEN_FCN (icode) (target, op0, op1, op2);
12063 case ARM_BUILTIN_WZERO:
12064 target = gen_reg_rtx (DImode);
12065 emit_insn (gen_iwmmxt_clrdi (target));
12072 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12073 if (d->code == (const enum arm_builtins) fcode)
12074 return arm_expand_binop_builtin (d->icode, arglist, target);
12076 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12077 if (d->code == (const enum arm_builtins) fcode)
12078 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12080 /* @@@ Should really do something sensible here. */
12084 /* Recursively search through all of the blocks in a function
12085 checking to see if any of the variables created in that
12086 function match the RTX called 'orig'. If they do then
12087 replace them with the RTX called 'new'. */
12089 replace_symbols_in_block (tree block, rtx orig, rtx new)
12091 for (; block; block = BLOCK_CHAIN (block))
12095 if (!TREE_USED (block))
12098 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12100 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12101 || DECL_IGNORED_P (sym)
12102 || TREE_CODE (sym) != VAR_DECL
12103 || DECL_EXTERNAL (sym)
12104 || !rtx_equal_p (DECL_RTL (sym), orig)
12108 SET_DECL_RTL (sym, new);
12111 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12115 /* Return the number (counting from 0) of
12116 the least significant set bit in MASK. */
12119 number_of_first_bit_set (int mask)
12124 (mask & (1 << bit)) == 0;
12131 /* Generate code to return from a thumb function.
12132 If 'reg_containing_return_addr' is -1, then the return address is
12133 actually on the stack, at the stack pointer. */
12135 thumb_exit (FILE *f, int reg_containing_return_addr)
12137 unsigned regs_available_for_popping;
12138 unsigned regs_to_pop;
12140 unsigned available;
12144 int restore_a4 = FALSE;
12146 /* Compute the registers we need to pop. */
12150 if (reg_containing_return_addr == -1)
12152 regs_to_pop |= 1 << LR_REGNUM;
12156 if (TARGET_BACKTRACE)
12158 /* Restore the (ARM) frame pointer and stack pointer. */
12159 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12163 /* If there is nothing to pop then just emit the BX instruction and
12165 if (pops_needed == 0)
12167 if (current_function_calls_eh_return)
12168 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12170 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12173 /* Otherwise if we are not supporting interworking and we have not created
12174 a backtrace structure and the function was not entered in ARM mode then
12175 just pop the return address straight into the PC. */
12176 else if (!TARGET_INTERWORK
12177 && !TARGET_BACKTRACE
12178 && !is_called_in_ARM_mode (current_function_decl)
12179 && !current_function_calls_eh_return)
12181 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12185 /* Find out how many of the (return) argument registers we can corrupt. */
12186 regs_available_for_popping = 0;
12188 /* If returning via __builtin_eh_return, the bottom three registers
12189 all contain information needed for the return. */
12190 if (current_function_calls_eh_return)
12194 /* If we can deduce the registers used from the function's
12195 return value. This is more reliable that examining
12196 regs_ever_live[] because that will be set if the register is
12197 ever used in the function, not just if the register is used
12198 to hold a return value. */
12200 if (current_function_return_rtx != 0)
12201 mode = GET_MODE (current_function_return_rtx);
12203 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12205 size = GET_MODE_SIZE (mode);
12209 /* In a void function we can use any argument register.
12210 In a function that returns a structure on the stack
12211 we can use the second and third argument registers. */
12212 if (mode == VOIDmode)
12213 regs_available_for_popping =
12214 (1 << ARG_REGISTER (1))
12215 | (1 << ARG_REGISTER (2))
12216 | (1 << ARG_REGISTER (3));
12218 regs_available_for_popping =
12219 (1 << ARG_REGISTER (2))
12220 | (1 << ARG_REGISTER (3));
12222 else if (size <= 4)
12223 regs_available_for_popping =
12224 (1 << ARG_REGISTER (2))
12225 | (1 << ARG_REGISTER (3));
12226 else if (size <= 8)
12227 regs_available_for_popping =
12228 (1 << ARG_REGISTER (3));
12231 /* Match registers to be popped with registers into which we pop them. */
12232 for (available = regs_available_for_popping,
12233 required = regs_to_pop;
12234 required != 0 && available != 0;
12235 available &= ~(available & - available),
12236 required &= ~(required & - required))
12239 /* If we have any popping registers left over, remove them. */
12241 regs_available_for_popping &= ~available;
12243 /* Otherwise if we need another popping register we can use
12244 the fourth argument register. */
12245 else if (pops_needed)
12247 /* If we have not found any free argument registers and
12248 reg a4 contains the return address, we must move it. */
12249 if (regs_available_for_popping == 0
12250 && reg_containing_return_addr == LAST_ARG_REGNUM)
12252 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12253 reg_containing_return_addr = LR_REGNUM;
12255 else if (size > 12)
12257 /* Register a4 is being used to hold part of the return value,
12258 but we have dire need of a free, low register. */
12261 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12264 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12266 /* The fourth argument register is available. */
12267 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12273 /* Pop as many registers as we can. */
12274 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12275 regs_available_for_popping);
12277 /* Process the registers we popped. */
12278 if (reg_containing_return_addr == -1)
12280 /* The return address was popped into the lowest numbered register. */
12281 regs_to_pop &= ~(1 << LR_REGNUM);
12283 reg_containing_return_addr =
12284 number_of_first_bit_set (regs_available_for_popping);
12286 /* Remove this register for the mask of available registers, so that
12287 the return address will not be corrupted by further pops. */
12288 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12291 /* If we popped other registers then handle them here. */
12292 if (regs_available_for_popping)
12296 /* Work out which register currently contains the frame pointer. */
12297 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12299 /* Move it into the correct place. */
12300 asm_fprintf (f, "\tmov\t%r, %r\n",
12301 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12303 /* (Temporarily) remove it from the mask of popped registers. */
12304 regs_available_for_popping &= ~(1 << frame_pointer);
12305 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12307 if (regs_available_for_popping)
12311 /* We popped the stack pointer as well,
12312 find the register that contains it. */
12313 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12315 /* Move it into the stack register. */
12316 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12318 /* At this point we have popped all necessary registers, so
12319 do not worry about restoring regs_available_for_popping
12320 to its correct value:
12322 assert (pops_needed == 0)
12323 assert (regs_available_for_popping == (1 << frame_pointer))
12324 assert (regs_to_pop == (1 << STACK_POINTER)) */
12328 /* Since we have just move the popped value into the frame
12329 pointer, the popping register is available for reuse, and
12330 we know that we still have the stack pointer left to pop. */
12331 regs_available_for_popping |= (1 << frame_pointer);
12335 /* If we still have registers left on the stack, but we no longer have
12336 any registers into which we can pop them, then we must move the return
12337 address into the link register and make available the register that
12339 if (regs_available_for_popping == 0 && pops_needed > 0)
12341 regs_available_for_popping |= 1 << reg_containing_return_addr;
12343 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12344 reg_containing_return_addr);
12346 reg_containing_return_addr = LR_REGNUM;
12349 /* If we have registers left on the stack then pop some more.
12350 We know that at most we will want to pop FP and SP. */
12351 if (pops_needed > 0)
12356 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12357 regs_available_for_popping);
12359 /* We have popped either FP or SP.
12360 Move whichever one it is into the correct register. */
12361 popped_into = number_of_first_bit_set (regs_available_for_popping);
12362 move_to = number_of_first_bit_set (regs_to_pop);
12364 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12366 regs_to_pop &= ~(1 << move_to);
12371 /* If we still have not popped everything then we must have only
12372 had one register available to us and we are now popping the SP. */
12373 if (pops_needed > 0)
12377 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12378 regs_available_for_popping);
12380 popped_into = number_of_first_bit_set (regs_available_for_popping);
12382 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12384 assert (regs_to_pop == (1 << STACK_POINTER))
12385 assert (pops_needed == 1)
12389 /* If necessary restore the a4 register. */
12392 if (reg_containing_return_addr != LR_REGNUM)
12394 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12395 reg_containing_return_addr = LR_REGNUM;
12398 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12401 if (current_function_calls_eh_return)
12402 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12404 /* Return to caller. */
12405 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12408 /* Emit code to push or pop registers to or from the stack. F is the
12409 assembly file. MASK is the registers to push or pop. PUSH is
12410 nonzero if we should push, and zero if we should pop. For debugging
12411 output, if pushing, adjust CFA_OFFSET by the amount of space added
12412 to the stack. REAL_REGS should have the same number of bits set as
12413 MASK, and will be used instead (in the same order) to describe which
12414 registers were saved - this is used to mark the save slots when we
12415 push high registers after moving them to low registers. */
12417 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12420 int lo_mask = mask & 0xFF;
12421 int pushed_words = 0;
12423 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12425 /* Special case. Do not generate a POP PC statement here, do it in
12427 thumb_exit (f, -1);
12431 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12433 /* Look at the low registers first. */
12434 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12438 asm_fprintf (f, "%r", regno);
12440 if ((lo_mask & ~1) != 0)
12447 if (push && (mask & (1 << LR_REGNUM)))
12449 /* Catch pushing the LR. */
12453 asm_fprintf (f, "%r", LR_REGNUM);
12457 else if (!push && (mask & (1 << PC_REGNUM)))
12459 /* Catch popping the PC. */
12460 if (TARGET_INTERWORK || TARGET_BACKTRACE
12461 || current_function_calls_eh_return)
12463 /* The PC is never poped directly, instead
12464 it is popped into r3 and then BX is used. */
12465 fprintf (f, "}\n");
12467 thumb_exit (f, -1);
12476 asm_fprintf (f, "%r", PC_REGNUM);
12480 fprintf (f, "}\n");
12482 if (push && pushed_words && dwarf2out_do_frame ())
12484 char *l = dwarf2out_cfi_label ();
12485 int pushed_mask = real_regs;
12487 *cfa_offset += pushed_words * 4;
12488 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12491 pushed_mask = real_regs;
12492 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12494 if (pushed_mask & 1)
12495 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12501 thumb_final_prescan_insn (rtx insn)
12503 if (flag_print_asm_name)
12504 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12505 INSN_ADDRESSES (INSN_UID (insn)));
12509 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12511 unsigned HOST_WIDE_INT mask = 0xff;
12514 if (val == 0) /* XXX */
12517 for (i = 0; i < 25; i++)
12518 if ((val & (mask << i)) == val)
12524 /* Returns nonzero if the current function contains,
12525 or might contain a far jump. */
12527 thumb_far_jump_used_p (void)
12531 /* This test is only important for leaf functions. */
12532 /* assert (!leaf_function_p ()); */
12534 /* If we have already decided that far jumps may be used,
12535 do not bother checking again, and always return true even if
12536 it turns out that they are not being used. Once we have made
12537 the decision that far jumps are present (and that hence the link
12538 register will be pushed onto the stack) we cannot go back on it. */
12539 if (cfun->machine->far_jump_used)
12542 /* If this function is not being called from the prologue/epilogue
12543 generation code then it must be being called from the
12544 INITIAL_ELIMINATION_OFFSET macro. */
12545 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12547 /* In this case we know that we are being asked about the elimination
12548 of the arg pointer register. If that register is not being used,
12549 then there are no arguments on the stack, and we do not have to
12550 worry that a far jump might force the prologue to push the link
12551 register, changing the stack offsets. In this case we can just
12552 return false, since the presence of far jumps in the function will
12553 not affect stack offsets.
12555 If the arg pointer is live (or if it was live, but has now been
12556 eliminated and so set to dead) then we do have to test to see if
12557 the function might contain a far jump. This test can lead to some
12558 false negatives, since before reload is completed, then length of
12559 branch instructions is not known, so gcc defaults to returning their
12560 longest length, which in turn sets the far jump attribute to true.
12562 A false negative will not result in bad code being generated, but it
12563 will result in a needless push and pop of the link register. We
12564 hope that this does not occur too often.
12566 If we need doubleword stack alignment this could affect the other
12567 elimination offsets so we can't risk getting it wrong. */
12568 if (regs_ever_live [ARG_POINTER_REGNUM])
12569 cfun->machine->arg_pointer_live = 1;
12570 else if (!cfun->machine->arg_pointer_live)
12574 /* Check to see if the function contains a branch
12575 insn with the far jump attribute set. */
12576 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12578 if (GET_CODE (insn) == JUMP_INSN
12579 /* Ignore tablejump patterns. */
12580 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12581 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12582 && get_attr_far_jump (insn) == FAR_JUMP_YES
12585 /* Record the fact that we have decided that
12586 the function does use far jumps. */
12587 cfun->machine->far_jump_used = 1;
12595 /* Return nonzero if FUNC must be entered in ARM mode. */
12597 is_called_in_ARM_mode (tree func)
12599 if (TREE_CODE (func) != FUNCTION_DECL)
12602 /* Ignore the problem about functions whoes address is taken. */
12603 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12607 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12613 /* The bits which aren't usefully expanded as rtl. */
12615 thumb_unexpanded_epilogue (void)
12618 int live_regs_mask = 0;
12619 int high_regs_pushed = 0;
12620 int had_to_push_lr;
12624 if (return_used_this_function)
12627 if (IS_NAKED (arm_current_func_type ()))
12630 live_regs_mask = thumb_compute_save_reg_mask ();
12631 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
12633 /* If we can deduce the registers used from the function's return value.
12634 This is more reliable that examining regs_ever_live[] because that
12635 will be set if the register is ever used in the function, not just if
12636 the register is used to hold a return value. */
12638 if (current_function_return_rtx != 0)
12639 mode = GET_MODE (current_function_return_rtx);
12641 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12643 size = GET_MODE_SIZE (mode);
12645 /* The prolog may have pushed some high registers to use as
12646 work registers. eg the testsuite file:
12647 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12648 compiles to produce:
12649 push {r4, r5, r6, r7, lr}
12653 as part of the prolog. We have to undo that pushing here. */
12655 if (high_regs_pushed)
12657 int mask = live_regs_mask & 0xff;
12660 /* The available low registers depend on the size of the value we are
12668 /* Oh dear! We have no low registers into which we can pop
12671 ("no low registers available for popping high registers");
12673 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12674 if (live_regs_mask & (1 << next_hi_reg))
12677 while (high_regs_pushed)
12679 /* Find lo register(s) into which the high register(s) can
12681 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12683 if (mask & (1 << regno))
12684 high_regs_pushed--;
12685 if (high_regs_pushed == 0)
12689 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12691 /* Pop the values into the low register(s). */
12692 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12694 /* Move the value(s) into the high registers. */
12695 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12697 if (mask & (1 << regno))
12699 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12702 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12703 if (live_regs_mask & (1 << next_hi_reg))
12708 live_regs_mask &= ~0x0f00;
12711 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
12712 live_regs_mask &= 0xff;
12714 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12716 /* Pop the return address into the PC. */
12717 if (had_to_push_lr)
12718 live_regs_mask |= 1 << PC_REGNUM;
12720 /* Either no argument registers were pushed or a backtrace
12721 structure was created which includes an adjusted stack
12722 pointer, so just pop everything. */
12723 if (live_regs_mask)
12724 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12727 /* We have either just popped the return address into the
12728 PC or it is was kept in LR for the entire function. */
12729 if (!had_to_push_lr)
12730 thumb_exit (asm_out_file, LR_REGNUM);
12734 /* Pop everything but the return address. */
12735 if (live_regs_mask)
12736 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12739 if (had_to_push_lr)
12743 /* We have no free low regs, so save one. */
12744 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
12748 /* Get the return address into a temporary register. */
12749 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12750 1 << LAST_ARG_REGNUM);
12754 /* Move the return address to lr. */
12755 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
12757 /* Restore the low register. */
12758 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
12763 regno = LAST_ARG_REGNUM;
12768 /* Remove the argument registers that were pushed onto the stack. */
12769 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12770 SP_REGNUM, SP_REGNUM,
12771 current_function_pretend_args_size);
12773 thumb_exit (asm_out_file, regno);
12779 /* Functions to save and restore machine-specific function data. */
12780 static struct machine_function *
12781 arm_init_machine_status (void)
12783 struct machine_function *machine;
12784 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12786 #if ARM_FT_UNKNOWN != 0
12787 machine->func_type = ARM_FT_UNKNOWN;
12792 /* Return an RTX indicating where the return address to the
12793 calling function can be found. */
12795 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12800 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12803 /* Do anything needed before RTL is emitted for each function. */
12805 arm_init_expanders (void)
12807 /* Arrange to initialize and mark the machine per-function status. */
12808 init_machine_status = arm_init_machine_status;
12810 /* This is to stop the combine pass optimizing away the alignment
12811 adjustment of va_arg. */
12812 /* ??? It is claimed that this should not be necessary. */
12814 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
12818 /* Like arm_compute_initial_elimination offset. Simpler because
12819 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
12822 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
12824 arm_stack_offsets *offsets;
12826 offsets = arm_get_frame_offsets ();
12830 case ARG_POINTER_REGNUM:
12833 case STACK_POINTER_REGNUM:
12834 return offsets->outgoing_args - offsets->saved_args;
12836 case FRAME_POINTER_REGNUM:
12837 return offsets->soft_frame - offsets->saved_args;
12839 case THUMB_HARD_FRAME_POINTER_REGNUM:
12840 case ARM_HARD_FRAME_POINTER_REGNUM:
12841 return offsets->saved_regs - offsets->saved_args;
12848 case FRAME_POINTER_REGNUM:
12851 case STACK_POINTER_REGNUM:
12852 return offsets->outgoing_args - offsets->soft_frame;
12854 case THUMB_HARD_FRAME_POINTER_REGNUM:
12855 case ARM_HARD_FRAME_POINTER_REGNUM:
12856 return offsets->saved_regs - offsets->soft_frame;
12869 /* Generate the rest of a function's prologue. */
12871 thumb_expand_prologue (void)
12875 HOST_WIDE_INT amount;
12876 arm_stack_offsets *offsets;
12877 unsigned long func_type;
12879 unsigned long live_regs_mask;
12881 func_type = arm_current_func_type ();
12883 /* Naked functions don't have prologues. */
12884 if (IS_NAKED (func_type))
12887 if (IS_INTERRUPT (func_type))
12889 error ("interrupt Service Routines cannot be coded in Thumb mode");
12893 /* Load the pic recister before setting the frame pointer, so we can use r7
12894 as a temporary work register. */
12896 arm_load_pic_register ();
12898 offsets = arm_get_frame_offsets ();
12900 if (frame_pointer_needed)
12902 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
12903 stack_pointer_rtx));
12904 RTX_FRAME_RELATED_P (insn) = 1;
12907 live_regs_mask = thumb_compute_save_reg_mask ();
12908 amount = offsets->outgoing_args - offsets->saved_regs;
12913 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12914 GEN_INT (- amount)));
12915 RTX_FRAME_RELATED_P (insn) = 1;
12921 /* The stack decrement is too big for an immediate value in a single
12922 insn. In theory we could issue multiple subtracts, but after
12923 three of them it becomes more space efficient to place the full
12924 value in the constant pool and load into a register. (Also the
12925 ARM debugger really likes to see only one stack decrement per
12926 function). So instead we look for a scratch register into which
12927 we can load the decrement, and then we subtract this from the
12928 stack pointer. Unfortunately on the thumb the only available
12929 scratch registers are the argument registers, and we cannot use
12930 these as they may hold arguments to the function. Instead we
12931 attempt to locate a call preserved register which is used by this
12932 function. If we can find one, then we know that it will have
12933 been pushed at the start of the prologue and so we can corrupt
12935 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
12936 if (live_regs_mask & (1 << regno)
12937 && !(frame_pointer_needed
12938 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
12941 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
12943 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
12945 /* Choose an arbitrary, non-argument low register. */
12946 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
12948 /* Save it by copying it into a high, scratch register. */
12949 emit_insn (gen_movsi (spare, reg));
12950 /* Add a USE to stop propagate_one_insn() from barfing. */
12951 emit_insn (gen_prologue_use (spare));
12953 /* Decrement the stack. */
12954 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12955 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12956 stack_pointer_rtx, reg));
12957 RTX_FRAME_RELATED_P (insn) = 1;
12958 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12959 plus_constant (stack_pointer_rtx,
12961 RTX_FRAME_RELATED_P (dwarf) = 1;
12963 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12966 /* Restore the low register's original value. */
12967 emit_insn (gen_movsi (reg, spare));
12969 /* Emit a USE of the restored scratch register, so that flow
12970 analysis will not consider the restore redundant. The
12971 register won't be used again in this function and isn't
12972 restored by the epilogue. */
12973 emit_insn (gen_prologue_use (reg));
12977 reg = gen_rtx_REG (SImode, regno);
12979 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12981 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12982 stack_pointer_rtx, reg));
12983 RTX_FRAME_RELATED_P (insn) = 1;
12984 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12985 plus_constant (stack_pointer_rtx,
12987 RTX_FRAME_RELATED_P (dwarf) = 1;
12989 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12993 /* If the frame pointer is needed, emit a special barrier that
12994 will prevent the scheduler from moving stores to the frame
12995 before the stack adjustment. */
12996 if (frame_pointer_needed)
12997 emit_insn (gen_stack_tie (stack_pointer_rtx,
12998 hard_frame_pointer_rtx));
13001 if (current_function_profile || TARGET_NO_SCHED_PRO)
13002 emit_insn (gen_blockage ());
13004 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13005 if (live_regs_mask & 0xff)
13006 cfun->machine->lr_save_eliminated = 0;
13008 /* If the link register is being kept alive, with the return address in it,
13009 then make sure that it does not get reused by the ce2 pass. */
13010 if (cfun->machine->lr_save_eliminated)
13011 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13016 thumb_expand_epilogue (void)
13018 HOST_WIDE_INT amount;
13019 arm_stack_offsets *offsets;
13022 /* Naked functions don't have prologues. */
13023 if (IS_NAKED (arm_current_func_type ()))
13026 offsets = arm_get_frame_offsets ();
13027 amount = offsets->outgoing_args - offsets->saved_regs;
13029 if (frame_pointer_needed)
13030 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13034 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13035 GEN_INT (amount)));
13038 /* r3 is always free in the epilogue. */
13039 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13041 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13042 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13046 /* Emit a USE (stack_pointer_rtx), so that
13047 the stack adjustment will not be deleted. */
13048 emit_insn (gen_prologue_use (stack_pointer_rtx));
13050 if (current_function_profile || TARGET_NO_SCHED_PRO)
13051 emit_insn (gen_blockage ());
13053 /* Emit a clobber for each insn that will be restored in the epilogue,
13054 so that flow2 will get register lifetimes correct. */
13055 for (regno = 0; regno < 13; regno++)
13056 if (regs_ever_live[regno] && !call_used_regs[regno])
13057 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13059 if (! regs_ever_live[LR_REGNUM])
13060 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13064 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13066 int live_regs_mask = 0;
13068 int high_regs_pushed = 0;
13069 int cfa_offset = 0;
13072 if (IS_NAKED (arm_current_func_type ()))
13075 if (is_called_in_ARM_mode (current_function_decl))
13079 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13081 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13083 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13085 /* Generate code sequence to switch us into Thumb mode. */
13086 /* The .code 32 directive has already been emitted by
13087 ASM_DECLARE_FUNCTION_NAME. */
13088 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13089 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13091 /* Generate a label, so that the debugger will notice the
13092 change in instruction sets. This label is also used by
13093 the assembler to bypass the ARM code when this function
13094 is called from a Thumb encoded function elsewhere in the
13095 same file. Hence the definition of STUB_NAME here must
13096 agree with the definition in gas/config/tc-arm.c. */
13098 #define STUB_NAME ".real_start_of"
13100 fprintf (f, "\t.code\t16\n");
13102 if (arm_dllexport_name_p (name))
13103 name = arm_strip_name_encoding (name);
13105 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13106 fprintf (f, "\t.thumb_func\n");
13107 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13110 if (current_function_pretend_args_size)
13112 if (cfun->machine->uses_anonymous_args)
13116 fprintf (f, "\tpush\t{");
13118 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13120 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13121 regno <= LAST_ARG_REGNUM;
13123 asm_fprintf (f, "%r%s", regno,
13124 regno == LAST_ARG_REGNUM ? "" : ", ");
13126 fprintf (f, "}\n");
13129 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13130 SP_REGNUM, SP_REGNUM,
13131 current_function_pretend_args_size);
13133 /* We don't need to record the stores for unwinding (would it
13134 help the debugger any if we did?), but record the change in
13135 the stack pointer. */
13136 if (dwarf2out_do_frame ())
13138 char *l = dwarf2out_cfi_label ();
13139 cfa_offset = cfa_offset + current_function_pretend_args_size;
13140 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13144 live_regs_mask = thumb_compute_save_reg_mask ();
13145 /* Just low regs and lr. */
13146 l_mask = live_regs_mask & 0x40ff;
13148 if (TARGET_BACKTRACE)
13153 /* We have been asked to create a stack backtrace structure.
13154 The code looks like this:
13158 0 sub SP, #16 Reserve space for 4 registers.
13159 2 push {R7} Push low registers.
13160 4 add R7, SP, #20 Get the stack pointer before the push.
13161 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13162 8 mov R7, PC Get hold of the start of this code plus 12.
13163 10 str R7, [SP, #16] Store it.
13164 12 mov R7, FP Get hold of the current frame pointer.
13165 14 str R7, [SP, #4] Store it.
13166 16 mov R7, LR Get hold of the current return address.
13167 18 str R7, [SP, #12] Store it.
13168 20 add R7, SP, #16 Point at the start of the backtrace structure.
13169 22 mov FP, R7 Put this value into the frame pointer. */
13171 work_register = thumb_find_work_register (live_regs_mask);
13174 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13175 SP_REGNUM, SP_REGNUM);
13177 if (dwarf2out_do_frame ())
13179 char *l = dwarf2out_cfi_label ();
13180 cfa_offset = cfa_offset + 16;
13181 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13186 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13187 offset = bit_count (l_mask);
13192 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13193 offset + 16 + current_function_pretend_args_size);
13195 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13198 /* Make sure that the instruction fetching the PC is in the right place
13199 to calculate "start of backtrace creation code + 12". */
13202 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13203 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13205 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13206 ARM_HARD_FRAME_POINTER_REGNUM);
13207 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13212 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13213 ARM_HARD_FRAME_POINTER_REGNUM);
13214 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13216 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13217 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13221 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13222 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13224 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13226 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13227 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13230 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13232 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13234 if (high_regs_pushed)
13236 int pushable_regs = 0;
13239 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13240 if (live_regs_mask & (1 << next_hi_reg))
13243 pushable_regs = l_mask & 0xff;
13245 if (pushable_regs == 0)
13246 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13248 while (high_regs_pushed > 0)
13250 int real_regs_mask = 0;
13252 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13254 if (pushable_regs & (1 << regno))
13256 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13258 high_regs_pushed--;
13259 real_regs_mask |= (1 << next_hi_reg);
13261 if (high_regs_pushed)
13263 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13265 if (live_regs_mask & (1 << next_hi_reg))
13270 pushable_regs &= ~((1 << regno) - 1);
13276 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13281 /* Handle the case of a double word load into a low register from
13282 a computed memory address. The computed address may involve a
13283 register which is overwritten by the load. */
13285 thumb_load_double_from_address (rtx *operands)
13293 if (GET_CODE (operands[0]) != REG)
13296 if (GET_CODE (operands[1]) != MEM)
13299 /* Get the memory address. */
13300 addr = XEXP (operands[1], 0);
13302 /* Work out how the memory address is computed. */
13303 switch (GET_CODE (addr))
13306 operands[2] = gen_rtx_MEM (SImode,
13307 plus_constant (XEXP (operands[1], 0), 4));
13309 if (REGNO (operands[0]) == REGNO (addr))
13311 output_asm_insn ("ldr\t%H0, %2", operands);
13312 output_asm_insn ("ldr\t%0, %1", operands);
13316 output_asm_insn ("ldr\t%0, %1", operands);
13317 output_asm_insn ("ldr\t%H0, %2", operands);
13322 /* Compute <address> + 4 for the high order load. */
13323 operands[2] = gen_rtx_MEM (SImode,
13324 plus_constant (XEXP (operands[1], 0), 4));
13326 output_asm_insn ("ldr\t%0, %1", operands);
13327 output_asm_insn ("ldr\t%H0, %2", operands);
13331 arg1 = XEXP (addr, 0);
13332 arg2 = XEXP (addr, 1);
13334 if (CONSTANT_P (arg1))
13335 base = arg2, offset = arg1;
13337 base = arg1, offset = arg2;
13339 if (GET_CODE (base) != REG)
13342 /* Catch the case of <address> = <reg> + <reg> */
13343 if (GET_CODE (offset) == REG)
13345 int reg_offset = REGNO (offset);
13346 int reg_base = REGNO (base);
13347 int reg_dest = REGNO (operands[0]);
13349 /* Add the base and offset registers together into the
13350 higher destination register. */
13351 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13352 reg_dest + 1, reg_base, reg_offset);
13354 /* Load the lower destination register from the address in
13355 the higher destination register. */
13356 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13357 reg_dest, reg_dest + 1);
13359 /* Load the higher destination register from its own address
13361 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13362 reg_dest + 1, reg_dest + 1);
13366 /* Compute <address> + 4 for the high order load. */
13367 operands[2] = gen_rtx_MEM (SImode,
13368 plus_constant (XEXP (operands[1], 0), 4));
13370 /* If the computed address is held in the low order register
13371 then load the high order register first, otherwise always
13372 load the low order register first. */
13373 if (REGNO (operands[0]) == REGNO (base))
13375 output_asm_insn ("ldr\t%H0, %2", operands);
13376 output_asm_insn ("ldr\t%0, %1", operands);
13380 output_asm_insn ("ldr\t%0, %1", operands);
13381 output_asm_insn ("ldr\t%H0, %2", operands);
13387 /* With no registers to worry about we can just load the value
13389 operands[2] = gen_rtx_MEM (SImode,
13390 plus_constant (XEXP (operands[1], 0), 4));
13392 output_asm_insn ("ldr\t%H0, %2", operands);
13393 output_asm_insn ("ldr\t%0, %1", operands);
13405 thumb_output_move_mem_multiple (int n, rtx *operands)
13412 if (REGNO (operands[4]) > REGNO (operands[5]))
13415 operands[4] = operands[5];
13418 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13419 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13423 if (REGNO (operands[4]) > REGNO (operands[5]))
13426 operands[4] = operands[5];
13429 if (REGNO (operands[5]) > REGNO (operands[6]))
13432 operands[5] = operands[6];
13435 if (REGNO (operands[4]) > REGNO (operands[5]))
13438 operands[4] = operands[5];
13442 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13443 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13453 /* Routines for generating rtl. */
13455 thumb_expand_movmemqi (rtx *operands)
13457 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13458 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13459 HOST_WIDE_INT len = INTVAL (operands[2]);
13460 HOST_WIDE_INT offset = 0;
13464 emit_insn (gen_movmem12b (out, in, out, in));
13470 emit_insn (gen_movmem8b (out, in, out, in));
13476 rtx reg = gen_reg_rtx (SImode);
13477 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13478 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13485 rtx reg = gen_reg_rtx (HImode);
13486 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13487 plus_constant (in, offset))));
13488 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13496 rtx reg = gen_reg_rtx (QImode);
13497 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13498 plus_constant (in, offset))));
13499 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13505 thumb_reload_out_hi (rtx *operands)
13507 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13510 /* Handle reading a half-word from memory during reload. */
13512 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13517 /* Return the length of a function name prefix
13518 that starts with the character 'c'. */
13520 arm_get_strip_length (int c)
13524 ARM_NAME_ENCODING_LENGTHS
13529 /* Return a pointer to a function's name with any
13530 and all prefix encodings stripped from it. */
13532 arm_strip_name_encoding (const char *name)
13536 while ((skip = arm_get_strip_length (* name)))
13542 /* If there is a '*' anywhere in the name's prefix, then
13543 emit the stripped name verbatim, otherwise prepend an
13544 underscore if leading underscores are being used. */
13546 arm_asm_output_labelref (FILE *stream, const char *name)
13551 while ((skip = arm_get_strip_length (* name)))
13553 verbatim |= (*name == '*');
13558 fputs (name, stream);
13560 asm_fprintf (stream, "%U%s", name);
13565 #ifdef AOF_ASSEMBLER
13566 /* Special functions only needed when producing AOF syntax assembler. */
13570 struct pic_chain * next;
13571 const char * symname;
13574 static struct pic_chain * aof_pic_chain = NULL;
13577 aof_pic_entry (rtx x)
13579 struct pic_chain ** chainp;
13582 if (aof_pic_label == NULL_RTX)
13584 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13587 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13588 offset += 4, chainp = &(*chainp)->next)
13589 if ((*chainp)->symname == XSTR (x, 0))
13590 return plus_constant (aof_pic_label, offset);
13592 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13593 (*chainp)->next = NULL;
13594 (*chainp)->symname = XSTR (x, 0);
13595 return plus_constant (aof_pic_label, offset);
13599 aof_dump_pic_table (FILE *f)
13601 struct pic_chain * chain;
13603 if (aof_pic_chain == NULL)
13606 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13607 PIC_OFFSET_TABLE_REGNUM,
13608 PIC_OFFSET_TABLE_REGNUM);
13609 fputs ("|x$adcons|\n", f);
13611 for (chain = aof_pic_chain; chain; chain = chain->next)
13613 fputs ("\tDCD\t", f);
13614 assemble_name (f, chain->symname);
13619 int arm_text_section_count = 1;
13622 aof_text_section (void )
13624 static char buf[100];
13625 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13626 arm_text_section_count++);
13628 strcat (buf, ", PIC, REENTRANT");
13632 static int arm_data_section_count = 1;
13635 aof_data_section (void)
13637 static char buf[100];
13638 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13642 /* The AOF assembler is religiously strict about declarations of
13643 imported and exported symbols, so that it is impossible to declare
13644 a function as imported near the beginning of the file, and then to
13645 export it later on. It is, however, possible to delay the decision
13646 until all the functions in the file have been compiled. To get
13647 around this, we maintain a list of the imports and exports, and
13648 delete from it any that are subsequently defined. At the end of
13649 compilation we spit the remainder of the list out before the END
13654 struct import * next;
13658 static struct import * imports_list = NULL;
13661 aof_add_import (const char *name)
13663 struct import * new;
13665 for (new = imports_list; new; new = new->next)
13666 if (new->name == name)
13669 new = (struct import *) xmalloc (sizeof (struct import));
13670 new->next = imports_list;
13671 imports_list = new;
13676 aof_delete_import (const char *name)
13678 struct import ** old;
13680 for (old = &imports_list; *old; old = & (*old)->next)
13682 if ((*old)->name == name)
13684 *old = (*old)->next;
13690 int arm_main_function = 0;
13693 aof_dump_imports (FILE *f)
13695 /* The AOF assembler needs this to cause the startup code to be extracted
13696 from the library. Brining in __main causes the whole thing to work
13698 if (arm_main_function)
13701 fputs ("\tIMPORT __main\n", f);
13702 fputs ("\tDCD __main\n", f);
13705 /* Now dump the remaining imports. */
13706 while (imports_list)
13708 fprintf (f, "\tIMPORT\t");
13709 assemble_name (f, imports_list->name);
13711 imports_list = imports_list->next;
13716 aof_globalize_label (FILE *stream, const char *name)
13718 default_globalize_label (stream, name);
13719 if (! strcmp (name, "main"))
13720 arm_main_function = 1;
13724 aof_file_start (void)
13726 fputs ("__r0\tRN\t0\n", asm_out_file);
13727 fputs ("__a1\tRN\t0\n", asm_out_file);
13728 fputs ("__a2\tRN\t1\n", asm_out_file);
13729 fputs ("__a3\tRN\t2\n", asm_out_file);
13730 fputs ("__a4\tRN\t3\n", asm_out_file);
13731 fputs ("__v1\tRN\t4\n", asm_out_file);
13732 fputs ("__v2\tRN\t5\n", asm_out_file);
13733 fputs ("__v3\tRN\t6\n", asm_out_file);
13734 fputs ("__v4\tRN\t7\n", asm_out_file);
13735 fputs ("__v5\tRN\t8\n", asm_out_file);
13736 fputs ("__v6\tRN\t9\n", asm_out_file);
13737 fputs ("__sl\tRN\t10\n", asm_out_file);
13738 fputs ("__fp\tRN\t11\n", asm_out_file);
13739 fputs ("__ip\tRN\t12\n", asm_out_file);
13740 fputs ("__sp\tRN\t13\n", asm_out_file);
13741 fputs ("__lr\tRN\t14\n", asm_out_file);
13742 fputs ("__pc\tRN\t15\n", asm_out_file);
13743 fputs ("__f0\tFN\t0\n", asm_out_file);
13744 fputs ("__f1\tFN\t1\n", asm_out_file);
13745 fputs ("__f2\tFN\t2\n", asm_out_file);
13746 fputs ("__f3\tFN\t3\n", asm_out_file);
13747 fputs ("__f4\tFN\t4\n", asm_out_file);
13748 fputs ("__f5\tFN\t5\n", asm_out_file);
13749 fputs ("__f6\tFN\t6\n", asm_out_file);
13750 fputs ("__f7\tFN\t7\n", asm_out_file);
13755 aof_file_end (void)
13758 aof_dump_pic_table (asm_out_file);
13759 aof_dump_imports (asm_out_file);
13760 fputs ("\tEND\n", asm_out_file);
13762 #endif /* AOF_ASSEMBLER */
13764 #ifdef OBJECT_FORMAT_ELF
13765 /* Switch to an arbitrary section NAME with attributes as specified
13766 by FLAGS. ALIGN specifies any known alignment requirements for
13767 the section; 0 if the default should be used.
13769 Differs from the default elf version only in the prefix character
13770 used before the section type. */
13773 arm_elf_asm_named_section (const char *name, unsigned int flags)
13775 char flagchars[10], *f = flagchars;
13777 if (! named_section_first_declaration (name))
13779 fprintf (asm_out_file, "\t.section\t%s\n", name);
13783 if (!(flags & SECTION_DEBUG))
13785 if (flags & SECTION_WRITE)
13787 if (flags & SECTION_CODE)
13789 if (flags & SECTION_SMALL)
13791 if (flags & SECTION_MERGE)
13793 if (flags & SECTION_STRINGS)
13795 if (flags & SECTION_TLS)
13799 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
13801 if (!(flags & SECTION_NOTYPE))
13805 if (flags & SECTION_BSS)
13810 fprintf (asm_out_file, ",%%%s", type);
13812 if (flags & SECTION_ENTSIZE)
13813 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
13816 putc ('\n', asm_out_file);
13821 /* Symbols in the text segment can be accessed without indirecting via the
13822 constant pool; it may take an extra binary operation, but this is still
13823 faster than indirecting via memory. Don't do this when not optimizing,
13824 since we won't be calculating al of the offsets necessary to do this
13828 arm_encode_section_info (tree decl, rtx rtl, int first)
13830 /* This doesn't work with AOF syntax, since the string table may be in
13831 a different AREA. */
13832 #ifndef AOF_ASSEMBLER
13833 if (optimize > 0 && TREE_CONSTANT (decl))
13834 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13837 /* If we are referencing a function that is weak then encode a long call
13838 flag in the function name, otherwise if the function is static or
13839 or known to be defined in this file then encode a short call flag. */
13840 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
13842 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13843 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13844 else if (! TREE_PUBLIC (decl))
13845 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13848 #endif /* !ARM_PE */
13851 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13853 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13854 && !strcmp (prefix, "L"))
13856 arm_ccfsm_state = 0;
13857 arm_target_insn = NULL;
13859 default_internal_label (stream, prefix, labelno);
13862 /* Output code to add DELTA to the first argument, and then jump
13863 to FUNCTION. Used for C++ multiple inheritance. */
13865 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13866 HOST_WIDE_INT delta,
13867 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13870 static int thunk_label = 0;
13872 int mi_delta = delta;
13873 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13875 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13878 mi_delta = - mi_delta;
13881 int labelno = thunk_label++;
13882 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
13883 fputs ("\tldr\tr12, ", file);
13884 assemble_name (file, label);
13885 fputc ('\n', file);
13887 while (mi_delta != 0)
13889 if ((mi_delta & (3 << shift)) == 0)
13893 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
13894 mi_op, this_regno, this_regno,
13895 mi_delta & (0xff << shift));
13896 mi_delta &= ~(0xff << shift);
13902 fprintf (file, "\tbx\tr12\n");
13903 ASM_OUTPUT_ALIGN (file, 2);
13904 assemble_name (file, label);
13905 fputs (":\n", file);
13906 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
13910 fputs ("\tb\t", file);
13911 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
13912 if (NEED_PLT_RELOC)
13913 fputs ("(PLT)", file);
13914 fputc ('\n', file);
13919 arm_emit_vector_const (FILE *file, rtx x)
13922 const char * pattern;
13924 if (GET_CODE (x) != CONST_VECTOR)
13927 switch (GET_MODE (x))
13929 case V2SImode: pattern = "%08x"; break;
13930 case V4HImode: pattern = "%04x"; break;
13931 case V8QImode: pattern = "%02x"; break;
13935 fprintf (file, "0x");
13936 for (i = CONST_VECTOR_NUNITS (x); i--;)
13940 element = CONST_VECTOR_ELT (x, i);
13941 fprintf (file, pattern, INTVAL (element));
13948 arm_output_load_gr (rtx *operands)
13955 if (GET_CODE (operands [1]) != MEM
13956 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
13957 || GET_CODE (reg = XEXP (sum, 0)) != REG
13958 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
13959 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
13960 return "wldrw%?\t%0, %1";
13962 /* Fix up an out-of-range load of a GR register. */
13963 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
13964 wcgr = operands[0];
13966 output_asm_insn ("ldr%?\t%0, %1", operands);
13968 operands[0] = wcgr;
13970 output_asm_insn ("tmcr%?\t%0, %1", operands);
13971 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
13977 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
13978 int incoming ATTRIBUTE_UNUSED)
13981 /* FIXME: The ARM backend has special code to handle structure
13982 returns, and will reserve its own hidden first argument. So
13983 if this macro is enabled a *second* hidden argument will be
13984 reserved, which will break binary compatibility with old
13985 toolchains and also thunk handling. One day this should be
13989 /* Register in which address to store a structure value
13990 is passed to a function. */
13991 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
13995 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
13997 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
13998 named arg and all anonymous args onto the stack.
13999 XXX I know the prologue shouldn't be pushing registers, but it is faster
14003 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14004 enum machine_mode mode ATTRIBUTE_UNUSED,
14005 tree type ATTRIBUTE_UNUSED,
14007 int second_time ATTRIBUTE_UNUSED)
14009 cfun->machine->uses_anonymous_args = 1;
14010 if (cum->nregs < NUM_ARG_REGS)
14011 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14014 /* Return nonzero if the CONSUMER instruction (a store) does not need
14015 PRODUCER's value to calculate the address. */
14018 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14020 rtx value = PATTERN (producer);
14021 rtx addr = PATTERN (consumer);
14023 if (GET_CODE (value) == COND_EXEC)
14024 value = COND_EXEC_CODE (value);
14025 if (GET_CODE (value) == PARALLEL)
14026 value = XVECEXP (value, 0, 0);
14027 value = XEXP (value, 0);
14028 if (GET_CODE (addr) == COND_EXEC)
14029 addr = COND_EXEC_CODE (addr);
14030 if (GET_CODE (addr) == PARALLEL)
14031 addr = XVECEXP (addr, 0, 0);
14032 addr = XEXP (addr, 0);
14034 return !reg_overlap_mentioned_p (value, addr);
14037 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14038 have an early register shift value or amount dependency on the
14039 result of PRODUCER. */
14042 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14044 rtx value = PATTERN (producer);
14045 rtx op = PATTERN (consumer);
14048 if (GET_CODE (value) == COND_EXEC)
14049 value = COND_EXEC_CODE (value);
14050 if (GET_CODE (value) == PARALLEL)
14051 value = XVECEXP (value, 0, 0);
14052 value = XEXP (value, 0);
14053 if (GET_CODE (op) == COND_EXEC)
14054 op = COND_EXEC_CODE (op);
14055 if (GET_CODE (op) == PARALLEL)
14056 op = XVECEXP (op, 0, 0);
14059 early_op = XEXP (op, 0);
14060 /* This is either an actual independent shift, or a shift applied to
14061 the first operand of another operation. We want the whole shift
14063 if (GET_CODE (early_op) == REG)
14066 return !reg_overlap_mentioned_p (value, early_op);
14069 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14070 have an early register shift value dependency on the result of
14074 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14076 rtx value = PATTERN (producer);
14077 rtx op = PATTERN (consumer);
14080 if (GET_CODE (value) == COND_EXEC)
14081 value = COND_EXEC_CODE (value);
14082 if (GET_CODE (value) == PARALLEL)
14083 value = XVECEXP (value, 0, 0);
14084 value = XEXP (value, 0);
14085 if (GET_CODE (op) == COND_EXEC)
14086 op = COND_EXEC_CODE (op);
14087 if (GET_CODE (op) == PARALLEL)
14088 op = XVECEXP (op, 0, 0);
14091 early_op = XEXP (op, 0);
14093 /* This is either an actual independent shift, or a shift applied to
14094 the first operand of another operation. We want the value being
14095 shifted, in either case. */
14096 if (GET_CODE (early_op) != REG)
14097 early_op = XEXP (early_op, 0);
14099 return !reg_overlap_mentioned_p (value, early_op);
14102 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14103 have an early register mult dependency on the result of
14107 arm_no_early_mul_dep (rtx producer, rtx consumer)
14109 rtx value = PATTERN (producer);
14110 rtx op = PATTERN (consumer);
14112 if (GET_CODE (value) == COND_EXEC)
14113 value = COND_EXEC_CODE (value);
14114 if (GET_CODE (value) == PARALLEL)
14115 value = XVECEXP (value, 0, 0);
14116 value = XEXP (value, 0);
14117 if (GET_CODE (op) == COND_EXEC)
14118 op = COND_EXEC_CODE (op);
14119 if (GET_CODE (op) == PARALLEL)
14120 op = XVECEXP (op, 0, 0);
14123 return (GET_CODE (op) == PLUS
14124 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14128 /* We can't rely on the caller doing the proper promotion when
14129 using APCS or ATPCS. */
14132 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14134 return !TARGET_AAPCS_BASED;
14138 /* AAPCS based ABIs use short enums by default. */
14141 arm_default_short_enums (void)
14143 return TARGET_AAPCS_BASED;
14147 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14150 arm_align_anon_bitfield (void)
14152 return TARGET_AAPCS_BASED;
14156 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14159 arm_cxx_guard_type (void)
14161 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14165 /* The EABI says test the least significan bit of a guard variable. */
14168 arm_cxx_guard_mask_bit (void)
14170 return TARGET_AAPCS_BASED;
14174 /* The EABI specifies that all array cookies are 8 bytes long. */
14177 arm_get_cookie_size (tree type)
14181 if (!TARGET_AAPCS_BASED)
14182 return default_cxx_get_cookie_size (type);
14184 size = build_int_cst (sizetype, 8, 0);
14189 /* The EABI says that array cookies should also contain the element size. */
14192 arm_cookie_has_size (void)
14194 return TARGET_AAPCS_BASED;
14198 /* The EABI says constructors and destructors should return a pointer to
14199 the object constructed/destroyed. */
14202 arm_cxx_cdtor_returns_this (void)
14204 return TARGET_AAPCS_BASED;
14209 arm_set_return_address (rtx source, rtx scratch)
14211 arm_stack_offsets *offsets;
14212 HOST_WIDE_INT delta;
14214 unsigned long saved_regs;
14216 saved_regs = arm_compute_save_reg_mask ();
14218 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14219 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14222 if (frame_pointer_needed)
14223 addr = plus_constant(hard_frame_pointer_rtx, -4);
14226 /* LR will be the first saved register. */
14227 offsets = arm_get_frame_offsets ();
14228 delta = offsets->outgoing_args - (offsets->frame + 4);
14233 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14234 GEN_INT (delta & ~4095)));
14239 addr = stack_pointer_rtx;
14241 addr = plus_constant (addr, delta);
14243 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14249 thumb_set_return_address (rtx source, rtx scratch)
14251 arm_stack_offsets *offsets;
14252 HOST_WIDE_INT delta;
14255 unsigned long mask;
14257 emit_insn (gen_rtx_USE (VOIDmode, source));
14259 mask = thumb_compute_save_reg_mask ();
14260 if (mask & (1 << LR_REGNUM))
14262 offsets = arm_get_frame_offsets ();
14264 /* Find the saved regs. */
14265 if (frame_pointer_needed)
14267 delta = offsets->soft_frame - offsets->saved_args;
14268 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14272 delta = offsets->outgoing_args - offsets->saved_args;
14275 /* Allow for the stack frame. */
14276 if (TARGET_BACKTRACE)
14278 /* The link register is always the first saved register. */
14281 /* Construct the address. */
14282 addr = gen_rtx_REG (SImode, reg);
14283 if ((reg != SP_REGNUM && delta >= 128)
14286 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14287 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14291 addr = plus_constant (addr, delta);
14293 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14296 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14299 /* Implements target hook vector_mode_supported_p. */
14301 arm_vector_mode_supported_p (enum machine_mode mode)
14303 if ((mode == V2SImode)
14304 || (mode == V4HImode)
14305 || (mode == V8QImode))