1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
71 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
72 inline static int thumb1_index_register_rtx_p (rtx, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
77 static rtx emit_sfm (int, int);
78 static int arm_size_return_regs (void);
80 static bool arm_assemble_integer (rtx, unsigned int, int);
82 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
83 static arm_cc get_arm_condition_code (rtx);
84 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
85 static rtx is_jump_table (rtx);
86 static const char *output_multi_immediate (rtx *, const char *, const char *,
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree);
110 static unsigned long arm_compute_func_type (void);
111 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
113 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
114 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
116 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static int arm_comp_type_attributes (tree, tree);
120 static void arm_set_default_type_attributes (tree);
121 static int arm_adjust_cost (rtx, rtx, rtx, int);
122 static int count_insns_for_constant (HOST_WIDE_INT, int);
123 static int arm_get_strip_length (int);
124 static bool arm_function_ok_for_sibcall (tree, tree);
125 static void arm_internal_label (FILE *, const char *, unsigned long);
126 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
128 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
129 static bool arm_size_rtx_costs (rtx, int, int, int *);
130 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
133 static bool arm_9e_rtx_costs (rtx, int, int, int *);
134 static int arm_address_cost (rtx);
135 static bool arm_memory_load_p (rtx);
136 static bool arm_cirrus_insn_p (rtx);
137 static void cirrus_reorg (rtx);
138 static void arm_init_builtins (void);
139 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140 static void arm_init_iwmmxt_builtins (void);
141 static rtx safe_vector_operand (rtx, enum machine_mode);
142 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
143 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
144 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
145 static void emit_constant_insn (rtx cond, rtx pattern);
146 static rtx emit_set_insn (rtx, rtx);
147 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
150 #ifdef OBJECT_FORMAT_ELF
151 static void arm_elf_asm_constructor (rtx, int);
152 static void arm_elf_asm_destructor (rtx, int);
155 static void arm_encode_section_info (tree, rtx, int);
158 static void arm_file_end (void);
159 static void arm_file_start (void);
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
172 enum machine_mode, tree, bool);
173 static bool arm_promote_prototypes (tree);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree);
177 static bool arm_must_pass_in_stack (enum machine_mode, tree);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx);
180 static bool arm_output_ttype (rtx);
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
184 static tree arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree arm_get_cookie_size (tree);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
196 static bool arm_cannot_copy_insn_p (rtx);
197 static bool arm_tls_symbol_p (rtx x);
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
254 #undef TARGET_ENCODE_SECTION_INFO
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
380 struct gcc_target targetm = TARGET_INITIALIZER;
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack;
384 static char * minipool_startobj;
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped = 5;
390 extern FILE * asm_out_file;
392 /* True if we are currently building a constant table. */
393 int making_const_table;
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0, arm_compare_op1;
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune = arm_none;
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu = arm_none;
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model;
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch;
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune;
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi;
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi;
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer = TP_AUTO;
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label[14];
428 static int thumb_call_reg_needed;
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 #define FL_DIV (1 << 18) /* Hardware divide. */
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags = 0;
481 /* The bits in this mask specify which instruction scheduling options should
483 static unsigned long tune_flags = 0;
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
506 /* Nonzero if this chip supports the ARM 6K extensions. */
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm = 0;
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched = 0;
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm = 0;
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus = 0;
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt = 0;
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale = 0;
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale = 0;
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf = 0;
534 /* Nonzero if generating Thumb instructions. */
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork = 0;
544 /* Nonzero if chip supports Thumb 2. */
547 /* Nonzero if chip supports integer division instruction. */
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode;
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register = INVALID_REGNUM;
558 /* Set to 1 when a return insn is output, this means that the epilogue
560 int return_used_this_function;
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg = 0;
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit = 3;
569 /* For an explanation of these variables, see final_prescan_insn below. */
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc;
574 int arm_target_label;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count = 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask = 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen = 0;
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes[] =
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
597 /* Initialization code. */
601 const char *const name;
602 enum processor_type core;
604 const unsigned long flags;
605 bool (* rtx_costs) (rtx, int, int, int *);
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores[] =
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
617 {NULL, arm_none, NULL, 0, NULL}
620 static const struct processors all_architectures[] =
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
626 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
627 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
628 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
629 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
630 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
634 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
635 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
636 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
637 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
638 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
639 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
640 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
641 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
642 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
643 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
644 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
645 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
646 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
647 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
648 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
649 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
650 {NULL, arm_none, NULL, 0 , NULL}
653 struct arm_cpu_select
657 const struct processors * processors;
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
664 static struct arm_cpu_select arm_select[] =
666 /* string name processors */
667 { NULL, "-mcpu=", all_cores },
668 { NULL, "-march=", all_architectures },
669 { NULL, "-mtune=", all_cores }
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
677 /* The name of the preprocessor macro to define for this architecture. */
679 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
688 /* Available values for -mfpu=. */
690 static const struct fpu_desc all_fpus[] =
692 {"fpa", FPUTYPE_FPA},
693 {"fpe2", FPUTYPE_FPA_EMU2},
694 {"fpe3", FPUTYPE_FPA_EMU2},
695 {"maverick", FPUTYPE_MAVERICK},
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
703 static const enum fputype fp_model_for_fpu[] =
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
718 enum float_abi_type abi_type;
722 /* Available values for -mfloat-abi=. */
724 static const struct float_abi all_float_abis[] =
726 {"soft", ARM_FLOAT_ABI_SOFT},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP},
728 {"hard", ARM_FLOAT_ABI_HARD}
735 enum arm_abi_type abi_type;
739 /* Available values for -mabi=. */
741 static const struct abi_name arm_all_abis[] =
743 {"apcs-gnu", ARM_ABI_APCS},
744 {"atpcs", ARM_ABI_ATPCS},
745 {"aapcs", ARM_ABI_AAPCS},
746 {"iwmmxt", ARM_ABI_IWMMXT},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
750 /* Supported TLS relocations. */
760 /* Emit an insn that's a simple single-set. Both the operands must be known
763 emit_set_insn (rtx x, rtx y)
765 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
768 /* Return the number of bits set in VALUE. */
770 bit_count (unsigned long value)
772 unsigned long count = 0;
777 value &= value - 1; /* Clear the least-significant set bit. */
783 /* Set up library functions unique to ARM. */
786 arm_init_libfuncs (void)
788 /* There are no special library functions unless we are using the
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab, DFmode, NULL);
806 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab, SFmode, NULL);
822 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
875 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
878 /* For SImode division the ABI provides div-without-mod routines,
880 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab, DImode, NULL);
886 set_optab_libfunc (umod_optab, DImode, NULL);
887 set_optab_libfunc (smod_optab, SImode, NULL);
888 set_optab_libfunc (umod_optab, SImode, NULL);
891 /* Implement TARGET_HANDLE_OPTION. */
894 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
899 arm_select[1].string = arg;
903 arm_select[0].string = arg;
906 case OPT_mhard_float:
907 target_float_abi_name = "hard";
910 case OPT_msoft_float:
911 target_float_abi_name = "soft";
915 arm_select[2].string = arg;
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
926 arm_override_options (void)
929 enum processor_type target_arch_cpu = arm_none;
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i = ARRAY_SIZE (arm_select); i--;)
934 struct arm_cpu_select * ptr = arm_select + i;
936 if (ptr->string != NULL && ptr->string[0] != '\0')
938 const struct processors * sel;
940 for (sel = ptr->processors; sel->name != NULL; sel++)
941 if (streq (ptr->string, sel->name))
943 /* Set the architecture define. */
944 if (i != ARM_OPT_SET_TUNE)
945 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i == ARM_OPT_SET_TUNE)
953 arm_tune = (enum processor_type) (sel - ptr->processors);
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
959 if (i == ARM_OPT_SET_ARCH)
960 target_arch_cpu = sel->core;
962 if (i != ARM_OPT_SET_TUNE)
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
968 if (insn_flags != 0 && (insn_flags ^ sel->flags))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
972 insn_flags = sel->flags;
978 if (sel->name == NULL)
979 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune == arm_none)
985 arm_tune = target_arch_cpu;
987 /* If the user did not specify a processor, choose one for them. */
990 const struct processors * sel;
992 enum processor_type cpu;
994 cpu = TARGET_CPU_DEFAULT;
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
1000 cpu = SUBTARGET_CPU_DEFAULT;
1002 /* Default to ARM6. */
1003 if (cpu == arm_none)
1006 sel = &all_cores[cpu];
1008 insn_flags = sel->flags;
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1014 if (TARGET_INTERWORK || TARGET_THUMB)
1016 sought |= (FL_THUMB | FL_MODE32);
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags &= ~FL_MODE26;
1025 if (sought != 0 && ((sought & insn_flags) != sought))
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1030 for (sel = all_cores; sel->name != NULL; sel++)
1031 if ((sel->flags & sought) == (sought | insn_flags))
1034 if (sel->name == NULL)
1036 unsigned current_bit_count = 0;
1037 const struct processors * best_fit = NULL;
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel = all_cores; sel->name != NULL; sel++)
1051 if ((sel->flags & sought) == sought)
1055 count = bit_count (sel->flags & insn_flags);
1057 if (count >= current_bit_count)
1060 current_bit_count = count;
1064 gcc_assert (best_fit);
1068 insn_flags = sel->flags;
1070 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1071 arm_default_cpu = (enum processor_type) (sel - all_cores);
1072 if (arm_tune == arm_none)
1073 arm_tune = arm_default_cpu;
1076 /* The processor for which we should tune should now have been
1078 gcc_assert (arm_tune != arm_none);
1080 tune_flags = all_cores[(int)arm_tune].flags;
1082 targetm.rtx_costs = arm_size_rtx_costs;
1084 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1089 error ("target CPU does not support ARM mode");
1091 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags &= ~MASK_INTERWORK;
1097 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags &= ~MASK_THUMB;
1103 if (TARGET_APCS_FRAME && TARGET_THUMB)
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags &= ~MASK_APCS_FRAME;
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1112 target_flags |= MASK_INTERWORK;
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1119 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1122 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1125 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags |= MASK_APCS_FRAME;
1131 if (TARGET_POKE_FUNCTION_NAME)
1132 target_flags |= MASK_APCS_FRAME;
1134 if (TARGET_APCS_REENT && flag_pic)
1135 error ("-fpic and -mapcs-reent are incompatible");
1137 if (TARGET_APCS_REENT)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1143 && write_symbols != NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1148 if (TARGET_APCS_FLOAT)
1149 warning (0, "passing floating point arguments in fp regs not yet supported");
1151 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1152 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1153 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1154 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1155 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1156 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1157 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1158 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1159 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1160 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1161 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1162 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1164 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1165 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1166 thumb_code = (TARGET_ARM == 0);
1167 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1168 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1169 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1170 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1172 /* V5 code we generate is completely interworking capable, so we turn off
1173 TARGET_INTERWORK here to avoid many tests later on. */
1175 /* XXX However, we must pass the right pre-processor defines to CPP
1176 or GLD can get confused. This is a hack. */
1177 if (TARGET_INTERWORK)
1178 arm_cpp_interwork = 1;
1181 target_flags &= ~MASK_INTERWORK;
1183 if (target_abi_name)
1185 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1187 if (streq (arm_all_abis[i].name, target_abi_name))
1189 arm_abi = arm_all_abis[i].abi_type;
1193 if (i == ARRAY_SIZE (arm_all_abis))
1194 error ("invalid ABI option: -mabi=%s", target_abi_name);
1197 arm_abi = ARM_DEFAULT_ABI;
1199 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1200 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1202 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1203 error ("iwmmxt abi requires an iwmmxt capable cpu");
1205 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1206 if (target_fpu_name == NULL && target_fpe_name != NULL)
1208 if (streq (target_fpe_name, "2"))
1209 target_fpu_name = "fpe2";
1210 else if (streq (target_fpe_name, "3"))
1211 target_fpu_name = "fpe3";
1213 error ("invalid floating point emulation option: -mfpe=%s",
1216 if (target_fpu_name != NULL)
1218 /* The user specified a FPU. */
1219 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1221 if (streq (all_fpus[i].name, target_fpu_name))
1223 arm_fpu_arch = all_fpus[i].fpu;
1224 arm_fpu_tune = arm_fpu_arch;
1225 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1229 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1230 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1234 #ifdef FPUTYPE_DEFAULT
1235 /* Use the default if it is specified for this platform. */
1236 arm_fpu_arch = FPUTYPE_DEFAULT;
1237 arm_fpu_tune = FPUTYPE_DEFAULT;
1239 /* Pick one based on CPU type. */
1240 /* ??? Some targets assume FPA is the default.
1241 if ((insn_flags & FL_VFP) != 0)
1242 arm_fpu_arch = FPUTYPE_VFP;
1245 if (arm_arch_cirrus)
1246 arm_fpu_arch = FPUTYPE_MAVERICK;
1248 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1250 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1251 arm_fpu_tune = FPUTYPE_FPA;
1253 arm_fpu_tune = arm_fpu_arch;
1254 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1255 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1258 if (target_float_abi_name != NULL)
1260 /* The user specified a FP ABI. */
1261 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1263 if (streq (all_float_abis[i].name, target_float_abi_name))
1265 arm_float_abi = all_float_abis[i].abi_type;
1269 if (i == ARRAY_SIZE (all_float_abis))
1270 error ("invalid floating point abi: -mfloat-abi=%s",
1271 target_float_abi_name);
1274 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1276 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1277 sorry ("-mfloat-abi=hard and VFP");
1279 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1280 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1281 will ever exist. GCC makes no attempt to support this combination. */
1282 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1283 sorry ("iWMMXt and hardware floating point");
1285 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1286 if (TARGET_THUMB2 && TARGET_IWMMXT)
1287 sorry ("Thumb-2 iWMMXt");
1289 /* If soft-float is specified then don't use FPU. */
1290 if (TARGET_SOFT_FLOAT)
1291 arm_fpu_arch = FPUTYPE_NONE;
1293 /* For arm2/3 there is no need to do any scheduling if there is only
1294 a floating point emulator, or we are doing software floating-point. */
1295 if ((TARGET_SOFT_FLOAT
1296 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1297 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1298 && (tune_flags & FL_MODE32) == 0)
1299 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1301 if (target_thread_switch)
1303 if (strcmp (target_thread_switch, "soft") == 0)
1304 target_thread_pointer = TP_SOFT;
1305 else if (strcmp (target_thread_switch, "auto") == 0)
1306 target_thread_pointer = TP_AUTO;
1307 else if (strcmp (target_thread_switch, "cp15") == 0)
1308 target_thread_pointer = TP_CP15;
1310 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1313 /* Use the cp15 method if it is available. */
1314 if (target_thread_pointer == TP_AUTO)
1316 if (arm_arch6k && !TARGET_THUMB)
1317 target_thread_pointer = TP_CP15;
1319 target_thread_pointer = TP_SOFT;
1322 if (TARGET_HARD_TP && TARGET_THUMB1)
1323 error ("can not use -mtp=cp15 with 16-bit Thumb");
1325 /* Override the default structure alignment for AAPCS ABI. */
1326 if (TARGET_AAPCS_BASED)
1327 arm_structure_size_boundary = 8;
1329 if (structure_size_string != NULL)
1331 int size = strtol (structure_size_string, NULL, 0);
1333 if (size == 8 || size == 32
1334 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1335 arm_structure_size_boundary = size;
1337 warning (0, "structure size boundary can only be set to %s",
1338 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1341 /* If stack checking is disabled, we can use r10 as the PIC register,
1342 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1343 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1344 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1346 if (arm_pic_register_string != NULL)
1348 int pic_register = decode_reg_name (arm_pic_register_string);
1351 warning (0, "-mpic-register= is useless without -fpic");
1353 /* Prevent the user from choosing an obviously stupid PIC register. */
1354 else if (pic_register < 0 || call_used_regs[pic_register]
1355 || pic_register == HARD_FRAME_POINTER_REGNUM
1356 || pic_register == STACK_POINTER_REGNUM
1357 || pic_register >= PC_REGNUM)
1358 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1360 arm_pic_register = pic_register;
1363 /* ??? We might want scheduling for thumb2. */
1364 if (TARGET_THUMB && flag_schedule_insns)
1366 /* Don't warn since it's on by default in -O2. */
1367 flag_schedule_insns = 0;
1372 arm_constant_limit = 1;
1374 /* If optimizing for size, bump the number of instructions that we
1375 are prepared to conditionally execute (even on a StrongARM). */
1376 max_insns_skipped = 6;
1380 /* For processors with load scheduling, it never costs more than
1381 2 cycles to load a constant, and the load scheduler may well
1382 reduce that to 1. */
1384 arm_constant_limit = 1;
1386 /* On XScale the longer latency of a load makes it more difficult
1387 to achieve a good schedule, so it's faster to synthesize
1388 constants that can be done in two insns. */
1389 if (arm_tune_xscale)
1390 arm_constant_limit = 2;
1392 /* StrongARM has early execution of branches, so a sequence
1393 that is worth skipping is shorter. */
1394 if (arm_tune_strongarm)
1395 max_insns_skipped = 3;
1398 /* Register global variables with the garbage collector. */
1399 arm_add_gc_roots ();
1403 arm_add_gc_roots (void)
1405 gcc_obstack_init(&minipool_obstack);
1406 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1409 /* A table of known ARM exception types.
1410 For use with the interrupt function attribute. */
1414 const char *const arg;
1415 const unsigned long return_value;
1419 static const isr_attribute_arg isr_attribute_args [] =
1421 { "IRQ", ARM_FT_ISR },
1422 { "irq", ARM_FT_ISR },
1423 { "FIQ", ARM_FT_FIQ },
1424 { "fiq", ARM_FT_FIQ },
1425 { "ABORT", ARM_FT_ISR },
1426 { "abort", ARM_FT_ISR },
1427 { "ABORT", ARM_FT_ISR },
1428 { "abort", ARM_FT_ISR },
1429 { "UNDEF", ARM_FT_EXCEPTION },
1430 { "undef", ARM_FT_EXCEPTION },
1431 { "SWI", ARM_FT_EXCEPTION },
1432 { "swi", ARM_FT_EXCEPTION },
1433 { NULL, ARM_FT_NORMAL }
1436 /* Returns the (interrupt) function type of the current
1437 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1439 static unsigned long
1440 arm_isr_value (tree argument)
1442 const isr_attribute_arg * ptr;
1446 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1448 /* No argument - default to IRQ. */
1449 if (argument == NULL_TREE)
1452 /* Get the value of the argument. */
1453 if (TREE_VALUE (argument) == NULL_TREE
1454 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1455 return ARM_FT_UNKNOWN;
1457 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1459 /* Check it against the list of known arguments. */
1460 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1461 if (streq (arg, ptr->arg))
1462 return ptr->return_value;
1464 /* An unrecognized interrupt type. */
1465 return ARM_FT_UNKNOWN;
1468 /* Computes the type of the current function. */
1470 static unsigned long
1471 arm_compute_func_type (void)
1473 unsigned long type = ARM_FT_UNKNOWN;
1477 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1479 /* Decide if the current function is volatile. Such functions
1480 never return, and many memory cycles can be saved by not storing
1481 register values that will never be needed again. This optimization
1482 was added to speed up context switching in a kernel application. */
1484 && (TREE_NOTHROW (current_function_decl)
1485 || !(flag_unwind_tables
1486 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1487 && TREE_THIS_VOLATILE (current_function_decl))
1488 type |= ARM_FT_VOLATILE;
1490 if (cfun->static_chain_decl != NULL)
1491 type |= ARM_FT_NESTED;
1493 attr = DECL_ATTRIBUTES (current_function_decl);
1495 a = lookup_attribute ("naked", attr);
1497 type |= ARM_FT_NAKED;
1499 a = lookup_attribute ("isr", attr);
1501 a = lookup_attribute ("interrupt", attr);
1504 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1506 type |= arm_isr_value (TREE_VALUE (a));
1511 /* Returns the type of the current function. */
1514 arm_current_func_type (void)
1516 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1517 cfun->machine->func_type = arm_compute_func_type ();
1519 return cfun->machine->func_type;
1522 /* Return 1 if it is possible to return using a single instruction.
1523 If SIBLING is non-null, this is a test for a return before a sibling
1524 call. SIBLING is the call insn, so we can examine its register usage. */
1527 use_return_insn (int iscond, rtx sibling)
1530 unsigned int func_type;
1531 unsigned long saved_int_regs;
1532 unsigned HOST_WIDE_INT stack_adjust;
1533 arm_stack_offsets *offsets;
1535 /* Never use a return instruction before reload has run. */
1536 if (!reload_completed)
1539 func_type = arm_current_func_type ();
1541 /* Naked, volatile and stack alignment functions need special
1543 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1546 /* So do interrupt functions that use the frame pointer and Thumb
1547 interrupt functions. */
1548 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1551 offsets = arm_get_frame_offsets ();
1552 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1554 /* As do variadic functions. */
1555 if (current_function_pretend_args_size
1556 || cfun->machine->uses_anonymous_args
1557 /* Or if the function calls __builtin_eh_return () */
1558 || current_function_calls_eh_return
1559 /* Or if the function calls alloca */
1560 || current_function_calls_alloca
1561 /* Or if there is a stack adjustment. However, if the stack pointer
1562 is saved on the stack, we can use a pre-incrementing stack load. */
1563 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1566 saved_int_regs = arm_compute_save_reg_mask ();
1568 /* Unfortunately, the insn
1570 ldmib sp, {..., sp, ...}
1572 triggers a bug on most SA-110 based devices, such that the stack
1573 pointer won't be correctly restored if the instruction takes a
1574 page fault. We work around this problem by popping r3 along with
1575 the other registers, since that is never slower than executing
1576 another instruction.
1578 We test for !arm_arch5 here, because code for any architecture
1579 less than this could potentially be run on one of the buggy
1581 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1583 /* Validate that r3 is a call-clobbered register (always true in
1584 the default abi) ... */
1585 if (!call_used_regs[3])
1588 /* ... that it isn't being used for a return value ... */
1589 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1592 /* ... or for a tail-call argument ... */
1595 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1597 if (find_regno_fusage (sibling, USE, 3))
1601 /* ... and that there are no call-saved registers in r0-r2
1602 (always true in the default ABI). */
1603 if (saved_int_regs & 0x7)
1607 /* Can't be done if interworking with Thumb, and any registers have been
1609 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1612 /* On StrongARM, conditional returns are expensive if they aren't
1613 taken and multiple registers have been stacked. */
1614 if (iscond && arm_tune_strongarm)
1616 /* Conditional return when just the LR is stored is a simple
1617 conditional-load instruction, that's not expensive. */
1618 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1622 && arm_pic_register != INVALID_REGNUM
1623 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1627 /* If there are saved registers but the LR isn't saved, then we need
1628 two instructions for the return. */
1629 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1632 /* Can't be done if any of the FPA regs are pushed,
1633 since this also requires an insn. */
1634 if (TARGET_HARD_FLOAT && TARGET_FPA)
1635 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1636 if (regs_ever_live[regno] && !call_used_regs[regno])
1639 /* Likewise VFP regs. */
1640 if (TARGET_HARD_FLOAT && TARGET_VFP)
1641 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1642 if (regs_ever_live[regno] && !call_used_regs[regno])
1645 if (TARGET_REALLY_IWMMXT)
1646 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1647 if (regs_ever_live[regno] && ! call_used_regs [regno])
1653 /* Return TRUE if int I is a valid immediate ARM constant. */
1656 const_ok_for_arm (HOST_WIDE_INT i)
1660 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1661 be all zero, or all one. */
1662 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1663 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1664 != ((~(unsigned HOST_WIDE_INT) 0)
1665 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1668 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1670 /* Fast return for 0 and small values. We must do this for zero, since
1671 the code below can't handle that one case. */
1672 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1675 /* Get the number of trailing zeros. */
1676 lowbit = ffs((int) i) - 1;
1678 /* Only even shifts are allowed in ARM mode so round down to the
1679 nearest even number. */
1683 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1688 /* Allow rotated constants in ARM mode. */
1690 && ((i & ~0xc000003f) == 0
1691 || (i & ~0xf000000f) == 0
1692 || (i & ~0xfc000003) == 0))
1699 /* Allow repeated pattern. */
1702 if (i == v || i == (v | (v << 8)))
1709 /* Return true if I is a valid constant for the operation CODE. */
1711 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1713 if (const_ok_for_arm (i))
1719 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1721 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1727 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1734 /* Emit a sequence of insns to handle a large constant.
1735 CODE is the code of the operation required, it can be any of SET, PLUS,
1736 IOR, AND, XOR, MINUS;
1737 MODE is the mode in which the operation is being performed;
1738 VAL is the integer to operate on;
1739 SOURCE is the other operand (a register, or a null-pointer for SET);
1740 SUBTARGETS means it is safe to create scratch registers if that will
1741 either produce a simpler sequence, or we will want to cse the values.
1742 Return value is the number of insns emitted. */
1744 /* ??? Tweak this for thumb2. */
1746 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1747 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1751 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1752 cond = COND_EXEC_TEST (PATTERN (insn));
1756 if (subtargets || code == SET
1757 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1758 && REGNO (target) != REGNO (source)))
1760 /* After arm_reorg has been called, we can't fix up expensive
1761 constants by pushing them into memory so we must synthesize
1762 them in-line, regardless of the cost. This is only likely to
1763 be more costly on chips that have load delay slots and we are
1764 compiling without running the scheduler (so no splitting
1765 occurred before the final instruction emission).
1767 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1769 if (!after_arm_reorg
1771 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1773 > arm_constant_limit + (code != SET)))
1777 /* Currently SET is the only monadic value for CODE, all
1778 the rest are diadic. */
1779 emit_set_insn (target, GEN_INT (val));
1784 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1786 emit_set_insn (temp, GEN_INT (val));
1787 /* For MINUS, the value is subtracted from, since we never
1788 have subtraction of a constant. */
1790 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1792 emit_set_insn (target,
1793 gen_rtx_fmt_ee (code, mode, source, temp));
1799 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1803 /* Return the number of ARM instructions required to synthesize the given
1806 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1808 HOST_WIDE_INT temp1;
1816 if (remainder & (3 << (i - 2)))
1821 temp1 = remainder & ((0x0ff << end)
1822 | ((i < end) ? (0xff >> (32 - end)) : 0));
1823 remainder &= ~temp1;
1828 } while (remainder);
1832 /* Emit an instruction with the indicated PATTERN. If COND is
1833 non-NULL, conditionalize the execution of the instruction on COND
1837 emit_constant_insn (rtx cond, rtx pattern)
1840 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1841 emit_insn (pattern);
1844 /* As above, but extra parameter GENERATE which, if clear, suppresses
1846 /* ??? This needs more work for thumb2. */
1849 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1850 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1855 int can_negate_initial = 0;
1858 int num_bits_set = 0;
1859 int set_sign_bit_copies = 0;
1860 int clear_sign_bit_copies = 0;
1861 int clear_zero_bit_copies = 0;
1862 int set_zero_bit_copies = 0;
1864 unsigned HOST_WIDE_INT temp1, temp2;
1865 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1867 /* Find out which operations are safe for a given CODE. Also do a quick
1868 check for degenerate cases; these can occur when DImode operations
1880 can_negate_initial = 1;
1884 if (remainder == 0xffffffff)
1887 emit_constant_insn (cond,
1888 gen_rtx_SET (VOIDmode, target,
1889 GEN_INT (ARM_SIGN_EXTEND (val))));
1894 if (reload_completed && rtx_equal_p (target, source))
1897 emit_constant_insn (cond,
1898 gen_rtx_SET (VOIDmode, target, source));
1907 emit_constant_insn (cond,
1908 gen_rtx_SET (VOIDmode, target, const0_rtx));
1911 if (remainder == 0xffffffff)
1913 if (reload_completed && rtx_equal_p (target, source))
1916 emit_constant_insn (cond,
1917 gen_rtx_SET (VOIDmode, target, source));
1926 if (reload_completed && rtx_equal_p (target, source))
1929 emit_constant_insn (cond,
1930 gen_rtx_SET (VOIDmode, target, source));
1934 /* We don't know how to handle other cases yet. */
1935 gcc_assert (remainder == 0xffffffff);
1938 emit_constant_insn (cond,
1939 gen_rtx_SET (VOIDmode, target,
1940 gen_rtx_NOT (mode, source)));
1944 /* We treat MINUS as (val - source), since (source - val) is always
1945 passed as (source + (-val)). */
1949 emit_constant_insn (cond,
1950 gen_rtx_SET (VOIDmode, target,
1951 gen_rtx_NEG (mode, source)));
1954 if (const_ok_for_arm (val))
1957 emit_constant_insn (cond,
1958 gen_rtx_SET (VOIDmode, target,
1959 gen_rtx_MINUS (mode, GEN_INT (val),
1971 /* If we can do it in one insn get out quickly. */
1972 if (const_ok_for_arm (val)
1973 || (can_negate_initial && const_ok_for_arm (-val))
1974 || (can_invert && const_ok_for_arm (~val)))
1977 emit_constant_insn (cond,
1978 gen_rtx_SET (VOIDmode, target,
1980 ? gen_rtx_fmt_ee (code, mode, source,
1986 /* Calculate a few attributes that may be useful for specific
1988 for (i = 31; i >= 0; i--)
1990 if ((remainder & (1 << i)) == 0)
1991 clear_sign_bit_copies++;
1996 for (i = 31; i >= 0; i--)
1998 if ((remainder & (1 << i)) != 0)
1999 set_sign_bit_copies++;
2004 for (i = 0; i <= 31; i++)
2006 if ((remainder & (1 << i)) == 0)
2007 clear_zero_bit_copies++;
2012 for (i = 0; i <= 31; i++)
2014 if ((remainder & (1 << i)) != 0)
2015 set_zero_bit_copies++;
2023 /* See if we can use movw. */
2024 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2027 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2032 /* See if we can do this by sign_extending a constant that is known
2033 to be negative. This is a good, way of doing it, since the shift
2034 may well merge into a subsequent insn. */
2035 if (set_sign_bit_copies > 1)
2037 if (const_ok_for_arm
2038 (temp1 = ARM_SIGN_EXTEND (remainder
2039 << (set_sign_bit_copies - 1))))
2043 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2044 emit_constant_insn (cond,
2045 gen_rtx_SET (VOIDmode, new_src,
2047 emit_constant_insn (cond,
2048 gen_ashrsi3 (target, new_src,
2049 GEN_INT (set_sign_bit_copies - 1)));
2053 /* For an inverted constant, we will need to set the low bits,
2054 these will be shifted out of harm's way. */
2055 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2056 if (const_ok_for_arm (~temp1))
2060 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2061 emit_constant_insn (cond,
2062 gen_rtx_SET (VOIDmode, new_src,
2064 emit_constant_insn (cond,
2065 gen_ashrsi3 (target, new_src,
2066 GEN_INT (set_sign_bit_copies - 1)));
2072 /* See if we can calculate the value as the difference between two
2073 valid immediates. */
2074 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2076 int topshift = clear_sign_bit_copies & ~1;
2078 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2079 & (0xff000000 >> topshift));
2081 /* If temp1 is zero, then that means the 9 most significant
2082 bits of remainder were 1 and we've caused it to overflow.
2083 When topshift is 0 we don't need to do anything since we
2084 can borrow from 'bit 32'. */
2085 if (temp1 == 0 && topshift != 0)
2086 temp1 = 0x80000000 >> (topshift - 1);
2088 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2090 if (const_ok_for_arm (temp2))
2094 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2095 emit_constant_insn (cond,
2096 gen_rtx_SET (VOIDmode, new_src,
2098 emit_constant_insn (cond,
2099 gen_addsi3 (target, new_src,
2107 /* See if we can generate this by setting the bottom (or the top)
2108 16 bits, and then shifting these into the other half of the
2109 word. We only look for the simplest cases, to do more would cost
2110 too much. Be careful, however, not to generate this when the
2111 alternative would take fewer insns. */
2112 if (val & 0xffff0000)
2114 temp1 = remainder & 0xffff0000;
2115 temp2 = remainder & 0x0000ffff;
2117 /* Overlaps outside this range are best done using other methods. */
2118 for (i = 9; i < 24; i++)
2120 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2121 && !const_ok_for_arm (temp2))
2123 rtx new_src = (subtargets
2124 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2126 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2127 source, subtargets, generate);
2135 gen_rtx_ASHIFT (mode, source,
2142 /* Don't duplicate cases already considered. */
2143 for (i = 17; i < 24; i++)
2145 if (((temp1 | (temp1 >> i)) == remainder)
2146 && !const_ok_for_arm (temp1))
2148 rtx new_src = (subtargets
2149 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2151 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2152 source, subtargets, generate);
2157 gen_rtx_SET (VOIDmode, target,
2160 gen_rtx_LSHIFTRT (mode, source,
2171 /* If we have IOR or XOR, and the constant can be loaded in a
2172 single instruction, and we can find a temporary to put it in,
2173 then this can be done in two instructions instead of 3-4. */
2175 /* TARGET can't be NULL if SUBTARGETS is 0 */
2176 || (reload_completed && !reg_mentioned_p (target, source)))
2178 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2182 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2184 emit_constant_insn (cond,
2185 gen_rtx_SET (VOIDmode, sub,
2187 emit_constant_insn (cond,
2188 gen_rtx_SET (VOIDmode, target,
2189 gen_rtx_fmt_ee (code, mode,
2199 if (set_sign_bit_copies > 8
2200 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2204 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2205 rtx shift = GEN_INT (set_sign_bit_copies);
2209 gen_rtx_SET (VOIDmode, sub,
2211 gen_rtx_ASHIFT (mode,
2216 gen_rtx_SET (VOIDmode, target,
2218 gen_rtx_LSHIFTRT (mode, sub,
2224 if (set_zero_bit_copies > 8
2225 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2229 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2230 rtx shift = GEN_INT (set_zero_bit_copies);
2234 gen_rtx_SET (VOIDmode, sub,
2236 gen_rtx_LSHIFTRT (mode,
2241 gen_rtx_SET (VOIDmode, target,
2243 gen_rtx_ASHIFT (mode, sub,
2249 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2253 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2254 emit_constant_insn (cond,
2255 gen_rtx_SET (VOIDmode, sub,
2256 gen_rtx_NOT (mode, source)));
2259 sub = gen_reg_rtx (mode);
2260 emit_constant_insn (cond,
2261 gen_rtx_SET (VOIDmode, sub,
2262 gen_rtx_AND (mode, source,
2264 emit_constant_insn (cond,
2265 gen_rtx_SET (VOIDmode, target,
2266 gen_rtx_NOT (mode, sub)));
2273 /* See if two shifts will do 2 or more insn's worth of work. */
2274 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2276 HOST_WIDE_INT shift_mask = ((0xffffffff
2277 << (32 - clear_sign_bit_copies))
2280 if ((remainder | shift_mask) != 0xffffffff)
2284 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2285 insns = arm_gen_constant (AND, mode, cond,
2286 remainder | shift_mask,
2287 new_src, source, subtargets, 1);
2292 rtx targ = subtargets ? NULL_RTX : target;
2293 insns = arm_gen_constant (AND, mode, cond,
2294 remainder | shift_mask,
2295 targ, source, subtargets, 0);
2301 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2302 rtx shift = GEN_INT (clear_sign_bit_copies);
2304 emit_insn (gen_ashlsi3 (new_src, source, shift));
2305 emit_insn (gen_lshrsi3 (target, new_src, shift));
2311 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2313 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2315 if ((remainder | shift_mask) != 0xffffffff)
2319 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2321 insns = arm_gen_constant (AND, mode, cond,
2322 remainder | shift_mask,
2323 new_src, source, subtargets, 1);
2328 rtx targ = subtargets ? NULL_RTX : target;
2330 insns = arm_gen_constant (AND, mode, cond,
2331 remainder | shift_mask,
2332 targ, source, subtargets, 0);
2338 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2339 rtx shift = GEN_INT (clear_zero_bit_copies);
2341 emit_insn (gen_lshrsi3 (new_src, source, shift));
2342 emit_insn (gen_ashlsi3 (target, new_src, shift));
2354 for (i = 0; i < 32; i++)
2355 if (remainder & (1 << i))
2358 if (code == AND || (can_invert && num_bits_set > 16))
2359 remainder = (~remainder) & 0xffffffff;
2360 else if (code == PLUS && num_bits_set > 16)
2361 remainder = (-remainder) & 0xffffffff;
2368 /* Now try and find a way of doing the job in either two or three
2370 We start by looking for the largest block of zeros that are aligned on
2371 a 2-bit boundary, we then fill up the temps, wrapping around to the
2372 top of the word when we drop off the bottom.
2373 In the worst case this code should produce no more than four insns.
2374 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2375 best place to start. */
2377 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2383 int best_consecutive_zeros = 0;
2385 for (i = 0; i < 32; i += 2)
2387 int consecutive_zeros = 0;
2389 if (!(remainder & (3 << i)))
2391 while ((i < 32) && !(remainder & (3 << i)))
2393 consecutive_zeros += 2;
2396 if (consecutive_zeros > best_consecutive_zeros)
2398 best_consecutive_zeros = consecutive_zeros;
2399 best_start = i - consecutive_zeros;
2405 /* So long as it won't require any more insns to do so, it's
2406 desirable to emit a small constant (in bits 0...9) in the last
2407 insn. This way there is more chance that it can be combined with
2408 a later addressing insn to form a pre-indexed load or store
2409 operation. Consider:
2411 *((volatile int *)0xe0000100) = 1;
2412 *((volatile int *)0xe0000110) = 2;
2414 We want this to wind up as:
2418 str rB, [rA, #0x100]
2420 str rB, [rA, #0x110]
2422 rather than having to synthesize both large constants from scratch.
2424 Therefore, we calculate how many insns would be required to emit
2425 the constant starting from `best_start', and also starting from
2426 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2427 yield a shorter sequence, we may as well use zero. */
2429 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2430 && (count_insns_for_constant (remainder, 0) <=
2431 count_insns_for_constant (remainder, best_start)))
2435 /* Now start emitting the insns. */
2443 if (remainder & (3 << (i - 2)))
2448 temp1 = remainder & ((0x0ff << end)
2449 | ((i < end) ? (0xff >> (32 - end)) : 0));
2450 remainder &= ~temp1;
2454 rtx new_src, temp1_rtx;
2456 if (code == SET || code == MINUS)
2458 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2459 if (can_invert && code != MINUS)
2464 if (remainder && subtargets)
2465 new_src = gen_reg_rtx (mode);
2470 else if (can_negate)
2474 temp1 = trunc_int_for_mode (temp1, mode);
2475 temp1_rtx = GEN_INT (temp1);
2479 else if (code == MINUS)
2480 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2482 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2484 emit_constant_insn (cond,
2485 gen_rtx_SET (VOIDmode, new_src,
2495 else if (code == MINUS)
2504 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2517 /* Canonicalize a comparison so that we are more likely to recognize it.
2518 This can be done for a few constant compares, where we can make the
2519 immediate value easier to load. */
2522 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2525 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2526 unsigned HOST_WIDE_INT maxval;
2527 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2538 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2540 *op1 = GEN_INT (i + 1);
2541 return code == GT ? GE : LT;
2548 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2550 *op1 = GEN_INT (i - 1);
2551 return code == GE ? GT : LE;
2557 if (i != ~((unsigned HOST_WIDE_INT) 0)
2558 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2560 *op1 = GEN_INT (i + 1);
2561 return code == GTU ? GEU : LTU;
2568 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2570 *op1 = GEN_INT (i - 1);
2571 return code == GEU ? GTU : LEU;
2583 /* Define how to find the value returned by a function. */
2586 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2588 enum machine_mode mode;
2589 int unsignedp ATTRIBUTE_UNUSED;
2590 rtx r ATTRIBUTE_UNUSED;
2592 mode = TYPE_MODE (type);
2593 /* Promote integer types. */
2594 if (INTEGRAL_TYPE_P (type))
2595 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2597 /* Promotes small structs returned in a register to full-word size
2598 for big-endian AAPCS. */
2599 if (arm_return_in_msb (type))
2601 HOST_WIDE_INT size = int_size_in_bytes (type);
2602 if (size % UNITS_PER_WORD != 0)
2604 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2605 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2609 return LIBCALL_VALUE(mode);
2612 /* Determine the amount of memory needed to store the possible return
2613 registers of an untyped call. */
2615 arm_apply_result_size (void)
2621 if (TARGET_HARD_FLOAT_ABI)
2625 if (TARGET_MAVERICK)
2628 if (TARGET_IWMMXT_ABI)
2635 /* Decide whether a type should be returned in memory (true)
2636 or in a register (false). This is called by the macro
2637 RETURN_IN_MEMORY. */
2639 arm_return_in_memory (tree type)
2643 if (!AGGREGATE_TYPE_P (type) &&
2644 (TREE_CODE (type) != VECTOR_TYPE) &&
2645 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2646 /* All simple types are returned in registers.
2647 For AAPCS, complex types are treated the same as aggregates. */
2650 size = int_size_in_bytes (type);
2652 if (arm_abi != ARM_ABI_APCS)
2654 /* ATPCS and later return aggregate types in memory only if they are
2655 larger than a word (or are variable size). */
2656 return (size < 0 || size > UNITS_PER_WORD);
2659 /* To maximize backwards compatibility with previous versions of gcc,
2660 return vectors up to 4 words in registers. */
2661 if (TREE_CODE (type) == VECTOR_TYPE)
2662 return (size < 0 || size > (4 * UNITS_PER_WORD));
2664 /* For the arm-wince targets we choose to be compatible with Microsoft's
2665 ARM and Thumb compilers, which always return aggregates in memory. */
2667 /* All structures/unions bigger than one word are returned in memory.
2668 Also catch the case where int_size_in_bytes returns -1. In this case
2669 the aggregate is either huge or of variable size, and in either case
2670 we will want to return it via memory and not in a register. */
2671 if (size < 0 || size > UNITS_PER_WORD)
2674 if (TREE_CODE (type) == RECORD_TYPE)
2678 /* For a struct the APCS says that we only return in a register
2679 if the type is 'integer like' and every addressable element
2680 has an offset of zero. For practical purposes this means
2681 that the structure can have at most one non bit-field element
2682 and that this element must be the first one in the structure. */
2684 /* Find the first field, ignoring non FIELD_DECL things which will
2685 have been created by C++. */
2686 for (field = TYPE_FIELDS (type);
2687 field && TREE_CODE (field) != FIELD_DECL;
2688 field = TREE_CHAIN (field))
2692 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2694 /* Check that the first field is valid for returning in a register. */
2696 /* ... Floats are not allowed */
2697 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2700 /* ... Aggregates that are not themselves valid for returning in
2701 a register are not allowed. */
2702 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2705 /* Now check the remaining fields, if any. Only bitfields are allowed,
2706 since they are not addressable. */
2707 for (field = TREE_CHAIN (field);
2709 field = TREE_CHAIN (field))
2711 if (TREE_CODE (field) != FIELD_DECL)
2714 if (!DECL_BIT_FIELD_TYPE (field))
2721 if (TREE_CODE (type) == UNION_TYPE)
2725 /* Unions can be returned in registers if every element is
2726 integral, or can be returned in an integer register. */
2727 for (field = TYPE_FIELDS (type);
2729 field = TREE_CHAIN (field))
2731 if (TREE_CODE (field) != FIELD_DECL)
2734 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2737 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2743 #endif /* not ARM_WINCE */
2745 /* Return all other types in memory. */
2749 /* Indicate whether or not words of a double are in big-endian order. */
2752 arm_float_words_big_endian (void)
2754 if (TARGET_MAVERICK)
2757 /* For FPA, float words are always big-endian. For VFP, floats words
2758 follow the memory system mode. */
2766 return (TARGET_BIG_END ? 1 : 0);
2771 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2772 for a call to a function whose data type is FNTYPE.
2773 For a library call, FNTYPE is NULL. */
2775 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2776 rtx libname ATTRIBUTE_UNUSED,
2777 tree fndecl ATTRIBUTE_UNUSED)
2779 /* On the ARM, the offset starts at 0. */
2781 pcum->iwmmxt_nregs = 0;
2782 pcum->can_split = true;
2784 /* Varargs vectors are treated the same as long long.
2785 named_count avoids having to change the way arm handles 'named' */
2786 pcum->named_count = 0;
2789 if (TARGET_REALLY_IWMMXT && fntype)
2793 for (fn_arg = TYPE_ARG_TYPES (fntype);
2795 fn_arg = TREE_CHAIN (fn_arg))
2796 pcum->named_count += 1;
2798 if (! pcum->named_count)
2799 pcum->named_count = INT_MAX;
2804 /* Return true if mode/type need doubleword alignment. */
2806 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2808 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2809 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2813 /* Determine where to put an argument to a function.
2814 Value is zero to push the argument on the stack,
2815 or a hard register in which to store the argument.
2817 MODE is the argument's machine mode.
2818 TYPE is the data type of the argument (as a tree).
2819 This is null for libcalls where that information may
2821 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2822 the preceding args and about the function being called.
2823 NAMED is nonzero if this argument is a named parameter
2824 (otherwise it is an extra parameter matching an ellipsis). */
2827 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2828 tree type, int named)
2832 /* Varargs vectors are treated the same as long long.
2833 named_count avoids having to change the way arm handles 'named' */
2834 if (TARGET_IWMMXT_ABI
2835 && arm_vector_mode_supported_p (mode)
2836 && pcum->named_count > pcum->nargs + 1)
2838 if (pcum->iwmmxt_nregs <= 9)
2839 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2842 pcum->can_split = false;
2847 /* Put doubleword aligned quantities in even register pairs. */
2849 && ARM_DOUBLEWORD_ALIGN
2850 && arm_needs_doubleword_align (mode, type))
2853 if (mode == VOIDmode)
2854 /* Pick an arbitrary value for operand 2 of the call insn. */
2857 /* Only allow splitting an arg between regs and memory if all preceding
2858 args were allocated to regs. For args passed by reference we only count
2859 the reference pointer. */
2860 if (pcum->can_split)
2863 nregs = ARM_NUM_REGS2 (mode, type);
2865 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2868 return gen_rtx_REG (mode, pcum->nregs);
2872 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2873 tree type, bool named ATTRIBUTE_UNUSED)
2875 int nregs = pcum->nregs;
2877 if (arm_vector_mode_supported_p (mode))
2880 if (NUM_ARG_REGS > nregs
2881 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2883 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2888 /* Variable sized types are passed by reference. This is a GCC
2889 extension to the ARM ABI. */
2892 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2893 enum machine_mode mode ATTRIBUTE_UNUSED,
2894 tree type, bool named ATTRIBUTE_UNUSED)
2896 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2899 /* Encode the current state of the #pragma [no_]long_calls. */
2902 OFF, /* No #pragma [no_]long_calls is in effect. */
2903 LONG, /* #pragma long_calls is in effect. */
2904 SHORT /* #pragma no_long_calls is in effect. */
2907 static arm_pragma_enum arm_pragma_long_calls = OFF;
2910 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2912 arm_pragma_long_calls = LONG;
2916 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2918 arm_pragma_long_calls = SHORT;
2922 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2924 arm_pragma_long_calls = OFF;
2927 /* Table of machine attributes. */
2928 const struct attribute_spec arm_attribute_table[] =
2930 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2931 /* Function calls made to this symbol must be done indirectly, because
2932 it may lie outside of the 26 bit addressing range of a normal function
2934 { "long_call", 0, 0, false, true, true, NULL },
2935 /* Whereas these functions are always known to reside within the 26 bit
2936 addressing range. */
2937 { "short_call", 0, 0, false, true, true, NULL },
2938 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2939 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2940 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2941 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2943 /* ARM/PE has three new attributes:
2945 dllexport - for exporting a function/variable that will live in a dll
2946 dllimport - for importing a function/variable from a dll
2948 Microsoft allows multiple declspecs in one __declspec, separating
2949 them with spaces. We do NOT support this. Instead, use __declspec
2952 { "dllimport", 0, 0, true, false, false, NULL },
2953 { "dllexport", 0, 0, true, false, false, NULL },
2954 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2955 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2956 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2957 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2958 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2960 { NULL, 0, 0, false, false, false, NULL }
2963 /* Handle an attribute requiring a FUNCTION_DECL;
2964 arguments as in struct attribute_spec.handler. */
2966 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2967 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2969 if (TREE_CODE (*node) != FUNCTION_DECL)
2971 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2972 IDENTIFIER_POINTER (name));
2973 *no_add_attrs = true;
2979 /* Handle an "interrupt" or "isr" attribute;
2980 arguments as in struct attribute_spec.handler. */
2982 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2987 if (TREE_CODE (*node) != FUNCTION_DECL)
2989 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2990 IDENTIFIER_POINTER (name));
2991 *no_add_attrs = true;
2993 /* FIXME: the argument if any is checked for type attributes;
2994 should it be checked for decl ones? */
2998 if (TREE_CODE (*node) == FUNCTION_TYPE
2999 || TREE_CODE (*node) == METHOD_TYPE)
3001 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3003 warning (OPT_Wattributes, "%qs attribute ignored",
3004 IDENTIFIER_POINTER (name));
3005 *no_add_attrs = true;
3008 else if (TREE_CODE (*node) == POINTER_TYPE
3009 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3010 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3011 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3013 *node = build_variant_type_copy (*node);
3014 TREE_TYPE (*node) = build_type_attribute_variant
3016 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3017 *no_add_attrs = true;
3021 /* Possibly pass this attribute on from the type to a decl. */
3022 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3023 | (int) ATTR_FLAG_FUNCTION_NEXT
3024 | (int) ATTR_FLAG_ARRAY_NEXT))
3026 *no_add_attrs = true;
3027 return tree_cons (name, args, NULL_TREE);
3031 warning (OPT_Wattributes, "%qs attribute ignored",
3032 IDENTIFIER_POINTER (name));
3040 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3041 /* Handle the "notshared" attribute. This attribute is another way of
3042 requesting hidden visibility. ARM's compiler supports
3043 "__declspec(notshared)"; we support the same thing via an
3047 arm_handle_notshared_attribute (tree *node,
3048 tree name ATTRIBUTE_UNUSED,
3049 tree args ATTRIBUTE_UNUSED,
3050 int flags ATTRIBUTE_UNUSED,
3053 tree decl = TYPE_NAME (*node);
3057 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3058 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3059 *no_add_attrs = false;
3065 /* Return 0 if the attributes for two types are incompatible, 1 if they
3066 are compatible, and 2 if they are nearly compatible (which causes a
3067 warning to be generated). */
3069 arm_comp_type_attributes (tree type1, tree type2)
3073 /* Check for mismatch of non-default calling convention. */
3074 if (TREE_CODE (type1) != FUNCTION_TYPE)
3077 /* Check for mismatched call attributes. */
3078 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3079 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3080 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3081 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3083 /* Only bother to check if an attribute is defined. */
3084 if (l1 | l2 | s1 | s2)
3086 /* If one type has an attribute, the other must have the same attribute. */
3087 if ((l1 != l2) || (s1 != s2))
3090 /* Disallow mixed attributes. */
3091 if ((l1 & s2) || (l2 & s1))
3095 /* Check for mismatched ISR attribute. */
3096 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3098 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3099 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3101 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3108 /* Assigns default attributes to newly defined type. This is used to
3109 set short_call/long_call attributes for function types of
3110 functions defined inside corresponding #pragma scopes. */
3112 arm_set_default_type_attributes (tree type)
3114 /* Add __attribute__ ((long_call)) to all functions, when
3115 inside #pragma long_calls or __attribute__ ((short_call)),
3116 when inside #pragma no_long_calls. */
3117 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3119 tree type_attr_list, attr_name;
3120 type_attr_list = TYPE_ATTRIBUTES (type);
3122 if (arm_pragma_long_calls == LONG)
3123 attr_name = get_identifier ("long_call");
3124 else if (arm_pragma_long_calls == SHORT)
3125 attr_name = get_identifier ("short_call");
3129 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3130 TYPE_ATTRIBUTES (type) = type_attr_list;
3134 /* Return true if DECL is known to be linked into section SECTION. */
3137 arm_function_in_section_p (tree decl, section *section)
3139 /* We can only be certain about functions defined in the same
3140 compilation unit. */
3141 if (!TREE_STATIC (decl))
3144 /* Make sure that SYMBOL always binds to the definition in this
3145 compilation unit. */
3146 if (!targetm.binds_local_p (decl))
3149 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3150 if (!DECL_SECTION_NAME (decl))
3152 /* Only cater for unit-at-a-time mode, where we know that the user
3153 cannot later specify a section for DECL. */
3154 if (!flag_unit_at_a_time)
3157 /* Make sure that we will not create a unique section for DECL. */
3158 if (flag_function_sections || DECL_ONE_ONLY (decl))
3162 return function_section (decl) == section;
3165 /* Return nonzero if a 32-bit "long_call" should be generated for
3166 a call from the current function to DECL. We generate a long_call
3169 a. has an __attribute__((long call))
3170 or b. is within the scope of a #pragma long_calls
3171 or c. the -mlong-calls command line switch has been specified
3173 However we do not generate a long call if the function:
3175 d. has an __attribute__ ((short_call))
3176 or e. is inside the scope of a #pragma no_long_calls
3177 or f. is defined in the same section as the current function. */
3180 arm_is_long_call_p (tree decl)
3185 return TARGET_LONG_CALLS;
3187 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3188 if (lookup_attribute ("short_call", attrs))
3191 /* For "f", be conservative, and only cater for cases in which the
3192 whole of the current function is placed in the same section. */
3193 if (!flag_reorder_blocks_and_partition
3194 && arm_function_in_section_p (decl, current_function_section ()))
3197 if (lookup_attribute ("long_call", attrs))
3200 return TARGET_LONG_CALLS;
3203 /* Return nonzero if it is ok to make a tail-call to DECL. */
3205 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3207 unsigned long func_type;
3209 if (cfun->machine->sibcall_blocked)
3212 /* Never tailcall something for which we have no decl, or if we
3213 are in Thumb mode. */
3214 if (decl == NULL || TARGET_THUMB)
3217 /* Cannot tail-call to long calls, since these are out of range of
3218 a branch instruction. */
3219 if (arm_is_long_call_p (decl))
3222 /* If we are interworking and the function is not declared static
3223 then we can't tail-call it unless we know that it exists in this
3224 compilation unit (since it might be a Thumb routine). */
3225 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3228 func_type = arm_current_func_type ();
3229 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3230 if (IS_INTERRUPT (func_type))
3233 /* Never tailcall if function may be called with a misaligned SP. */
3234 if (IS_STACKALIGN (func_type))
3237 /* Everything else is ok. */
3242 /* Addressing mode support functions. */
3244 /* Return nonzero if X is a legitimate immediate operand when compiling
3245 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3247 legitimate_pic_operand_p (rtx x)
3249 if (GET_CODE (x) == SYMBOL_REF
3250 || (GET_CODE (x) == CONST
3251 && GET_CODE (XEXP (x, 0)) == PLUS
3252 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3259 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3261 if (GET_CODE (orig) == SYMBOL_REF
3262 || GET_CODE (orig) == LABEL_REF)
3264 #ifndef AOF_ASSEMBLER
3265 rtx pic_ref, address;
3270 /* If this function doesn't have a pic register, create one now.
3271 A lot of the logic here is made obscure by the fact that this
3272 routine gets called as part of the rtx cost estimation
3273 process. We don't want those calls to affect any assumptions
3274 about the real function; and further, we can't call
3275 entry_of_function() until we start the real expansion
3277 if (!current_function_uses_pic_offset_table)
3279 gcc_assert (!no_new_pseudos);
3280 if (arm_pic_register != INVALID_REGNUM)
3282 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3284 /* Play games to avoid marking the function as needing pic
3285 if we are being called as part of the cost-estimation
3287 if (current_ir_type () != IR_GIMPLE)
3288 current_function_uses_pic_offset_table = 1;
3294 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3296 /* Play games to avoid marking the function as needing pic
3297 if we are being called as part of the cost-estimation
3299 if (current_ir_type () != IR_GIMPLE)
3301 current_function_uses_pic_offset_table = 1;
3304 arm_load_pic_register (0UL);
3308 emit_insn_after (seq, entry_of_function ());
3315 gcc_assert (!no_new_pseudos);
3316 reg = gen_reg_rtx (Pmode);
3321 #ifdef AOF_ASSEMBLER
3322 /* The AOF assembler can generate relocations for these directly, and
3323 understands that the PIC register has to be added into the offset. */
3324 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3327 address = gen_reg_rtx (Pmode);
3332 emit_insn (gen_pic_load_addr_arm (address, orig));
3333 else if (TARGET_THUMB2)
3334 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3335 else /* TARGET_THUMB1 */
3336 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3338 if ((GET_CODE (orig) == LABEL_REF
3339 || (GET_CODE (orig) == SYMBOL_REF &&
3340 SYMBOL_REF_LOCAL_P (orig)))
3342 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3345 pic_ref = gen_const_mem (Pmode,
3346 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3350 insn = emit_move_insn (reg, pic_ref);
3352 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3354 set_unique_reg_note (insn, REG_EQUAL, orig);
3358 else if (GET_CODE (orig) == CONST)
3362 if (GET_CODE (XEXP (orig, 0)) == PLUS
3363 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3366 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3367 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3372 gcc_assert (!no_new_pseudos);
3373 reg = gen_reg_rtx (Pmode);
3376 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3378 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3379 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3380 base == reg ? 0 : reg);
3382 if (GET_CODE (offset) == CONST_INT)
3384 /* The base register doesn't really matter, we only want to
3385 test the index for the appropriate mode. */
3386 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3388 gcc_assert (!no_new_pseudos);
3389 offset = force_reg (Pmode, offset);
3392 if (GET_CODE (offset) == CONST_INT)
3393 return plus_constant (base, INTVAL (offset));
3396 if (GET_MODE_SIZE (mode) > 4
3397 && (GET_MODE_CLASS (mode) == MODE_INT
3398 || TARGET_SOFT_FLOAT))
3400 emit_insn (gen_addsi3 (reg, base, offset));
3404 return gen_rtx_PLUS (Pmode, base, offset);
3411 /* Find a spare register to use during the prolog of a function. */
3414 thumb_find_work_register (unsigned long pushed_regs_mask)
3418 /* Check the argument registers first as these are call-used. The
3419 register allocation order means that sometimes r3 might be used
3420 but earlier argument registers might not, so check them all. */
3421 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3422 if (!regs_ever_live[reg])
3425 /* Before going on to check the call-saved registers we can try a couple
3426 more ways of deducing that r3 is available. The first is when we are
3427 pushing anonymous arguments onto the stack and we have less than 4
3428 registers worth of fixed arguments(*). In this case r3 will be part of
3429 the variable argument list and so we can be sure that it will be
3430 pushed right at the start of the function. Hence it will be available
3431 for the rest of the prologue.
3432 (*): ie current_function_pretend_args_size is greater than 0. */
3433 if (cfun->machine->uses_anonymous_args
3434 && current_function_pretend_args_size > 0)
3435 return LAST_ARG_REGNUM;
3437 /* The other case is when we have fixed arguments but less than 4 registers
3438 worth. In this case r3 might be used in the body of the function, but
3439 it is not being used to convey an argument into the function. In theory
3440 we could just check current_function_args_size to see how many bytes are
3441 being passed in argument registers, but it seems that it is unreliable.
3442 Sometimes it will have the value 0 when in fact arguments are being
3443 passed. (See testcase execute/20021111-1.c for an example). So we also
3444 check the args_info.nregs field as well. The problem with this field is
3445 that it makes no allowances for arguments that are passed to the
3446 function but which are not used. Hence we could miss an opportunity
3447 when a function has an unused argument in r3. But it is better to be
3448 safe than to be sorry. */
3449 if (! cfun->machine->uses_anonymous_args
3450 && current_function_args_size >= 0
3451 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3452 && cfun->args_info.nregs < 4)
3453 return LAST_ARG_REGNUM;
3455 /* Otherwise look for a call-saved register that is going to be pushed. */
3456 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3457 if (pushed_regs_mask & (1 << reg))
3462 /* Thumb-2 can use high regs. */
3463 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3464 if (pushed_regs_mask & (1 << reg))
3467 /* Something went wrong - thumb_compute_save_reg_mask()
3468 should have arranged for a suitable register to be pushed. */
3472 static GTY(()) int pic_labelno;
3474 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3478 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3480 #ifndef AOF_ASSEMBLER
3481 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx;
3482 rtx global_offset_table;
3484 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3487 gcc_assert (flag_pic);
3489 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3490 in the code stream. */
3492 labelno = GEN_INT (pic_labelno++);
3493 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3494 l1 = gen_rtx_CONST (VOIDmode, l1);
3496 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3497 /* On the ARM the PC register contains 'dot + 8' at the time of the
3498 addition, on the Thumb it is 'dot + 4'. */
3499 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3501 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3502 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3504 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3506 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3510 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx));
3511 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg,
3512 cfun->machine->pic_reg, labelno));
3514 else if (TARGET_THUMB2)
3516 /* Thumb-2 only allows very limited access to the PC. Calculate the
3517 address in a temporary register. */
3518 if (arm_pic_register != INVALID_REGNUM)
3520 pic_tmp = gen_rtx_REG (SImode,
3521 thumb_find_work_register (saved_regs));
3525 gcc_assert (!no_new_pseudos);
3526 pic_tmp = gen_reg_rtx (Pmode);
3529 emit_insn (gen_pic_load_addr_thumb2 (cfun->machine->pic_reg, pic_rtx));
3530 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3531 emit_insn (gen_addsi3(cfun->machine->pic_reg, cfun->machine->pic_reg,
3534 else /* TARGET_THUMB1 */
3536 if (arm_pic_register != INVALID_REGNUM
3537 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM)
3539 /* We will have pushed the pic register, so we should always be
3540 able to find a work register. */
3541 pic_tmp = gen_rtx_REG (SImode,
3542 thumb_find_work_register (saved_regs));
3543 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3544 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3547 emit_insn (gen_pic_load_addr_thumb1 (cfun->machine->pic_reg, pic_rtx));
3548 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg,
3549 cfun->machine->pic_reg, labelno));
3552 /* Need to emit this whether or not we obey regdecls,
3553 since setjmp/longjmp can cause life info to screw up. */
3554 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg));
3555 #endif /* AOF_ASSEMBLER */
3559 /* Return nonzero if X is valid as an ARM state addressing register. */
3561 arm_address_register_rtx_p (rtx x, int strict_p)
3565 if (GET_CODE (x) != REG)
3571 return ARM_REGNO_OK_FOR_BASE_P (regno);
3573 return (regno <= LAST_ARM_REGNUM
3574 || regno >= FIRST_PSEUDO_REGISTER
3575 || regno == FRAME_POINTER_REGNUM
3576 || regno == ARG_POINTER_REGNUM);
3579 /* Return TRUE if this rtx is the difference of a symbol and a label,
3580 and will reduce to a PC-relative relocation in the object file.
3581 Expressions like this can be left alone when generating PIC, rather
3582 than forced through the GOT. */
3584 pcrel_constant_p (rtx x)
3586 if (GET_CODE (x) == MINUS)
3587 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3592 /* Return nonzero if X is a valid ARM state address operand. */
3594 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3598 enum rtx_code code = GET_CODE (x);
3600 if (arm_address_register_rtx_p (x, strict_p))
3603 use_ldrd = (TARGET_LDRD
3605 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3607 if (code == POST_INC || code == PRE_DEC
3608 || ((code == PRE_INC || code == POST_DEC)
3609 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3610 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3612 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3613 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3614 && GET_CODE (XEXP (x, 1)) == PLUS
3615 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3617 rtx addend = XEXP (XEXP (x, 1), 1);
3619 /* Don't allow ldrd post increment by register because it's hard
3620 to fixup invalid register choices. */
3622 && GET_CODE (x) == POST_MODIFY
3623 && GET_CODE (addend) == REG)
3626 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3627 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3630 /* After reload constants split into minipools will have addresses
3631 from a LABEL_REF. */
3632 else if (reload_completed
3633 && (code == LABEL_REF
3635 && GET_CODE (XEXP (x, 0)) == PLUS
3636 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3637 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3640 else if (mode == TImode)
3643 else if (code == PLUS)
3645 rtx xop0 = XEXP (x, 0);
3646 rtx xop1 = XEXP (x, 1);
3648 return ((arm_address_register_rtx_p (xop0, strict_p)
3649 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3650 || (arm_address_register_rtx_p (xop1, strict_p)
3651 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3655 /* Reload currently can't handle MINUS, so disable this for now */
3656 else if (GET_CODE (x) == MINUS)
3658 rtx xop0 = XEXP (x, 0);
3659 rtx xop1 = XEXP (x, 1);
3661 return (arm_address_register_rtx_p (xop0, strict_p)
3662 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3666 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3667 && code == SYMBOL_REF
3668 && CONSTANT_POOL_ADDRESS_P (x)
3670 && symbol_mentioned_p (get_pool_constant (x))
3671 && ! pcrel_constant_p (get_pool_constant (x))))
3677 /* Return nonzero if X is a valid Thumb-2 address operand. */
3679 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3682 enum rtx_code code = GET_CODE (x);
3684 if (arm_address_register_rtx_p (x, strict_p))
3687 use_ldrd = (TARGET_LDRD
3689 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3691 if (code == POST_INC || code == PRE_DEC
3692 || ((code == PRE_INC || code == POST_DEC)
3693 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3694 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3696 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3697 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3698 && GET_CODE (XEXP (x, 1)) == PLUS
3699 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3701 /* Thumb-2 only has autoincrement by constant. */
3702 rtx addend = XEXP (XEXP (x, 1), 1);
3703 HOST_WIDE_INT offset;
3705 if (GET_CODE (addend) != CONST_INT)
3708 offset = INTVAL(addend);
3709 if (GET_MODE_SIZE (mode) <= 4)
3710 return (offset > -256 && offset < 256);
3712 return (use_ldrd && offset > -1024 && offset < 1024
3713 && (offset & 3) == 0);
3716 /* After reload constants split into minipools will have addresses
3717 from a LABEL_REF. */
3718 else if (reload_completed
3719 && (code == LABEL_REF
3721 && GET_CODE (XEXP (x, 0)) == PLUS
3722 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3723 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3726 else if (mode == TImode)
3729 else if (code == PLUS)
3731 rtx xop0 = XEXP (x, 0);
3732 rtx xop1 = XEXP (x, 1);
3734 return ((arm_address_register_rtx_p (xop0, strict_p)
3735 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3736 || (arm_address_register_rtx_p (xop1, strict_p)
3737 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3740 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3741 && code == SYMBOL_REF
3742 && CONSTANT_POOL_ADDRESS_P (x)
3744 && symbol_mentioned_p (get_pool_constant (x))
3745 && ! pcrel_constant_p (get_pool_constant (x))))
3751 /* Return nonzero if INDEX is valid for an address index operand in
3754 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3757 HOST_WIDE_INT range;
3758 enum rtx_code code = GET_CODE (index);
3760 /* Standard coprocessor addressing modes. */
3761 if (TARGET_HARD_FLOAT
3762 && (TARGET_FPA || TARGET_MAVERICK)
3763 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3764 || (TARGET_MAVERICK && mode == DImode)))
3765 return (code == CONST_INT && INTVAL (index) < 1024
3766 && INTVAL (index) > -1024
3767 && (INTVAL (index) & 3) == 0);
3769 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3770 return (code == CONST_INT
3771 && INTVAL (index) < 1024
3772 && INTVAL (index) > -1024
3773 && (INTVAL (index) & 3) == 0);
3775 if (arm_address_register_rtx_p (index, strict_p)
3776 && (GET_MODE_SIZE (mode) <= 4))
3779 if (mode == DImode || mode == DFmode)
3781 if (code == CONST_INT)
3783 HOST_WIDE_INT val = INTVAL (index);
3786 return val > -256 && val < 256;
3788 return val > -4096 && val < 4092;
3791 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3794 if (GET_MODE_SIZE (mode) <= 4
3797 || (mode == QImode && outer == SIGN_EXTEND))))
3801 rtx xiop0 = XEXP (index, 0);
3802 rtx xiop1 = XEXP (index, 1);
3804 return ((arm_address_register_rtx_p (xiop0, strict_p)
3805 && power_of_two_operand (xiop1, SImode))
3806 || (arm_address_register_rtx_p (xiop1, strict_p)
3807 && power_of_two_operand (xiop0, SImode)));
3809 else if (code == LSHIFTRT || code == ASHIFTRT
3810 || code == ASHIFT || code == ROTATERT)
3812 rtx op = XEXP (index, 1);
3814 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3815 && GET_CODE (op) == CONST_INT
3817 && INTVAL (op) <= 31);
3821 /* For ARM v4 we may be doing a sign-extend operation during the
3825 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3831 range = (mode == HImode) ? 4095 : 4096;
3833 return (code == CONST_INT
3834 && INTVAL (index) < range
3835 && INTVAL (index) > -range);
3838 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3839 index operand. i.e. 1, 2, 4 or 8. */
3841 thumb2_index_mul_operand (rtx op)
3845 if (GET_CODE(op) != CONST_INT)
3849 return (val == 1 || val == 2 || val == 4 || val == 8);
3852 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3854 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
3856 enum rtx_code code = GET_CODE (index);
3858 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3859 /* Standard coprocessor addressing modes. */
3860 if (TARGET_HARD_FLOAT
3861 && (TARGET_FPA || TARGET_MAVERICK)
3862 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3863 || (TARGET_MAVERICK && mode == DImode)))
3864 return (code == CONST_INT && INTVAL (index) < 1024
3865 && INTVAL (index) > -1024
3866 && (INTVAL (index) & 3) == 0);
3868 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3870 /* For DImode assume values will usually live in core regs
3871 and only allow LDRD addressing modes. */
3872 if (!TARGET_LDRD || mode != DImode)
3873 return (code == CONST_INT
3874 && INTVAL (index) < 1024
3875 && INTVAL (index) > -1024
3876 && (INTVAL (index) & 3) == 0);
3879 if (arm_address_register_rtx_p (index, strict_p)
3880 && (GET_MODE_SIZE (mode) <= 4))
3883 if (mode == DImode || mode == DFmode)
3885 HOST_WIDE_INT val = INTVAL (index);
3886 /* ??? Can we assume ldrd for thumb2? */
3887 /* Thumb-2 ldrd only has reg+const addressing modes. */
3888 if (code != CONST_INT)
3891 /* ldrd supports offsets of +-1020.
3892 However the ldr fallback does not. */
3893 return val > -256 && val < 256 && (val & 3) == 0;
3898 rtx xiop0 = XEXP (index, 0);
3899 rtx xiop1 = XEXP (index, 1);
3901 return ((arm_address_register_rtx_p (xiop0, strict_p)
3902 && thumb2_index_mul_operand (xiop1))
3903 || (arm_address_register_rtx_p (xiop1, strict_p)
3904 && thumb2_index_mul_operand (xiop0)));
3906 else if (code == ASHIFT)
3908 rtx op = XEXP (index, 1);
3910 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3911 && GET_CODE (op) == CONST_INT
3913 && INTVAL (op) <= 3);
3916 return (code == CONST_INT
3917 && INTVAL (index) < 4096
3918 && INTVAL (index) > -256);
3921 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3923 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3927 if (GET_CODE (x) != REG)
3933 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3935 return (regno <= LAST_LO_REGNUM
3936 || regno > LAST_VIRTUAL_REGISTER
3937 || regno == FRAME_POINTER_REGNUM
3938 || (GET_MODE_SIZE (mode) >= 4
3939 && (regno == STACK_POINTER_REGNUM
3940 || regno >= FIRST_PSEUDO_REGISTER
3941 || x == hard_frame_pointer_rtx
3942 || x == arg_pointer_rtx)));
3945 /* Return nonzero if x is a legitimate index register. This is the case
3946 for any base register that can access a QImode object. */
3948 thumb1_index_register_rtx_p (rtx x, int strict_p)
3950 return thumb1_base_register_rtx_p (x, QImode, strict_p);
3953 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
3955 The AP may be eliminated to either the SP or the FP, so we use the
3956 least common denominator, e.g. SImode, and offsets from 0 to 64.
3958 ??? Verify whether the above is the right approach.
3960 ??? Also, the FP may be eliminated to the SP, so perhaps that
3961 needs special handling also.
3963 ??? Look at how the mips16 port solves this problem. It probably uses
3964 better ways to solve some of these problems.
3966 Although it is not incorrect, we don't accept QImode and HImode
3967 addresses based on the frame pointer or arg pointer until the
3968 reload pass starts. This is so that eliminating such addresses
3969 into stack based ones won't produce impossible code. */
3971 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3973 /* ??? Not clear if this is right. Experiment. */
3974 if (GET_MODE_SIZE (mode) < 4
3975 && !(reload_in_progress || reload_completed)
3976 && (reg_mentioned_p (frame_pointer_rtx, x)
3977 || reg_mentioned_p (arg_pointer_rtx, x)
3978 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3979 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3980 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3981 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3984 /* Accept any base register. SP only in SImode or larger. */
3985 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
3988 /* This is PC relative data before arm_reorg runs. */
3989 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3990 && GET_CODE (x) == SYMBOL_REF
3991 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
3994 /* This is PC relative data after arm_reorg runs. */
3995 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3996 && (GET_CODE (x) == LABEL_REF
3997 || (GET_CODE (x) == CONST
3998 && GET_CODE (XEXP (x, 0)) == PLUS
3999 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4000 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4003 /* Post-inc indexing only supported for SImode and larger. */
4004 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4005 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4008 else if (GET_CODE (x) == PLUS)
4010 /* REG+REG address can be any two index registers. */
4011 /* We disallow FRAME+REG addressing since we know that FRAME
4012 will be replaced with STACK, and SP relative addressing only
4013 permits SP+OFFSET. */
4014 if (GET_MODE_SIZE (mode) <= 4
4015 && XEXP (x, 0) != frame_pointer_rtx
4016 && XEXP (x, 1) != frame_pointer_rtx
4017 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4018 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4021 /* REG+const has 5-7 bit offset for non-SP registers. */
4022 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4023 || XEXP (x, 0) == arg_pointer_rtx)
4024 && GET_CODE (XEXP (x, 1)) == CONST_INT
4025 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4028 /* REG+const has 10-bit offset for SP, but only SImode and
4029 larger is supported. */
4030 /* ??? Should probably check for DI/DFmode overflow here
4031 just like GO_IF_LEGITIMATE_OFFSET does. */
4032 else if (GET_CODE (XEXP (x, 0)) == REG
4033 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4034 && GET_MODE_SIZE (mode) >= 4
4035 && GET_CODE (XEXP (x, 1)) == CONST_INT
4036 && INTVAL (XEXP (x, 1)) >= 0
4037 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4038 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4041 else if (GET_CODE (XEXP (x, 0)) == REG
4042 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4043 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4044 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4045 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4046 && GET_MODE_SIZE (mode) >= 4
4047 && GET_CODE (XEXP (x, 1)) == CONST_INT
4048 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4052 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4053 && GET_MODE_SIZE (mode) == 4
4054 && GET_CODE (x) == SYMBOL_REF
4055 && CONSTANT_POOL_ADDRESS_P (x)
4057 && symbol_mentioned_p (get_pool_constant (x))
4058 && ! pcrel_constant_p (get_pool_constant (x))))
4064 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4065 instruction of mode MODE. */
4067 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4069 switch (GET_MODE_SIZE (mode))
4072 return val >= 0 && val < 32;
4075 return val >= 0 && val < 64 && (val & 1) == 0;
4079 && (val + GET_MODE_SIZE (mode)) <= 128
4084 /* Build the SYMBOL_REF for __tls_get_addr. */
4086 static GTY(()) rtx tls_get_addr_libfunc;
4089 get_tls_get_addr (void)
4091 if (!tls_get_addr_libfunc)
4092 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4093 return tls_get_addr_libfunc;
4097 arm_load_tp (rtx target)
4100 target = gen_reg_rtx (SImode);
4104 /* Can return in any reg. */
4105 emit_insn (gen_load_tp_hard (target));
4109 /* Always returned in r0. Immediately copy the result into a pseudo,
4110 otherwise other uses of r0 (e.g. setting up function arguments) may
4111 clobber the value. */
4115 emit_insn (gen_load_tp_soft ());
4117 tmp = gen_rtx_REG (SImode, 0);
4118 emit_move_insn (target, tmp);
4124 load_tls_operand (rtx x, rtx reg)
4128 if (reg == NULL_RTX)
4129 reg = gen_reg_rtx (SImode);
4131 tmp = gen_rtx_CONST (SImode, x);
4133 emit_move_insn (reg, tmp);
4139 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4141 rtx insns, label, labelno, sum;
4145 labelno = GEN_INT (pic_labelno++);
4146 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4147 label = gen_rtx_CONST (VOIDmode, label);
4149 sum = gen_rtx_UNSPEC (Pmode,
4150 gen_rtvec (4, x, GEN_INT (reloc), label,
4151 GEN_INT (TARGET_ARM ? 8 : 4)),
4153 reg = load_tls_operand (sum, reg);
4156 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4157 else if (TARGET_THUMB2)
4160 /* Thumb-2 only allows very limited access to the PC. Calculate
4161 the address in a temporary register. */
4162 tmp = gen_reg_rtx (SImode);
4163 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4164 emit_insn (gen_addsi3(reg, reg, tmp));
4166 else /* TARGET_THUMB1 */
4167 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4169 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4170 Pmode, 1, reg, Pmode);
4172 insns = get_insns ();
4179 legitimize_tls_address (rtx x, rtx reg)
4181 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4182 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4186 case TLS_MODEL_GLOBAL_DYNAMIC:
4187 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4188 dest = gen_reg_rtx (Pmode);
4189 emit_libcall_block (insns, dest, ret, x);
4192 case TLS_MODEL_LOCAL_DYNAMIC:
4193 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4195 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4196 share the LDM result with other LD model accesses. */
4197 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4199 dest = gen_reg_rtx (Pmode);
4200 emit_libcall_block (insns, dest, ret, eqv);
4202 /* Load the addend. */
4203 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4205 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4206 return gen_rtx_PLUS (Pmode, dest, addend);
4208 case TLS_MODEL_INITIAL_EXEC:
4209 labelno = GEN_INT (pic_labelno++);
4210 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4211 label = gen_rtx_CONST (VOIDmode, label);
4212 sum = gen_rtx_UNSPEC (Pmode,
4213 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4214 GEN_INT (TARGET_ARM ? 8 : 4)),
4216 reg = load_tls_operand (sum, reg);
4219 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4220 else if (TARGET_THUMB2)
4223 /* Thumb-2 only allows very limited access to the PC. Calculate
4224 the address in a temporary register. */
4225 tmp = gen_reg_rtx (SImode);
4226 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4227 emit_insn (gen_addsi3(reg, reg, tmp));
4228 emit_move_insn (reg, gen_const_mem (SImode, reg));
4232 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4233 emit_move_insn (reg, gen_const_mem (SImode, reg));
4236 tp = arm_load_tp (NULL_RTX);
4238 return gen_rtx_PLUS (Pmode, tp, reg);
4240 case TLS_MODEL_LOCAL_EXEC:
4241 tp = arm_load_tp (NULL_RTX);
4243 reg = gen_rtx_UNSPEC (Pmode,
4244 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4246 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4248 return gen_rtx_PLUS (Pmode, tp, reg);
4255 /* Try machine-dependent ways of modifying an illegitimate address
4256 to be legitimate. If we find one, return the new, valid address. */
4258 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4260 if (arm_tls_symbol_p (x))
4261 return legitimize_tls_address (x, NULL_RTX);
4263 if (GET_CODE (x) == PLUS)
4265 rtx xop0 = XEXP (x, 0);
4266 rtx xop1 = XEXP (x, 1);
4268 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4269 xop0 = force_reg (SImode, xop0);
4271 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4272 xop1 = force_reg (SImode, xop1);
4274 if (ARM_BASE_REGISTER_RTX_P (xop0)
4275 && GET_CODE (xop1) == CONST_INT)
4277 HOST_WIDE_INT n, low_n;
4281 /* VFP addressing modes actually allow greater offsets, but for
4282 now we just stick with the lowest common denominator. */
4284 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4296 low_n = ((mode) == TImode ? 0
4297 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4301 base_reg = gen_reg_rtx (SImode);
4302 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4303 emit_move_insn (base_reg, val);
4304 x = plus_constant (base_reg, low_n);
4306 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4307 x = gen_rtx_PLUS (SImode, xop0, xop1);
4310 /* XXX We don't allow MINUS any more -- see comment in
4311 arm_legitimate_address_p (). */
4312 else if (GET_CODE (x) == MINUS)
4314 rtx xop0 = XEXP (x, 0);
4315 rtx xop1 = XEXP (x, 1);
4317 if (CONSTANT_P (xop0))
4318 xop0 = force_reg (SImode, xop0);
4320 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4321 xop1 = force_reg (SImode, xop1);
4323 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4324 x = gen_rtx_MINUS (SImode, xop0, xop1);
4327 /* Make sure to take full advantage of the pre-indexed addressing mode
4328 with absolute addresses which often allows for the base register to
4329 be factorized for multiple adjacent memory references, and it might
4330 even allows for the mini pool to be avoided entirely. */
4331 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4334 HOST_WIDE_INT mask, base, index;
4337 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4338 use a 8-bit index. So let's use a 12-bit index for SImode only and
4339 hope that arm_gen_constant will enable ldrb to use more bits. */
4340 bits = (mode == SImode) ? 12 : 8;
4341 mask = (1 << bits) - 1;
4342 base = INTVAL (x) & ~mask;
4343 index = INTVAL (x) & mask;
4344 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4346 /* It'll most probably be more efficient to generate the base
4347 with more bits set and use a negative index instead. */
4351 base_reg = force_reg (SImode, GEN_INT (base));
4352 x = plus_constant (base_reg, index);
4357 /* We need to find and carefully transform any SYMBOL and LABEL
4358 references; so go back to the original address expression. */
4359 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4361 if (new_x != orig_x)
4369 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4370 to be legitimate. If we find one, return the new, valid address. */
4372 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4374 if (arm_tls_symbol_p (x))
4375 return legitimize_tls_address (x, NULL_RTX);
4377 if (GET_CODE (x) == PLUS
4378 && GET_CODE (XEXP (x, 1)) == CONST_INT
4379 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4380 || INTVAL (XEXP (x, 1)) < 0))
4382 rtx xop0 = XEXP (x, 0);
4383 rtx xop1 = XEXP (x, 1);
4384 HOST_WIDE_INT offset = INTVAL (xop1);
4386 /* Try and fold the offset into a biasing of the base register and
4387 then offsetting that. Don't do this when optimizing for space
4388 since it can cause too many CSEs. */
4389 if (optimize_size && offset >= 0
4390 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4392 HOST_WIDE_INT delta;
4395 delta = offset - (256 - GET_MODE_SIZE (mode));
4396 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4397 delta = 31 * GET_MODE_SIZE (mode);
4399 delta = offset & (~31 * GET_MODE_SIZE (mode));
4401 xop0 = force_operand (plus_constant (xop0, offset - delta),
4403 x = plus_constant (xop0, delta);
4405 else if (offset < 0 && offset > -256)
4406 /* Small negative offsets are best done with a subtract before the
4407 dereference, forcing these into a register normally takes two
4409 x = force_operand (x, NULL_RTX);
4412 /* For the remaining cases, force the constant into a register. */
4413 xop1 = force_reg (SImode, xop1);
4414 x = gen_rtx_PLUS (SImode, xop0, xop1);
4417 else if (GET_CODE (x) == PLUS
4418 && s_register_operand (XEXP (x, 1), SImode)
4419 && !s_register_operand (XEXP (x, 0), SImode))
4421 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4423 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4428 /* We need to find and carefully transform any SYMBOL and LABEL
4429 references; so go back to the original address expression. */
4430 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4432 if (new_x != orig_x)
4440 thumb_legitimize_reload_address (rtx *x_p,
4441 enum machine_mode mode,
4442 int opnum, int type,
4443 int ind_levels ATTRIBUTE_UNUSED)
4447 if (GET_CODE (x) == PLUS
4448 && GET_MODE_SIZE (mode) < 4
4449 && REG_P (XEXP (x, 0))
4450 && XEXP (x, 0) == stack_pointer_rtx
4451 && GET_CODE (XEXP (x, 1)) == CONST_INT
4452 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4457 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4458 Pmode, VOIDmode, 0, 0, opnum, type);
4462 /* If both registers are hi-regs, then it's better to reload the
4463 entire expression rather than each register individually. That
4464 only requires one reload register rather than two. */
4465 if (GET_CODE (x) == PLUS
4466 && REG_P (XEXP (x, 0))
4467 && REG_P (XEXP (x, 1))
4468 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4469 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4474 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4475 Pmode, VOIDmode, 0, 0, opnum, type);
4482 /* Test for various thread-local symbols. */
4484 /* Return TRUE if X is a thread-local symbol. */
4487 arm_tls_symbol_p (rtx x)
4489 if (! TARGET_HAVE_TLS)
4492 if (GET_CODE (x) != SYMBOL_REF)
4495 return SYMBOL_REF_TLS_MODEL (x) != 0;
4498 /* Helper for arm_tls_referenced_p. */
4501 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4503 if (GET_CODE (*x) == SYMBOL_REF)
4504 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4506 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4507 TLS offsets, not real symbol references. */
4508 if (GET_CODE (*x) == UNSPEC
4509 && XINT (*x, 1) == UNSPEC_TLS)
4515 /* Return TRUE if X contains any TLS symbol references. */
4518 arm_tls_referenced_p (rtx x)
4520 if (! TARGET_HAVE_TLS)
4523 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4526 #define REG_OR_SUBREG_REG(X) \
4527 (GET_CODE (X) == REG \
4528 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4530 #define REG_OR_SUBREG_RTX(X) \
4531 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4533 #ifndef COSTS_N_INSNS
4534 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4537 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4539 enum machine_mode mode = GET_MODE (x);
4552 return COSTS_N_INSNS (1);
4555 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4558 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4565 return COSTS_N_INSNS (2) + cycles;
4567 return COSTS_N_INSNS (1) + 16;
4570 return (COSTS_N_INSNS (1)
4571 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4572 + GET_CODE (SET_DEST (x)) == MEM));
4577 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4579 if (thumb_shiftable_const (INTVAL (x)))
4580 return COSTS_N_INSNS (2);
4581 return COSTS_N_INSNS (3);
4583 else if ((outer == PLUS || outer == COMPARE)
4584 && INTVAL (x) < 256 && INTVAL (x) > -256)
4586 else if (outer == AND
4587 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4588 return COSTS_N_INSNS (1);
4589 else if (outer == ASHIFT || outer == ASHIFTRT
4590 || outer == LSHIFTRT)
4592 return COSTS_N_INSNS (2);
4598 return COSTS_N_INSNS (3);
4616 /* XXX another guess. */
4617 /* Memory costs quite a lot for the first word, but subsequent words
4618 load at the equivalent of a single insn each. */
4619 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4620 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4625 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4630 /* XXX still guessing. */
4631 switch (GET_MODE (XEXP (x, 0)))
4634 return (1 + (mode == DImode ? 4 : 0)
4635 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4638 return (4 + (mode == DImode ? 4 : 0)
4639 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4642 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4654 /* Worker routine for arm_rtx_costs. */
4655 /* ??? This needs updating for thumb2. */
4657 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4659 enum machine_mode mode = GET_MODE (x);
4660 enum rtx_code subcode;
4666 /* Memory costs quite a lot for the first word, but subsequent words
4667 load at the equivalent of a single insn each. */
4668 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4669 + (GET_CODE (x) == SYMBOL_REF
4670 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4676 return optimize_size ? COSTS_N_INSNS (2) : 100;
4679 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4686 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4688 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4689 + ((GET_CODE (XEXP (x, 0)) == REG
4690 || (GET_CODE (XEXP (x, 0)) == SUBREG
4691 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4693 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4694 || (GET_CODE (XEXP (x, 0)) == SUBREG
4695 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4697 + ((GET_CODE (XEXP (x, 1)) == REG
4698 || (GET_CODE (XEXP (x, 1)) == SUBREG
4699 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4700 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4704 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4706 extra_cost = rtx_cost (XEXP (x, 1), code);
4707 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4708 extra_cost += 4 * ARM_NUM_REGS (mode);
4713 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4714 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4715 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4716 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4719 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4720 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4721 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4722 && arm_const_double_rtx (XEXP (x, 1))))
4724 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4725 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4726 && arm_const_double_rtx (XEXP (x, 0))))
4729 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4730 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4731 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4732 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4733 || subcode == ASHIFTRT || subcode == LSHIFTRT
4734 || subcode == ROTATE || subcode == ROTATERT
4736 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4737 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4738 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4739 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4740 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4741 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4742 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4747 if (GET_CODE (XEXP (x, 0)) == MULT)
4749 extra_cost = rtx_cost (XEXP (x, 0), code);
4750 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4751 extra_cost += 4 * ARM_NUM_REGS (mode);
4755 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4756 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4757 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4758 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4759 && arm_const_double_rtx (XEXP (x, 1))))
4763 case AND: case XOR: case IOR:
4766 /* Normally the frame registers will be spilt into reg+const during
4767 reload, so it is a bad idea to combine them with other instructions,
4768 since then they might not be moved outside of loops. As a compromise
4769 we allow integration with ops that have a constant as their second
4771 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4772 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4773 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4774 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4775 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4779 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4780 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4781 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4782 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4785 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4786 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4787 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4788 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4789 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4792 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4793 return (1 + extra_cost
4794 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4795 || subcode == LSHIFTRT || subcode == ASHIFTRT
4796 || subcode == ROTATE || subcode == ROTATERT
4798 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4799 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4800 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4801 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4802 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4803 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4809 /* This should have been handled by the CPU specific routines. */
4813 if (arm_arch3m && mode == SImode
4814 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4815 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4816 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4817 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4818 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4819 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4824 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4825 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4829 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4831 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4834 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4842 return 4 + (mode == DImode ? 4 : 0);
4845 /* ??? value extensions are cheaper on armv6. */
4846 if (GET_MODE (XEXP (x, 0)) == QImode)
4847 return (4 + (mode == DImode ? 4 : 0)
4848 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4851 switch (GET_MODE (XEXP (x, 0)))
4854 return (1 + (mode == DImode ? 4 : 0)
4855 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4858 return (4 + (mode == DImode ? 4 : 0)
4859 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4862 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4877 if (const_ok_for_arm (INTVAL (x)))
4878 return outer == SET ? 2 : -1;
4879 else if (outer == AND
4880 && const_ok_for_arm (~INTVAL (x)))
4882 else if ((outer == COMPARE
4883 || outer == PLUS || outer == MINUS)
4884 && const_ok_for_arm (-INTVAL (x)))
4895 if (arm_const_double_rtx (x))
4896 return outer == SET ? 2 : -1;
4897 else if ((outer == COMPARE || outer == PLUS)
4898 && neg_const_double_rtx_ok_for_fpa (x))
4907 /* RTX costs when optimizing for size. */
4909 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4911 enum machine_mode mode = GET_MODE (x);
4915 /* XXX TBD. For now, use the standard costs. */
4916 *total = thumb1_rtx_costs (x, code, outer_code);
4923 /* A memory access costs 1 insn if the mode is small, or the address is
4924 a single register, otherwise it costs one insn per word. */
4925 if (REG_P (XEXP (x, 0)))
4926 *total = COSTS_N_INSNS (1);
4928 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4935 /* Needs a libcall, so it costs about this. */
4936 *total = COSTS_N_INSNS (2);
4940 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4942 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4950 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4952 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4955 else if (mode == SImode)
4957 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4958 /* Slightly disparage register shifts, but not by much. */
4959 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4960 *total += 1 + rtx_cost (XEXP (x, 1), code);
4964 /* Needs a libcall. */
4965 *total = COSTS_N_INSNS (2);
4969 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4971 *total = COSTS_N_INSNS (1);
4977 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4978 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4980 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4981 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4982 || subcode1 == ROTATE || subcode1 == ROTATERT
4983 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4984 || subcode1 == ASHIFTRT)
4986 /* It's just the cost of the two operands. */
4991 *total = COSTS_N_INSNS (1);
4995 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4999 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5001 *total = COSTS_N_INSNS (1);
5006 case AND: case XOR: case IOR:
5009 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5011 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5012 || subcode == LSHIFTRT || subcode == ASHIFTRT
5013 || (code == AND && subcode == NOT))
5015 /* It's just the cost of the two operands. */
5021 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5025 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5029 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5030 *total = COSTS_N_INSNS (1);
5033 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5042 if (cc_register (XEXP (x, 0), VOIDmode))
5045 *total = COSTS_N_INSNS (1);
5049 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5050 *total = COSTS_N_INSNS (1);
5052 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5057 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5059 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5060 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5063 *total += COSTS_N_INSNS (1);
5068 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5070 switch (GET_MODE (XEXP (x, 0)))
5073 *total += COSTS_N_INSNS (1);
5077 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5083 *total += COSTS_N_INSNS (2);
5088 *total += COSTS_N_INSNS (1);
5093 if (const_ok_for_arm (INTVAL (x)))
5094 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5095 else if (const_ok_for_arm (~INTVAL (x)))
5096 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5097 else if (const_ok_for_arm (-INTVAL (x)))
5099 if (outer_code == COMPARE || outer_code == PLUS
5100 || outer_code == MINUS)
5103 *total = COSTS_N_INSNS (1);
5106 *total = COSTS_N_INSNS (2);
5112 *total = COSTS_N_INSNS (2);
5116 *total = COSTS_N_INSNS (4);
5120 if (mode != VOIDmode)
5121 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5123 *total = COSTS_N_INSNS (4); /* How knows? */
5128 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5129 supported on any "slowmul" cores, so it can be ignored. */
5132 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5134 enum machine_mode mode = GET_MODE (x);
5138 *total = thumb1_rtx_costs (x, code, outer_code);
5145 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5152 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5154 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5155 & (unsigned HOST_WIDE_INT) 0xffffffff);
5156 int cost, const_ok = const_ok_for_arm (i);
5157 int j, booth_unit_size;
5159 /* Tune as appropriate. */
5160 cost = const_ok ? 4 : 8;
5161 booth_unit_size = 2;
5162 for (j = 0; i && j < 32; j += booth_unit_size)
5164 i >>= booth_unit_size;
5172 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5173 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5177 *total = arm_rtx_costs_1 (x, code, outer_code);
5183 /* RTX cost for cores with a fast multiply unit (M variants). */
5186 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5188 enum machine_mode mode = GET_MODE (x);
5192 *total = thumb1_rtx_costs (x, code, outer_code);
5196 /* ??? should thumb2 use different costs? */
5200 /* There is no point basing this on the tuning, since it is always the
5201 fast variant if it exists at all. */
5203 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5204 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5205 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5212 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5219 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5221 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5222 & (unsigned HOST_WIDE_INT) 0xffffffff);
5223 int cost, const_ok = const_ok_for_arm (i);
5224 int j, booth_unit_size;
5226 /* Tune as appropriate. */
5227 cost = const_ok ? 4 : 8;
5228 booth_unit_size = 8;
5229 for (j = 0; i && j < 32; j += booth_unit_size)
5231 i >>= booth_unit_size;
5239 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5240 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5244 *total = arm_rtx_costs_1 (x, code, outer_code);
5250 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5251 so it can be ignored. */
5254 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5256 enum machine_mode mode = GET_MODE (x);
5260 *total = thumb1_rtx_costs (x, code, outer_code);
5267 /* There is no point basing this on the tuning, since it is always the
5268 fast variant if it exists at all. */
5270 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5271 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5272 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5279 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5286 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5288 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5289 & (unsigned HOST_WIDE_INT) 0xffffffff);
5290 int cost, const_ok = const_ok_for_arm (i);
5291 unsigned HOST_WIDE_INT masked_const;
5293 /* The cost will be related to two insns.
5294 First a load of the constant (MOV or LDR), then a multiply. */
5297 cost += 1; /* LDR is probably more expensive because
5298 of longer result latency. */
5299 masked_const = i & 0xffff8000;
5300 if (masked_const != 0 && masked_const != 0xffff8000)
5302 masked_const = i & 0xf8000000;
5303 if (masked_const == 0 || masked_const == 0xf8000000)
5312 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5313 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5317 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5318 will stall until the multiplication is complete. */
5319 if (GET_CODE (XEXP (x, 0)) == MULT)
5320 *total = 4 + rtx_cost (XEXP (x, 0), code);
5322 *total = arm_rtx_costs_1 (x, code, outer_code);
5326 *total = arm_rtx_costs_1 (x, code, outer_code);
5332 /* RTX costs for 9e (and later) cores. */
5335 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5337 enum machine_mode mode = GET_MODE (x);
5346 *total = COSTS_N_INSNS (3);
5350 *total = thumb1_rtx_costs (x, code, outer_code);
5358 /* There is no point basing this on the tuning, since it is always the
5359 fast variant if it exists at all. */
5361 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5362 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5363 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5370 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5387 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5388 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5392 *total = arm_rtx_costs_1 (x, code, outer_code);
5396 /* All address computations that can be done are free, but rtx cost returns
5397 the same for practically all of them. So we weight the different types
5398 of address here in the order (most pref first):
5399 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5401 arm_arm_address_cost (rtx x)
5403 enum rtx_code c = GET_CODE (x);
5405 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5407 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5410 if (c == PLUS || c == MINUS)
5412 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5415 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5425 arm_thumb_address_cost (rtx x)
5427 enum rtx_code c = GET_CODE (x);
5432 && GET_CODE (XEXP (x, 0)) == REG
5433 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5440 arm_address_cost (rtx x)
5442 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5446 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5450 /* Some true dependencies can have a higher cost depending
5451 on precisely how certain input operands are used. */
5453 && REG_NOTE_KIND (link) == 0
5454 && recog_memoized (insn) >= 0
5455 && recog_memoized (dep) >= 0)
5457 int shift_opnum = get_attr_shift (insn);
5458 enum attr_type attr_type = get_attr_type (dep);
5460 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5461 operand for INSN. If we have a shifted input operand and the
5462 instruction we depend on is another ALU instruction, then we may
5463 have to account for an additional stall. */
5464 if (shift_opnum != 0
5465 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5467 rtx shifted_operand;
5470 /* Get the shifted operand. */
5471 extract_insn (insn);
5472 shifted_operand = recog_data.operand[shift_opnum];
5474 /* Iterate over all the operands in DEP. If we write an operand
5475 that overlaps with SHIFTED_OPERAND, then we have increase the
5476 cost of this dependency. */
5478 preprocess_constraints ();
5479 for (opno = 0; opno < recog_data.n_operands; opno++)
5481 /* We can ignore strict inputs. */
5482 if (recog_data.operand_type[opno] == OP_IN)
5485 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5492 /* XXX This is not strictly true for the FPA. */
5493 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5494 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5497 /* Call insns don't incur a stall, even if they follow a load. */
5498 if (REG_NOTE_KIND (link) == 0
5499 && GET_CODE (insn) == CALL_INSN)
5502 if ((i_pat = single_set (insn)) != NULL
5503 && GET_CODE (SET_SRC (i_pat)) == MEM
5504 && (d_pat = single_set (dep)) != NULL
5505 && GET_CODE (SET_DEST (d_pat)) == MEM)
5507 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5508 /* This is a load after a store, there is no conflict if the load reads
5509 from a cached area. Assume that loads from the stack, and from the
5510 constant pool are cached, and that others will miss. This is a
5513 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5514 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5515 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5516 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5523 static int fp_consts_inited = 0;
5525 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5526 static const char * const strings_fp[8] =
5529 "4", "5", "0.5", "10"
5532 static REAL_VALUE_TYPE values_fp[8];
5535 init_fp_table (void)
5541 fp_consts_inited = 1;
5543 fp_consts_inited = 8;
5545 for (i = 0; i < fp_consts_inited; i++)
5547 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5552 /* Return TRUE if rtx X is a valid immediate FP constant. */
5554 arm_const_double_rtx (rtx x)
5559 if (!fp_consts_inited)
5562 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5563 if (REAL_VALUE_MINUS_ZERO (r))
5566 for (i = 0; i < fp_consts_inited; i++)
5567 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5573 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5575 neg_const_double_rtx_ok_for_fpa (rtx x)
5580 if (!fp_consts_inited)
5583 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5584 r = REAL_VALUE_NEGATE (r);
5585 if (REAL_VALUE_MINUS_ZERO (r))
5588 for (i = 0; i < 8; i++)
5589 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5595 /* Predicates for `match_operand' and `match_operator'. */
5597 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5599 cirrus_memory_offset (rtx op)
5601 /* Reject eliminable registers. */
5602 if (! (reload_in_progress || reload_completed)
5603 && ( reg_mentioned_p (frame_pointer_rtx, op)
5604 || reg_mentioned_p (arg_pointer_rtx, op)
5605 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5606 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5607 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5608 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5611 if (GET_CODE (op) == MEM)
5617 /* Match: (mem (reg)). */
5618 if (GET_CODE (ind) == REG)
5624 if (GET_CODE (ind) == PLUS
5625 && GET_CODE (XEXP (ind, 0)) == REG
5626 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5627 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5634 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5635 WB is true if full writeback address modes are allowed and is false
5636 if limited writeback address modes (POST_INC and PRE_DEC) are
5640 arm_coproc_mem_operand (rtx op, bool wb)
5644 /* Reject eliminable registers. */
5645 if (! (reload_in_progress || reload_completed)
5646 && ( reg_mentioned_p (frame_pointer_rtx, op)
5647 || reg_mentioned_p (arg_pointer_rtx, op)
5648 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5649 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5650 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5651 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5654 /* Constants are converted into offsets from labels. */
5655 if (GET_CODE (op) != MEM)
5660 if (reload_completed
5661 && (GET_CODE (ind) == LABEL_REF
5662 || (GET_CODE (ind) == CONST
5663 && GET_CODE (XEXP (ind, 0)) == PLUS
5664 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5665 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5668 /* Match: (mem (reg)). */
5669 if (GET_CODE (ind) == REG)
5670 return arm_address_register_rtx_p (ind, 0);
5672 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5673 acceptable in any case (subject to verification by
5674 arm_address_register_rtx_p). We need WB to be true to accept
5675 PRE_INC and POST_DEC. */
5676 if (GET_CODE (ind) == POST_INC
5677 || GET_CODE (ind) == PRE_DEC
5679 && (GET_CODE (ind) == PRE_INC
5680 || GET_CODE (ind) == POST_DEC)))
5681 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5684 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5685 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5686 && GET_CODE (XEXP (ind, 1)) == PLUS
5687 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5688 ind = XEXP (ind, 1);
5693 if (GET_CODE (ind) == PLUS
5694 && GET_CODE (XEXP (ind, 0)) == REG
5695 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5696 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5697 && INTVAL (XEXP (ind, 1)) > -1024
5698 && INTVAL (XEXP (ind, 1)) < 1024
5699 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5705 /* Return true if X is a register that will be eliminated later on. */
5707 arm_eliminable_register (rtx x)
5709 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5710 || REGNO (x) == ARG_POINTER_REGNUM
5711 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5712 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5715 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5716 coprocessor registers. Otherwise return NO_REGS. */
5719 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5721 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5724 return GENERAL_REGS;
5727 /* Values which must be returned in the most-significant end of the return
5731 arm_return_in_msb (tree valtype)
5733 return (TARGET_AAPCS_BASED
5735 && (AGGREGATE_TYPE_P (valtype)
5736 || TREE_CODE (valtype) == COMPLEX_TYPE));
5739 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5740 Use by the Cirrus Maverick code which has to workaround
5741 a hardware bug triggered by such instructions. */
5743 arm_memory_load_p (rtx insn)
5745 rtx body, lhs, rhs;;
5747 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5750 body = PATTERN (insn);
5752 if (GET_CODE (body) != SET)
5755 lhs = XEXP (body, 0);
5756 rhs = XEXP (body, 1);
5758 lhs = REG_OR_SUBREG_RTX (lhs);
5760 /* If the destination is not a general purpose
5761 register we do not have to worry. */
5762 if (GET_CODE (lhs) != REG
5763 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5766 /* As well as loads from memory we also have to react
5767 to loads of invalid constants which will be turned
5768 into loads from the minipool. */
5769 return (GET_CODE (rhs) == MEM
5770 || GET_CODE (rhs) == SYMBOL_REF
5771 || note_invalid_constants (insn, -1, false));
5774 /* Return TRUE if INSN is a Cirrus instruction. */
5776 arm_cirrus_insn_p (rtx insn)
5778 enum attr_cirrus attr;
5780 /* get_attr cannot accept USE or CLOBBER. */
5782 || GET_CODE (insn) != INSN
5783 || GET_CODE (PATTERN (insn)) == USE
5784 || GET_CODE (PATTERN (insn)) == CLOBBER)
5787 attr = get_attr_cirrus (insn);
5789 return attr != CIRRUS_NOT;
5792 /* Cirrus reorg for invalid instruction combinations. */
5794 cirrus_reorg (rtx first)
5796 enum attr_cirrus attr;
5797 rtx body = PATTERN (first);
5801 /* Any branch must be followed by 2 non Cirrus instructions. */
5802 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5805 t = next_nonnote_insn (first);
5807 if (arm_cirrus_insn_p (t))
5810 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5814 emit_insn_after (gen_nop (), first);
5819 /* (float (blah)) is in parallel with a clobber. */
5820 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5821 body = XVECEXP (body, 0, 0);
5823 if (GET_CODE (body) == SET)
5825 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5827 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5828 be followed by a non Cirrus insn. */
5829 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5831 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5832 emit_insn_after (gen_nop (), first);
5836 else if (arm_memory_load_p (first))
5838 unsigned int arm_regno;
5840 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5841 ldr/cfmv64hr combination where the Rd field is the same
5842 in both instructions must be split with a non Cirrus
5849 /* Get Arm register number for ldr insn. */
5850 if (GET_CODE (lhs) == REG)
5851 arm_regno = REGNO (lhs);
5854 gcc_assert (GET_CODE (rhs) == REG);
5855 arm_regno = REGNO (rhs);
5859 first = next_nonnote_insn (first);
5861 if (! arm_cirrus_insn_p (first))
5864 body = PATTERN (first);
5866 /* (float (blah)) is in parallel with a clobber. */
5867 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5868 body = XVECEXP (body, 0, 0);
5870 if (GET_CODE (body) == FLOAT)
5871 body = XEXP (body, 0);
5873 if (get_attr_cirrus (first) == CIRRUS_MOVE
5874 && GET_CODE (XEXP (body, 1)) == REG
5875 && arm_regno == REGNO (XEXP (body, 1)))
5876 emit_insn_after (gen_nop (), first);
5882 /* get_attr cannot accept USE or CLOBBER. */
5884 || GET_CODE (first) != INSN
5885 || GET_CODE (PATTERN (first)) == USE
5886 || GET_CODE (PATTERN (first)) == CLOBBER)
5889 attr = get_attr_cirrus (first);
5891 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5892 must be followed by a non-coprocessor instruction. */
5893 if (attr == CIRRUS_COMPARE)
5897 t = next_nonnote_insn (first);
5899 if (arm_cirrus_insn_p (t))
5902 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5906 emit_insn_after (gen_nop (), first);
5912 /* Return TRUE if X references a SYMBOL_REF. */
5914 symbol_mentioned_p (rtx x)
5919 if (GET_CODE (x) == SYMBOL_REF)
5922 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5923 are constant offsets, not symbols. */
5924 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5927 fmt = GET_RTX_FORMAT (GET_CODE (x));
5929 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5935 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5936 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5939 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5946 /* Return TRUE if X references a LABEL_REF. */
5948 label_mentioned_p (rtx x)
5953 if (GET_CODE (x) == LABEL_REF)
5956 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5957 instruction, but they are constant offsets, not symbols. */
5958 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5961 fmt = GET_RTX_FORMAT (GET_CODE (x));
5962 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5968 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5969 if (label_mentioned_p (XVECEXP (x, i, j)))
5972 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5980 tls_mentioned_p (rtx x)
5982 switch (GET_CODE (x))
5985 return tls_mentioned_p (XEXP (x, 0));
5988 if (XINT (x, 1) == UNSPEC_TLS)
5996 /* Must not copy a SET whose source operand is PC-relative. */
5999 arm_cannot_copy_insn_p (rtx insn)
6001 rtx pat = PATTERN (insn);
6003 if (GET_CODE (pat) == PARALLEL
6004 && GET_CODE (XVECEXP (pat, 0, 0)) == SET)
6006 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0));
6008 if (GET_CODE (rhs) == UNSPEC
6009 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6012 if (GET_CODE (rhs) == MEM
6013 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6014 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6024 enum rtx_code code = GET_CODE (x);
6041 /* Return 1 if memory locations are adjacent. */
6043 adjacent_mem_locations (rtx a, rtx b)
6045 /* We don't guarantee to preserve the order of these memory refs. */
6046 if (volatile_refs_p (a) || volatile_refs_p (b))
6049 if ((GET_CODE (XEXP (a, 0)) == REG
6050 || (GET_CODE (XEXP (a, 0)) == PLUS
6051 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6052 && (GET_CODE (XEXP (b, 0)) == REG
6053 || (GET_CODE (XEXP (b, 0)) == PLUS
6054 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6056 HOST_WIDE_INT val0 = 0, val1 = 0;
6060 if (GET_CODE (XEXP (a, 0)) == PLUS)
6062 reg0 = XEXP (XEXP (a, 0), 0);
6063 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6068 if (GET_CODE (XEXP (b, 0)) == PLUS)
6070 reg1 = XEXP (XEXP (b, 0), 0);
6071 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6076 /* Don't accept any offset that will require multiple
6077 instructions to handle, since this would cause the
6078 arith_adjacentmem pattern to output an overlong sequence. */
6079 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6082 /* Don't allow an eliminable register: register elimination can make
6083 the offset too large. */
6084 if (arm_eliminable_register (reg0))
6087 val_diff = val1 - val0;
6091 /* If the target has load delay slots, then there's no benefit
6092 to using an ldm instruction unless the offset is zero and
6093 we are optimizing for size. */
6094 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6095 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6096 && (val_diff == 4 || val_diff == -4));
6099 return ((REGNO (reg0) == REGNO (reg1))
6100 && (val_diff == 4 || val_diff == -4));
6107 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6108 HOST_WIDE_INT *load_offset)
6110 int unsorted_regs[4];
6111 HOST_WIDE_INT unsorted_offsets[4];
6116 /* Can only handle 2, 3, or 4 insns at present,
6117 though could be easily extended if required. */
6118 gcc_assert (nops >= 2 && nops <= 4);
6120 /* Loop over the operands and check that the memory references are
6121 suitable (i.e. immediate offsets from the same base register). At
6122 the same time, extract the target register, and the memory
6124 for (i = 0; i < nops; i++)
6129 /* Convert a subreg of a mem into the mem itself. */
6130 if (GET_CODE (operands[nops + i]) == SUBREG)
6131 operands[nops + i] = alter_subreg (operands + (nops + i));
6133 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6135 /* Don't reorder volatile memory references; it doesn't seem worth
6136 looking for the case where the order is ok anyway. */
6137 if (MEM_VOLATILE_P (operands[nops + i]))
6140 offset = const0_rtx;
6142 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6143 || (GET_CODE (reg) == SUBREG
6144 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6145 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6146 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6148 || (GET_CODE (reg) == SUBREG
6149 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6150 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6155 base_reg = REGNO (reg);
6156 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6157 ? REGNO (operands[i])
6158 : REGNO (SUBREG_REG (operands[i])));
6163 if (base_reg != (int) REGNO (reg))
6164 /* Not addressed from the same base register. */
6167 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6168 ? REGNO (operands[i])
6169 : REGNO (SUBREG_REG (operands[i])));
6170 if (unsorted_regs[i] < unsorted_regs[order[0]])
6174 /* If it isn't an integer register, or if it overwrites the
6175 base register but isn't the last insn in the list, then
6176 we can't do this. */
6177 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6178 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6181 unsorted_offsets[i] = INTVAL (offset);
6184 /* Not a suitable memory address. */
6188 /* All the useful information has now been extracted from the
6189 operands into unsorted_regs and unsorted_offsets; additionally,
6190 order[0] has been set to the lowest numbered register in the
6191 list. Sort the registers into order, and check that the memory
6192 offsets are ascending and adjacent. */
6194 for (i = 1; i < nops; i++)
6198 order[i] = order[i - 1];
6199 for (j = 0; j < nops; j++)
6200 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6201 && (order[i] == order[i - 1]
6202 || unsorted_regs[j] < unsorted_regs[order[i]]))
6205 /* Have we found a suitable register? if not, one must be used more
6207 if (order[i] == order[i - 1])
6210 /* Is the memory address adjacent and ascending? */
6211 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6219 for (i = 0; i < nops; i++)
6220 regs[i] = unsorted_regs[order[i]];
6222 *load_offset = unsorted_offsets[order[0]];
6225 if (unsorted_offsets[order[0]] == 0)
6226 return 1; /* ldmia */
6228 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
6229 return 2; /* ldmib */
6231 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
6232 return 3; /* ldmda */
6234 if (unsorted_offsets[order[nops - 1]] == -4)
6235 return 4; /* ldmdb */
6237 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6238 if the offset isn't small enough. The reason 2 ldrs are faster
6239 is because these ARMs are able to do more than one cache access
6240 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6241 whilst the ARM8 has a double bandwidth cache. This means that
6242 these cores can do both an instruction fetch and a data fetch in
6243 a single cycle, so the trick of calculating the address into a
6244 scratch register (one of the result regs) and then doing a load
6245 multiple actually becomes slower (and no smaller in code size).
6246 That is the transformation
6248 ldr rd1, [rbase + offset]
6249 ldr rd2, [rbase + offset + 4]
6253 add rd1, rbase, offset
6254 ldmia rd1, {rd1, rd2}
6256 produces worse code -- '3 cycles + any stalls on rd2' instead of
6257 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6258 access per cycle, the first sequence could never complete in less
6259 than 6 cycles, whereas the ldm sequence would only take 5 and
6260 would make better use of sequential accesses if not hitting the
6263 We cheat here and test 'arm_ld_sched' which we currently know to
6264 only be true for the ARM8, ARM9 and StrongARM. If this ever
6265 changes, then the test below needs to be reworked. */
6266 if (nops == 2 && arm_ld_sched)
6269 /* Can't do it without setting up the offset, only do this if it takes
6270 no more than one insn. */
6271 return (const_ok_for_arm (unsorted_offsets[order[0]])
6272 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
6276 emit_ldm_seq (rtx *operands, int nops)
6280 HOST_WIDE_INT offset;
6284 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6287 strcpy (buf, "ldm%(ia%)\t");
6291 strcpy (buf, "ldm%(ib%)\t");
6295 strcpy (buf, "ldm%(da%)\t");
6299 strcpy (buf, "ldm%(db%)\t");
6304 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6305 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6308 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6309 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6311 output_asm_insn (buf, operands);
6313 strcpy (buf, "ldm%(ia%)\t");
6320 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6321 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6323 for (i = 1; i < nops; i++)
6324 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6325 reg_names[regs[i]]);
6327 strcat (buf, "}\t%@ phole ldm");
6329 output_asm_insn (buf, operands);
6334 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6335 HOST_WIDE_INT * load_offset)
6337 int unsorted_regs[4];
6338 HOST_WIDE_INT unsorted_offsets[4];
6343 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6344 extended if required. */
6345 gcc_assert (nops >= 2 && nops <= 4);
6347 /* Loop over the operands and check that the memory references are
6348 suitable (i.e. immediate offsets from the same base register). At
6349 the same time, extract the target register, and the memory
6351 for (i = 0; i < nops; i++)
6356 /* Convert a subreg of a mem into the mem itself. */
6357 if (GET_CODE (operands[nops + i]) == SUBREG)
6358 operands[nops + i] = alter_subreg (operands + (nops + i));
6360 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6362 /* Don't reorder volatile memory references; it doesn't seem worth
6363 looking for the case where the order is ok anyway. */
6364 if (MEM_VOLATILE_P (operands[nops + i]))
6367 offset = const0_rtx;
6369 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6370 || (GET_CODE (reg) == SUBREG
6371 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6372 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6373 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6375 || (GET_CODE (reg) == SUBREG
6376 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6377 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6382 base_reg = REGNO (reg);
6383 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6384 ? REGNO (operands[i])
6385 : REGNO (SUBREG_REG (operands[i])));
6390 if (base_reg != (int) REGNO (reg))
6391 /* Not addressed from the same base register. */
6394 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6395 ? REGNO (operands[i])
6396 : REGNO (SUBREG_REG (operands[i])));
6397 if (unsorted_regs[i] < unsorted_regs[order[0]])
6401 /* If it isn't an integer register, then we can't do this. */
6402 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6405 unsorted_offsets[i] = INTVAL (offset);
6408 /* Not a suitable memory address. */
6412 /* All the useful information has now been extracted from the
6413 operands into unsorted_regs and unsorted_offsets; additionally,
6414 order[0] has been set to the lowest numbered register in the
6415 list. Sort the registers into order, and check that the memory
6416 offsets are ascending and adjacent. */
6418 for (i = 1; i < nops; i++)
6422 order[i] = order[i - 1];
6423 for (j = 0; j < nops; j++)
6424 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6425 && (order[i] == order[i - 1]
6426 || unsorted_regs[j] < unsorted_regs[order[i]]))
6429 /* Have we found a suitable register? if not, one must be used more
6431 if (order[i] == order[i - 1])
6434 /* Is the memory address adjacent and ascending? */
6435 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6443 for (i = 0; i < nops; i++)
6444 regs[i] = unsorted_regs[order[i]];
6446 *load_offset = unsorted_offsets[order[0]];
6449 if (unsorted_offsets[order[0]] == 0)
6450 return 1; /* stmia */
6452 if (unsorted_offsets[order[0]] == 4)
6453 return 2; /* stmib */
6455 if (unsorted_offsets[order[nops - 1]] == 0)
6456 return 3; /* stmda */
6458 if (unsorted_offsets[order[nops - 1]] == -4)
6459 return 4; /* stmdb */
6465 emit_stm_seq (rtx *operands, int nops)
6469 HOST_WIDE_INT offset;
6473 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6476 strcpy (buf, "stm%(ia%)\t");
6480 strcpy (buf, "stm%(ib%)\t");
6484 strcpy (buf, "stm%(da%)\t");
6488 strcpy (buf, "stm%(db%)\t");
6495 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6496 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6498 for (i = 1; i < nops; i++)
6499 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6500 reg_names[regs[i]]);
6502 strcat (buf, "}\t%@ phole stm");
6504 output_asm_insn (buf, operands);
6508 /* Routines for use in generating RTL. */
6511 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6512 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6514 HOST_WIDE_INT offset = *offsetp;
6517 int sign = up ? 1 : -1;
6520 /* XScale has load-store double instructions, but they have stricter
6521 alignment requirements than load-store multiple, so we cannot
6524 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6525 the pipeline until completion.
6533 An ldr instruction takes 1-3 cycles, but does not block the
6542 Best case ldr will always win. However, the more ldr instructions
6543 we issue, the less likely we are to be able to schedule them well.
6544 Using ldr instructions also increases code size.
6546 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6547 for counts of 3 or 4 regs. */
6548 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6554 for (i = 0; i < count; i++)
6556 addr = plus_constant (from, i * 4 * sign);
6557 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6558 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6564 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6574 result = gen_rtx_PARALLEL (VOIDmode,
6575 rtvec_alloc (count + (write_back ? 1 : 0)));
6578 XVECEXP (result, 0, 0)
6579 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6584 for (j = 0; i < count; i++, j++)
6586 addr = plus_constant (from, j * 4 * sign);
6587 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6588 XVECEXP (result, 0, i)
6589 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6600 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6601 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6603 HOST_WIDE_INT offset = *offsetp;
6606 int sign = up ? 1 : -1;
6609 /* See arm_gen_load_multiple for discussion of
6610 the pros/cons of ldm/stm usage for XScale. */
6611 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6617 for (i = 0; i < count; i++)
6619 addr = plus_constant (to, i * 4 * sign);
6620 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6621 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6627 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6637 result = gen_rtx_PARALLEL (VOIDmode,
6638 rtvec_alloc (count + (write_back ? 1 : 0)));
6641 XVECEXP (result, 0, 0)
6642 = gen_rtx_SET (VOIDmode, to,
6643 plus_constant (to, count * 4 * sign));
6648 for (j = 0; i < count; i++, j++)
6650 addr = plus_constant (to, j * 4 * sign);
6651 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6652 XVECEXP (result, 0, i)
6653 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6664 arm_gen_movmemqi (rtx *operands)
6666 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6667 HOST_WIDE_INT srcoffset, dstoffset;
6669 rtx src, dst, srcbase, dstbase;
6670 rtx part_bytes_reg = NULL;
6673 if (GET_CODE (operands[2]) != CONST_INT
6674 || GET_CODE (operands[3]) != CONST_INT
6675 || INTVAL (operands[2]) > 64
6676 || INTVAL (operands[3]) & 3)
6679 dstbase = operands[0];
6680 srcbase = operands[1];
6682 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6683 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6685 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6686 out_words_to_go = INTVAL (operands[2]) / 4;
6687 last_bytes = INTVAL (operands[2]) & 3;
6688 dstoffset = srcoffset = 0;
6690 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6691 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6693 for (i = 0; in_words_to_go >= 2; i+=4)
6695 if (in_words_to_go > 4)
6696 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6697 srcbase, &srcoffset));
6699 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6700 FALSE, srcbase, &srcoffset));
6702 if (out_words_to_go)
6704 if (out_words_to_go > 4)
6705 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6706 dstbase, &dstoffset));
6707 else if (out_words_to_go != 1)
6708 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6712 dstbase, &dstoffset));
6715 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6716 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6717 if (last_bytes != 0)
6719 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6725 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6726 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6729 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6730 if (out_words_to_go)
6734 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6735 sreg = copy_to_reg (mem);
6737 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6738 emit_move_insn (mem, sreg);
6741 gcc_assert (!in_words_to_go); /* Sanity check */
6746 gcc_assert (in_words_to_go > 0);
6748 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6749 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6752 gcc_assert (!last_bytes || part_bytes_reg);
6754 if (BYTES_BIG_ENDIAN && last_bytes)
6756 rtx tmp = gen_reg_rtx (SImode);
6758 /* The bytes we want are in the top end of the word. */
6759 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6760 GEN_INT (8 * (4 - last_bytes))));
6761 part_bytes_reg = tmp;
6765 mem = adjust_automodify_address (dstbase, QImode,
6766 plus_constant (dst, last_bytes - 1),
6767 dstoffset + last_bytes - 1);
6768 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6772 tmp = gen_reg_rtx (SImode);
6773 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6774 part_bytes_reg = tmp;
6783 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6784 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6788 rtx tmp = gen_reg_rtx (SImode);
6789 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6790 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6791 part_bytes_reg = tmp;
6798 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6799 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6806 /* Select a dominance comparison mode if possible for a test of the general
6807 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6808 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6809 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6810 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6811 In all cases OP will be either EQ or NE, but we don't need to know which
6812 here. If we are unable to support a dominance comparison we return
6813 CC mode. This will then fail to match for the RTL expressions that
6814 generate this call. */
6816 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6818 enum rtx_code cond1, cond2;
6821 /* Currently we will probably get the wrong result if the individual
6822 comparisons are not simple. This also ensures that it is safe to
6823 reverse a comparison if necessary. */
6824 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6826 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6830 /* The if_then_else variant of this tests the second condition if the
6831 first passes, but is true if the first fails. Reverse the first
6832 condition to get a true "inclusive-or" expression. */
6833 if (cond_or == DOM_CC_NX_OR_Y)
6834 cond1 = reverse_condition (cond1);
6836 /* If the comparisons are not equal, and one doesn't dominate the other,
6837 then we can't do this. */
6839 && !comparison_dominates_p (cond1, cond2)
6840 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6845 enum rtx_code temp = cond1;
6853 if (cond_or == DOM_CC_X_AND_Y)
6858 case EQ: return CC_DEQmode;
6859 case LE: return CC_DLEmode;
6860 case LEU: return CC_DLEUmode;
6861 case GE: return CC_DGEmode;
6862 case GEU: return CC_DGEUmode;
6863 default: gcc_unreachable ();
6867 if (cond_or == DOM_CC_X_AND_Y)
6883 if (cond_or == DOM_CC_X_AND_Y)
6899 if (cond_or == DOM_CC_X_AND_Y)
6915 if (cond_or == DOM_CC_X_AND_Y)
6930 /* The remaining cases only occur when both comparisons are the
6933 gcc_assert (cond1 == cond2);
6937 gcc_assert (cond1 == cond2);
6941 gcc_assert (cond1 == cond2);
6945 gcc_assert (cond1 == cond2);
6949 gcc_assert (cond1 == cond2);
6958 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6960 /* All floating point compares return CCFP if it is an equality
6961 comparison, and CCFPE otherwise. */
6962 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6982 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6991 /* A compare with a shifted operand. Because of canonicalization, the
6992 comparison will have to be swapped when we emit the assembler. */
6993 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6994 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6995 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6996 || GET_CODE (x) == ROTATERT))
6999 /* This operation is performed swapped, but since we only rely on the Z
7000 flag we don't need an additional mode. */
7001 if (GET_MODE (y) == SImode && REG_P (y)
7002 && GET_CODE (x) == NEG
7003 && (op == EQ || op == NE))
7006 /* This is a special case that is used by combine to allow a
7007 comparison of a shifted byte load to be split into a zero-extend
7008 followed by a comparison of the shifted integer (only valid for
7009 equalities and unsigned inequalities). */
7010 if (GET_MODE (x) == SImode
7011 && GET_CODE (x) == ASHIFT
7012 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7013 && GET_CODE (XEXP (x, 0)) == SUBREG
7014 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7015 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7016 && (op == EQ || op == NE
7017 || op == GEU || op == GTU || op == LTU || op == LEU)
7018 && GET_CODE (y) == CONST_INT)
7021 /* A construct for a conditional compare, if the false arm contains
7022 0, then both conditions must be true, otherwise either condition
7023 must be true. Not all conditions are possible, so CCmode is
7024 returned if it can't be done. */
7025 if (GET_CODE (x) == IF_THEN_ELSE
7026 && (XEXP (x, 2) == const0_rtx
7027 || XEXP (x, 2) == const1_rtx)
7028 && COMPARISON_P (XEXP (x, 0))
7029 && COMPARISON_P (XEXP (x, 1)))
7030 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7031 INTVAL (XEXP (x, 2)));
7033 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7034 if (GET_CODE (x) == AND
7035 && COMPARISON_P (XEXP (x, 0))
7036 && COMPARISON_P (XEXP (x, 1)))
7037 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7040 if (GET_CODE (x) == IOR
7041 && COMPARISON_P (XEXP (x, 0))
7042 && COMPARISON_P (XEXP (x, 1)))
7043 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7046 /* An operation (on Thumb) where we want to test for a single bit.
7047 This is done by shifting that bit up into the top bit of a
7048 scratch register; we can then branch on the sign bit. */
7050 && GET_MODE (x) == SImode
7051 && (op == EQ || op == NE)
7052 && GET_CODE (x) == ZERO_EXTRACT
7053 && XEXP (x, 1) == const1_rtx)
7056 /* An operation that sets the condition codes as a side-effect, the
7057 V flag is not set correctly, so we can only use comparisons where
7058 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7060 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7061 if (GET_MODE (x) == SImode
7063 && (op == EQ || op == NE || op == LT || op == GE)
7064 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7065 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7066 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7067 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7068 || GET_CODE (x) == LSHIFTRT
7069 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7070 || GET_CODE (x) == ROTATERT
7071 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
7074 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7077 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7078 && GET_CODE (x) == PLUS
7079 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7085 /* X and Y are two things to compare using CODE. Emit the compare insn and
7086 return the rtx for register 0 in the proper mode. FP means this is a
7087 floating point compare: I don't think that it is needed on the arm. */
7089 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
7091 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
7092 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
7094 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
7099 /* Generate a sequence of insns that will generate the correct return
7100 address mask depending on the physical architecture that the program
7103 arm_gen_return_addr_mask (void)
7105 rtx reg = gen_reg_rtx (Pmode);
7107 emit_insn (gen_return_addr_mask (reg));
7112 arm_reload_in_hi (rtx *operands)
7114 rtx ref = operands[1];
7116 HOST_WIDE_INT offset = 0;
7118 if (GET_CODE (ref) == SUBREG)
7120 offset = SUBREG_BYTE (ref);
7121 ref = SUBREG_REG (ref);
7124 if (GET_CODE (ref) == REG)
7126 /* We have a pseudo which has been spilt onto the stack; there
7127 are two cases here: the first where there is a simple
7128 stack-slot replacement and a second where the stack-slot is
7129 out of range, or is used as a subreg. */
7130 if (reg_equiv_mem[REGNO (ref)])
7132 ref = reg_equiv_mem[REGNO (ref)];
7133 base = find_replacement (&XEXP (ref, 0));
7136 /* The slot is out of range, or was dressed up in a SUBREG. */
7137 base = reg_equiv_address[REGNO (ref)];
7140 base = find_replacement (&XEXP (ref, 0));
7142 /* Handle the case where the address is too complex to be offset by 1. */
7143 if (GET_CODE (base) == MINUS
7144 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7146 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7148 emit_set_insn (base_plus, base);
7151 else if (GET_CODE (base) == PLUS)
7153 /* The addend must be CONST_INT, or we would have dealt with it above. */
7154 HOST_WIDE_INT hi, lo;
7156 offset += INTVAL (XEXP (base, 1));
7157 base = XEXP (base, 0);
7159 /* Rework the address into a legal sequence of insns. */
7160 /* Valid range for lo is -4095 -> 4095 */
7163 : -((-offset) & 0xfff));
7165 /* Corner case, if lo is the max offset then we would be out of range
7166 once we have added the additional 1 below, so bump the msb into the
7167 pre-loading insn(s). */
7171 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7172 ^ (HOST_WIDE_INT) 0x80000000)
7173 - (HOST_WIDE_INT) 0x80000000);
7175 gcc_assert (hi + lo == offset);
7179 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7181 /* Get the base address; addsi3 knows how to handle constants
7182 that require more than one insn. */
7183 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7189 /* Operands[2] may overlap operands[0] (though it won't overlap
7190 operands[1]), that's why we asked for a DImode reg -- so we can
7191 use the bit that does not overlap. */
7192 if (REGNO (operands[2]) == REGNO (operands[0]))
7193 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7195 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7197 emit_insn (gen_zero_extendqisi2 (scratch,
7198 gen_rtx_MEM (QImode,
7199 plus_constant (base,
7201 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
7202 gen_rtx_MEM (QImode,
7203 plus_constant (base,
7205 if (!BYTES_BIG_ENDIAN)
7206 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7207 gen_rtx_IOR (SImode,
7210 gen_rtx_SUBREG (SImode, operands[0], 0),
7214 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7215 gen_rtx_IOR (SImode,
7216 gen_rtx_ASHIFT (SImode, scratch,
7218 gen_rtx_SUBREG (SImode, operands[0], 0)));
7221 /* Handle storing a half-word to memory during reload by synthesizing as two
7222 byte stores. Take care not to clobber the input values until after we
7223 have moved them somewhere safe. This code assumes that if the DImode
7224 scratch in operands[2] overlaps either the input value or output address
7225 in some way, then that value must die in this insn (we absolutely need
7226 two scratch registers for some corner cases). */
7228 arm_reload_out_hi (rtx *operands)
7230 rtx ref = operands[0];
7231 rtx outval = operands[1];
7233 HOST_WIDE_INT offset = 0;
7235 if (GET_CODE (ref) == SUBREG)
7237 offset = SUBREG_BYTE (ref);
7238 ref = SUBREG_REG (ref);
7241 if (GET_CODE (ref) == REG)
7243 /* We have a pseudo which has been spilt onto the stack; there
7244 are two cases here: the first where there is a simple
7245 stack-slot replacement and a second where the stack-slot is
7246 out of range, or is used as a subreg. */
7247 if (reg_equiv_mem[REGNO (ref)])
7249 ref = reg_equiv_mem[REGNO (ref)];
7250 base = find_replacement (&XEXP (ref, 0));
7253 /* The slot is out of range, or was dressed up in a SUBREG. */
7254 base = reg_equiv_address[REGNO (ref)];
7257 base = find_replacement (&XEXP (ref, 0));
7259 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7261 /* Handle the case where the address is too complex to be offset by 1. */
7262 if (GET_CODE (base) == MINUS
7263 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7265 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7267 /* Be careful not to destroy OUTVAL. */
7268 if (reg_overlap_mentioned_p (base_plus, outval))
7270 /* Updating base_plus might destroy outval, see if we can
7271 swap the scratch and base_plus. */
7272 if (!reg_overlap_mentioned_p (scratch, outval))
7275 scratch = base_plus;
7280 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7282 /* Be conservative and copy OUTVAL into the scratch now,
7283 this should only be necessary if outval is a subreg
7284 of something larger than a word. */
7285 /* XXX Might this clobber base? I can't see how it can,
7286 since scratch is known to overlap with OUTVAL, and
7287 must be wider than a word. */
7288 emit_insn (gen_movhi (scratch_hi, outval));
7289 outval = scratch_hi;
7293 emit_set_insn (base_plus, base);
7296 else if (GET_CODE (base) == PLUS)
7298 /* The addend must be CONST_INT, or we would have dealt with it above. */
7299 HOST_WIDE_INT hi, lo;
7301 offset += INTVAL (XEXP (base, 1));
7302 base = XEXP (base, 0);
7304 /* Rework the address into a legal sequence of insns. */
7305 /* Valid range for lo is -4095 -> 4095 */
7308 : -((-offset) & 0xfff));
7310 /* Corner case, if lo is the max offset then we would be out of range
7311 once we have added the additional 1 below, so bump the msb into the
7312 pre-loading insn(s). */
7316 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7317 ^ (HOST_WIDE_INT) 0x80000000)
7318 - (HOST_WIDE_INT) 0x80000000);
7320 gcc_assert (hi + lo == offset);
7324 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7326 /* Be careful not to destroy OUTVAL. */
7327 if (reg_overlap_mentioned_p (base_plus, outval))
7329 /* Updating base_plus might destroy outval, see if we
7330 can swap the scratch and base_plus. */
7331 if (!reg_overlap_mentioned_p (scratch, outval))
7334 scratch = base_plus;
7339 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7341 /* Be conservative and copy outval into scratch now,
7342 this should only be necessary if outval is a
7343 subreg of something larger than a word. */
7344 /* XXX Might this clobber base? I can't see how it
7345 can, since scratch is known to overlap with
7347 emit_insn (gen_movhi (scratch_hi, outval));
7348 outval = scratch_hi;
7352 /* Get the base address; addsi3 knows how to handle constants
7353 that require more than one insn. */
7354 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7360 if (BYTES_BIG_ENDIAN)
7362 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7363 plus_constant (base, offset + 1)),
7364 gen_lowpart (QImode, outval)));
7365 emit_insn (gen_lshrsi3 (scratch,
7366 gen_rtx_SUBREG (SImode, outval, 0),
7368 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7369 gen_lowpart (QImode, scratch)));
7373 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7374 gen_lowpart (QImode, outval)));
7375 emit_insn (gen_lshrsi3 (scratch,
7376 gen_rtx_SUBREG (SImode, outval, 0),
7378 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7379 plus_constant (base, offset + 1)),
7380 gen_lowpart (QImode, scratch)));
7384 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7385 (padded to the size of a word) should be passed in a register. */
7388 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7390 if (TARGET_AAPCS_BASED)
7391 return must_pass_in_stack_var_size (mode, type);
7393 return must_pass_in_stack_var_size_or_pad (mode, type);
7397 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7398 Return true if an argument passed on the stack should be padded upwards,
7399 i.e. if the least-significant byte has useful data.
7400 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7401 aggregate types are placed in the lowest memory address. */
7404 arm_pad_arg_upward (enum machine_mode mode, tree type)
7406 if (!TARGET_AAPCS_BASED)
7407 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7409 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7416 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7417 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7418 byte of the register has useful data, and return the opposite if the
7419 most significant byte does.
7420 For AAPCS, small aggregates and small complex types are always padded
7424 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7425 tree type, int first ATTRIBUTE_UNUSED)
7427 if (TARGET_AAPCS_BASED
7429 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7430 && int_size_in_bytes (type) <= 4)
7433 /* Otherwise, use default padding. */
7434 return !BYTES_BIG_ENDIAN;
7438 /* Print a symbolic form of X to the debug file, F. */
7440 arm_print_value (FILE *f, rtx x)
7442 switch (GET_CODE (x))
7445 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7449 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7457 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7459 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7460 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7468 fprintf (f, "\"%s\"", XSTR (x, 0));
7472 fprintf (f, "`%s'", XSTR (x, 0));
7476 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7480 arm_print_value (f, XEXP (x, 0));
7484 arm_print_value (f, XEXP (x, 0));
7486 arm_print_value (f, XEXP (x, 1));
7494 fprintf (f, "????");
7499 /* Routines for manipulation of the constant pool. */
7501 /* Arm instructions cannot load a large constant directly into a
7502 register; they have to come from a pc relative load. The constant
7503 must therefore be placed in the addressable range of the pc
7504 relative load. Depending on the precise pc relative load
7505 instruction the range is somewhere between 256 bytes and 4k. This
7506 means that we often have to dump a constant inside a function, and
7507 generate code to branch around it.
7509 It is important to minimize this, since the branches will slow
7510 things down and make the code larger.
7512 Normally we can hide the table after an existing unconditional
7513 branch so that there is no interruption of the flow, but in the
7514 worst case the code looks like this:
7532 We fix this by performing a scan after scheduling, which notices
7533 which instructions need to have their operands fetched from the
7534 constant table and builds the table.
7536 The algorithm starts by building a table of all the constants that
7537 need fixing up and all the natural barriers in the function (places
7538 where a constant table can be dropped without breaking the flow).
7539 For each fixup we note how far the pc-relative replacement will be
7540 able to reach and the offset of the instruction into the function.
7542 Having built the table we then group the fixes together to form
7543 tables that are as large as possible (subject to addressing
7544 constraints) and emit each table of constants after the last
7545 barrier that is within range of all the instructions in the group.
7546 If a group does not contain a barrier, then we forcibly create one
7547 by inserting a jump instruction into the flow. Once the table has
7548 been inserted, the insns are then modified to reference the
7549 relevant entry in the pool.
7551 Possible enhancements to the algorithm (not implemented) are:
7553 1) For some processors and object formats, there may be benefit in
7554 aligning the pools to the start of cache lines; this alignment
7555 would need to be taken into account when calculating addressability
7558 /* These typedefs are located at the start of this file, so that
7559 they can be used in the prototypes there. This comment is to
7560 remind readers of that fact so that the following structures
7561 can be understood more easily.
7563 typedef struct minipool_node Mnode;
7564 typedef struct minipool_fixup Mfix; */
7566 struct minipool_node
7568 /* Doubly linked chain of entries. */
7571 /* The maximum offset into the code that this entry can be placed. While
7572 pushing fixes for forward references, all entries are sorted in order
7573 of increasing max_address. */
7574 HOST_WIDE_INT max_address;
7575 /* Similarly for an entry inserted for a backwards ref. */
7576 HOST_WIDE_INT min_address;
7577 /* The number of fixes referencing this entry. This can become zero
7578 if we "unpush" an entry. In this case we ignore the entry when we
7579 come to emit the code. */
7581 /* The offset from the start of the minipool. */
7582 HOST_WIDE_INT offset;
7583 /* The value in table. */
7585 /* The mode of value. */
7586 enum machine_mode mode;
7587 /* The size of the value. With iWMMXt enabled
7588 sizes > 4 also imply an alignment of 8-bytes. */
7592 struct minipool_fixup
7596 HOST_WIDE_INT address;
7598 enum machine_mode mode;
7602 HOST_WIDE_INT forwards;
7603 HOST_WIDE_INT backwards;
7606 /* Fixes less than a word need padding out to a word boundary. */
7607 #define MINIPOOL_FIX_SIZE(mode) \
7608 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7610 static Mnode * minipool_vector_head;
7611 static Mnode * minipool_vector_tail;
7612 static rtx minipool_vector_label;
7613 static int minipool_pad;
7615 /* The linked list of all minipool fixes required for this function. */
7616 Mfix * minipool_fix_head;
7617 Mfix * minipool_fix_tail;
7618 /* The fix entry for the current minipool, once it has been placed. */
7619 Mfix * minipool_barrier;
7621 /* Determines if INSN is the start of a jump table. Returns the end
7622 of the TABLE or NULL_RTX. */
7624 is_jump_table (rtx insn)
7628 if (GET_CODE (insn) == JUMP_INSN
7629 && JUMP_LABEL (insn) != NULL
7630 && ((table = next_real_insn (JUMP_LABEL (insn)))
7631 == next_real_insn (insn))
7633 && GET_CODE (table) == JUMP_INSN
7634 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7635 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7641 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7642 #define JUMP_TABLES_IN_TEXT_SECTION 0
7645 static HOST_WIDE_INT
7646 get_jump_table_size (rtx insn)
7648 /* ADDR_VECs only take room if read-only data does into the text
7650 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7652 rtx body = PATTERN (insn);
7653 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7655 HOST_WIDE_INT modesize;
7657 modesize = GET_MODE_SIZE (GET_MODE (body));
7658 size = modesize * XVECLEN (body, elt);
7662 /* Round up size of TBB table to a halfword boundary. */
7663 size = (size + 1) & ~(HOST_WIDE_INT)1;
7666 /* No padding necessary for TBH. */
7669 /* Add two bytes for alignment on Thumb. */
7682 /* Move a minipool fix MP from its current location to before MAX_MP.
7683 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7684 constraints may need updating. */
7686 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7687 HOST_WIDE_INT max_address)
7689 /* The code below assumes these are different. */
7690 gcc_assert (mp != max_mp);
7694 if (max_address < mp->max_address)
7695 mp->max_address = max_address;
7699 if (max_address > max_mp->max_address - mp->fix_size)
7700 mp->max_address = max_mp->max_address - mp->fix_size;
7702 mp->max_address = max_address;
7704 /* Unlink MP from its current position. Since max_mp is non-null,
7705 mp->prev must be non-null. */
7706 mp->prev->next = mp->next;
7707 if (mp->next != NULL)
7708 mp->next->prev = mp->prev;
7710 minipool_vector_tail = mp->prev;
7712 /* Re-insert it before MAX_MP. */
7714 mp->prev = max_mp->prev;
7717 if (mp->prev != NULL)
7718 mp->prev->next = mp;
7720 minipool_vector_head = mp;
7723 /* Save the new entry. */
7726 /* Scan over the preceding entries and adjust their addresses as
7728 while (mp->prev != NULL
7729 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7731 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7738 /* Add a constant to the minipool for a forward reference. Returns the
7739 node added or NULL if the constant will not fit in this pool. */
7741 add_minipool_forward_ref (Mfix *fix)
7743 /* If set, max_mp is the first pool_entry that has a lower
7744 constraint than the one we are trying to add. */
7745 Mnode * max_mp = NULL;
7746 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
7749 /* If the minipool starts before the end of FIX->INSN then this FIX
7750 can not be placed into the current pool. Furthermore, adding the
7751 new constant pool entry may cause the pool to start FIX_SIZE bytes
7753 if (minipool_vector_head &&
7754 (fix->address + get_attr_length (fix->insn)
7755 >= minipool_vector_head->max_address - fix->fix_size))
7758 /* Scan the pool to see if a constant with the same value has
7759 already been added. While we are doing this, also note the
7760 location where we must insert the constant if it doesn't already
7762 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7764 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7765 && fix->mode == mp->mode
7766 && (GET_CODE (fix->value) != CODE_LABEL
7767 || (CODE_LABEL_NUMBER (fix->value)
7768 == CODE_LABEL_NUMBER (mp->value)))
7769 && rtx_equal_p (fix->value, mp->value))
7771 /* More than one fix references this entry. */
7773 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7776 /* Note the insertion point if necessary. */
7778 && mp->max_address > max_address)
7781 /* If we are inserting an 8-bytes aligned quantity and
7782 we have not already found an insertion point, then
7783 make sure that all such 8-byte aligned quantities are
7784 placed at the start of the pool. */
7785 if (ARM_DOUBLEWORD_ALIGN
7787 && fix->fix_size == 8
7788 && mp->fix_size != 8)
7791 max_address = mp->max_address;
7795 /* The value is not currently in the minipool, so we need to create
7796 a new entry for it. If MAX_MP is NULL, the entry will be put on
7797 the end of the list since the placement is less constrained than
7798 any existing entry. Otherwise, we insert the new fix before
7799 MAX_MP and, if necessary, adjust the constraints on the other
7802 mp->fix_size = fix->fix_size;
7803 mp->mode = fix->mode;
7804 mp->value = fix->value;
7806 /* Not yet required for a backwards ref. */
7807 mp->min_address = -65536;
7811 mp->max_address = max_address;
7813 mp->prev = minipool_vector_tail;
7815 if (mp->prev == NULL)
7817 minipool_vector_head = mp;
7818 minipool_vector_label = gen_label_rtx ();
7821 mp->prev->next = mp;
7823 minipool_vector_tail = mp;
7827 if (max_address > max_mp->max_address - mp->fix_size)
7828 mp->max_address = max_mp->max_address - mp->fix_size;
7830 mp->max_address = max_address;
7833 mp->prev = max_mp->prev;
7835 if (mp->prev != NULL)
7836 mp->prev->next = mp;
7838 minipool_vector_head = mp;
7841 /* Save the new entry. */
7844 /* Scan over the preceding entries and adjust their addresses as
7846 while (mp->prev != NULL
7847 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7849 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7857 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7858 HOST_WIDE_INT min_address)
7860 HOST_WIDE_INT offset;
7862 /* The code below assumes these are different. */
7863 gcc_assert (mp != min_mp);
7867 if (min_address > mp->min_address)
7868 mp->min_address = min_address;
7872 /* We will adjust this below if it is too loose. */
7873 mp->min_address = min_address;
7875 /* Unlink MP from its current position. Since min_mp is non-null,
7876 mp->next must be non-null. */
7877 mp->next->prev = mp->prev;
7878 if (mp->prev != NULL)
7879 mp->prev->next = mp->next;
7881 minipool_vector_head = mp->next;
7883 /* Reinsert it after MIN_MP. */
7885 mp->next = min_mp->next;
7887 if (mp->next != NULL)
7888 mp->next->prev = mp;
7890 minipool_vector_tail = mp;
7896 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7898 mp->offset = offset;
7899 if (mp->refcount > 0)
7900 offset += mp->fix_size;
7902 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7903 mp->next->min_address = mp->min_address + mp->fix_size;
7909 /* Add a constant to the minipool for a backward reference. Returns the
7910 node added or NULL if the constant will not fit in this pool.
7912 Note that the code for insertion for a backwards reference can be
7913 somewhat confusing because the calculated offsets for each fix do
7914 not take into account the size of the pool (which is still under
7917 add_minipool_backward_ref (Mfix *fix)
7919 /* If set, min_mp is the last pool_entry that has a lower constraint
7920 than the one we are trying to add. */
7921 Mnode *min_mp = NULL;
7922 /* This can be negative, since it is only a constraint. */
7923 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7926 /* If we can't reach the current pool from this insn, or if we can't
7927 insert this entry at the end of the pool without pushing other
7928 fixes out of range, then we don't try. This ensures that we
7929 can't fail later on. */
7930 if (min_address >= minipool_barrier->address
7931 || (minipool_vector_tail->min_address + fix->fix_size
7932 >= minipool_barrier->address))
7935 /* Scan the pool to see if a constant with the same value has
7936 already been added. While we are doing this, also note the
7937 location where we must insert the constant if it doesn't already
7939 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7941 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7942 && fix->mode == mp->mode
7943 && (GET_CODE (fix->value) != CODE_LABEL
7944 || (CODE_LABEL_NUMBER (fix->value)
7945 == CODE_LABEL_NUMBER (mp->value)))
7946 && rtx_equal_p (fix->value, mp->value)
7947 /* Check that there is enough slack to move this entry to the
7948 end of the table (this is conservative). */
7950 > (minipool_barrier->address
7951 + minipool_vector_tail->offset
7952 + minipool_vector_tail->fix_size)))
7955 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7959 mp->min_address += fix->fix_size;
7962 /* Note the insertion point if necessary. */
7963 if (mp->min_address < min_address)
7965 /* For now, we do not allow the insertion of 8-byte alignment
7966 requiring nodes anywhere but at the start of the pool. */
7967 if (ARM_DOUBLEWORD_ALIGN
7968 && fix->fix_size == 8 && mp->fix_size != 8)
7973 else if (mp->max_address
7974 < minipool_barrier->address + mp->offset + fix->fix_size)
7976 /* Inserting before this entry would push the fix beyond
7977 its maximum address (which can happen if we have
7978 re-located a forwards fix); force the new fix to come
7981 min_address = mp->min_address + fix->fix_size;
7983 /* If we are inserting an 8-bytes aligned quantity and
7984 we have not already found an insertion point, then
7985 make sure that all such 8-byte aligned quantities are
7986 placed at the start of the pool. */
7987 else if (ARM_DOUBLEWORD_ALIGN
7989 && fix->fix_size == 8
7990 && mp->fix_size < 8)
7993 min_address = mp->min_address + fix->fix_size;
7998 /* We need to create a new entry. */
8000 mp->fix_size = fix->fix_size;
8001 mp->mode = fix->mode;
8002 mp->value = fix->value;
8004 mp->max_address = minipool_barrier->address + 65536;
8006 mp->min_address = min_address;
8011 mp->next = minipool_vector_head;
8013 if (mp->next == NULL)
8015 minipool_vector_tail = mp;
8016 minipool_vector_label = gen_label_rtx ();
8019 mp->next->prev = mp;
8021 minipool_vector_head = mp;
8025 mp->next = min_mp->next;
8029 if (mp->next != NULL)
8030 mp->next->prev = mp;
8032 minipool_vector_tail = mp;
8035 /* Save the new entry. */
8043 /* Scan over the following entries and adjust their offsets. */
8044 while (mp->next != NULL)
8046 if (mp->next->min_address < mp->min_address + mp->fix_size)
8047 mp->next->min_address = mp->min_address + mp->fix_size;
8050 mp->next->offset = mp->offset + mp->fix_size;
8052 mp->next->offset = mp->offset;
8061 assign_minipool_offsets (Mfix *barrier)
8063 HOST_WIDE_INT offset = 0;
8066 minipool_barrier = barrier;
8068 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8070 mp->offset = offset;
8072 if (mp->refcount > 0)
8073 offset += mp->fix_size;
8077 /* Output the literal table */
8079 dump_minipool (rtx scan)
8085 if (ARM_DOUBLEWORD_ALIGN)
8086 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8087 if (mp->refcount > 0 && mp->fix_size == 8)
8095 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8096 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
8098 scan = emit_label_after (gen_label_rtx (), scan);
8099 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
8100 scan = emit_label_after (minipool_vector_label, scan);
8102 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8104 if (mp->refcount > 0)
8109 ";; Offset %u, min %ld, max %ld ",
8110 (unsigned) mp->offset, (unsigned long) mp->min_address,
8111 (unsigned long) mp->max_address);
8112 arm_print_value (dump_file, mp->value);
8113 fputc ('\n', dump_file);
8116 switch (mp->fix_size)
8118 #ifdef HAVE_consttable_1
8120 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8124 #ifdef HAVE_consttable_2
8126 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8130 #ifdef HAVE_consttable_4
8132 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8136 #ifdef HAVE_consttable_8
8138 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8151 minipool_vector_head = minipool_vector_tail = NULL;
8152 scan = emit_insn_after (gen_consttable_end (), scan);
8153 scan = emit_barrier_after (scan);
8156 /* Return the cost of forcibly inserting a barrier after INSN. */
8158 arm_barrier_cost (rtx insn)
8160 /* Basing the location of the pool on the loop depth is preferable,
8161 but at the moment, the basic block information seems to be
8162 corrupt by this stage of the compilation. */
8164 rtx next = next_nonnote_insn (insn);
8166 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8169 switch (GET_CODE (insn))
8172 /* It will always be better to place the table before the label, rather
8181 return base_cost - 10;
8184 return base_cost + 10;
8188 /* Find the best place in the insn stream in the range
8189 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8190 Create the barrier by inserting a jump and add a new fix entry for
8193 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
8195 HOST_WIDE_INT count = 0;
8197 rtx from = fix->insn;
8198 /* The instruction after which we will insert the jump. */
8199 rtx selected = NULL;
8201 /* The address at which the jump instruction will be placed. */
8202 HOST_WIDE_INT selected_address;
8204 HOST_WIDE_INT max_count = max_address - fix->address;
8205 rtx label = gen_label_rtx ();
8207 selected_cost = arm_barrier_cost (from);
8208 selected_address = fix->address;
8210 while (from && count < max_count)
8215 /* This code shouldn't have been called if there was a natural barrier
8217 gcc_assert (GET_CODE (from) != BARRIER);
8219 /* Count the length of this insn. */
8220 count += get_attr_length (from);
8222 /* If there is a jump table, add its length. */
8223 tmp = is_jump_table (from);
8226 count += get_jump_table_size (tmp);
8228 /* Jump tables aren't in a basic block, so base the cost on
8229 the dispatch insn. If we select this location, we will
8230 still put the pool after the table. */
8231 new_cost = arm_barrier_cost (from);
8233 if (count < max_count
8234 && (!selected || new_cost <= selected_cost))
8237 selected_cost = new_cost;
8238 selected_address = fix->address + count;
8241 /* Continue after the dispatch table. */
8242 from = NEXT_INSN (tmp);
8246 new_cost = arm_barrier_cost (from);
8248 if (count < max_count
8249 && (!selected || new_cost <= selected_cost))
8252 selected_cost = new_cost;
8253 selected_address = fix->address + count;
8256 from = NEXT_INSN (from);
8259 /* Make sure that we found a place to insert the jump. */
8260 gcc_assert (selected);
8262 /* Create a new JUMP_INSN that branches around a barrier. */
8263 from = emit_jump_insn_after (gen_jump (label), selected);
8264 JUMP_LABEL (from) = label;
8265 barrier = emit_barrier_after (from);
8266 emit_label_after (label, barrier);
8268 /* Create a minipool barrier entry for the new barrier. */
8269 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
8270 new_fix->insn = barrier;
8271 new_fix->address = selected_address;
8272 new_fix->next = fix->next;
8273 fix->next = new_fix;
8278 /* Record that there is a natural barrier in the insn stream at
8281 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
8283 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8286 fix->address = address;
8289 if (minipool_fix_head != NULL)
8290 minipool_fix_tail->next = fix;
8292 minipool_fix_head = fix;
8294 minipool_fix_tail = fix;
8297 /* Record INSN, which will need fixing up to load a value from the
8298 minipool. ADDRESS is the offset of the insn since the start of the
8299 function; LOC is a pointer to the part of the insn which requires
8300 fixing; VALUE is the constant that must be loaded, which is of type
8303 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8304 enum machine_mode mode, rtx value)
8306 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8308 #ifdef AOF_ASSEMBLER
8309 /* PIC symbol references need to be converted into offsets into the
8311 /* XXX This shouldn't be done here. */
8312 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8313 value = aof_pic_entry (value);
8314 #endif /* AOF_ASSEMBLER */
8317 fix->address = address;
8320 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8322 fix->forwards = get_attr_pool_range (insn);
8323 fix->backwards = get_attr_neg_pool_range (insn);
8324 fix->minipool = NULL;
8326 /* If an insn doesn't have a range defined for it, then it isn't
8327 expecting to be reworked by this code. Better to stop now than
8328 to generate duff assembly code. */
8329 gcc_assert (fix->forwards || fix->backwards);
8331 /* If an entry requires 8-byte alignment then assume all constant pools
8332 require 4 bytes of padding. Trying to do this later on a per-pool
8333 basis is awkward because existing pool entries have to be modified. */
8334 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8340 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8341 GET_MODE_NAME (mode),
8342 INSN_UID (insn), (unsigned long) address,
8343 -1 * (long)fix->backwards, (long)fix->forwards);
8344 arm_print_value (dump_file, fix->value);
8345 fprintf (dump_file, "\n");
8348 /* Add it to the chain of fixes. */
8351 if (minipool_fix_head != NULL)
8352 minipool_fix_tail->next = fix;
8354 minipool_fix_head = fix;
8356 minipool_fix_tail = fix;
8359 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8360 Returns the number of insns needed, or 99 if we don't know how to
8363 arm_const_double_inline_cost (rtx val)
8365 rtx lowpart, highpart;
8366 enum machine_mode mode;
8368 mode = GET_MODE (val);
8370 if (mode == VOIDmode)
8373 gcc_assert (GET_MODE_SIZE (mode) == 8);
8375 lowpart = gen_lowpart (SImode, val);
8376 highpart = gen_highpart_mode (SImode, mode, val);
8378 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8379 gcc_assert (GET_CODE (highpart) == CONST_INT);
8381 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8382 NULL_RTX, NULL_RTX, 0, 0)
8383 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8384 NULL_RTX, NULL_RTX, 0, 0));
8387 /* Return true if it is worthwhile to split a 64-bit constant into two
8388 32-bit operations. This is the case if optimizing for size, or
8389 if we have load delay slots, or if one 32-bit part can be done with
8390 a single data operation. */
8392 arm_const_double_by_parts (rtx val)
8394 enum machine_mode mode = GET_MODE (val);
8397 if (optimize_size || arm_ld_sched)
8400 if (mode == VOIDmode)
8403 part = gen_highpart_mode (SImode, mode, val);
8405 gcc_assert (GET_CODE (part) == CONST_INT);
8407 if (const_ok_for_arm (INTVAL (part))
8408 || const_ok_for_arm (~INTVAL (part)))
8411 part = gen_lowpart (SImode, val);
8413 gcc_assert (GET_CODE (part) == CONST_INT);
8415 if (const_ok_for_arm (INTVAL (part))
8416 || const_ok_for_arm (~INTVAL (part)))
8422 /* Scan INSN and note any of its operands that need fixing.
8423 If DO_PUSHES is false we do not actually push any of the fixups
8424 needed. The function returns TRUE if any fixups were needed/pushed.
8425 This is used by arm_memory_load_p() which needs to know about loads
8426 of constants that will be converted into minipool loads. */
8428 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8430 bool result = false;
8433 extract_insn (insn);
8435 if (!constrain_operands (1))
8436 fatal_insn_not_found (insn);
8438 if (recog_data.n_alternatives == 0)
8441 /* Fill in recog_op_alt with information about the constraints of
8443 preprocess_constraints ();
8445 for (opno = 0; opno < recog_data.n_operands; opno++)
8447 /* Things we need to fix can only occur in inputs. */
8448 if (recog_data.operand_type[opno] != OP_IN)
8451 /* If this alternative is a memory reference, then any mention
8452 of constants in this alternative is really to fool reload
8453 into allowing us to accept one there. We need to fix them up
8454 now so that we output the right code. */
8455 if (recog_op_alt[opno][which_alternative].memory_ok)
8457 rtx op = recog_data.operand[opno];
8459 if (CONSTANT_P (op))
8462 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8463 recog_data.operand_mode[opno], op);
8466 else if (GET_CODE (op) == MEM
8467 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8468 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8472 rtx cop = avoid_constant_pool_reference (op);
8474 /* Casting the address of something to a mode narrower
8475 than a word can cause avoid_constant_pool_reference()
8476 to return the pool reference itself. That's no good to
8477 us here. Lets just hope that we can use the
8478 constant pool value directly. */
8480 cop = get_pool_constant (XEXP (op, 0));
8482 push_minipool_fix (insn, address,
8483 recog_data.operand_loc[opno],
8484 recog_data.operand_mode[opno], cop);
8495 /* Gcc puts the pool in the wrong place for ARM, since we can only
8496 load addresses a limited distance around the pc. We do some
8497 special munging to move the constant pool values to the correct
8498 point in the code. */
8503 HOST_WIDE_INT address = 0;
8506 minipool_fix_head = minipool_fix_tail = NULL;
8508 /* The first insn must always be a note, or the code below won't
8509 scan it properly. */
8510 insn = get_insns ();
8511 gcc_assert (GET_CODE (insn) == NOTE);
8514 /* Scan all the insns and record the operands that will need fixing. */
8515 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8517 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8518 && (arm_cirrus_insn_p (insn)
8519 || GET_CODE (insn) == JUMP_INSN
8520 || arm_memory_load_p (insn)))
8521 cirrus_reorg (insn);
8523 if (GET_CODE (insn) == BARRIER)
8524 push_minipool_barrier (insn, address);
8525 else if (INSN_P (insn))
8529 note_invalid_constants (insn, address, true);
8530 address += get_attr_length (insn);
8532 /* If the insn is a vector jump, add the size of the table
8533 and skip the table. */
8534 if ((table = is_jump_table (insn)) != NULL)
8536 address += get_jump_table_size (table);
8542 fix = minipool_fix_head;
8544 /* Now scan the fixups and perform the required changes. */
8549 Mfix * last_added_fix;
8550 Mfix * last_barrier = NULL;
8553 /* Skip any further barriers before the next fix. */
8554 while (fix && GET_CODE (fix->insn) == BARRIER)
8557 /* No more fixes. */
8561 last_added_fix = NULL;
8563 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8565 if (GET_CODE (ftmp->insn) == BARRIER)
8567 if (ftmp->address >= minipool_vector_head->max_address)
8570 last_barrier = ftmp;
8572 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8575 last_added_fix = ftmp; /* Keep track of the last fix added. */
8578 /* If we found a barrier, drop back to that; any fixes that we
8579 could have reached but come after the barrier will now go in
8580 the next mini-pool. */
8581 if (last_barrier != NULL)
8583 /* Reduce the refcount for those fixes that won't go into this
8585 for (fdel = last_barrier->next;
8586 fdel && fdel != ftmp;
8589 fdel->minipool->refcount--;
8590 fdel->minipool = NULL;
8593 ftmp = last_barrier;
8597 /* ftmp is first fix that we can't fit into this pool and
8598 there no natural barriers that we could use. Insert a
8599 new barrier in the code somewhere between the previous
8600 fix and this one, and arrange to jump around it. */
8601 HOST_WIDE_INT max_address;
8603 /* The last item on the list of fixes must be a barrier, so
8604 we can never run off the end of the list of fixes without
8605 last_barrier being set. */
8608 max_address = minipool_vector_head->max_address;
8609 /* Check that there isn't another fix that is in range that
8610 we couldn't fit into this pool because the pool was
8611 already too large: we need to put the pool before such an
8612 instruction. The pool itself may come just after the
8613 fix because create_fix_barrier also allows space for a
8614 jump instruction. */
8615 if (ftmp->address < max_address)
8616 max_address = ftmp->address + 1;
8618 last_barrier = create_fix_barrier (last_added_fix, max_address);
8621 assign_minipool_offsets (last_barrier);
8625 if (GET_CODE (ftmp->insn) != BARRIER
8626 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8633 /* Scan over the fixes we have identified for this pool, fixing them
8634 up and adding the constants to the pool itself. */
8635 for (this_fix = fix; this_fix && ftmp != this_fix;
8636 this_fix = this_fix->next)
8637 if (GET_CODE (this_fix->insn) != BARRIER)
8640 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8641 minipool_vector_label),
8642 this_fix->minipool->offset);
8643 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8646 dump_minipool (last_barrier->insn);
8650 /* From now on we must synthesize any constants that we can't handle
8651 directly. This can happen if the RTL gets split during final
8652 instruction generation. */
8653 after_arm_reorg = 1;
8655 /* Free the minipool memory. */
8656 obstack_free (&minipool_obstack, minipool_startobj);
8659 /* Routines to output assembly language. */
8661 /* If the rtx is the correct value then return the string of the number.
8662 In this way we can ensure that valid double constants are generated even
8663 when cross compiling. */
8665 fp_immediate_constant (rtx x)
8670 if (!fp_consts_inited)
8673 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8674 for (i = 0; i < 8; i++)
8675 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8676 return strings_fp[i];
8681 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8683 fp_const_from_val (REAL_VALUE_TYPE *r)
8687 if (!fp_consts_inited)
8690 for (i = 0; i < 8; i++)
8691 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8692 return strings_fp[i];
8697 /* Output the operands of a LDM/STM instruction to STREAM.
8698 MASK is the ARM register set mask of which only bits 0-15 are important.
8699 REG is the base register, either the frame pointer or the stack pointer,
8700 INSTR is the possibly suffixed load or store instruction.
8701 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8704 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8705 unsigned long mask, int rfe)
8708 bool not_first = FALSE;
8710 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
8711 fputc ('\t', stream);
8712 asm_fprintf (stream, instr, reg);
8713 fputc ('{', stream);
8715 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8716 if (mask & (1 << i))
8719 fprintf (stream, ", ");
8721 asm_fprintf (stream, "%r", i);
8726 fprintf (stream, "}^\n");
8728 fprintf (stream, "}\n");
8732 /* Output a FLDMD instruction to STREAM.
8733 BASE if the register containing the address.
8734 REG and COUNT specify the register range.
8735 Extra registers may be added to avoid hardware bugs.
8737 We output FLDMD even for ARMv5 VFP implementations. Although
8738 FLDMD is technically not supported until ARMv6, it is believed
8739 that all VFP implementations support its use in this context. */
8742 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
8746 /* Workaround ARM10 VFPr1 bug. */
8747 if (count == 2 && !arm_arch6)
8754 fputc ('\t', stream);
8755 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
8757 for (i = reg; i < reg + count; i++)
8760 fputs (", ", stream);
8761 asm_fprintf (stream, "d%d", i);
8763 fputs ("}\n", stream);
8768 /* Output the assembly for a store multiple. */
8771 vfp_output_fstmd (rtx * operands)
8778 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
8779 p = strlen (pattern);
8781 gcc_assert (GET_CODE (operands[1]) == REG);
8783 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8784 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8786 p += sprintf (&pattern[p], ", d%d", base + i);
8788 strcpy (&pattern[p], "}");
8790 output_asm_insn (pattern, operands);
8795 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8796 number of bytes pushed. */
8799 vfp_emit_fstmd (int base_reg, int count)
8806 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8807 register pairs are stored by a store multiple insn. We avoid this
8808 by pushing an extra pair. */
8809 if (count == 2 && !arm_arch6)
8811 if (base_reg == LAST_VFP_REGNUM - 3)
8816 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8817 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8819 reg = gen_rtx_REG (DFmode, base_reg);
8823 = gen_rtx_SET (VOIDmode,
8824 gen_frame_mem (BLKmode,
8825 gen_rtx_PRE_DEC (BLKmode,
8826 stack_pointer_rtx)),
8827 gen_rtx_UNSPEC (BLKmode,
8831 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8832 plus_constant (stack_pointer_rtx, -(count * 8)));
8833 RTX_FRAME_RELATED_P (tmp) = 1;
8834 XVECEXP (dwarf, 0, 0) = tmp;
8836 tmp = gen_rtx_SET (VOIDmode,
8837 gen_frame_mem (DFmode, stack_pointer_rtx),
8839 RTX_FRAME_RELATED_P (tmp) = 1;
8840 XVECEXP (dwarf, 0, 1) = tmp;
8842 for (i = 1; i < count; i++)
8844 reg = gen_rtx_REG (DFmode, base_reg);
8846 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8848 tmp = gen_rtx_SET (VOIDmode,
8849 gen_frame_mem (DFmode,
8850 plus_constant (stack_pointer_rtx,
8853 RTX_FRAME_RELATED_P (tmp) = 1;
8854 XVECEXP (dwarf, 0, i + 1) = tmp;
8857 par = emit_insn (par);
8858 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8860 RTX_FRAME_RELATED_P (par) = 1;
8866 /* Output a 'call' insn. */
8868 output_call (rtx *operands)
8870 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8872 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8873 if (REGNO (operands[0]) == LR_REGNUM)
8875 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8876 output_asm_insn ("mov%?\t%0, %|lr", operands);
8879 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8881 if (TARGET_INTERWORK || arm_arch4t)
8882 output_asm_insn ("bx%?\t%0", operands);
8884 output_asm_insn ("mov%?\t%|pc, %0", operands);
8889 /* Output a 'call' insn that is a reference in memory. */
8891 output_call_mem (rtx *operands)
8893 if (TARGET_INTERWORK && !arm_arch5)
8895 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8896 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8897 output_asm_insn ("bx%?\t%|ip", operands);
8899 else if (regno_use_in (LR_REGNUM, operands[0]))
8901 /* LR is used in the memory address. We load the address in the
8902 first instruction. It's safe to use IP as the target of the
8903 load since the call will kill it anyway. */
8904 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8906 output_asm_insn ("blx%?\t%|ip", operands);
8909 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8911 output_asm_insn ("bx%?\t%|ip", operands);
8913 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8918 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8919 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8926 /* Output a move from arm registers to an fpa registers.
8927 OPERANDS[0] is an fpa register.
8928 OPERANDS[1] is the first registers of an arm register pair. */
8930 output_mov_long_double_fpa_from_arm (rtx *operands)
8932 int arm_reg0 = REGNO (operands[1]);
8935 gcc_assert (arm_reg0 != IP_REGNUM);
8937 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8938 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8939 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8941 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
8942 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8947 /* Output a move from an fpa register to arm registers.
8948 OPERANDS[0] is the first registers of an arm register pair.
8949 OPERANDS[1] is an fpa register. */
8951 output_mov_long_double_arm_from_fpa (rtx *operands)
8953 int arm_reg0 = REGNO (operands[0]);
8956 gcc_assert (arm_reg0 != IP_REGNUM);
8958 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8959 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8960 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8962 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8963 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
8967 /* Output a move from arm registers to arm registers of a long double
8968 OPERANDS[0] is the destination.
8969 OPERANDS[1] is the source. */
8971 output_mov_long_double_arm_from_arm (rtx *operands)
8973 /* We have to be careful here because the two might overlap. */
8974 int dest_start = REGNO (operands[0]);
8975 int src_start = REGNO (operands[1]);
8979 if (dest_start < src_start)
8981 for (i = 0; i < 3; i++)
8983 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8984 ops[1] = gen_rtx_REG (SImode, src_start + i);
8985 output_asm_insn ("mov%?\t%0, %1", ops);
8990 for (i = 2; i >= 0; i--)
8992 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8993 ops[1] = gen_rtx_REG (SImode, src_start + i);
8994 output_asm_insn ("mov%?\t%0, %1", ops);
9002 /* Output a move from arm registers to an fpa registers.
9003 OPERANDS[0] is an fpa register.
9004 OPERANDS[1] is the first registers of an arm register pair. */
9006 output_mov_double_fpa_from_arm (rtx *operands)
9008 int arm_reg0 = REGNO (operands[1]);
9011 gcc_assert (arm_reg0 != IP_REGNUM);
9013 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9014 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9015 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
9016 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
9020 /* Output a move from an fpa register to arm registers.
9021 OPERANDS[0] is the first registers of an arm register pair.
9022 OPERANDS[1] is an fpa register. */
9024 output_mov_double_arm_from_fpa (rtx *operands)
9026 int arm_reg0 = REGNO (operands[0]);
9029 gcc_assert (arm_reg0 != IP_REGNUM);
9031 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9032 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9033 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
9034 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
9038 /* Output a move between double words.
9039 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9040 or MEM<-REG and all MEMs must be offsettable addresses. */
9042 output_move_double (rtx *operands)
9044 enum rtx_code code0 = GET_CODE (operands[0]);
9045 enum rtx_code code1 = GET_CODE (operands[1]);
9050 int reg0 = REGNO (operands[0]);
9052 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9054 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9056 switch (GET_CODE (XEXP (operands[1], 0)))
9059 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
9063 gcc_assert (TARGET_LDRD);
9064 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
9069 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9071 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
9075 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
9079 gcc_assert (TARGET_LDRD);
9080 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
9085 otherops[0] = operands[0];
9086 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9087 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
9089 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
9091 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9093 /* Registers overlap so split out the increment. */
9094 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9095 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
9099 /* IWMMXT allows offsets larger than ldrd can handle,
9100 fix these up with a pair of ldr. */
9101 if (GET_CODE (otherops[2]) == CONST_INT
9102 && (INTVAL(otherops[2]) <= -256
9103 || INTVAL(otherops[2]) >= 256))
9105 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9106 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9107 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9110 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9115 /* IWMMXT allows offsets larger than ldrd can handle,
9116 fix these up with a pair of ldr. */
9117 if (GET_CODE (otherops[2]) == CONST_INT
9118 && (INTVAL(otherops[2]) <= -256
9119 || INTVAL(otherops[2]) >= 256))
9121 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9122 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9123 otherops[0] = operands[0];
9124 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9127 /* We only allow constant increments, so this is safe. */
9128 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
9134 output_asm_insn ("adr%?\t%0, %1", operands);
9135 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
9138 /* ??? This needs checking for thumb2. */
9140 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9141 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9143 otherops[0] = operands[0];
9144 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9145 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
9147 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
9149 if (GET_CODE (otherops[2]) == CONST_INT)
9151 switch ((int) INTVAL (otherops[2]))
9154 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
9159 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
9164 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
9169 && (GET_CODE (otherops[2]) == REG
9170 || (GET_CODE (otherops[2]) == CONST_INT
9171 && INTVAL (otherops[2]) > -256
9172 && INTVAL (otherops[2]) < 256)))
9174 if (reg_overlap_mentioned_p (otherops[0],
9177 /* Swap base and index registers over to
9178 avoid a conflict. */
9179 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9180 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
9182 /* If both registers conflict, it will usually
9183 have been fixed by a splitter. */
9184 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9186 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9187 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9191 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
9195 if (GET_CODE (otherops[2]) == CONST_INT)
9197 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
9198 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
9200 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9203 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9206 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
9208 return "ldm%(ia%)\t%0, %M0";
9212 otherops[1] = adjust_address (operands[1], SImode, 4);
9213 /* Take care of overlapping base/data reg. */
9214 if (reg_mentioned_p (operands[0], operands[1]))
9216 output_asm_insn ("ldr%?\t%0, %1", otherops);
9217 output_asm_insn ("ldr%?\t%0, %1", operands);
9221 output_asm_insn ("ldr%?\t%0, %1", operands);
9222 output_asm_insn ("ldr%?\t%0, %1", otherops);
9229 /* Constraints should ensure this. */
9230 gcc_assert (code0 == MEM && code1 == REG);
9231 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
9233 switch (GET_CODE (XEXP (operands[0], 0)))
9236 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9240 gcc_assert (TARGET_LDRD);
9241 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9246 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
9248 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9252 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9256 gcc_assert (TARGET_LDRD);
9257 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
9262 otherops[0] = operands[1];
9263 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
9264 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
9266 /* IWMMXT allows offsets larger than ldrd can handle,
9267 fix these up with a pair of ldr. */
9268 if (GET_CODE (otherops[2]) == CONST_INT
9269 && (INTVAL(otherops[2]) <= -256
9270 || INTVAL(otherops[2]) >= 256))
9273 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9274 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9276 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9278 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9283 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9284 otherops[0] = operands[1];
9285 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9288 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9289 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
9291 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9295 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
9296 if (GET_CODE (otherops[2]) == CONST_INT)
9298 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
9301 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
9307 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
9313 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
9318 && (GET_CODE (otherops[2]) == REG
9319 || (GET_CODE (otherops[2]) == CONST_INT
9320 && INTVAL (otherops[2]) > -256
9321 && INTVAL (otherops[2]) < 256)))
9323 otherops[0] = operands[1];
9324 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9325 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
9331 otherops[0] = adjust_address (operands[0], SImode, 4);
9332 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9333 output_asm_insn ("str%?\t%1, %0", operands);
9334 output_asm_insn ("str%?\t%1, %0", otherops);
9341 /* Output a VFP load or store instruction. */
9344 output_move_vfp (rtx *operands)
9346 rtx reg, mem, addr, ops[2];
9347 int load = REG_P (operands[0]);
9348 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
9349 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
9350 const char *template;
9353 reg = operands[!load];
9354 mem = operands[load];
9356 gcc_assert (REG_P (reg));
9357 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
9358 gcc_assert (GET_MODE (reg) == SFmode
9359 || GET_MODE (reg) == DFmode
9360 || GET_MODE (reg) == SImode
9361 || GET_MODE (reg) == DImode);
9362 gcc_assert (MEM_P (mem));
9364 addr = XEXP (mem, 0);
9366 switch (GET_CODE (addr))
9369 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9370 ops[0] = XEXP (addr, 0);
9375 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9376 ops[0] = XEXP (addr, 0);
9381 template = "f%s%c%%?\t%%%s0, %%1%s";
9387 sprintf (buff, template,
9391 integer_p ? "\t%@ int" : "");
9392 output_asm_insn (buff, ops);
9397 /* Output an ADD r, s, #n where n may be too big for one instruction.
9398 If adding zero to one register, output nothing. */
9400 output_add_immediate (rtx *operands)
9402 HOST_WIDE_INT n = INTVAL (operands[2]);
9404 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9407 output_multi_immediate (operands,
9408 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9411 output_multi_immediate (operands,
9412 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9419 /* Output a multiple immediate operation.
9420 OPERANDS is the vector of operands referred to in the output patterns.
9421 INSTR1 is the output pattern to use for the first constant.
9422 INSTR2 is the output pattern to use for subsequent constants.
9423 IMMED_OP is the index of the constant slot in OPERANDS.
9424 N is the constant value. */
9426 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9427 int immed_op, HOST_WIDE_INT n)
9429 #if HOST_BITS_PER_WIDE_INT > 32
9435 /* Quick and easy output. */
9436 operands[immed_op] = const0_rtx;
9437 output_asm_insn (instr1, operands);
9442 const char * instr = instr1;
9444 /* Note that n is never zero here (which would give no output). */
9445 for (i = 0; i < 32; i += 2)
9449 operands[immed_op] = GEN_INT (n & (255 << i));
9450 output_asm_insn (instr, operands);
9460 /* Return the name of a shifter operation. */
9462 arm_shift_nmem(enum rtx_code code)
9467 return ARM_LSL_NAME;
9483 /* Return the appropriate ARM instruction for the operation code.
9484 The returned result should not be overwritten. OP is the rtx of the
9485 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9488 arithmetic_instr (rtx op, int shift_first_arg)
9490 switch (GET_CODE (op))
9496 return shift_first_arg ? "rsb" : "sub";
9511 return arm_shift_nmem(GET_CODE(op));
9518 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9519 for the operation code. The returned result should not be overwritten.
9520 OP is the rtx code of the shift.
9521 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9524 shift_op (rtx op, HOST_WIDE_INT *amountp)
9527 enum rtx_code code = GET_CODE (op);
9529 switch (GET_CODE (XEXP (op, 1)))
9537 *amountp = INTVAL (XEXP (op, 1));
9547 gcc_assert (*amountp != -1);
9548 *amountp = 32 - *amountp;
9557 mnem = arm_shift_nmem(code);
9561 /* We never have to worry about the amount being other than a
9562 power of 2, since this case can never be reloaded from a reg. */
9563 gcc_assert (*amountp != -1);
9564 *amountp = int_log2 (*amountp);
9565 return ARM_LSL_NAME;
9573 /* This is not 100% correct, but follows from the desire to merge
9574 multiplication by a power of 2 with the recognizer for a
9575 shift. >=32 is not a valid shift for "lsl", so we must try and
9576 output a shift that produces the correct arithmetical result.
9577 Using lsr #32 is identical except for the fact that the carry bit
9578 is not set correctly if we set the flags; but we never use the
9579 carry bit from such an operation, so we can ignore that. */
9580 if (code == ROTATERT)
9581 /* Rotate is just modulo 32. */
9583 else if (*amountp != (*amountp & 31))
9590 /* Shifts of 0 are no-ops. */
9598 /* Obtain the shift from the POWER of two. */
9600 static HOST_WIDE_INT
9601 int_log2 (HOST_WIDE_INT power)
9603 HOST_WIDE_INT shift = 0;
9605 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9607 gcc_assert (shift <= 31);
9614 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9615 because /bin/as is horribly restrictive. The judgement about
9616 whether or not each character is 'printable' (and can be output as
9617 is) or not (and must be printed with an octal escape) must be made
9618 with reference to the *host* character set -- the situation is
9619 similar to that discussed in the comments above pp_c_char in
9620 c-pretty-print.c. */
9622 #define MAX_ASCII_LEN 51
9625 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9630 fputs ("\t.ascii\t\"", stream);
9632 for (i = 0; i < len; i++)
9636 if (len_so_far >= MAX_ASCII_LEN)
9638 fputs ("\"\n\t.ascii\t\"", stream);
9644 if (c == '\\' || c == '\"')
9646 putc ('\\', stream);
9654 fprintf (stream, "\\%03o", c);
9659 fputs ("\"\n", stream);
9662 /* Compute the register save mask for registers 0 through 12
9663 inclusive. This code is used by arm_compute_save_reg_mask. */
9665 static unsigned long
9666 arm_compute_save_reg0_reg12_mask (void)
9668 unsigned long func_type = arm_current_func_type ();
9669 unsigned long save_reg_mask = 0;
9672 if (IS_INTERRUPT (func_type))
9674 unsigned int max_reg;
9675 /* Interrupt functions must not corrupt any registers,
9676 even call clobbered ones. If this is a leaf function
9677 we can just examine the registers used by the RTL, but
9678 otherwise we have to assume that whatever function is
9679 called might clobber anything, and so we have to save
9680 all the call-clobbered registers as well. */
9681 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9682 /* FIQ handlers have registers r8 - r12 banked, so
9683 we only need to check r0 - r7, Normal ISRs only
9684 bank r14 and r15, so we must check up to r12.
9685 r13 is the stack pointer which is always preserved,
9686 so we do not need to consider it here. */
9691 for (reg = 0; reg <= max_reg; reg++)
9692 if (regs_ever_live[reg]
9693 || (! current_function_is_leaf && call_used_regs [reg]))
9694 save_reg_mask |= (1 << reg);
9696 /* Also save the pic base register if necessary. */
9698 && !TARGET_SINGLE_PIC_BASE
9699 && arm_pic_register != INVALID_REGNUM
9700 && current_function_uses_pic_offset_table)
9701 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9705 /* In arm mode we handle r11 (FP) as a special case. */
9706 unsigned last_reg = TARGET_ARM ? 10 : 11;
9708 /* In the normal case we only need to save those registers
9709 which are call saved and which are used by this function. */
9710 for (reg = 0; reg <= last_reg; reg++)
9711 if (regs_ever_live[reg] && ! call_used_regs [reg])
9712 save_reg_mask |= (1 << reg);
9714 /* Handle the frame pointer as a special case. */
9715 if (TARGET_THUMB2 && frame_pointer_needed)
9716 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9717 else if (! TARGET_APCS_FRAME
9718 && ! frame_pointer_needed
9719 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9720 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9721 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9723 /* If we aren't loading the PIC register,
9724 don't stack it even though it may be live. */
9726 && !TARGET_SINGLE_PIC_BASE
9727 && arm_pic_register != INVALID_REGNUM
9728 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
9729 || current_function_uses_pic_offset_table))
9730 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9732 /* The prologue will copy SP into R0, so save it. */
9733 if (IS_STACKALIGN (func_type))
9737 /* Save registers so the exception handler can modify them. */
9738 if (current_function_calls_eh_return)
9744 reg = EH_RETURN_DATA_REGNO (i);
9745 if (reg == INVALID_REGNUM)
9747 save_reg_mask |= 1 << reg;
9751 return save_reg_mask;
9755 /* Compute a bit mask of which registers need to be
9756 saved on the stack for the current function. */
9758 static unsigned long
9759 arm_compute_save_reg_mask (void)
9761 unsigned int save_reg_mask = 0;
9762 unsigned long func_type = arm_current_func_type ();
9765 if (IS_NAKED (func_type))
9766 /* This should never really happen. */
9769 /* If we are creating a stack frame, then we must save the frame pointer,
9770 IP (which will hold the old stack pointer), LR and the PC. */
9771 if (frame_pointer_needed && TARGET_ARM)
9773 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9778 /* Volatile functions do not return, so there
9779 is no need to save any other registers. */
9780 if (IS_VOLATILE (func_type))
9781 return save_reg_mask;
9783 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9785 /* Decide if we need to save the link register.
9786 Interrupt routines have their own banked link register,
9787 so they never need to save it.
9788 Otherwise if we do not use the link register we do not need to save
9789 it. If we are pushing other registers onto the stack however, we
9790 can save an instruction in the epilogue by pushing the link register
9791 now and then popping it back into the PC. This incurs extra memory
9792 accesses though, so we only do it when optimizing for size, and only
9793 if we know that we will not need a fancy return sequence. */
9794 if (regs_ever_live [LR_REGNUM]
9797 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9798 && !current_function_calls_eh_return))
9799 save_reg_mask |= 1 << LR_REGNUM;
9801 if (cfun->machine->lr_save_eliminated)
9802 save_reg_mask &= ~ (1 << LR_REGNUM);
9804 if (TARGET_REALLY_IWMMXT
9805 && ((bit_count (save_reg_mask)
9806 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9808 /* The total number of registers that are going to be pushed
9809 onto the stack is odd. We need to ensure that the stack
9810 is 64-bit aligned before we start to save iWMMXt registers,
9811 and also before we start to create locals. (A local variable
9812 might be a double or long long which we will load/store using
9813 an iWMMXt instruction). Therefore we need to push another
9814 ARM register, so that the stack will be 64-bit aligned. We
9815 try to avoid using the arg registers (r0 -r3) as they might be
9816 used to pass values in a tail call. */
9817 for (reg = 4; reg <= 12; reg++)
9818 if ((save_reg_mask & (1 << reg)) == 0)
9822 save_reg_mask |= (1 << reg);
9825 cfun->machine->sibcall_blocked = 1;
9826 save_reg_mask |= (1 << 3);
9830 /* We may need to push an additional register for use initializing the
9831 PIC base register. */
9832 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
9833 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
9835 reg = thumb_find_work_register (1 << 4);
9836 if (!call_used_regs[reg])
9837 save_reg_mask |= (1 << reg);
9840 return save_reg_mask;
9844 /* Compute a bit mask of which registers need to be
9845 saved on the stack for the current function. */
9846 static unsigned long
9847 thumb1_compute_save_reg_mask (void)
9853 for (reg = 0; reg < 12; reg ++)
9854 if (regs_ever_live[reg] && !call_used_regs[reg])
9858 && !TARGET_SINGLE_PIC_BASE
9859 && arm_pic_register != INVALID_REGNUM
9860 && current_function_uses_pic_offset_table)
9861 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9863 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9864 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
9865 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
9867 /* LR will also be pushed if any lo regs are pushed. */
9868 if (mask & 0xff || thumb_force_lr_save ())
9869 mask |= (1 << LR_REGNUM);
9871 /* Make sure we have a low work register if we need one.
9872 We will need one if we are going to push a high register,
9873 but we are not currently intending to push a low register. */
9874 if ((mask & 0xff) == 0
9875 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9877 /* Use thumb_find_work_register to choose which register
9878 we will use. If the register is live then we will
9879 have to push it. Use LAST_LO_REGNUM as our fallback
9880 choice for the register to select. */
9881 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9883 if (! call_used_regs[reg])
9891 /* Return the number of bytes required to save VFP registers. */
9893 arm_get_vfp_saved_size (void)
9900 /* Space for saved VFP registers. */
9901 if (TARGET_HARD_FLOAT && TARGET_VFP)
9904 for (regno = FIRST_VFP_REGNUM;
9905 regno < LAST_VFP_REGNUM;
9908 if ((!regs_ever_live[regno] || call_used_regs[regno])
9909 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9913 /* Workaround ARM10 VFPr1 bug. */
9914 if (count == 2 && !arm_arch6)
9925 if (count == 2 && !arm_arch6)
9934 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9935 everything bar the final return instruction. */
9937 output_return_instruction (rtx operand, int really_return, int reverse)
9939 char conditional[10];
9942 unsigned long live_regs_mask;
9943 unsigned long func_type;
9944 arm_stack_offsets *offsets;
9946 func_type = arm_current_func_type ();
9948 if (IS_NAKED (func_type))
9951 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9953 /* If this function was declared non-returning, and we have
9954 found a tail call, then we have to trust that the called
9955 function won't return. */
9960 /* Otherwise, trap an attempted return by aborting. */
9962 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9964 assemble_external_libcall (ops[1]);
9965 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9971 gcc_assert (!current_function_calls_alloca || really_return);
9973 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9975 return_used_this_function = 1;
9977 live_regs_mask = arm_compute_save_reg_mask ();
9981 const char * return_reg;
9983 /* If we do not have any special requirements for function exit
9984 (e.g. interworking) then we can load the return address
9985 directly into the PC. Otherwise we must load it into LR. */
9987 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
9988 return_reg = reg_names[PC_REGNUM];
9990 return_reg = reg_names[LR_REGNUM];
9992 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9994 /* There are three possible reasons for the IP register
9995 being saved. 1) a stack frame was created, in which case
9996 IP contains the old stack pointer, or 2) an ISR routine
9997 corrupted it, or 3) it was saved to align the stack on
9998 iWMMXt. In case 1, restore IP into SP, otherwise just
10000 if (frame_pointer_needed)
10002 live_regs_mask &= ~ (1 << IP_REGNUM);
10003 live_regs_mask |= (1 << SP_REGNUM);
10006 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
10009 /* On some ARM architectures it is faster to use LDR rather than
10010 LDM to load a single register. On other architectures, the
10011 cost is the same. In 26 bit mode, or for exception handlers,
10012 we have to use LDM to load the PC so that the CPSR is also
10014 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10015 if (live_regs_mask == (1U << reg))
10018 if (reg <= LAST_ARM_REGNUM
10019 && (reg != LR_REGNUM
10021 || ! IS_INTERRUPT (func_type)))
10023 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
10024 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
10031 /* Generate the load multiple instruction to restore the
10032 registers. Note we can get here, even if
10033 frame_pointer_needed is true, but only if sp already
10034 points to the base of the saved core registers. */
10035 if (live_regs_mask & (1 << SP_REGNUM))
10037 unsigned HOST_WIDE_INT stack_adjust;
10039 offsets = arm_get_frame_offsets ();
10040 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
10041 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
10043 if (stack_adjust && arm_arch5 && TARGET_ARM)
10044 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
10047 /* If we can't use ldmib (SA110 bug),
10048 then try to pop r3 instead. */
10050 live_regs_mask |= 1 << 3;
10051 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
10055 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
10057 p = instr + strlen (instr);
10059 for (reg = 0; reg <= SP_REGNUM; reg++)
10060 if (live_regs_mask & (1 << reg))
10062 int l = strlen (reg_names[reg]);
10068 memcpy (p, ", ", 2);
10072 memcpy (p, "%|", 2);
10073 memcpy (p + 2, reg_names[reg], l);
10077 if (live_regs_mask & (1 << LR_REGNUM))
10079 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
10080 /* If returning from an interrupt, restore the CPSR. */
10081 if (IS_INTERRUPT (func_type))
10088 output_asm_insn (instr, & operand);
10090 /* See if we need to generate an extra instruction to
10091 perform the actual function return. */
10093 && func_type != ARM_FT_INTERWORKED
10094 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
10096 /* The return has already been handled
10097 by loading the LR into the PC. */
10104 switch ((int) ARM_FUNC_TYPE (func_type))
10108 /* ??? This is wrong for unified assembly syntax. */
10109 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
10112 case ARM_FT_INTERWORKED:
10113 sprintf (instr, "bx%s\t%%|lr", conditional);
10116 case ARM_FT_EXCEPTION:
10117 /* ??? This is wrong for unified assembly syntax. */
10118 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
10122 /* Use bx if it's available. */
10123 if (arm_arch5 || arm_arch4t)
10124 sprintf (instr, "bx%s\t%%|lr", conditional);
10126 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
10130 output_asm_insn (instr, & operand);
10136 /* Write the function name into the code section, directly preceding
10137 the function prologue.
10139 Code will be output similar to this:
10141 .ascii "arm_poke_function_name", 0
10144 .word 0xff000000 + (t1 - t0)
10145 arm_poke_function_name
10147 stmfd sp!, {fp, ip, lr, pc}
10150 When performing a stack backtrace, code can inspect the value
10151 of 'pc' stored at 'fp' + 0. If the trace function then looks
10152 at location pc - 12 and the top 8 bits are set, then we know
10153 that there is a function name embedded immediately preceding this
10154 location and has length ((pc[-3]) & 0xff000000).
10156 We assume that pc is declared as a pointer to an unsigned long.
10158 It is of no benefit to output the function name if we are assembling
10159 a leaf function. These function types will not contain a stack
10160 backtrace structure, therefore it is not possible to determine the
10163 arm_poke_function_name (FILE *stream, const char *name)
10165 unsigned long alignlength;
10166 unsigned long length;
10169 length = strlen (name) + 1;
10170 alignlength = ROUND_UP_WORD (length);
10172 ASM_OUTPUT_ASCII (stream, name, length);
10173 ASM_OUTPUT_ALIGN (stream, 2);
10174 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
10175 assemble_aligned_integer (UNITS_PER_WORD, x);
10178 /* Place some comments into the assembler stream
10179 describing the current function. */
10181 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
10183 unsigned long func_type;
10187 thumb1_output_function_prologue (f, frame_size);
10191 /* Sanity check. */
10192 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
10194 func_type = arm_current_func_type ();
10196 switch ((int) ARM_FUNC_TYPE (func_type))
10199 case ARM_FT_NORMAL:
10201 case ARM_FT_INTERWORKED:
10202 asm_fprintf (f, "\t%@ Function supports interworking.\n");
10205 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
10208 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
10210 case ARM_FT_EXCEPTION:
10211 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
10215 if (IS_NAKED (func_type))
10216 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10218 if (IS_VOLATILE (func_type))
10219 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
10221 if (IS_NESTED (func_type))
10222 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
10223 if (IS_STACKALIGN (func_type))
10224 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10226 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10227 current_function_args_size,
10228 current_function_pretend_args_size, frame_size);
10230 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10231 frame_pointer_needed,
10232 cfun->machine->uses_anonymous_args);
10234 if (cfun->machine->lr_save_eliminated)
10235 asm_fprintf (f, "\t%@ link register save eliminated.\n");
10237 if (current_function_calls_eh_return)
10238 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
10240 #ifdef AOF_ASSEMBLER
10242 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
10245 return_used_this_function = 0;
10249 arm_output_epilogue (rtx sibling)
10252 unsigned long saved_regs_mask;
10253 unsigned long func_type;
10254 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10255 frame that is $fp + 4 for a non-variadic function. */
10256 int floats_offset = 0;
10258 FILE * f = asm_out_file;
10259 unsigned int lrm_count = 0;
10260 int really_return = (sibling == NULL);
10262 arm_stack_offsets *offsets;
10264 /* If we have already generated the return instruction
10265 then it is futile to generate anything else. */
10266 if (use_return_insn (FALSE, sibling) && return_used_this_function)
10269 func_type = arm_current_func_type ();
10271 if (IS_NAKED (func_type))
10272 /* Naked functions don't have epilogues. */
10275 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10279 /* A volatile function should never return. Call abort. */
10280 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
10281 assemble_external_libcall (op);
10282 output_asm_insn ("bl\t%a0", &op);
10287 /* If we are throwing an exception, then we really must be doing a
10288 return, so we can't tail-call. */
10289 gcc_assert (!current_function_calls_eh_return || really_return);
10291 offsets = arm_get_frame_offsets ();
10292 saved_regs_mask = arm_compute_save_reg_mask ();
10295 lrm_count = bit_count (saved_regs_mask);
10297 floats_offset = offsets->saved_args;
10298 /* Compute how far away the floats will be. */
10299 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10300 if (saved_regs_mask & (1 << reg))
10301 floats_offset += 4;
10303 if (frame_pointer_needed && TARGET_ARM)
10305 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10306 int vfp_offset = offsets->frame;
10308 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10310 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10311 if (regs_ever_live[reg] && !call_used_regs[reg])
10313 floats_offset += 12;
10314 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
10315 reg, FP_REGNUM, floats_offset - vfp_offset);
10320 start_reg = LAST_FPA_REGNUM;
10322 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10324 if (regs_ever_live[reg] && !call_used_regs[reg])
10326 floats_offset += 12;
10328 /* We can't unstack more than four registers at once. */
10329 if (start_reg - reg == 3)
10331 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
10332 reg, FP_REGNUM, floats_offset - vfp_offset);
10333 start_reg = reg - 1;
10338 if (reg != start_reg)
10339 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10340 reg + 1, start_reg - reg,
10341 FP_REGNUM, floats_offset - vfp_offset);
10342 start_reg = reg - 1;
10346 /* Just in case the last register checked also needs unstacking. */
10347 if (reg != start_reg)
10348 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10349 reg + 1, start_reg - reg,
10350 FP_REGNUM, floats_offset - vfp_offset);
10353 if (TARGET_HARD_FLOAT && TARGET_VFP)
10357 /* The fldmd insns do not have base+offset addressing
10358 modes, so we use IP to hold the address. */
10359 saved_size = arm_get_vfp_saved_size ();
10361 if (saved_size > 0)
10363 floats_offset += saved_size;
10364 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
10365 FP_REGNUM, floats_offset - vfp_offset);
10367 start_reg = FIRST_VFP_REGNUM;
10368 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10370 if ((!regs_ever_live[reg] || call_used_regs[reg])
10371 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10373 if (start_reg != reg)
10374 vfp_output_fldmd (f, IP_REGNUM,
10375 (start_reg - FIRST_VFP_REGNUM) / 2,
10376 (reg - start_reg) / 2);
10377 start_reg = reg + 2;
10380 if (start_reg != reg)
10381 vfp_output_fldmd (f, IP_REGNUM,
10382 (start_reg - FIRST_VFP_REGNUM) / 2,
10383 (reg - start_reg) / 2);
10388 /* The frame pointer is guaranteed to be non-double-word aligned.
10389 This is because it is set to (old_stack_pointer - 4) and the
10390 old_stack_pointer was double word aligned. Thus the offset to
10391 the iWMMXt registers to be loaded must also be non-double-word
10392 sized, so that the resultant address *is* double-word aligned.
10393 We can ignore floats_offset since that was already included in
10394 the live_regs_mask. */
10395 lrm_count += (lrm_count % 2 ? 2 : 1);
10397 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10398 if (regs_ever_live[reg] && !call_used_regs[reg])
10400 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
10401 reg, FP_REGNUM, lrm_count * 4);
10406 /* saved_regs_mask should contain the IP, which at the time of stack
10407 frame generation actually contains the old stack pointer. So a
10408 quick way to unwind the stack is just pop the IP register directly
10409 into the stack pointer. */
10410 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
10411 saved_regs_mask &= ~ (1 << IP_REGNUM);
10412 saved_regs_mask |= (1 << SP_REGNUM);
10414 /* There are two registers left in saved_regs_mask - LR and PC. We
10415 only need to restore the LR register (the return address), but to
10416 save time we can load it directly into the PC, unless we need a
10417 special function exit sequence, or we are not really returning. */
10419 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10420 && !current_function_calls_eh_return)
10421 /* Delete the LR from the register mask, so that the LR on
10422 the stack is loaded into the PC in the register mask. */
10423 saved_regs_mask &= ~ (1 << LR_REGNUM);
10425 saved_regs_mask &= ~ (1 << PC_REGNUM);
10427 /* We must use SP as the base register, because SP is one of the
10428 registers being restored. If an interrupt or page fault
10429 happens in the ldm instruction, the SP might or might not
10430 have been restored. That would be bad, as then SP will no
10431 longer indicate the safe area of stack, and we can get stack
10432 corruption. Using SP as the base register means that it will
10433 be reset correctly to the original value, should an interrupt
10434 occur. If the stack pointer already points at the right
10435 place, then omit the subtraction. */
10436 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10437 || current_function_calls_alloca)
10438 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10439 4 * bit_count (saved_regs_mask));
10440 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
10442 if (IS_INTERRUPT (func_type))
10443 /* Interrupt handlers will have pushed the
10444 IP onto the stack, so restore it now. */
10445 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
10449 HOST_WIDE_INT amount;
10451 /* Restore stack pointer if necessary. */
10452 if (frame_pointer_needed)
10454 /* For Thumb-2 restore sp from the frame pointer.
10455 Operand restrictions mean we have to increment FP, then copy
10457 amount = offsets->locals_base - offsets->saved_regs;
10458 operands[0] = hard_frame_pointer_rtx;
10462 operands[0] = stack_pointer_rtx;
10463 amount = offsets->outgoing_args - offsets->saved_regs;
10468 operands[1] = operands[0];
10469 operands[2] = GEN_INT (amount);
10470 output_add_immediate (operands);
10472 if (frame_pointer_needed)
10473 asm_fprintf (f, "\tmov\t%r, %r\n",
10474 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
10476 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10478 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10479 if (regs_ever_live[reg] && !call_used_regs[reg])
10480 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10485 start_reg = FIRST_FPA_REGNUM;
10487 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10489 if (regs_ever_live[reg] && !call_used_regs[reg])
10491 if (reg - start_reg == 3)
10493 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10494 start_reg, SP_REGNUM);
10495 start_reg = reg + 1;
10500 if (reg != start_reg)
10501 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10502 start_reg, reg - start_reg,
10505 start_reg = reg + 1;
10509 /* Just in case the last register checked also needs unstacking. */
10510 if (reg != start_reg)
10511 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10512 start_reg, reg - start_reg, SP_REGNUM);
10515 if (TARGET_HARD_FLOAT && TARGET_VFP)
10517 start_reg = FIRST_VFP_REGNUM;
10518 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10520 if ((!regs_ever_live[reg] || call_used_regs[reg])
10521 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10523 if (start_reg != reg)
10524 vfp_output_fldmd (f, SP_REGNUM,
10525 (start_reg - FIRST_VFP_REGNUM) / 2,
10526 (reg - start_reg) / 2);
10527 start_reg = reg + 2;
10530 if (start_reg != reg)
10531 vfp_output_fldmd (f, SP_REGNUM,
10532 (start_reg - FIRST_VFP_REGNUM) / 2,
10533 (reg - start_reg) / 2);
10536 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10537 if (regs_ever_live[reg] && !call_used_regs[reg])
10538 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10540 /* If we can, restore the LR into the PC. */
10541 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
10542 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
10543 && !IS_STACKALIGN (func_type)
10545 && current_function_pretend_args_size == 0
10546 && saved_regs_mask & (1 << LR_REGNUM)
10547 && !current_function_calls_eh_return)
10549 saved_regs_mask &= ~ (1 << LR_REGNUM);
10550 saved_regs_mask |= (1 << PC_REGNUM);
10551 rfe = IS_INTERRUPT (func_type);
10556 /* Load the registers off the stack. If we only have one register
10557 to load use the LDR instruction - it is faster. For Thumb-2
10558 always use pop and the assembler will pick the best instruction.*/
10559 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
10560 && !IS_INTERRUPT(func_type))
10562 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10564 else if (saved_regs_mask)
10566 if (saved_regs_mask & (1 << SP_REGNUM))
10567 /* Note - write back to the stack register is not enabled
10568 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10569 in the list of registers and if we add writeback the
10570 instruction becomes UNPREDICTABLE. */
10571 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
10573 else if (TARGET_ARM)
10574 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
10577 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
10580 if (current_function_pretend_args_size)
10582 /* Unwind the pre-pushed regs. */
10583 operands[0] = operands[1] = stack_pointer_rtx;
10584 operands[2] = GEN_INT (current_function_pretend_args_size);
10585 output_add_immediate (operands);
10589 /* We may have already restored PC directly from the stack. */
10590 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10593 /* Stack adjustment for exception handler. */
10594 if (current_function_calls_eh_return)
10595 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10596 ARM_EH_STACKADJ_REGNUM);
10598 /* Generate the return instruction. */
10599 switch ((int) ARM_FUNC_TYPE (func_type))
10603 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10606 case ARM_FT_EXCEPTION:
10607 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10610 case ARM_FT_INTERWORKED:
10611 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10615 if (IS_STACKALIGN (func_type))
10617 /* See comment in arm_expand_prologue. */
10618 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
10620 if (arm_arch5 || arm_arch4t)
10621 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10623 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10631 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10632 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10634 arm_stack_offsets *offsets;
10640 /* Emit any call-via-reg trampolines that are needed for v4t support
10641 of call_reg and call_value_reg type insns. */
10642 for (regno = 0; regno < LR_REGNUM; regno++)
10644 rtx label = cfun->machine->call_via[regno];
10648 switch_to_section (function_section (current_function_decl));
10649 targetm.asm_out.internal_label (asm_out_file, "L",
10650 CODE_LABEL_NUMBER (label));
10651 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10655 /* ??? Probably not safe to set this here, since it assumes that a
10656 function will be emitted as assembly immediately after we generate
10657 RTL for it. This does not happen for inline functions. */
10658 return_used_this_function = 0;
10660 else /* TARGET_32BIT */
10662 /* We need to take into account any stack-frame rounding. */
10663 offsets = arm_get_frame_offsets ();
10665 gcc_assert (!use_return_insn (FALSE, NULL)
10666 || !return_used_this_function
10667 || offsets->saved_regs == offsets->outgoing_args
10668 || frame_pointer_needed);
10670 /* Reset the ARM-specific per-function variables. */
10671 after_arm_reorg = 0;
10675 /* Generate and emit an insn that we will recognize as a push_multi.
10676 Unfortunately, since this insn does not reflect very well the actual
10677 semantics of the operation, we need to annotate the insn for the benefit
10678 of DWARF2 frame unwind information. */
10680 emit_multi_reg_push (unsigned long mask)
10683 int num_dwarf_regs;
10687 int dwarf_par_index;
10690 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10691 if (mask & (1 << i))
10694 gcc_assert (num_regs && num_regs <= 16);
10696 /* We don't record the PC in the dwarf frame information. */
10697 num_dwarf_regs = num_regs;
10698 if (mask & (1 << PC_REGNUM))
10701 /* For the body of the insn we are going to generate an UNSPEC in
10702 parallel with several USEs. This allows the insn to be recognized
10703 by the push_multi pattern in the arm.md file. The insn looks
10704 something like this:
10707 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10708 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10709 (use (reg:SI 11 fp))
10710 (use (reg:SI 12 ip))
10711 (use (reg:SI 14 lr))
10712 (use (reg:SI 15 pc))
10715 For the frame note however, we try to be more explicit and actually
10716 show each register being stored into the stack frame, plus a (single)
10717 decrement of the stack pointer. We do it this way in order to be
10718 friendly to the stack unwinding code, which only wants to see a single
10719 stack decrement per instruction. The RTL we generate for the note looks
10720 something like this:
10723 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10724 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10725 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10726 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10727 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10730 This sequence is used both by the code to support stack unwinding for
10731 exceptions handlers and the code to generate dwarf2 frame debugging. */
10733 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10734 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10735 dwarf_par_index = 1;
10737 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10739 if (mask & (1 << i))
10741 reg = gen_rtx_REG (SImode, i);
10743 XVECEXP (par, 0, 0)
10744 = gen_rtx_SET (VOIDmode,
10745 gen_frame_mem (BLKmode,
10746 gen_rtx_PRE_DEC (BLKmode,
10747 stack_pointer_rtx)),
10748 gen_rtx_UNSPEC (BLKmode,
10749 gen_rtvec (1, reg),
10750 UNSPEC_PUSH_MULT));
10752 if (i != PC_REGNUM)
10754 tmp = gen_rtx_SET (VOIDmode,
10755 gen_frame_mem (SImode, stack_pointer_rtx),
10757 RTX_FRAME_RELATED_P (tmp) = 1;
10758 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10766 for (j = 1, i++; j < num_regs; i++)
10768 if (mask & (1 << i))
10770 reg = gen_rtx_REG (SImode, i);
10772 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10774 if (i != PC_REGNUM)
10777 = gen_rtx_SET (VOIDmode,
10778 gen_frame_mem (SImode,
10779 plus_constant (stack_pointer_rtx,
10782 RTX_FRAME_RELATED_P (tmp) = 1;
10783 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10790 par = emit_insn (par);
10792 tmp = gen_rtx_SET (VOIDmode,
10794 plus_constant (stack_pointer_rtx, -4 * num_regs));
10795 RTX_FRAME_RELATED_P (tmp) = 1;
10796 XVECEXP (dwarf, 0, 0) = tmp;
10798 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10803 /* Calculate the size of the return value that is passed in registers. */
10805 arm_size_return_regs (void)
10807 enum machine_mode mode;
10809 if (current_function_return_rtx != 0)
10810 mode = GET_MODE (current_function_return_rtx);
10812 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10814 return GET_MODE_SIZE (mode);
10818 emit_sfm (int base_reg, int count)
10825 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10826 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10828 reg = gen_rtx_REG (XFmode, base_reg++);
10830 XVECEXP (par, 0, 0)
10831 = gen_rtx_SET (VOIDmode,
10832 gen_frame_mem (BLKmode,
10833 gen_rtx_PRE_DEC (BLKmode,
10834 stack_pointer_rtx)),
10835 gen_rtx_UNSPEC (BLKmode,
10836 gen_rtvec (1, reg),
10837 UNSPEC_PUSH_MULT));
10838 tmp = gen_rtx_SET (VOIDmode,
10839 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
10840 RTX_FRAME_RELATED_P (tmp) = 1;
10841 XVECEXP (dwarf, 0, 1) = tmp;
10843 for (i = 1; i < count; i++)
10845 reg = gen_rtx_REG (XFmode, base_reg++);
10846 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10848 tmp = gen_rtx_SET (VOIDmode,
10849 gen_frame_mem (XFmode,
10850 plus_constant (stack_pointer_rtx,
10853 RTX_FRAME_RELATED_P (tmp) = 1;
10854 XVECEXP (dwarf, 0, i + 1) = tmp;
10857 tmp = gen_rtx_SET (VOIDmode,
10859 plus_constant (stack_pointer_rtx, -12 * count));
10861 RTX_FRAME_RELATED_P (tmp) = 1;
10862 XVECEXP (dwarf, 0, 0) = tmp;
10864 par = emit_insn (par);
10865 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10871 /* Return true if the current function needs to save/restore LR. */
10874 thumb_force_lr_save (void)
10876 return !cfun->machine->lr_save_eliminated
10877 && (!leaf_function_p ()
10878 || thumb_far_jump_used_p ()
10879 || regs_ever_live [LR_REGNUM]);
10883 /* Compute the distance from register FROM to register TO.
10884 These can be the arg pointer (26), the soft frame pointer (25),
10885 the stack pointer (13) or the hard frame pointer (11).
10886 In thumb mode r7 is used as the soft frame pointer, if needed.
10887 Typical stack layout looks like this:
10889 old stack pointer -> | |
10892 | | saved arguments for
10893 | | vararg functions
10896 hard FP & arg pointer -> | | \
10904 soft frame pointer -> | | /
10909 locals base pointer -> | | /
10914 current stack pointer -> | | /
10917 For a given function some or all of these stack components
10918 may not be needed, giving rise to the possibility of
10919 eliminating some of the registers.
10921 The values returned by this function must reflect the behavior
10922 of arm_expand_prologue() and arm_compute_save_reg_mask().
10924 The sign of the number returned reflects the direction of stack
10925 growth, so the values are positive for all eliminations except
10926 from the soft frame pointer to the hard frame pointer.
10928 SFP may point just inside the local variables block to ensure correct
10932 /* Calculate stack offsets. These are used to calculate register elimination
10933 offsets and in prologue/epilogue code. */
10935 static arm_stack_offsets *
10936 arm_get_frame_offsets (void)
10938 struct arm_stack_offsets *offsets;
10939 unsigned long func_type;
10942 HOST_WIDE_INT frame_size;
10944 offsets = &cfun->machine->stack_offsets;
10946 /* We need to know if we are a leaf function. Unfortunately, it
10947 is possible to be called after start_sequence has been called,
10948 which causes get_insns to return the insns for the sequence,
10949 not the function, which will cause leaf_function_p to return
10950 the incorrect result.
10952 to know about leaf functions once reload has completed, and the
10953 frame size cannot be changed after that time, so we can safely
10954 use the cached value. */
10956 if (reload_completed)
10959 /* Initially this is the size of the local variables. It will translated
10960 into an offset once we have determined the size of preceding data. */
10961 frame_size = ROUND_UP_WORD (get_frame_size ());
10963 leaf = leaf_function_p ();
10965 /* Space for variadic functions. */
10966 offsets->saved_args = current_function_pretend_args_size;
10968 /* In Thumb mode this is incorrect, but never used. */
10969 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10973 unsigned int regno;
10975 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10977 /* We know that SP will be doubleword aligned on entry, and we must
10978 preserve that condition at any subroutine call. We also require the
10979 soft frame pointer to be doubleword aligned. */
10981 if (TARGET_REALLY_IWMMXT)
10983 /* Check for the call-saved iWMMXt registers. */
10984 for (regno = FIRST_IWMMXT_REGNUM;
10985 regno <= LAST_IWMMXT_REGNUM;
10987 if (regs_ever_live [regno] && ! call_used_regs [regno])
10991 func_type = arm_current_func_type ();
10992 if (! IS_VOLATILE (func_type))
10994 /* Space for saved FPA registers. */
10995 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10996 if (regs_ever_live[regno] && ! call_used_regs[regno])
10999 /* Space for saved VFP registers. */
11000 if (TARGET_HARD_FLOAT && TARGET_VFP)
11001 saved += arm_get_vfp_saved_size ();
11004 else /* TARGET_THUMB1 */
11006 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
11007 if (TARGET_BACKTRACE)
11011 /* Saved registers include the stack frame. */
11012 offsets->saved_regs = offsets->saved_args + saved;
11013 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
11014 /* A leaf function does not need any stack alignment if it has nothing
11016 if (leaf && frame_size == 0)
11018 offsets->outgoing_args = offsets->soft_frame;
11022 /* Ensure SFP has the correct alignment. */
11023 if (ARM_DOUBLEWORD_ALIGN
11024 && (offsets->soft_frame & 7))
11025 offsets->soft_frame += 4;
11027 offsets->locals_base = offsets->soft_frame + frame_size;
11028 offsets->outgoing_args = (offsets->locals_base
11029 + current_function_outgoing_args_size);
11031 if (ARM_DOUBLEWORD_ALIGN)
11033 /* Ensure SP remains doubleword aligned. */
11034 if (offsets->outgoing_args & 7)
11035 offsets->outgoing_args += 4;
11036 gcc_assert (!(offsets->outgoing_args & 7));
11043 /* Calculate the relative offsets for the different stack pointers. Positive
11044 offsets are in the direction of stack growth. */
11047 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
11049 arm_stack_offsets *offsets;
11051 offsets = arm_get_frame_offsets ();
11053 /* OK, now we have enough information to compute the distances.
11054 There must be an entry in these switch tables for each pair
11055 of registers in ELIMINABLE_REGS, even if some of the entries
11056 seem to be redundant or useless. */
11059 case ARG_POINTER_REGNUM:
11062 case THUMB_HARD_FRAME_POINTER_REGNUM:
11065 case FRAME_POINTER_REGNUM:
11066 /* This is the reverse of the soft frame pointer
11067 to hard frame pointer elimination below. */
11068 return offsets->soft_frame - offsets->saved_args;
11070 case ARM_HARD_FRAME_POINTER_REGNUM:
11071 /* If there is no stack frame then the hard
11072 frame pointer and the arg pointer coincide. */
11073 if (offsets->frame == offsets->saved_regs)
11075 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11076 return (frame_pointer_needed
11077 && cfun->static_chain_decl != NULL
11078 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
11080 case STACK_POINTER_REGNUM:
11081 /* If nothing has been pushed on the stack at all
11082 then this will return -4. This *is* correct! */
11083 return offsets->outgoing_args - (offsets->saved_args + 4);
11086 gcc_unreachable ();
11088 gcc_unreachable ();
11090 case FRAME_POINTER_REGNUM:
11093 case THUMB_HARD_FRAME_POINTER_REGNUM:
11096 case ARM_HARD_FRAME_POINTER_REGNUM:
11097 /* The hard frame pointer points to the top entry in the
11098 stack frame. The soft frame pointer to the bottom entry
11099 in the stack frame. If there is no stack frame at all,
11100 then they are identical. */
11102 return offsets->frame - offsets->soft_frame;
11104 case STACK_POINTER_REGNUM:
11105 return offsets->outgoing_args - offsets->soft_frame;
11108 gcc_unreachable ();
11110 gcc_unreachable ();
11113 /* You cannot eliminate from the stack pointer.
11114 In theory you could eliminate from the hard frame
11115 pointer to the stack pointer, but this will never
11116 happen, since if a stack frame is not needed the
11117 hard frame pointer will never be used. */
11118 gcc_unreachable ();
11123 /* Emit RTL to save coprocessor registers on function entry. Returns the
11124 number of bytes pushed. */
11127 arm_save_coproc_regs(void)
11129 int saved_size = 0;
11131 unsigned start_reg;
11134 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
11135 if (regs_ever_live[reg] && ! call_used_regs [reg])
11137 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
11138 insn = gen_rtx_MEM (V2SImode, insn);
11139 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
11140 RTX_FRAME_RELATED_P (insn) = 1;
11144 /* Save any floating point call-saved registers used by this
11146 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
11148 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11149 if (regs_ever_live[reg] && !call_used_regs[reg])
11151 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
11152 insn = gen_rtx_MEM (XFmode, insn);
11153 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
11154 RTX_FRAME_RELATED_P (insn) = 1;
11160 start_reg = LAST_FPA_REGNUM;
11162 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11164 if (regs_ever_live[reg] && !call_used_regs[reg])
11166 if (start_reg - reg == 3)
11168 insn = emit_sfm (reg, 4);
11169 RTX_FRAME_RELATED_P (insn) = 1;
11171 start_reg = reg - 1;
11176 if (start_reg != reg)
11178 insn = emit_sfm (reg + 1, start_reg - reg);
11179 RTX_FRAME_RELATED_P (insn) = 1;
11180 saved_size += (start_reg - reg) * 12;
11182 start_reg = reg - 1;
11186 if (start_reg != reg)
11188 insn = emit_sfm (reg + 1, start_reg - reg);
11189 saved_size += (start_reg - reg) * 12;
11190 RTX_FRAME_RELATED_P (insn) = 1;
11193 if (TARGET_HARD_FLOAT && TARGET_VFP)
11195 start_reg = FIRST_VFP_REGNUM;
11197 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11199 if ((!regs_ever_live[reg] || call_used_regs[reg])
11200 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
11202 if (start_reg != reg)
11203 saved_size += vfp_emit_fstmd (start_reg,
11204 (reg - start_reg) / 2);
11205 start_reg = reg + 2;
11208 if (start_reg != reg)
11209 saved_size += vfp_emit_fstmd (start_reg,
11210 (reg - start_reg) / 2);
11216 /* Set the Thumb frame pointer from the stack pointer. */
11219 thumb_set_frame_pointer (arm_stack_offsets *offsets)
11221 HOST_WIDE_INT amount;
11224 amount = offsets->outgoing_args - offsets->locals_base;
11226 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11227 stack_pointer_rtx, GEN_INT (amount)));
11230 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
11231 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11232 hard_frame_pointer_rtx,
11233 stack_pointer_rtx));
11234 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11235 plus_constant (stack_pointer_rtx, amount));
11236 RTX_FRAME_RELATED_P (dwarf) = 1;
11237 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11241 RTX_FRAME_RELATED_P (insn) = 1;
11244 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11247 arm_expand_prologue (void)
11252 unsigned long live_regs_mask;
11253 unsigned long func_type;
11255 int saved_pretend_args = 0;
11256 int saved_regs = 0;
11257 unsigned HOST_WIDE_INT args_to_push;
11258 arm_stack_offsets *offsets;
11260 func_type = arm_current_func_type ();
11262 /* Naked functions don't have prologues. */
11263 if (IS_NAKED (func_type))
11266 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11267 args_to_push = current_function_pretend_args_size;
11269 /* Compute which register we will have to save onto the stack. */
11270 live_regs_mask = arm_compute_save_reg_mask ();
11272 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
11274 if (IS_STACKALIGN (func_type))
11279 /* Handle a word-aligned stack pointer. We generate the following:
11284 <save and restore r0 in normal prologue/epilogue>
11288 The unwinder doesn't need to know about the stack realignment.
11289 Just tell it we saved SP in r0. */
11290 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
11292 r0 = gen_rtx_REG (SImode, 0);
11293 r1 = gen_rtx_REG (SImode, 1);
11294 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
11295 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
11296 insn = gen_movsi (r0, stack_pointer_rtx);
11297 RTX_FRAME_RELATED_P (insn) = 1;
11298 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11299 dwarf, REG_NOTES (insn));
11301 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
11302 emit_insn (gen_movsi (stack_pointer_rtx, r1));
11305 if (frame_pointer_needed && TARGET_ARM)
11307 if (IS_INTERRUPT (func_type))
11309 /* Interrupt functions must not corrupt any registers.
11310 Creating a frame pointer however, corrupts the IP
11311 register, so we must push it first. */
11312 insn = emit_multi_reg_push (1 << IP_REGNUM);
11314 /* Do not set RTX_FRAME_RELATED_P on this insn.
11315 The dwarf stack unwinding code only wants to see one
11316 stack decrement per function, and this is not it. If
11317 this instruction is labeled as being part of the frame
11318 creation sequence then dwarf2out_frame_debug_expr will
11319 die when it encounters the assignment of IP to FP
11320 later on, since the use of SP here establishes SP as
11321 the CFA register and not IP.
11323 Anyway this instruction is not really part of the stack
11324 frame creation although it is part of the prologue. */
11326 else if (IS_NESTED (func_type))
11328 /* The Static chain register is the same as the IP register
11329 used as a scratch register during stack frame creation.
11330 To get around this need to find somewhere to store IP
11331 whilst the frame is being created. We try the following
11334 1. The last argument register.
11335 2. A slot on the stack above the frame. (This only
11336 works if the function is not a varargs function).
11337 3. Register r3, after pushing the argument registers
11340 Note - we only need to tell the dwarf2 backend about the SP
11341 adjustment in the second variant; the static chain register
11342 doesn't need to be unwound, as it doesn't contain a value
11343 inherited from the caller. */
11345 if (regs_ever_live[3] == 0)
11346 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11347 else if (args_to_push == 0)
11351 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
11352 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
11355 /* Just tell the dwarf backend that we adjusted SP. */
11356 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11357 plus_constant (stack_pointer_rtx,
11359 RTX_FRAME_RELATED_P (insn) = 1;
11360 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11361 dwarf, REG_NOTES (insn));
11365 /* Store the args on the stack. */
11366 if (cfun->machine->uses_anonymous_args)
11367 insn = emit_multi_reg_push
11368 ((0xf0 >> (args_to_push / 4)) & 0xf);
11371 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11372 GEN_INT (- args_to_push)));
11374 RTX_FRAME_RELATED_P (insn) = 1;
11376 saved_pretend_args = 1;
11377 fp_offset = args_to_push;
11380 /* Now reuse r3 to preserve IP. */
11381 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11385 insn = emit_set_insn (ip_rtx,
11386 plus_constant (stack_pointer_rtx, fp_offset));
11387 RTX_FRAME_RELATED_P (insn) = 1;
11392 /* Push the argument registers, or reserve space for them. */
11393 if (cfun->machine->uses_anonymous_args)
11394 insn = emit_multi_reg_push
11395 ((0xf0 >> (args_to_push / 4)) & 0xf);
11398 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11399 GEN_INT (- args_to_push)));
11400 RTX_FRAME_RELATED_P (insn) = 1;
11403 /* If this is an interrupt service routine, and the link register
11404 is going to be pushed, and we are not creating a stack frame,
11405 (which would involve an extra push of IP and a pop in the epilogue)
11406 subtracting four from LR now will mean that the function return
11407 can be done with a single instruction. */
11408 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
11409 && (live_regs_mask & (1 << LR_REGNUM)) != 0
11410 && ! frame_pointer_needed
11413 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
11415 emit_set_insn (lr, plus_constant (lr, -4));
11418 if (live_regs_mask)
11420 insn = emit_multi_reg_push (live_regs_mask);
11421 saved_regs += bit_count (live_regs_mask) * 4;
11422 RTX_FRAME_RELATED_P (insn) = 1;
11425 if (! IS_VOLATILE (func_type))
11426 saved_regs += arm_save_coproc_regs ();
11428 if (frame_pointer_needed && TARGET_ARM)
11430 /* Create the new frame pointer. */
11432 insn = GEN_INT (-(4 + args_to_push + fp_offset));
11433 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
11434 RTX_FRAME_RELATED_P (insn) = 1;
11436 if (IS_NESTED (func_type))
11438 /* Recover the static chain register. */
11439 if (regs_ever_live [3] == 0
11440 || saved_pretend_args)
11441 insn = gen_rtx_REG (SImode, 3);
11442 else /* if (current_function_pretend_args_size == 0) */
11444 insn = plus_constant (hard_frame_pointer_rtx, 4);
11445 insn = gen_frame_mem (SImode, insn);
11447 emit_set_insn (ip_rtx, insn);
11448 /* Add a USE to stop propagate_one_insn() from barfing. */
11449 emit_insn (gen_prologue_use (ip_rtx));
11454 offsets = arm_get_frame_offsets ();
11455 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
11457 /* This add can produce multiple insns for a large constant, so we
11458 need to get tricky. */
11459 rtx last = get_last_insn ();
11461 amount = GEN_INT (offsets->saved_args + saved_regs
11462 - offsets->outgoing_args);
11464 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11468 last = last ? NEXT_INSN (last) : get_insns ();
11469 RTX_FRAME_RELATED_P (last) = 1;
11471 while (last != insn);
11473 /* If the frame pointer is needed, emit a special barrier that
11474 will prevent the scheduler from moving stores to the frame
11475 before the stack adjustment. */
11476 if (frame_pointer_needed)
11477 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
11478 hard_frame_pointer_rtx));
11482 if (frame_pointer_needed && TARGET_THUMB2)
11483 thumb_set_frame_pointer (offsets);
11485 if (flag_pic && arm_pic_register != INVALID_REGNUM)
11487 unsigned long mask;
11489 mask = live_regs_mask;
11490 mask &= THUMB2_WORK_REGS;
11491 if (!IS_NESTED (func_type))
11492 mask |= (1 << IP_REGNUM);
11493 arm_load_pic_register (mask);
11496 /* If we are profiling, make sure no instructions are scheduled before
11497 the call to mcount. Similarly if the user has requested no
11498 scheduling in the prolog. Similarly if we want non-call exceptions
11499 using the EABI unwinder, to prevent faulting instructions from being
11500 swapped with a stack adjustment. */
11501 if (current_function_profile || !TARGET_SCHED_PROLOG
11502 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
11503 emit_insn (gen_blockage ());
11505 /* If the link register is being kept alive, with the return address in it,
11506 then make sure that it does not get reused by the ce2 pass. */
11507 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
11509 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
11510 cfun->machine->lr_save_eliminated = 1;
11514 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11516 arm_print_condition (FILE *stream)
11518 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11520 /* Branch conversion is not implemented for Thumb-2. */
11523 output_operand_lossage ("predicated Thumb instruction");
11526 if (current_insn_predicate != NULL)
11528 output_operand_lossage
11529 ("predicated instruction in conditional sequence");
11533 fputs (arm_condition_codes[arm_current_cc], stream);
11535 else if (current_insn_predicate)
11537 enum arm_cond_code code;
11541 output_operand_lossage ("predicated Thumb instruction");
11545 code = get_arm_condition_code (current_insn_predicate);
11546 fputs (arm_condition_codes[code], stream);
11551 /* If CODE is 'd', then the X is a condition operand and the instruction
11552 should only be executed if the condition is true.
11553 if CODE is 'D', then the X is a condition operand and the instruction
11554 should only be executed if the condition is false: however, if the mode
11555 of the comparison is CCFPEmode, then always execute the instruction -- we
11556 do this because in these circumstances !GE does not necessarily imply LT;
11557 in these cases the instruction pattern will take care to make sure that
11558 an instruction containing %d will follow, thereby undoing the effects of
11559 doing this instruction unconditionally.
11560 If CODE is 'N' then X is a floating point operand that must be negated
11562 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11563 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11565 arm_print_operand (FILE *stream, rtx x, int code)
11570 fputs (ASM_COMMENT_START, stream);
11574 fputs (user_label_prefix, stream);
11578 fputs (REGISTER_PREFIX, stream);
11582 arm_print_condition (stream);
11586 /* Nothing in unified syntax, otherwise the current condition code. */
11587 if (!TARGET_UNIFIED_ASM)
11588 arm_print_condition (stream);
11592 /* The current condition code in unified syntax, otherwise nothing. */
11593 if (TARGET_UNIFIED_ASM)
11594 arm_print_condition (stream);
11598 /* The current condition code for a condition code setting instruction.
11599 Preceded by 's' in unified syntax, otherwise followed by 's'. */
11600 if (TARGET_UNIFIED_ASM)
11602 fputc('s', stream);
11603 arm_print_condition (stream);
11607 arm_print_condition (stream);
11608 fputc('s', stream);
11613 /* If the instruction is conditionally executed then print
11614 the current condition code, otherwise print 's'. */
11615 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
11616 if (current_insn_predicate)
11617 arm_print_condition (stream);
11619 fputc('s', stream);
11625 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11626 r = REAL_VALUE_NEGATE (r);
11627 fprintf (stream, "%s", fp_const_from_val (&r));
11632 if (GET_CODE (x) == CONST_INT)
11635 val = ARM_SIGN_EXTEND (~INTVAL (x));
11636 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11640 putc ('~', stream);
11641 output_addr_const (stream, x);
11646 /* The low 16 bits of an immediate constant. */
11647 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
11651 fprintf (stream, "%s", arithmetic_instr (x, 1));
11654 /* Truncate Cirrus shift counts. */
11656 if (GET_CODE (x) == CONST_INT)
11658 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11661 arm_print_operand (stream, x, 0);
11665 fprintf (stream, "%s", arithmetic_instr (x, 0));
11673 if (!shift_operator (x, SImode))
11675 output_operand_lossage ("invalid shift operand");
11679 shift = shift_op (x, &val);
11683 fprintf (stream, ", %s ", shift);
11685 arm_print_operand (stream, XEXP (x, 1), 0);
11687 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11692 /* An explanation of the 'Q', 'R' and 'H' register operands:
11694 In a pair of registers containing a DI or DF value the 'Q'
11695 operand returns the register number of the register containing
11696 the least significant part of the value. The 'R' operand returns
11697 the register number of the register containing the most
11698 significant part of the value.
11700 The 'H' operand returns the higher of the two register numbers.
11701 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11702 same as the 'Q' operand, since the most significant part of the
11703 value is held in the lower number register. The reverse is true
11704 on systems where WORDS_BIG_ENDIAN is false.
11706 The purpose of these operands is to distinguish between cases
11707 where the endian-ness of the values is important (for example
11708 when they are added together), and cases where the endian-ness
11709 is irrelevant, but the order of register operations is important.
11710 For example when loading a value from memory into a register
11711 pair, the endian-ness does not matter. Provided that the value
11712 from the lower memory address is put into the lower numbered
11713 register, and the value from the higher address is put into the
11714 higher numbered register, the load will work regardless of whether
11715 the value being loaded is big-wordian or little-wordian. The
11716 order of the two register loads can matter however, if the address
11717 of the memory location is actually held in one of the registers
11718 being overwritten by the load. */
11720 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11722 output_operand_lossage ("invalid operand for code '%c'", code);
11726 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11730 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11732 output_operand_lossage ("invalid operand for code '%c'", code);
11736 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11740 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11742 output_operand_lossage ("invalid operand for code '%c'", code);
11746 asm_fprintf (stream, "%r", REGNO (x) + 1);
11750 asm_fprintf (stream, "%r",
11751 GET_CODE (XEXP (x, 0)) == REG
11752 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11756 asm_fprintf (stream, "{%r-%r}",
11758 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11762 /* CONST_TRUE_RTX means always -- that's the default. */
11763 if (x == const_true_rtx)
11766 if (!COMPARISON_P (x))
11768 output_operand_lossage ("invalid operand for code '%c'", code);
11772 fputs (arm_condition_codes[get_arm_condition_code (x)],
11777 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11778 want to do that. */
11779 if (x == const_true_rtx)
11781 output_operand_lossage ("instruction never executed");
11784 if (!COMPARISON_P (x))
11786 output_operand_lossage ("invalid operand for code '%c'", code);
11790 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11791 (get_arm_condition_code (x))],
11795 /* Cirrus registers can be accessed in a variety of ways:
11796 single floating point (f)
11797 double floating point (d)
11799 64bit integer (dx). */
11800 case 'W': /* Cirrus register in F mode. */
11801 case 'X': /* Cirrus register in D mode. */
11802 case 'Y': /* Cirrus register in FX mode. */
11803 case 'Z': /* Cirrus register in DX mode. */
11804 gcc_assert (GET_CODE (x) == REG
11805 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
11807 fprintf (stream, "mv%s%s",
11809 : code == 'X' ? "d"
11810 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11814 /* Print cirrus register in the mode specified by the register's mode. */
11817 int mode = GET_MODE (x);
11819 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11821 output_operand_lossage ("invalid operand for code '%c'", code);
11825 fprintf (stream, "mv%s%s",
11826 mode == DFmode ? "d"
11827 : mode == SImode ? "fx"
11828 : mode == DImode ? "dx"
11829 : "f", reg_names[REGNO (x)] + 2);
11835 if (GET_CODE (x) != REG
11836 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11837 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11838 /* Bad value for wCG register number. */
11840 output_operand_lossage ("invalid operand for code '%c'", code);
11845 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11848 /* Print an iWMMXt control register name. */
11850 if (GET_CODE (x) != CONST_INT
11852 || INTVAL (x) >= 16)
11853 /* Bad value for wC register number. */
11855 output_operand_lossage ("invalid operand for code '%c'", code);
11861 static const char * wc_reg_names [16] =
11863 "wCID", "wCon", "wCSSF", "wCASF",
11864 "wC4", "wC5", "wC6", "wC7",
11865 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11866 "wC12", "wC13", "wC14", "wC15"
11869 fprintf (stream, wc_reg_names [INTVAL (x)]);
11873 /* Print a VFP double precision register name. */
11876 int mode = GET_MODE (x);
11879 if (mode != DImode && mode != DFmode)
11881 output_operand_lossage ("invalid operand for code '%c'", code);
11885 if (GET_CODE (x) != REG
11886 || !IS_VFP_REGNUM (REGNO (x)))
11888 output_operand_lossage ("invalid operand for code '%c'", code);
11892 num = REGNO(x) - FIRST_VFP_REGNUM;
11895 output_operand_lossage ("invalid operand for code '%c'", code);
11899 fprintf (stream, "d%d", num >> 1);
11906 output_operand_lossage ("missing operand");
11910 switch (GET_CODE (x))
11913 asm_fprintf (stream, "%r", REGNO (x));
11917 output_memory_reference_mode = GET_MODE (x);
11918 output_address (XEXP (x, 0));
11922 fprintf (stream, "#%s", fp_immediate_constant (x));
11926 gcc_assert (GET_CODE (x) != NEG);
11927 fputc ('#', stream);
11928 output_addr_const (stream, x);
11934 #ifndef AOF_ASSEMBLER
11935 /* Target hook for assembling integer objects. The ARM version needs to
11936 handle word-sized values specially. */
11938 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11940 if (size == UNITS_PER_WORD && aligned_p)
11942 fputs ("\t.word\t", asm_out_file);
11943 output_addr_const (asm_out_file, x);
11945 /* Mark symbols as position independent. We only do this in the
11946 .text segment, not in the .data segment. */
11947 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11948 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11950 if (GET_CODE (x) == SYMBOL_REF
11951 && (CONSTANT_POOL_ADDRESS_P (x)
11952 || SYMBOL_REF_LOCAL_P (x)))
11953 fputs ("(GOTOFF)", asm_out_file);
11954 else if (GET_CODE (x) == LABEL_REF)
11955 fputs ("(GOTOFF)", asm_out_file);
11957 fputs ("(GOT)", asm_out_file);
11959 fputc ('\n', asm_out_file);
11963 if (arm_vector_mode_supported_p (GET_MODE (x)))
11967 gcc_assert (GET_CODE (x) == CONST_VECTOR);
11969 units = CONST_VECTOR_NUNITS (x);
11971 switch (GET_MODE (x))
11973 case V2SImode: size = 4; break;
11974 case V4HImode: size = 2; break;
11975 case V8QImode: size = 1; break;
11977 gcc_unreachable ();
11980 for (i = 0; i < units; i++)
11984 elt = CONST_VECTOR_ELT (x, i);
11986 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11992 return default_assemble_integer (x, size, aligned_p);
11996 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
12000 if (!TARGET_AAPCS_BASED)
12003 default_named_section_asm_out_constructor
12004 : default_named_section_asm_out_destructor) (symbol, priority);
12008 /* Put these in the .init_array section, using a special relocation. */
12009 if (priority != DEFAULT_INIT_PRIORITY)
12012 sprintf (buf, "%s.%.5u",
12013 is_ctor ? ".init_array" : ".fini_array",
12015 s = get_section (buf, SECTION_WRITE, NULL_TREE);
12022 switch_to_section (s);
12023 assemble_align (POINTER_SIZE);
12024 fputs ("\t.word\t", asm_out_file);
12025 output_addr_const (asm_out_file, symbol);
12026 fputs ("(target1)\n", asm_out_file);
12029 /* Add a function to the list of static constructors. */
12032 arm_elf_asm_constructor (rtx symbol, int priority)
12034 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
12037 /* Add a function to the list of static destructors. */
12040 arm_elf_asm_destructor (rtx symbol, int priority)
12042 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
12046 /* A finite state machine takes care of noticing whether or not instructions
12047 can be conditionally executed, and thus decrease execution time and code
12048 size by deleting branch instructions. The fsm is controlled by
12049 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12051 /* The state of the fsm controlling condition codes are:
12052 0: normal, do nothing special
12053 1: make ASM_OUTPUT_OPCODE not output this instruction
12054 2: make ASM_OUTPUT_OPCODE not output this instruction
12055 3: make instructions conditional
12056 4: make instructions conditional
12058 State transitions (state->state by whom under condition):
12059 0 -> 1 final_prescan_insn if the `target' is a label
12060 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12061 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12062 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12063 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12064 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12065 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12066 (the target insn is arm_target_insn).
12068 If the jump clobbers the conditions then we use states 2 and 4.
12070 A similar thing can be done with conditional return insns.
12072 XXX In case the `target' is an unconditional branch, this conditionalising
12073 of the instructions always reduces code size, but not always execution
12074 time. But then, I want to reduce the code size to somewhere near what
12075 /bin/cc produces. */
12077 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12078 instructions. When a COND_EXEC instruction is seen the subsequent
12079 instructions are scanned so that multiple conditional instructions can be
12080 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12081 specify the length and true/false mask for the IT block. These will be
12082 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12084 /* Returns the index of the ARM condition code string in
12085 `arm_condition_codes'. COMPARISON should be an rtx like
12086 `(eq (...) (...))'. */
12087 static enum arm_cond_code
12088 get_arm_condition_code (rtx comparison)
12090 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
12092 enum rtx_code comp_code = GET_CODE (comparison);
12094 if (GET_MODE_CLASS (mode) != MODE_CC)
12095 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
12096 XEXP (comparison, 1));
12100 case CC_DNEmode: code = ARM_NE; goto dominance;
12101 case CC_DEQmode: code = ARM_EQ; goto dominance;
12102 case CC_DGEmode: code = ARM_GE; goto dominance;
12103 case CC_DGTmode: code = ARM_GT; goto dominance;
12104 case CC_DLEmode: code = ARM_LE; goto dominance;
12105 case CC_DLTmode: code = ARM_LT; goto dominance;
12106 case CC_DGEUmode: code = ARM_CS; goto dominance;
12107 case CC_DGTUmode: code = ARM_HI; goto dominance;
12108 case CC_DLEUmode: code = ARM_LS; goto dominance;
12109 case CC_DLTUmode: code = ARM_CC;
12112 gcc_assert (comp_code == EQ || comp_code == NE);
12114 if (comp_code == EQ)
12115 return ARM_INVERSE_CONDITION_CODE (code);
12121 case NE: return ARM_NE;
12122 case EQ: return ARM_EQ;
12123 case GE: return ARM_PL;
12124 case LT: return ARM_MI;
12125 default: gcc_unreachable ();
12131 case NE: return ARM_NE;
12132 case EQ: return ARM_EQ;
12133 default: gcc_unreachable ();
12139 case NE: return ARM_MI;
12140 case EQ: return ARM_PL;
12141 default: gcc_unreachable ();
12146 /* These encodings assume that AC=1 in the FPA system control
12147 byte. This allows us to handle all cases except UNEQ and
12151 case GE: return ARM_GE;
12152 case GT: return ARM_GT;
12153 case LE: return ARM_LS;
12154 case LT: return ARM_MI;
12155 case NE: return ARM_NE;
12156 case EQ: return ARM_EQ;
12157 case ORDERED: return ARM_VC;
12158 case UNORDERED: return ARM_VS;
12159 case UNLT: return ARM_LT;
12160 case UNLE: return ARM_LE;
12161 case UNGT: return ARM_HI;
12162 case UNGE: return ARM_PL;
12163 /* UNEQ and LTGT do not have a representation. */
12164 case UNEQ: /* Fall through. */
12165 case LTGT: /* Fall through. */
12166 default: gcc_unreachable ();
12172 case NE: return ARM_NE;
12173 case EQ: return ARM_EQ;
12174 case GE: return ARM_LE;
12175 case GT: return ARM_LT;
12176 case LE: return ARM_GE;
12177 case LT: return ARM_GT;
12178 case GEU: return ARM_LS;
12179 case GTU: return ARM_CC;
12180 case LEU: return ARM_CS;
12181 case LTU: return ARM_HI;
12182 default: gcc_unreachable ();
12188 case LTU: return ARM_CS;
12189 case GEU: return ARM_CC;
12190 default: gcc_unreachable ();
12196 case NE: return ARM_NE;
12197 case EQ: return ARM_EQ;
12198 case GE: return ARM_GE;
12199 case GT: return ARM_GT;
12200 case LE: return ARM_LE;
12201 case LT: return ARM_LT;
12202 case GEU: return ARM_CS;
12203 case GTU: return ARM_HI;
12204 case LEU: return ARM_LS;
12205 case LTU: return ARM_CC;
12206 default: gcc_unreachable ();
12209 default: gcc_unreachable ();
12213 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
12216 thumb2_final_prescan_insn (rtx insn)
12218 rtx first_insn = insn;
12219 rtx body = PATTERN (insn);
12221 enum arm_cond_code code;
12225 /* Remove the previous insn from the count of insns to be output. */
12226 if (arm_condexec_count)
12227 arm_condexec_count--;
12229 /* Nothing to do if we are already inside a conditional block. */
12230 if (arm_condexec_count)
12233 if (GET_CODE (body) != COND_EXEC)
12236 /* Conditional jumps are implemented directly. */
12237 if (GET_CODE (insn) == JUMP_INSN)
12240 predicate = COND_EXEC_TEST (body);
12241 arm_current_cc = get_arm_condition_code (predicate);
12243 n = get_attr_ce_count (insn);
12244 arm_condexec_count = 1;
12245 arm_condexec_mask = (1 << n) - 1;
12246 arm_condexec_masklen = n;
12247 /* See if subsequent instructions can be combined into the same block. */
12250 insn = next_nonnote_insn (insn);
12252 /* Jumping into the middle of an IT block is illegal, so a label or
12253 barrier terminates the block. */
12254 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
12257 body = PATTERN (insn);
12258 /* USE and CLOBBER aren't really insns, so just skip them. */
12259 if (GET_CODE (body) == USE
12260 || GET_CODE (body) == CLOBBER)
12263 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
12264 if (GET_CODE (body) != COND_EXEC)
12266 /* Allow up to 4 conditionally executed instructions in a block. */
12267 n = get_attr_ce_count (insn);
12268 if (arm_condexec_masklen + n > 4)
12271 predicate = COND_EXEC_TEST (body);
12272 code = get_arm_condition_code (predicate);
12273 mask = (1 << n) - 1;
12274 if (arm_current_cc == code)
12275 arm_condexec_mask |= (mask << arm_condexec_masklen);
12276 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
12279 arm_condexec_count++;
12280 arm_condexec_masklen += n;
12282 /* A jump must be the last instruction in a conditional block. */
12283 if (GET_CODE(insn) == JUMP_INSN)
12286 /* Restore recog_data (getting the attributes of other insns can
12287 destroy this array, but final.c assumes that it remains intact
12288 across this call). */
12289 extract_constrain_insn_cached (first_insn);
12293 arm_final_prescan_insn (rtx insn)
12295 /* BODY will hold the body of INSN. */
12296 rtx body = PATTERN (insn);
12298 /* This will be 1 if trying to repeat the trick, and things need to be
12299 reversed if it appears to fail. */
12302 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12303 taken are clobbered, even if the rtl suggests otherwise. It also
12304 means that we have to grub around within the jump expression to find
12305 out what the conditions are when the jump isn't taken. */
12306 int jump_clobbers = 0;
12308 /* If we start with a return insn, we only succeed if we find another one. */
12309 int seeking_return = 0;
12311 /* START_INSN will hold the insn from where we start looking. This is the
12312 first insn after the following code_label if REVERSE is true. */
12313 rtx start_insn = insn;
12315 /* If in state 4, check if the target branch is reached, in order to
12316 change back to state 0. */
12317 if (arm_ccfsm_state == 4)
12319 if (insn == arm_target_insn)
12321 arm_target_insn = NULL;
12322 arm_ccfsm_state = 0;
12327 /* If in state 3, it is possible to repeat the trick, if this insn is an
12328 unconditional branch to a label, and immediately following this branch
12329 is the previous target label which is only used once, and the label this
12330 branch jumps to is not too far off. */
12331 if (arm_ccfsm_state == 3)
12333 if (simplejump_p (insn))
12335 start_insn = next_nonnote_insn (start_insn);
12336 if (GET_CODE (start_insn) == BARRIER)
12338 /* XXX Isn't this always a barrier? */
12339 start_insn = next_nonnote_insn (start_insn);
12341 if (GET_CODE (start_insn) == CODE_LABEL
12342 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12343 && LABEL_NUSES (start_insn) == 1)
12348 else if (GET_CODE (body) == RETURN)
12350 start_insn = next_nonnote_insn (start_insn);
12351 if (GET_CODE (start_insn) == BARRIER)
12352 start_insn = next_nonnote_insn (start_insn);
12353 if (GET_CODE (start_insn) == CODE_LABEL
12354 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12355 && LABEL_NUSES (start_insn) == 1)
12358 seeking_return = 1;
12367 gcc_assert (!arm_ccfsm_state || reverse);
12368 if (GET_CODE (insn) != JUMP_INSN)
12371 /* This jump might be paralleled with a clobber of the condition codes
12372 the jump should always come first */
12373 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
12374 body = XVECEXP (body, 0, 0);
12377 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
12378 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
12381 int fail = FALSE, succeed = FALSE;
12382 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12383 int then_not_else = TRUE;
12384 rtx this_insn = start_insn, label = 0;
12386 /* If the jump cannot be done with one instruction, we cannot
12387 conditionally execute the instruction in the inverse case. */
12388 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
12394 /* Register the insn jumped to. */
12397 if (!seeking_return)
12398 label = XEXP (SET_SRC (body), 0);
12400 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
12401 label = XEXP (XEXP (SET_SRC (body), 1), 0);
12402 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
12404 label = XEXP (XEXP (SET_SRC (body), 2), 0);
12405 then_not_else = FALSE;
12407 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
12408 seeking_return = 1;
12409 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
12411 seeking_return = 1;
12412 then_not_else = FALSE;
12415 gcc_unreachable ();
12417 /* See how many insns this branch skips, and what kind of insns. If all
12418 insns are okay, and the label or unconditional branch to the same
12419 label is not too far away, succeed. */
12420 for (insns_skipped = 0;
12421 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
12425 this_insn = next_nonnote_insn (this_insn);
12429 switch (GET_CODE (this_insn))
12432 /* Succeed if it is the target label, otherwise fail since
12433 control falls in from somewhere else. */
12434 if (this_insn == label)
12438 arm_ccfsm_state = 2;
12439 this_insn = next_nonnote_insn (this_insn);
12442 arm_ccfsm_state = 1;
12450 /* Succeed if the following insn is the target label.
12452 If return insns are used then the last insn in a function
12453 will be a barrier. */
12454 this_insn = next_nonnote_insn (this_insn);
12455 if (this_insn && this_insn == label)
12459 arm_ccfsm_state = 2;
12460 this_insn = next_nonnote_insn (this_insn);
12463 arm_ccfsm_state = 1;
12471 /* The AAPCS says that conditional calls should not be
12472 used since they make interworking inefficient (the
12473 linker can't transform BL<cond> into BLX). That's
12474 only a problem if the machine has BLX. */
12481 /* Succeed if the following insn is the target label, or
12482 if the following two insns are a barrier and the
12484 this_insn = next_nonnote_insn (this_insn);
12485 if (this_insn && GET_CODE (this_insn) == BARRIER)
12486 this_insn = next_nonnote_insn (this_insn);
12488 if (this_insn && this_insn == label
12489 && insns_skipped < max_insns_skipped)
12493 arm_ccfsm_state = 2;
12494 this_insn = next_nonnote_insn (this_insn);
12497 arm_ccfsm_state = 1;
12505 /* If this is an unconditional branch to the same label, succeed.
12506 If it is to another label, do nothing. If it is conditional,
12508 /* XXX Probably, the tests for SET and the PC are
12511 scanbody = PATTERN (this_insn);
12512 if (GET_CODE (scanbody) == SET
12513 && GET_CODE (SET_DEST (scanbody)) == PC)
12515 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
12516 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
12518 arm_ccfsm_state = 2;
12521 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
12524 /* Fail if a conditional return is undesirable (e.g. on a
12525 StrongARM), but still allow this if optimizing for size. */
12526 else if (GET_CODE (scanbody) == RETURN
12527 && !use_return_insn (TRUE, NULL)
12530 else if (GET_CODE (scanbody) == RETURN
12533 arm_ccfsm_state = 2;
12536 else if (GET_CODE (scanbody) == PARALLEL)
12538 switch (get_attr_conds (this_insn))
12548 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
12553 /* Instructions using or affecting the condition codes make it
12555 scanbody = PATTERN (this_insn);
12556 if (!(GET_CODE (scanbody) == SET
12557 || GET_CODE (scanbody) == PARALLEL)
12558 || get_attr_conds (this_insn) != CONDS_NOCOND)
12561 /* A conditional cirrus instruction must be followed by
12562 a non Cirrus instruction. However, since we
12563 conditionalize instructions in this function and by
12564 the time we get here we can't add instructions
12565 (nops), because shorten_branches() has already been
12566 called, we will disable conditionalizing Cirrus
12567 instructions to be safe. */
12568 if (GET_CODE (scanbody) != USE
12569 && GET_CODE (scanbody) != CLOBBER
12570 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
12580 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
12581 arm_target_label = CODE_LABEL_NUMBER (label);
12584 gcc_assert (seeking_return || arm_ccfsm_state == 2);
12586 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
12588 this_insn = next_nonnote_insn (this_insn);
12589 gcc_assert (!this_insn
12590 || (GET_CODE (this_insn) != BARRIER
12591 && GET_CODE (this_insn) != CODE_LABEL));
12595 /* Oh, dear! we ran off the end.. give up. */
12596 extract_constrain_insn_cached (insn);
12597 arm_ccfsm_state = 0;
12598 arm_target_insn = NULL;
12601 arm_target_insn = this_insn;
12605 gcc_assert (!reverse);
12607 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
12609 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
12610 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12611 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
12612 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12616 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12619 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
12623 if (reverse || then_not_else)
12624 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12627 /* Restore recog_data (getting the attributes of other insns can
12628 destroy this array, but final.c assumes that it remains intact
12629 across this call. */
12630 extract_constrain_insn_cached (insn);
12634 /* Output IT instructions. */
12636 thumb2_asm_output_opcode (FILE * stream)
12641 if (arm_condexec_mask)
12643 for (n = 0; n < arm_condexec_masklen; n++)
12644 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
12646 asm_fprintf(stream, "i%s\t%s\n\t", buff,
12647 arm_condition_codes[arm_current_cc]);
12648 arm_condexec_mask = 0;
12652 /* Returns true if REGNO is a valid register
12653 for holding a quantity of type MODE. */
12655 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
12657 if (GET_MODE_CLASS (mode) == MODE_CC)
12658 return (regno == CC_REGNUM
12659 || (TARGET_HARD_FLOAT && TARGET_VFP
12660 && regno == VFPCC_REGNUM));
12663 /* For the Thumb we only allow values bigger than SImode in
12664 registers 0 - 6, so that there is always a second low
12665 register available to hold the upper part of the value.
12666 We probably we ought to ensure that the register is the
12667 start of an even numbered register pair. */
12668 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
12670 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
12671 && IS_CIRRUS_REGNUM (regno))
12672 /* We have outlawed SI values in Cirrus registers because they
12673 reside in the lower 32 bits, but SF values reside in the
12674 upper 32 bits. This causes gcc all sorts of grief. We can't
12675 even split the registers into pairs because Cirrus SI values
12676 get sign extended to 64bits-- aldyh. */
12677 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
12679 if (TARGET_HARD_FLOAT && TARGET_VFP
12680 && IS_VFP_REGNUM (regno))
12682 if (mode == SFmode || mode == SImode)
12685 /* DFmode values are only valid in even register pairs. */
12686 if (mode == DFmode)
12687 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
12691 if (TARGET_REALLY_IWMMXT)
12693 if (IS_IWMMXT_GR_REGNUM (regno))
12694 return mode == SImode;
12696 if (IS_IWMMXT_REGNUM (regno))
12697 return VALID_IWMMXT_REG_MODE (mode);
12700 /* We allow any value to be stored in the general registers.
12701 Restrict doubleword quantities to even register pairs so that we can
12703 if (regno <= LAST_ARM_REGNUM)
12704 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
12706 if (regno == FRAME_POINTER_REGNUM
12707 || regno == ARG_POINTER_REGNUM)
12708 /* We only allow integers in the fake hard registers. */
12709 return GET_MODE_CLASS (mode) == MODE_INT;
12711 /* The only registers left are the FPA registers
12712 which we only allow to hold FP values. */
12713 return (TARGET_HARD_FLOAT && TARGET_FPA
12714 && GET_MODE_CLASS (mode) == MODE_FLOAT
12715 && regno >= FIRST_FPA_REGNUM
12716 && regno <= LAST_FPA_REGNUM);
12719 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
12720 not used in arm mode. */
12722 arm_regno_class (int regno)
12726 if (regno == STACK_POINTER_REGNUM)
12728 if (regno == CC_REGNUM)
12735 if (TARGET_THUMB2 && regno < 8)
12738 if ( regno <= LAST_ARM_REGNUM
12739 || regno == FRAME_POINTER_REGNUM
12740 || regno == ARG_POINTER_REGNUM)
12741 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
12743 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
12744 return TARGET_THUMB2 ? CC_REG : NO_REGS;
12746 if (IS_CIRRUS_REGNUM (regno))
12747 return CIRRUS_REGS;
12749 if (IS_VFP_REGNUM (regno))
12752 if (IS_IWMMXT_REGNUM (regno))
12753 return IWMMXT_REGS;
12755 if (IS_IWMMXT_GR_REGNUM (regno))
12756 return IWMMXT_GR_REGS;
12761 /* Handle a special case when computing the offset
12762 of an argument from the frame pointer. */
12764 arm_debugger_arg_offset (int value, rtx addr)
12768 /* We are only interested if dbxout_parms() failed to compute the offset. */
12772 /* We can only cope with the case where the address is held in a register. */
12773 if (GET_CODE (addr) != REG)
12776 /* If we are using the frame pointer to point at the argument, then
12777 an offset of 0 is correct. */
12778 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
12781 /* If we are using the stack pointer to point at the
12782 argument, then an offset of 0 is correct. */
12783 /* ??? Check this is consistent with thumb2 frame layout. */
12784 if ((TARGET_THUMB || !frame_pointer_needed)
12785 && REGNO (addr) == SP_REGNUM)
12788 /* Oh dear. The argument is pointed to by a register rather
12789 than being held in a register, or being stored at a known
12790 offset from the frame pointer. Since GDB only understands
12791 those two kinds of argument we must translate the address
12792 held in the register into an offset from the frame pointer.
12793 We do this by searching through the insns for the function
12794 looking to see where this register gets its value. If the
12795 register is initialized from the frame pointer plus an offset
12796 then we are in luck and we can continue, otherwise we give up.
12798 This code is exercised by producing debugging information
12799 for a function with arguments like this:
12801 double func (double a, double b, int c, double d) {return d;}
12803 Without this code the stab for parameter 'd' will be set to
12804 an offset of 0 from the frame pointer, rather than 8. */
12806 /* The if() statement says:
12808 If the insn is a normal instruction
12809 and if the insn is setting the value in a register
12810 and if the register being set is the register holding the address of the argument
12811 and if the address is computing by an addition
12812 that involves adding to a register
12813 which is the frame pointer
12818 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12820 if ( GET_CODE (insn) == INSN
12821 && GET_CODE (PATTERN (insn)) == SET
12822 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
12823 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
12824 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
12825 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12826 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
12829 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
12838 warning (0, "unable to compute real location of stacked parameter");
12839 value = 8; /* XXX magic hack */
12845 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12848 if ((MASK) & insn_flags) \
12849 add_builtin_function ((NAME), (TYPE), (CODE), \
12850 BUILT_IN_MD, NULL, NULL_TREE); \
12854 struct builtin_description
12856 const unsigned int mask;
12857 const enum insn_code icode;
12858 const char * const name;
12859 const enum arm_builtins code;
12860 const enum rtx_code comparison;
12861 const unsigned int flag;
12864 static const struct builtin_description bdesc_2arg[] =
12866 #define IWMMXT_BUILTIN(code, string, builtin) \
12867 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12868 ARM_BUILTIN_##builtin, 0, 0 },
12870 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
12871 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
12872 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
12873 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
12874 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
12875 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
12876 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
12877 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
12878 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
12879 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
12880 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
12881 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
12882 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
12883 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12884 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12885 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12886 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12887 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12888 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12889 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12890 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12891 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12892 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12893 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12894 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12895 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12896 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12897 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12898 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12899 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12900 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12901 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12902 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12903 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12904 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12905 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12906 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12907 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12908 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12909 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12910 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12911 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12912 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12913 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12914 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12915 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12916 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12917 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12918 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12919 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12920 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12921 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12922 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12923 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12924 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12925 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
12926 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
12927 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
12929 #define IWMMXT_BUILTIN2(code, builtin) \
12930 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12932 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
12933 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
12934 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
12935 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
12936 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
12937 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
12938 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
12939 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
12940 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
12941 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
12942 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
12943 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
12944 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
12945 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
12946 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
12947 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
12948 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
12949 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
12950 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
12951 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
12952 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
12953 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
12954 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
12955 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
12956 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
12957 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
12958 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
12959 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
12960 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
12961 IWMMXT_BUILTIN2 (rordi3, WRORDI)
12962 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
12963 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
12966 static const struct builtin_description bdesc_1arg[] =
12968 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
12969 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
12970 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
12971 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
12972 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
12973 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
12974 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
12975 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
12976 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
12977 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
12978 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
12979 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
12980 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
12981 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
12982 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
12983 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
12984 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
12985 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
12988 /* Set up all the iWMMXt builtins. This is
12989 not called if TARGET_IWMMXT is zero. */
12992 arm_init_iwmmxt_builtins (void)
12994 const struct builtin_description * d;
12996 tree endlink = void_list_node;
12998 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
12999 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
13000 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
13003 = build_function_type (integer_type_node,
13004 tree_cons (NULL_TREE, integer_type_node, endlink));
13005 tree v8qi_ftype_v8qi_v8qi_int
13006 = build_function_type (V8QI_type_node,
13007 tree_cons (NULL_TREE, V8QI_type_node,
13008 tree_cons (NULL_TREE, V8QI_type_node,
13009 tree_cons (NULL_TREE,
13012 tree v4hi_ftype_v4hi_int
13013 = build_function_type (V4HI_type_node,
13014 tree_cons (NULL_TREE, V4HI_type_node,
13015 tree_cons (NULL_TREE, integer_type_node,
13017 tree v2si_ftype_v2si_int
13018 = build_function_type (V2SI_type_node,
13019 tree_cons (NULL_TREE, V2SI_type_node,
13020 tree_cons (NULL_TREE, integer_type_node,
13022 tree v2si_ftype_di_di
13023 = build_function_type (V2SI_type_node,
13024 tree_cons (NULL_TREE, long_long_integer_type_node,
13025 tree_cons (NULL_TREE, long_long_integer_type_node,
13027 tree di_ftype_di_int
13028 = build_function_type (long_long_integer_type_node,
13029 tree_cons (NULL_TREE, long_long_integer_type_node,
13030 tree_cons (NULL_TREE, integer_type_node,
13032 tree di_ftype_di_int_int
13033 = build_function_type (long_long_integer_type_node,
13034 tree_cons (NULL_TREE, long_long_integer_type_node,
13035 tree_cons (NULL_TREE, integer_type_node,
13036 tree_cons (NULL_TREE,
13039 tree int_ftype_v8qi
13040 = build_function_type (integer_type_node,
13041 tree_cons (NULL_TREE, V8QI_type_node,
13043 tree int_ftype_v4hi
13044 = build_function_type (integer_type_node,
13045 tree_cons (NULL_TREE, V4HI_type_node,
13047 tree int_ftype_v2si
13048 = build_function_type (integer_type_node,
13049 tree_cons (NULL_TREE, V2SI_type_node,
13051 tree int_ftype_v8qi_int
13052 = build_function_type (integer_type_node,
13053 tree_cons (NULL_TREE, V8QI_type_node,
13054 tree_cons (NULL_TREE, integer_type_node,
13056 tree int_ftype_v4hi_int
13057 = build_function_type (integer_type_node,
13058 tree_cons (NULL_TREE, V4HI_type_node,
13059 tree_cons (NULL_TREE, integer_type_node,
13061 tree int_ftype_v2si_int
13062 = build_function_type (integer_type_node,
13063 tree_cons (NULL_TREE, V2SI_type_node,
13064 tree_cons (NULL_TREE, integer_type_node,
13066 tree v8qi_ftype_v8qi_int_int
13067 = build_function_type (V8QI_type_node,
13068 tree_cons (NULL_TREE, V8QI_type_node,
13069 tree_cons (NULL_TREE, integer_type_node,
13070 tree_cons (NULL_TREE,
13073 tree v4hi_ftype_v4hi_int_int
13074 = build_function_type (V4HI_type_node,
13075 tree_cons (NULL_TREE, V4HI_type_node,
13076 tree_cons (NULL_TREE, integer_type_node,
13077 tree_cons (NULL_TREE,
13080 tree v2si_ftype_v2si_int_int
13081 = build_function_type (V2SI_type_node,
13082 tree_cons (NULL_TREE, V2SI_type_node,
13083 tree_cons (NULL_TREE, integer_type_node,
13084 tree_cons (NULL_TREE,
13087 /* Miscellaneous. */
13088 tree v8qi_ftype_v4hi_v4hi
13089 = build_function_type (V8QI_type_node,
13090 tree_cons (NULL_TREE, V4HI_type_node,
13091 tree_cons (NULL_TREE, V4HI_type_node,
13093 tree v4hi_ftype_v2si_v2si
13094 = build_function_type (V4HI_type_node,
13095 tree_cons (NULL_TREE, V2SI_type_node,
13096 tree_cons (NULL_TREE, V2SI_type_node,
13098 tree v2si_ftype_v4hi_v4hi
13099 = build_function_type (V2SI_type_node,
13100 tree_cons (NULL_TREE, V4HI_type_node,
13101 tree_cons (NULL_TREE, V4HI_type_node,
13103 tree v2si_ftype_v8qi_v8qi
13104 = build_function_type (V2SI_type_node,
13105 tree_cons (NULL_TREE, V8QI_type_node,
13106 tree_cons (NULL_TREE, V8QI_type_node,
13108 tree v4hi_ftype_v4hi_di
13109 = build_function_type (V4HI_type_node,
13110 tree_cons (NULL_TREE, V4HI_type_node,
13111 tree_cons (NULL_TREE,
13112 long_long_integer_type_node,
13114 tree v2si_ftype_v2si_di
13115 = build_function_type (V2SI_type_node,
13116 tree_cons (NULL_TREE, V2SI_type_node,
13117 tree_cons (NULL_TREE,
13118 long_long_integer_type_node,
13120 tree void_ftype_int_int
13121 = build_function_type (void_type_node,
13122 tree_cons (NULL_TREE, integer_type_node,
13123 tree_cons (NULL_TREE, integer_type_node,
13126 = build_function_type (long_long_unsigned_type_node, endlink);
13128 = build_function_type (long_long_integer_type_node,
13129 tree_cons (NULL_TREE, V8QI_type_node,
13132 = build_function_type (long_long_integer_type_node,
13133 tree_cons (NULL_TREE, V4HI_type_node,
13136 = build_function_type (long_long_integer_type_node,
13137 tree_cons (NULL_TREE, V2SI_type_node,
13139 tree v2si_ftype_v4hi
13140 = build_function_type (V2SI_type_node,
13141 tree_cons (NULL_TREE, V4HI_type_node,
13143 tree v4hi_ftype_v8qi
13144 = build_function_type (V4HI_type_node,
13145 tree_cons (NULL_TREE, V8QI_type_node,
13148 tree di_ftype_di_v4hi_v4hi
13149 = build_function_type (long_long_unsigned_type_node,
13150 tree_cons (NULL_TREE,
13151 long_long_unsigned_type_node,
13152 tree_cons (NULL_TREE, V4HI_type_node,
13153 tree_cons (NULL_TREE,
13157 tree di_ftype_v4hi_v4hi
13158 = build_function_type (long_long_unsigned_type_node,
13159 tree_cons (NULL_TREE, V4HI_type_node,
13160 tree_cons (NULL_TREE, V4HI_type_node,
13163 /* Normal vector binops. */
13164 tree v8qi_ftype_v8qi_v8qi
13165 = build_function_type (V8QI_type_node,
13166 tree_cons (NULL_TREE, V8QI_type_node,
13167 tree_cons (NULL_TREE, V8QI_type_node,
13169 tree v4hi_ftype_v4hi_v4hi
13170 = build_function_type (V4HI_type_node,
13171 tree_cons (NULL_TREE, V4HI_type_node,
13172 tree_cons (NULL_TREE, V4HI_type_node,
13174 tree v2si_ftype_v2si_v2si
13175 = build_function_type (V2SI_type_node,
13176 tree_cons (NULL_TREE, V2SI_type_node,
13177 tree_cons (NULL_TREE, V2SI_type_node,
13179 tree di_ftype_di_di
13180 = build_function_type (long_long_unsigned_type_node,
13181 tree_cons (NULL_TREE, long_long_unsigned_type_node,
13182 tree_cons (NULL_TREE,
13183 long_long_unsigned_type_node,
13186 /* Add all builtins that are more or less simple operations on two
13188 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13190 /* Use one of the operands; the target can have a different mode for
13191 mask-generating compares. */
13192 enum machine_mode mode;
13198 mode = insn_data[d->icode].operand[1].mode;
13203 type = v8qi_ftype_v8qi_v8qi;
13206 type = v4hi_ftype_v4hi_v4hi;
13209 type = v2si_ftype_v2si_v2si;
13212 type = di_ftype_di_di;
13216 gcc_unreachable ();
13219 def_mbuiltin (d->mask, d->name, type, d->code);
13222 /* Add the remaining MMX insns with somewhat more complicated types. */
13223 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
13224 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
13225 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
13227 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
13228 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
13229 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
13230 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
13231 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
13232 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
13234 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
13235 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
13236 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
13237 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
13238 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
13239 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
13241 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
13242 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
13243 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
13244 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
13245 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
13246 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
13248 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
13249 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
13250 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
13251 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
13252 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
13253 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
13255 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
13257 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
13258 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
13259 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
13260 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
13262 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
13263 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
13264 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
13265 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
13266 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
13267 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
13268 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
13269 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
13270 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
13272 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
13273 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
13274 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
13276 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
13277 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
13278 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
13280 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
13281 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
13282 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
13283 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
13284 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
13285 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
13287 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
13288 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
13289 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
13290 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
13291 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
13292 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
13293 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
13294 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
13295 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
13296 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
13297 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
13298 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
13300 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
13301 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
13302 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
13303 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
13305 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
13306 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
13307 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
13308 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
13309 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
13310 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
13311 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
13315 arm_init_tls_builtins (void)
13318 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
13319 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
13321 ftype = build_function_type (ptr_type_node, void_list_node);
13322 add_builtin_function ("__builtin_thread_pointer", ftype,
13323 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
13324 NULL, const_nothrow);
13328 arm_init_builtins (void)
13330 arm_init_tls_builtins ();
13332 if (TARGET_REALLY_IWMMXT)
13333 arm_init_iwmmxt_builtins ();
13336 /* Errors in the source file can cause expand_expr to return const0_rtx
13337 where we expect a vector. To avoid crashing, use one of the vector
13338 clear instructions. */
13341 safe_vector_operand (rtx x, enum machine_mode mode)
13343 if (x != const0_rtx)
13345 x = gen_reg_rtx (mode);
13347 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
13348 : gen_rtx_SUBREG (DImode, x, 0)));
13352 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13355 arm_expand_binop_builtin (enum insn_code icode,
13356 tree exp, rtx target)
13359 tree arg0 = CALL_EXPR_ARG (exp, 0);
13360 tree arg1 = CALL_EXPR_ARG (exp, 1);
13361 rtx op0 = expand_normal (arg0);
13362 rtx op1 = expand_normal (arg1);
13363 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13364 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13365 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
13367 if (VECTOR_MODE_P (mode0))
13368 op0 = safe_vector_operand (op0, mode0);
13369 if (VECTOR_MODE_P (mode1))
13370 op1 = safe_vector_operand (op1, mode1);
13373 || GET_MODE (target) != tmode
13374 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13375 target = gen_reg_rtx (tmode);
13377 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
13379 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13380 op0 = copy_to_mode_reg (mode0, op0);
13381 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13382 op1 = copy_to_mode_reg (mode1, op1);
13384 pat = GEN_FCN (icode) (target, op0, op1);
13391 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13394 arm_expand_unop_builtin (enum insn_code icode,
13395 tree exp, rtx target, int do_load)
13398 tree arg0 = CALL_EXPR_ARG (exp, 0);
13399 rtx op0 = expand_normal (arg0);
13400 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13401 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13404 || GET_MODE (target) != tmode
13405 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13406 target = gen_reg_rtx (tmode);
13408 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
13411 if (VECTOR_MODE_P (mode0))
13412 op0 = safe_vector_operand (op0, mode0);
13414 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13415 op0 = copy_to_mode_reg (mode0, op0);
13418 pat = GEN_FCN (icode) (target, op0);
13425 /* Expand an expression EXP that calls a built-in function,
13426 with result going to TARGET if that's convenient
13427 (and in mode MODE if that's convenient).
13428 SUBTARGET may be used as the target for computing one of EXP's operands.
13429 IGNORE is nonzero if the value is to be ignored. */
13432 arm_expand_builtin (tree exp,
13434 rtx subtarget ATTRIBUTE_UNUSED,
13435 enum machine_mode mode ATTRIBUTE_UNUSED,
13436 int ignore ATTRIBUTE_UNUSED)
13438 const struct builtin_description * d;
13439 enum insn_code icode;
13440 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13448 int fcode = DECL_FUNCTION_CODE (fndecl);
13450 enum machine_mode tmode;
13451 enum machine_mode mode0;
13452 enum machine_mode mode1;
13453 enum machine_mode mode2;
13457 case ARM_BUILTIN_TEXTRMSB:
13458 case ARM_BUILTIN_TEXTRMUB:
13459 case ARM_BUILTIN_TEXTRMSH:
13460 case ARM_BUILTIN_TEXTRMUH:
13461 case ARM_BUILTIN_TEXTRMSW:
13462 case ARM_BUILTIN_TEXTRMUW:
13463 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
13464 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
13465 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
13466 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
13467 : CODE_FOR_iwmmxt_textrmw);
13469 arg0 = CALL_EXPR_ARG (exp, 0);
13470 arg1 = CALL_EXPR_ARG (exp, 1);
13471 op0 = expand_normal (arg0);
13472 op1 = expand_normal (arg1);
13473 tmode = insn_data[icode].operand[0].mode;
13474 mode0 = insn_data[icode].operand[1].mode;
13475 mode1 = insn_data[icode].operand[2].mode;
13477 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13478 op0 = copy_to_mode_reg (mode0, op0);
13479 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13481 /* @@@ better error message */
13482 error ("selector must be an immediate");
13483 return gen_reg_rtx (tmode);
13486 || GET_MODE (target) != tmode
13487 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13488 target = gen_reg_rtx (tmode);
13489 pat = GEN_FCN (icode) (target, op0, op1);
13495 case ARM_BUILTIN_TINSRB:
13496 case ARM_BUILTIN_TINSRH:
13497 case ARM_BUILTIN_TINSRW:
13498 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
13499 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
13500 : CODE_FOR_iwmmxt_tinsrw);
13501 arg0 = CALL_EXPR_ARG (exp, 0);
13502 arg1 = CALL_EXPR_ARG (exp, 1);
13503 arg2 = CALL_EXPR_ARG (exp, 2);
13504 op0 = expand_normal (arg0);
13505 op1 = expand_normal (arg1);
13506 op2 = expand_normal (arg2);
13507 tmode = insn_data[icode].operand[0].mode;
13508 mode0 = insn_data[icode].operand[1].mode;
13509 mode1 = insn_data[icode].operand[2].mode;
13510 mode2 = insn_data[icode].operand[3].mode;
13512 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13513 op0 = copy_to_mode_reg (mode0, op0);
13514 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13515 op1 = copy_to_mode_reg (mode1, op1);
13516 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13518 /* @@@ better error message */
13519 error ("selector must be an immediate");
13523 || GET_MODE (target) != tmode
13524 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13525 target = gen_reg_rtx (tmode);
13526 pat = GEN_FCN (icode) (target, op0, op1, op2);
13532 case ARM_BUILTIN_SETWCX:
13533 arg0 = CALL_EXPR_ARG (exp, 0);
13534 arg1 = CALL_EXPR_ARG (exp, 1);
13535 op0 = force_reg (SImode, expand_normal (arg0));
13536 op1 = expand_normal (arg1);
13537 emit_insn (gen_iwmmxt_tmcr (op1, op0));
13540 case ARM_BUILTIN_GETWCX:
13541 arg0 = CALL_EXPR_ARG (exp, 0);
13542 op0 = expand_normal (arg0);
13543 target = gen_reg_rtx (SImode);
13544 emit_insn (gen_iwmmxt_tmrc (target, op0));
13547 case ARM_BUILTIN_WSHUFH:
13548 icode = CODE_FOR_iwmmxt_wshufh;
13549 arg0 = CALL_EXPR_ARG (exp, 0);
13550 arg1 = CALL_EXPR_ARG (exp, 1);
13551 op0 = expand_normal (arg0);
13552 op1 = expand_normal (arg1);
13553 tmode = insn_data[icode].operand[0].mode;
13554 mode1 = insn_data[icode].operand[1].mode;
13555 mode2 = insn_data[icode].operand[2].mode;
13557 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
13558 op0 = copy_to_mode_reg (mode1, op0);
13559 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
13561 /* @@@ better error message */
13562 error ("mask must be an immediate");
13566 || GET_MODE (target) != tmode
13567 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13568 target = gen_reg_rtx (tmode);
13569 pat = GEN_FCN (icode) (target, op0, op1);
13575 case ARM_BUILTIN_WSADB:
13576 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
13577 case ARM_BUILTIN_WSADH:
13578 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
13579 case ARM_BUILTIN_WSADBZ:
13580 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
13581 case ARM_BUILTIN_WSADHZ:
13582 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
13584 /* Several three-argument builtins. */
13585 case ARM_BUILTIN_WMACS:
13586 case ARM_BUILTIN_WMACU:
13587 case ARM_BUILTIN_WALIGN:
13588 case ARM_BUILTIN_TMIA:
13589 case ARM_BUILTIN_TMIAPH:
13590 case ARM_BUILTIN_TMIATT:
13591 case ARM_BUILTIN_TMIATB:
13592 case ARM_BUILTIN_TMIABT:
13593 case ARM_BUILTIN_TMIABB:
13594 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
13595 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
13596 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
13597 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
13598 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
13599 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
13600 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
13601 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
13602 : CODE_FOR_iwmmxt_walign);
13603 arg0 = CALL_EXPR_ARG (exp, 0);
13604 arg1 = CALL_EXPR_ARG (exp, 1);
13605 arg2 = CALL_EXPR_ARG (exp, 2);
13606 op0 = expand_normal (arg0);
13607 op1 = expand_normal (arg1);
13608 op2 = expand_normal (arg2);
13609 tmode = insn_data[icode].operand[0].mode;
13610 mode0 = insn_data[icode].operand[1].mode;
13611 mode1 = insn_data[icode].operand[2].mode;
13612 mode2 = insn_data[icode].operand[3].mode;
13614 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13615 op0 = copy_to_mode_reg (mode0, op0);
13616 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13617 op1 = copy_to_mode_reg (mode1, op1);
13618 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13619 op2 = copy_to_mode_reg (mode2, op2);
13621 || GET_MODE (target) != tmode
13622 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13623 target = gen_reg_rtx (tmode);
13624 pat = GEN_FCN (icode) (target, op0, op1, op2);
13630 case ARM_BUILTIN_WZERO:
13631 target = gen_reg_rtx (DImode);
13632 emit_insn (gen_iwmmxt_clrdi (target));
13635 case ARM_BUILTIN_THREAD_POINTER:
13636 return arm_load_tp (target);
13642 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13643 if (d->code == (const enum arm_builtins) fcode)
13644 return arm_expand_binop_builtin (d->icode, exp, target);
13646 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13647 if (d->code == (const enum arm_builtins) fcode)
13648 return arm_expand_unop_builtin (d->icode, exp, target, 0);
13650 /* @@@ Should really do something sensible here. */
13654 /* Return the number (counting from 0) of
13655 the least significant set bit in MASK. */
13658 number_of_first_bit_set (unsigned mask)
13663 (mask & (1 << bit)) == 0;
13670 /* Emit code to push or pop registers to or from the stack. F is the
13671 assembly file. MASK is the registers to push or pop. PUSH is
13672 nonzero if we should push, and zero if we should pop. For debugging
13673 output, if pushing, adjust CFA_OFFSET by the amount of space added
13674 to the stack. REAL_REGS should have the same number of bits set as
13675 MASK, and will be used instead (in the same order) to describe which
13676 registers were saved - this is used to mark the save slots when we
13677 push high registers after moving them to low registers. */
13679 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
13680 unsigned long real_regs)
13683 int lo_mask = mask & 0xFF;
13684 int pushed_words = 0;
13688 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
13690 /* Special case. Do not generate a POP PC statement here, do it in
13692 thumb_exit (f, -1);
13696 if (ARM_EABI_UNWIND_TABLES && push)
13698 fprintf (f, "\t.save\t{");
13699 for (regno = 0; regno < 15; regno++)
13701 if (real_regs & (1 << regno))
13703 if (real_regs & ((1 << regno) -1))
13705 asm_fprintf (f, "%r", regno);
13708 fprintf (f, "}\n");
13711 fprintf (f, "\t%s\t{", push ? "push" : "pop");
13713 /* Look at the low registers first. */
13714 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
13718 asm_fprintf (f, "%r", regno);
13720 if ((lo_mask & ~1) != 0)
13727 if (push && (mask & (1 << LR_REGNUM)))
13729 /* Catch pushing the LR. */
13733 asm_fprintf (f, "%r", LR_REGNUM);
13737 else if (!push && (mask & (1 << PC_REGNUM)))
13739 /* Catch popping the PC. */
13740 if (TARGET_INTERWORK || TARGET_BACKTRACE
13741 || current_function_calls_eh_return)
13743 /* The PC is never poped directly, instead
13744 it is popped into r3 and then BX is used. */
13745 fprintf (f, "}\n");
13747 thumb_exit (f, -1);
13756 asm_fprintf (f, "%r", PC_REGNUM);
13760 fprintf (f, "}\n");
13762 if (push && pushed_words && dwarf2out_do_frame ())
13764 char *l = dwarf2out_cfi_label ();
13765 int pushed_mask = real_regs;
13767 *cfa_offset += pushed_words * 4;
13768 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13771 pushed_mask = real_regs;
13772 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13774 if (pushed_mask & 1)
13775 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13780 /* Generate code to return from a thumb function.
13781 If 'reg_containing_return_addr' is -1, then the return address is
13782 actually on the stack, at the stack pointer. */
13784 thumb_exit (FILE *f, int reg_containing_return_addr)
13786 unsigned regs_available_for_popping;
13787 unsigned regs_to_pop;
13789 unsigned available;
13793 int restore_a4 = FALSE;
13795 /* Compute the registers we need to pop. */
13799 if (reg_containing_return_addr == -1)
13801 regs_to_pop |= 1 << LR_REGNUM;
13805 if (TARGET_BACKTRACE)
13807 /* Restore the (ARM) frame pointer and stack pointer. */
13808 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
13812 /* If there is nothing to pop then just emit the BX instruction and
13814 if (pops_needed == 0)
13816 if (current_function_calls_eh_return)
13817 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13819 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13822 /* Otherwise if we are not supporting interworking and we have not created
13823 a backtrace structure and the function was not entered in ARM mode then
13824 just pop the return address straight into the PC. */
13825 else if (!TARGET_INTERWORK
13826 && !TARGET_BACKTRACE
13827 && !is_called_in_ARM_mode (current_function_decl)
13828 && !current_function_calls_eh_return)
13830 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
13834 /* Find out how many of the (return) argument registers we can corrupt. */
13835 regs_available_for_popping = 0;
13837 /* If returning via __builtin_eh_return, the bottom three registers
13838 all contain information needed for the return. */
13839 if (current_function_calls_eh_return)
13843 /* If we can deduce the registers used from the function's
13844 return value. This is more reliable that examining
13845 regs_ever_live[] because that will be set if the register is
13846 ever used in the function, not just if the register is used
13847 to hold a return value. */
13849 if (current_function_return_rtx != 0)
13850 mode = GET_MODE (current_function_return_rtx);
13852 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13854 size = GET_MODE_SIZE (mode);
13858 /* In a void function we can use any argument register.
13859 In a function that returns a structure on the stack
13860 we can use the second and third argument registers. */
13861 if (mode == VOIDmode)
13862 regs_available_for_popping =
13863 (1 << ARG_REGISTER (1))
13864 | (1 << ARG_REGISTER (2))
13865 | (1 << ARG_REGISTER (3));
13867 regs_available_for_popping =
13868 (1 << ARG_REGISTER (2))
13869 | (1 << ARG_REGISTER (3));
13871 else if (size <= 4)
13872 regs_available_for_popping =
13873 (1 << ARG_REGISTER (2))
13874 | (1 << ARG_REGISTER (3));
13875 else if (size <= 8)
13876 regs_available_for_popping =
13877 (1 << ARG_REGISTER (3));
13880 /* Match registers to be popped with registers into which we pop them. */
13881 for (available = regs_available_for_popping,
13882 required = regs_to_pop;
13883 required != 0 && available != 0;
13884 available &= ~(available & - available),
13885 required &= ~(required & - required))
13888 /* If we have any popping registers left over, remove them. */
13890 regs_available_for_popping &= ~available;
13892 /* Otherwise if we need another popping register we can use
13893 the fourth argument register. */
13894 else if (pops_needed)
13896 /* If we have not found any free argument registers and
13897 reg a4 contains the return address, we must move it. */
13898 if (regs_available_for_popping == 0
13899 && reg_containing_return_addr == LAST_ARG_REGNUM)
13901 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13902 reg_containing_return_addr = LR_REGNUM;
13904 else if (size > 12)
13906 /* Register a4 is being used to hold part of the return value,
13907 but we have dire need of a free, low register. */
13910 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
13913 if (reg_containing_return_addr != LAST_ARG_REGNUM)
13915 /* The fourth argument register is available. */
13916 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
13922 /* Pop as many registers as we can. */
13923 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13924 regs_available_for_popping);
13926 /* Process the registers we popped. */
13927 if (reg_containing_return_addr == -1)
13929 /* The return address was popped into the lowest numbered register. */
13930 regs_to_pop &= ~(1 << LR_REGNUM);
13932 reg_containing_return_addr =
13933 number_of_first_bit_set (regs_available_for_popping);
13935 /* Remove this register for the mask of available registers, so that
13936 the return address will not be corrupted by further pops. */
13937 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
13940 /* If we popped other registers then handle them here. */
13941 if (regs_available_for_popping)
13945 /* Work out which register currently contains the frame pointer. */
13946 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
13948 /* Move it into the correct place. */
13949 asm_fprintf (f, "\tmov\t%r, %r\n",
13950 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
13952 /* (Temporarily) remove it from the mask of popped registers. */
13953 regs_available_for_popping &= ~(1 << frame_pointer);
13954 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
13956 if (regs_available_for_popping)
13960 /* We popped the stack pointer as well,
13961 find the register that contains it. */
13962 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
13964 /* Move it into the stack register. */
13965 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
13967 /* At this point we have popped all necessary registers, so
13968 do not worry about restoring regs_available_for_popping
13969 to its correct value:
13971 assert (pops_needed == 0)
13972 assert (regs_available_for_popping == (1 << frame_pointer))
13973 assert (regs_to_pop == (1 << STACK_POINTER)) */
13977 /* Since we have just move the popped value into the frame
13978 pointer, the popping register is available for reuse, and
13979 we know that we still have the stack pointer left to pop. */
13980 regs_available_for_popping |= (1 << frame_pointer);
13984 /* If we still have registers left on the stack, but we no longer have
13985 any registers into which we can pop them, then we must move the return
13986 address into the link register and make available the register that
13988 if (regs_available_for_popping == 0 && pops_needed > 0)
13990 regs_available_for_popping |= 1 << reg_containing_return_addr;
13992 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
13993 reg_containing_return_addr);
13995 reg_containing_return_addr = LR_REGNUM;
13998 /* If we have registers left on the stack then pop some more.
13999 We know that at most we will want to pop FP and SP. */
14000 if (pops_needed > 0)
14005 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14006 regs_available_for_popping);
14008 /* We have popped either FP or SP.
14009 Move whichever one it is into the correct register. */
14010 popped_into = number_of_first_bit_set (regs_available_for_popping);
14011 move_to = number_of_first_bit_set (regs_to_pop);
14013 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
14015 regs_to_pop &= ~(1 << move_to);
14020 /* If we still have not popped everything then we must have only
14021 had one register available to us and we are now popping the SP. */
14022 if (pops_needed > 0)
14026 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14027 regs_available_for_popping);
14029 popped_into = number_of_first_bit_set (regs_available_for_popping);
14031 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
14033 assert (regs_to_pop == (1 << STACK_POINTER))
14034 assert (pops_needed == 1)
14038 /* If necessary restore the a4 register. */
14041 if (reg_containing_return_addr != LR_REGNUM)
14043 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14044 reg_containing_return_addr = LR_REGNUM;
14047 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
14050 if (current_function_calls_eh_return)
14051 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14053 /* Return to caller. */
14054 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14059 thumb1_final_prescan_insn (rtx insn)
14061 if (flag_print_asm_name)
14062 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
14063 INSN_ADDRESSES (INSN_UID (insn)));
14067 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
14069 unsigned HOST_WIDE_INT mask = 0xff;
14072 if (val == 0) /* XXX */
14075 for (i = 0; i < 25; i++)
14076 if ((val & (mask << i)) == val)
14082 /* Returns nonzero if the current function contains,
14083 or might contain a far jump. */
14085 thumb_far_jump_used_p (void)
14089 /* This test is only important for leaf functions. */
14090 /* assert (!leaf_function_p ()); */
14092 /* If we have already decided that far jumps may be used,
14093 do not bother checking again, and always return true even if
14094 it turns out that they are not being used. Once we have made
14095 the decision that far jumps are present (and that hence the link
14096 register will be pushed onto the stack) we cannot go back on it. */
14097 if (cfun->machine->far_jump_used)
14100 /* If this function is not being called from the prologue/epilogue
14101 generation code then it must be being called from the
14102 INITIAL_ELIMINATION_OFFSET macro. */
14103 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
14105 /* In this case we know that we are being asked about the elimination
14106 of the arg pointer register. If that register is not being used,
14107 then there are no arguments on the stack, and we do not have to
14108 worry that a far jump might force the prologue to push the link
14109 register, changing the stack offsets. In this case we can just
14110 return false, since the presence of far jumps in the function will
14111 not affect stack offsets.
14113 If the arg pointer is live (or if it was live, but has now been
14114 eliminated and so set to dead) then we do have to test to see if
14115 the function might contain a far jump. This test can lead to some
14116 false negatives, since before reload is completed, then length of
14117 branch instructions is not known, so gcc defaults to returning their
14118 longest length, which in turn sets the far jump attribute to true.
14120 A false negative will not result in bad code being generated, but it
14121 will result in a needless push and pop of the link register. We
14122 hope that this does not occur too often.
14124 If we need doubleword stack alignment this could affect the other
14125 elimination offsets so we can't risk getting it wrong. */
14126 if (regs_ever_live [ARG_POINTER_REGNUM])
14127 cfun->machine->arg_pointer_live = 1;
14128 else if (!cfun->machine->arg_pointer_live)
14132 /* Check to see if the function contains a branch
14133 insn with the far jump attribute set. */
14134 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14136 if (GET_CODE (insn) == JUMP_INSN
14137 /* Ignore tablejump patterns. */
14138 && GET_CODE (PATTERN (insn)) != ADDR_VEC
14139 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
14140 && get_attr_far_jump (insn) == FAR_JUMP_YES
14143 /* Record the fact that we have decided that
14144 the function does use far jumps. */
14145 cfun->machine->far_jump_used = 1;
14153 /* Return nonzero if FUNC must be entered in ARM mode. */
14155 is_called_in_ARM_mode (tree func)
14157 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
14159 /* Ignore the problem about functions whose address is taken. */
14160 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
14164 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
14170 /* The bits which aren't usefully expanded as rtl. */
14172 thumb_unexpanded_epilogue (void)
14175 unsigned long live_regs_mask = 0;
14176 int high_regs_pushed = 0;
14177 int had_to_push_lr;
14180 if (return_used_this_function)
14183 if (IS_NAKED (arm_current_func_type ()))
14186 live_regs_mask = thumb1_compute_save_reg_mask ();
14187 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14189 /* If we can deduce the registers used from the function's return value.
14190 This is more reliable that examining regs_ever_live[] because that
14191 will be set if the register is ever used in the function, not just if
14192 the register is used to hold a return value. */
14193 size = arm_size_return_regs ();
14195 /* The prolog may have pushed some high registers to use as
14196 work registers. e.g. the testsuite file:
14197 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14198 compiles to produce:
14199 push {r4, r5, r6, r7, lr}
14203 as part of the prolog. We have to undo that pushing here. */
14205 if (high_regs_pushed)
14207 unsigned long mask = live_regs_mask & 0xff;
14210 /* The available low registers depend on the size of the value we are
14218 /* Oh dear! We have no low registers into which we can pop
14221 ("no low registers available for popping high registers");
14223 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
14224 if (live_regs_mask & (1 << next_hi_reg))
14227 while (high_regs_pushed)
14229 /* Find lo register(s) into which the high register(s) can
14231 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14233 if (mask & (1 << regno))
14234 high_regs_pushed--;
14235 if (high_regs_pushed == 0)
14239 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
14241 /* Pop the values into the low register(s). */
14242 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
14244 /* Move the value(s) into the high registers. */
14245 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14247 if (mask & (1 << regno))
14249 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
14252 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
14253 if (live_regs_mask & (1 << next_hi_reg))
14258 live_regs_mask &= ~0x0f00;
14261 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
14262 live_regs_mask &= 0xff;
14264 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
14266 /* Pop the return address into the PC. */
14267 if (had_to_push_lr)
14268 live_regs_mask |= 1 << PC_REGNUM;
14270 /* Either no argument registers were pushed or a backtrace
14271 structure was created which includes an adjusted stack
14272 pointer, so just pop everything. */
14273 if (live_regs_mask)
14274 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14277 /* We have either just popped the return address into the
14278 PC or it is was kept in LR for the entire function. */
14279 if (!had_to_push_lr)
14280 thumb_exit (asm_out_file, LR_REGNUM);
14284 /* Pop everything but the return address. */
14285 if (live_regs_mask)
14286 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14289 if (had_to_push_lr)
14293 /* We have no free low regs, so save one. */
14294 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
14298 /* Get the return address into a temporary register. */
14299 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
14300 1 << LAST_ARG_REGNUM);
14304 /* Move the return address to lr. */
14305 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
14307 /* Restore the low register. */
14308 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
14313 regno = LAST_ARG_REGNUM;
14318 /* Remove the argument registers that were pushed onto the stack. */
14319 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
14320 SP_REGNUM, SP_REGNUM,
14321 current_function_pretend_args_size);
14323 thumb_exit (asm_out_file, regno);
14329 /* Functions to save and restore machine-specific function data. */
14330 static struct machine_function *
14331 arm_init_machine_status (void)
14333 struct machine_function *machine;
14334 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
14336 #if ARM_FT_UNKNOWN != 0
14337 machine->func_type = ARM_FT_UNKNOWN;
14342 /* Return an RTX indicating where the return address to the
14343 calling function can be found. */
14345 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
14350 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
14353 /* Do anything needed before RTL is emitted for each function. */
14355 arm_init_expanders (void)
14357 /* Arrange to initialize and mark the machine per-function status. */
14358 init_machine_status = arm_init_machine_status;
14360 /* This is to stop the combine pass optimizing away the alignment
14361 adjustment of va_arg. */
14362 /* ??? It is claimed that this should not be necessary. */
14364 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
14368 /* Like arm_compute_initial_elimination offset. Simpler because there
14369 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14370 to point at the base of the local variables after static stack
14371 space for a function has been allocated. */
14374 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
14376 arm_stack_offsets *offsets;
14378 offsets = arm_get_frame_offsets ();
14382 case ARG_POINTER_REGNUM:
14385 case STACK_POINTER_REGNUM:
14386 return offsets->outgoing_args - offsets->saved_args;
14388 case FRAME_POINTER_REGNUM:
14389 return offsets->soft_frame - offsets->saved_args;
14391 case ARM_HARD_FRAME_POINTER_REGNUM:
14392 return offsets->saved_regs - offsets->saved_args;
14394 case THUMB_HARD_FRAME_POINTER_REGNUM:
14395 return offsets->locals_base - offsets->saved_args;
14398 gcc_unreachable ();
14402 case FRAME_POINTER_REGNUM:
14405 case STACK_POINTER_REGNUM:
14406 return offsets->outgoing_args - offsets->soft_frame;
14408 case ARM_HARD_FRAME_POINTER_REGNUM:
14409 return offsets->saved_regs - offsets->soft_frame;
14411 case THUMB_HARD_FRAME_POINTER_REGNUM:
14412 return offsets->locals_base - offsets->soft_frame;
14415 gcc_unreachable ();
14420 gcc_unreachable ();
14424 /* Generate the rest of a function's prologue. */
14426 thumb1_expand_prologue (void)
14430 HOST_WIDE_INT amount;
14431 arm_stack_offsets *offsets;
14432 unsigned long func_type;
14434 unsigned long live_regs_mask;
14436 func_type = arm_current_func_type ();
14438 /* Naked functions don't have prologues. */
14439 if (IS_NAKED (func_type))
14442 if (IS_INTERRUPT (func_type))
14444 error ("interrupt Service Routines cannot be coded in Thumb mode");
14448 live_regs_mask = thumb1_compute_save_reg_mask ();
14449 /* Load the pic register before setting the frame pointer,
14450 so we can use r7 as a temporary work register. */
14451 if (flag_pic && arm_pic_register != INVALID_REGNUM)
14452 arm_load_pic_register (live_regs_mask);
14454 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
14455 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
14456 stack_pointer_rtx);
14458 offsets = arm_get_frame_offsets ();
14459 amount = offsets->outgoing_args - offsets->saved_regs;
14464 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14465 GEN_INT (- amount)));
14466 RTX_FRAME_RELATED_P (insn) = 1;
14472 /* The stack decrement is too big for an immediate value in a single
14473 insn. In theory we could issue multiple subtracts, but after
14474 three of them it becomes more space efficient to place the full
14475 value in the constant pool and load into a register. (Also the
14476 ARM debugger really likes to see only one stack decrement per
14477 function). So instead we look for a scratch register into which
14478 we can load the decrement, and then we subtract this from the
14479 stack pointer. Unfortunately on the thumb the only available
14480 scratch registers are the argument registers, and we cannot use
14481 these as they may hold arguments to the function. Instead we
14482 attempt to locate a call preserved register which is used by this
14483 function. If we can find one, then we know that it will have
14484 been pushed at the start of the prologue and so we can corrupt
14486 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
14487 if (live_regs_mask & (1 << regno)
14488 && !(frame_pointer_needed
14489 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
14492 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
14494 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
14496 /* Choose an arbitrary, non-argument low register. */
14497 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
14499 /* Save it by copying it into a high, scratch register. */
14500 emit_insn (gen_movsi (spare, reg));
14501 /* Add a USE to stop propagate_one_insn() from barfing. */
14502 emit_insn (gen_prologue_use (spare));
14504 /* Decrement the stack. */
14505 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14506 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14507 stack_pointer_rtx, reg));
14508 RTX_FRAME_RELATED_P (insn) = 1;
14509 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14510 plus_constant (stack_pointer_rtx,
14512 RTX_FRAME_RELATED_P (dwarf) = 1;
14514 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14517 /* Restore the low register's original value. */
14518 emit_insn (gen_movsi (reg, spare));
14520 /* Emit a USE of the restored scratch register, so that flow
14521 analysis will not consider the restore redundant. The
14522 register won't be used again in this function and isn't
14523 restored by the epilogue. */
14524 emit_insn (gen_prologue_use (reg));
14528 reg = gen_rtx_REG (SImode, regno);
14530 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14532 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14533 stack_pointer_rtx, reg));
14534 RTX_FRAME_RELATED_P (insn) = 1;
14535 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14536 plus_constant (stack_pointer_rtx,
14538 RTX_FRAME_RELATED_P (dwarf) = 1;
14540 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14546 if (frame_pointer_needed)
14547 thumb_set_frame_pointer (offsets);
14549 /* If we are profiling, make sure no instructions are scheduled before
14550 the call to mcount. Similarly if the user has requested no
14551 scheduling in the prolog. Similarly if we want non-call exceptions
14552 using the EABI unwinder, to prevent faulting instructions from being
14553 swapped with a stack adjustment. */
14554 if (current_function_profile || !TARGET_SCHED_PROLOG
14555 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
14556 emit_insn (gen_blockage ());
14558 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
14559 if (live_regs_mask & 0xff)
14560 cfun->machine->lr_save_eliminated = 0;
14562 /* If the link register is being kept alive, with the return address in it,
14563 then make sure that it does not get reused by the ce2 pass. */
14564 if (cfun->machine->lr_save_eliminated)
14565 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
14570 thumb1_expand_epilogue (void)
14572 HOST_WIDE_INT amount;
14573 arm_stack_offsets *offsets;
14576 /* Naked functions don't have prologues. */
14577 if (IS_NAKED (arm_current_func_type ()))
14580 offsets = arm_get_frame_offsets ();
14581 amount = offsets->outgoing_args - offsets->saved_regs;
14583 if (frame_pointer_needed)
14585 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
14586 amount = offsets->locals_base - offsets->saved_regs;
14592 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14593 GEN_INT (amount)));
14596 /* r3 is always free in the epilogue. */
14597 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
14599 emit_insn (gen_movsi (reg, GEN_INT (amount)));
14600 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
14604 /* Emit a USE (stack_pointer_rtx), so that
14605 the stack adjustment will not be deleted. */
14606 emit_insn (gen_prologue_use (stack_pointer_rtx));
14608 if (current_function_profile || !TARGET_SCHED_PROLOG)
14609 emit_insn (gen_blockage ());
14611 /* Emit a clobber for each insn that will be restored in the epilogue,
14612 so that flow2 will get register lifetimes correct. */
14613 for (regno = 0; regno < 13; regno++)
14614 if (regs_ever_live[regno] && !call_used_regs[regno])
14615 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
14617 if (! regs_ever_live[LR_REGNUM])
14618 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
14622 thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14624 unsigned long live_regs_mask = 0;
14625 unsigned long l_mask;
14626 unsigned high_regs_pushed = 0;
14627 int cfa_offset = 0;
14630 if (IS_NAKED (arm_current_func_type ()))
14633 if (is_called_in_ARM_mode (current_function_decl))
14637 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
14638 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
14640 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14642 /* Generate code sequence to switch us into Thumb mode. */
14643 /* The .code 32 directive has already been emitted by
14644 ASM_DECLARE_FUNCTION_NAME. */
14645 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
14646 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
14648 /* Generate a label, so that the debugger will notice the
14649 change in instruction sets. This label is also used by
14650 the assembler to bypass the ARM code when this function
14651 is called from a Thumb encoded function elsewhere in the
14652 same file. Hence the definition of STUB_NAME here must
14653 agree with the definition in gas/config/tc-arm.c. */
14655 #define STUB_NAME ".real_start_of"
14657 fprintf (f, "\t.code\t16\n");
14659 if (arm_dllexport_name_p (name))
14660 name = arm_strip_name_encoding (name);
14662 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
14663 fprintf (f, "\t.thumb_func\n");
14664 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
14667 if (current_function_pretend_args_size)
14669 /* Output unwind directive for the stack adjustment. */
14670 if (ARM_EABI_UNWIND_TABLES)
14671 fprintf (f, "\t.pad #%d\n",
14672 current_function_pretend_args_size);
14674 if (cfun->machine->uses_anonymous_args)
14678 fprintf (f, "\tpush\t{");
14680 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
14682 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
14683 regno <= LAST_ARG_REGNUM;
14685 asm_fprintf (f, "%r%s", regno,
14686 regno == LAST_ARG_REGNUM ? "" : ", ");
14688 fprintf (f, "}\n");
14691 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
14692 SP_REGNUM, SP_REGNUM,
14693 current_function_pretend_args_size);
14695 /* We don't need to record the stores for unwinding (would it
14696 help the debugger any if we did?), but record the change in
14697 the stack pointer. */
14698 if (dwarf2out_do_frame ())
14700 char *l = dwarf2out_cfi_label ();
14702 cfa_offset = cfa_offset + current_function_pretend_args_size;
14703 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14707 /* Get the registers we are going to push. */
14708 live_regs_mask = thumb1_compute_save_reg_mask ();
14709 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14710 l_mask = live_regs_mask & 0x40ff;
14711 /* Then count how many other high registers will need to be pushed. */
14712 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14714 if (TARGET_BACKTRACE)
14717 unsigned work_register;
14719 /* We have been asked to create a stack backtrace structure.
14720 The code looks like this:
14724 0 sub SP, #16 Reserve space for 4 registers.
14725 2 push {R7} Push low registers.
14726 4 add R7, SP, #20 Get the stack pointer before the push.
14727 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14728 8 mov R7, PC Get hold of the start of this code plus 12.
14729 10 str R7, [SP, #16] Store it.
14730 12 mov R7, FP Get hold of the current frame pointer.
14731 14 str R7, [SP, #4] Store it.
14732 16 mov R7, LR Get hold of the current return address.
14733 18 str R7, [SP, #12] Store it.
14734 20 add R7, SP, #16 Point at the start of the backtrace structure.
14735 22 mov FP, R7 Put this value into the frame pointer. */
14737 work_register = thumb_find_work_register (live_regs_mask);
14739 if (ARM_EABI_UNWIND_TABLES)
14740 asm_fprintf (f, "\t.pad #16\n");
14743 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14744 SP_REGNUM, SP_REGNUM);
14746 if (dwarf2out_do_frame ())
14748 char *l = dwarf2out_cfi_label ();
14750 cfa_offset = cfa_offset + 16;
14751 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14756 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14757 offset = bit_count (l_mask) * UNITS_PER_WORD;
14762 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14763 offset + 16 + current_function_pretend_args_size);
14765 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14768 /* Make sure that the instruction fetching the PC is in the right place
14769 to calculate "start of backtrace creation code + 12". */
14772 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14773 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14775 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14776 ARM_HARD_FRAME_POINTER_REGNUM);
14777 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14782 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14783 ARM_HARD_FRAME_POINTER_REGNUM);
14784 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14786 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14787 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14791 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
14792 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14794 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14796 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14797 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
14799 /* Optimization: If we are not pushing any low registers but we are going
14800 to push some high registers then delay our first push. This will just
14801 be a push of LR and we can combine it with the push of the first high
14803 else if ((l_mask & 0xff) != 0
14804 || (high_regs_pushed == 0 && l_mask))
14805 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14807 if (high_regs_pushed)
14809 unsigned pushable_regs;
14810 unsigned next_hi_reg;
14812 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
14813 if (live_regs_mask & (1 << next_hi_reg))
14816 pushable_regs = l_mask & 0xff;
14818 if (pushable_regs == 0)
14819 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
14821 while (high_regs_pushed > 0)
14823 unsigned long real_regs_mask = 0;
14825 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
14827 if (pushable_regs & (1 << regno))
14829 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
14831 high_regs_pushed --;
14832 real_regs_mask |= (1 << next_hi_reg);
14834 if (high_regs_pushed)
14836 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
14838 if (live_regs_mask & (1 << next_hi_reg))
14843 pushable_regs &= ~((1 << regno) - 1);
14849 /* If we had to find a work register and we have not yet
14850 saved the LR then add it to the list of regs to push. */
14851 if (l_mask == (1 << LR_REGNUM))
14853 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
14855 real_regs_mask | (1 << LR_REGNUM));
14859 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
14864 /* Handle the case of a double word load into a low register from
14865 a computed memory address. The computed address may involve a
14866 register which is overwritten by the load. */
14868 thumb_load_double_from_address (rtx *operands)
14876 gcc_assert (GET_CODE (operands[0]) == REG);
14877 gcc_assert (GET_CODE (operands[1]) == MEM);
14879 /* Get the memory address. */
14880 addr = XEXP (operands[1], 0);
14882 /* Work out how the memory address is computed. */
14883 switch (GET_CODE (addr))
14886 operands[2] = adjust_address (operands[1], SImode, 4);
14888 if (REGNO (operands[0]) == REGNO (addr))
14890 output_asm_insn ("ldr\t%H0, %2", operands);
14891 output_asm_insn ("ldr\t%0, %1", operands);
14895 output_asm_insn ("ldr\t%0, %1", operands);
14896 output_asm_insn ("ldr\t%H0, %2", operands);
14901 /* Compute <address> + 4 for the high order load. */
14902 operands[2] = adjust_address (operands[1], SImode, 4);
14904 output_asm_insn ("ldr\t%0, %1", operands);
14905 output_asm_insn ("ldr\t%H0, %2", operands);
14909 arg1 = XEXP (addr, 0);
14910 arg2 = XEXP (addr, 1);
14912 if (CONSTANT_P (arg1))
14913 base = arg2, offset = arg1;
14915 base = arg1, offset = arg2;
14917 gcc_assert (GET_CODE (base) == REG);
14919 /* Catch the case of <address> = <reg> + <reg> */
14920 if (GET_CODE (offset) == REG)
14922 int reg_offset = REGNO (offset);
14923 int reg_base = REGNO (base);
14924 int reg_dest = REGNO (operands[0]);
14926 /* Add the base and offset registers together into the
14927 higher destination register. */
14928 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
14929 reg_dest + 1, reg_base, reg_offset);
14931 /* Load the lower destination register from the address in
14932 the higher destination register. */
14933 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
14934 reg_dest, reg_dest + 1);
14936 /* Load the higher destination register from its own address
14938 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
14939 reg_dest + 1, reg_dest + 1);
14943 /* Compute <address> + 4 for the high order load. */
14944 operands[2] = adjust_address (operands[1], SImode, 4);
14946 /* If the computed address is held in the low order register
14947 then load the high order register first, otherwise always
14948 load the low order register first. */
14949 if (REGNO (operands[0]) == REGNO (base))
14951 output_asm_insn ("ldr\t%H0, %2", operands);
14952 output_asm_insn ("ldr\t%0, %1", operands);
14956 output_asm_insn ("ldr\t%0, %1", operands);
14957 output_asm_insn ("ldr\t%H0, %2", operands);
14963 /* With no registers to worry about we can just load the value
14965 operands[2] = adjust_address (operands[1], SImode, 4);
14967 output_asm_insn ("ldr\t%H0, %2", operands);
14968 output_asm_insn ("ldr\t%0, %1", operands);
14972 gcc_unreachable ();
14979 thumb_output_move_mem_multiple (int n, rtx *operands)
14986 if (REGNO (operands[4]) > REGNO (operands[5]))
14989 operands[4] = operands[5];
14992 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
14993 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
14997 if (REGNO (operands[4]) > REGNO (operands[5]))
15000 operands[4] = operands[5];
15003 if (REGNO (operands[5]) > REGNO (operands[6]))
15006 operands[5] = operands[6];
15009 if (REGNO (operands[4]) > REGNO (operands[5]))
15012 operands[4] = operands[5];
15016 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
15017 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
15021 gcc_unreachable ();
15027 /* Output a call-via instruction for thumb state. */
15029 thumb_call_via_reg (rtx reg)
15031 int regno = REGNO (reg);
15034 gcc_assert (regno < LR_REGNUM);
15036 /* If we are in the normal text section we can use a single instance
15037 per compilation unit. If we are doing function sections, then we need
15038 an entry per section, since we can't rely on reachability. */
15039 if (in_section == text_section)
15041 thumb_call_reg_needed = 1;
15043 if (thumb_call_via_label[regno] == NULL)
15044 thumb_call_via_label[regno] = gen_label_rtx ();
15045 labelp = thumb_call_via_label + regno;
15049 if (cfun->machine->call_via[regno] == NULL)
15050 cfun->machine->call_via[regno] = gen_label_rtx ();
15051 labelp = cfun->machine->call_via + regno;
15054 output_asm_insn ("bl\t%a0", labelp);
15058 /* Routines for generating rtl. */
15060 thumb_expand_movmemqi (rtx *operands)
15062 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
15063 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
15064 HOST_WIDE_INT len = INTVAL (operands[2]);
15065 HOST_WIDE_INT offset = 0;
15069 emit_insn (gen_movmem12b (out, in, out, in));
15075 emit_insn (gen_movmem8b (out, in, out, in));
15081 rtx reg = gen_reg_rtx (SImode);
15082 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
15083 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
15090 rtx reg = gen_reg_rtx (HImode);
15091 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
15092 plus_constant (in, offset))));
15093 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
15101 rtx reg = gen_reg_rtx (QImode);
15102 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
15103 plus_constant (in, offset))));
15104 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
15110 thumb_reload_out_hi (rtx *operands)
15112 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
15115 /* Handle reading a half-word from memory during reload. */
15117 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
15119 gcc_unreachable ();
15122 /* Return the length of a function name prefix
15123 that starts with the character 'c'. */
15125 arm_get_strip_length (int c)
15129 ARM_NAME_ENCODING_LENGTHS
15134 /* Return a pointer to a function's name with any
15135 and all prefix encodings stripped from it. */
15137 arm_strip_name_encoding (const char *name)
15141 while ((skip = arm_get_strip_length (* name)))
15147 /* If there is a '*' anywhere in the name's prefix, then
15148 emit the stripped name verbatim, otherwise prepend an
15149 underscore if leading underscores are being used. */
15151 arm_asm_output_labelref (FILE *stream, const char *name)
15156 while ((skip = arm_get_strip_length (* name)))
15158 verbatim |= (*name == '*');
15163 fputs (name, stream);
15165 asm_fprintf (stream, "%U%s", name);
15169 arm_file_start (void)
15173 if (TARGET_UNIFIED_ASM)
15174 asm_fprintf (asm_out_file, "\t.syntax unified\n");
15178 const char *fpu_name;
15179 if (arm_select[0].string)
15180 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
15181 else if (arm_select[1].string)
15182 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
15184 asm_fprintf (asm_out_file, "\t.cpu %s\n",
15185 all_cores[arm_default_cpu].name);
15187 if (TARGET_SOFT_FLOAT)
15190 fpu_name = "softvfp";
15192 fpu_name = "softfpa";
15196 switch (arm_fpu_arch)
15201 case FPUTYPE_FPA_EMU2:
15204 case FPUTYPE_FPA_EMU3:
15207 case FPUTYPE_MAVERICK:
15208 fpu_name = "maverick";
15211 if (TARGET_HARD_FLOAT)
15212 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
15213 if (TARGET_HARD_FLOAT_ABI)
15214 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
15221 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
15223 /* Some of these attributes only apply when the corresponding features
15224 are used. However we don't have any easy way of figuring this out.
15225 Conservatively record the setting that would have been used. */
15227 /* Tag_ABI_PCS_wchar_t. */
15228 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
15229 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
15231 /* Tag_ABI_FP_rounding. */
15232 if (flag_rounding_math)
15233 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
15234 if (!flag_unsafe_math_optimizations)
15236 /* Tag_ABI_FP_denomal. */
15237 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
15238 /* Tag_ABI_FP_exceptions. */
15239 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
15241 /* Tag_ABI_FP_user_exceptions. */
15242 if (flag_signaling_nans)
15243 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
15244 /* Tag_ABI_FP_number_model. */
15245 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
15246 flag_finite_math_only ? 1 : 3);
15248 /* Tag_ABI_align8_needed. */
15249 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
15250 /* Tag_ABI_align8_preserved. */
15251 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
15252 /* Tag_ABI_enum_size. */
15253 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
15254 flag_short_enums ? 1 : 2);
15256 /* Tag_ABI_optimization_goals. */
15259 else if (optimize >= 2)
15265 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
15267 default_file_start();
15271 arm_file_end (void)
15275 if (NEED_INDICATE_EXEC_STACK)
15276 /* Add .note.GNU-stack. */
15277 file_end_indicate_exec_stack ();
15279 if (! thumb_call_reg_needed)
15282 switch_to_section (text_section);
15283 asm_fprintf (asm_out_file, "\t.code 16\n");
15284 ASM_OUTPUT_ALIGN (asm_out_file, 1);
15286 for (regno = 0; regno < LR_REGNUM; regno++)
15288 rtx label = thumb_call_via_label[regno];
15292 targetm.asm_out.internal_label (asm_out_file, "L",
15293 CODE_LABEL_NUMBER (label));
15294 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
15301 #ifdef AOF_ASSEMBLER
15302 /* Special functions only needed when producing AOF syntax assembler. */
15306 struct pic_chain * next;
15307 const char * symname;
15310 static struct pic_chain * aof_pic_chain = NULL;
15313 aof_pic_entry (rtx x)
15315 struct pic_chain ** chainp;
15318 if (aof_pic_label == NULL_RTX)
15320 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
15323 for (offset = 0, chainp = &aof_pic_chain; *chainp;
15324 offset += 4, chainp = &(*chainp)->next)
15325 if ((*chainp)->symname == XSTR (x, 0))
15326 return plus_constant (aof_pic_label, offset);
15328 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
15329 (*chainp)->next = NULL;
15330 (*chainp)->symname = XSTR (x, 0);
15331 return plus_constant (aof_pic_label, offset);
15335 aof_dump_pic_table (FILE *f)
15337 struct pic_chain * chain;
15339 if (aof_pic_chain == NULL)
15342 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
15343 PIC_OFFSET_TABLE_REGNUM,
15344 PIC_OFFSET_TABLE_REGNUM);
15345 fputs ("|x$adcons|\n", f);
15347 for (chain = aof_pic_chain; chain; chain = chain->next)
15349 fputs ("\tDCD\t", f);
15350 assemble_name (f, chain->symname);
15355 int arm_text_section_count = 1;
15357 /* A get_unnamed_section callback for switching to the text section. */
15360 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15362 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
15363 arm_text_section_count++);
15365 fprintf (asm_out_file, ", PIC, REENTRANT");
15366 fprintf (asm_out_file, "\n");
15369 static int arm_data_section_count = 1;
15371 /* A get_unnamed_section callback for switching to the data section. */
15374 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15376 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
15377 arm_data_section_count++);
15380 /* Implement TARGET_ASM_INIT_SECTIONS.
15382 AOF Assembler syntax is a nightmare when it comes to areas, since once
15383 we change from one area to another, we can't go back again. Instead,
15384 we must create a new area with the same attributes and add the new output
15385 to that. Unfortunately, there is nothing we can do here to guarantee that
15386 two areas with the same attributes will be linked adjacently in the
15387 resulting executable, so we have to be careful not to do pc-relative
15388 addressing across such boundaries. */
15391 aof_asm_init_sections (void)
15393 text_section = get_unnamed_section (SECTION_CODE,
15394 aof_output_text_section_asm_op, NULL);
15395 data_section = get_unnamed_section (SECTION_WRITE,
15396 aof_output_data_section_asm_op, NULL);
15397 readonly_data_section = text_section;
15401 zero_init_section (void)
15403 static int zero_init_count = 1;
15405 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
15409 /* The AOF assembler is religiously strict about declarations of
15410 imported and exported symbols, so that it is impossible to declare
15411 a function as imported near the beginning of the file, and then to
15412 export it later on. It is, however, possible to delay the decision
15413 until all the functions in the file have been compiled. To get
15414 around this, we maintain a list of the imports and exports, and
15415 delete from it any that are subsequently defined. At the end of
15416 compilation we spit the remainder of the list out before the END
15421 struct import * next;
15425 static struct import * imports_list = NULL;
15428 aof_add_import (const char *name)
15430 struct import * new;
15432 for (new = imports_list; new; new = new->next)
15433 if (new->name == name)
15436 new = (struct import *) xmalloc (sizeof (struct import));
15437 new->next = imports_list;
15438 imports_list = new;
15443 aof_delete_import (const char *name)
15445 struct import ** old;
15447 for (old = &imports_list; *old; old = & (*old)->next)
15449 if ((*old)->name == name)
15451 *old = (*old)->next;
15457 int arm_main_function = 0;
15460 aof_dump_imports (FILE *f)
15462 /* The AOF assembler needs this to cause the startup code to be extracted
15463 from the library. Brining in __main causes the whole thing to work
15465 if (arm_main_function)
15467 switch_to_section (text_section);
15468 fputs ("\tIMPORT __main\n", f);
15469 fputs ("\tDCD __main\n", f);
15472 /* Now dump the remaining imports. */
15473 while (imports_list)
15475 fprintf (f, "\tIMPORT\t");
15476 assemble_name (f, imports_list->name);
15478 imports_list = imports_list->next;
15483 aof_globalize_label (FILE *stream, const char *name)
15485 default_globalize_label (stream, name);
15486 if (! strcmp (name, "main"))
15487 arm_main_function = 1;
15491 aof_file_start (void)
15493 fputs ("__r0\tRN\t0\n", asm_out_file);
15494 fputs ("__a1\tRN\t0\n", asm_out_file);
15495 fputs ("__a2\tRN\t1\n", asm_out_file);
15496 fputs ("__a3\tRN\t2\n", asm_out_file);
15497 fputs ("__a4\tRN\t3\n", asm_out_file);
15498 fputs ("__v1\tRN\t4\n", asm_out_file);
15499 fputs ("__v2\tRN\t5\n", asm_out_file);
15500 fputs ("__v3\tRN\t6\n", asm_out_file);
15501 fputs ("__v4\tRN\t7\n", asm_out_file);
15502 fputs ("__v5\tRN\t8\n", asm_out_file);
15503 fputs ("__v6\tRN\t9\n", asm_out_file);
15504 fputs ("__sl\tRN\t10\n", asm_out_file);
15505 fputs ("__fp\tRN\t11\n", asm_out_file);
15506 fputs ("__ip\tRN\t12\n", asm_out_file);
15507 fputs ("__sp\tRN\t13\n", asm_out_file);
15508 fputs ("__lr\tRN\t14\n", asm_out_file);
15509 fputs ("__pc\tRN\t15\n", asm_out_file);
15510 fputs ("__f0\tFN\t0\n", asm_out_file);
15511 fputs ("__f1\tFN\t1\n", asm_out_file);
15512 fputs ("__f2\tFN\t2\n", asm_out_file);
15513 fputs ("__f3\tFN\t3\n", asm_out_file);
15514 fputs ("__f4\tFN\t4\n", asm_out_file);
15515 fputs ("__f5\tFN\t5\n", asm_out_file);
15516 fputs ("__f6\tFN\t6\n", asm_out_file);
15517 fputs ("__f7\tFN\t7\n", asm_out_file);
15518 switch_to_section (text_section);
15522 aof_file_end (void)
15525 aof_dump_pic_table (asm_out_file);
15527 aof_dump_imports (asm_out_file);
15528 fputs ("\tEND\n", asm_out_file);
15530 #endif /* AOF_ASSEMBLER */
15533 /* Symbols in the text segment can be accessed without indirecting via the
15534 constant pool; it may take an extra binary operation, but this is still
15535 faster than indirecting via memory. Don't do this when not optimizing,
15536 since we won't be calculating al of the offsets necessary to do this
15540 arm_encode_section_info (tree decl, rtx rtl, int first)
15542 /* This doesn't work with AOF syntax, since the string table may be in
15543 a different AREA. */
15544 #ifndef AOF_ASSEMBLER
15545 if (optimize > 0 && TREE_CONSTANT (decl))
15546 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
15549 default_encode_section_info (decl, rtl, first);
15551 #endif /* !ARM_PE */
15554 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
15556 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
15557 && !strcmp (prefix, "L"))
15559 arm_ccfsm_state = 0;
15560 arm_target_insn = NULL;
15562 default_internal_label (stream, prefix, labelno);
15565 /* Output code to add DELTA to the first argument, and then jump
15566 to FUNCTION. Used for C++ multiple inheritance. */
15568 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
15569 HOST_WIDE_INT delta,
15570 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
15573 static int thunk_label = 0;
15576 int mi_delta = delta;
15577 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
15579 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
15582 mi_delta = - mi_delta;
15583 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15586 int labelno = thunk_label++;
15587 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
15588 fputs ("\tldr\tr12, ", file);
15589 assemble_name (file, label);
15590 fputc ('\n', file);
15593 /* If we are generating PIC, the ldr instruction below loads
15594 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15595 the address of the add + 8, so we have:
15597 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15600 Note that we have "+ 1" because some versions of GNU ld
15601 don't set the low bit of the result for R_ARM_REL32
15602 relocations against thumb function symbols. */
15603 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
15604 assemble_name (file, labelpc);
15605 fputs (":\n", file);
15606 fputs ("\tadd\tr12, pc, r12\n", file);
15609 /* TODO: Use movw/movt for large constants when available. */
15610 while (mi_delta != 0)
15612 if ((mi_delta & (3 << shift)) == 0)
15616 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
15617 mi_op, this_regno, this_regno,
15618 mi_delta & (0xff << shift));
15619 mi_delta &= ~(0xff << shift);
15625 fprintf (file, "\tbx\tr12\n");
15626 ASM_OUTPUT_ALIGN (file, 2);
15627 assemble_name (file, label);
15628 fputs (":\n", file);
15631 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15632 rtx tem = XEXP (DECL_RTL (function), 0);
15633 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
15634 tem = gen_rtx_MINUS (GET_MODE (tem),
15636 gen_rtx_SYMBOL_REF (Pmode,
15637 ggc_strdup (labelpc)));
15638 assemble_integer (tem, 4, BITS_PER_WORD, 1);
15641 /* Output ".word .LTHUNKn". */
15642 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
15646 fputs ("\tb\t", file);
15647 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
15648 if (NEED_PLT_RELOC)
15649 fputs ("(PLT)", file);
15650 fputc ('\n', file);
15655 arm_emit_vector_const (FILE *file, rtx x)
15658 const char * pattern;
15660 gcc_assert (GET_CODE (x) == CONST_VECTOR);
15662 switch (GET_MODE (x))
15664 case V2SImode: pattern = "%08x"; break;
15665 case V4HImode: pattern = "%04x"; break;
15666 case V8QImode: pattern = "%02x"; break;
15667 default: gcc_unreachable ();
15670 fprintf (file, "0x");
15671 for (i = CONST_VECTOR_NUNITS (x); i--;)
15675 element = CONST_VECTOR_ELT (x, i);
15676 fprintf (file, pattern, INTVAL (element));
15683 arm_output_load_gr (rtx *operands)
15690 if (GET_CODE (operands [1]) != MEM
15691 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
15692 || GET_CODE (reg = XEXP (sum, 0)) != REG
15693 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
15694 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
15695 return "wldrw%?\t%0, %1";
15697 /* Fix up an out-of-range load of a GR register. */
15698 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
15699 wcgr = operands[0];
15701 output_asm_insn ("ldr%?\t%0, %1", operands);
15703 operands[0] = wcgr;
15705 output_asm_insn ("tmcr%?\t%0, %1", operands);
15706 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
15711 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
15713 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
15714 named arg and all anonymous args onto the stack.
15715 XXX I know the prologue shouldn't be pushing registers, but it is faster
15719 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
15720 enum machine_mode mode ATTRIBUTE_UNUSED,
15721 tree type ATTRIBUTE_UNUSED,
15723 int second_time ATTRIBUTE_UNUSED)
15725 cfun->machine->uses_anonymous_args = 1;
15726 if (cum->nregs < NUM_ARG_REGS)
15727 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
15730 /* Return nonzero if the CONSUMER instruction (a store) does not need
15731 PRODUCER's value to calculate the address. */
15734 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
15736 rtx value = PATTERN (producer);
15737 rtx addr = PATTERN (consumer);
15739 if (GET_CODE (value) == COND_EXEC)
15740 value = COND_EXEC_CODE (value);
15741 if (GET_CODE (value) == PARALLEL)
15742 value = XVECEXP (value, 0, 0);
15743 value = XEXP (value, 0);
15744 if (GET_CODE (addr) == COND_EXEC)
15745 addr = COND_EXEC_CODE (addr);
15746 if (GET_CODE (addr) == PARALLEL)
15747 addr = XVECEXP (addr, 0, 0);
15748 addr = XEXP (addr, 0);
15750 return !reg_overlap_mentioned_p (value, addr);
15753 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15754 have an early register shift value or amount dependency on the
15755 result of PRODUCER. */
15758 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
15760 rtx value = PATTERN (producer);
15761 rtx op = PATTERN (consumer);
15764 if (GET_CODE (value) == COND_EXEC)
15765 value = COND_EXEC_CODE (value);
15766 if (GET_CODE (value) == PARALLEL)
15767 value = XVECEXP (value, 0, 0);
15768 value = XEXP (value, 0);
15769 if (GET_CODE (op) == COND_EXEC)
15770 op = COND_EXEC_CODE (op);
15771 if (GET_CODE (op) == PARALLEL)
15772 op = XVECEXP (op, 0, 0);
15775 early_op = XEXP (op, 0);
15776 /* This is either an actual independent shift, or a shift applied to
15777 the first operand of another operation. We want the whole shift
15779 if (GET_CODE (early_op) == REG)
15782 return !reg_overlap_mentioned_p (value, early_op);
15785 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15786 have an early register shift value dependency on the result of
15790 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
15792 rtx value = PATTERN (producer);
15793 rtx op = PATTERN (consumer);
15796 if (GET_CODE (value) == COND_EXEC)
15797 value = COND_EXEC_CODE (value);
15798 if (GET_CODE (value) == PARALLEL)
15799 value = XVECEXP (value, 0, 0);
15800 value = XEXP (value, 0);
15801 if (GET_CODE (op) == COND_EXEC)
15802 op = COND_EXEC_CODE (op);
15803 if (GET_CODE (op) == PARALLEL)
15804 op = XVECEXP (op, 0, 0);
15807 early_op = XEXP (op, 0);
15809 /* This is either an actual independent shift, or a shift applied to
15810 the first operand of another operation. We want the value being
15811 shifted, in either case. */
15812 if (GET_CODE (early_op) != REG)
15813 early_op = XEXP (early_op, 0);
15815 return !reg_overlap_mentioned_p (value, early_op);
15818 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15819 have an early register mult dependency on the result of
15823 arm_no_early_mul_dep (rtx producer, rtx consumer)
15825 rtx value = PATTERN (producer);
15826 rtx op = PATTERN (consumer);
15828 if (GET_CODE (value) == COND_EXEC)
15829 value = COND_EXEC_CODE (value);
15830 if (GET_CODE (value) == PARALLEL)
15831 value = XVECEXP (value, 0, 0);
15832 value = XEXP (value, 0);
15833 if (GET_CODE (op) == COND_EXEC)
15834 op = COND_EXEC_CODE (op);
15835 if (GET_CODE (op) == PARALLEL)
15836 op = XVECEXP (op, 0, 0);
15839 return (GET_CODE (op) == PLUS
15840 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
15844 /* We can't rely on the caller doing the proper promotion when
15845 using APCS or ATPCS. */
15848 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
15850 return !TARGET_AAPCS_BASED;
15854 /* AAPCS based ABIs use short enums by default. */
15857 arm_default_short_enums (void)
15859 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
15863 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15866 arm_align_anon_bitfield (void)
15868 return TARGET_AAPCS_BASED;
15872 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15875 arm_cxx_guard_type (void)
15877 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
15881 /* The EABI says test the least significant bit of a guard variable. */
15884 arm_cxx_guard_mask_bit (void)
15886 return TARGET_AAPCS_BASED;
15890 /* The EABI specifies that all array cookies are 8 bytes long. */
15893 arm_get_cookie_size (tree type)
15897 if (!TARGET_AAPCS_BASED)
15898 return default_cxx_get_cookie_size (type);
15900 size = build_int_cst (sizetype, 8);
15905 /* The EABI says that array cookies should also contain the element size. */
15908 arm_cookie_has_size (void)
15910 return TARGET_AAPCS_BASED;
15914 /* The EABI says constructors and destructors should return a pointer to
15915 the object constructed/destroyed. */
15918 arm_cxx_cdtor_returns_this (void)
15920 return TARGET_AAPCS_BASED;
15923 /* The EABI says that an inline function may never be the key
15927 arm_cxx_key_method_may_be_inline (void)
15929 return !TARGET_AAPCS_BASED;
15933 arm_cxx_determine_class_data_visibility (tree decl)
15935 if (!TARGET_AAPCS_BASED)
15938 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15939 is exported. However, on systems without dynamic vague linkage,
15940 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15941 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
15942 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
15944 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
15945 DECL_VISIBILITY_SPECIFIED (decl) = 1;
15949 arm_cxx_class_data_always_comdat (void)
15951 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15952 vague linkage if the class has no key function. */
15953 return !TARGET_AAPCS_BASED;
15957 /* The EABI says __aeabi_atexit should be used to register static
15961 arm_cxx_use_aeabi_atexit (void)
15963 return TARGET_AAPCS_BASED;
15968 arm_set_return_address (rtx source, rtx scratch)
15970 arm_stack_offsets *offsets;
15971 HOST_WIDE_INT delta;
15973 unsigned long saved_regs;
15975 saved_regs = arm_compute_save_reg_mask ();
15977 if ((saved_regs & (1 << LR_REGNUM)) == 0)
15978 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15981 if (frame_pointer_needed)
15982 addr = plus_constant(hard_frame_pointer_rtx, -4);
15985 /* LR will be the first saved register. */
15986 offsets = arm_get_frame_offsets ();
15987 delta = offsets->outgoing_args - (offsets->frame + 4);
15992 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
15993 GEN_INT (delta & ~4095)));
15998 addr = stack_pointer_rtx;
16000 addr = plus_constant (addr, delta);
16002 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16008 thumb_set_return_address (rtx source, rtx scratch)
16010 arm_stack_offsets *offsets;
16011 HOST_WIDE_INT delta;
16012 HOST_WIDE_INT limit;
16015 unsigned long mask;
16017 emit_insn (gen_rtx_USE (VOIDmode, source));
16019 mask = thumb1_compute_save_reg_mask ();
16020 if (mask & (1 << LR_REGNUM))
16022 offsets = arm_get_frame_offsets ();
16025 /* Find the saved regs. */
16026 if (frame_pointer_needed)
16028 delta = offsets->soft_frame - offsets->saved_args;
16029 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
16035 delta = offsets->outgoing_args - offsets->saved_args;
16038 /* Allow for the stack frame. */
16039 if (TARGET_THUMB1 && TARGET_BACKTRACE)
16041 /* The link register is always the first saved register. */
16044 /* Construct the address. */
16045 addr = gen_rtx_REG (SImode, reg);
16048 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
16049 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
16053 addr = plus_constant (addr, delta);
16055 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16058 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16061 /* Implements target hook vector_mode_supported_p. */
16063 arm_vector_mode_supported_p (enum machine_mode mode)
16065 if ((mode == V2SImode)
16066 || (mode == V4HImode)
16067 || (mode == V8QImode))
16073 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16074 ARM insns and therefore guarantee that the shift count is modulo 256.
16075 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16076 guarantee no particular behavior for out-of-range counts. */
16078 static unsigned HOST_WIDE_INT
16079 arm_shift_truncation_mask (enum machine_mode mode)
16081 return mode == SImode ? 255 : 0;
16085 /* Map internal gcc register numbers to DWARF2 register numbers. */
16088 arm_dbx_register_number (unsigned int regno)
16093 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16094 compatibility. The EABI defines them as registers 96-103. */
16095 if (IS_FPA_REGNUM (regno))
16096 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
16098 if (IS_VFP_REGNUM (regno))
16099 return 64 + regno - FIRST_VFP_REGNUM;
16101 if (IS_IWMMXT_GR_REGNUM (regno))
16102 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
16104 if (IS_IWMMXT_REGNUM (regno))
16105 return 112 + regno - FIRST_IWMMXT_REGNUM;
16107 gcc_unreachable ();
16111 #ifdef TARGET_UNWIND_INFO
16112 /* Emit unwind directives for a store-multiple instruction or stack pointer
16113 push during alignment.
16114 These should only ever be generated by the function prologue code, so
16115 expect them to have a particular form. */
16118 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
16121 HOST_WIDE_INT offset;
16122 HOST_WIDE_INT nregs;
16128 e = XVECEXP (p, 0, 0);
16129 if (GET_CODE (e) != SET)
16132 /* First insn will adjust the stack pointer. */
16133 if (GET_CODE (e) != SET
16134 || GET_CODE (XEXP (e, 0)) != REG
16135 || REGNO (XEXP (e, 0)) != SP_REGNUM
16136 || GET_CODE (XEXP (e, 1)) != PLUS)
16139 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
16140 nregs = XVECLEN (p, 0) - 1;
16142 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
16145 /* The function prologue may also push pc, but not annotate it as it is
16146 never restored. We turn this into a stack pointer adjustment. */
16147 if (nregs * 4 == offset - 4)
16149 fprintf (asm_out_file, "\t.pad #4\n");
16153 fprintf (asm_out_file, "\t.save {");
16155 else if (IS_VFP_REGNUM (reg))
16158 fprintf (asm_out_file, "\t.vsave {");
16160 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
16162 /* FPA registers are done differently. */
16163 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
16167 /* Unknown register type. */
16170 /* If the stack increment doesn't match the size of the saved registers,
16171 something has gone horribly wrong. */
16172 if (offset != nregs * reg_size)
16177 /* The remaining insns will describe the stores. */
16178 for (i = 1; i <= nregs; i++)
16180 /* Expect (set (mem <addr>) (reg)).
16181 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16182 e = XVECEXP (p, 0, i);
16183 if (GET_CODE (e) != SET
16184 || GET_CODE (XEXP (e, 0)) != MEM
16185 || GET_CODE (XEXP (e, 1)) != REG)
16188 reg = REGNO (XEXP (e, 1));
16193 fprintf (asm_out_file, ", ");
16194 /* We can't use %r for vfp because we need to use the
16195 double precision register names. */
16196 if (IS_VFP_REGNUM (reg))
16197 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
16199 asm_fprintf (asm_out_file, "%r", reg);
16201 #ifdef ENABLE_CHECKING
16202 /* Check that the addresses are consecutive. */
16203 e = XEXP (XEXP (e, 0), 0);
16204 if (GET_CODE (e) == PLUS)
16206 offset += reg_size;
16207 if (GET_CODE (XEXP (e, 0)) != REG
16208 || REGNO (XEXP (e, 0)) != SP_REGNUM
16209 || GET_CODE (XEXP (e, 1)) != CONST_INT
16210 || offset != INTVAL (XEXP (e, 1)))
16214 || GET_CODE (e) != REG
16215 || REGNO (e) != SP_REGNUM)
16219 fprintf (asm_out_file, "}\n");
16222 /* Emit unwind directives for a SET. */
16225 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
16233 switch (GET_CODE (e0))
16236 /* Pushing a single register. */
16237 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
16238 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
16239 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
16242 asm_fprintf (asm_out_file, "\t.save ");
16243 if (IS_VFP_REGNUM (REGNO (e1)))
16244 asm_fprintf(asm_out_file, "{d%d}\n",
16245 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
16247 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
16251 if (REGNO (e0) == SP_REGNUM)
16253 /* A stack increment. */
16254 if (GET_CODE (e1) != PLUS
16255 || GET_CODE (XEXP (e1, 0)) != REG
16256 || REGNO (XEXP (e1, 0)) != SP_REGNUM
16257 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16260 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
16261 -INTVAL (XEXP (e1, 1)));
16263 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
16265 HOST_WIDE_INT offset;
16267 if (GET_CODE (e1) == PLUS)
16269 if (GET_CODE (XEXP (e1, 0)) != REG
16270 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16272 reg = REGNO (XEXP (e1, 0));
16273 offset = INTVAL (XEXP (e1, 1));
16274 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
16275 HARD_FRAME_POINTER_REGNUM, reg,
16276 INTVAL (XEXP (e1, 1)));
16278 else if (GET_CODE (e1) == REG)
16281 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
16282 HARD_FRAME_POINTER_REGNUM, reg);
16287 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
16289 /* Move from sp to reg. */
16290 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
16292 else if (GET_CODE (e1) == PLUS
16293 && GET_CODE (XEXP (e1, 0)) == REG
16294 && REGNO (XEXP (e1, 0)) == SP_REGNUM
16295 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
16297 /* Set reg to offset from sp. */
16298 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
16299 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
16301 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
16303 /* Stack pointer save before alignment. */
16305 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16318 /* Emit unwind directives for the given insn. */
16321 arm_unwind_emit (FILE * asm_out_file, rtx insn)
16325 if (!ARM_EABI_UNWIND_TABLES)
16328 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
16331 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
16333 pat = XEXP (pat, 0);
16335 pat = PATTERN (insn);
16337 switch (GET_CODE (pat))
16340 arm_unwind_emit_set (asm_out_file, pat);
16344 /* Store multiple. */
16345 arm_unwind_emit_sequence (asm_out_file, pat);
16354 /* Output a reference from a function exception table to the type_info
16355 object X. The EABI specifies that the symbol should be relocated by
16356 an R_ARM_TARGET2 relocation. */
16359 arm_output_ttype (rtx x)
16361 fputs ("\t.word\t", asm_out_file);
16362 output_addr_const (asm_out_file, x);
16363 /* Use special relocations for symbol references. */
16364 if (GET_CODE (x) != CONST_INT)
16365 fputs ("(TARGET2)", asm_out_file);
16366 fputc ('\n', asm_out_file);
16370 #endif /* TARGET_UNWIND_INFO */
16373 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16374 stack alignment. */
16377 arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
16379 rtx unspec = SET_SRC (pattern);
16380 gcc_assert (GET_CODE (unspec) == UNSPEC);
16384 case UNSPEC_STACK_ALIGN:
16385 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16386 put anything on the stack, so hopefully it won't matter.
16387 CFA = SP will be correct after alignment. */
16388 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
16389 SET_DEST (pattern));
16392 gcc_unreachable ();
16397 /* Output unwind directives for the start/end of a function. */
16400 arm_output_fn_unwind (FILE * f, bool prologue)
16402 if (!ARM_EABI_UNWIND_TABLES)
16406 fputs ("\t.fnstart\n", f);
16408 fputs ("\t.fnend\n", f);
16412 arm_emit_tls_decoration (FILE *fp, rtx x)
16414 enum tls_reloc reloc;
16417 val = XVECEXP (x, 0, 0);
16418 reloc = INTVAL (XVECEXP (x, 0, 1));
16420 output_addr_const (fp, val);
16425 fputs ("(tlsgd)", fp);
16428 fputs ("(tlsldm)", fp);
16431 fputs ("(tlsldo)", fp);
16434 fputs ("(gottpoff)", fp);
16437 fputs ("(tpoff)", fp);
16440 gcc_unreachable ();
16448 fputs (" + (. - ", fp);
16449 output_addr_const (fp, XVECEXP (x, 0, 2));
16451 output_addr_const (fp, XVECEXP (x, 0, 3));
16462 arm_output_addr_const_extra (FILE *fp, rtx x)
16464 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
16465 return arm_emit_tls_decoration (fp, x);
16466 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
16469 int labelno = INTVAL (XVECEXP (x, 0, 0));
16471 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
16472 assemble_name_raw (fp, label);
16476 else if (GET_CODE (x) == CONST_VECTOR)
16477 return arm_emit_vector_const (fp, x);
16482 /* Output assembly for a shift instruction.
16483 SET_FLAGS determines how the instruction modifies the condition codes.
16484 0 - Do not set condition codes.
16485 1 - Set condition codes.
16486 2 - Use smallest instruction. */
16488 arm_output_shift(rtx * operands, int set_flags)
16491 static const char flag_chars[3] = {'?', '.', '!'};
16496 c = flag_chars[set_flags];
16497 if (TARGET_UNIFIED_ASM)
16499 shift = shift_op(operands[3], &val);
16503 operands[2] = GEN_INT(val);
16504 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
16507 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
16510 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
16511 output_asm_insn (pattern, operands);
16515 /* Output a Thumb-2 casesi instruction. */
16517 thumb2_output_casesi (rtx *operands)
16519 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
16521 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
16523 output_asm_insn ("cmp\t%0, %1", operands);
16524 output_asm_insn ("bhi\t%l3", operands);
16525 switch (GET_MODE(diff_vec))
16528 return "tbb\t[%|pc, %0]";
16530 return "tbh\t[%|pc, %0, lsl #1]";
16534 output_asm_insn ("adr\t%4, %l2", operands);
16535 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
16536 output_asm_insn ("add\t%4, %4, %5", operands);
16541 output_asm_insn ("adr\t%4, %l2", operands);
16542 return "ldr\t%|pc, [%4, %0, lsl #2]";
16545 gcc_unreachable ();
16549 #include "gt-arm.h"