1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
71 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
72 inline static int thumb1_index_register_rtx_p (rtx, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
77 static rtx emit_sfm (int, int);
78 static int arm_size_return_regs (void);
80 static bool arm_assemble_integer (rtx, unsigned int, int);
82 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
83 static arm_cc get_arm_condition_code (rtx);
84 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
85 static rtx is_jump_table (rtx);
86 static const char *output_multi_immediate (rtx *, const char *, const char *,
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
147 static rtx emit_set_insn (rtx, rtx);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx, int);
155 static void arm_encode_section_info (tree, rtx, int);
158 static void arm_file_end (void);
159 static void arm_file_start (void);
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
172 enum machine_mode, tree, bool);
173 static bool arm_promote_prototypes (tree);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree);
177 static bool arm_must_pass_in_stack (enum machine_mode, tree);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx);
180 static bool arm_output_ttype (rtx);
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
184 static tree arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree arm_get_cookie_size (tree);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
196 static bool arm_cannot_copy_insn_p (rtx);
197 static bool arm_tls_symbol_p (rtx x);
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
254 #undef TARGET_ENCODE_SECTION_INFO
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
380 struct gcc_target targetm = TARGET_INITIALIZER;
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack;
384 static char * minipool_startobj;
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped = 5;
390 extern FILE * asm_out_file;
392 /* True if we are currently building a constant table. */
393 int making_const_table;
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0, arm_compare_op1;
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune = arm_none;
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu = arm_none;
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model;
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch;
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune;
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi;
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi;
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer = TP_AUTO;
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label[14];
428 static int thumb_call_reg_needed;
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 #define FL_DIV (1 << 18) /* Hardware divde. */
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags = 0;
481 /* The bits in this mask specify which instruction scheduling options should
483 static unsigned long tune_flags = 0;
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
506 /* Nonzero if this chip supports the ARM 6K extensions. */
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm = 0;
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched = 0;
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm = 0;
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus = 0;
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt = 0;
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale = 0;
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale = 0;
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf = 0;
534 /* Nonzero if generating Thumb instructions. */
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork = 0;
544 /* Nonzero if chip supports Thumb 2. */
547 /* Nonzero if chip supports integer division instruction. */
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode;
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register = INVALID_REGNUM;
558 /* Set to 1 when a return insn is output, this means that the epilogue
560 int return_used_this_function;
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg = 0;
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit = 3;
569 /* For an explanation of these variables, see final_prescan_insn below. */
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc;
574 int arm_target_label;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count = 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask = 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen = 0;
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes[] =
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
597 /* Initialization code. */
601 const char *const name;
602 enum processor_type core;
604 const unsigned long flags;
605 bool (* rtx_costs) (rtx, int, int, int *);
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores[] =
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
617 {NULL, arm_none, NULL, 0, NULL}
620 static const struct processors all_architectures[] =
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
626 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
627 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
628 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
629 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
630 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
634 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
635 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
636 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
637 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
638 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
639 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
640 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
641 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
642 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
643 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
644 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
645 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
646 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
647 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
648 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
649 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
650 {NULL, arm_none, NULL, 0 , NULL}
653 struct arm_cpu_select
657 const struct processors * processors;
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
664 static struct arm_cpu_select arm_select[] =
666 /* string name processors */
667 { NULL, "-mcpu=", all_cores },
668 { NULL, "-march=", all_architectures },
669 { NULL, "-mtune=", all_cores }
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
677 /* The name of the preprocessor macro to define for this architecture. */
679 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
688 /* Available values for -mfpu=. */
690 static const struct fpu_desc all_fpus[] =
692 {"fpa", FPUTYPE_FPA},
693 {"fpe2", FPUTYPE_FPA_EMU2},
694 {"fpe3", FPUTYPE_FPA_EMU2},
695 {"maverick", FPUTYPE_MAVERICK},
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
703 static const enum fputype fp_model_for_fpu[] =
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
718 enum float_abi_type abi_type;
722 /* Available values for -mfloat-abi=. */
724 static const struct float_abi all_float_abis[] =
726 {"soft", ARM_FLOAT_ABI_SOFT},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP},
728 {"hard", ARM_FLOAT_ABI_HARD}
735 enum arm_abi_type abi_type;
739 /* Available values for -mabi=. */
741 static const struct abi_name arm_all_abis[] =
743 {"apcs-gnu", ARM_ABI_APCS},
744 {"atpcs", ARM_ABI_ATPCS},
745 {"aapcs", ARM_ABI_AAPCS},
746 {"iwmmxt", ARM_ABI_IWMMXT},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
750 /* Supported TLS relocations. */
760 /* Emit an insn that's a simple single-set. Both the operands must be known
763 emit_set_insn (rtx x, rtx y)
765 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
768 /* Return the number of bits set in VALUE. */
770 bit_count (unsigned long value)
772 unsigned long count = 0;
777 value &= value - 1; /* Clear the least-significant set bit. */
783 /* Set up library functions unique to ARM. */
786 arm_init_libfuncs (void)
788 /* There are no special library functions unless we are using the
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab, DFmode, NULL);
806 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab, SFmode, NULL);
822 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
875 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
878 /* For SImode division the ABI provides div-without-mod routines,
880 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab, DImode, NULL);
886 set_optab_libfunc (umod_optab, DImode, NULL);
887 set_optab_libfunc (smod_optab, SImode, NULL);
888 set_optab_libfunc (umod_optab, SImode, NULL);
891 /* Implement TARGET_HANDLE_OPTION. */
894 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
899 arm_select[1].string = arg;
903 arm_select[0].string = arg;
906 case OPT_mhard_float:
907 target_float_abi_name = "hard";
910 case OPT_msoft_float:
911 target_float_abi_name = "soft";
915 arm_select[2].string = arg;
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
926 arm_override_options (void)
929 enum processor_type target_arch_cpu = arm_none;
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i = ARRAY_SIZE (arm_select); i--;)
934 struct arm_cpu_select * ptr = arm_select + i;
936 if (ptr->string != NULL && ptr->string[0] != '\0')
938 const struct processors * sel;
940 for (sel = ptr->processors; sel->name != NULL; sel++)
941 if (streq (ptr->string, sel->name))
943 /* Set the architecture define. */
944 if (i != ARM_OPT_SET_TUNE)
945 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i == ARM_OPT_SET_TUNE)
953 arm_tune = (enum processor_type) (sel - ptr->processors);
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
959 if (i == ARM_OPT_SET_ARCH)
960 target_arch_cpu = sel->core;
962 if (i != ARM_OPT_SET_TUNE)
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
968 if (insn_flags != 0 && (insn_flags ^ sel->flags))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
972 insn_flags = sel->flags;
978 if (sel->name == NULL)
979 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune == arm_none)
985 arm_tune = target_arch_cpu;
987 /* If the user did not specify a processor, choose one for them. */
990 const struct processors * sel;
992 enum processor_type cpu;
994 cpu = TARGET_CPU_DEFAULT;
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
1000 cpu = SUBTARGET_CPU_DEFAULT;
1002 /* Default to ARM6. */
1003 if (cpu == arm_none)
1006 sel = &all_cores[cpu];
1008 insn_flags = sel->flags;
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1014 if (TARGET_INTERWORK || TARGET_THUMB)
1016 sought |= (FL_THUMB | FL_MODE32);
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags &= ~FL_MODE26;
1025 if (sought != 0 && ((sought & insn_flags) != sought))
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1030 for (sel = all_cores; sel->name != NULL; sel++)
1031 if ((sel->flags & sought) == (sought | insn_flags))
1034 if (sel->name == NULL)
1036 unsigned current_bit_count = 0;
1037 const struct processors * best_fit = NULL;
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel = all_cores; sel->name != NULL; sel++)
1051 if ((sel->flags & sought) == sought)
1055 count = bit_count (sel->flags & insn_flags);
1057 if (count >= current_bit_count)
1060 current_bit_count = count;
1064 gcc_assert (best_fit);
1068 insn_flags = sel->flags;
1070 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1071 arm_default_cpu = (enum processor_type) (sel - all_cores);
1072 if (arm_tune == arm_none)
1073 arm_tune = arm_default_cpu;
1076 /* The processor for which we should tune should now have been
1078 gcc_assert (arm_tune != arm_none);
1080 tune_flags = all_cores[(int)arm_tune].flags;
1082 targetm.rtx_costs = arm_size_rtx_costs;
1084 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1089 error ("target CPU does not support ARM mode");
1091 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags &= ~MASK_INTERWORK;
1097 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags &= ~MASK_THUMB;
1103 if (TARGET_APCS_FRAME && TARGET_THUMB)
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags &= ~MASK_APCS_FRAME;
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1112 target_flags |= MASK_INTERWORK;
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1119 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1122 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1125 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags |= MASK_APCS_FRAME;
1131 if (TARGET_POKE_FUNCTION_NAME)
1132 target_flags |= MASK_APCS_FRAME;
1134 if (TARGET_APCS_REENT && flag_pic)
1135 error ("-fpic and -mapcs-reent are incompatible");
1137 if (TARGET_APCS_REENT)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1143 && write_symbols != NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1148 /* If stack checking is disabled, we can use r10 as the PIC register,
1149 which keeps r9 available. */
1150 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1151 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1153 if (TARGET_APCS_FLOAT)
1154 warning (0, "passing floating point arguments in fp regs not yet supported");
1156 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1157 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1158 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1159 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1160 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1161 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1162 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1163 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1164 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1165 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1166 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1167 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1169 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1170 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1171 thumb_code = (TARGET_ARM == 0);
1172 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1173 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1174 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1175 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1177 /* V5 code we generate is completely interworking capable, so we turn off
1178 TARGET_INTERWORK here to avoid many tests later on. */
1180 /* XXX However, we must pass the right pre-processor defines to CPP
1181 or GLD can get confused. This is a hack. */
1182 if (TARGET_INTERWORK)
1183 arm_cpp_interwork = 1;
1186 target_flags &= ~MASK_INTERWORK;
1188 if (target_abi_name)
1190 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1192 if (streq (arm_all_abis[i].name, target_abi_name))
1194 arm_abi = arm_all_abis[i].abi_type;
1198 if (i == ARRAY_SIZE (arm_all_abis))
1199 error ("invalid ABI option: -mabi=%s", target_abi_name);
1202 arm_abi = ARM_DEFAULT_ABI;
1204 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1205 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1207 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1208 error ("iwmmxt abi requires an iwmmxt capable cpu");
1210 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1211 if (target_fpu_name == NULL && target_fpe_name != NULL)
1213 if (streq (target_fpe_name, "2"))
1214 target_fpu_name = "fpe2";
1215 else if (streq (target_fpe_name, "3"))
1216 target_fpu_name = "fpe3";
1218 error ("invalid floating point emulation option: -mfpe=%s",
1221 if (target_fpu_name != NULL)
1223 /* The user specified a FPU. */
1224 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1226 if (streq (all_fpus[i].name, target_fpu_name))
1228 arm_fpu_arch = all_fpus[i].fpu;
1229 arm_fpu_tune = arm_fpu_arch;
1230 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1234 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1235 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1239 #ifdef FPUTYPE_DEFAULT
1240 /* Use the default if it is specified for this platform. */
1241 arm_fpu_arch = FPUTYPE_DEFAULT;
1242 arm_fpu_tune = FPUTYPE_DEFAULT;
1244 /* Pick one based on CPU type. */
1245 /* ??? Some targets assume FPA is the default.
1246 if ((insn_flags & FL_VFP) != 0)
1247 arm_fpu_arch = FPUTYPE_VFP;
1250 if (arm_arch_cirrus)
1251 arm_fpu_arch = FPUTYPE_MAVERICK;
1253 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1255 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1256 arm_fpu_tune = FPUTYPE_FPA;
1258 arm_fpu_tune = arm_fpu_arch;
1259 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1260 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1263 if (target_float_abi_name != NULL)
1265 /* The user specified a FP ABI. */
1266 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1268 if (streq (all_float_abis[i].name, target_float_abi_name))
1270 arm_float_abi = all_float_abis[i].abi_type;
1274 if (i == ARRAY_SIZE (all_float_abis))
1275 error ("invalid floating point abi: -mfloat-abi=%s",
1276 target_float_abi_name);
1279 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1281 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1282 sorry ("-mfloat-abi=hard and VFP");
1284 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1285 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1286 will ever exist. GCC makes no attempt to support this combination. */
1287 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1288 sorry ("iWMMXt and hardware floating point");
1290 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1291 if (TARGET_THUMB2 && TARGET_IWMMXT)
1292 sorry ("Thumb-2 iWMMXt");
1294 /* If soft-float is specified then don't use FPU. */
1295 if (TARGET_SOFT_FLOAT)
1296 arm_fpu_arch = FPUTYPE_NONE;
1298 /* For arm2/3 there is no need to do any scheduling if there is only
1299 a floating point emulator, or we are doing software floating-point. */
1300 if ((TARGET_SOFT_FLOAT
1301 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1302 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1303 && (tune_flags & FL_MODE32) == 0)
1304 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1306 if (target_thread_switch)
1308 if (strcmp (target_thread_switch, "soft") == 0)
1309 target_thread_pointer = TP_SOFT;
1310 else if (strcmp (target_thread_switch, "auto") == 0)
1311 target_thread_pointer = TP_AUTO;
1312 else if (strcmp (target_thread_switch, "cp15") == 0)
1313 target_thread_pointer = TP_CP15;
1315 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1318 /* Use the cp15 method if it is available. */
1319 if (target_thread_pointer == TP_AUTO)
1321 if (arm_arch6k && !TARGET_THUMB)
1322 target_thread_pointer = TP_CP15;
1324 target_thread_pointer = TP_SOFT;
1327 if (TARGET_HARD_TP && TARGET_THUMB1)
1328 error ("can not use -mtp=cp15 with 16-bit Thumb");
1330 /* Override the default structure alignment for AAPCS ABI. */
1331 if (TARGET_AAPCS_BASED)
1332 arm_structure_size_boundary = 8;
1334 if (structure_size_string != NULL)
1336 int size = strtol (structure_size_string, NULL, 0);
1338 if (size == 8 || size == 32
1339 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1340 arm_structure_size_boundary = size;
1342 warning (0, "structure size boundary can only be set to %s",
1343 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1346 if (arm_pic_register_string != NULL)
1348 int pic_register = decode_reg_name (arm_pic_register_string);
1351 warning (0, "-mpic-register= is useless without -fpic");
1353 /* Prevent the user from choosing an obviously stupid PIC register. */
1354 else if (pic_register < 0 || call_used_regs[pic_register]
1355 || pic_register == HARD_FRAME_POINTER_REGNUM
1356 || pic_register == STACK_POINTER_REGNUM
1357 || pic_register >= PC_REGNUM)
1358 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1360 arm_pic_register = pic_register;
1363 /* ??? We might want scheduling for thumb2. */
1364 if (TARGET_THUMB && flag_schedule_insns)
1366 /* Don't warn since it's on by default in -O2. */
1367 flag_schedule_insns = 0;
1372 arm_constant_limit = 1;
1374 /* If optimizing for size, bump the number of instructions that we
1375 are prepared to conditionally execute (even on a StrongARM). */
1376 max_insns_skipped = 6;
1380 /* For processors with load scheduling, it never costs more than
1381 2 cycles to load a constant, and the load scheduler may well
1382 reduce that to 1. */
1384 arm_constant_limit = 1;
1386 /* On XScale the longer latency of a load makes it more difficult
1387 to achieve a good schedule, so it's faster to synthesize
1388 constants that can be done in two insns. */
1389 if (arm_tune_xscale)
1390 arm_constant_limit = 2;
1392 /* StrongARM has early execution of branches, so a sequence
1393 that is worth skipping is shorter. */
1394 if (arm_tune_strongarm)
1395 max_insns_skipped = 3;
1398 /* Register global variables with the garbage collector. */
1399 arm_add_gc_roots ();
1403 arm_add_gc_roots (void)
1405 gcc_obstack_init(&minipool_obstack);
1406 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1409 /* A table of known ARM exception types.
1410 For use with the interrupt function attribute. */
1414 const char *const arg;
1415 const unsigned long return_value;
1419 static const isr_attribute_arg isr_attribute_args [] =
1421 { "IRQ", ARM_FT_ISR },
1422 { "irq", ARM_FT_ISR },
1423 { "FIQ", ARM_FT_FIQ },
1424 { "fiq", ARM_FT_FIQ },
1425 { "ABORT", ARM_FT_ISR },
1426 { "abort", ARM_FT_ISR },
1427 { "ABORT", ARM_FT_ISR },
1428 { "abort", ARM_FT_ISR },
1429 { "UNDEF", ARM_FT_EXCEPTION },
1430 { "undef", ARM_FT_EXCEPTION },
1431 { "SWI", ARM_FT_EXCEPTION },
1432 { "swi", ARM_FT_EXCEPTION },
1433 { NULL, ARM_FT_NORMAL }
1436 /* Returns the (interrupt) function type of the current
1437 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1439 static unsigned long
1440 arm_isr_value (tree argument)
1442 const isr_attribute_arg * ptr;
1446 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1448 /* No argument - default to IRQ. */
1449 if (argument == NULL_TREE)
1452 /* Get the value of the argument. */
1453 if (TREE_VALUE (argument) == NULL_TREE
1454 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1455 return ARM_FT_UNKNOWN;
1457 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1459 /* Check it against the list of known arguments. */
1460 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1461 if (streq (arg, ptr->arg))
1462 return ptr->return_value;
1464 /* An unrecognized interrupt type. */
1465 return ARM_FT_UNKNOWN;
1468 /* Computes the type of the current function. */
1470 static unsigned long
1471 arm_compute_func_type (void)
1473 unsigned long type = ARM_FT_UNKNOWN;
1477 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1479 /* Decide if the current function is volatile. Such functions
1480 never return, and many memory cycles can be saved by not storing
1481 register values that will never be needed again. This optimization
1482 was added to speed up context switching in a kernel application. */
1484 && (TREE_NOTHROW (current_function_decl)
1485 || !(flag_unwind_tables
1486 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1487 && TREE_THIS_VOLATILE (current_function_decl))
1488 type |= ARM_FT_VOLATILE;
1490 if (cfun->static_chain_decl != NULL)
1491 type |= ARM_FT_NESTED;
1493 attr = DECL_ATTRIBUTES (current_function_decl);
1495 a = lookup_attribute ("naked", attr);
1497 type |= ARM_FT_NAKED;
1499 a = lookup_attribute ("isr", attr);
1501 a = lookup_attribute ("interrupt", attr);
1504 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1506 type |= arm_isr_value (TREE_VALUE (a));
1511 /* Returns the type of the current function. */
1514 arm_current_func_type (void)
1516 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1517 cfun->machine->func_type = arm_compute_func_type ();
1519 return cfun->machine->func_type;
1522 /* Return 1 if it is possible to return using a single instruction.
1523 If SIBLING is non-null, this is a test for a return before a sibling
1524 call. SIBLING is the call insn, so we can examine its register usage. */
1527 use_return_insn (int iscond, rtx sibling)
1530 unsigned int func_type;
1531 unsigned long saved_int_regs;
1532 unsigned HOST_WIDE_INT stack_adjust;
1533 arm_stack_offsets *offsets;
1535 /* Never use a return instruction before reload has run. */
1536 if (!reload_completed)
1539 func_type = arm_current_func_type ();
1541 /* Naked, volatile and stack alignment functions need special
1543 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1546 /* So do interrupt functions that use the frame pointer and Thumb
1547 interrupt functions. */
1548 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1551 offsets = arm_get_frame_offsets ();
1552 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1554 /* As do variadic functions. */
1555 if (current_function_pretend_args_size
1556 || cfun->machine->uses_anonymous_args
1557 /* Or if the function calls __builtin_eh_return () */
1558 || current_function_calls_eh_return
1559 /* Or if the function calls alloca */
1560 || current_function_calls_alloca
1561 /* Or if there is a stack adjustment. However, if the stack pointer
1562 is saved on the stack, we can use a pre-incrementing stack load. */
1563 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1566 saved_int_regs = arm_compute_save_reg_mask ();
1568 /* Unfortunately, the insn
1570 ldmib sp, {..., sp, ...}
1572 triggers a bug on most SA-110 based devices, such that the stack
1573 pointer won't be correctly restored if the instruction takes a
1574 page fault. We work around this problem by popping r3 along with
1575 the other registers, since that is never slower than executing
1576 another instruction.
1578 We test for !arm_arch5 here, because code for any architecture
1579 less than this could potentially be run on one of the buggy
1581 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1583 /* Validate that r3 is a call-clobbered register (always true in
1584 the default abi) ... */
1585 if (!call_used_regs[3])
1588 /* ... that it isn't being used for a return value ... */
1589 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1592 /* ... or for a tail-call argument ... */
1595 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1597 if (find_regno_fusage (sibling, USE, 3))
1601 /* ... and that there are no call-saved registers in r0-r2
1602 (always true in the default ABI). */
1603 if (saved_int_regs & 0x7)
1607 /* Can't be done if interworking with Thumb, and any registers have been
1609 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1612 /* On StrongARM, conditional returns are expensive if they aren't
1613 taken and multiple registers have been stacked. */
1614 if (iscond && arm_tune_strongarm)
1616 /* Conditional return when just the LR is stored is a simple
1617 conditional-load instruction, that's not expensive. */
1618 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1622 && arm_pic_register != INVALID_REGNUM
1623 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1627 /* If there are saved registers but the LR isn't saved, then we need
1628 two instructions for the return. */
1629 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1632 /* Can't be done if any of the FPA regs are pushed,
1633 since this also requires an insn. */
1634 if (TARGET_HARD_FLOAT && TARGET_FPA)
1635 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1636 if (regs_ever_live[regno] && !call_used_regs[regno])
1639 /* Likewise VFP regs. */
1640 if (TARGET_HARD_FLOAT && TARGET_VFP)
1641 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1642 if (regs_ever_live[regno] && !call_used_regs[regno])
1645 if (TARGET_REALLY_IWMMXT)
1646 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1647 if (regs_ever_live[regno] && ! call_used_regs [regno])
1653 /* Return TRUE if int I is a valid immediate ARM constant. */
1656 const_ok_for_arm (HOST_WIDE_INT i)
1660 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1661 be all zero, or all one. */
1662 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1663 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1664 != ((~(unsigned HOST_WIDE_INT) 0)
1665 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1668 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1670 /* Fast return for 0 and small values. We must do this for zero, since
1671 the code below can't handle that one case. */
1672 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1675 /* Get the number of trailing zeros. */
1676 lowbit = ffs((int) i) - 1;
1678 /* Only even shifts are allowed in ARM mode so round down to the
1679 nearest even number. */
1683 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1688 /* Allow rotated constants in ARM mode. */
1690 && ((i & ~0xc000003f) == 0
1691 || (i & ~0xf000000f) == 0
1692 || (i & ~0xfc000003) == 0))
1699 /* Allow repeated pattern. */
1702 if (i == v || i == (v | (v << 8)))
1709 /* Return true if I is a valid constant for the operation CODE. */
1711 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1713 if (const_ok_for_arm (i))
1719 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1721 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1727 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1734 /* Emit a sequence of insns to handle a large constant.
1735 CODE is the code of the operation required, it can be any of SET, PLUS,
1736 IOR, AND, XOR, MINUS;
1737 MODE is the mode in which the operation is being performed;
1738 VAL is the integer to operate on;
1739 SOURCE is the other operand (a register, or a null-pointer for SET);
1740 SUBTARGETS means it is safe to create scratch registers if that will
1741 either produce a simpler sequence, or we will want to cse the values.
1742 Return value is the number of insns emitted. */
1744 /* ??? Tweak this for thumb2. */
1746 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1747 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1751 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1752 cond = COND_EXEC_TEST (PATTERN (insn));
1756 if (subtargets || code == SET
1757 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1758 && REGNO (target) != REGNO (source)))
1760 /* After arm_reorg has been called, we can't fix up expensive
1761 constants by pushing them into memory so we must synthesize
1762 them in-line, regardless of the cost. This is only likely to
1763 be more costly on chips that have load delay slots and we are
1764 compiling without running the scheduler (so no splitting
1765 occurred before the final instruction emission).
1767 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1769 if (!after_arm_reorg
1771 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1773 > arm_constant_limit + (code != SET)))
1777 /* Currently SET is the only monadic value for CODE, all
1778 the rest are diadic. */
1779 emit_set_insn (target, GEN_INT (val));
1784 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1786 emit_set_insn (temp, GEN_INT (val));
1787 /* For MINUS, the value is subtracted from, since we never
1788 have subtraction of a constant. */
1790 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1792 emit_set_insn (target,
1793 gen_rtx_fmt_ee (code, mode, source, temp));
1799 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1803 /* Return the number of ARM instructions required to synthesize the given
1806 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1808 HOST_WIDE_INT temp1;
1816 if (remainder & (3 << (i - 2)))
1821 temp1 = remainder & ((0x0ff << end)
1822 | ((i < end) ? (0xff >> (32 - end)) : 0));
1823 remainder &= ~temp1;
1828 } while (remainder);
1832 /* Emit an instruction with the indicated PATTERN. If COND is
1833 non-NULL, conditionalize the execution of the instruction on COND
1837 emit_constant_insn (rtx cond, rtx pattern)
1840 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1841 emit_insn (pattern);
1844 /* As above, but extra parameter GENERATE which, if clear, suppresses
1846 /* ??? This needs more work for thumb2. */
1849 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1850 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1855 int can_negate_initial = 0;
1858 int num_bits_set = 0;
1859 int set_sign_bit_copies = 0;
1860 int clear_sign_bit_copies = 0;
1861 int clear_zero_bit_copies = 0;
1862 int set_zero_bit_copies = 0;
1864 unsigned HOST_WIDE_INT temp1, temp2;
1865 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1867 /* Find out which operations are safe for a given CODE. Also do a quick
1868 check for degenerate cases; these can occur when DImode operations
1880 can_negate_initial = 1;
1884 if (remainder == 0xffffffff)
1887 emit_constant_insn (cond,
1888 gen_rtx_SET (VOIDmode, target,
1889 GEN_INT (ARM_SIGN_EXTEND (val))));
1894 if (reload_completed && rtx_equal_p (target, source))
1897 emit_constant_insn (cond,
1898 gen_rtx_SET (VOIDmode, target, source));
1907 emit_constant_insn (cond,
1908 gen_rtx_SET (VOIDmode, target, const0_rtx));
1911 if (remainder == 0xffffffff)
1913 if (reload_completed && rtx_equal_p (target, source))
1916 emit_constant_insn (cond,
1917 gen_rtx_SET (VOIDmode, target, source));
1926 if (reload_completed && rtx_equal_p (target, source))
1929 emit_constant_insn (cond,
1930 gen_rtx_SET (VOIDmode, target, source));
1934 /* We don't know how to handle other cases yet. */
1935 gcc_assert (remainder == 0xffffffff);
1938 emit_constant_insn (cond,
1939 gen_rtx_SET (VOIDmode, target,
1940 gen_rtx_NOT (mode, source)));
1944 /* We treat MINUS as (val - source), since (source - val) is always
1945 passed as (source + (-val)). */
1949 emit_constant_insn (cond,
1950 gen_rtx_SET (VOIDmode, target,
1951 gen_rtx_NEG (mode, source)));
1954 if (const_ok_for_arm (val))
1957 emit_constant_insn (cond,
1958 gen_rtx_SET (VOIDmode, target,
1959 gen_rtx_MINUS (mode, GEN_INT (val),
1971 /* If we can do it in one insn get out quickly. */
1972 if (const_ok_for_arm (val)
1973 || (can_negate_initial && const_ok_for_arm (-val))
1974 || (can_invert && const_ok_for_arm (~val)))
1977 emit_constant_insn (cond,
1978 gen_rtx_SET (VOIDmode, target,
1980 ? gen_rtx_fmt_ee (code, mode, source,
1986 /* Calculate a few attributes that may be useful for specific
1988 for (i = 31; i >= 0; i--)
1990 if ((remainder & (1 << i)) == 0)
1991 clear_sign_bit_copies++;
1996 for (i = 31; i >= 0; i--)
1998 if ((remainder & (1 << i)) != 0)
1999 set_sign_bit_copies++;
2004 for (i = 0; i <= 31; i++)
2006 if ((remainder & (1 << i)) == 0)
2007 clear_zero_bit_copies++;
2012 for (i = 0; i <= 31; i++)
2014 if ((remainder & (1 << i)) != 0)
2015 set_zero_bit_copies++;
2023 /* See if we can use movw. */
2024 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2027 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2032 /* See if we can do this by sign_extending a constant that is known
2033 to be negative. This is a good, way of doing it, since the shift
2034 may well merge into a subsequent insn. */
2035 if (set_sign_bit_copies > 1)
2037 if (const_ok_for_arm
2038 (temp1 = ARM_SIGN_EXTEND (remainder
2039 << (set_sign_bit_copies - 1))))
2043 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2044 emit_constant_insn (cond,
2045 gen_rtx_SET (VOIDmode, new_src,
2047 emit_constant_insn (cond,
2048 gen_ashrsi3 (target, new_src,
2049 GEN_INT (set_sign_bit_copies - 1)));
2053 /* For an inverted constant, we will need to set the low bits,
2054 these will be shifted out of harm's way. */
2055 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2056 if (const_ok_for_arm (~temp1))
2060 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2061 emit_constant_insn (cond,
2062 gen_rtx_SET (VOIDmode, new_src,
2064 emit_constant_insn (cond,
2065 gen_ashrsi3 (target, new_src,
2066 GEN_INT (set_sign_bit_copies - 1)));
2072 /* See if we can calculate the value as the difference between two
2073 valid immediates. */
2074 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2076 int topshift = clear_sign_bit_copies & ~1;
2078 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2079 & (0xff000000 >> topshift));
2081 /* If temp1 is zero, then that means the 9 most significant
2082 bits of remainder were 1 and we've caused it to overflow.
2083 When topshift is 0 we don't need to do anything since we
2084 can borrow from 'bit 32'. */
2085 if (temp1 == 0 && topshift != 0)
2086 temp1 = 0x80000000 >> (topshift - 1);
2088 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2090 if (const_ok_for_arm (temp2))
2094 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2095 emit_constant_insn (cond,
2096 gen_rtx_SET (VOIDmode, new_src,
2098 emit_constant_insn (cond,
2099 gen_addsi3 (target, new_src,
2107 /* See if we can generate this by setting the bottom (or the top)
2108 16 bits, and then shifting these into the other half of the
2109 word. We only look for the simplest cases, to do more would cost
2110 too much. Be careful, however, not to generate this when the
2111 alternative would take fewer insns. */
2112 if (val & 0xffff0000)
2114 temp1 = remainder & 0xffff0000;
2115 temp2 = remainder & 0x0000ffff;
2117 /* Overlaps outside this range are best done using other methods. */
2118 for (i = 9; i < 24; i++)
2120 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2121 && !const_ok_for_arm (temp2))
2123 rtx new_src = (subtargets
2124 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2126 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2127 source, subtargets, generate);
2135 gen_rtx_ASHIFT (mode, source,
2142 /* Don't duplicate cases already considered. */
2143 for (i = 17; i < 24; i++)
2145 if (((temp1 | (temp1 >> i)) == remainder)
2146 && !const_ok_for_arm (temp1))
2148 rtx new_src = (subtargets
2149 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2151 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2152 source, subtargets, generate);
2157 gen_rtx_SET (VOIDmode, target,
2160 gen_rtx_LSHIFTRT (mode, source,
2171 /* If we have IOR or XOR, and the constant can be loaded in a
2172 single instruction, and we can find a temporary to put it in,
2173 then this can be done in two instructions instead of 3-4. */
2175 /* TARGET can't be NULL if SUBTARGETS is 0 */
2176 || (reload_completed && !reg_mentioned_p (target, source)))
2178 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2182 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2184 emit_constant_insn (cond,
2185 gen_rtx_SET (VOIDmode, sub,
2187 emit_constant_insn (cond,
2188 gen_rtx_SET (VOIDmode, target,
2189 gen_rtx_fmt_ee (code, mode,
2199 if (set_sign_bit_copies > 8
2200 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2204 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2205 rtx shift = GEN_INT (set_sign_bit_copies);
2209 gen_rtx_SET (VOIDmode, sub,
2211 gen_rtx_ASHIFT (mode,
2216 gen_rtx_SET (VOIDmode, target,
2218 gen_rtx_LSHIFTRT (mode, sub,
2224 if (set_zero_bit_copies > 8
2225 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2229 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2230 rtx shift = GEN_INT (set_zero_bit_copies);
2234 gen_rtx_SET (VOIDmode, sub,
2236 gen_rtx_LSHIFTRT (mode,
2241 gen_rtx_SET (VOIDmode, target,
2243 gen_rtx_ASHIFT (mode, sub,
2249 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2253 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2254 emit_constant_insn (cond,
2255 gen_rtx_SET (VOIDmode, sub,
2256 gen_rtx_NOT (mode, source)));
2259 sub = gen_reg_rtx (mode);
2260 emit_constant_insn (cond,
2261 gen_rtx_SET (VOIDmode, sub,
2262 gen_rtx_AND (mode, source,
2264 emit_constant_insn (cond,
2265 gen_rtx_SET (VOIDmode, target,
2266 gen_rtx_NOT (mode, sub)));
2273 /* See if two shifts will do 2 or more insn's worth of work. */
2274 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2276 HOST_WIDE_INT shift_mask = ((0xffffffff
2277 << (32 - clear_sign_bit_copies))
2280 if ((remainder | shift_mask) != 0xffffffff)
2284 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2285 insns = arm_gen_constant (AND, mode, cond,
2286 remainder | shift_mask,
2287 new_src, source, subtargets, 1);
2292 rtx targ = subtargets ? NULL_RTX : target;
2293 insns = arm_gen_constant (AND, mode, cond,
2294 remainder | shift_mask,
2295 targ, source, subtargets, 0);
2301 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2302 rtx shift = GEN_INT (clear_sign_bit_copies);
2304 emit_insn (gen_ashlsi3 (new_src, source, shift));
2305 emit_insn (gen_lshrsi3 (target, new_src, shift));
2311 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2313 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2315 if ((remainder | shift_mask) != 0xffffffff)
2319 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2321 insns = arm_gen_constant (AND, mode, cond,
2322 remainder | shift_mask,
2323 new_src, source, subtargets, 1);
2328 rtx targ = subtargets ? NULL_RTX : target;
2330 insns = arm_gen_constant (AND, mode, cond,
2331 remainder | shift_mask,
2332 targ, source, subtargets, 0);
2338 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2339 rtx shift = GEN_INT (clear_zero_bit_copies);
2341 emit_insn (gen_lshrsi3 (new_src, source, shift));
2342 emit_insn (gen_ashlsi3 (target, new_src, shift));
2354 for (i = 0; i < 32; i++)
2355 if (remainder & (1 << i))
2358 if (code == AND || (can_invert && num_bits_set > 16))
2359 remainder = (~remainder) & 0xffffffff;
2360 else if (code == PLUS && num_bits_set > 16)
2361 remainder = (-remainder) & 0xffffffff;
2368 /* Now try and find a way of doing the job in either two or three
2370 We start by looking for the largest block of zeros that are aligned on
2371 a 2-bit boundary, we then fill up the temps, wrapping around to the
2372 top of the word when we drop off the bottom.
2373 In the worst case this code should produce no more than four insns.
2374 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2375 best place to start. */
2377 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2383 int best_consecutive_zeros = 0;
2385 for (i = 0; i < 32; i += 2)
2387 int consecutive_zeros = 0;
2389 if (!(remainder & (3 << i)))
2391 while ((i < 32) && !(remainder & (3 << i)))
2393 consecutive_zeros += 2;
2396 if (consecutive_zeros > best_consecutive_zeros)
2398 best_consecutive_zeros = consecutive_zeros;
2399 best_start = i - consecutive_zeros;
2405 /* So long as it won't require any more insns to do so, it's
2406 desirable to emit a small constant (in bits 0...9) in the last
2407 insn. This way there is more chance that it can be combined with
2408 a later addressing insn to form a pre-indexed load or store
2409 operation. Consider:
2411 *((volatile int *)0xe0000100) = 1;
2412 *((volatile int *)0xe0000110) = 2;
2414 We want this to wind up as:
2418 str rB, [rA, #0x100]
2420 str rB, [rA, #0x110]
2422 rather than having to synthesize both large constants from scratch.
2424 Therefore, we calculate how many insns would be required to emit
2425 the constant starting from `best_start', and also starting from
2426 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2427 yield a shorter sequence, we may as well use zero. */
2429 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2430 && (count_insns_for_constant (remainder, 0) <=
2431 count_insns_for_constant (remainder, best_start)))
2435 /* Now start emitting the insns. */
2443 if (remainder & (3 << (i - 2)))
2448 temp1 = remainder & ((0x0ff << end)
2449 | ((i < end) ? (0xff >> (32 - end)) : 0));
2450 remainder &= ~temp1;
2454 rtx new_src, temp1_rtx;
2456 if (code == SET || code == MINUS)
2458 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2459 if (can_invert && code != MINUS)
2464 if (remainder && subtargets)
2465 new_src = gen_reg_rtx (mode);
2470 else if (can_negate)
2474 temp1 = trunc_int_for_mode (temp1, mode);
2475 temp1_rtx = GEN_INT (temp1);
2479 else if (code == MINUS)
2480 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2482 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2484 emit_constant_insn (cond,
2485 gen_rtx_SET (VOIDmode, new_src,
2495 else if (code == MINUS)
2504 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitary
2517 /* Canonicalize a comparison so that we are more likely to recognize it.
2518 This can be done for a few constant compares, where we can make the
2519 immediate value easier to load. */
2522 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2525 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2526 unsigned HOST_WIDE_INT maxval;
2527 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2538 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2540 *op1 = GEN_INT (i + 1);
2541 return code == GT ? GE : LT;
2548 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2550 *op1 = GEN_INT (i - 1);
2551 return code == GE ? GT : LE;
2557 if (i != ~((unsigned HOST_WIDE_INT) 0)
2558 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2560 *op1 = GEN_INT (i + 1);
2561 return code == GTU ? GEU : LTU;
2568 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2570 *op1 = GEN_INT (i - 1);
2571 return code == GEU ? GTU : LEU;
2583 /* Define how to find the value returned by a function. */
2586 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2588 enum machine_mode mode;
2589 int unsignedp ATTRIBUTE_UNUSED;
2590 rtx r ATTRIBUTE_UNUSED;
2592 mode = TYPE_MODE (type);
2593 /* Promote integer types. */
2594 if (INTEGRAL_TYPE_P (type))
2595 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2597 /* Promotes small structs returned in a register to full-word size
2598 for big-endian AAPCS. */
2599 if (arm_return_in_msb (type))
2601 HOST_WIDE_INT size = int_size_in_bytes (type);
2602 if (size % UNITS_PER_WORD != 0)
2604 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2605 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2609 return LIBCALL_VALUE(mode);
2612 /* Determine the amount of memory needed to store the possible return
2613 registers of an untyped call. */
2615 arm_apply_result_size (void)
2621 if (TARGET_HARD_FLOAT_ABI)
2625 if (TARGET_MAVERICK)
2628 if (TARGET_IWMMXT_ABI)
2635 /* Decide whether a type should be returned in memory (true)
2636 or in a register (false). This is called by the macro
2637 RETURN_IN_MEMORY. */
2639 arm_return_in_memory (tree type)
2643 if (!AGGREGATE_TYPE_P (type) &&
2644 (TREE_CODE (type) != VECTOR_TYPE) &&
2645 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2646 /* All simple types are returned in registers.
2647 For AAPCS, complex types are treated the same as aggregates. */
2650 size = int_size_in_bytes (type);
2652 if (arm_abi != ARM_ABI_APCS)
2654 /* ATPCS and later return aggregate types in memory only if they are
2655 larger than a word (or are variable size). */
2656 return (size < 0 || size > UNITS_PER_WORD);
2659 /* To maximize backwards compatibility with previous versions of gcc,
2660 return vectors up to 4 words in registers. */
2661 if (TREE_CODE (type) == VECTOR_TYPE)
2662 return (size < 0 || size > (4 * UNITS_PER_WORD));
2664 /* For the arm-wince targets we choose to be compatible with Microsoft's
2665 ARM and Thumb compilers, which always return aggregates in memory. */
2667 /* All structures/unions bigger than one word are returned in memory.
2668 Also catch the case where int_size_in_bytes returns -1. In this case
2669 the aggregate is either huge or of variable size, and in either case
2670 we will want to return it via memory and not in a register. */
2671 if (size < 0 || size > UNITS_PER_WORD)
2674 if (TREE_CODE (type) == RECORD_TYPE)
2678 /* For a struct the APCS says that we only return in a register
2679 if the type is 'integer like' and every addressable element
2680 has an offset of zero. For practical purposes this means
2681 that the structure can have at most one non bit-field element
2682 and that this element must be the first one in the structure. */
2684 /* Find the first field, ignoring non FIELD_DECL things which will
2685 have been created by C++. */
2686 for (field = TYPE_FIELDS (type);
2687 field && TREE_CODE (field) != FIELD_DECL;
2688 field = TREE_CHAIN (field))
2692 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2694 /* Check that the first field is valid for returning in a register. */
2696 /* ... Floats are not allowed */
2697 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2700 /* ... Aggregates that are not themselves valid for returning in
2701 a register are not allowed. */
2702 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2705 /* Now check the remaining fields, if any. Only bitfields are allowed,
2706 since they are not addressable. */
2707 for (field = TREE_CHAIN (field);
2709 field = TREE_CHAIN (field))
2711 if (TREE_CODE (field) != FIELD_DECL)
2714 if (!DECL_BIT_FIELD_TYPE (field))
2721 if (TREE_CODE (type) == UNION_TYPE)
2725 /* Unions can be returned in registers if every element is
2726 integral, or can be returned in an integer register. */
2727 for (field = TYPE_FIELDS (type);
2729 field = TREE_CHAIN (field))
2731 if (TREE_CODE (field) != FIELD_DECL)
2734 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2737 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2743 #endif /* not ARM_WINCE */
2745 /* Return all other types in memory. */
2749 /* Indicate whether or not words of a double are in big-endian order. */
2752 arm_float_words_big_endian (void)
2754 if (TARGET_MAVERICK)
2757 /* For FPA, float words are always big-endian. For VFP, floats words
2758 follow the memory system mode. */
2766 return (TARGET_BIG_END ? 1 : 0);
2771 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2772 for a call to a function whose data type is FNTYPE.
2773 For a library call, FNTYPE is NULL. */
2775 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2776 rtx libname ATTRIBUTE_UNUSED,
2777 tree fndecl ATTRIBUTE_UNUSED)
2779 /* On the ARM, the offset starts at 0. */
2781 pcum->iwmmxt_nregs = 0;
2782 pcum->can_split = true;
2784 pcum->call_cookie = CALL_NORMAL;
2786 if (TARGET_LONG_CALLS)
2787 pcum->call_cookie = CALL_LONG;
2789 /* Check for long call/short call attributes. The attributes
2790 override any command line option. */
2793 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2794 pcum->call_cookie = CALL_SHORT;
2795 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2796 pcum->call_cookie = CALL_LONG;
2799 /* Varargs vectors are treated the same as long long.
2800 named_count avoids having to change the way arm handles 'named' */
2801 pcum->named_count = 0;
2804 if (TARGET_REALLY_IWMMXT && fntype)
2808 for (fn_arg = TYPE_ARG_TYPES (fntype);
2810 fn_arg = TREE_CHAIN (fn_arg))
2811 pcum->named_count += 1;
2813 if (! pcum->named_count)
2814 pcum->named_count = INT_MAX;
2819 /* Return true if mode/type need doubleword alignment. */
2821 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2823 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2824 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2828 /* Determine where to put an argument to a function.
2829 Value is zero to push the argument on the stack,
2830 or a hard register in which to store the argument.
2832 MODE is the argument's machine mode.
2833 TYPE is the data type of the argument (as a tree).
2834 This is null for libcalls where that information may
2836 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2837 the preceding args and about the function being called.
2838 NAMED is nonzero if this argument is a named parameter
2839 (otherwise it is an extra parameter matching an ellipsis). */
2842 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2843 tree type, int named)
2847 /* Varargs vectors are treated the same as long long.
2848 named_count avoids having to change the way arm handles 'named' */
2849 if (TARGET_IWMMXT_ABI
2850 && arm_vector_mode_supported_p (mode)
2851 && pcum->named_count > pcum->nargs + 1)
2853 if (pcum->iwmmxt_nregs <= 9)
2854 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2857 pcum->can_split = false;
2862 /* Put doubleword aligned quantities in even register pairs. */
2864 && ARM_DOUBLEWORD_ALIGN
2865 && arm_needs_doubleword_align (mode, type))
2868 if (mode == VOIDmode)
2869 /* Compute operand 2 of the call insn. */
2870 return GEN_INT (pcum->call_cookie);
2872 /* Only allow splitting an arg between regs and memory if all preceding
2873 args were allocated to regs. For args passed by reference we only count
2874 the reference pointer. */
2875 if (pcum->can_split)
2878 nregs = ARM_NUM_REGS2 (mode, type);
2880 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2883 return gen_rtx_REG (mode, pcum->nregs);
2887 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2888 tree type, bool named ATTRIBUTE_UNUSED)
2890 int nregs = pcum->nregs;
2892 if (arm_vector_mode_supported_p (mode))
2895 if (NUM_ARG_REGS > nregs
2896 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2898 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2903 /* Variable sized types are passed by reference. This is a GCC
2904 extension to the ARM ABI. */
2907 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2908 enum machine_mode mode ATTRIBUTE_UNUSED,
2909 tree type, bool named ATTRIBUTE_UNUSED)
2911 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2914 /* Encode the current state of the #pragma [no_]long_calls. */
2917 OFF, /* No #pragma [no_]long_calls is in effect. */
2918 LONG, /* #pragma long_calls is in effect. */
2919 SHORT /* #pragma no_long_calls is in effect. */
2922 static arm_pragma_enum arm_pragma_long_calls = OFF;
2925 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2927 arm_pragma_long_calls = LONG;
2931 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2933 arm_pragma_long_calls = SHORT;
2937 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2939 arm_pragma_long_calls = OFF;
2942 /* Table of machine attributes. */
2943 const struct attribute_spec arm_attribute_table[] =
2945 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2946 /* Function calls made to this symbol must be done indirectly, because
2947 it may lie outside of the 26 bit addressing range of a normal function
2949 { "long_call", 0, 0, false, true, true, NULL },
2950 /* Whereas these functions are always known to reside within the 26 bit
2951 addressing range. */
2952 { "short_call", 0, 0, false, true, true, NULL },
2953 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2954 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2955 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2956 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2958 /* ARM/PE has three new attributes:
2960 dllexport - for exporting a function/variable that will live in a dll
2961 dllimport - for importing a function/variable from a dll
2963 Microsoft allows multiple declspecs in one __declspec, separating
2964 them with spaces. We do NOT support this. Instead, use __declspec
2967 { "dllimport", 0, 0, true, false, false, NULL },
2968 { "dllexport", 0, 0, true, false, false, NULL },
2969 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2970 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2971 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2972 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2973 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2975 { NULL, 0, 0, false, false, false, NULL }
2978 /* Handle an attribute requiring a FUNCTION_DECL;
2979 arguments as in struct attribute_spec.handler. */
2981 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2982 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2984 if (TREE_CODE (*node) != FUNCTION_DECL)
2986 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2987 IDENTIFIER_POINTER (name));
2988 *no_add_attrs = true;
2994 /* Handle an "interrupt" or "isr" attribute;
2995 arguments as in struct attribute_spec.handler. */
2997 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3002 if (TREE_CODE (*node) != FUNCTION_DECL)
3004 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3005 IDENTIFIER_POINTER (name));
3006 *no_add_attrs = true;
3008 /* FIXME: the argument if any is checked for type attributes;
3009 should it be checked for decl ones? */
3013 if (TREE_CODE (*node) == FUNCTION_TYPE
3014 || TREE_CODE (*node) == METHOD_TYPE)
3016 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3018 warning (OPT_Wattributes, "%qs attribute ignored",
3019 IDENTIFIER_POINTER (name));
3020 *no_add_attrs = true;
3023 else if (TREE_CODE (*node) == POINTER_TYPE
3024 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3025 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3026 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3028 *node = build_variant_type_copy (*node);
3029 TREE_TYPE (*node) = build_type_attribute_variant
3031 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3032 *no_add_attrs = true;
3036 /* Possibly pass this attribute on from the type to a decl. */
3037 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3038 | (int) ATTR_FLAG_FUNCTION_NEXT
3039 | (int) ATTR_FLAG_ARRAY_NEXT))
3041 *no_add_attrs = true;
3042 return tree_cons (name, args, NULL_TREE);
3046 warning (OPT_Wattributes, "%qs attribute ignored",
3047 IDENTIFIER_POINTER (name));
3055 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3056 /* Handle the "notshared" attribute. This attribute is another way of
3057 requesting hidden visibility. ARM's compiler supports
3058 "__declspec(notshared)"; we support the same thing via an
3062 arm_handle_notshared_attribute (tree *node,
3063 tree name ATTRIBUTE_UNUSED,
3064 tree args ATTRIBUTE_UNUSED,
3065 int flags ATTRIBUTE_UNUSED,
3068 tree decl = TYPE_NAME (*node);
3072 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3073 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3074 *no_add_attrs = false;
3080 /* Return 0 if the attributes for two types are incompatible, 1 if they
3081 are compatible, and 2 if they are nearly compatible (which causes a
3082 warning to be generated). */
3084 arm_comp_type_attributes (tree type1, tree type2)
3088 /* Check for mismatch of non-default calling convention. */
3089 if (TREE_CODE (type1) != FUNCTION_TYPE)
3092 /* Check for mismatched call attributes. */
3093 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3094 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3095 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3096 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3098 /* Only bother to check if an attribute is defined. */
3099 if (l1 | l2 | s1 | s2)
3101 /* If one type has an attribute, the other must have the same attribute. */
3102 if ((l1 != l2) || (s1 != s2))
3105 /* Disallow mixed attributes. */
3106 if ((l1 & s2) || (l2 & s1))
3110 /* Check for mismatched ISR attribute. */
3111 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3113 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3114 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3116 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3123 /* Encode long_call or short_call attribute by prefixing
3124 symbol name in DECL with a special character FLAG. */
3126 arm_encode_call_attribute (tree decl, int flag)
3128 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3129 int len = strlen (str);
3132 /* Do not allow weak functions to be treated as short call. */
3133 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
3136 newstr = alloca (len + 2);
3138 strcpy (newstr + 1, str);
3140 newstr = (char *) ggc_alloc_string (newstr, len + 1);
3141 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3144 /* Assigns default attributes to newly defined type. This is used to
3145 set short_call/long_call attributes for function types of
3146 functions defined inside corresponding #pragma scopes. */
3148 arm_set_default_type_attributes (tree type)
3150 /* Add __attribute__ ((long_call)) to all functions, when
3151 inside #pragma long_calls or __attribute__ ((short_call)),
3152 when inside #pragma no_long_calls. */
3153 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3155 tree type_attr_list, attr_name;
3156 type_attr_list = TYPE_ATTRIBUTES (type);
3158 if (arm_pragma_long_calls == LONG)
3159 attr_name = get_identifier ("long_call");
3160 else if (arm_pragma_long_calls == SHORT)
3161 attr_name = get_identifier ("short_call");
3165 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3166 TYPE_ATTRIBUTES (type) = type_attr_list;
3170 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3171 defined within the current compilation unit. If this cannot be
3172 determined, then 0 is returned. */
3174 current_file_function_operand (rtx sym_ref)
3176 /* This is a bit of a fib. A function will have a short call flag
3177 applied to its name if it has the short call attribute, or it has
3178 already been defined within the current compilation unit. */
3179 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
3182 /* The current function is always defined within the current compilation
3183 unit. If it s a weak definition however, then this may not be the real
3184 definition of the function, and so we have to say no. */
3185 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3186 && !DECL_WEAK (current_function_decl))
3189 /* We cannot make the determination - default to returning 0. */
3193 /* Return nonzero if a 32 bit "long_call" should be generated for
3194 this call. We generate a long_call if the function:
3196 a. has an __attribute__((long call))
3197 or b. is within the scope of a #pragma long_calls
3198 or c. the -mlong-calls command line switch has been specified
3200 1. -ffunction-sections is in effect
3201 or 2. the current function has __attribute__ ((section))
3202 or 3. the target function has __attribute__ ((section))
3204 However we do not generate a long call if the function:
3206 d. has an __attribute__ ((short_call))
3207 or e. is inside the scope of a #pragma no_long_calls
3208 or f. is defined within the current compilation unit.
3210 This function will be called by C fragments contained in the machine
3211 description file. SYM_REF and CALL_COOKIE correspond to the matched
3212 rtl operands. CALL_SYMBOL is used to distinguish between
3213 two different callers of the function. It is set to 1 in the
3214 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3215 and "call_value" patterns. This is because of the difference in the
3216 SYM_REFs passed by these patterns. */
3218 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3222 if (GET_CODE (sym_ref) != MEM)
3225 sym_ref = XEXP (sym_ref, 0);
3228 if (GET_CODE (sym_ref) != SYMBOL_REF)
3231 if (call_cookie & CALL_SHORT)
3234 if (TARGET_LONG_CALLS)
3236 if (flag_function_sections
3237 || DECL_SECTION_NAME (current_function_decl))
3238 /* c.3 is handled by the definition of the
3239 ARM_DECLARE_FUNCTION_SIZE macro. */
3243 if (current_file_function_operand (sym_ref))
3246 return (call_cookie & CALL_LONG)
3247 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3248 || TARGET_LONG_CALLS;
3251 /* Return nonzero if it is ok to make a tail-call to DECL. */
3253 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3255 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3256 unsigned long func_type;
3258 if (cfun->machine->sibcall_blocked)
3261 /* Never tailcall something for which we have no decl, or if we
3262 are in Thumb mode. */
3263 if (decl == NULL || TARGET_THUMB)
3266 /* Get the calling method. */
3267 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3268 call_type = CALL_SHORT;
3269 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3270 call_type = CALL_LONG;
3272 /* Cannot tail-call to long calls, since these are out of range of
3273 a branch instruction. However, if not compiling PIC, we know
3274 we can reach the symbol if it is in this compilation unit. */
3275 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3278 /* If we are interworking and the function is not declared static
3279 then we can't tail-call it unless we know that it exists in this
3280 compilation unit (since it might be a Thumb routine). */
3281 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3284 func_type = arm_current_func_type ();
3285 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3286 if (IS_INTERRUPT (func_type))
3289 /* Never tailcall if function may be called with a misaligned SP. */
3290 if (IS_STACKALIGN (func_type))
3293 /* Everything else is ok. */
3298 /* Addressing mode support functions. */
3300 /* Return nonzero if X is a legitimate immediate operand when compiling
3301 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3303 legitimate_pic_operand_p (rtx x)
3305 if (GET_CODE (x) == SYMBOL_REF
3306 || (GET_CODE (x) == CONST
3307 && GET_CODE (XEXP (x, 0)) == PLUS
3308 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3315 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3317 if (GET_CODE (orig) == SYMBOL_REF
3318 || GET_CODE (orig) == LABEL_REF)
3320 #ifndef AOF_ASSEMBLER
3321 rtx pic_ref, address;
3326 /* If this function doesn't have a pic register, create one now.
3327 A lot of the logic here is made obscure by the fact that this
3328 routine gets called as part of the rtx cost estimation
3329 process. We don't want those calls to affect any assumptions
3330 about the real function; and further, we can't call
3331 entry_of_function() until we start the real expansion
3333 if (!current_function_uses_pic_offset_table)
3335 gcc_assert (!no_new_pseudos);
3336 if (arm_pic_register != INVALID_REGNUM)
3338 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3340 /* Play games to avoid marking the function as needing pic
3341 if we are being called as part of the cost-estimation
3343 if (current_ir_type () != IR_GIMPLE)
3344 current_function_uses_pic_offset_table = 1;
3350 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3352 /* Play games to avoid marking the function as needing pic
3353 if we are being called as part of the cost-estimation
3355 if (current_ir_type () != IR_GIMPLE)
3357 current_function_uses_pic_offset_table = 1;
3360 arm_load_pic_register (0UL);
3364 emit_insn_after (seq, entry_of_function ());
3371 gcc_assert (!no_new_pseudos);
3372 reg = gen_reg_rtx (Pmode);
3377 #ifdef AOF_ASSEMBLER
3378 /* The AOF assembler can generate relocations for these directly, and
3379 understands that the PIC register has to be added into the offset. */
3380 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3383 address = gen_reg_rtx (Pmode);
3388 emit_insn (gen_pic_load_addr_arm (address, orig));
3389 else if (TARGET_THUMB2)
3390 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3391 else /* TARGET_THUMB1 */
3392 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3394 if ((GET_CODE (orig) == LABEL_REF
3395 || (GET_CODE (orig) == SYMBOL_REF &&
3396 SYMBOL_REF_LOCAL_P (orig)))
3398 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3401 pic_ref = gen_const_mem (Pmode,
3402 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3406 insn = emit_move_insn (reg, pic_ref);
3408 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3410 set_unique_reg_note (insn, REG_EQUAL, orig);
3414 else if (GET_CODE (orig) == CONST)
3418 if (GET_CODE (XEXP (orig, 0)) == PLUS
3419 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3422 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3423 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3428 gcc_assert (!no_new_pseudos);
3429 reg = gen_reg_rtx (Pmode);
3432 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3434 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3435 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3436 base == reg ? 0 : reg);
3438 if (GET_CODE (offset) == CONST_INT)
3440 /* The base register doesn't really matter, we only want to
3441 test the index for the appropriate mode. */
3442 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3444 gcc_assert (!no_new_pseudos);
3445 offset = force_reg (Pmode, offset);
3448 if (GET_CODE (offset) == CONST_INT)
3449 return plus_constant (base, INTVAL (offset));
3452 if (GET_MODE_SIZE (mode) > 4
3453 && (GET_MODE_CLASS (mode) == MODE_INT
3454 || TARGET_SOFT_FLOAT))
3456 emit_insn (gen_addsi3 (reg, base, offset));
3460 return gen_rtx_PLUS (Pmode, base, offset);
3467 /* Find a spare register to use during the prolog of a function. */
3470 thumb_find_work_register (unsigned long pushed_regs_mask)
3474 /* Check the argument registers first as these are call-used. The
3475 register allocation order means that sometimes r3 might be used
3476 but earlier argument registers might not, so check them all. */
3477 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3478 if (!regs_ever_live[reg])
3481 /* Before going on to check the call-saved registers we can try a couple
3482 more ways of deducing that r3 is available. The first is when we are
3483 pushing anonymous arguments onto the stack and we have less than 4
3484 registers worth of fixed arguments(*). In this case r3 will be part of
3485 the variable argument list and so we can be sure that it will be
3486 pushed right at the start of the function. Hence it will be available
3487 for the rest of the prologue.
3488 (*): ie current_function_pretend_args_size is greater than 0. */
3489 if (cfun->machine->uses_anonymous_args
3490 && current_function_pretend_args_size > 0)
3491 return LAST_ARG_REGNUM;
3493 /* The other case is when we have fixed arguments but less than 4 registers
3494 worth. In this case r3 might be used in the body of the function, but
3495 it is not being used to convey an argument into the function. In theory
3496 we could just check current_function_args_size to see how many bytes are
3497 being passed in argument registers, but it seems that it is unreliable.
3498 Sometimes it will have the value 0 when in fact arguments are being
3499 passed. (See testcase execute/20021111-1.c for an example). So we also
3500 check the args_info.nregs field as well. The problem with this field is
3501 that it makes no allowances for arguments that are passed to the
3502 function but which are not used. Hence we could miss an opportunity
3503 when a function has an unused argument in r3. But it is better to be
3504 safe than to be sorry. */
3505 if (! cfun->machine->uses_anonymous_args
3506 && current_function_args_size >= 0
3507 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3508 && cfun->args_info.nregs < 4)
3509 return LAST_ARG_REGNUM;
3511 /* Otherwise look for a call-saved register that is going to be pushed. */
3512 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3513 if (pushed_regs_mask & (1 << reg))
3518 /* Thumb-2 can use high regs. */
3519 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3520 if (pushed_regs_mask & (1 << reg))
3523 /* Something went wrong - thumb_compute_save_reg_mask()
3524 should have arranged for a suitable register to be pushed. */
3528 static GTY(()) int pic_labelno;
3530 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3534 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3536 #ifndef AOF_ASSEMBLER
3537 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx;
3538 rtx global_offset_table;
3540 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3543 gcc_assert (flag_pic);
3545 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3546 in the code stream. */
3548 labelno = GEN_INT (pic_labelno++);
3549 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3550 l1 = gen_rtx_CONST (VOIDmode, l1);
3552 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3553 /* On the ARM the PC register contains 'dot + 8' at the time of the
3554 addition, on the Thumb it is 'dot + 4'. */
3555 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3557 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3558 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3560 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3562 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3566 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx));
3567 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg,
3568 cfun->machine->pic_reg, labelno));
3570 else if (TARGET_THUMB2)
3572 /* Thumb-2 only allows very limited access to the PC. Calculate the
3573 address in a temporary register. */
3574 if (arm_pic_register != INVALID_REGNUM)
3576 pic_tmp = gen_rtx_REG (SImode,
3577 thumb_find_work_register (saved_regs));
3581 gcc_assert (!no_new_pseudos);
3582 pic_tmp = gen_reg_rtx (Pmode);
3585 emit_insn (gen_pic_load_addr_thumb2 (cfun->machine->pic_reg, pic_rtx));
3586 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3587 emit_insn (gen_addsi3(cfun->machine->pic_reg, cfun->machine->pic_reg,
3590 else /* TARGET_THUMB1 */
3592 if (arm_pic_register != INVALID_REGNUM
3593 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM)
3595 /* We will have pushed the pic register, so we should always be
3596 able to find a work register. */
3597 pic_tmp = gen_rtx_REG (SImode,
3598 thumb_find_work_register (saved_regs));
3599 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3600 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3603 emit_insn (gen_pic_load_addr_thumb1 (cfun->machine->pic_reg, pic_rtx));
3604 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg,
3605 cfun->machine->pic_reg, labelno));
3608 /* Need to emit this whether or not we obey regdecls,
3609 since setjmp/longjmp can cause life info to screw up. */
3610 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg));
3611 #endif /* AOF_ASSEMBLER */
3615 /* Return nonzero if X is valid as an ARM state addressing register. */
3617 arm_address_register_rtx_p (rtx x, int strict_p)
3621 if (GET_CODE (x) != REG)
3627 return ARM_REGNO_OK_FOR_BASE_P (regno);
3629 return (regno <= LAST_ARM_REGNUM
3630 || regno >= FIRST_PSEUDO_REGISTER
3631 || regno == FRAME_POINTER_REGNUM
3632 || regno == ARG_POINTER_REGNUM);
3635 /* Return TRUE if this rtx is the difference of a symbol and a label,
3636 and will reduce to a PC-relative relocation in the object file.
3637 Expressions like this can be left alone when generating PIC, rather
3638 than forced through the GOT. */
3640 pcrel_constant_p (rtx x)
3642 if (GET_CODE (x) == MINUS)
3643 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3648 /* Return nonzero if X is a valid ARM state address operand. */
3650 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3654 enum rtx_code code = GET_CODE (x);
3656 if (arm_address_register_rtx_p (x, strict_p))
3659 use_ldrd = (TARGET_LDRD
3661 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3663 if (code == POST_INC || code == PRE_DEC
3664 || ((code == PRE_INC || code == POST_DEC)
3665 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3666 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3668 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3669 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3670 && GET_CODE (XEXP (x, 1)) == PLUS
3671 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3673 rtx addend = XEXP (XEXP (x, 1), 1);
3675 /* Don't allow ldrd post increment by register because it's hard
3676 to fixup invalid register choices. */
3678 && GET_CODE (x) == POST_MODIFY
3679 && GET_CODE (addend) == REG)
3682 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3683 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3686 /* After reload constants split into minipools will have addresses
3687 from a LABEL_REF. */
3688 else if (reload_completed
3689 && (code == LABEL_REF
3691 && GET_CODE (XEXP (x, 0)) == PLUS
3692 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3693 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3696 else if (mode == TImode)
3699 else if (code == PLUS)
3701 rtx xop0 = XEXP (x, 0);
3702 rtx xop1 = XEXP (x, 1);
3704 return ((arm_address_register_rtx_p (xop0, strict_p)
3705 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3706 || (arm_address_register_rtx_p (xop1, strict_p)
3707 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3711 /* Reload currently can't handle MINUS, so disable this for now */
3712 else if (GET_CODE (x) == MINUS)
3714 rtx xop0 = XEXP (x, 0);
3715 rtx xop1 = XEXP (x, 1);
3717 return (arm_address_register_rtx_p (xop0, strict_p)
3718 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3722 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3723 && code == SYMBOL_REF
3724 && CONSTANT_POOL_ADDRESS_P (x)
3726 && symbol_mentioned_p (get_pool_constant (x))
3727 && ! pcrel_constant_p (get_pool_constant (x))))
3733 /* Return nonzero if X is a valid Thumb-2 address operand. */
3735 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3738 enum rtx_code code = GET_CODE (x);
3740 if (arm_address_register_rtx_p (x, strict_p))
3743 use_ldrd = (TARGET_LDRD
3745 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3747 if (code == POST_INC || code == PRE_DEC
3748 || ((code == PRE_INC || code == POST_DEC)
3749 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3750 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3752 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3753 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3754 && GET_CODE (XEXP (x, 1)) == PLUS
3755 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3757 /* Thumb-2 only has autoincrement by constant. */
3758 rtx addend = XEXP (XEXP (x, 1), 1);
3759 HOST_WIDE_INT offset;
3761 if (GET_CODE (addend) != CONST_INT)
3764 offset = INTVAL(addend);
3765 if (GET_MODE_SIZE (mode) <= 4)
3766 return (offset > -256 && offset < 256);
3768 return (use_ldrd && offset > -1024 && offset < 1024
3769 && (offset & 3) == 0);
3772 /* After reload constants split into minipools will have addresses
3773 from a LABEL_REF. */
3774 else if (reload_completed
3775 && (code == LABEL_REF
3777 && GET_CODE (XEXP (x, 0)) == PLUS
3778 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3779 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3782 else if (mode == TImode)
3785 else if (code == PLUS)
3787 rtx xop0 = XEXP (x, 0);
3788 rtx xop1 = XEXP (x, 1);
3790 return ((arm_address_register_rtx_p (xop0, strict_p)
3791 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3792 || (arm_address_register_rtx_p (xop1, strict_p)
3793 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3796 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3797 && code == SYMBOL_REF
3798 && CONSTANT_POOL_ADDRESS_P (x)
3800 && symbol_mentioned_p (get_pool_constant (x))
3801 && ! pcrel_constant_p (get_pool_constant (x))))
3807 /* Return nonzero if INDEX is valid for an address index operand in
3810 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3813 HOST_WIDE_INT range;
3814 enum rtx_code code = GET_CODE (index);
3816 /* Standard coprocessor addressing modes. */
3817 if (TARGET_HARD_FLOAT
3818 && (TARGET_FPA || TARGET_MAVERICK)
3819 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3820 || (TARGET_MAVERICK && mode == DImode)))
3821 return (code == CONST_INT && INTVAL (index) < 1024
3822 && INTVAL (index) > -1024
3823 && (INTVAL (index) & 3) == 0);
3825 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3826 return (code == CONST_INT
3827 && INTVAL (index) < 1024
3828 && INTVAL (index) > -1024
3829 && (INTVAL (index) & 3) == 0);
3831 if (arm_address_register_rtx_p (index, strict_p)
3832 && (GET_MODE_SIZE (mode) <= 4))
3835 if (mode == DImode || mode == DFmode)
3837 if (code == CONST_INT)
3839 HOST_WIDE_INT val = INTVAL (index);
3842 return val > -256 && val < 256;
3844 return val > -4096 && val < 4092;
3847 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3850 if (GET_MODE_SIZE (mode) <= 4
3853 || (mode == QImode && outer == SIGN_EXTEND))))
3857 rtx xiop0 = XEXP (index, 0);
3858 rtx xiop1 = XEXP (index, 1);
3860 return ((arm_address_register_rtx_p (xiop0, strict_p)
3861 && power_of_two_operand (xiop1, SImode))
3862 || (arm_address_register_rtx_p (xiop1, strict_p)
3863 && power_of_two_operand (xiop0, SImode)));
3865 else if (code == LSHIFTRT || code == ASHIFTRT
3866 || code == ASHIFT || code == ROTATERT)
3868 rtx op = XEXP (index, 1);
3870 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3871 && GET_CODE (op) == CONST_INT
3873 && INTVAL (op) <= 31);
3877 /* For ARM v4 we may be doing a sign-extend operation during the
3881 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3887 range = (mode == HImode) ? 4095 : 4096;
3889 return (code == CONST_INT
3890 && INTVAL (index) < range
3891 && INTVAL (index) > -range);
3894 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3895 index operand. i.e. 1, 2, 4 or 8. */
3897 thumb2_index_mul_operand (rtx op)
3901 if (GET_CODE(op) != CONST_INT)
3905 return (val == 1 || val == 2 || val == 4 || val == 8);
3908 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3910 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
3912 enum rtx_code code = GET_CODE (index);
3914 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3915 /* Standard coprocessor addressing modes. */
3916 if (TARGET_HARD_FLOAT
3917 && (TARGET_FPA || TARGET_MAVERICK)
3918 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3919 || (TARGET_MAVERICK && mode == DImode)))
3920 return (code == CONST_INT && INTVAL (index) < 1024
3921 && INTVAL (index) > -1024
3922 && (INTVAL (index) & 3) == 0);
3924 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3925 return (code == CONST_INT
3926 && INTVAL (index) < 1024
3927 && INTVAL (index) > -1024
3928 && (INTVAL (index) & 3) == 0);
3930 if (arm_address_register_rtx_p (index, strict_p)
3931 && (GET_MODE_SIZE (mode) <= 4))
3934 if (mode == DImode || mode == DFmode)
3936 HOST_WIDE_INT val = INTVAL (index);
3937 /* ??? Can we assume ldrd for thumb2? */
3938 /* Thumb-2 ldrd only has reg+const addressing modes. */
3939 if (code != CONST_INT)
3942 /* ldrd supports offsets of +-1020.
3943 However the ldr fallback does not. */
3944 return val > -256 && val < 256 && (val & 3) == 0;
3949 rtx xiop0 = XEXP (index, 0);
3950 rtx xiop1 = XEXP (index, 1);
3952 return ((arm_address_register_rtx_p (xiop0, strict_p)
3953 && thumb2_index_mul_operand (xiop1))
3954 || (arm_address_register_rtx_p (xiop1, strict_p)
3955 && thumb2_index_mul_operand (xiop0)));
3957 else if (code == ASHIFT)
3959 rtx op = XEXP (index, 1);
3961 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3962 && GET_CODE (op) == CONST_INT
3964 && INTVAL (op) <= 3);
3967 return (code == CONST_INT
3968 && INTVAL (index) < 4096
3969 && INTVAL (index) > -256);
3972 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3974 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3978 if (GET_CODE (x) != REG)
3984 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3986 return (regno <= LAST_LO_REGNUM
3987 || regno > LAST_VIRTUAL_REGISTER
3988 || regno == FRAME_POINTER_REGNUM
3989 || (GET_MODE_SIZE (mode) >= 4
3990 && (regno == STACK_POINTER_REGNUM
3991 || regno >= FIRST_PSEUDO_REGISTER
3992 || x == hard_frame_pointer_rtx
3993 || x == arg_pointer_rtx)));
3996 /* Return nonzero if x is a legitimate index register. This is the case
3997 for any base register that can access a QImode object. */
3999 thumb1_index_register_rtx_p (rtx x, int strict_p)
4001 return thumb1_base_register_rtx_p (x, QImode, strict_p);
4004 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4006 The AP may be eliminated to either the SP or the FP, so we use the
4007 least common denominator, e.g. SImode, and offsets from 0 to 64.
4009 ??? Verify whether the above is the right approach.
4011 ??? Also, the FP may be eliminated to the SP, so perhaps that
4012 needs special handling also.
4014 ??? Look at how the mips16 port solves this problem. It probably uses
4015 better ways to solve some of these problems.
4017 Although it is not incorrect, we don't accept QImode and HImode
4018 addresses based on the frame pointer or arg pointer until the
4019 reload pass starts. This is so that eliminating such addresses
4020 into stack based ones won't produce impossible code. */
4022 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
4024 /* ??? Not clear if this is right. Experiment. */
4025 if (GET_MODE_SIZE (mode) < 4
4026 && !(reload_in_progress || reload_completed)
4027 && (reg_mentioned_p (frame_pointer_rtx, x)
4028 || reg_mentioned_p (arg_pointer_rtx, x)
4029 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4030 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4031 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4032 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4035 /* Accept any base register. SP only in SImode or larger. */
4036 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
4039 /* This is PC relative data before arm_reorg runs. */
4040 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4041 && GET_CODE (x) == SYMBOL_REF
4042 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
4045 /* This is PC relative data after arm_reorg runs. */
4046 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4047 && (GET_CODE (x) == LABEL_REF
4048 || (GET_CODE (x) == CONST
4049 && GET_CODE (XEXP (x, 0)) == PLUS
4050 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4051 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4054 /* Post-inc indexing only supported for SImode and larger. */
4055 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4056 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4059 else if (GET_CODE (x) == PLUS)
4061 /* REG+REG address can be any two index registers. */
4062 /* We disallow FRAME+REG addressing since we know that FRAME
4063 will be replaced with STACK, and SP relative addressing only
4064 permits SP+OFFSET. */
4065 if (GET_MODE_SIZE (mode) <= 4
4066 && XEXP (x, 0) != frame_pointer_rtx
4067 && XEXP (x, 1) != frame_pointer_rtx
4068 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4069 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4072 /* REG+const has 5-7 bit offset for non-SP registers. */
4073 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4074 || XEXP (x, 0) == arg_pointer_rtx)
4075 && GET_CODE (XEXP (x, 1)) == CONST_INT
4076 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4079 /* REG+const has 10 bit offset for SP, but only SImode and
4080 larger is supported. */
4081 /* ??? Should probably check for DI/DFmode overflow here
4082 just like GO_IF_LEGITIMATE_OFFSET does. */
4083 else if (GET_CODE (XEXP (x, 0)) == REG
4084 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4085 && GET_MODE_SIZE (mode) >= 4
4086 && GET_CODE (XEXP (x, 1)) == CONST_INT
4087 && INTVAL (XEXP (x, 1)) >= 0
4088 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4089 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4092 else if (GET_CODE (XEXP (x, 0)) == REG
4093 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4094 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4095 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4096 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4097 && GET_MODE_SIZE (mode) >= 4
4098 && GET_CODE (XEXP (x, 1)) == CONST_INT
4099 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4103 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4104 && GET_MODE_SIZE (mode) == 4
4105 && GET_CODE (x) == SYMBOL_REF
4106 && CONSTANT_POOL_ADDRESS_P (x)
4108 && symbol_mentioned_p (get_pool_constant (x))
4109 && ! pcrel_constant_p (get_pool_constant (x))))
4115 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4116 instruction of mode MODE. */
4118 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4120 switch (GET_MODE_SIZE (mode))
4123 return val >= 0 && val < 32;
4126 return val >= 0 && val < 64 && (val & 1) == 0;
4130 && (val + GET_MODE_SIZE (mode)) <= 128
4135 /* Build the SYMBOL_REF for __tls_get_addr. */
4137 static GTY(()) rtx tls_get_addr_libfunc;
4140 get_tls_get_addr (void)
4142 if (!tls_get_addr_libfunc)
4143 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4144 return tls_get_addr_libfunc;
4148 arm_load_tp (rtx target)
4151 target = gen_reg_rtx (SImode);
4155 /* Can return in any reg. */
4156 emit_insn (gen_load_tp_hard (target));
4160 /* Always returned in r0. Immediately copy the result into a pseudo,
4161 otherwise other uses of r0 (e.g. setting up function arguments) may
4162 clobber the value. */
4166 emit_insn (gen_load_tp_soft ());
4168 tmp = gen_rtx_REG (SImode, 0);
4169 emit_move_insn (target, tmp);
4175 load_tls_operand (rtx x, rtx reg)
4179 if (reg == NULL_RTX)
4180 reg = gen_reg_rtx (SImode);
4182 tmp = gen_rtx_CONST (SImode, x);
4184 emit_move_insn (reg, tmp);
4190 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4192 rtx insns, label, labelno, sum;
4196 labelno = GEN_INT (pic_labelno++);
4197 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4198 label = gen_rtx_CONST (VOIDmode, label);
4200 sum = gen_rtx_UNSPEC (Pmode,
4201 gen_rtvec (4, x, GEN_INT (reloc), label,
4202 GEN_INT (TARGET_ARM ? 8 : 4)),
4204 reg = load_tls_operand (sum, reg);
4207 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4208 else if (TARGET_THUMB2)
4211 /* Thumb-2 only allows very limited access to the PC. Calculate
4212 the address in a temporary register. */
4213 tmp = gen_reg_rtx (SImode);
4214 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4215 emit_insn (gen_addsi3(reg, reg, tmp));
4217 else /* TARGET_THUMB1 */
4218 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4220 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4221 Pmode, 1, reg, Pmode);
4223 insns = get_insns ();
4230 legitimize_tls_address (rtx x, rtx reg)
4232 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4233 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4237 case TLS_MODEL_GLOBAL_DYNAMIC:
4238 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4239 dest = gen_reg_rtx (Pmode);
4240 emit_libcall_block (insns, dest, ret, x);
4243 case TLS_MODEL_LOCAL_DYNAMIC:
4244 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4246 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4247 share the LDM result with other LD model accesses. */
4248 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4250 dest = gen_reg_rtx (Pmode);
4251 emit_libcall_block (insns, dest, ret, eqv);
4253 /* Load the addend. */
4254 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4256 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4257 return gen_rtx_PLUS (Pmode, dest, addend);
4259 case TLS_MODEL_INITIAL_EXEC:
4260 labelno = GEN_INT (pic_labelno++);
4261 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4262 label = gen_rtx_CONST (VOIDmode, label);
4263 sum = gen_rtx_UNSPEC (Pmode,
4264 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4265 GEN_INT (TARGET_ARM ? 8 : 4)),
4267 reg = load_tls_operand (sum, reg);
4270 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4271 else if (TARGET_THUMB2)
4274 /* Thumb-2 only allows very limited access to the PC. Calculate
4275 the address in a temporary register. */
4276 tmp = gen_reg_rtx (SImode);
4277 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4278 emit_insn (gen_addsi3(reg, reg, tmp));
4279 emit_move_insn (reg, gen_const_mem (SImode, reg));
4283 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4284 emit_move_insn (reg, gen_const_mem (SImode, reg));
4287 tp = arm_load_tp (NULL_RTX);
4289 return gen_rtx_PLUS (Pmode, tp, reg);
4291 case TLS_MODEL_LOCAL_EXEC:
4292 tp = arm_load_tp (NULL_RTX);
4294 reg = gen_rtx_UNSPEC (Pmode,
4295 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4297 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4299 return gen_rtx_PLUS (Pmode, tp, reg);
4306 /* Try machine-dependent ways of modifying an illegitimate address
4307 to be legitimate. If we find one, return the new, valid address. */
4309 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4311 if (arm_tls_symbol_p (x))
4312 return legitimize_tls_address (x, NULL_RTX);
4314 if (GET_CODE (x) == PLUS)
4316 rtx xop0 = XEXP (x, 0);
4317 rtx xop1 = XEXP (x, 1);
4319 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4320 xop0 = force_reg (SImode, xop0);
4322 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4323 xop1 = force_reg (SImode, xop1);
4325 if (ARM_BASE_REGISTER_RTX_P (xop0)
4326 && GET_CODE (xop1) == CONST_INT)
4328 HOST_WIDE_INT n, low_n;
4332 /* VFP addressing modes actually allow greater offsets, but for
4333 now we just stick with the lowest common denominator. */
4335 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4347 low_n = ((mode) == TImode ? 0
4348 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4352 base_reg = gen_reg_rtx (SImode);
4353 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4354 emit_move_insn (base_reg, val);
4355 x = plus_constant (base_reg, low_n);
4357 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4358 x = gen_rtx_PLUS (SImode, xop0, xop1);
4361 /* XXX We don't allow MINUS any more -- see comment in
4362 arm_legitimate_address_p (). */
4363 else if (GET_CODE (x) == MINUS)
4365 rtx xop0 = XEXP (x, 0);
4366 rtx xop1 = XEXP (x, 1);
4368 if (CONSTANT_P (xop0))
4369 xop0 = force_reg (SImode, xop0);
4371 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4372 xop1 = force_reg (SImode, xop1);
4374 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4375 x = gen_rtx_MINUS (SImode, xop0, xop1);
4378 /* Make sure to take full advantage of the pre-indexed addressing mode
4379 with absolute addresses which often allows for the base register to
4380 be factorized for multiple adjacent memory references, and it might
4381 even allows for the mini pool to be avoided entirely. */
4382 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4385 HOST_WIDE_INT mask, base, index;
4388 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4389 use a 8 bit index. So let's use a 12 bit index for SImode only and
4390 hope that arm_gen_constant will enable ldrb to use more bits. */
4391 bits = (mode == SImode) ? 12 : 8;
4392 mask = (1 << bits) - 1;
4393 base = INTVAL (x) & ~mask;
4394 index = INTVAL (x) & mask;
4395 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4397 /* It'll most probably be more efficient to generate the base
4398 with more bits set and use a negative index instead. */
4402 base_reg = force_reg (SImode, GEN_INT (base));
4403 x = plus_constant (base_reg, index);
4408 /* We need to find and carefully transform any SYMBOL and LABEL
4409 references; so go back to the original address expression. */
4410 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4412 if (new_x != orig_x)
4420 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4421 to be legitimate. If we find one, return the new, valid address. */
4423 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4425 if (arm_tls_symbol_p (x))
4426 return legitimize_tls_address (x, NULL_RTX);
4428 if (GET_CODE (x) == PLUS
4429 && GET_CODE (XEXP (x, 1)) == CONST_INT
4430 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4431 || INTVAL (XEXP (x, 1)) < 0))
4433 rtx xop0 = XEXP (x, 0);
4434 rtx xop1 = XEXP (x, 1);
4435 HOST_WIDE_INT offset = INTVAL (xop1);
4437 /* Try and fold the offset into a biasing of the base register and
4438 then offsetting that. Don't do this when optimizing for space
4439 since it can cause too many CSEs. */
4440 if (optimize_size && offset >= 0
4441 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4443 HOST_WIDE_INT delta;
4446 delta = offset - (256 - GET_MODE_SIZE (mode));
4447 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4448 delta = 31 * GET_MODE_SIZE (mode);
4450 delta = offset & (~31 * GET_MODE_SIZE (mode));
4452 xop0 = force_operand (plus_constant (xop0, offset - delta),
4454 x = plus_constant (xop0, delta);
4456 else if (offset < 0 && offset > -256)
4457 /* Small negative offsets are best done with a subtract before the
4458 dereference, forcing these into a register normally takes two
4460 x = force_operand (x, NULL_RTX);
4463 /* For the remaining cases, force the constant into a register. */
4464 xop1 = force_reg (SImode, xop1);
4465 x = gen_rtx_PLUS (SImode, xop0, xop1);
4468 else if (GET_CODE (x) == PLUS
4469 && s_register_operand (XEXP (x, 1), SImode)
4470 && !s_register_operand (XEXP (x, 0), SImode))
4472 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4474 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4479 /* We need to find and carefully transform any SYMBOL and LABEL
4480 references; so go back to the original address expression. */
4481 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4483 if (new_x != orig_x)
4491 thumb_legitimize_reload_address (rtx *x_p,
4492 enum machine_mode mode,
4493 int opnum, int type,
4494 int ind_levels ATTRIBUTE_UNUSED)
4498 if (GET_CODE (x) == PLUS
4499 && GET_MODE_SIZE (mode) < 4
4500 && REG_P (XEXP (x, 0))
4501 && XEXP (x, 0) == stack_pointer_rtx
4502 && GET_CODE (XEXP (x, 1)) == CONST_INT
4503 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4508 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4509 Pmode, VOIDmode, 0, 0, opnum, type);
4513 /* If both registers are hi-regs, then it's better to reload the
4514 entire expression rather than each register individually. That
4515 only requires one reload register rather than two. */
4516 if (GET_CODE (x) == PLUS
4517 && REG_P (XEXP (x, 0))
4518 && REG_P (XEXP (x, 1))
4519 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4520 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4525 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4526 Pmode, VOIDmode, 0, 0, opnum, type);
4533 /* Test for various thread-local symbols. */
4535 /* Return TRUE if X is a thread-local symbol. */
4538 arm_tls_symbol_p (rtx x)
4540 if (! TARGET_HAVE_TLS)
4543 if (GET_CODE (x) != SYMBOL_REF)
4546 return SYMBOL_REF_TLS_MODEL (x) != 0;
4549 /* Helper for arm_tls_referenced_p. */
4552 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4554 if (GET_CODE (*x) == SYMBOL_REF)
4555 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4557 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4558 TLS offsets, not real symbol references. */
4559 if (GET_CODE (*x) == UNSPEC
4560 && XINT (*x, 1) == UNSPEC_TLS)
4566 /* Return TRUE if X contains any TLS symbol references. */
4569 arm_tls_referenced_p (rtx x)
4571 if (! TARGET_HAVE_TLS)
4574 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4577 #define REG_OR_SUBREG_REG(X) \
4578 (GET_CODE (X) == REG \
4579 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4581 #define REG_OR_SUBREG_RTX(X) \
4582 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4584 #ifndef COSTS_N_INSNS
4585 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4588 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4590 enum machine_mode mode = GET_MODE (x);
4603 return COSTS_N_INSNS (1);
4606 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4609 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4616 return COSTS_N_INSNS (2) + cycles;
4618 return COSTS_N_INSNS (1) + 16;
4621 return (COSTS_N_INSNS (1)
4622 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4623 + GET_CODE (SET_DEST (x)) == MEM));
4628 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4630 if (thumb_shiftable_const (INTVAL (x)))
4631 return COSTS_N_INSNS (2);
4632 return COSTS_N_INSNS (3);
4634 else if ((outer == PLUS || outer == COMPARE)
4635 && INTVAL (x) < 256 && INTVAL (x) > -256)
4637 else if (outer == AND
4638 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4639 return COSTS_N_INSNS (1);
4640 else if (outer == ASHIFT || outer == ASHIFTRT
4641 || outer == LSHIFTRT)
4643 return COSTS_N_INSNS (2);
4649 return COSTS_N_INSNS (3);
4667 /* XXX another guess. */
4668 /* Memory costs quite a lot for the first word, but subsequent words
4669 load at the equivalent of a single insn each. */
4670 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4671 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4676 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4681 /* XXX still guessing. */
4682 switch (GET_MODE (XEXP (x, 0)))
4685 return (1 + (mode == DImode ? 4 : 0)
4686 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4689 return (4 + (mode == DImode ? 4 : 0)
4690 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4693 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4705 /* Worker routine for arm_rtx_costs. */
4706 /* ??? This needs updating for thumb2. */
4708 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4710 enum machine_mode mode = GET_MODE (x);
4711 enum rtx_code subcode;
4717 /* Memory costs quite a lot for the first word, but subsequent words
4718 load at the equivalent of a single insn each. */
4719 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4720 + (GET_CODE (x) == SYMBOL_REF
4721 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4727 return optimize_size ? COSTS_N_INSNS (2) : 100;
4730 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4737 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4739 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4740 + ((GET_CODE (XEXP (x, 0)) == REG
4741 || (GET_CODE (XEXP (x, 0)) == SUBREG
4742 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4744 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4745 || (GET_CODE (XEXP (x, 0)) == SUBREG
4746 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4748 + ((GET_CODE (XEXP (x, 1)) == REG
4749 || (GET_CODE (XEXP (x, 1)) == SUBREG
4750 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4751 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4756 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4757 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4758 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4759 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4762 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4763 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4764 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4765 && arm_const_double_rtx (XEXP (x, 1))))
4767 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4768 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4769 && arm_const_double_rtx (XEXP (x, 0))))
4772 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4773 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4774 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4775 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4776 || subcode == ASHIFTRT || subcode == LSHIFTRT
4777 || subcode == ROTATE || subcode == ROTATERT
4779 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4780 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4781 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4782 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4783 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4784 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4785 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4790 if (GET_CODE (XEXP (x, 0)) == MULT)
4792 extra_cost = rtx_cost (XEXP (x, 0), code);
4793 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4794 extra_cost += 4 * ARM_NUM_REGS (mode);
4798 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4799 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4800 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4801 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4802 && arm_const_double_rtx (XEXP (x, 1))))
4806 case AND: case XOR: case IOR:
4809 /* Normally the frame registers will be spilt into reg+const during
4810 reload, so it is a bad idea to combine them with other instructions,
4811 since then they might not be moved outside of loops. As a compromise
4812 we allow integration with ops that have a constant as their second
4814 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4815 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4816 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4817 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4818 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4822 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4823 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4824 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4825 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4828 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4829 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4830 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4831 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4832 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4835 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4836 return (1 + extra_cost
4837 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4838 || subcode == LSHIFTRT || subcode == ASHIFTRT
4839 || subcode == ROTATE || subcode == ROTATERT
4841 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4842 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4843 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4844 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4845 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4846 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4852 /* This should have been handled by the CPU specific routines. */
4856 if (arm_arch3m && mode == SImode
4857 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4858 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4859 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4860 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4861 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4862 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4867 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4868 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4872 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4874 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4877 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4885 return 4 + (mode == DImode ? 4 : 0);
4888 /* ??? value extensions are cheaper on armv6. */
4889 if (GET_MODE (XEXP (x, 0)) == QImode)
4890 return (4 + (mode == DImode ? 4 : 0)
4891 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4894 switch (GET_MODE (XEXP (x, 0)))
4897 return (1 + (mode == DImode ? 4 : 0)
4898 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4901 return (4 + (mode == DImode ? 4 : 0)
4902 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4905 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4920 if (const_ok_for_arm (INTVAL (x)))
4921 return outer == SET ? 2 : -1;
4922 else if (outer == AND
4923 && const_ok_for_arm (~INTVAL (x)))
4925 else if ((outer == COMPARE
4926 || outer == PLUS || outer == MINUS)
4927 && const_ok_for_arm (-INTVAL (x)))
4938 if (arm_const_double_rtx (x))
4939 return outer == SET ? 2 : -1;
4940 else if ((outer == COMPARE || outer == PLUS)
4941 && neg_const_double_rtx_ok_for_fpa (x))
4950 /* RTX costs when optimizing for size. */
4952 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4954 enum machine_mode mode = GET_MODE (x);
4958 /* XXX TBD. For now, use the standard costs. */
4959 *total = thumb1_rtx_costs (x, code, outer_code);
4966 /* A memory access costs 1 insn if the mode is small, or the address is
4967 a single register, otherwise it costs one insn per word. */
4968 if (REG_P (XEXP (x, 0)))
4969 *total = COSTS_N_INSNS (1);
4971 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4978 /* Needs a libcall, so it costs about this. */
4979 *total = COSTS_N_INSNS (2);
4983 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4985 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4993 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4995 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4998 else if (mode == SImode)
5000 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5001 /* Slightly disparage register shifts, but not by much. */
5002 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5003 *total += 1 + rtx_cost (XEXP (x, 1), code);
5007 /* Needs a libcall. */
5008 *total = COSTS_N_INSNS (2);
5012 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5014 *total = COSTS_N_INSNS (1);
5020 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5021 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5023 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5024 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5025 || subcode1 == ROTATE || subcode1 == ROTATERT
5026 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5027 || subcode1 == ASHIFTRT)
5029 /* It's just the cost of the two operands. */
5034 *total = COSTS_N_INSNS (1);
5038 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5042 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5044 *total = COSTS_N_INSNS (1);
5049 case AND: case XOR: case IOR:
5052 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5054 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5055 || subcode == LSHIFTRT || subcode == ASHIFTRT
5056 || (code == AND && subcode == NOT))
5058 /* It's just the cost of the two operands. */
5064 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5068 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5072 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5073 *total = COSTS_N_INSNS (1);
5076 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5085 if (cc_register (XEXP (x, 0), VOIDmode))
5088 *total = COSTS_N_INSNS (1);
5092 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5093 *total = COSTS_N_INSNS (1);
5095 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5100 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5102 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5103 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5106 *total += COSTS_N_INSNS (1);
5111 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5113 switch (GET_MODE (XEXP (x, 0)))
5116 *total += COSTS_N_INSNS (1);
5120 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5126 *total += COSTS_N_INSNS (2);
5131 *total += COSTS_N_INSNS (1);
5136 if (const_ok_for_arm (INTVAL (x)))
5137 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5138 else if (const_ok_for_arm (~INTVAL (x)))
5139 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5140 else if (const_ok_for_arm (-INTVAL (x)))
5142 if (outer_code == COMPARE || outer_code == PLUS
5143 || outer_code == MINUS)
5146 *total = COSTS_N_INSNS (1);
5149 *total = COSTS_N_INSNS (2);
5155 *total = COSTS_N_INSNS (2);
5159 *total = COSTS_N_INSNS (4);
5163 if (mode != VOIDmode)
5164 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5166 *total = COSTS_N_INSNS (4); /* How knows? */
5171 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5172 supported on any "slowmul" cores, so it can be ignored. */
5175 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5177 enum machine_mode mode = GET_MODE (x);
5181 *total = thumb1_rtx_costs (x, code, outer_code);
5188 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5195 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5197 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5198 & (unsigned HOST_WIDE_INT) 0xffffffff);
5199 int cost, const_ok = const_ok_for_arm (i);
5200 int j, booth_unit_size;
5202 /* Tune as appropriate. */
5203 cost = const_ok ? 4 : 8;
5204 booth_unit_size = 2;
5205 for (j = 0; i && j < 32; j += booth_unit_size)
5207 i >>= booth_unit_size;
5215 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5216 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5220 *total = arm_rtx_costs_1 (x, code, outer_code);
5226 /* RTX cost for cores with a fast multiply unit (M variants). */
5229 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5231 enum machine_mode mode = GET_MODE (x);
5235 *total = thumb1_rtx_costs (x, code, outer_code);
5239 /* ??? should thumb2 use different costs? */
5243 /* There is no point basing this on the tuning, since it is always the
5244 fast variant if it exists at all. */
5246 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5247 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5248 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5255 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5262 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5264 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5265 & (unsigned HOST_WIDE_INT) 0xffffffff);
5266 int cost, const_ok = const_ok_for_arm (i);
5267 int j, booth_unit_size;
5269 /* Tune as appropriate. */
5270 cost = const_ok ? 4 : 8;
5271 booth_unit_size = 8;
5272 for (j = 0; i && j < 32; j += booth_unit_size)
5274 i >>= booth_unit_size;
5282 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5283 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5287 *total = arm_rtx_costs_1 (x, code, outer_code);
5293 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5294 so it can be ignored. */
5297 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5299 enum machine_mode mode = GET_MODE (x);
5303 *total = thumb1_rtx_costs (x, code, outer_code);
5310 /* There is no point basing this on the tuning, since it is always the
5311 fast variant if it exists at all. */
5313 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5314 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5315 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5322 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5329 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5331 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5332 & (unsigned HOST_WIDE_INT) 0xffffffff);
5333 int cost, const_ok = const_ok_for_arm (i);
5334 unsigned HOST_WIDE_INT masked_const;
5336 /* The cost will be related to two insns.
5337 First a load of the constant (MOV or LDR), then a multiply. */
5340 cost += 1; /* LDR is probably more expensive because
5341 of longer result latency. */
5342 masked_const = i & 0xffff8000;
5343 if (masked_const != 0 && masked_const != 0xffff8000)
5345 masked_const = i & 0xf8000000;
5346 if (masked_const == 0 || masked_const == 0xf8000000)
5355 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5356 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5360 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5361 will stall until the multiplication is complete. */
5362 if (GET_CODE (XEXP (x, 0)) == MULT)
5363 *total = 4 + rtx_cost (XEXP (x, 0), code);
5365 *total = arm_rtx_costs_1 (x, code, outer_code);
5369 *total = arm_rtx_costs_1 (x, code, outer_code);
5375 /* RTX costs for 9e (and later) cores. */
5378 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5380 enum machine_mode mode = GET_MODE (x);
5389 *total = COSTS_N_INSNS (3);
5393 *total = thumb1_rtx_costs (x, code, outer_code);
5401 /* There is no point basing this on the tuning, since it is always the
5402 fast variant if it exists at all. */
5404 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5405 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5406 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5413 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5430 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5431 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5435 *total = arm_rtx_costs_1 (x, code, outer_code);
5439 /* All address computations that can be done are free, but rtx cost returns
5440 the same for practically all of them. So we weight the different types
5441 of address here in the order (most pref first):
5442 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5444 arm_arm_address_cost (rtx x)
5446 enum rtx_code c = GET_CODE (x);
5448 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5450 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5453 if (c == PLUS || c == MINUS)
5455 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5458 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5468 arm_thumb_address_cost (rtx x)
5470 enum rtx_code c = GET_CODE (x);
5475 && GET_CODE (XEXP (x, 0)) == REG
5476 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5483 arm_address_cost (rtx x)
5485 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5489 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5493 /* Some true dependencies can have a higher cost depending
5494 on precisely how certain input operands are used. */
5496 && REG_NOTE_KIND (link) == 0
5497 && recog_memoized (insn) >= 0
5498 && recog_memoized (dep) >= 0)
5500 int shift_opnum = get_attr_shift (insn);
5501 enum attr_type attr_type = get_attr_type (dep);
5503 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5504 operand for INSN. If we have a shifted input operand and the
5505 instruction we depend on is another ALU instruction, then we may
5506 have to account for an additional stall. */
5507 if (shift_opnum != 0
5508 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5510 rtx shifted_operand;
5513 /* Get the shifted operand. */
5514 extract_insn (insn);
5515 shifted_operand = recog_data.operand[shift_opnum];
5517 /* Iterate over all the operands in DEP. If we write an operand
5518 that overlaps with SHIFTED_OPERAND, then we have increase the
5519 cost of this dependency. */
5521 preprocess_constraints ();
5522 for (opno = 0; opno < recog_data.n_operands; opno++)
5524 /* We can ignore strict inputs. */
5525 if (recog_data.operand_type[opno] == OP_IN)
5528 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5535 /* XXX This is not strictly true for the FPA. */
5536 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5537 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5540 /* Call insns don't incur a stall, even if they follow a load. */
5541 if (REG_NOTE_KIND (link) == 0
5542 && GET_CODE (insn) == CALL_INSN)
5545 if ((i_pat = single_set (insn)) != NULL
5546 && GET_CODE (SET_SRC (i_pat)) == MEM
5547 && (d_pat = single_set (dep)) != NULL
5548 && GET_CODE (SET_DEST (d_pat)) == MEM)
5550 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5551 /* This is a load after a store, there is no conflict if the load reads
5552 from a cached area. Assume that loads from the stack, and from the
5553 constant pool are cached, and that others will miss. This is a
5556 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5557 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5558 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5559 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5566 static int fp_consts_inited = 0;
5568 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5569 static const char * const strings_fp[8] =
5572 "4", "5", "0.5", "10"
5575 static REAL_VALUE_TYPE values_fp[8];
5578 init_fp_table (void)
5584 fp_consts_inited = 1;
5586 fp_consts_inited = 8;
5588 for (i = 0; i < fp_consts_inited; i++)
5590 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5595 /* Return TRUE if rtx X is a valid immediate FP constant. */
5597 arm_const_double_rtx (rtx x)
5602 if (!fp_consts_inited)
5605 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5606 if (REAL_VALUE_MINUS_ZERO (r))
5609 for (i = 0; i < fp_consts_inited; i++)
5610 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5616 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5618 neg_const_double_rtx_ok_for_fpa (rtx x)
5623 if (!fp_consts_inited)
5626 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5627 r = REAL_VALUE_NEGATE (r);
5628 if (REAL_VALUE_MINUS_ZERO (r))
5631 for (i = 0; i < 8; i++)
5632 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5638 /* Predicates for `match_operand' and `match_operator'. */
5640 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5642 cirrus_memory_offset (rtx op)
5644 /* Reject eliminable registers. */
5645 if (! (reload_in_progress || reload_completed)
5646 && ( reg_mentioned_p (frame_pointer_rtx, op)
5647 || reg_mentioned_p (arg_pointer_rtx, op)
5648 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5649 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5650 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5651 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5654 if (GET_CODE (op) == MEM)
5660 /* Match: (mem (reg)). */
5661 if (GET_CODE (ind) == REG)
5667 if (GET_CODE (ind) == PLUS
5668 && GET_CODE (XEXP (ind, 0)) == REG
5669 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5670 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5677 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5678 WB is true if full writeback address modes are allowed and is false
5679 if limited writeback address modes (POST_INC and PRE_DEC) are
5683 arm_coproc_mem_operand (rtx op, bool wb)
5687 /* Reject eliminable registers. */
5688 if (! (reload_in_progress || reload_completed)
5689 && ( reg_mentioned_p (frame_pointer_rtx, op)
5690 || reg_mentioned_p (arg_pointer_rtx, op)
5691 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5692 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5693 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5694 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5697 /* Constants are converted into offsets from labels. */
5698 if (GET_CODE (op) != MEM)
5703 if (reload_completed
5704 && (GET_CODE (ind) == LABEL_REF
5705 || (GET_CODE (ind) == CONST
5706 && GET_CODE (XEXP (ind, 0)) == PLUS
5707 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5708 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5711 /* Match: (mem (reg)). */
5712 if (GET_CODE (ind) == REG)
5713 return arm_address_register_rtx_p (ind, 0);
5715 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5716 acceptable in any case (subject to verification by
5717 arm_address_register_rtx_p). We need WB to be true to accept
5718 PRE_INC and POST_DEC. */
5719 if (GET_CODE (ind) == POST_INC
5720 || GET_CODE (ind) == PRE_DEC
5722 && (GET_CODE (ind) == PRE_INC
5723 || GET_CODE (ind) == POST_DEC)))
5724 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5727 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5728 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5729 && GET_CODE (XEXP (ind, 1)) == PLUS
5730 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5731 ind = XEXP (ind, 1);
5736 if (GET_CODE (ind) == PLUS
5737 && GET_CODE (XEXP (ind, 0)) == REG
5738 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5739 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5740 && INTVAL (XEXP (ind, 1)) > -1024
5741 && INTVAL (XEXP (ind, 1)) < 1024
5742 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5748 /* Return true if X is a register that will be eliminated later on. */
5750 arm_eliminable_register (rtx x)
5752 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5753 || REGNO (x) == ARG_POINTER_REGNUM
5754 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5755 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5758 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5759 VFP registers. Otherwise return NO_REGS. */
5762 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
5764 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
5767 return GENERAL_REGS;
5770 /* Values which must be returned in the most-significant end of the return
5774 arm_return_in_msb (tree valtype)
5776 return (TARGET_AAPCS_BASED
5778 && (AGGREGATE_TYPE_P (valtype)
5779 || TREE_CODE (valtype) == COMPLEX_TYPE));
5782 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5783 Use by the Cirrus Maverick code which has to workaround
5784 a hardware bug triggered by such instructions. */
5786 arm_memory_load_p (rtx insn)
5788 rtx body, lhs, rhs;;
5790 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5793 body = PATTERN (insn);
5795 if (GET_CODE (body) != SET)
5798 lhs = XEXP (body, 0);
5799 rhs = XEXP (body, 1);
5801 lhs = REG_OR_SUBREG_RTX (lhs);
5803 /* If the destination is not a general purpose
5804 register we do not have to worry. */
5805 if (GET_CODE (lhs) != REG
5806 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5809 /* As well as loads from memory we also have to react
5810 to loads of invalid constants which will be turned
5811 into loads from the minipool. */
5812 return (GET_CODE (rhs) == MEM
5813 || GET_CODE (rhs) == SYMBOL_REF
5814 || note_invalid_constants (insn, -1, false));
5817 /* Return TRUE if INSN is a Cirrus instruction. */
5819 arm_cirrus_insn_p (rtx insn)
5821 enum attr_cirrus attr;
5823 /* get_attr cannot accept USE or CLOBBER. */
5825 || GET_CODE (insn) != INSN
5826 || GET_CODE (PATTERN (insn)) == USE
5827 || GET_CODE (PATTERN (insn)) == CLOBBER)
5830 attr = get_attr_cirrus (insn);
5832 return attr != CIRRUS_NOT;
5835 /* Cirrus reorg for invalid instruction combinations. */
5837 cirrus_reorg (rtx first)
5839 enum attr_cirrus attr;
5840 rtx body = PATTERN (first);
5844 /* Any branch must be followed by 2 non Cirrus instructions. */
5845 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5848 t = next_nonnote_insn (first);
5850 if (arm_cirrus_insn_p (t))
5853 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5857 emit_insn_after (gen_nop (), first);
5862 /* (float (blah)) is in parallel with a clobber. */
5863 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5864 body = XVECEXP (body, 0, 0);
5866 if (GET_CODE (body) == SET)
5868 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5870 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5871 be followed by a non Cirrus insn. */
5872 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5874 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5875 emit_insn_after (gen_nop (), first);
5879 else if (arm_memory_load_p (first))
5881 unsigned int arm_regno;
5883 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5884 ldr/cfmv64hr combination where the Rd field is the same
5885 in both instructions must be split with a non Cirrus
5892 /* Get Arm register number for ldr insn. */
5893 if (GET_CODE (lhs) == REG)
5894 arm_regno = REGNO (lhs);
5897 gcc_assert (GET_CODE (rhs) == REG);
5898 arm_regno = REGNO (rhs);
5902 first = next_nonnote_insn (first);
5904 if (! arm_cirrus_insn_p (first))
5907 body = PATTERN (first);
5909 /* (float (blah)) is in parallel with a clobber. */
5910 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5911 body = XVECEXP (body, 0, 0);
5913 if (GET_CODE (body) == FLOAT)
5914 body = XEXP (body, 0);
5916 if (get_attr_cirrus (first) == CIRRUS_MOVE
5917 && GET_CODE (XEXP (body, 1)) == REG
5918 && arm_regno == REGNO (XEXP (body, 1)))
5919 emit_insn_after (gen_nop (), first);
5925 /* get_attr cannot accept USE or CLOBBER. */
5927 || GET_CODE (first) != INSN
5928 || GET_CODE (PATTERN (first)) == USE
5929 || GET_CODE (PATTERN (first)) == CLOBBER)
5932 attr = get_attr_cirrus (first);
5934 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5935 must be followed by a non-coprocessor instruction. */
5936 if (attr == CIRRUS_COMPARE)
5940 t = next_nonnote_insn (first);
5942 if (arm_cirrus_insn_p (t))
5945 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5949 emit_insn_after (gen_nop (), first);
5955 /* Return TRUE if X references a SYMBOL_REF. */
5957 symbol_mentioned_p (rtx x)
5962 if (GET_CODE (x) == SYMBOL_REF)
5965 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5966 are constant offsets, not symbols. */
5967 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5970 fmt = GET_RTX_FORMAT (GET_CODE (x));
5972 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5978 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5979 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5982 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5989 /* Return TRUE if X references a LABEL_REF. */
5991 label_mentioned_p (rtx x)
5996 if (GET_CODE (x) == LABEL_REF)
5999 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6000 instruction, but they are constant offsets, not symbols. */
6001 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6004 fmt = GET_RTX_FORMAT (GET_CODE (x));
6005 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6011 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6012 if (label_mentioned_p (XVECEXP (x, i, j)))
6015 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6023 tls_mentioned_p (rtx x)
6025 switch (GET_CODE (x))
6028 return tls_mentioned_p (XEXP (x, 0));
6031 if (XINT (x, 1) == UNSPEC_TLS)
6039 /* Must not copy a SET whose source operand is PC-relative. */
6042 arm_cannot_copy_insn_p (rtx insn)
6044 rtx pat = PATTERN (insn);
6046 if (GET_CODE (pat) == PARALLEL
6047 && GET_CODE (XVECEXP (pat, 0, 0)) == SET)
6049 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0));
6051 if (GET_CODE (rhs) == UNSPEC
6052 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6055 if (GET_CODE (rhs) == MEM
6056 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6057 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6067 enum rtx_code code = GET_CODE (x);
6084 /* Return 1 if memory locations are adjacent. */
6086 adjacent_mem_locations (rtx a, rtx b)
6088 /* We don't guarantee to preserve the order of these memory refs. */
6089 if (volatile_refs_p (a) || volatile_refs_p (b))
6092 if ((GET_CODE (XEXP (a, 0)) == REG
6093 || (GET_CODE (XEXP (a, 0)) == PLUS
6094 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6095 && (GET_CODE (XEXP (b, 0)) == REG
6096 || (GET_CODE (XEXP (b, 0)) == PLUS
6097 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6099 HOST_WIDE_INT val0 = 0, val1 = 0;
6103 if (GET_CODE (XEXP (a, 0)) == PLUS)
6105 reg0 = XEXP (XEXP (a, 0), 0);
6106 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6111 if (GET_CODE (XEXP (b, 0)) == PLUS)
6113 reg1 = XEXP (XEXP (b, 0), 0);
6114 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6119 /* Don't accept any offset that will require multiple
6120 instructions to handle, since this would cause the
6121 arith_adjacentmem pattern to output an overlong sequence. */
6122 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6125 /* Don't allow an eliminable register: register elimination can make
6126 the offset too large. */
6127 if (arm_eliminable_register (reg0))
6130 val_diff = val1 - val0;
6134 /* If the target has load delay slots, then there's no benefit
6135 to using an ldm instruction unless the offset is zero and
6136 we are optimizing for size. */
6137 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6138 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6139 && (val_diff == 4 || val_diff == -4));
6142 return ((REGNO (reg0) == REGNO (reg1))
6143 && (val_diff == 4 || val_diff == -4));
6150 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6151 HOST_WIDE_INT *load_offset)
6153 int unsorted_regs[4];
6154 HOST_WIDE_INT unsorted_offsets[4];
6159 /* Can only handle 2, 3, or 4 insns at present,
6160 though could be easily extended if required. */
6161 gcc_assert (nops >= 2 && nops <= 4);
6163 /* Loop over the operands and check that the memory references are
6164 suitable (i.e. immediate offsets from the same base register). At
6165 the same time, extract the target register, and the memory
6167 for (i = 0; i < nops; i++)
6172 /* Convert a subreg of a mem into the mem itself. */
6173 if (GET_CODE (operands[nops + i]) == SUBREG)
6174 operands[nops + i] = alter_subreg (operands + (nops + i));
6176 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6178 /* Don't reorder volatile memory references; it doesn't seem worth
6179 looking for the case where the order is ok anyway. */
6180 if (MEM_VOLATILE_P (operands[nops + i]))
6183 offset = const0_rtx;
6185 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6186 || (GET_CODE (reg) == SUBREG
6187 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6188 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6189 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6191 || (GET_CODE (reg) == SUBREG
6192 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6193 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6198 base_reg = REGNO (reg);
6199 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6200 ? REGNO (operands[i])
6201 : REGNO (SUBREG_REG (operands[i])));
6206 if (base_reg != (int) REGNO (reg))
6207 /* Not addressed from the same base register. */
6210 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6211 ? REGNO (operands[i])
6212 : REGNO (SUBREG_REG (operands[i])));
6213 if (unsorted_regs[i] < unsorted_regs[order[0]])
6217 /* If it isn't an integer register, or if it overwrites the
6218 base register but isn't the last insn in the list, then
6219 we can't do this. */
6220 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6221 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6224 unsorted_offsets[i] = INTVAL (offset);
6227 /* Not a suitable memory address. */
6231 /* All the useful information has now been extracted from the
6232 operands into unsorted_regs and unsorted_offsets; additionally,
6233 order[0] has been set to the lowest numbered register in the
6234 list. Sort the registers into order, and check that the memory
6235 offsets are ascending and adjacent. */
6237 for (i = 1; i < nops; i++)
6241 order[i] = order[i - 1];
6242 for (j = 0; j < nops; j++)
6243 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6244 && (order[i] == order[i - 1]
6245 || unsorted_regs[j] < unsorted_regs[order[i]]))
6248 /* Have we found a suitable register? if not, one must be used more
6250 if (order[i] == order[i - 1])
6253 /* Is the memory address adjacent and ascending? */
6254 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6262 for (i = 0; i < nops; i++)
6263 regs[i] = unsorted_regs[order[i]];
6265 *load_offset = unsorted_offsets[order[0]];
6268 if (unsorted_offsets[order[0]] == 0)
6269 return 1; /* ldmia */
6271 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
6272 return 2; /* ldmib */
6274 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
6275 return 3; /* ldmda */
6277 if (unsorted_offsets[order[nops - 1]] == -4)
6278 return 4; /* ldmdb */
6280 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6281 if the offset isn't small enough. The reason 2 ldrs are faster
6282 is because these ARMs are able to do more than one cache access
6283 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6284 whilst the ARM8 has a double bandwidth cache. This means that
6285 these cores can do both an instruction fetch and a data fetch in
6286 a single cycle, so the trick of calculating the address into a
6287 scratch register (one of the result regs) and then doing a load
6288 multiple actually becomes slower (and no smaller in code size).
6289 That is the transformation
6291 ldr rd1, [rbase + offset]
6292 ldr rd2, [rbase + offset + 4]
6296 add rd1, rbase, offset
6297 ldmia rd1, {rd1, rd2}
6299 produces worse code -- '3 cycles + any stalls on rd2' instead of
6300 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6301 access per cycle, the first sequence could never complete in less
6302 than 6 cycles, whereas the ldm sequence would only take 5 and
6303 would make better use of sequential accesses if not hitting the
6306 We cheat here and test 'arm_ld_sched' which we currently know to
6307 only be true for the ARM8, ARM9 and StrongARM. If this ever
6308 changes, then the test below needs to be reworked. */
6309 if (nops == 2 && arm_ld_sched)
6312 /* Can't do it without setting up the offset, only do this if it takes
6313 no more than one insn. */
6314 return (const_ok_for_arm (unsorted_offsets[order[0]])
6315 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
6319 emit_ldm_seq (rtx *operands, int nops)
6323 HOST_WIDE_INT offset;
6327 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6330 strcpy (buf, "ldm%(ia%)\t");
6334 strcpy (buf, "ldm%(ib%)\t");
6338 strcpy (buf, "ldm%(da%)\t");
6342 strcpy (buf, "ldm%(db%)\t");
6347 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6348 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6351 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6352 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6354 output_asm_insn (buf, operands);
6356 strcpy (buf, "ldm%(ia%)\t");
6363 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6364 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6366 for (i = 1; i < nops; i++)
6367 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6368 reg_names[regs[i]]);
6370 strcat (buf, "}\t%@ phole ldm");
6372 output_asm_insn (buf, operands);
6377 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6378 HOST_WIDE_INT * load_offset)
6380 int unsorted_regs[4];
6381 HOST_WIDE_INT unsorted_offsets[4];
6386 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6387 extended if required. */
6388 gcc_assert (nops >= 2 && nops <= 4);
6390 /* Loop over the operands and check that the memory references are
6391 suitable (i.e. immediate offsets from the same base register). At
6392 the same time, extract the target register, and the memory
6394 for (i = 0; i < nops; i++)
6399 /* Convert a subreg of a mem into the mem itself. */
6400 if (GET_CODE (operands[nops + i]) == SUBREG)
6401 operands[nops + i] = alter_subreg (operands + (nops + i));
6403 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6405 /* Don't reorder volatile memory references; it doesn't seem worth
6406 looking for the case where the order is ok anyway. */
6407 if (MEM_VOLATILE_P (operands[nops + i]))
6410 offset = const0_rtx;
6412 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6413 || (GET_CODE (reg) == SUBREG
6414 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6415 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6416 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6418 || (GET_CODE (reg) == SUBREG
6419 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6420 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6425 base_reg = REGNO (reg);
6426 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6427 ? REGNO (operands[i])
6428 : REGNO (SUBREG_REG (operands[i])));
6433 if (base_reg != (int) REGNO (reg))
6434 /* Not addressed from the same base register. */
6437 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6438 ? REGNO (operands[i])
6439 : REGNO (SUBREG_REG (operands[i])));
6440 if (unsorted_regs[i] < unsorted_regs[order[0]])
6444 /* If it isn't an integer register, then we can't do this. */
6445 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6448 unsorted_offsets[i] = INTVAL (offset);
6451 /* Not a suitable memory address. */
6455 /* All the useful information has now been extracted from the
6456 operands into unsorted_regs and unsorted_offsets; additionally,
6457 order[0] has been set to the lowest numbered register in the
6458 list. Sort the registers into order, and check that the memory
6459 offsets are ascending and adjacent. */
6461 for (i = 1; i < nops; i++)
6465 order[i] = order[i - 1];
6466 for (j = 0; j < nops; j++)
6467 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6468 && (order[i] == order[i - 1]
6469 || unsorted_regs[j] < unsorted_regs[order[i]]))
6472 /* Have we found a suitable register? if not, one must be used more
6474 if (order[i] == order[i - 1])
6477 /* Is the memory address adjacent and ascending? */
6478 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6486 for (i = 0; i < nops; i++)
6487 regs[i] = unsorted_regs[order[i]];
6489 *load_offset = unsorted_offsets[order[0]];
6492 if (unsorted_offsets[order[0]] == 0)
6493 return 1; /* stmia */
6495 if (unsorted_offsets[order[0]] == 4)
6496 return 2; /* stmib */
6498 if (unsorted_offsets[order[nops - 1]] == 0)
6499 return 3; /* stmda */
6501 if (unsorted_offsets[order[nops - 1]] == -4)
6502 return 4; /* stmdb */
6508 emit_stm_seq (rtx *operands, int nops)
6512 HOST_WIDE_INT offset;
6516 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6519 strcpy (buf, "stm%(ia%)\t");
6523 strcpy (buf, "stm%(ib%)\t");
6527 strcpy (buf, "stm%(da%)\t");
6531 strcpy (buf, "stm%(db%)\t");
6538 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6539 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6541 for (i = 1; i < nops; i++)
6542 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6543 reg_names[regs[i]]);
6545 strcat (buf, "}\t%@ phole stm");
6547 output_asm_insn (buf, operands);
6551 /* Routines for use in generating RTL. */
6554 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6555 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6557 HOST_WIDE_INT offset = *offsetp;
6560 int sign = up ? 1 : -1;
6563 /* XScale has load-store double instructions, but they have stricter
6564 alignment requirements than load-store multiple, so we cannot
6567 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6568 the pipeline until completion.
6576 An ldr instruction takes 1-3 cycles, but does not block the
6585 Best case ldr will always win. However, the more ldr instructions
6586 we issue, the less likely we are to be able to schedule them well.
6587 Using ldr instructions also increases code size.
6589 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6590 for counts of 3 or 4 regs. */
6591 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6597 for (i = 0; i < count; i++)
6599 addr = plus_constant (from, i * 4 * sign);
6600 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6601 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6607 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6617 result = gen_rtx_PARALLEL (VOIDmode,
6618 rtvec_alloc (count + (write_back ? 1 : 0)));
6621 XVECEXP (result, 0, 0)
6622 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6627 for (j = 0; i < count; i++, j++)
6629 addr = plus_constant (from, j * 4 * sign);
6630 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6631 XVECEXP (result, 0, i)
6632 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6643 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6644 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6646 HOST_WIDE_INT offset = *offsetp;
6649 int sign = up ? 1 : -1;
6652 /* See arm_gen_load_multiple for discussion of
6653 the pros/cons of ldm/stm usage for XScale. */
6654 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6660 for (i = 0; i < count; i++)
6662 addr = plus_constant (to, i * 4 * sign);
6663 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6664 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6670 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6680 result = gen_rtx_PARALLEL (VOIDmode,
6681 rtvec_alloc (count + (write_back ? 1 : 0)));
6684 XVECEXP (result, 0, 0)
6685 = gen_rtx_SET (VOIDmode, to,
6686 plus_constant (to, count * 4 * sign));
6691 for (j = 0; i < count; i++, j++)
6693 addr = plus_constant (to, j * 4 * sign);
6694 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6695 XVECEXP (result, 0, i)
6696 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6707 arm_gen_movmemqi (rtx *operands)
6709 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6710 HOST_WIDE_INT srcoffset, dstoffset;
6712 rtx src, dst, srcbase, dstbase;
6713 rtx part_bytes_reg = NULL;
6716 if (GET_CODE (operands[2]) != CONST_INT
6717 || GET_CODE (operands[3]) != CONST_INT
6718 || INTVAL (operands[2]) > 64
6719 || INTVAL (operands[3]) & 3)
6722 dstbase = operands[0];
6723 srcbase = operands[1];
6725 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6726 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6728 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6729 out_words_to_go = INTVAL (operands[2]) / 4;
6730 last_bytes = INTVAL (operands[2]) & 3;
6731 dstoffset = srcoffset = 0;
6733 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6734 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6736 for (i = 0; in_words_to_go >= 2; i+=4)
6738 if (in_words_to_go > 4)
6739 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6740 srcbase, &srcoffset));
6742 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6743 FALSE, srcbase, &srcoffset));
6745 if (out_words_to_go)
6747 if (out_words_to_go > 4)
6748 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6749 dstbase, &dstoffset));
6750 else if (out_words_to_go != 1)
6751 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6755 dstbase, &dstoffset));
6758 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6759 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6760 if (last_bytes != 0)
6762 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6768 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6769 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6772 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6773 if (out_words_to_go)
6777 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6778 sreg = copy_to_reg (mem);
6780 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6781 emit_move_insn (mem, sreg);
6784 gcc_assert (!in_words_to_go); /* Sanity check */
6789 gcc_assert (in_words_to_go > 0);
6791 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6792 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6795 gcc_assert (!last_bytes || part_bytes_reg);
6797 if (BYTES_BIG_ENDIAN && last_bytes)
6799 rtx tmp = gen_reg_rtx (SImode);
6801 /* The bytes we want are in the top end of the word. */
6802 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6803 GEN_INT (8 * (4 - last_bytes))));
6804 part_bytes_reg = tmp;
6808 mem = adjust_automodify_address (dstbase, QImode,
6809 plus_constant (dst, last_bytes - 1),
6810 dstoffset + last_bytes - 1);
6811 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6815 tmp = gen_reg_rtx (SImode);
6816 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6817 part_bytes_reg = tmp;
6826 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6827 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6831 rtx tmp = gen_reg_rtx (SImode);
6832 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6833 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6834 part_bytes_reg = tmp;
6841 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6842 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6849 /* Select a dominance comparison mode if possible for a test of the general
6850 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6851 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6852 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6853 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6854 In all cases OP will be either EQ or NE, but we don't need to know which
6855 here. If we are unable to support a dominance comparison we return
6856 CC mode. This will then fail to match for the RTL expressions that
6857 generate this call. */
6859 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6861 enum rtx_code cond1, cond2;
6864 /* Currently we will probably get the wrong result if the individual
6865 comparisons are not simple. This also ensures that it is safe to
6866 reverse a comparison if necessary. */
6867 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6869 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6873 /* The if_then_else variant of this tests the second condition if the
6874 first passes, but is true if the first fails. Reverse the first
6875 condition to get a true "inclusive-or" expression. */
6876 if (cond_or == DOM_CC_NX_OR_Y)
6877 cond1 = reverse_condition (cond1);
6879 /* If the comparisons are not equal, and one doesn't dominate the other,
6880 then we can't do this. */
6882 && !comparison_dominates_p (cond1, cond2)
6883 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6888 enum rtx_code temp = cond1;
6896 if (cond_or == DOM_CC_X_AND_Y)
6901 case EQ: return CC_DEQmode;
6902 case LE: return CC_DLEmode;
6903 case LEU: return CC_DLEUmode;
6904 case GE: return CC_DGEmode;
6905 case GEU: return CC_DGEUmode;
6906 default: gcc_unreachable ();
6910 if (cond_or == DOM_CC_X_AND_Y)
6926 if (cond_or == DOM_CC_X_AND_Y)
6942 if (cond_or == DOM_CC_X_AND_Y)
6958 if (cond_or == DOM_CC_X_AND_Y)
6973 /* The remaining cases only occur when both comparisons are the
6976 gcc_assert (cond1 == cond2);
6980 gcc_assert (cond1 == cond2);
6984 gcc_assert (cond1 == cond2);
6988 gcc_assert (cond1 == cond2);
6992 gcc_assert (cond1 == cond2);
7001 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
7003 /* All floating point compares return CCFP if it is an equality
7004 comparison, and CCFPE otherwise. */
7005 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
7025 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
7034 /* A compare with a shifted operand. Because of canonicalization, the
7035 comparison will have to be swapped when we emit the assembler. */
7036 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7037 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7038 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7039 || GET_CODE (x) == ROTATERT))
7042 /* This operation is performed swapped, but since we only rely on the Z
7043 flag we don't need an additional mode. */
7044 if (GET_MODE (y) == SImode && REG_P (y)
7045 && GET_CODE (x) == NEG
7046 && (op == EQ || op == NE))
7049 /* This is a special case that is used by combine to allow a
7050 comparison of a shifted byte load to be split into a zero-extend
7051 followed by a comparison of the shifted integer (only valid for
7052 equalities and unsigned inequalities). */
7053 if (GET_MODE (x) == SImode
7054 && GET_CODE (x) == ASHIFT
7055 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7056 && GET_CODE (XEXP (x, 0)) == SUBREG
7057 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7058 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7059 && (op == EQ || op == NE
7060 || op == GEU || op == GTU || op == LTU || op == LEU)
7061 && GET_CODE (y) == CONST_INT)
7064 /* A construct for a conditional compare, if the false arm contains
7065 0, then both conditions must be true, otherwise either condition
7066 must be true. Not all conditions are possible, so CCmode is
7067 returned if it can't be done. */
7068 if (GET_CODE (x) == IF_THEN_ELSE
7069 && (XEXP (x, 2) == const0_rtx
7070 || XEXP (x, 2) == const1_rtx)
7071 && COMPARISON_P (XEXP (x, 0))
7072 && COMPARISON_P (XEXP (x, 1)))
7073 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7074 INTVAL (XEXP (x, 2)));
7076 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7077 if (GET_CODE (x) == AND
7078 && COMPARISON_P (XEXP (x, 0))
7079 && COMPARISON_P (XEXP (x, 1)))
7080 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7083 if (GET_CODE (x) == IOR
7084 && COMPARISON_P (XEXP (x, 0))
7085 && COMPARISON_P (XEXP (x, 1)))
7086 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7089 /* An operation (on Thumb) where we want to test for a single bit.
7090 This is done by shifting that bit up into the top bit of a
7091 scratch register; we can then branch on the sign bit. */
7093 && GET_MODE (x) == SImode
7094 && (op == EQ || op == NE)
7095 && GET_CODE (x) == ZERO_EXTRACT
7096 && XEXP (x, 1) == const1_rtx)
7099 /* An operation that sets the condition codes as a side-effect, the
7100 V flag is not set correctly, so we can only use comparisons where
7101 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7103 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7104 if (GET_MODE (x) == SImode
7106 && (op == EQ || op == NE || op == LT || op == GE)
7107 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7108 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7109 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7110 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7111 || GET_CODE (x) == LSHIFTRT
7112 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7113 || GET_CODE (x) == ROTATERT
7114 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
7117 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7120 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7121 && GET_CODE (x) == PLUS
7122 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7128 /* X and Y are two things to compare using CODE. Emit the compare insn and
7129 return the rtx for register 0 in the proper mode. FP means this is a
7130 floating point compare: I don't think that it is needed on the arm. */
7132 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
7134 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
7135 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
7137 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
7142 /* Generate a sequence of insns that will generate the correct return
7143 address mask depending on the physical architecture that the program
7146 arm_gen_return_addr_mask (void)
7148 rtx reg = gen_reg_rtx (Pmode);
7150 emit_insn (gen_return_addr_mask (reg));
7155 arm_reload_in_hi (rtx *operands)
7157 rtx ref = operands[1];
7159 HOST_WIDE_INT offset = 0;
7161 if (GET_CODE (ref) == SUBREG)
7163 offset = SUBREG_BYTE (ref);
7164 ref = SUBREG_REG (ref);
7167 if (GET_CODE (ref) == REG)
7169 /* We have a pseudo which has been spilt onto the stack; there
7170 are two cases here: the first where there is a simple
7171 stack-slot replacement and a second where the stack-slot is
7172 out of range, or is used as a subreg. */
7173 if (reg_equiv_mem[REGNO (ref)])
7175 ref = reg_equiv_mem[REGNO (ref)];
7176 base = find_replacement (&XEXP (ref, 0));
7179 /* The slot is out of range, or was dressed up in a SUBREG. */
7180 base = reg_equiv_address[REGNO (ref)];
7183 base = find_replacement (&XEXP (ref, 0));
7185 /* Handle the case where the address is too complex to be offset by 1. */
7186 if (GET_CODE (base) == MINUS
7187 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7189 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7191 emit_set_insn (base_plus, base);
7194 else if (GET_CODE (base) == PLUS)
7196 /* The addend must be CONST_INT, or we would have dealt with it above. */
7197 HOST_WIDE_INT hi, lo;
7199 offset += INTVAL (XEXP (base, 1));
7200 base = XEXP (base, 0);
7202 /* Rework the address into a legal sequence of insns. */
7203 /* Valid range for lo is -4095 -> 4095 */
7206 : -((-offset) & 0xfff));
7208 /* Corner case, if lo is the max offset then we would be out of range
7209 once we have added the additional 1 below, so bump the msb into the
7210 pre-loading insn(s). */
7214 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7215 ^ (HOST_WIDE_INT) 0x80000000)
7216 - (HOST_WIDE_INT) 0x80000000);
7218 gcc_assert (hi + lo == offset);
7222 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7224 /* Get the base address; addsi3 knows how to handle constants
7225 that require more than one insn. */
7226 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7232 /* Operands[2] may overlap operands[0] (though it won't overlap
7233 operands[1]), that's why we asked for a DImode reg -- so we can
7234 use the bit that does not overlap. */
7235 if (REGNO (operands[2]) == REGNO (operands[0]))
7236 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7238 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7240 emit_insn (gen_zero_extendqisi2 (scratch,
7241 gen_rtx_MEM (QImode,
7242 plus_constant (base,
7244 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
7245 gen_rtx_MEM (QImode,
7246 plus_constant (base,
7248 if (!BYTES_BIG_ENDIAN)
7249 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7250 gen_rtx_IOR (SImode,
7253 gen_rtx_SUBREG (SImode, operands[0], 0),
7257 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7258 gen_rtx_IOR (SImode,
7259 gen_rtx_ASHIFT (SImode, scratch,
7261 gen_rtx_SUBREG (SImode, operands[0], 0)));
7264 /* Handle storing a half-word to memory during reload by synthesizing as two
7265 byte stores. Take care not to clobber the input values until after we
7266 have moved them somewhere safe. This code assumes that if the DImode
7267 scratch in operands[2] overlaps either the input value or output address
7268 in some way, then that value must die in this insn (we absolutely need
7269 two scratch registers for some corner cases). */
7271 arm_reload_out_hi (rtx *operands)
7273 rtx ref = operands[0];
7274 rtx outval = operands[1];
7276 HOST_WIDE_INT offset = 0;
7278 if (GET_CODE (ref) == SUBREG)
7280 offset = SUBREG_BYTE (ref);
7281 ref = SUBREG_REG (ref);
7284 if (GET_CODE (ref) == REG)
7286 /* We have a pseudo which has been spilt onto the stack; there
7287 are two cases here: the first where there is a simple
7288 stack-slot replacement and a second where the stack-slot is
7289 out of range, or is used as a subreg. */
7290 if (reg_equiv_mem[REGNO (ref)])
7292 ref = reg_equiv_mem[REGNO (ref)];
7293 base = find_replacement (&XEXP (ref, 0));
7296 /* The slot is out of range, or was dressed up in a SUBREG. */
7297 base = reg_equiv_address[REGNO (ref)];
7300 base = find_replacement (&XEXP (ref, 0));
7302 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7304 /* Handle the case where the address is too complex to be offset by 1. */
7305 if (GET_CODE (base) == MINUS
7306 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7308 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7310 /* Be careful not to destroy OUTVAL. */
7311 if (reg_overlap_mentioned_p (base_plus, outval))
7313 /* Updating base_plus might destroy outval, see if we can
7314 swap the scratch and base_plus. */
7315 if (!reg_overlap_mentioned_p (scratch, outval))
7318 scratch = base_plus;
7323 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7325 /* Be conservative and copy OUTVAL into the scratch now,
7326 this should only be necessary if outval is a subreg
7327 of something larger than a word. */
7328 /* XXX Might this clobber base? I can't see how it can,
7329 since scratch is known to overlap with OUTVAL, and
7330 must be wider than a word. */
7331 emit_insn (gen_movhi (scratch_hi, outval));
7332 outval = scratch_hi;
7336 emit_set_insn (base_plus, base);
7339 else if (GET_CODE (base) == PLUS)
7341 /* The addend must be CONST_INT, or we would have dealt with it above. */
7342 HOST_WIDE_INT hi, lo;
7344 offset += INTVAL (XEXP (base, 1));
7345 base = XEXP (base, 0);
7347 /* Rework the address into a legal sequence of insns. */
7348 /* Valid range for lo is -4095 -> 4095 */
7351 : -((-offset) & 0xfff));
7353 /* Corner case, if lo is the max offset then we would be out of range
7354 once we have added the additional 1 below, so bump the msb into the
7355 pre-loading insn(s). */
7359 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7360 ^ (HOST_WIDE_INT) 0x80000000)
7361 - (HOST_WIDE_INT) 0x80000000);
7363 gcc_assert (hi + lo == offset);
7367 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7369 /* Be careful not to destroy OUTVAL. */
7370 if (reg_overlap_mentioned_p (base_plus, outval))
7372 /* Updating base_plus might destroy outval, see if we
7373 can swap the scratch and base_plus. */
7374 if (!reg_overlap_mentioned_p (scratch, outval))
7377 scratch = base_plus;
7382 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7384 /* Be conservative and copy outval into scratch now,
7385 this should only be necessary if outval is a
7386 subreg of something larger than a word. */
7387 /* XXX Might this clobber base? I can't see how it
7388 can, since scratch is known to overlap with
7390 emit_insn (gen_movhi (scratch_hi, outval));
7391 outval = scratch_hi;
7395 /* Get the base address; addsi3 knows how to handle constants
7396 that require more than one insn. */
7397 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7403 if (BYTES_BIG_ENDIAN)
7405 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7406 plus_constant (base, offset + 1)),
7407 gen_lowpart (QImode, outval)));
7408 emit_insn (gen_lshrsi3 (scratch,
7409 gen_rtx_SUBREG (SImode, outval, 0),
7411 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7412 gen_lowpart (QImode, scratch)));
7416 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7417 gen_lowpart (QImode, outval)));
7418 emit_insn (gen_lshrsi3 (scratch,
7419 gen_rtx_SUBREG (SImode, outval, 0),
7421 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7422 plus_constant (base, offset + 1)),
7423 gen_lowpart (QImode, scratch)));
7427 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7428 (padded to the size of a word) should be passed in a register. */
7431 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7433 if (TARGET_AAPCS_BASED)
7434 return must_pass_in_stack_var_size (mode, type);
7436 return must_pass_in_stack_var_size_or_pad (mode, type);
7440 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7441 Return true if an argument passed on the stack should be padded upwards,
7442 i.e. if the least-significant byte has useful data.
7443 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7444 aggregate types are placed in the lowest memory address. */
7447 arm_pad_arg_upward (enum machine_mode mode, tree type)
7449 if (!TARGET_AAPCS_BASED)
7450 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7452 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7459 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7460 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7461 byte of the register has useful data, and return the opposite if the
7462 most significant byte does.
7463 For AAPCS, small aggregates and small complex types are always padded
7467 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7468 tree type, int first ATTRIBUTE_UNUSED)
7470 if (TARGET_AAPCS_BASED
7472 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7473 && int_size_in_bytes (type) <= 4)
7476 /* Otherwise, use default padding. */
7477 return !BYTES_BIG_ENDIAN;
7481 /* Print a symbolic form of X to the debug file, F. */
7483 arm_print_value (FILE *f, rtx x)
7485 switch (GET_CODE (x))
7488 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7492 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7500 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7502 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7503 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7511 fprintf (f, "\"%s\"", XSTR (x, 0));
7515 fprintf (f, "`%s'", XSTR (x, 0));
7519 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7523 arm_print_value (f, XEXP (x, 0));
7527 arm_print_value (f, XEXP (x, 0));
7529 arm_print_value (f, XEXP (x, 1));
7537 fprintf (f, "????");
7542 /* Routines for manipulation of the constant pool. */
7544 /* Arm instructions cannot load a large constant directly into a
7545 register; they have to come from a pc relative load. The constant
7546 must therefore be placed in the addressable range of the pc
7547 relative load. Depending on the precise pc relative load
7548 instruction the range is somewhere between 256 bytes and 4k. This
7549 means that we often have to dump a constant inside a function, and
7550 generate code to branch around it.
7552 It is important to minimize this, since the branches will slow
7553 things down and make the code larger.
7555 Normally we can hide the table after an existing unconditional
7556 branch so that there is no interruption of the flow, but in the
7557 worst case the code looks like this:
7575 We fix this by performing a scan after scheduling, which notices
7576 which instructions need to have their operands fetched from the
7577 constant table and builds the table.
7579 The algorithm starts by building a table of all the constants that
7580 need fixing up and all the natural barriers in the function (places
7581 where a constant table can be dropped without breaking the flow).
7582 For each fixup we note how far the pc-relative replacement will be
7583 able to reach and the offset of the instruction into the function.
7585 Having built the table we then group the fixes together to form
7586 tables that are as large as possible (subject to addressing
7587 constraints) and emit each table of constants after the last
7588 barrier that is within range of all the instructions in the group.
7589 If a group does not contain a barrier, then we forcibly create one
7590 by inserting a jump instruction into the flow. Once the table has
7591 been inserted, the insns are then modified to reference the
7592 relevant entry in the pool.
7594 Possible enhancements to the algorithm (not implemented) are:
7596 1) For some processors and object formats, there may be benefit in
7597 aligning the pools to the start of cache lines; this alignment
7598 would need to be taken into account when calculating addressability
7601 /* These typedefs are located at the start of this file, so that
7602 they can be used in the prototypes there. This comment is to
7603 remind readers of that fact so that the following structures
7604 can be understood more easily.
7606 typedef struct minipool_node Mnode;
7607 typedef struct minipool_fixup Mfix; */
7609 struct minipool_node
7611 /* Doubly linked chain of entries. */
7614 /* The maximum offset into the code that this entry can be placed. While
7615 pushing fixes for forward references, all entries are sorted in order
7616 of increasing max_address. */
7617 HOST_WIDE_INT max_address;
7618 /* Similarly for an entry inserted for a backwards ref. */
7619 HOST_WIDE_INT min_address;
7620 /* The number of fixes referencing this entry. This can become zero
7621 if we "unpush" an entry. In this case we ignore the entry when we
7622 come to emit the code. */
7624 /* The offset from the start of the minipool. */
7625 HOST_WIDE_INT offset;
7626 /* The value in table. */
7628 /* The mode of value. */
7629 enum machine_mode mode;
7630 /* The size of the value. With iWMMXt enabled
7631 sizes > 4 also imply an alignment of 8-bytes. */
7635 struct minipool_fixup
7639 HOST_WIDE_INT address;
7641 enum machine_mode mode;
7645 HOST_WIDE_INT forwards;
7646 HOST_WIDE_INT backwards;
7649 /* Fixes less than a word need padding out to a word boundary. */
7650 #define MINIPOOL_FIX_SIZE(mode) \
7651 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7653 static Mnode * minipool_vector_head;
7654 static Mnode * minipool_vector_tail;
7655 static rtx minipool_vector_label;
7656 static int minipool_pad;
7658 /* The linked list of all minipool fixes required for this function. */
7659 Mfix * minipool_fix_head;
7660 Mfix * minipool_fix_tail;
7661 /* The fix entry for the current minipool, once it has been placed. */
7662 Mfix * minipool_barrier;
7664 /* Determines if INSN is the start of a jump table. Returns the end
7665 of the TABLE or NULL_RTX. */
7667 is_jump_table (rtx insn)
7671 if (GET_CODE (insn) == JUMP_INSN
7672 && JUMP_LABEL (insn) != NULL
7673 && ((table = next_real_insn (JUMP_LABEL (insn)))
7674 == next_real_insn (insn))
7676 && GET_CODE (table) == JUMP_INSN
7677 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7678 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7684 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7685 #define JUMP_TABLES_IN_TEXT_SECTION 0
7688 static HOST_WIDE_INT
7689 get_jump_table_size (rtx insn)
7691 /* ADDR_VECs only take room if read-only data does into the text
7693 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7695 rtx body = PATTERN (insn);
7696 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7698 HOST_WIDE_INT modesize;
7700 modesize = GET_MODE_SIZE (GET_MODE (body));
7701 size = modesize * XVECLEN (body, elt);
7705 /* Round up size of TBB table to a hafword boundary. */
7706 size = (size + 1) & ~(HOST_WIDE_INT)1;
7709 /* No padding neccessary for TBH. */
7712 /* Add two bytes for alignment on Thumb. */
7725 /* Move a minipool fix MP from its current location to before MAX_MP.
7726 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7727 constraints may need updating. */
7729 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7730 HOST_WIDE_INT max_address)
7732 /* The code below assumes these are different. */
7733 gcc_assert (mp != max_mp);
7737 if (max_address < mp->max_address)
7738 mp->max_address = max_address;
7742 if (max_address > max_mp->max_address - mp->fix_size)
7743 mp->max_address = max_mp->max_address - mp->fix_size;
7745 mp->max_address = max_address;
7747 /* Unlink MP from its current position. Since max_mp is non-null,
7748 mp->prev must be non-null. */
7749 mp->prev->next = mp->next;
7750 if (mp->next != NULL)
7751 mp->next->prev = mp->prev;
7753 minipool_vector_tail = mp->prev;
7755 /* Re-insert it before MAX_MP. */
7757 mp->prev = max_mp->prev;
7760 if (mp->prev != NULL)
7761 mp->prev->next = mp;
7763 minipool_vector_head = mp;
7766 /* Save the new entry. */
7769 /* Scan over the preceding entries and adjust their addresses as
7771 while (mp->prev != NULL
7772 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7774 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7781 /* Add a constant to the minipool for a forward reference. Returns the
7782 node added or NULL if the constant will not fit in this pool. */
7784 add_minipool_forward_ref (Mfix *fix)
7786 /* If set, max_mp is the first pool_entry that has a lower
7787 constraint than the one we are trying to add. */
7788 Mnode * max_mp = NULL;
7789 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
7792 /* If the minipool starts before the end of FIX->INSN then this FIX
7793 can not be placed into the current pool. Furthermore, adding the
7794 new constant pool entry may cause the pool to start FIX_SIZE bytes
7796 if (minipool_vector_head &&
7797 (fix->address + get_attr_length (fix->insn)
7798 >= minipool_vector_head->max_address - fix->fix_size))
7801 /* Scan the pool to see if a constant with the same value has
7802 already been added. While we are doing this, also note the
7803 location where we must insert the constant if it doesn't already
7805 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7807 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7808 && fix->mode == mp->mode
7809 && (GET_CODE (fix->value) != CODE_LABEL
7810 || (CODE_LABEL_NUMBER (fix->value)
7811 == CODE_LABEL_NUMBER (mp->value)))
7812 && rtx_equal_p (fix->value, mp->value))
7814 /* More than one fix references this entry. */
7816 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7819 /* Note the insertion point if necessary. */
7821 && mp->max_address > max_address)
7824 /* If we are inserting an 8-bytes aligned quantity and
7825 we have not already found an insertion point, then
7826 make sure that all such 8-byte aligned quantities are
7827 placed at the start of the pool. */
7828 if (ARM_DOUBLEWORD_ALIGN
7830 && fix->fix_size == 8
7831 && mp->fix_size != 8)
7834 max_address = mp->max_address;
7838 /* The value is not currently in the minipool, so we need to create
7839 a new entry for it. If MAX_MP is NULL, the entry will be put on
7840 the end of the list since the placement is less constrained than
7841 any existing entry. Otherwise, we insert the new fix before
7842 MAX_MP and, if necessary, adjust the constraints on the other
7845 mp->fix_size = fix->fix_size;
7846 mp->mode = fix->mode;
7847 mp->value = fix->value;
7849 /* Not yet required for a backwards ref. */
7850 mp->min_address = -65536;
7854 mp->max_address = max_address;
7856 mp->prev = minipool_vector_tail;
7858 if (mp->prev == NULL)
7860 minipool_vector_head = mp;
7861 minipool_vector_label = gen_label_rtx ();
7864 mp->prev->next = mp;
7866 minipool_vector_tail = mp;
7870 if (max_address > max_mp->max_address - mp->fix_size)
7871 mp->max_address = max_mp->max_address - mp->fix_size;
7873 mp->max_address = max_address;
7876 mp->prev = max_mp->prev;
7878 if (mp->prev != NULL)
7879 mp->prev->next = mp;
7881 minipool_vector_head = mp;
7884 /* Save the new entry. */
7887 /* Scan over the preceding entries and adjust their addresses as
7889 while (mp->prev != NULL
7890 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7892 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7900 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7901 HOST_WIDE_INT min_address)
7903 HOST_WIDE_INT offset;
7905 /* The code below assumes these are different. */
7906 gcc_assert (mp != min_mp);
7910 if (min_address > mp->min_address)
7911 mp->min_address = min_address;
7915 /* We will adjust this below if it is too loose. */
7916 mp->min_address = min_address;
7918 /* Unlink MP from its current position. Since min_mp is non-null,
7919 mp->next must be non-null. */
7920 mp->next->prev = mp->prev;
7921 if (mp->prev != NULL)
7922 mp->prev->next = mp->next;
7924 minipool_vector_head = mp->next;
7926 /* Reinsert it after MIN_MP. */
7928 mp->next = min_mp->next;
7930 if (mp->next != NULL)
7931 mp->next->prev = mp;
7933 minipool_vector_tail = mp;
7939 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7941 mp->offset = offset;
7942 if (mp->refcount > 0)
7943 offset += mp->fix_size;
7945 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7946 mp->next->min_address = mp->min_address + mp->fix_size;
7952 /* Add a constant to the minipool for a backward reference. Returns the
7953 node added or NULL if the constant will not fit in this pool.
7955 Note that the code for insertion for a backwards reference can be
7956 somewhat confusing because the calculated offsets for each fix do
7957 not take into account the size of the pool (which is still under
7960 add_minipool_backward_ref (Mfix *fix)
7962 /* If set, min_mp is the last pool_entry that has a lower constraint
7963 than the one we are trying to add. */
7964 Mnode *min_mp = NULL;
7965 /* This can be negative, since it is only a constraint. */
7966 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7969 /* If we can't reach the current pool from this insn, or if we can't
7970 insert this entry at the end of the pool without pushing other
7971 fixes out of range, then we don't try. This ensures that we
7972 can't fail later on. */
7973 if (min_address >= minipool_barrier->address
7974 || (minipool_vector_tail->min_address + fix->fix_size
7975 >= minipool_barrier->address))
7978 /* Scan the pool to see if a constant with the same value has
7979 already been added. While we are doing this, also note the
7980 location where we must insert the constant if it doesn't already
7982 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7984 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7985 && fix->mode == mp->mode
7986 && (GET_CODE (fix->value) != CODE_LABEL
7987 || (CODE_LABEL_NUMBER (fix->value)
7988 == CODE_LABEL_NUMBER (mp->value)))
7989 && rtx_equal_p (fix->value, mp->value)
7990 /* Check that there is enough slack to move this entry to the
7991 end of the table (this is conservative). */
7993 > (minipool_barrier->address
7994 + minipool_vector_tail->offset
7995 + minipool_vector_tail->fix_size)))
7998 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8002 mp->min_address += fix->fix_size;
8005 /* Note the insertion point if necessary. */
8006 if (mp->min_address < min_address)
8008 /* For now, we do not allow the insertion of 8-byte alignment
8009 requiring nodes anywhere but at the start of the pool. */
8010 if (ARM_DOUBLEWORD_ALIGN
8011 && fix->fix_size == 8 && mp->fix_size != 8)
8016 else if (mp->max_address
8017 < minipool_barrier->address + mp->offset + fix->fix_size)
8019 /* Inserting before this entry would push the fix beyond
8020 its maximum address (which can happen if we have
8021 re-located a forwards fix); force the new fix to come
8024 min_address = mp->min_address + fix->fix_size;
8026 /* If we are inserting an 8-bytes aligned quantity and
8027 we have not already found an insertion point, then
8028 make sure that all such 8-byte aligned quantities are
8029 placed at the start of the pool. */
8030 else if (ARM_DOUBLEWORD_ALIGN
8032 && fix->fix_size == 8
8033 && mp->fix_size < 8)
8036 min_address = mp->min_address + fix->fix_size;
8041 /* We need to create a new entry. */
8043 mp->fix_size = fix->fix_size;
8044 mp->mode = fix->mode;
8045 mp->value = fix->value;
8047 mp->max_address = minipool_barrier->address + 65536;
8049 mp->min_address = min_address;
8054 mp->next = minipool_vector_head;
8056 if (mp->next == NULL)
8058 minipool_vector_tail = mp;
8059 minipool_vector_label = gen_label_rtx ();
8062 mp->next->prev = mp;
8064 minipool_vector_head = mp;
8068 mp->next = min_mp->next;
8072 if (mp->next != NULL)
8073 mp->next->prev = mp;
8075 minipool_vector_tail = mp;
8078 /* Save the new entry. */
8086 /* Scan over the following entries and adjust their offsets. */
8087 while (mp->next != NULL)
8089 if (mp->next->min_address < mp->min_address + mp->fix_size)
8090 mp->next->min_address = mp->min_address + mp->fix_size;
8093 mp->next->offset = mp->offset + mp->fix_size;
8095 mp->next->offset = mp->offset;
8104 assign_minipool_offsets (Mfix *barrier)
8106 HOST_WIDE_INT offset = 0;
8109 minipool_barrier = barrier;
8111 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8113 mp->offset = offset;
8115 if (mp->refcount > 0)
8116 offset += mp->fix_size;
8120 /* Output the literal table */
8122 dump_minipool (rtx scan)
8128 if (ARM_DOUBLEWORD_ALIGN)
8129 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8130 if (mp->refcount > 0 && mp->fix_size == 8)
8138 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8139 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
8141 scan = emit_label_after (gen_label_rtx (), scan);
8142 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
8143 scan = emit_label_after (minipool_vector_label, scan);
8145 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8147 if (mp->refcount > 0)
8152 ";; Offset %u, min %ld, max %ld ",
8153 (unsigned) mp->offset, (unsigned long) mp->min_address,
8154 (unsigned long) mp->max_address);
8155 arm_print_value (dump_file, mp->value);
8156 fputc ('\n', dump_file);
8159 switch (mp->fix_size)
8161 #ifdef HAVE_consttable_1
8163 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8167 #ifdef HAVE_consttable_2
8169 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8173 #ifdef HAVE_consttable_4
8175 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8179 #ifdef HAVE_consttable_8
8181 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8194 minipool_vector_head = minipool_vector_tail = NULL;
8195 scan = emit_insn_after (gen_consttable_end (), scan);
8196 scan = emit_barrier_after (scan);
8199 /* Return the cost of forcibly inserting a barrier after INSN. */
8201 arm_barrier_cost (rtx insn)
8203 /* Basing the location of the pool on the loop depth is preferable,
8204 but at the moment, the basic block information seems to be
8205 corrupt by this stage of the compilation. */
8207 rtx next = next_nonnote_insn (insn);
8209 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8212 switch (GET_CODE (insn))
8215 /* It will always be better to place the table before the label, rather
8224 return base_cost - 10;
8227 return base_cost + 10;
8231 /* Find the best place in the insn stream in the range
8232 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8233 Create the barrier by inserting a jump and add a new fix entry for
8236 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
8238 HOST_WIDE_INT count = 0;
8240 rtx from = fix->insn;
8241 /* The instruction after which we will insert the jump. */
8242 rtx selected = NULL;
8244 /* The address at which the jump instruction will be placed. */
8245 HOST_WIDE_INT selected_address;
8247 HOST_WIDE_INT max_count = max_address - fix->address;
8248 rtx label = gen_label_rtx ();
8250 selected_cost = arm_barrier_cost (from);
8251 selected_address = fix->address;
8253 while (from && count < max_count)
8258 /* This code shouldn't have been called if there was a natural barrier
8260 gcc_assert (GET_CODE (from) != BARRIER);
8262 /* Count the length of this insn. */
8263 count += get_attr_length (from);
8265 /* If there is a jump table, add its length. */
8266 tmp = is_jump_table (from);
8269 count += get_jump_table_size (tmp);
8271 /* Jump tables aren't in a basic block, so base the cost on
8272 the dispatch insn. If we select this location, we will
8273 still put the pool after the table. */
8274 new_cost = arm_barrier_cost (from);
8276 if (count < max_count
8277 && (!selected || new_cost <= selected_cost))
8280 selected_cost = new_cost;
8281 selected_address = fix->address + count;
8284 /* Continue after the dispatch table. */
8285 from = NEXT_INSN (tmp);
8289 new_cost = arm_barrier_cost (from);
8291 if (count < max_count
8292 && (!selected || new_cost <= selected_cost))
8295 selected_cost = new_cost;
8296 selected_address = fix->address + count;
8299 from = NEXT_INSN (from);
8302 /* Make sure that we found a place to insert the jump. */
8303 gcc_assert (selected);
8305 /* Create a new JUMP_INSN that branches around a barrier. */
8306 from = emit_jump_insn_after (gen_jump (label), selected);
8307 JUMP_LABEL (from) = label;
8308 barrier = emit_barrier_after (from);
8309 emit_label_after (label, barrier);
8311 /* Create a minipool barrier entry for the new barrier. */
8312 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
8313 new_fix->insn = barrier;
8314 new_fix->address = selected_address;
8315 new_fix->next = fix->next;
8316 fix->next = new_fix;
8321 /* Record that there is a natural barrier in the insn stream at
8324 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
8326 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8329 fix->address = address;
8332 if (minipool_fix_head != NULL)
8333 minipool_fix_tail->next = fix;
8335 minipool_fix_head = fix;
8337 minipool_fix_tail = fix;
8340 /* Record INSN, which will need fixing up to load a value from the
8341 minipool. ADDRESS is the offset of the insn since the start of the
8342 function; LOC is a pointer to the part of the insn which requires
8343 fixing; VALUE is the constant that must be loaded, which is of type
8346 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8347 enum machine_mode mode, rtx value)
8349 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8351 #ifdef AOF_ASSEMBLER
8352 /* PIC symbol references need to be converted into offsets into the
8354 /* XXX This shouldn't be done here. */
8355 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8356 value = aof_pic_entry (value);
8357 #endif /* AOF_ASSEMBLER */
8360 fix->address = address;
8363 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8365 fix->forwards = get_attr_pool_range (insn);
8366 fix->backwards = get_attr_neg_pool_range (insn);
8367 fix->minipool = NULL;
8369 /* If an insn doesn't have a range defined for it, then it isn't
8370 expecting to be reworked by this code. Better to stop now than
8371 to generate duff assembly code. */
8372 gcc_assert (fix->forwards || fix->backwards);
8374 /* If an entry requires 8-byte alignment then assume all constant pools
8375 require 4 bytes of padding. Trying to do this later on a per-pool
8376 basis is awkward because existing pool entries have to be modified. */
8377 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8383 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8384 GET_MODE_NAME (mode),
8385 INSN_UID (insn), (unsigned long) address,
8386 -1 * (long)fix->backwards, (long)fix->forwards);
8387 arm_print_value (dump_file, fix->value);
8388 fprintf (dump_file, "\n");
8391 /* Add it to the chain of fixes. */
8394 if (minipool_fix_head != NULL)
8395 minipool_fix_tail->next = fix;
8397 minipool_fix_head = fix;
8399 minipool_fix_tail = fix;
8402 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8403 Returns the number of insns needed, or 99 if we don't know how to
8406 arm_const_double_inline_cost (rtx val)
8408 rtx lowpart, highpart;
8409 enum machine_mode mode;
8411 mode = GET_MODE (val);
8413 if (mode == VOIDmode)
8416 gcc_assert (GET_MODE_SIZE (mode) == 8);
8418 lowpart = gen_lowpart (SImode, val);
8419 highpart = gen_highpart_mode (SImode, mode, val);
8421 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8422 gcc_assert (GET_CODE (highpart) == CONST_INT);
8424 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8425 NULL_RTX, NULL_RTX, 0, 0)
8426 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8427 NULL_RTX, NULL_RTX, 0, 0));
8430 /* Return true if it is worthwhile to split a 64-bit constant into two
8431 32-bit operations. This is the case if optimizing for size, or
8432 if we have load delay slots, or if one 32-bit part can be done with
8433 a single data operation. */
8435 arm_const_double_by_parts (rtx val)
8437 enum machine_mode mode = GET_MODE (val);
8440 if (optimize_size || arm_ld_sched)
8443 if (mode == VOIDmode)
8446 part = gen_highpart_mode (SImode, mode, val);
8448 gcc_assert (GET_CODE (part) == CONST_INT);
8450 if (const_ok_for_arm (INTVAL (part))
8451 || const_ok_for_arm (~INTVAL (part)))
8454 part = gen_lowpart (SImode, val);
8456 gcc_assert (GET_CODE (part) == CONST_INT);
8458 if (const_ok_for_arm (INTVAL (part))
8459 || const_ok_for_arm (~INTVAL (part)))
8465 /* Scan INSN and note any of its operands that need fixing.
8466 If DO_PUSHES is false we do not actually push any of the fixups
8467 needed. The function returns TRUE if any fixups were needed/pushed.
8468 This is used by arm_memory_load_p() which needs to know about loads
8469 of constants that will be converted into minipool loads. */
8471 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8473 bool result = false;
8476 extract_insn (insn);
8478 if (!constrain_operands (1))
8479 fatal_insn_not_found (insn);
8481 if (recog_data.n_alternatives == 0)
8484 /* Fill in recog_op_alt with information about the constraints of
8486 preprocess_constraints ();
8488 for (opno = 0; opno < recog_data.n_operands; opno++)
8490 /* Things we need to fix can only occur in inputs. */
8491 if (recog_data.operand_type[opno] != OP_IN)
8494 /* If this alternative is a memory reference, then any mention
8495 of constants in this alternative is really to fool reload
8496 into allowing us to accept one there. We need to fix them up
8497 now so that we output the right code. */
8498 if (recog_op_alt[opno][which_alternative].memory_ok)
8500 rtx op = recog_data.operand[opno];
8502 if (CONSTANT_P (op))
8505 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8506 recog_data.operand_mode[opno], op);
8509 else if (GET_CODE (op) == MEM
8510 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8511 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8515 rtx cop = avoid_constant_pool_reference (op);
8517 /* Casting the address of something to a mode narrower
8518 than a word can cause avoid_constant_pool_reference()
8519 to return the pool reference itself. That's no good to
8520 us here. Lets just hope that we can use the
8521 constant pool value directly. */
8523 cop = get_pool_constant (XEXP (op, 0));
8525 push_minipool_fix (insn, address,
8526 recog_data.operand_loc[opno],
8527 recog_data.operand_mode[opno], cop);
8538 /* Gcc puts the pool in the wrong place for ARM, since we can only
8539 load addresses a limited distance around the pc. We do some
8540 special munging to move the constant pool values to the correct
8541 point in the code. */
8546 HOST_WIDE_INT address = 0;
8549 minipool_fix_head = minipool_fix_tail = NULL;
8551 /* The first insn must always be a note, or the code below won't
8552 scan it properly. */
8553 insn = get_insns ();
8554 gcc_assert (GET_CODE (insn) == NOTE);
8557 /* Scan all the insns and record the operands that will need fixing. */
8558 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8560 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8561 && (arm_cirrus_insn_p (insn)
8562 || GET_CODE (insn) == JUMP_INSN
8563 || arm_memory_load_p (insn)))
8564 cirrus_reorg (insn);
8566 if (GET_CODE (insn) == BARRIER)
8567 push_minipool_barrier (insn, address);
8568 else if (INSN_P (insn))
8572 note_invalid_constants (insn, address, true);
8573 address += get_attr_length (insn);
8575 /* If the insn is a vector jump, add the size of the table
8576 and skip the table. */
8577 if ((table = is_jump_table (insn)) != NULL)
8579 address += get_jump_table_size (table);
8585 fix = minipool_fix_head;
8587 /* Now scan the fixups and perform the required changes. */
8592 Mfix * last_added_fix;
8593 Mfix * last_barrier = NULL;
8596 /* Skip any further barriers before the next fix. */
8597 while (fix && GET_CODE (fix->insn) == BARRIER)
8600 /* No more fixes. */
8604 last_added_fix = NULL;
8606 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8608 if (GET_CODE (ftmp->insn) == BARRIER)
8610 if (ftmp->address >= minipool_vector_head->max_address)
8613 last_barrier = ftmp;
8615 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8618 last_added_fix = ftmp; /* Keep track of the last fix added. */
8621 /* If we found a barrier, drop back to that; any fixes that we
8622 could have reached but come after the barrier will now go in
8623 the next mini-pool. */
8624 if (last_barrier != NULL)
8626 /* Reduce the refcount for those fixes that won't go into this
8628 for (fdel = last_barrier->next;
8629 fdel && fdel != ftmp;
8632 fdel->minipool->refcount--;
8633 fdel->minipool = NULL;
8636 ftmp = last_barrier;
8640 /* ftmp is first fix that we can't fit into this pool and
8641 there no natural barriers that we could use. Insert a
8642 new barrier in the code somewhere between the previous
8643 fix and this one, and arrange to jump around it. */
8644 HOST_WIDE_INT max_address;
8646 /* The last item on the list of fixes must be a barrier, so
8647 we can never run off the end of the list of fixes without
8648 last_barrier being set. */
8651 max_address = minipool_vector_head->max_address;
8652 /* Check that there isn't another fix that is in range that
8653 we couldn't fit into this pool because the pool was
8654 already too large: we need to put the pool before such an
8655 instruction. The pool itself may come just after the
8656 fix because create_fix_barrier also allows space for a
8657 jump instruction. */
8658 if (ftmp->address < max_address)
8659 max_address = ftmp->address + 1;
8661 last_barrier = create_fix_barrier (last_added_fix, max_address);
8664 assign_minipool_offsets (last_barrier);
8668 if (GET_CODE (ftmp->insn) != BARRIER
8669 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8676 /* Scan over the fixes we have identified for this pool, fixing them
8677 up and adding the constants to the pool itself. */
8678 for (this_fix = fix; this_fix && ftmp != this_fix;
8679 this_fix = this_fix->next)
8680 if (GET_CODE (this_fix->insn) != BARRIER)
8683 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8684 minipool_vector_label),
8685 this_fix->minipool->offset);
8686 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8689 dump_minipool (last_barrier->insn);
8693 /* From now on we must synthesize any constants that we can't handle
8694 directly. This can happen if the RTL gets split during final
8695 instruction generation. */
8696 after_arm_reorg = 1;
8698 /* Free the minipool memory. */
8699 obstack_free (&minipool_obstack, minipool_startobj);
8702 /* Routines to output assembly language. */
8704 /* If the rtx is the correct value then return the string of the number.
8705 In this way we can ensure that valid double constants are generated even
8706 when cross compiling. */
8708 fp_immediate_constant (rtx x)
8713 if (!fp_consts_inited)
8716 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8717 for (i = 0; i < 8; i++)
8718 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8719 return strings_fp[i];
8724 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8726 fp_const_from_val (REAL_VALUE_TYPE *r)
8730 if (!fp_consts_inited)
8733 for (i = 0; i < 8; i++)
8734 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8735 return strings_fp[i];
8740 /* Output the operands of a LDM/STM instruction to STREAM.
8741 MASK is the ARM register set mask of which only bits 0-15 are important.
8742 REG is the base register, either the frame pointer or the stack pointer,
8743 INSTR is the possibly suffixed load or store instruction.
8744 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8747 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8748 unsigned long mask, int rfe)
8751 bool not_first = FALSE;
8753 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
8754 fputc ('\t', stream);
8755 asm_fprintf (stream, instr, reg);
8756 fputc ('{', stream);
8758 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8759 if (mask & (1 << i))
8762 fprintf (stream, ", ");
8764 asm_fprintf (stream, "%r", i);
8769 fprintf (stream, "}^\n");
8771 fprintf (stream, "}\n");
8775 /* Output a FLDMD instruction to STREAM.
8776 BASE if the register containing the address.
8777 REG and COUNT specify the register range.
8778 Extra registers may be added to avoid hardware bugs.
8780 We output FLDMD even for ARMv5 VFP implementations. Although
8781 FLDMD is technically not supported until ARMv6, it is believed
8782 that all VFP implementations support its use in this context. */
8785 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
8789 /* Workaround ARM10 VFPr1 bug. */
8790 if (count == 2 && !arm_arch6)
8797 fputc ('\t', stream);
8798 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
8800 for (i = reg; i < reg + count; i++)
8803 fputs (", ", stream);
8804 asm_fprintf (stream, "d%d", i);
8806 fputs ("}\n", stream);
8811 /* Output the assembly for a store multiple. */
8814 vfp_output_fstmd (rtx * operands)
8821 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
8822 p = strlen (pattern);
8824 gcc_assert (GET_CODE (operands[1]) == REG);
8826 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8827 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8829 p += sprintf (&pattern[p], ", d%d", base + i);
8831 strcpy (&pattern[p], "}");
8833 output_asm_insn (pattern, operands);
8838 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8839 number of bytes pushed. */
8842 vfp_emit_fstmd (int base_reg, int count)
8849 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8850 register pairs are stored by a store multiple insn. We avoid this
8851 by pushing an extra pair. */
8852 if (count == 2 && !arm_arch6)
8854 if (base_reg == LAST_VFP_REGNUM - 3)
8859 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8860 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8862 reg = gen_rtx_REG (DFmode, base_reg);
8866 = gen_rtx_SET (VOIDmode,
8867 gen_frame_mem (BLKmode,
8868 gen_rtx_PRE_DEC (BLKmode,
8869 stack_pointer_rtx)),
8870 gen_rtx_UNSPEC (BLKmode,
8874 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8875 plus_constant (stack_pointer_rtx, -(count * 8)));
8876 RTX_FRAME_RELATED_P (tmp) = 1;
8877 XVECEXP (dwarf, 0, 0) = tmp;
8879 tmp = gen_rtx_SET (VOIDmode,
8880 gen_frame_mem (DFmode, stack_pointer_rtx),
8882 RTX_FRAME_RELATED_P (tmp) = 1;
8883 XVECEXP (dwarf, 0, 1) = tmp;
8885 for (i = 1; i < count; i++)
8887 reg = gen_rtx_REG (DFmode, base_reg);
8889 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8891 tmp = gen_rtx_SET (VOIDmode,
8892 gen_frame_mem (DFmode,
8893 plus_constant (stack_pointer_rtx,
8896 RTX_FRAME_RELATED_P (tmp) = 1;
8897 XVECEXP (dwarf, 0, i + 1) = tmp;
8900 par = emit_insn (par);
8901 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8903 RTX_FRAME_RELATED_P (par) = 1;
8909 /* Output a 'call' insn. */
8911 output_call (rtx *operands)
8913 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8915 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8916 if (REGNO (operands[0]) == LR_REGNUM)
8918 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8919 output_asm_insn ("mov%?\t%0, %|lr", operands);
8922 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8924 if (TARGET_INTERWORK || arm_arch4t)
8925 output_asm_insn ("bx%?\t%0", operands);
8927 output_asm_insn ("mov%?\t%|pc, %0", operands);
8932 /* Output a 'call' insn that is a reference in memory. */
8934 output_call_mem (rtx *operands)
8936 if (TARGET_INTERWORK && !arm_arch5)
8938 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8939 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8940 output_asm_insn ("bx%?\t%|ip", operands);
8942 else if (regno_use_in (LR_REGNUM, operands[0]))
8944 /* LR is used in the memory address. We load the address in the
8945 first instruction. It's safe to use IP as the target of the
8946 load since the call will kill it anyway. */
8947 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8949 output_asm_insn ("blx%?\t%|ip", operands);
8952 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8954 output_asm_insn ("bx%?\t%|ip", operands);
8956 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8961 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8962 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8969 /* Output a move from arm registers to an fpa registers.
8970 OPERANDS[0] is an fpa register.
8971 OPERANDS[1] is the first registers of an arm register pair. */
8973 output_mov_long_double_fpa_from_arm (rtx *operands)
8975 int arm_reg0 = REGNO (operands[1]);
8978 gcc_assert (arm_reg0 != IP_REGNUM);
8980 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8981 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8982 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8984 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
8985 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8990 /* Output a move from an fpa register to arm registers.
8991 OPERANDS[0] is the first registers of an arm register pair.
8992 OPERANDS[1] is an fpa register. */
8994 output_mov_long_double_arm_from_fpa (rtx *operands)
8996 int arm_reg0 = REGNO (operands[0]);
8999 gcc_assert (arm_reg0 != IP_REGNUM);
9001 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9002 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9003 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9005 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
9006 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9010 /* Output a move from arm registers to arm registers of a long double
9011 OPERANDS[0] is the destination.
9012 OPERANDS[1] is the source. */
9014 output_mov_long_double_arm_from_arm (rtx *operands)
9016 /* We have to be careful here because the two might overlap. */
9017 int dest_start = REGNO (operands[0]);
9018 int src_start = REGNO (operands[1]);
9022 if (dest_start < src_start)
9024 for (i = 0; i < 3; i++)
9026 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9027 ops[1] = gen_rtx_REG (SImode, src_start + i);
9028 output_asm_insn ("mov%?\t%0, %1", ops);
9033 for (i = 2; i >= 0; i--)
9035 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9036 ops[1] = gen_rtx_REG (SImode, src_start + i);
9037 output_asm_insn ("mov%?\t%0, %1", ops);
9045 /* Output a move from arm registers to an fpa registers.
9046 OPERANDS[0] is an fpa register.
9047 OPERANDS[1] is the first registers of an arm register pair. */
9049 output_mov_double_fpa_from_arm (rtx *operands)
9051 int arm_reg0 = REGNO (operands[1]);
9054 gcc_assert (arm_reg0 != IP_REGNUM);
9056 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9057 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9058 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
9059 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
9063 /* Output a move from an fpa register to arm registers.
9064 OPERANDS[0] is the first registers of an arm register pair.
9065 OPERANDS[1] is an fpa register. */
9067 output_mov_double_arm_from_fpa (rtx *operands)
9069 int arm_reg0 = REGNO (operands[0]);
9072 gcc_assert (arm_reg0 != IP_REGNUM);
9074 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9075 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9076 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
9077 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
9081 /* Output a move between double words.
9082 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9083 or MEM<-REG and all MEMs must be offsettable addresses. */
9085 output_move_double (rtx *operands)
9087 enum rtx_code code0 = GET_CODE (operands[0]);
9088 enum rtx_code code1 = GET_CODE (operands[1]);
9093 int reg0 = REGNO (operands[0]);
9095 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9097 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9099 switch (GET_CODE (XEXP (operands[1], 0)))
9102 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
9106 gcc_assert (TARGET_LDRD);
9107 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
9112 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9114 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
9118 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
9122 gcc_assert (TARGET_LDRD);
9123 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
9128 otherops[0] = operands[0];
9129 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9130 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
9132 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
9134 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9136 /* Registers overlap so split out the increment. */
9137 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9138 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
9141 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9145 /* We only allow constant increments, so this is safe. */
9146 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
9152 output_asm_insn ("adr%?\t%0, %1", operands);
9153 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
9156 /* ??? This needs checking for thumb2. */
9158 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9159 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9161 otherops[0] = operands[0];
9162 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9163 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
9165 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
9167 if (GET_CODE (otherops[2]) == CONST_INT)
9169 switch ((int) INTVAL (otherops[2]))
9172 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
9177 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
9182 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
9187 && (GET_CODE (otherops[2]) == REG
9188 || (GET_CODE (otherops[2]) == CONST_INT
9189 && INTVAL (otherops[2]) > -256
9190 && INTVAL (otherops[2]) < 256)))
9192 if (reg_overlap_mentioned_p (otherops[0],
9195 /* Swap base and index registers over to
9196 avoid a conflict. */
9197 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9198 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
9200 /* If both registers conflict, it will usually
9201 have been fixed by a splitter. */
9202 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9204 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9205 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9209 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
9213 if (GET_CODE (otherops[2]) == CONST_INT)
9215 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
9216 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
9218 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9221 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9224 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
9226 return "ldm%(ia%)\t%0, %M0";
9230 otherops[1] = adjust_address (operands[1], SImode, 4);
9231 /* Take care of overlapping base/data reg. */
9232 if (reg_mentioned_p (operands[0], operands[1]))
9234 output_asm_insn ("ldr%?\t%0, %1", otherops);
9235 output_asm_insn ("ldr%?\t%0, %1", operands);
9239 output_asm_insn ("ldr%?\t%0, %1", operands);
9240 output_asm_insn ("ldr%?\t%0, %1", otherops);
9247 /* Constraints should ensure this. */
9248 gcc_assert (code0 == MEM && code1 == REG);
9249 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
9251 switch (GET_CODE (XEXP (operands[0], 0)))
9254 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9258 gcc_assert (TARGET_LDRD);
9259 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9264 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
9266 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9270 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9274 gcc_assert (TARGET_LDRD);
9275 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
9280 otherops[0] = operands[1];
9281 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
9282 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
9284 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9285 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
9287 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9291 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
9292 if (GET_CODE (otherops[2]) == CONST_INT)
9294 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
9297 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
9303 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
9309 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
9314 && (GET_CODE (otherops[2]) == REG
9315 || (GET_CODE (otherops[2]) == CONST_INT
9316 && INTVAL (otherops[2]) > -256
9317 && INTVAL (otherops[2]) < 256)))
9319 otherops[0] = operands[1];
9320 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9321 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
9327 otherops[0] = adjust_address (operands[0], SImode, 4);
9328 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9329 output_asm_insn ("str%?\t%1, %0", operands);
9330 output_asm_insn ("str%?\t%1, %0", otherops);
9337 /* Output a VFP load or store instruction. */
9340 output_move_vfp (rtx *operands)
9342 rtx reg, mem, addr, ops[2];
9343 int load = REG_P (operands[0]);
9344 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
9345 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
9346 const char *template;
9349 reg = operands[!load];
9350 mem = operands[load];
9352 gcc_assert (REG_P (reg));
9353 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
9354 gcc_assert (GET_MODE (reg) == SFmode
9355 || GET_MODE (reg) == DFmode
9356 || GET_MODE (reg) == SImode
9357 || GET_MODE (reg) == DImode);
9358 gcc_assert (MEM_P (mem));
9360 addr = XEXP (mem, 0);
9362 switch (GET_CODE (addr))
9365 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9366 ops[0] = XEXP (addr, 0);
9371 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9372 ops[0] = XEXP (addr, 0);
9377 template = "f%s%c%%?\t%%%s0, %%1%s";
9383 sprintf (buff, template,
9387 integer_p ? "\t%@ int" : "");
9388 output_asm_insn (buff, ops);
9393 /* Output an ADD r, s, #n where n may be too big for one instruction.
9394 If adding zero to one register, output nothing. */
9396 output_add_immediate (rtx *operands)
9398 HOST_WIDE_INT n = INTVAL (operands[2]);
9400 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9403 output_multi_immediate (operands,
9404 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9407 output_multi_immediate (operands,
9408 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9415 /* Output a multiple immediate operation.
9416 OPERANDS is the vector of operands referred to in the output patterns.
9417 INSTR1 is the output pattern to use for the first constant.
9418 INSTR2 is the output pattern to use for subsequent constants.
9419 IMMED_OP is the index of the constant slot in OPERANDS.
9420 N is the constant value. */
9422 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9423 int immed_op, HOST_WIDE_INT n)
9425 #if HOST_BITS_PER_WIDE_INT > 32
9431 /* Quick and easy output. */
9432 operands[immed_op] = const0_rtx;
9433 output_asm_insn (instr1, operands);
9438 const char * instr = instr1;
9440 /* Note that n is never zero here (which would give no output). */
9441 for (i = 0; i < 32; i += 2)
9445 operands[immed_op] = GEN_INT (n & (255 << i));
9446 output_asm_insn (instr, operands);
9456 /* Return the name of a shifter operation. */
9458 arm_shift_nmem(enum rtx_code code)
9463 return ARM_LSL_NAME;
9479 /* Return the appropriate ARM instruction for the operation code.
9480 The returned result should not be overwritten. OP is the rtx of the
9481 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9484 arithmetic_instr (rtx op, int shift_first_arg)
9486 switch (GET_CODE (op))
9492 return shift_first_arg ? "rsb" : "sub";
9507 return arm_shift_nmem(GET_CODE(op));
9514 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9515 for the operation code. The returned result should not be overwritten.
9516 OP is the rtx code of the shift.
9517 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9520 shift_op (rtx op, HOST_WIDE_INT *amountp)
9523 enum rtx_code code = GET_CODE (op);
9525 switch (GET_CODE (XEXP (op, 1)))
9533 *amountp = INTVAL (XEXP (op, 1));
9543 gcc_assert (*amountp != -1);
9544 *amountp = 32 - *amountp;
9553 mnem = arm_shift_nmem(code);
9557 /* We never have to worry about the amount being other than a
9558 power of 2, since this case can never be reloaded from a reg. */
9559 gcc_assert (*amountp != -1);
9560 *amountp = int_log2 (*amountp);
9561 return ARM_LSL_NAME;
9569 /* This is not 100% correct, but follows from the desire to merge
9570 multiplication by a power of 2 with the recognizer for a
9571 shift. >=32 is not a valid shift for "lsl", so we must try and
9572 output a shift that produces the correct arithmetical result.
9573 Using lsr #32 is identical except for the fact that the carry bit
9574 is not set correctly if we set the flags; but we never use the
9575 carry bit from such an operation, so we can ignore that. */
9576 if (code == ROTATERT)
9577 /* Rotate is just modulo 32. */
9579 else if (*amountp != (*amountp & 31))
9586 /* Shifts of 0 are no-ops. */
9594 /* Obtain the shift from the POWER of two. */
9596 static HOST_WIDE_INT
9597 int_log2 (HOST_WIDE_INT power)
9599 HOST_WIDE_INT shift = 0;
9601 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9603 gcc_assert (shift <= 31);
9610 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9611 because /bin/as is horribly restrictive. The judgement about
9612 whether or not each character is 'printable' (and can be output as
9613 is) or not (and must be printed with an octal escape) must be made
9614 with reference to the *host* character set -- the situation is
9615 similar to that discussed in the comments above pp_c_char in
9616 c-pretty-print.c. */
9618 #define MAX_ASCII_LEN 51
9621 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9626 fputs ("\t.ascii\t\"", stream);
9628 for (i = 0; i < len; i++)
9632 if (len_so_far >= MAX_ASCII_LEN)
9634 fputs ("\"\n\t.ascii\t\"", stream);
9640 if (c == '\\' || c == '\"')
9642 putc ('\\', stream);
9650 fprintf (stream, "\\%03o", c);
9655 fputs ("\"\n", stream);
9658 /* Compute the register save mask for registers 0 through 12
9659 inclusive. This code is used by arm_compute_save_reg_mask. */
9661 static unsigned long
9662 arm_compute_save_reg0_reg12_mask (void)
9664 unsigned long func_type = arm_current_func_type ();
9665 unsigned long save_reg_mask = 0;
9668 if (IS_INTERRUPT (func_type))
9670 unsigned int max_reg;
9671 /* Interrupt functions must not corrupt any registers,
9672 even call clobbered ones. If this is a leaf function
9673 we can just examine the registers used by the RTL, but
9674 otherwise we have to assume that whatever function is
9675 called might clobber anything, and so we have to save
9676 all the call-clobbered registers as well. */
9677 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9678 /* FIQ handlers have registers r8 - r12 banked, so
9679 we only need to check r0 - r7, Normal ISRs only
9680 bank r14 and r15, so we must check up to r12.
9681 r13 is the stack pointer which is always preserved,
9682 so we do not need to consider it here. */
9687 for (reg = 0; reg <= max_reg; reg++)
9688 if (regs_ever_live[reg]
9689 || (! current_function_is_leaf && call_used_regs [reg]))
9690 save_reg_mask |= (1 << reg);
9692 /* Also save the pic base register if necessary. */
9694 && !TARGET_SINGLE_PIC_BASE
9695 && arm_pic_register != INVALID_REGNUM
9696 && current_function_uses_pic_offset_table)
9697 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9701 /* In arm mode we handle r11 (FP) as a special case. */
9702 unsigned last_reg = TARGET_ARM ? 10 : 11;
9704 /* In the normal case we only need to save those registers
9705 which are call saved and which are used by this function. */
9706 for (reg = 0; reg <= last_reg; reg++)
9707 if (regs_ever_live[reg] && ! call_used_regs [reg])
9708 save_reg_mask |= (1 << reg);
9710 /* Handle the frame pointer as a special case. */
9711 if (TARGET_THUMB2 && frame_pointer_needed)
9712 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9713 else if (! TARGET_APCS_FRAME
9714 && ! frame_pointer_needed
9715 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9716 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9717 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9719 /* If we aren't loading the PIC register,
9720 don't stack it even though it may be live. */
9722 && !TARGET_SINGLE_PIC_BASE
9723 && arm_pic_register != INVALID_REGNUM
9724 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
9725 || current_function_uses_pic_offset_table))
9726 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9728 /* The prologue will copy SP into R0, so save it. */
9729 if (IS_STACKALIGN (func_type))
9733 /* Save registers so the exception handler can modify them. */
9734 if (current_function_calls_eh_return)
9740 reg = EH_RETURN_DATA_REGNO (i);
9741 if (reg == INVALID_REGNUM)
9743 save_reg_mask |= 1 << reg;
9747 return save_reg_mask;
9751 /* Compute a bit mask of which registers need to be
9752 saved on the stack for the current function. */
9754 static unsigned long
9755 arm_compute_save_reg_mask (void)
9757 unsigned int save_reg_mask = 0;
9758 unsigned long func_type = arm_current_func_type ();
9761 if (IS_NAKED (func_type))
9762 /* This should never really happen. */
9765 /* If we are creating a stack frame, then we must save the frame pointer,
9766 IP (which will hold the old stack pointer), LR and the PC. */
9767 if (frame_pointer_needed && TARGET_ARM)
9769 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9774 /* Volatile functions do not return, so there
9775 is no need to save any other registers. */
9776 if (IS_VOLATILE (func_type))
9777 return save_reg_mask;
9779 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9781 /* Decide if we need to save the link register.
9782 Interrupt routines have their own banked link register,
9783 so they never need to save it.
9784 Otherwise if we do not use the link register we do not need to save
9785 it. If we are pushing other registers onto the stack however, we
9786 can save an instruction in the epilogue by pushing the link register
9787 now and then popping it back into the PC. This incurs extra memory
9788 accesses though, so we only do it when optimizing for size, and only
9789 if we know that we will not need a fancy return sequence. */
9790 if (regs_ever_live [LR_REGNUM]
9793 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9794 && !current_function_calls_eh_return))
9795 save_reg_mask |= 1 << LR_REGNUM;
9797 if (cfun->machine->lr_save_eliminated)
9798 save_reg_mask &= ~ (1 << LR_REGNUM);
9800 if (TARGET_REALLY_IWMMXT
9801 && ((bit_count (save_reg_mask)
9802 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9804 /* The total number of registers that are going to be pushed
9805 onto the stack is odd. We need to ensure that the stack
9806 is 64-bit aligned before we start to save iWMMXt registers,
9807 and also before we start to create locals. (A local variable
9808 might be a double or long long which we will load/store using
9809 an iWMMXt instruction). Therefore we need to push another
9810 ARM register, so that the stack will be 64-bit aligned. We
9811 try to avoid using the arg registers (r0 -r3) as they might be
9812 used to pass values in a tail call. */
9813 for (reg = 4; reg <= 12; reg++)
9814 if ((save_reg_mask & (1 << reg)) == 0)
9818 save_reg_mask |= (1 << reg);
9821 cfun->machine->sibcall_blocked = 1;
9822 save_reg_mask |= (1 << 3);
9826 /* We may need to push an additional register for use initializing the
9827 PIC base register. */
9828 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
9829 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
9831 reg = thumb_find_work_register (1 << 4);
9832 if (!call_used_regs[reg])
9833 save_reg_mask |= (1 << reg);
9836 return save_reg_mask;
9840 /* Compute a bit mask of which registers need to be
9841 saved on the stack for the current function. */
9842 static unsigned long
9843 thumb1_compute_save_reg_mask (void)
9849 for (reg = 0; reg < 12; reg ++)
9850 if (regs_ever_live[reg] && !call_used_regs[reg])
9854 && !TARGET_SINGLE_PIC_BASE
9855 && arm_pic_register != INVALID_REGNUM
9856 && current_function_uses_pic_offset_table)
9857 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9859 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9860 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
9861 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
9863 /* LR will also be pushed if any lo regs are pushed. */
9864 if (mask & 0xff || thumb_force_lr_save ())
9865 mask |= (1 << LR_REGNUM);
9867 /* Make sure we have a low work register if we need one.
9868 We will need one if we are going to push a high register,
9869 but we are not currently intending to push a low register. */
9870 if ((mask & 0xff) == 0
9871 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9873 /* Use thumb_find_work_register to choose which register
9874 we will use. If the register is live then we will
9875 have to push it. Use LAST_LO_REGNUM as our fallback
9876 choice for the register to select. */
9877 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9879 if (! call_used_regs[reg])
9887 /* Return the number of bytes required to save VFP registers. */
9889 arm_get_vfp_saved_size (void)
9896 /* Space for saved VFP registers. */
9897 if (TARGET_HARD_FLOAT && TARGET_VFP)
9900 for (regno = FIRST_VFP_REGNUM;
9901 regno < LAST_VFP_REGNUM;
9904 if ((!regs_ever_live[regno] || call_used_regs[regno])
9905 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9909 /* Workaround ARM10 VFPr1 bug. */
9910 if (count == 2 && !arm_arch6)
9921 if (count == 2 && !arm_arch6)
9930 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9931 everything bar the final return instruction. */
9933 output_return_instruction (rtx operand, int really_return, int reverse)
9935 char conditional[10];
9938 unsigned long live_regs_mask;
9939 unsigned long func_type;
9940 arm_stack_offsets *offsets;
9942 func_type = arm_current_func_type ();
9944 if (IS_NAKED (func_type))
9947 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9949 /* If this function was declared non-returning, and we have
9950 found a tail call, then we have to trust that the called
9951 function won't return. */
9956 /* Otherwise, trap an attempted return by aborting. */
9958 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9960 assemble_external_libcall (ops[1]);
9961 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9967 gcc_assert (!current_function_calls_alloca || really_return);
9969 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9971 return_used_this_function = 1;
9973 live_regs_mask = arm_compute_save_reg_mask ();
9977 const char * return_reg;
9979 /* If we do not have any special requirements for function exit
9980 (e.g. interworking) then we can load the return address
9981 directly into the PC. Otherwise we must load it into LR. */
9983 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
9984 return_reg = reg_names[PC_REGNUM];
9986 return_reg = reg_names[LR_REGNUM];
9988 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9990 /* There are three possible reasons for the IP register
9991 being saved. 1) a stack frame was created, in which case
9992 IP contains the old stack pointer, or 2) an ISR routine
9993 corrupted it, or 3) it was saved to align the stack on
9994 iWMMXt. In case 1, restore IP into SP, otherwise just
9996 if (frame_pointer_needed)
9998 live_regs_mask &= ~ (1 << IP_REGNUM);
9999 live_regs_mask |= (1 << SP_REGNUM);
10002 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
10005 /* On some ARM architectures it is faster to use LDR rather than
10006 LDM to load a single register. On other architectures, the
10007 cost is the same. In 26 bit mode, or for exception handlers,
10008 we have to use LDM to load the PC so that the CPSR is also
10010 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10011 if (live_regs_mask == (1U << reg))
10014 if (reg <= LAST_ARM_REGNUM
10015 && (reg != LR_REGNUM
10017 || ! IS_INTERRUPT (func_type)))
10019 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
10020 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
10027 /* Generate the load multiple instruction to restore the
10028 registers. Note we can get here, even if
10029 frame_pointer_needed is true, but only if sp already
10030 points to the base of the saved core registers. */
10031 if (live_regs_mask & (1 << SP_REGNUM))
10033 unsigned HOST_WIDE_INT stack_adjust;
10035 offsets = arm_get_frame_offsets ();
10036 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
10037 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
10039 if (stack_adjust && arm_arch5 && TARGET_ARM)
10040 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
10043 /* If we can't use ldmib (SA110 bug),
10044 then try to pop r3 instead. */
10046 live_regs_mask |= 1 << 3;
10047 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
10051 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
10053 p = instr + strlen (instr);
10055 for (reg = 0; reg <= SP_REGNUM; reg++)
10056 if (live_regs_mask & (1 << reg))
10058 int l = strlen (reg_names[reg]);
10064 memcpy (p, ", ", 2);
10068 memcpy (p, "%|", 2);
10069 memcpy (p + 2, reg_names[reg], l);
10073 if (live_regs_mask & (1 << LR_REGNUM))
10075 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
10076 /* If returning from an interrupt, restore the CPSR. */
10077 if (IS_INTERRUPT (func_type))
10084 output_asm_insn (instr, & operand);
10086 /* See if we need to generate an extra instruction to
10087 perform the actual function return. */
10089 && func_type != ARM_FT_INTERWORKED
10090 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
10092 /* The return has already been handled
10093 by loading the LR into the PC. */
10100 switch ((int) ARM_FUNC_TYPE (func_type))
10104 /* ??? This is wrong for unified assembly syntax. */
10105 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
10108 case ARM_FT_INTERWORKED:
10109 sprintf (instr, "bx%s\t%%|lr", conditional);
10112 case ARM_FT_EXCEPTION:
10113 /* ??? This is wrong for unified assembly syntax. */
10114 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
10118 /* Use bx if it's available. */
10119 if (arm_arch5 || arm_arch4t)
10120 sprintf (instr, "bx%s\t%%|lr", conditional);
10122 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
10126 output_asm_insn (instr, & operand);
10132 /* Write the function name into the code section, directly preceding
10133 the function prologue.
10135 Code will be output similar to this:
10137 .ascii "arm_poke_function_name", 0
10140 .word 0xff000000 + (t1 - t0)
10141 arm_poke_function_name
10143 stmfd sp!, {fp, ip, lr, pc}
10146 When performing a stack backtrace, code can inspect the value
10147 of 'pc' stored at 'fp' + 0. If the trace function then looks
10148 at location pc - 12 and the top 8 bits are set, then we know
10149 that there is a function name embedded immediately preceding this
10150 location and has length ((pc[-3]) & 0xff000000).
10152 We assume that pc is declared as a pointer to an unsigned long.
10154 It is of no benefit to output the function name if we are assembling
10155 a leaf function. These function types will not contain a stack
10156 backtrace structure, therefore it is not possible to determine the
10159 arm_poke_function_name (FILE *stream, const char *name)
10161 unsigned long alignlength;
10162 unsigned long length;
10165 length = strlen (name) + 1;
10166 alignlength = ROUND_UP_WORD (length);
10168 ASM_OUTPUT_ASCII (stream, name, length);
10169 ASM_OUTPUT_ALIGN (stream, 2);
10170 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
10171 assemble_aligned_integer (UNITS_PER_WORD, x);
10174 /* Place some comments into the assembler stream
10175 describing the current function. */
10177 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
10179 unsigned long func_type;
10183 thumb1_output_function_prologue (f, frame_size);
10187 /* Sanity check. */
10188 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
10190 func_type = arm_current_func_type ();
10192 switch ((int) ARM_FUNC_TYPE (func_type))
10195 case ARM_FT_NORMAL:
10197 case ARM_FT_INTERWORKED:
10198 asm_fprintf (f, "\t%@ Function supports interworking.\n");
10201 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
10204 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
10206 case ARM_FT_EXCEPTION:
10207 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
10211 if (IS_NAKED (func_type))
10212 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10214 if (IS_VOLATILE (func_type))
10215 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
10217 if (IS_NESTED (func_type))
10218 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
10219 if (IS_STACKALIGN (func_type))
10220 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10222 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10223 current_function_args_size,
10224 current_function_pretend_args_size, frame_size);
10226 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10227 frame_pointer_needed,
10228 cfun->machine->uses_anonymous_args);
10230 if (cfun->machine->lr_save_eliminated)
10231 asm_fprintf (f, "\t%@ link register save eliminated.\n");
10233 if (current_function_calls_eh_return)
10234 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
10236 #ifdef AOF_ASSEMBLER
10238 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
10241 return_used_this_function = 0;
10245 arm_output_epilogue (rtx sibling)
10248 unsigned long saved_regs_mask;
10249 unsigned long func_type;
10250 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10251 frame that is $fp + 4 for a non-variadic function. */
10252 int floats_offset = 0;
10254 FILE * f = asm_out_file;
10255 unsigned int lrm_count = 0;
10256 int really_return = (sibling == NULL);
10258 arm_stack_offsets *offsets;
10260 /* If we have already generated the return instruction
10261 then it is futile to generate anything else. */
10262 if (use_return_insn (FALSE, sibling) && return_used_this_function)
10265 func_type = arm_current_func_type ();
10267 if (IS_NAKED (func_type))
10268 /* Naked functions don't have epilogues. */
10271 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10275 /* A volatile function should never return. Call abort. */
10276 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
10277 assemble_external_libcall (op);
10278 output_asm_insn ("bl\t%a0", &op);
10283 /* If we are throwing an exception, then we really must be doing a
10284 return, so we can't tail-call. */
10285 gcc_assert (!current_function_calls_eh_return || really_return);
10287 offsets = arm_get_frame_offsets ();
10288 saved_regs_mask = arm_compute_save_reg_mask ();
10291 lrm_count = bit_count (saved_regs_mask);
10293 floats_offset = offsets->saved_args;
10294 /* Compute how far away the floats will be. */
10295 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10296 if (saved_regs_mask & (1 << reg))
10297 floats_offset += 4;
10299 if (frame_pointer_needed && TARGET_ARM)
10301 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10302 int vfp_offset = offsets->frame;
10304 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10306 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10307 if (regs_ever_live[reg] && !call_used_regs[reg])
10309 floats_offset += 12;
10310 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
10311 reg, FP_REGNUM, floats_offset - vfp_offset);
10316 start_reg = LAST_FPA_REGNUM;
10318 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10320 if (regs_ever_live[reg] && !call_used_regs[reg])
10322 floats_offset += 12;
10324 /* We can't unstack more than four registers at once. */
10325 if (start_reg - reg == 3)
10327 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
10328 reg, FP_REGNUM, floats_offset - vfp_offset);
10329 start_reg = reg - 1;
10334 if (reg != start_reg)
10335 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10336 reg + 1, start_reg - reg,
10337 FP_REGNUM, floats_offset - vfp_offset);
10338 start_reg = reg - 1;
10342 /* Just in case the last register checked also needs unstacking. */
10343 if (reg != start_reg)
10344 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10345 reg + 1, start_reg - reg,
10346 FP_REGNUM, floats_offset - vfp_offset);
10349 if (TARGET_HARD_FLOAT && TARGET_VFP)
10353 /* The fldmd insns do not have base+offset addressing
10354 modes, so we use IP to hold the address. */
10355 saved_size = arm_get_vfp_saved_size ();
10357 if (saved_size > 0)
10359 floats_offset += saved_size;
10360 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
10361 FP_REGNUM, floats_offset - vfp_offset);
10363 start_reg = FIRST_VFP_REGNUM;
10364 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10366 if ((!regs_ever_live[reg] || call_used_regs[reg])
10367 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10369 if (start_reg != reg)
10370 vfp_output_fldmd (f, IP_REGNUM,
10371 (start_reg - FIRST_VFP_REGNUM) / 2,
10372 (reg - start_reg) / 2);
10373 start_reg = reg + 2;
10376 if (start_reg != reg)
10377 vfp_output_fldmd (f, IP_REGNUM,
10378 (start_reg - FIRST_VFP_REGNUM) / 2,
10379 (reg - start_reg) / 2);
10384 /* The frame pointer is guaranteed to be non-double-word aligned.
10385 This is because it is set to (old_stack_pointer - 4) and the
10386 old_stack_pointer was double word aligned. Thus the offset to
10387 the iWMMXt registers to be loaded must also be non-double-word
10388 sized, so that the resultant address *is* double-word aligned.
10389 We can ignore floats_offset since that was already included in
10390 the live_regs_mask. */
10391 lrm_count += (lrm_count % 2 ? 2 : 1);
10393 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10394 if (regs_ever_live[reg] && !call_used_regs[reg])
10396 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
10397 reg, FP_REGNUM, lrm_count * 4);
10402 /* saved_regs_mask should contain the IP, which at the time of stack
10403 frame generation actually contains the old stack pointer. So a
10404 quick way to unwind the stack is just pop the IP register directly
10405 into the stack pointer. */
10406 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
10407 saved_regs_mask &= ~ (1 << IP_REGNUM);
10408 saved_regs_mask |= (1 << SP_REGNUM);
10410 /* There are two registers left in saved_regs_mask - LR and PC. We
10411 only need to restore the LR register (the return address), but to
10412 save time we can load it directly into the PC, unless we need a
10413 special function exit sequence, or we are not really returning. */
10415 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10416 && !current_function_calls_eh_return)
10417 /* Delete the LR from the register mask, so that the LR on
10418 the stack is loaded into the PC in the register mask. */
10419 saved_regs_mask &= ~ (1 << LR_REGNUM);
10421 saved_regs_mask &= ~ (1 << PC_REGNUM);
10423 /* We must use SP as the base register, because SP is one of the
10424 registers being restored. If an interrupt or page fault
10425 happens in the ldm instruction, the SP might or might not
10426 have been restored. That would be bad, as then SP will no
10427 longer indicate the safe area of stack, and we can get stack
10428 corruption. Using SP as the base register means that it will
10429 be reset correctly to the original value, should an interrupt
10430 occur. If the stack pointer already points at the right
10431 place, then omit the subtraction. */
10432 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10433 || current_function_calls_alloca)
10434 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10435 4 * bit_count (saved_regs_mask));
10436 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
10438 if (IS_INTERRUPT (func_type))
10439 /* Interrupt handlers will have pushed the
10440 IP onto the stack, so restore it now. */
10441 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
10445 HOST_WIDE_INT amount;
10447 /* Restore stack pointer if necessary. */
10448 if (frame_pointer_needed)
10450 /* For Thumb-2 restore sp from the frame pointer.
10451 Operand restrictions mean we have to incrememnt FP, then copy
10453 amount = offsets->locals_base - offsets->saved_regs;
10454 operands[0] = hard_frame_pointer_rtx;
10458 operands[0] = stack_pointer_rtx;
10459 amount = offsets->outgoing_args - offsets->saved_regs;
10464 operands[1] = operands[0];
10465 operands[2] = GEN_INT (amount);
10466 output_add_immediate (operands);
10468 if (frame_pointer_needed)
10469 asm_fprintf (f, "\tmov\t%r, %r\n",
10470 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
10472 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10474 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10475 if (regs_ever_live[reg] && !call_used_regs[reg])
10476 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10481 start_reg = FIRST_FPA_REGNUM;
10483 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10485 if (regs_ever_live[reg] && !call_used_regs[reg])
10487 if (reg - start_reg == 3)
10489 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10490 start_reg, SP_REGNUM);
10491 start_reg = reg + 1;
10496 if (reg != start_reg)
10497 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10498 start_reg, reg - start_reg,
10501 start_reg = reg + 1;
10505 /* Just in case the last register checked also needs unstacking. */
10506 if (reg != start_reg)
10507 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10508 start_reg, reg - start_reg, SP_REGNUM);
10511 if (TARGET_HARD_FLOAT && TARGET_VFP)
10513 start_reg = FIRST_VFP_REGNUM;
10514 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10516 if ((!regs_ever_live[reg] || call_used_regs[reg])
10517 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10519 if (start_reg != reg)
10520 vfp_output_fldmd (f, SP_REGNUM,
10521 (start_reg - FIRST_VFP_REGNUM) / 2,
10522 (reg - start_reg) / 2);
10523 start_reg = reg + 2;
10526 if (start_reg != reg)
10527 vfp_output_fldmd (f, SP_REGNUM,
10528 (start_reg - FIRST_VFP_REGNUM) / 2,
10529 (reg - start_reg) / 2);
10532 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10533 if (regs_ever_live[reg] && !call_used_regs[reg])
10534 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10536 /* If we can, restore the LR into the PC. */
10537 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
10538 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
10539 && !IS_STACKALIGN (func_type)
10541 && current_function_pretend_args_size == 0
10542 && saved_regs_mask & (1 << LR_REGNUM)
10543 && !current_function_calls_eh_return)
10545 saved_regs_mask &= ~ (1 << LR_REGNUM);
10546 saved_regs_mask |= (1 << PC_REGNUM);
10547 rfe = IS_INTERRUPT (func_type);
10552 /* Load the registers off the stack. If we only have one register
10553 to load use the LDR instruction - it is faster. For Thumb-2
10554 always use pop and the assembler will pick the best instruction.*/
10555 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
10556 && !IS_INTERRUPT(func_type))
10558 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10560 else if (saved_regs_mask)
10562 if (saved_regs_mask & (1 << SP_REGNUM))
10563 /* Note - write back to the stack register is not enabled
10564 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10565 in the list of registers and if we add writeback the
10566 instruction becomes UNPREDICTABLE. */
10567 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
10569 else if (TARGET_ARM)
10570 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
10573 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
10576 if (current_function_pretend_args_size)
10578 /* Unwind the pre-pushed regs. */
10579 operands[0] = operands[1] = stack_pointer_rtx;
10580 operands[2] = GEN_INT (current_function_pretend_args_size);
10581 output_add_immediate (operands);
10585 /* We may have already restored PC directly from the stack. */
10586 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10589 /* Stack adjustment for exception handler. */
10590 if (current_function_calls_eh_return)
10591 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10592 ARM_EH_STACKADJ_REGNUM);
10594 /* Generate the return instruction. */
10595 switch ((int) ARM_FUNC_TYPE (func_type))
10599 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10602 case ARM_FT_EXCEPTION:
10603 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10606 case ARM_FT_INTERWORKED:
10607 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10611 if (IS_STACKALIGN (func_type))
10613 /* See comment in arm_expand_prologue. */
10614 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
10616 if (arm_arch5 || arm_arch4t)
10617 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10619 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10627 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10628 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10630 arm_stack_offsets *offsets;
10636 /* Emit any call-via-reg trampolines that are needed for v4t support
10637 of call_reg and call_value_reg type insns. */
10638 for (regno = 0; regno < LR_REGNUM; regno++)
10640 rtx label = cfun->machine->call_via[regno];
10644 switch_to_section (function_section (current_function_decl));
10645 targetm.asm_out.internal_label (asm_out_file, "L",
10646 CODE_LABEL_NUMBER (label));
10647 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10651 /* ??? Probably not safe to set this here, since it assumes that a
10652 function will be emitted as assembly immediately after we generate
10653 RTL for it. This does not happen for inline functions. */
10654 return_used_this_function = 0;
10656 else /* TARGET_32BIT */
10658 /* We need to take into account any stack-frame rounding. */
10659 offsets = arm_get_frame_offsets ();
10661 gcc_assert (!use_return_insn (FALSE, NULL)
10662 || !return_used_this_function
10663 || offsets->saved_regs == offsets->outgoing_args
10664 || frame_pointer_needed);
10666 /* Reset the ARM-specific per-function variables. */
10667 after_arm_reorg = 0;
10671 /* Generate and emit an insn that we will recognize as a push_multi.
10672 Unfortunately, since this insn does not reflect very well the actual
10673 semantics of the operation, we need to annotate the insn for the benefit
10674 of DWARF2 frame unwind information. */
10676 emit_multi_reg_push (unsigned long mask)
10679 int num_dwarf_regs;
10683 int dwarf_par_index;
10686 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10687 if (mask & (1 << i))
10690 gcc_assert (num_regs && num_regs <= 16);
10692 /* We don't record the PC in the dwarf frame information. */
10693 num_dwarf_regs = num_regs;
10694 if (mask & (1 << PC_REGNUM))
10697 /* For the body of the insn we are going to generate an UNSPEC in
10698 parallel with several USEs. This allows the insn to be recognized
10699 by the push_multi pattern in the arm.md file. The insn looks
10700 something like this:
10703 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10704 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10705 (use (reg:SI 11 fp))
10706 (use (reg:SI 12 ip))
10707 (use (reg:SI 14 lr))
10708 (use (reg:SI 15 pc))
10711 For the frame note however, we try to be more explicit and actually
10712 show each register being stored into the stack frame, plus a (single)
10713 decrement of the stack pointer. We do it this way in order to be
10714 friendly to the stack unwinding code, which only wants to see a single
10715 stack decrement per instruction. The RTL we generate for the note looks
10716 something like this:
10719 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10720 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10721 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10722 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10723 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10726 This sequence is used both by the code to support stack unwinding for
10727 exceptions handlers and the code to generate dwarf2 frame debugging. */
10729 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10730 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10731 dwarf_par_index = 1;
10733 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10735 if (mask & (1 << i))
10737 reg = gen_rtx_REG (SImode, i);
10739 XVECEXP (par, 0, 0)
10740 = gen_rtx_SET (VOIDmode,
10741 gen_frame_mem (BLKmode,
10742 gen_rtx_PRE_DEC (BLKmode,
10743 stack_pointer_rtx)),
10744 gen_rtx_UNSPEC (BLKmode,
10745 gen_rtvec (1, reg),
10746 UNSPEC_PUSH_MULT));
10748 if (i != PC_REGNUM)
10750 tmp = gen_rtx_SET (VOIDmode,
10751 gen_frame_mem (SImode, stack_pointer_rtx),
10753 RTX_FRAME_RELATED_P (tmp) = 1;
10754 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10762 for (j = 1, i++; j < num_regs; i++)
10764 if (mask & (1 << i))
10766 reg = gen_rtx_REG (SImode, i);
10768 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10770 if (i != PC_REGNUM)
10773 = gen_rtx_SET (VOIDmode,
10774 gen_frame_mem (SImode,
10775 plus_constant (stack_pointer_rtx,
10778 RTX_FRAME_RELATED_P (tmp) = 1;
10779 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10786 par = emit_insn (par);
10788 tmp = gen_rtx_SET (VOIDmode,
10790 plus_constant (stack_pointer_rtx, -4 * num_regs));
10791 RTX_FRAME_RELATED_P (tmp) = 1;
10792 XVECEXP (dwarf, 0, 0) = tmp;
10794 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10799 /* Calculate the size of the return value that is passed in registers. */
10801 arm_size_return_regs (void)
10803 enum machine_mode mode;
10805 if (current_function_return_rtx != 0)
10806 mode = GET_MODE (current_function_return_rtx);
10808 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10810 return GET_MODE_SIZE (mode);
10814 emit_sfm (int base_reg, int count)
10821 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10822 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10824 reg = gen_rtx_REG (XFmode, base_reg++);
10826 XVECEXP (par, 0, 0)
10827 = gen_rtx_SET (VOIDmode,
10828 gen_frame_mem (BLKmode,
10829 gen_rtx_PRE_DEC (BLKmode,
10830 stack_pointer_rtx)),
10831 gen_rtx_UNSPEC (BLKmode,
10832 gen_rtvec (1, reg),
10833 UNSPEC_PUSH_MULT));
10834 tmp = gen_rtx_SET (VOIDmode,
10835 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
10836 RTX_FRAME_RELATED_P (tmp) = 1;
10837 XVECEXP (dwarf, 0, 1) = tmp;
10839 for (i = 1; i < count; i++)
10841 reg = gen_rtx_REG (XFmode, base_reg++);
10842 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10844 tmp = gen_rtx_SET (VOIDmode,
10845 gen_frame_mem (XFmode,
10846 plus_constant (stack_pointer_rtx,
10849 RTX_FRAME_RELATED_P (tmp) = 1;
10850 XVECEXP (dwarf, 0, i + 1) = tmp;
10853 tmp = gen_rtx_SET (VOIDmode,
10855 plus_constant (stack_pointer_rtx, -12 * count));
10857 RTX_FRAME_RELATED_P (tmp) = 1;
10858 XVECEXP (dwarf, 0, 0) = tmp;
10860 par = emit_insn (par);
10861 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10867 /* Return true if the current function needs to save/restore LR. */
10870 thumb_force_lr_save (void)
10872 return !cfun->machine->lr_save_eliminated
10873 && (!leaf_function_p ()
10874 || thumb_far_jump_used_p ()
10875 || regs_ever_live [LR_REGNUM]);
10879 /* Compute the distance from register FROM to register TO.
10880 These can be the arg pointer (26), the soft frame pointer (25),
10881 the stack pointer (13) or the hard frame pointer (11).
10882 In thumb mode r7 is used as the soft frame pointer, if needed.
10883 Typical stack layout looks like this:
10885 old stack pointer -> | |
10888 | | saved arguments for
10889 | | vararg functions
10892 hard FP & arg pointer -> | | \
10900 soft frame pointer -> | | /
10905 locals base pointer -> | | /
10910 current stack pointer -> | | /
10913 For a given function some or all of these stack components
10914 may not be needed, giving rise to the possibility of
10915 eliminating some of the registers.
10917 The values returned by this function must reflect the behavior
10918 of arm_expand_prologue() and arm_compute_save_reg_mask().
10920 The sign of the number returned reflects the direction of stack
10921 growth, so the values are positive for all eliminations except
10922 from the soft frame pointer to the hard frame pointer.
10924 SFP may point just inside the local variables block to ensure correct
10928 /* Calculate stack offsets. These are used to calculate register elimination
10929 offsets and in prologue/epilogue code. */
10931 static arm_stack_offsets *
10932 arm_get_frame_offsets (void)
10934 struct arm_stack_offsets *offsets;
10935 unsigned long func_type;
10938 HOST_WIDE_INT frame_size;
10940 offsets = &cfun->machine->stack_offsets;
10942 /* We need to know if we are a leaf function. Unfortunately, it
10943 is possible to be called after start_sequence has been called,
10944 which causes get_insns to return the insns for the sequence,
10945 not the function, which will cause leaf_function_p to return
10946 the incorrect result.
10948 to know about leaf functions once reload has completed, and the
10949 frame size cannot be changed after that time, so we can safely
10950 use the cached value. */
10952 if (reload_completed)
10955 /* Initially this is the size of the local variables. It will translated
10956 into an offset once we have determined the size of preceding data. */
10957 frame_size = ROUND_UP_WORD (get_frame_size ());
10959 leaf = leaf_function_p ();
10961 /* Space for variadic functions. */
10962 offsets->saved_args = current_function_pretend_args_size;
10964 /* In Thumb mode this is incorrect, but never used. */
10965 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10969 unsigned int regno;
10971 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10973 /* We know that SP will be doubleword aligned on entry, and we must
10974 preserve that condition at any subroutine call. We also require the
10975 soft frame pointer to be doubleword aligned. */
10977 if (TARGET_REALLY_IWMMXT)
10979 /* Check for the call-saved iWMMXt registers. */
10980 for (regno = FIRST_IWMMXT_REGNUM;
10981 regno <= LAST_IWMMXT_REGNUM;
10983 if (regs_ever_live [regno] && ! call_used_regs [regno])
10987 func_type = arm_current_func_type ();
10988 if (! IS_VOLATILE (func_type))
10990 /* Space for saved FPA registers. */
10991 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10992 if (regs_ever_live[regno] && ! call_used_regs[regno])
10995 /* Space for saved VFP registers. */
10996 if (TARGET_HARD_FLOAT && TARGET_VFP)
10997 saved += arm_get_vfp_saved_size ();
11000 else /* TARGET_THUMB1 */
11002 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
11003 if (TARGET_BACKTRACE)
11007 /* Saved registers include the stack frame. */
11008 offsets->saved_regs = offsets->saved_args + saved;
11009 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
11010 /* A leaf function does not need any stack alignment if it has nothing
11012 if (leaf && frame_size == 0)
11014 offsets->outgoing_args = offsets->soft_frame;
11018 /* Ensure SFP has the correct alignment. */
11019 if (ARM_DOUBLEWORD_ALIGN
11020 && (offsets->soft_frame & 7))
11021 offsets->soft_frame += 4;
11023 offsets->locals_base = offsets->soft_frame + frame_size;
11024 offsets->outgoing_args = (offsets->locals_base
11025 + current_function_outgoing_args_size);
11027 if (ARM_DOUBLEWORD_ALIGN)
11029 /* Ensure SP remains doubleword aligned. */
11030 if (offsets->outgoing_args & 7)
11031 offsets->outgoing_args += 4;
11032 gcc_assert (!(offsets->outgoing_args & 7));
11039 /* Calculate the relative offsets for the different stack pointers. Positive
11040 offsets are in the direction of stack growth. */
11043 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
11045 arm_stack_offsets *offsets;
11047 offsets = arm_get_frame_offsets ();
11049 /* OK, now we have enough information to compute the distances.
11050 There must be an entry in these switch tables for each pair
11051 of registers in ELIMINABLE_REGS, even if some of the entries
11052 seem to be redundant or useless. */
11055 case ARG_POINTER_REGNUM:
11058 case THUMB_HARD_FRAME_POINTER_REGNUM:
11061 case FRAME_POINTER_REGNUM:
11062 /* This is the reverse of the soft frame pointer
11063 to hard frame pointer elimination below. */
11064 return offsets->soft_frame - offsets->saved_args;
11066 case ARM_HARD_FRAME_POINTER_REGNUM:
11067 /* If there is no stack frame then the hard
11068 frame pointer and the arg pointer coincide. */
11069 if (offsets->frame == offsets->saved_regs)
11071 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11072 return (frame_pointer_needed
11073 && cfun->static_chain_decl != NULL
11074 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
11076 case STACK_POINTER_REGNUM:
11077 /* If nothing has been pushed on the stack at all
11078 then this will return -4. This *is* correct! */
11079 return offsets->outgoing_args - (offsets->saved_args + 4);
11082 gcc_unreachable ();
11084 gcc_unreachable ();
11086 case FRAME_POINTER_REGNUM:
11089 case THUMB_HARD_FRAME_POINTER_REGNUM:
11092 case ARM_HARD_FRAME_POINTER_REGNUM:
11093 /* The hard frame pointer points to the top entry in the
11094 stack frame. The soft frame pointer to the bottom entry
11095 in the stack frame. If there is no stack frame at all,
11096 then they are identical. */
11098 return offsets->frame - offsets->soft_frame;
11100 case STACK_POINTER_REGNUM:
11101 return offsets->outgoing_args - offsets->soft_frame;
11104 gcc_unreachable ();
11106 gcc_unreachable ();
11109 /* You cannot eliminate from the stack pointer.
11110 In theory you could eliminate from the hard frame
11111 pointer to the stack pointer, but this will never
11112 happen, since if a stack frame is not needed the
11113 hard frame pointer will never be used. */
11114 gcc_unreachable ();
11119 /* Emit RTL to save coprocessor registers on funciton entry. Returns the
11120 number of bytes pushed. */
11123 arm_save_coproc_regs(void)
11125 int saved_size = 0;
11127 unsigned start_reg;
11130 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
11131 if (regs_ever_live[reg] && ! call_used_regs [reg])
11133 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
11134 insn = gen_rtx_MEM (V2SImode, insn);
11135 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
11136 RTX_FRAME_RELATED_P (insn) = 1;
11140 /* Save any floating point call-saved registers used by this
11142 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
11144 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11145 if (regs_ever_live[reg] && !call_used_regs[reg])
11147 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
11148 insn = gen_rtx_MEM (XFmode, insn);
11149 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
11150 RTX_FRAME_RELATED_P (insn) = 1;
11156 start_reg = LAST_FPA_REGNUM;
11158 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11160 if (regs_ever_live[reg] && !call_used_regs[reg])
11162 if (start_reg - reg == 3)
11164 insn = emit_sfm (reg, 4);
11165 RTX_FRAME_RELATED_P (insn) = 1;
11167 start_reg = reg - 1;
11172 if (start_reg != reg)
11174 insn = emit_sfm (reg + 1, start_reg - reg);
11175 RTX_FRAME_RELATED_P (insn) = 1;
11176 saved_size += (start_reg - reg) * 12;
11178 start_reg = reg - 1;
11182 if (start_reg != reg)
11184 insn = emit_sfm (reg + 1, start_reg - reg);
11185 saved_size += (start_reg - reg) * 12;
11186 RTX_FRAME_RELATED_P (insn) = 1;
11189 if (TARGET_HARD_FLOAT && TARGET_VFP)
11191 start_reg = FIRST_VFP_REGNUM;
11193 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11195 if ((!regs_ever_live[reg] || call_used_regs[reg])
11196 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
11198 if (start_reg != reg)
11199 saved_size += vfp_emit_fstmd (start_reg,
11200 (reg - start_reg) / 2);
11201 start_reg = reg + 2;
11204 if (start_reg != reg)
11205 saved_size += vfp_emit_fstmd (start_reg,
11206 (reg - start_reg) / 2);
11212 /* Set the Thumb frame pointer from the stack pointer. */
11215 thumb_set_frame_pointer (arm_stack_offsets *offsets)
11217 HOST_WIDE_INT amount;
11220 amount = offsets->outgoing_args - offsets->locals_base;
11222 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11223 stack_pointer_rtx, GEN_INT (amount)));
11226 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
11227 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11228 hard_frame_pointer_rtx,
11229 stack_pointer_rtx));
11230 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11231 plus_constant (stack_pointer_rtx, amount));
11232 RTX_FRAME_RELATED_P (dwarf) = 1;
11233 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11237 RTX_FRAME_RELATED_P (insn) = 1;
11240 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11243 arm_expand_prologue (void)
11248 unsigned long live_regs_mask;
11249 unsigned long func_type;
11251 int saved_pretend_args = 0;
11252 int saved_regs = 0;
11253 unsigned HOST_WIDE_INT args_to_push;
11254 arm_stack_offsets *offsets;
11256 func_type = arm_current_func_type ();
11258 /* Naked functions don't have prologues. */
11259 if (IS_NAKED (func_type))
11262 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11263 args_to_push = current_function_pretend_args_size;
11265 /* Compute which register we will have to save onto the stack. */
11266 live_regs_mask = arm_compute_save_reg_mask ();
11268 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
11270 if (IS_STACKALIGN (func_type))
11275 /* Handle a word-aligned stack pointer. We generate the following:
11280 <save and restore r0 in normal prologue/epilogue>
11284 The unwinder doesn't need to know about the stack realignment.
11285 Just tell it we saved SP in r0. */
11286 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
11288 r0 = gen_rtx_REG (SImode, 0);
11289 r1 = gen_rtx_REG (SImode, 1);
11290 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
11291 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
11292 insn = gen_movsi (r0, stack_pointer_rtx);
11293 RTX_FRAME_RELATED_P (insn) = 1;
11294 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11295 dwarf, REG_NOTES (insn));
11297 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
11298 emit_insn (gen_movsi (stack_pointer_rtx, r1));
11301 if (frame_pointer_needed && TARGET_ARM)
11303 if (IS_INTERRUPT (func_type))
11305 /* Interrupt functions must not corrupt any registers.
11306 Creating a frame pointer however, corrupts the IP
11307 register, so we must push it first. */
11308 insn = emit_multi_reg_push (1 << IP_REGNUM);
11310 /* Do not set RTX_FRAME_RELATED_P on this insn.
11311 The dwarf stack unwinding code only wants to see one
11312 stack decrement per function, and this is not it. If
11313 this instruction is labeled as being part of the frame
11314 creation sequence then dwarf2out_frame_debug_expr will
11315 die when it encounters the assignment of IP to FP
11316 later on, since the use of SP here establishes SP as
11317 the CFA register and not IP.
11319 Anyway this instruction is not really part of the stack
11320 frame creation although it is part of the prologue. */
11322 else if (IS_NESTED (func_type))
11324 /* The Static chain register is the same as the IP register
11325 used as a scratch register during stack frame creation.
11326 To get around this need to find somewhere to store IP
11327 whilst the frame is being created. We try the following
11330 1. The last argument register.
11331 2. A slot on the stack above the frame. (This only
11332 works if the function is not a varargs function).
11333 3. Register r3, after pushing the argument registers
11336 Note - we only need to tell the dwarf2 backend about the SP
11337 adjustment in the second variant; the static chain register
11338 doesn't need to be unwound, as it doesn't contain a value
11339 inherited from the caller. */
11341 if (regs_ever_live[3] == 0)
11342 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11343 else if (args_to_push == 0)
11347 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
11348 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
11351 /* Just tell the dwarf backend that we adjusted SP. */
11352 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11353 plus_constant (stack_pointer_rtx,
11355 RTX_FRAME_RELATED_P (insn) = 1;
11356 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11357 dwarf, REG_NOTES (insn));
11361 /* Store the args on the stack. */
11362 if (cfun->machine->uses_anonymous_args)
11363 insn = emit_multi_reg_push
11364 ((0xf0 >> (args_to_push / 4)) & 0xf);
11367 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11368 GEN_INT (- args_to_push)));
11370 RTX_FRAME_RELATED_P (insn) = 1;
11372 saved_pretend_args = 1;
11373 fp_offset = args_to_push;
11376 /* Now reuse r3 to preserve IP. */
11377 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11381 insn = emit_set_insn (ip_rtx,
11382 plus_constant (stack_pointer_rtx, fp_offset));
11383 RTX_FRAME_RELATED_P (insn) = 1;
11388 /* Push the argument registers, or reserve space for them. */
11389 if (cfun->machine->uses_anonymous_args)
11390 insn = emit_multi_reg_push
11391 ((0xf0 >> (args_to_push / 4)) & 0xf);
11394 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11395 GEN_INT (- args_to_push)));
11396 RTX_FRAME_RELATED_P (insn) = 1;
11399 /* If this is an interrupt service routine, and the link register
11400 is going to be pushed, and we are not creating a stack frame,
11401 (which would involve an extra push of IP and a pop in the epilogue)
11402 subtracting four from LR now will mean that the function return
11403 can be done with a single instruction. */
11404 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
11405 && (live_regs_mask & (1 << LR_REGNUM)) != 0
11406 && ! frame_pointer_needed
11409 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
11411 emit_set_insn (lr, plus_constant (lr, -4));
11414 if (live_regs_mask)
11416 insn = emit_multi_reg_push (live_regs_mask);
11417 saved_regs += bit_count (live_regs_mask) * 4;
11418 RTX_FRAME_RELATED_P (insn) = 1;
11421 if (! IS_VOLATILE (func_type))
11422 saved_regs += arm_save_coproc_regs ();
11424 if (frame_pointer_needed && TARGET_ARM)
11426 /* Create the new frame pointer. */
11428 insn = GEN_INT (-(4 + args_to_push + fp_offset));
11429 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
11430 RTX_FRAME_RELATED_P (insn) = 1;
11432 if (IS_NESTED (func_type))
11434 /* Recover the static chain register. */
11435 if (regs_ever_live [3] == 0
11436 || saved_pretend_args)
11437 insn = gen_rtx_REG (SImode, 3);
11438 else /* if (current_function_pretend_args_size == 0) */
11440 insn = plus_constant (hard_frame_pointer_rtx, 4);
11441 insn = gen_frame_mem (SImode, insn);
11443 emit_set_insn (ip_rtx, insn);
11444 /* Add a USE to stop propagate_one_insn() from barfing. */
11445 emit_insn (gen_prologue_use (ip_rtx));
11450 offsets = arm_get_frame_offsets ();
11451 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
11453 /* This add can produce multiple insns for a large constant, so we
11454 need to get tricky. */
11455 rtx last = get_last_insn ();
11457 amount = GEN_INT (offsets->saved_args + saved_regs
11458 - offsets->outgoing_args);
11460 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11464 last = last ? NEXT_INSN (last) : get_insns ();
11465 RTX_FRAME_RELATED_P (last) = 1;
11467 while (last != insn);
11469 /* If the frame pointer is needed, emit a special barrier that
11470 will prevent the scheduler from moving stores to the frame
11471 before the stack adjustment. */
11472 if (frame_pointer_needed)
11473 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
11474 hard_frame_pointer_rtx));
11478 if (frame_pointer_needed && TARGET_THUMB2)
11479 thumb_set_frame_pointer (offsets);
11481 if (flag_pic && arm_pic_register != INVALID_REGNUM)
11483 unsigned long mask;
11485 mask = live_regs_mask;
11486 mask &= THUMB2_WORK_REGS;
11487 if (!IS_NESTED (func_type))
11488 mask |= (1 << IP_REGNUM);
11489 arm_load_pic_register (mask);
11492 /* If we are profiling, make sure no instructions are scheduled before
11493 the call to mcount. Similarly if the user has requested no
11494 scheduling in the prolog. Similarly if we want non-call exceptions
11495 using the EABI unwinder, to prevent faulting instructions from being
11496 swapped with a stack adjustment. */
11497 if (current_function_profile || !TARGET_SCHED_PROLOG
11498 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
11499 emit_insn (gen_blockage ());
11501 /* If the link register is being kept alive, with the return address in it,
11502 then make sure that it does not get reused by the ce2 pass. */
11503 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
11505 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
11506 cfun->machine->lr_save_eliminated = 1;
11510 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11512 arm_print_condition (FILE *stream)
11514 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11516 /* Branch conversion is not implemented for Thumb-2. */
11519 output_operand_lossage ("predicated Thumb instruction");
11522 if (current_insn_predicate != NULL)
11524 output_operand_lossage
11525 ("predicated instruction in conditional sequence");
11529 fputs (arm_condition_codes[arm_current_cc], stream);
11531 else if (current_insn_predicate)
11533 enum arm_cond_code code;
11537 output_operand_lossage ("predicated Thumb instruction");
11541 code = get_arm_condition_code (current_insn_predicate);
11542 fputs (arm_condition_codes[code], stream);
11547 /* If CODE is 'd', then the X is a condition operand and the instruction
11548 should only be executed if the condition is true.
11549 if CODE is 'D', then the X is a condition operand and the instruction
11550 should only be executed if the condition is false: however, if the mode
11551 of the comparison is CCFPEmode, then always execute the instruction -- we
11552 do this because in these circumstances !GE does not necessarily imply LT;
11553 in these cases the instruction pattern will take care to make sure that
11554 an instruction containing %d will follow, thereby undoing the effects of
11555 doing this instruction unconditionally.
11556 If CODE is 'N' then X is a floating point operand that must be negated
11558 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11559 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11561 arm_print_operand (FILE *stream, rtx x, int code)
11566 fputs (ASM_COMMENT_START, stream);
11570 fputs (user_label_prefix, stream);
11574 fputs (REGISTER_PREFIX, stream);
11578 arm_print_condition (stream);
11582 /* Nothing in unified syntax, otherwise the current condition code. */
11583 if (!TARGET_UNIFIED_ASM)
11584 arm_print_condition (stream);
11588 /* The current condition code in unified syntax, otherwise nothing. */
11589 if (TARGET_UNIFIED_ASM)
11590 arm_print_condition (stream);
11594 /* The current condition code for a condition code setting instruction.
11595 Preceeded by 's' in unified syntax, otherwise followed by 's'. */
11596 if (TARGET_UNIFIED_ASM)
11598 fputc('s', stream);
11599 arm_print_condition (stream);
11603 arm_print_condition (stream);
11604 fputc('s', stream);
11609 /* If the instruction is conditionally executed then print
11610 the current condition code, otherwise print 's'. */
11611 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
11612 if (current_insn_predicate)
11613 arm_print_condition (stream);
11615 fputc('s', stream);
11621 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11622 r = REAL_VALUE_NEGATE (r);
11623 fprintf (stream, "%s", fp_const_from_val (&r));
11628 if (GET_CODE (x) == CONST_INT)
11631 val = ARM_SIGN_EXTEND (~INTVAL (x));
11632 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11636 putc ('~', stream);
11637 output_addr_const (stream, x);
11642 /* The low 16 bits of an immediate constant. */
11643 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
11647 fprintf (stream, "%s", arithmetic_instr (x, 1));
11650 /* Truncate Cirrus shift counts. */
11652 if (GET_CODE (x) == CONST_INT)
11654 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11657 arm_print_operand (stream, x, 0);
11661 fprintf (stream, "%s", arithmetic_instr (x, 0));
11669 if (!shift_operator (x, SImode))
11671 output_operand_lossage ("invalid shift operand");
11675 shift = shift_op (x, &val);
11679 fprintf (stream, ", %s ", shift);
11681 arm_print_operand (stream, XEXP (x, 1), 0);
11683 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11688 /* An explanation of the 'Q', 'R' and 'H' register operands:
11690 In a pair of registers containing a DI or DF value the 'Q'
11691 operand returns the register number of the register containing
11692 the least significant part of the value. The 'R' operand returns
11693 the register number of the register containing the most
11694 significant part of the value.
11696 The 'H' operand returns the higher of the two register numbers.
11697 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11698 same as the 'Q' operand, since the most significant part of the
11699 value is held in the lower number register. The reverse is true
11700 on systems where WORDS_BIG_ENDIAN is false.
11702 The purpose of these operands is to distinguish between cases
11703 where the endian-ness of the values is important (for example
11704 when they are added together), and cases where the endian-ness
11705 is irrelevant, but the order of register operations is important.
11706 For example when loading a value from memory into a register
11707 pair, the endian-ness does not matter. Provided that the value
11708 from the lower memory address is put into the lower numbered
11709 register, and the value from the higher address is put into the
11710 higher numbered register, the load will work regardless of whether
11711 the value being loaded is big-wordian or little-wordian. The
11712 order of the two register loads can matter however, if the address
11713 of the memory location is actually held in one of the registers
11714 being overwritten by the load. */
11716 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11718 output_operand_lossage ("invalid operand for code '%c'", code);
11722 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11726 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11728 output_operand_lossage ("invalid operand for code '%c'", code);
11732 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11736 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11738 output_operand_lossage ("invalid operand for code '%c'", code);
11742 asm_fprintf (stream, "%r", REGNO (x) + 1);
11746 asm_fprintf (stream, "%r",
11747 GET_CODE (XEXP (x, 0)) == REG
11748 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11752 asm_fprintf (stream, "{%r-%r}",
11754 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11758 /* CONST_TRUE_RTX means always -- that's the default. */
11759 if (x == const_true_rtx)
11762 if (!COMPARISON_P (x))
11764 output_operand_lossage ("invalid operand for code '%c'", code);
11768 fputs (arm_condition_codes[get_arm_condition_code (x)],
11773 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11774 want to do that. */
11775 if (x == const_true_rtx)
11777 output_operand_lossage ("instruction never exectued");
11780 if (!COMPARISON_P (x))
11782 output_operand_lossage ("invalid operand for code '%c'", code);
11786 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11787 (get_arm_condition_code (x))],
11791 /* Cirrus registers can be accessed in a variety of ways:
11792 single floating point (f)
11793 double floating point (d)
11795 64bit integer (dx). */
11796 case 'W': /* Cirrus register in F mode. */
11797 case 'X': /* Cirrus register in D mode. */
11798 case 'Y': /* Cirrus register in FX mode. */
11799 case 'Z': /* Cirrus register in DX mode. */
11800 gcc_assert (GET_CODE (x) == REG
11801 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
11803 fprintf (stream, "mv%s%s",
11805 : code == 'X' ? "d"
11806 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11810 /* Print cirrus register in the mode specified by the register's mode. */
11813 int mode = GET_MODE (x);
11815 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11817 output_operand_lossage ("invalid operand for code '%c'", code);
11821 fprintf (stream, "mv%s%s",
11822 mode == DFmode ? "d"
11823 : mode == SImode ? "fx"
11824 : mode == DImode ? "dx"
11825 : "f", reg_names[REGNO (x)] + 2);
11831 if (GET_CODE (x) != REG
11832 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11833 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11834 /* Bad value for wCG register number. */
11836 output_operand_lossage ("invalid operand for code '%c'", code);
11841 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11844 /* Print an iWMMXt control register name. */
11846 if (GET_CODE (x) != CONST_INT
11848 || INTVAL (x) >= 16)
11849 /* Bad value for wC register number. */
11851 output_operand_lossage ("invalid operand for code '%c'", code);
11857 static const char * wc_reg_names [16] =
11859 "wCID", "wCon", "wCSSF", "wCASF",
11860 "wC4", "wC5", "wC6", "wC7",
11861 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11862 "wC12", "wC13", "wC14", "wC15"
11865 fprintf (stream, wc_reg_names [INTVAL (x)]);
11869 /* Print a VFP double precision register name. */
11872 int mode = GET_MODE (x);
11875 if (mode != DImode && mode != DFmode)
11877 output_operand_lossage ("invalid operand for code '%c'", code);
11881 if (GET_CODE (x) != REG
11882 || !IS_VFP_REGNUM (REGNO (x)))
11884 output_operand_lossage ("invalid operand for code '%c'", code);
11888 num = REGNO(x) - FIRST_VFP_REGNUM;
11891 output_operand_lossage ("invalid operand for code '%c'", code);
11895 fprintf (stream, "d%d", num >> 1);
11902 output_operand_lossage ("missing operand");
11906 switch (GET_CODE (x))
11909 asm_fprintf (stream, "%r", REGNO (x));
11913 output_memory_reference_mode = GET_MODE (x);
11914 output_address (XEXP (x, 0));
11918 fprintf (stream, "#%s", fp_immediate_constant (x));
11922 gcc_assert (GET_CODE (x) != NEG);
11923 fputc ('#', stream);
11924 output_addr_const (stream, x);
11930 #ifndef AOF_ASSEMBLER
11931 /* Target hook for assembling integer objects. The ARM version needs to
11932 handle word-sized values specially. */
11934 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11936 if (size == UNITS_PER_WORD && aligned_p)
11938 fputs ("\t.word\t", asm_out_file);
11939 output_addr_const (asm_out_file, x);
11941 /* Mark symbols as position independent. We only do this in the
11942 .text segment, not in the .data segment. */
11943 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11944 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11946 if (GET_CODE (x) == SYMBOL_REF
11947 && (CONSTANT_POOL_ADDRESS_P (x)
11948 || SYMBOL_REF_LOCAL_P (x)))
11949 fputs ("(GOTOFF)", asm_out_file);
11950 else if (GET_CODE (x) == LABEL_REF)
11951 fputs ("(GOTOFF)", asm_out_file);
11953 fputs ("(GOT)", asm_out_file);
11955 fputc ('\n', asm_out_file);
11959 if (arm_vector_mode_supported_p (GET_MODE (x)))
11963 gcc_assert (GET_CODE (x) == CONST_VECTOR);
11965 units = CONST_VECTOR_NUNITS (x);
11967 switch (GET_MODE (x))
11969 case V2SImode: size = 4; break;
11970 case V4HImode: size = 2; break;
11971 case V8QImode: size = 1; break;
11973 gcc_unreachable ();
11976 for (i = 0; i < units; i++)
11980 elt = CONST_VECTOR_ELT (x, i);
11982 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11988 return default_assemble_integer (x, size, aligned_p);
11992 /* Add a function to the list of static constructors. */
11995 arm_elf_asm_constructor (rtx symbol, int priority)
11999 if (!TARGET_AAPCS_BASED)
12001 default_named_section_asm_out_constructor (symbol, priority);
12005 /* Put these in the .init_array section, using a special relocation. */
12006 if (priority != DEFAULT_INIT_PRIORITY)
12009 sprintf (buf, ".init_array.%.5u", priority);
12010 s = get_section (buf, SECTION_WRITE, NULL_TREE);
12015 switch_to_section (s);
12016 assemble_align (POINTER_SIZE);
12017 fputs ("\t.word\t", asm_out_file);
12018 output_addr_const (asm_out_file, symbol);
12019 fputs ("(target1)\n", asm_out_file);
12023 /* A finite state machine takes care of noticing whether or not instructions
12024 can be conditionally executed, and thus decrease execution time and code
12025 size by deleting branch instructions. The fsm is controlled by
12026 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12028 /* The state of the fsm controlling condition codes are:
12029 0: normal, do nothing special
12030 1: make ASM_OUTPUT_OPCODE not output this instruction
12031 2: make ASM_OUTPUT_OPCODE not output this instruction
12032 3: make instructions conditional
12033 4: make instructions conditional
12035 State transitions (state->state by whom under condition):
12036 0 -> 1 final_prescan_insn if the `target' is a label
12037 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12038 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12039 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12040 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12041 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12042 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12043 (the target insn is arm_target_insn).
12045 If the jump clobbers the conditions then we use states 2 and 4.
12047 A similar thing can be done with conditional return insns.
12049 XXX In case the `target' is an unconditional branch, this conditionalising
12050 of the instructions always reduces code size, but not always execution
12051 time. But then, I want to reduce the code size to somewhere near what
12052 /bin/cc produces. */
12054 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12055 instructions. When a COND_EXEC instruction is seen the subsequent
12056 instructions are scanned so that multiple conditional instructions can be
12057 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12058 specify the length and true/false mask for the IT block. These will be
12059 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12061 /* Returns the index of the ARM condition code string in
12062 `arm_condition_codes'. COMPARISON should be an rtx like
12063 `(eq (...) (...))'. */
12064 static enum arm_cond_code
12065 get_arm_condition_code (rtx comparison)
12067 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
12069 enum rtx_code comp_code = GET_CODE (comparison);
12071 if (GET_MODE_CLASS (mode) != MODE_CC)
12072 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
12073 XEXP (comparison, 1));
12077 case CC_DNEmode: code = ARM_NE; goto dominance;
12078 case CC_DEQmode: code = ARM_EQ; goto dominance;
12079 case CC_DGEmode: code = ARM_GE; goto dominance;
12080 case CC_DGTmode: code = ARM_GT; goto dominance;
12081 case CC_DLEmode: code = ARM_LE; goto dominance;
12082 case CC_DLTmode: code = ARM_LT; goto dominance;
12083 case CC_DGEUmode: code = ARM_CS; goto dominance;
12084 case CC_DGTUmode: code = ARM_HI; goto dominance;
12085 case CC_DLEUmode: code = ARM_LS; goto dominance;
12086 case CC_DLTUmode: code = ARM_CC;
12089 gcc_assert (comp_code == EQ || comp_code == NE);
12091 if (comp_code == EQ)
12092 return ARM_INVERSE_CONDITION_CODE (code);
12098 case NE: return ARM_NE;
12099 case EQ: return ARM_EQ;
12100 case GE: return ARM_PL;
12101 case LT: return ARM_MI;
12102 default: gcc_unreachable ();
12108 case NE: return ARM_NE;
12109 case EQ: return ARM_EQ;
12110 default: gcc_unreachable ();
12116 case NE: return ARM_MI;
12117 case EQ: return ARM_PL;
12118 default: gcc_unreachable ();
12123 /* These encodings assume that AC=1 in the FPA system control
12124 byte. This allows us to handle all cases except UNEQ and
12128 case GE: return ARM_GE;
12129 case GT: return ARM_GT;
12130 case LE: return ARM_LS;
12131 case LT: return ARM_MI;
12132 case NE: return ARM_NE;
12133 case EQ: return ARM_EQ;
12134 case ORDERED: return ARM_VC;
12135 case UNORDERED: return ARM_VS;
12136 case UNLT: return ARM_LT;
12137 case UNLE: return ARM_LE;
12138 case UNGT: return ARM_HI;
12139 case UNGE: return ARM_PL;
12140 /* UNEQ and LTGT do not have a representation. */
12141 case UNEQ: /* Fall through. */
12142 case LTGT: /* Fall through. */
12143 default: gcc_unreachable ();
12149 case NE: return ARM_NE;
12150 case EQ: return ARM_EQ;
12151 case GE: return ARM_LE;
12152 case GT: return ARM_LT;
12153 case LE: return ARM_GE;
12154 case LT: return ARM_GT;
12155 case GEU: return ARM_LS;
12156 case GTU: return ARM_CC;
12157 case LEU: return ARM_CS;
12158 case LTU: return ARM_HI;
12159 default: gcc_unreachable ();
12165 case LTU: return ARM_CS;
12166 case GEU: return ARM_CC;
12167 default: gcc_unreachable ();
12173 case NE: return ARM_NE;
12174 case EQ: return ARM_EQ;
12175 case GE: return ARM_GE;
12176 case GT: return ARM_GT;
12177 case LE: return ARM_LE;
12178 case LT: return ARM_LT;
12179 case GEU: return ARM_CS;
12180 case GTU: return ARM_HI;
12181 case LEU: return ARM_LS;
12182 case LTU: return ARM_CC;
12183 default: gcc_unreachable ();
12186 default: gcc_unreachable ();
12190 /* Tell arm_asm_ouput_opcode to output IT blocks for conditionally executed
12193 thumb2_final_prescan_insn (rtx insn)
12195 rtx first_insn = insn;
12196 rtx body = PATTERN (insn);
12198 enum arm_cond_code code;
12202 /* Remove the previous insn from the count of insns to be output. */
12203 if (arm_condexec_count)
12204 arm_condexec_count--;
12206 /* Nothing to do if we are already inside a conditional block. */
12207 if (arm_condexec_count)
12210 if (GET_CODE (body) != COND_EXEC)
12213 /* Conditional jumps are implemented directly. */
12214 if (GET_CODE (insn) == JUMP_INSN)
12217 predicate = COND_EXEC_TEST (body);
12218 arm_current_cc = get_arm_condition_code (predicate);
12220 n = get_attr_ce_count (insn);
12221 arm_condexec_count = 1;
12222 arm_condexec_mask = (1 << n) - 1;
12223 arm_condexec_masklen = n;
12224 /* See if subsequent instructions can be combined into the same block. */
12227 insn = next_nonnote_insn (insn);
12229 /* Jumping into the middle of an IT block is illegal, so a label or
12230 barrier terminates the block. */
12231 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
12234 body = PATTERN (insn);
12235 /* USE and CLOBBER aren't really insns, so just skip them. */
12236 if (GET_CODE (body) == USE
12237 || GET_CODE (body) == CLOBBER)
12239 arm_condexec_count++;
12243 /* ??? Recognise conditional jumps, and combine them with IT blocks. */
12244 if (GET_CODE (body) != COND_EXEC)
12246 /* Allow up to 4 conditionally executed instructions in a block. */
12247 n = get_attr_ce_count (insn);
12248 if (arm_condexec_masklen + n > 4)
12251 predicate = COND_EXEC_TEST (body);
12252 code = get_arm_condition_code (predicate);
12253 mask = (1 << n) - 1;
12254 if (arm_current_cc == code)
12255 arm_condexec_mask |= (mask << arm_condexec_masklen);
12256 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
12259 arm_condexec_count++;
12260 arm_condexec_masklen += n;
12262 /* A jump must be the last instruction in a conditional block. */
12263 if (GET_CODE(insn) == JUMP_INSN)
12266 /* Restore recog_data (getting the attributes of other insns can
12267 destroy this array, but final.c assumes that it remains intact
12268 across this call). */
12269 extract_constrain_insn_cached (first_insn);
12273 arm_final_prescan_insn (rtx insn)
12275 /* BODY will hold the body of INSN. */
12276 rtx body = PATTERN (insn);
12278 /* This will be 1 if trying to repeat the trick, and things need to be
12279 reversed if it appears to fail. */
12282 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12283 taken are clobbered, even if the rtl suggests otherwise. It also
12284 means that we have to grub around within the jump expression to find
12285 out what the conditions are when the jump isn't taken. */
12286 int jump_clobbers = 0;
12288 /* If we start with a return insn, we only succeed if we find another one. */
12289 int seeking_return = 0;
12291 /* START_INSN will hold the insn from where we start looking. This is the
12292 first insn after the following code_label if REVERSE is true. */
12293 rtx start_insn = insn;
12295 /* If in state 4, check if the target branch is reached, in order to
12296 change back to state 0. */
12297 if (arm_ccfsm_state == 4)
12299 if (insn == arm_target_insn)
12301 arm_target_insn = NULL;
12302 arm_ccfsm_state = 0;
12307 /* If in state 3, it is possible to repeat the trick, if this insn is an
12308 unconditional branch to a label, and immediately following this branch
12309 is the previous target label which is only used once, and the label this
12310 branch jumps to is not too far off. */
12311 if (arm_ccfsm_state == 3)
12313 if (simplejump_p (insn))
12315 start_insn = next_nonnote_insn (start_insn);
12316 if (GET_CODE (start_insn) == BARRIER)
12318 /* XXX Isn't this always a barrier? */
12319 start_insn = next_nonnote_insn (start_insn);
12321 if (GET_CODE (start_insn) == CODE_LABEL
12322 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12323 && LABEL_NUSES (start_insn) == 1)
12328 else if (GET_CODE (body) == RETURN)
12330 start_insn = next_nonnote_insn (start_insn);
12331 if (GET_CODE (start_insn) == BARRIER)
12332 start_insn = next_nonnote_insn (start_insn);
12333 if (GET_CODE (start_insn) == CODE_LABEL
12334 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12335 && LABEL_NUSES (start_insn) == 1)
12338 seeking_return = 1;
12347 gcc_assert (!arm_ccfsm_state || reverse);
12348 if (GET_CODE (insn) != JUMP_INSN)
12351 /* This jump might be paralleled with a clobber of the condition codes
12352 the jump should always come first */
12353 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
12354 body = XVECEXP (body, 0, 0);
12357 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
12358 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
12361 int fail = FALSE, succeed = FALSE;
12362 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12363 int then_not_else = TRUE;
12364 rtx this_insn = start_insn, label = 0;
12366 /* If the jump cannot be done with one instruction, we cannot
12367 conditionally execute the instruction in the inverse case. */
12368 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
12374 /* Register the insn jumped to. */
12377 if (!seeking_return)
12378 label = XEXP (SET_SRC (body), 0);
12380 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
12381 label = XEXP (XEXP (SET_SRC (body), 1), 0);
12382 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
12384 label = XEXP (XEXP (SET_SRC (body), 2), 0);
12385 then_not_else = FALSE;
12387 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
12388 seeking_return = 1;
12389 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
12391 seeking_return = 1;
12392 then_not_else = FALSE;
12395 gcc_unreachable ();
12397 /* See how many insns this branch skips, and what kind of insns. If all
12398 insns are okay, and the label or unconditional branch to the same
12399 label is not too far away, succeed. */
12400 for (insns_skipped = 0;
12401 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
12405 this_insn = next_nonnote_insn (this_insn);
12409 switch (GET_CODE (this_insn))
12412 /* Succeed if it is the target label, otherwise fail since
12413 control falls in from somewhere else. */
12414 if (this_insn == label)
12418 arm_ccfsm_state = 2;
12419 this_insn = next_nonnote_insn (this_insn);
12422 arm_ccfsm_state = 1;
12430 /* Succeed if the following insn is the target label.
12432 If return insns are used then the last insn in a function
12433 will be a barrier. */
12434 this_insn = next_nonnote_insn (this_insn);
12435 if (this_insn && this_insn == label)
12439 arm_ccfsm_state = 2;
12440 this_insn = next_nonnote_insn (this_insn);
12443 arm_ccfsm_state = 1;
12451 /* The AAPCS says that conditional calls should not be
12452 used since they make interworking inefficient (the
12453 linker can't transform BL<cond> into BLX). That's
12454 only a problem if the machine has BLX. */
12461 /* Succeed if the following insn is the target label, or
12462 if the following two insns are a barrier and the
12464 this_insn = next_nonnote_insn (this_insn);
12465 if (this_insn && GET_CODE (this_insn) == BARRIER)
12466 this_insn = next_nonnote_insn (this_insn);
12468 if (this_insn && this_insn == label
12469 && insns_skipped < max_insns_skipped)
12473 arm_ccfsm_state = 2;
12474 this_insn = next_nonnote_insn (this_insn);
12477 arm_ccfsm_state = 1;
12485 /* If this is an unconditional branch to the same label, succeed.
12486 If it is to another label, do nothing. If it is conditional,
12488 /* XXX Probably, the tests for SET and the PC are
12491 scanbody = PATTERN (this_insn);
12492 if (GET_CODE (scanbody) == SET
12493 && GET_CODE (SET_DEST (scanbody)) == PC)
12495 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
12496 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
12498 arm_ccfsm_state = 2;
12501 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
12504 /* Fail if a conditional return is undesirable (e.g. on a
12505 StrongARM), but still allow this if optimizing for size. */
12506 else if (GET_CODE (scanbody) == RETURN
12507 && !use_return_insn (TRUE, NULL)
12510 else if (GET_CODE (scanbody) == RETURN
12513 arm_ccfsm_state = 2;
12516 else if (GET_CODE (scanbody) == PARALLEL)
12518 switch (get_attr_conds (this_insn))
12528 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
12533 /* Instructions using or affecting the condition codes make it
12535 scanbody = PATTERN (this_insn);
12536 if (!(GET_CODE (scanbody) == SET
12537 || GET_CODE (scanbody) == PARALLEL)
12538 || get_attr_conds (this_insn) != CONDS_NOCOND)
12541 /* A conditional cirrus instruction must be followed by
12542 a non Cirrus instruction. However, since we
12543 conditionalize instructions in this function and by
12544 the time we get here we can't add instructions
12545 (nops), because shorten_branches() has already been
12546 called, we will disable conditionalizing Cirrus
12547 instructions to be safe. */
12548 if (GET_CODE (scanbody) != USE
12549 && GET_CODE (scanbody) != CLOBBER
12550 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
12560 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
12561 arm_target_label = CODE_LABEL_NUMBER (label);
12564 gcc_assert (seeking_return || arm_ccfsm_state == 2);
12566 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
12568 this_insn = next_nonnote_insn (this_insn);
12569 gcc_assert (!this_insn
12570 || (GET_CODE (this_insn) != BARRIER
12571 && GET_CODE (this_insn) != CODE_LABEL));
12575 /* Oh, dear! we ran off the end.. give up. */
12576 extract_constrain_insn_cached (insn);
12577 arm_ccfsm_state = 0;
12578 arm_target_insn = NULL;
12581 arm_target_insn = this_insn;
12585 gcc_assert (!reverse);
12587 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
12589 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
12590 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12591 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
12592 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12596 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12599 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
12603 if (reverse || then_not_else)
12604 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12607 /* Restore recog_data (getting the attributes of other insns can
12608 destroy this array, but final.c assumes that it remains intact
12609 across this call. */
12610 extract_constrain_insn_cached (insn);
12614 /* Output IT instructions. */
12616 thumb2_asm_output_opcode (FILE * stream)
12621 if (arm_condexec_mask)
12623 for (n = 0; n < arm_condexec_masklen; n++)
12624 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
12626 asm_fprintf(stream, "i%s\t%s\n\t", buff,
12627 arm_condition_codes[arm_current_cc]);
12628 arm_condexec_mask = 0;
12632 /* Returns true if REGNO is a valid register
12633 for holding a quantity of type MODE. */
12635 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
12637 if (GET_MODE_CLASS (mode) == MODE_CC)
12638 return (regno == CC_REGNUM
12639 || (TARGET_HARD_FLOAT && TARGET_VFP
12640 && regno == VFPCC_REGNUM));
12643 /* For the Thumb we only allow values bigger than SImode in
12644 registers 0 - 6, so that there is always a second low
12645 register available to hold the upper part of the value.
12646 We probably we ought to ensure that the register is the
12647 start of an even numbered register pair. */
12648 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
12650 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
12651 && IS_CIRRUS_REGNUM (regno))
12652 /* We have outlawed SI values in Cirrus registers because they
12653 reside in the lower 32 bits, but SF values reside in the
12654 upper 32 bits. This causes gcc all sorts of grief. We can't
12655 even split the registers into pairs because Cirrus SI values
12656 get sign extended to 64bits-- aldyh. */
12657 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
12659 if (TARGET_HARD_FLOAT && TARGET_VFP
12660 && IS_VFP_REGNUM (regno))
12662 if (mode == SFmode || mode == SImode)
12665 /* DFmode values are only valid in even register pairs. */
12666 if (mode == DFmode)
12667 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
12671 if (TARGET_REALLY_IWMMXT)
12673 if (IS_IWMMXT_GR_REGNUM (regno))
12674 return mode == SImode;
12676 if (IS_IWMMXT_REGNUM (regno))
12677 return VALID_IWMMXT_REG_MODE (mode);
12680 /* We allow any value to be stored in the general registers.
12681 Restrict doubleword quantities to even register pairs so that we can
12683 if (regno <= LAST_ARM_REGNUM)
12684 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
12686 if (regno == FRAME_POINTER_REGNUM
12687 || regno == ARG_POINTER_REGNUM)
12688 /* We only allow integers in the fake hard registers. */
12689 return GET_MODE_CLASS (mode) == MODE_INT;
12691 /* The only registers left are the FPA registers
12692 which we only allow to hold FP values. */
12693 return (TARGET_HARD_FLOAT && TARGET_FPA
12694 && GET_MODE_CLASS (mode) == MODE_FLOAT
12695 && regno >= FIRST_FPA_REGNUM
12696 && regno <= LAST_FPA_REGNUM);
12699 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
12700 not used in arm mode. */
12702 arm_regno_class (int regno)
12706 if (regno == STACK_POINTER_REGNUM)
12708 if (regno == CC_REGNUM)
12715 if (TARGET_THUMB2 && regno < 8)
12718 if ( regno <= LAST_ARM_REGNUM
12719 || regno == FRAME_POINTER_REGNUM
12720 || regno == ARG_POINTER_REGNUM)
12721 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
12723 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
12724 return TARGET_THUMB2 ? CC_REG : NO_REGS;
12726 if (IS_CIRRUS_REGNUM (regno))
12727 return CIRRUS_REGS;
12729 if (IS_VFP_REGNUM (regno))
12732 if (IS_IWMMXT_REGNUM (regno))
12733 return IWMMXT_REGS;
12735 if (IS_IWMMXT_GR_REGNUM (regno))
12736 return IWMMXT_GR_REGS;
12741 /* Handle a special case when computing the offset
12742 of an argument from the frame pointer. */
12744 arm_debugger_arg_offset (int value, rtx addr)
12748 /* We are only interested if dbxout_parms() failed to compute the offset. */
12752 /* We can only cope with the case where the address is held in a register. */
12753 if (GET_CODE (addr) != REG)
12756 /* If we are using the frame pointer to point at the argument, then
12757 an offset of 0 is correct. */
12758 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
12761 /* If we are using the stack pointer to point at the
12762 argument, then an offset of 0 is correct. */
12763 /* ??? Check this is consistent with thumb2 frame layout. */
12764 if ((TARGET_THUMB || !frame_pointer_needed)
12765 && REGNO (addr) == SP_REGNUM)
12768 /* Oh dear. The argument is pointed to by a register rather
12769 than being held in a register, or being stored at a known
12770 offset from the frame pointer. Since GDB only understands
12771 those two kinds of argument we must translate the address
12772 held in the register into an offset from the frame pointer.
12773 We do this by searching through the insns for the function
12774 looking to see where this register gets its value. If the
12775 register is initialized from the frame pointer plus an offset
12776 then we are in luck and we can continue, otherwise we give up.
12778 This code is exercised by producing debugging information
12779 for a function with arguments like this:
12781 double func (double a, double b, int c, double d) {return d;}
12783 Without this code the stab for parameter 'd' will be set to
12784 an offset of 0 from the frame pointer, rather than 8. */
12786 /* The if() statement says:
12788 If the insn is a normal instruction
12789 and if the insn is setting the value in a register
12790 and if the register being set is the register holding the address of the argument
12791 and if the address is computing by an addition
12792 that involves adding to a register
12793 which is the frame pointer
12798 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12800 if ( GET_CODE (insn) == INSN
12801 && GET_CODE (PATTERN (insn)) == SET
12802 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
12803 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
12804 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
12805 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12806 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
12809 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
12818 warning (0, "unable to compute real location of stacked parameter");
12819 value = 8; /* XXX magic hack */
12825 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12828 if ((MASK) & insn_flags) \
12829 add_builtin_function ((NAME), (TYPE), (CODE), \
12830 BUILT_IN_MD, NULL, NULL_TREE); \
12834 struct builtin_description
12836 const unsigned int mask;
12837 const enum insn_code icode;
12838 const char * const name;
12839 const enum arm_builtins code;
12840 const enum rtx_code comparison;
12841 const unsigned int flag;
12844 static const struct builtin_description bdesc_2arg[] =
12846 #define IWMMXT_BUILTIN(code, string, builtin) \
12847 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12848 ARM_BUILTIN_##builtin, 0, 0 },
12850 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
12851 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
12852 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
12853 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
12854 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
12855 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
12856 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
12857 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
12858 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
12859 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
12860 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
12861 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
12862 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
12863 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12864 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12865 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12866 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12867 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12868 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12869 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12870 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12871 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12872 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12873 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12874 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12875 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12876 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12877 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12878 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12879 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12880 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12881 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12882 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12883 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12884 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12885 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12886 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12887 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12888 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12889 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12890 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12891 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12892 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12893 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12894 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12895 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12896 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12897 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12898 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12899 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12900 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12901 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12902 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12903 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12904 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12905 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
12906 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
12907 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
12909 #define IWMMXT_BUILTIN2(code, builtin) \
12910 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12912 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
12913 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
12914 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
12915 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
12916 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
12917 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
12918 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
12919 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
12920 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
12921 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
12922 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
12923 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
12924 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
12925 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
12926 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
12927 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
12928 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
12929 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
12930 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
12931 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
12932 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
12933 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
12934 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
12935 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
12936 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
12937 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
12938 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
12939 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
12940 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
12941 IWMMXT_BUILTIN2 (rordi3, WRORDI)
12942 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
12943 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
12946 static const struct builtin_description bdesc_1arg[] =
12948 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
12949 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
12950 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
12951 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
12952 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
12953 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
12954 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
12955 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
12956 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
12957 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
12958 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
12959 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
12960 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
12961 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
12962 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
12963 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
12964 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
12965 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
12968 /* Set up all the iWMMXt builtins. This is
12969 not called if TARGET_IWMMXT is zero. */
12972 arm_init_iwmmxt_builtins (void)
12974 const struct builtin_description * d;
12976 tree endlink = void_list_node;
12978 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
12979 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
12980 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
12983 = build_function_type (integer_type_node,
12984 tree_cons (NULL_TREE, integer_type_node, endlink));
12985 tree v8qi_ftype_v8qi_v8qi_int
12986 = build_function_type (V8QI_type_node,
12987 tree_cons (NULL_TREE, V8QI_type_node,
12988 tree_cons (NULL_TREE, V8QI_type_node,
12989 tree_cons (NULL_TREE,
12992 tree v4hi_ftype_v4hi_int
12993 = build_function_type (V4HI_type_node,
12994 tree_cons (NULL_TREE, V4HI_type_node,
12995 tree_cons (NULL_TREE, integer_type_node,
12997 tree v2si_ftype_v2si_int
12998 = build_function_type (V2SI_type_node,
12999 tree_cons (NULL_TREE, V2SI_type_node,
13000 tree_cons (NULL_TREE, integer_type_node,
13002 tree v2si_ftype_di_di
13003 = build_function_type (V2SI_type_node,
13004 tree_cons (NULL_TREE, long_long_integer_type_node,
13005 tree_cons (NULL_TREE, long_long_integer_type_node,
13007 tree di_ftype_di_int
13008 = build_function_type (long_long_integer_type_node,
13009 tree_cons (NULL_TREE, long_long_integer_type_node,
13010 tree_cons (NULL_TREE, integer_type_node,
13012 tree di_ftype_di_int_int
13013 = build_function_type (long_long_integer_type_node,
13014 tree_cons (NULL_TREE, long_long_integer_type_node,
13015 tree_cons (NULL_TREE, integer_type_node,
13016 tree_cons (NULL_TREE,
13019 tree int_ftype_v8qi
13020 = build_function_type (integer_type_node,
13021 tree_cons (NULL_TREE, V8QI_type_node,
13023 tree int_ftype_v4hi
13024 = build_function_type (integer_type_node,
13025 tree_cons (NULL_TREE, V4HI_type_node,
13027 tree int_ftype_v2si
13028 = build_function_type (integer_type_node,
13029 tree_cons (NULL_TREE, V2SI_type_node,
13031 tree int_ftype_v8qi_int
13032 = build_function_type (integer_type_node,
13033 tree_cons (NULL_TREE, V8QI_type_node,
13034 tree_cons (NULL_TREE, integer_type_node,
13036 tree int_ftype_v4hi_int
13037 = build_function_type (integer_type_node,
13038 tree_cons (NULL_TREE, V4HI_type_node,
13039 tree_cons (NULL_TREE, integer_type_node,
13041 tree int_ftype_v2si_int
13042 = build_function_type (integer_type_node,
13043 tree_cons (NULL_TREE, V2SI_type_node,
13044 tree_cons (NULL_TREE, integer_type_node,
13046 tree v8qi_ftype_v8qi_int_int
13047 = build_function_type (V8QI_type_node,
13048 tree_cons (NULL_TREE, V8QI_type_node,
13049 tree_cons (NULL_TREE, integer_type_node,
13050 tree_cons (NULL_TREE,
13053 tree v4hi_ftype_v4hi_int_int
13054 = build_function_type (V4HI_type_node,
13055 tree_cons (NULL_TREE, V4HI_type_node,
13056 tree_cons (NULL_TREE, integer_type_node,
13057 tree_cons (NULL_TREE,
13060 tree v2si_ftype_v2si_int_int
13061 = build_function_type (V2SI_type_node,
13062 tree_cons (NULL_TREE, V2SI_type_node,
13063 tree_cons (NULL_TREE, integer_type_node,
13064 tree_cons (NULL_TREE,
13067 /* Miscellaneous. */
13068 tree v8qi_ftype_v4hi_v4hi
13069 = build_function_type (V8QI_type_node,
13070 tree_cons (NULL_TREE, V4HI_type_node,
13071 tree_cons (NULL_TREE, V4HI_type_node,
13073 tree v4hi_ftype_v2si_v2si
13074 = build_function_type (V4HI_type_node,
13075 tree_cons (NULL_TREE, V2SI_type_node,
13076 tree_cons (NULL_TREE, V2SI_type_node,
13078 tree v2si_ftype_v4hi_v4hi
13079 = build_function_type (V2SI_type_node,
13080 tree_cons (NULL_TREE, V4HI_type_node,
13081 tree_cons (NULL_TREE, V4HI_type_node,
13083 tree v2si_ftype_v8qi_v8qi
13084 = build_function_type (V2SI_type_node,
13085 tree_cons (NULL_TREE, V8QI_type_node,
13086 tree_cons (NULL_TREE, V8QI_type_node,
13088 tree v4hi_ftype_v4hi_di
13089 = build_function_type (V4HI_type_node,
13090 tree_cons (NULL_TREE, V4HI_type_node,
13091 tree_cons (NULL_TREE,
13092 long_long_integer_type_node,
13094 tree v2si_ftype_v2si_di
13095 = build_function_type (V2SI_type_node,
13096 tree_cons (NULL_TREE, V2SI_type_node,
13097 tree_cons (NULL_TREE,
13098 long_long_integer_type_node,
13100 tree void_ftype_int_int
13101 = build_function_type (void_type_node,
13102 tree_cons (NULL_TREE, integer_type_node,
13103 tree_cons (NULL_TREE, integer_type_node,
13106 = build_function_type (long_long_unsigned_type_node, endlink);
13108 = build_function_type (long_long_integer_type_node,
13109 tree_cons (NULL_TREE, V8QI_type_node,
13112 = build_function_type (long_long_integer_type_node,
13113 tree_cons (NULL_TREE, V4HI_type_node,
13116 = build_function_type (long_long_integer_type_node,
13117 tree_cons (NULL_TREE, V2SI_type_node,
13119 tree v2si_ftype_v4hi
13120 = build_function_type (V2SI_type_node,
13121 tree_cons (NULL_TREE, V4HI_type_node,
13123 tree v4hi_ftype_v8qi
13124 = build_function_type (V4HI_type_node,
13125 tree_cons (NULL_TREE, V8QI_type_node,
13128 tree di_ftype_di_v4hi_v4hi
13129 = build_function_type (long_long_unsigned_type_node,
13130 tree_cons (NULL_TREE,
13131 long_long_unsigned_type_node,
13132 tree_cons (NULL_TREE, V4HI_type_node,
13133 tree_cons (NULL_TREE,
13137 tree di_ftype_v4hi_v4hi
13138 = build_function_type (long_long_unsigned_type_node,
13139 tree_cons (NULL_TREE, V4HI_type_node,
13140 tree_cons (NULL_TREE, V4HI_type_node,
13143 /* Normal vector binops. */
13144 tree v8qi_ftype_v8qi_v8qi
13145 = build_function_type (V8QI_type_node,
13146 tree_cons (NULL_TREE, V8QI_type_node,
13147 tree_cons (NULL_TREE, V8QI_type_node,
13149 tree v4hi_ftype_v4hi_v4hi
13150 = build_function_type (V4HI_type_node,
13151 tree_cons (NULL_TREE, V4HI_type_node,
13152 tree_cons (NULL_TREE, V4HI_type_node,
13154 tree v2si_ftype_v2si_v2si
13155 = build_function_type (V2SI_type_node,
13156 tree_cons (NULL_TREE, V2SI_type_node,
13157 tree_cons (NULL_TREE, V2SI_type_node,
13159 tree di_ftype_di_di
13160 = build_function_type (long_long_unsigned_type_node,
13161 tree_cons (NULL_TREE, long_long_unsigned_type_node,
13162 tree_cons (NULL_TREE,
13163 long_long_unsigned_type_node,
13166 /* Add all builtins that are more or less simple operations on two
13168 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13170 /* Use one of the operands; the target can have a different mode for
13171 mask-generating compares. */
13172 enum machine_mode mode;
13178 mode = insn_data[d->icode].operand[1].mode;
13183 type = v8qi_ftype_v8qi_v8qi;
13186 type = v4hi_ftype_v4hi_v4hi;
13189 type = v2si_ftype_v2si_v2si;
13192 type = di_ftype_di_di;
13196 gcc_unreachable ();
13199 def_mbuiltin (d->mask, d->name, type, d->code);
13202 /* Add the remaining MMX insns with somewhat more complicated types. */
13203 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
13204 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
13205 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
13207 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
13208 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
13209 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
13210 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
13211 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
13212 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
13214 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
13215 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
13216 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
13217 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
13218 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
13219 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
13221 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
13222 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
13223 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
13224 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
13225 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
13226 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
13228 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
13229 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
13230 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
13231 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
13232 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
13233 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
13235 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
13237 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
13238 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
13239 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
13240 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
13242 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
13243 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
13244 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
13245 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
13246 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
13247 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
13248 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
13249 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
13250 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
13252 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
13253 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
13254 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
13256 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
13257 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
13258 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
13260 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
13261 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
13262 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
13263 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
13264 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
13265 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
13267 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
13268 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
13269 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
13270 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
13271 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
13272 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
13273 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
13274 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
13275 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
13276 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
13277 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
13278 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
13280 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
13281 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
13282 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
13283 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
13285 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
13286 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
13287 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
13288 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
13289 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
13290 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
13291 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
13295 arm_init_tls_builtins (void)
13298 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
13299 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
13301 ftype = build_function_type (ptr_type_node, void_list_node);
13302 add_builtin_function ("__builtin_thread_pointer", ftype,
13303 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
13304 NULL, const_nothrow);
13308 arm_init_builtins (void)
13310 arm_init_tls_builtins ();
13312 if (TARGET_REALLY_IWMMXT)
13313 arm_init_iwmmxt_builtins ();
13316 /* Errors in the source file can cause expand_expr to return const0_rtx
13317 where we expect a vector. To avoid crashing, use one of the vector
13318 clear instructions. */
13321 safe_vector_operand (rtx x, enum machine_mode mode)
13323 if (x != const0_rtx)
13325 x = gen_reg_rtx (mode);
13327 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
13328 : gen_rtx_SUBREG (DImode, x, 0)));
13332 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13335 arm_expand_binop_builtin (enum insn_code icode,
13336 tree arglist, rtx target)
13339 tree arg0 = TREE_VALUE (arglist);
13340 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13341 rtx op0 = expand_normal (arg0);
13342 rtx op1 = expand_normal (arg1);
13343 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13344 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13345 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
13347 if (VECTOR_MODE_P (mode0))
13348 op0 = safe_vector_operand (op0, mode0);
13349 if (VECTOR_MODE_P (mode1))
13350 op1 = safe_vector_operand (op1, mode1);
13353 || GET_MODE (target) != tmode
13354 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13355 target = gen_reg_rtx (tmode);
13357 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
13359 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13360 op0 = copy_to_mode_reg (mode0, op0);
13361 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13362 op1 = copy_to_mode_reg (mode1, op1);
13364 pat = GEN_FCN (icode) (target, op0, op1);
13371 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13374 arm_expand_unop_builtin (enum insn_code icode,
13375 tree arglist, rtx target, int do_load)
13378 tree arg0 = TREE_VALUE (arglist);
13379 rtx op0 = expand_normal (arg0);
13380 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13381 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13384 || GET_MODE (target) != tmode
13385 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13386 target = gen_reg_rtx (tmode);
13388 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
13391 if (VECTOR_MODE_P (mode0))
13392 op0 = safe_vector_operand (op0, mode0);
13394 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13395 op0 = copy_to_mode_reg (mode0, op0);
13398 pat = GEN_FCN (icode) (target, op0);
13405 /* Expand an expression EXP that calls a built-in function,
13406 with result going to TARGET if that's convenient
13407 (and in mode MODE if that's convenient).
13408 SUBTARGET may be used as the target for computing one of EXP's operands.
13409 IGNORE is nonzero if the value is to be ignored. */
13412 arm_expand_builtin (tree exp,
13414 rtx subtarget ATTRIBUTE_UNUSED,
13415 enum machine_mode mode ATTRIBUTE_UNUSED,
13416 int ignore ATTRIBUTE_UNUSED)
13418 const struct builtin_description * d;
13419 enum insn_code icode;
13420 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
13421 tree arglist = TREE_OPERAND (exp, 1);
13429 int fcode = DECL_FUNCTION_CODE (fndecl);
13431 enum machine_mode tmode;
13432 enum machine_mode mode0;
13433 enum machine_mode mode1;
13434 enum machine_mode mode2;
13438 case ARM_BUILTIN_TEXTRMSB:
13439 case ARM_BUILTIN_TEXTRMUB:
13440 case ARM_BUILTIN_TEXTRMSH:
13441 case ARM_BUILTIN_TEXTRMUH:
13442 case ARM_BUILTIN_TEXTRMSW:
13443 case ARM_BUILTIN_TEXTRMUW:
13444 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
13445 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
13446 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
13447 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
13448 : CODE_FOR_iwmmxt_textrmw);
13450 arg0 = TREE_VALUE (arglist);
13451 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13452 op0 = expand_normal (arg0);
13453 op1 = expand_normal (arg1);
13454 tmode = insn_data[icode].operand[0].mode;
13455 mode0 = insn_data[icode].operand[1].mode;
13456 mode1 = insn_data[icode].operand[2].mode;
13458 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13459 op0 = copy_to_mode_reg (mode0, op0);
13460 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13462 /* @@@ better error message */
13463 error ("selector must be an immediate");
13464 return gen_reg_rtx (tmode);
13467 || GET_MODE (target) != tmode
13468 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13469 target = gen_reg_rtx (tmode);
13470 pat = GEN_FCN (icode) (target, op0, op1);
13476 case ARM_BUILTIN_TINSRB:
13477 case ARM_BUILTIN_TINSRH:
13478 case ARM_BUILTIN_TINSRW:
13479 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
13480 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
13481 : CODE_FOR_iwmmxt_tinsrw);
13482 arg0 = TREE_VALUE (arglist);
13483 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13484 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
13485 op0 = expand_normal (arg0);
13486 op1 = expand_normal (arg1);
13487 op2 = expand_normal (arg2);
13488 tmode = insn_data[icode].operand[0].mode;
13489 mode0 = insn_data[icode].operand[1].mode;
13490 mode1 = insn_data[icode].operand[2].mode;
13491 mode2 = insn_data[icode].operand[3].mode;
13493 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13494 op0 = copy_to_mode_reg (mode0, op0);
13495 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13496 op1 = copy_to_mode_reg (mode1, op1);
13497 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13499 /* @@@ better error message */
13500 error ("selector must be an immediate");
13504 || GET_MODE (target) != tmode
13505 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13506 target = gen_reg_rtx (tmode);
13507 pat = GEN_FCN (icode) (target, op0, op1, op2);
13513 case ARM_BUILTIN_SETWCX:
13514 arg0 = TREE_VALUE (arglist);
13515 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13516 op0 = force_reg (SImode, expand_normal (arg0));
13517 op1 = expand_normal (arg1);
13518 emit_insn (gen_iwmmxt_tmcr (op1, op0));
13521 case ARM_BUILTIN_GETWCX:
13522 arg0 = TREE_VALUE (arglist);
13523 op0 = expand_normal (arg0);
13524 target = gen_reg_rtx (SImode);
13525 emit_insn (gen_iwmmxt_tmrc (target, op0));
13528 case ARM_BUILTIN_WSHUFH:
13529 icode = CODE_FOR_iwmmxt_wshufh;
13530 arg0 = TREE_VALUE (arglist);
13531 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13532 op0 = expand_normal (arg0);
13533 op1 = expand_normal (arg1);
13534 tmode = insn_data[icode].operand[0].mode;
13535 mode1 = insn_data[icode].operand[1].mode;
13536 mode2 = insn_data[icode].operand[2].mode;
13538 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
13539 op0 = copy_to_mode_reg (mode1, op0);
13540 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
13542 /* @@@ better error message */
13543 error ("mask must be an immediate");
13547 || GET_MODE (target) != tmode
13548 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13549 target = gen_reg_rtx (tmode);
13550 pat = GEN_FCN (icode) (target, op0, op1);
13556 case ARM_BUILTIN_WSADB:
13557 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
13558 case ARM_BUILTIN_WSADH:
13559 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
13560 case ARM_BUILTIN_WSADBZ:
13561 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
13562 case ARM_BUILTIN_WSADHZ:
13563 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
13565 /* Several three-argument builtins. */
13566 case ARM_BUILTIN_WMACS:
13567 case ARM_BUILTIN_WMACU:
13568 case ARM_BUILTIN_WALIGN:
13569 case ARM_BUILTIN_TMIA:
13570 case ARM_BUILTIN_TMIAPH:
13571 case ARM_BUILTIN_TMIATT:
13572 case ARM_BUILTIN_TMIATB:
13573 case ARM_BUILTIN_TMIABT:
13574 case ARM_BUILTIN_TMIABB:
13575 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
13576 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
13577 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
13578 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
13579 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
13580 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
13581 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
13582 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
13583 : CODE_FOR_iwmmxt_walign);
13584 arg0 = TREE_VALUE (arglist);
13585 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
13586 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
13587 op0 = expand_normal (arg0);
13588 op1 = expand_normal (arg1);
13589 op2 = expand_normal (arg2);
13590 tmode = insn_data[icode].operand[0].mode;
13591 mode0 = insn_data[icode].operand[1].mode;
13592 mode1 = insn_data[icode].operand[2].mode;
13593 mode2 = insn_data[icode].operand[3].mode;
13595 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13596 op0 = copy_to_mode_reg (mode0, op0);
13597 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13598 op1 = copy_to_mode_reg (mode1, op1);
13599 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13600 op2 = copy_to_mode_reg (mode2, op2);
13602 || GET_MODE (target) != tmode
13603 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13604 target = gen_reg_rtx (tmode);
13605 pat = GEN_FCN (icode) (target, op0, op1, op2);
13611 case ARM_BUILTIN_WZERO:
13612 target = gen_reg_rtx (DImode);
13613 emit_insn (gen_iwmmxt_clrdi (target));
13616 case ARM_BUILTIN_THREAD_POINTER:
13617 return arm_load_tp (target);
13623 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13624 if (d->code == (const enum arm_builtins) fcode)
13625 return arm_expand_binop_builtin (d->icode, arglist, target);
13627 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13628 if (d->code == (const enum arm_builtins) fcode)
13629 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
13631 /* @@@ Should really do something sensible here. */
13635 /* Return the number (counting from 0) of
13636 the least significant set bit in MASK. */
13639 number_of_first_bit_set (unsigned mask)
13644 (mask & (1 << bit)) == 0;
13651 /* Emit code to push or pop registers to or from the stack. F is the
13652 assembly file. MASK is the registers to push or pop. PUSH is
13653 nonzero if we should push, and zero if we should pop. For debugging
13654 output, if pushing, adjust CFA_OFFSET by the amount of space added
13655 to the stack. REAL_REGS should have the same number of bits set as
13656 MASK, and will be used instead (in the same order) to describe which
13657 registers were saved - this is used to mark the save slots when we
13658 push high registers after moving them to low registers. */
13660 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
13661 unsigned long real_regs)
13664 int lo_mask = mask & 0xFF;
13665 int pushed_words = 0;
13669 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
13671 /* Special case. Do not generate a POP PC statement here, do it in
13673 thumb_exit (f, -1);
13677 if (ARM_EABI_UNWIND_TABLES && push)
13679 fprintf (f, "\t.save\t{");
13680 for (regno = 0; regno < 15; regno++)
13682 if (real_regs & (1 << regno))
13684 if (real_regs & ((1 << regno) -1))
13686 asm_fprintf (f, "%r", regno);
13689 fprintf (f, "}\n");
13692 fprintf (f, "\t%s\t{", push ? "push" : "pop");
13694 /* Look at the low registers first. */
13695 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
13699 asm_fprintf (f, "%r", regno);
13701 if ((lo_mask & ~1) != 0)
13708 if (push && (mask & (1 << LR_REGNUM)))
13710 /* Catch pushing the LR. */
13714 asm_fprintf (f, "%r", LR_REGNUM);
13718 else if (!push && (mask & (1 << PC_REGNUM)))
13720 /* Catch popping the PC. */
13721 if (TARGET_INTERWORK || TARGET_BACKTRACE
13722 || current_function_calls_eh_return)
13724 /* The PC is never poped directly, instead
13725 it is popped into r3 and then BX is used. */
13726 fprintf (f, "}\n");
13728 thumb_exit (f, -1);
13737 asm_fprintf (f, "%r", PC_REGNUM);
13741 fprintf (f, "}\n");
13743 if (push && pushed_words && dwarf2out_do_frame ())
13745 char *l = dwarf2out_cfi_label ();
13746 int pushed_mask = real_regs;
13748 *cfa_offset += pushed_words * 4;
13749 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13752 pushed_mask = real_regs;
13753 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13755 if (pushed_mask & 1)
13756 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13761 /* Generate code to return from a thumb function.
13762 If 'reg_containing_return_addr' is -1, then the return address is
13763 actually on the stack, at the stack pointer. */
13765 thumb_exit (FILE *f, int reg_containing_return_addr)
13767 unsigned regs_available_for_popping;
13768 unsigned regs_to_pop;
13770 unsigned available;
13774 int restore_a4 = FALSE;
13776 /* Compute the registers we need to pop. */
13780 if (reg_containing_return_addr == -1)
13782 regs_to_pop |= 1 << LR_REGNUM;
13786 if (TARGET_BACKTRACE)
13788 /* Restore the (ARM) frame pointer and stack pointer. */
13789 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
13793 /* If there is nothing to pop then just emit the BX instruction and
13795 if (pops_needed == 0)
13797 if (current_function_calls_eh_return)
13798 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13800 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13803 /* Otherwise if we are not supporting interworking and we have not created
13804 a backtrace structure and the function was not entered in ARM mode then
13805 just pop the return address straight into the PC. */
13806 else if (!TARGET_INTERWORK
13807 && !TARGET_BACKTRACE
13808 && !is_called_in_ARM_mode (current_function_decl)
13809 && !current_function_calls_eh_return)
13811 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
13815 /* Find out how many of the (return) argument registers we can corrupt. */
13816 regs_available_for_popping = 0;
13818 /* If returning via __builtin_eh_return, the bottom three registers
13819 all contain information needed for the return. */
13820 if (current_function_calls_eh_return)
13824 /* If we can deduce the registers used from the function's
13825 return value. This is more reliable that examining
13826 regs_ever_live[] because that will be set if the register is
13827 ever used in the function, not just if the register is used
13828 to hold a return value. */
13830 if (current_function_return_rtx != 0)
13831 mode = GET_MODE (current_function_return_rtx);
13833 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13835 size = GET_MODE_SIZE (mode);
13839 /* In a void function we can use any argument register.
13840 In a function that returns a structure on the stack
13841 we can use the second and third argument registers. */
13842 if (mode == VOIDmode)
13843 regs_available_for_popping =
13844 (1 << ARG_REGISTER (1))
13845 | (1 << ARG_REGISTER (2))
13846 | (1 << ARG_REGISTER (3));
13848 regs_available_for_popping =
13849 (1 << ARG_REGISTER (2))
13850 | (1 << ARG_REGISTER (3));
13852 else if (size <= 4)
13853 regs_available_for_popping =
13854 (1 << ARG_REGISTER (2))
13855 | (1 << ARG_REGISTER (3));
13856 else if (size <= 8)
13857 regs_available_for_popping =
13858 (1 << ARG_REGISTER (3));
13861 /* Match registers to be popped with registers into which we pop them. */
13862 for (available = regs_available_for_popping,
13863 required = regs_to_pop;
13864 required != 0 && available != 0;
13865 available &= ~(available & - available),
13866 required &= ~(required & - required))
13869 /* If we have any popping registers left over, remove them. */
13871 regs_available_for_popping &= ~available;
13873 /* Otherwise if we need another popping register we can use
13874 the fourth argument register. */
13875 else if (pops_needed)
13877 /* If we have not found any free argument registers and
13878 reg a4 contains the return address, we must move it. */
13879 if (regs_available_for_popping == 0
13880 && reg_containing_return_addr == LAST_ARG_REGNUM)
13882 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13883 reg_containing_return_addr = LR_REGNUM;
13885 else if (size > 12)
13887 /* Register a4 is being used to hold part of the return value,
13888 but we have dire need of a free, low register. */
13891 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
13894 if (reg_containing_return_addr != LAST_ARG_REGNUM)
13896 /* The fourth argument register is available. */
13897 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
13903 /* Pop as many registers as we can. */
13904 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13905 regs_available_for_popping);
13907 /* Process the registers we popped. */
13908 if (reg_containing_return_addr == -1)
13910 /* The return address was popped into the lowest numbered register. */
13911 regs_to_pop &= ~(1 << LR_REGNUM);
13913 reg_containing_return_addr =
13914 number_of_first_bit_set (regs_available_for_popping);
13916 /* Remove this register for the mask of available registers, so that
13917 the return address will not be corrupted by further pops. */
13918 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
13921 /* If we popped other registers then handle them here. */
13922 if (regs_available_for_popping)
13926 /* Work out which register currently contains the frame pointer. */
13927 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
13929 /* Move it into the correct place. */
13930 asm_fprintf (f, "\tmov\t%r, %r\n",
13931 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
13933 /* (Temporarily) remove it from the mask of popped registers. */
13934 regs_available_for_popping &= ~(1 << frame_pointer);
13935 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
13937 if (regs_available_for_popping)
13941 /* We popped the stack pointer as well,
13942 find the register that contains it. */
13943 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
13945 /* Move it into the stack register. */
13946 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
13948 /* At this point we have popped all necessary registers, so
13949 do not worry about restoring regs_available_for_popping
13950 to its correct value:
13952 assert (pops_needed == 0)
13953 assert (regs_available_for_popping == (1 << frame_pointer))
13954 assert (regs_to_pop == (1 << STACK_POINTER)) */
13958 /* Since we have just move the popped value into the frame
13959 pointer, the popping register is available for reuse, and
13960 we know that we still have the stack pointer left to pop. */
13961 regs_available_for_popping |= (1 << frame_pointer);
13965 /* If we still have registers left on the stack, but we no longer have
13966 any registers into which we can pop them, then we must move the return
13967 address into the link register and make available the register that
13969 if (regs_available_for_popping == 0 && pops_needed > 0)
13971 regs_available_for_popping |= 1 << reg_containing_return_addr;
13973 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
13974 reg_containing_return_addr);
13976 reg_containing_return_addr = LR_REGNUM;
13979 /* If we have registers left on the stack then pop some more.
13980 We know that at most we will want to pop FP and SP. */
13981 if (pops_needed > 0)
13986 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13987 regs_available_for_popping);
13989 /* We have popped either FP or SP.
13990 Move whichever one it is into the correct register. */
13991 popped_into = number_of_first_bit_set (regs_available_for_popping);
13992 move_to = number_of_first_bit_set (regs_to_pop);
13994 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
13996 regs_to_pop &= ~(1 << move_to);
14001 /* If we still have not popped everything then we must have only
14002 had one register available to us and we are now popping the SP. */
14003 if (pops_needed > 0)
14007 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14008 regs_available_for_popping);
14010 popped_into = number_of_first_bit_set (regs_available_for_popping);
14012 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
14014 assert (regs_to_pop == (1 << STACK_POINTER))
14015 assert (pops_needed == 1)
14019 /* If necessary restore the a4 register. */
14022 if (reg_containing_return_addr != LR_REGNUM)
14024 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14025 reg_containing_return_addr = LR_REGNUM;
14028 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
14031 if (current_function_calls_eh_return)
14032 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14034 /* Return to caller. */
14035 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14040 thumb1_final_prescan_insn (rtx insn)
14042 if (flag_print_asm_name)
14043 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
14044 INSN_ADDRESSES (INSN_UID (insn)));
14048 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
14050 unsigned HOST_WIDE_INT mask = 0xff;
14053 if (val == 0) /* XXX */
14056 for (i = 0; i < 25; i++)
14057 if ((val & (mask << i)) == val)
14063 /* Returns nonzero if the current function contains,
14064 or might contain a far jump. */
14066 thumb_far_jump_used_p (void)
14070 /* This test is only important for leaf functions. */
14071 /* assert (!leaf_function_p ()); */
14073 /* If we have already decided that far jumps may be used,
14074 do not bother checking again, and always return true even if
14075 it turns out that they are not being used. Once we have made
14076 the decision that far jumps are present (and that hence the link
14077 register will be pushed onto the stack) we cannot go back on it. */
14078 if (cfun->machine->far_jump_used)
14081 /* If this function is not being called from the prologue/epilogue
14082 generation code then it must be being called from the
14083 INITIAL_ELIMINATION_OFFSET macro. */
14084 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
14086 /* In this case we know that we are being asked about the elimination
14087 of the arg pointer register. If that register is not being used,
14088 then there are no arguments on the stack, and we do not have to
14089 worry that a far jump might force the prologue to push the link
14090 register, changing the stack offsets. In this case we can just
14091 return false, since the presence of far jumps in the function will
14092 not affect stack offsets.
14094 If the arg pointer is live (or if it was live, but has now been
14095 eliminated and so set to dead) then we do have to test to see if
14096 the function might contain a far jump. This test can lead to some
14097 false negatives, since before reload is completed, then length of
14098 branch instructions is not known, so gcc defaults to returning their
14099 longest length, which in turn sets the far jump attribute to true.
14101 A false negative will not result in bad code being generated, but it
14102 will result in a needless push and pop of the link register. We
14103 hope that this does not occur too often.
14105 If we need doubleword stack alignment this could affect the other
14106 elimination offsets so we can't risk getting it wrong. */
14107 if (regs_ever_live [ARG_POINTER_REGNUM])
14108 cfun->machine->arg_pointer_live = 1;
14109 else if (!cfun->machine->arg_pointer_live)
14113 /* Check to see if the function contains a branch
14114 insn with the far jump attribute set. */
14115 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14117 if (GET_CODE (insn) == JUMP_INSN
14118 /* Ignore tablejump patterns. */
14119 && GET_CODE (PATTERN (insn)) != ADDR_VEC
14120 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
14121 && get_attr_far_jump (insn) == FAR_JUMP_YES
14124 /* Record the fact that we have decided that
14125 the function does use far jumps. */
14126 cfun->machine->far_jump_used = 1;
14134 /* Return nonzero if FUNC must be entered in ARM mode. */
14136 is_called_in_ARM_mode (tree func)
14138 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
14140 /* Ignore the problem about functions whose address is taken. */
14141 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
14145 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
14151 /* The bits which aren't usefully expanded as rtl. */
14153 thumb_unexpanded_epilogue (void)
14156 unsigned long live_regs_mask = 0;
14157 int high_regs_pushed = 0;
14158 int had_to_push_lr;
14161 if (return_used_this_function)
14164 if (IS_NAKED (arm_current_func_type ()))
14167 live_regs_mask = thumb1_compute_save_reg_mask ();
14168 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14170 /* If we can deduce the registers used from the function's return value.
14171 This is more reliable that examining regs_ever_live[] because that
14172 will be set if the register is ever used in the function, not just if
14173 the register is used to hold a return value. */
14174 size = arm_size_return_regs ();
14176 /* The prolog may have pushed some high registers to use as
14177 work registers. e.g. the testsuite file:
14178 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14179 compiles to produce:
14180 push {r4, r5, r6, r7, lr}
14184 as part of the prolog. We have to undo that pushing here. */
14186 if (high_regs_pushed)
14188 unsigned long mask = live_regs_mask & 0xff;
14191 /* The available low registers depend on the size of the value we are
14199 /* Oh dear! We have no low registers into which we can pop
14202 ("no low registers available for popping high registers");
14204 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
14205 if (live_regs_mask & (1 << next_hi_reg))
14208 while (high_regs_pushed)
14210 /* Find lo register(s) into which the high register(s) can
14212 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14214 if (mask & (1 << regno))
14215 high_regs_pushed--;
14216 if (high_regs_pushed == 0)
14220 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
14222 /* Pop the values into the low register(s). */
14223 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
14225 /* Move the value(s) into the high registers. */
14226 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14228 if (mask & (1 << regno))
14230 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
14233 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
14234 if (live_regs_mask & (1 << next_hi_reg))
14239 live_regs_mask &= ~0x0f00;
14242 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
14243 live_regs_mask &= 0xff;
14245 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
14247 /* Pop the return address into the PC. */
14248 if (had_to_push_lr)
14249 live_regs_mask |= 1 << PC_REGNUM;
14251 /* Either no argument registers were pushed or a backtrace
14252 structure was created which includes an adjusted stack
14253 pointer, so just pop everything. */
14254 if (live_regs_mask)
14255 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14258 /* We have either just popped the return address into the
14259 PC or it is was kept in LR for the entire function. */
14260 if (!had_to_push_lr)
14261 thumb_exit (asm_out_file, LR_REGNUM);
14265 /* Pop everything but the return address. */
14266 if (live_regs_mask)
14267 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14270 if (had_to_push_lr)
14274 /* We have no free low regs, so save one. */
14275 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
14279 /* Get the return address into a temporary register. */
14280 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
14281 1 << LAST_ARG_REGNUM);
14285 /* Move the return address to lr. */
14286 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
14288 /* Restore the low register. */
14289 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
14294 regno = LAST_ARG_REGNUM;
14299 /* Remove the argument registers that were pushed onto the stack. */
14300 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
14301 SP_REGNUM, SP_REGNUM,
14302 current_function_pretend_args_size);
14304 thumb_exit (asm_out_file, regno);
14310 /* Functions to save and restore machine-specific function data. */
14311 static struct machine_function *
14312 arm_init_machine_status (void)
14314 struct machine_function *machine;
14315 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
14317 #if ARM_FT_UNKNOWN != 0
14318 machine->func_type = ARM_FT_UNKNOWN;
14323 /* Return an RTX indicating where the return address to the
14324 calling function can be found. */
14326 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
14331 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
14334 /* Do anything needed before RTL is emitted for each function. */
14336 arm_init_expanders (void)
14338 /* Arrange to initialize and mark the machine per-function status. */
14339 init_machine_status = arm_init_machine_status;
14341 /* This is to stop the combine pass optimizing away the alignment
14342 adjustment of va_arg. */
14343 /* ??? It is claimed that this should not be necessary. */
14345 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
14349 /* Like arm_compute_initial_elimination offset. Simpler because there
14350 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14351 to point at the base of the local variables after static stack
14352 space for a function has been allocated. */
14355 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
14357 arm_stack_offsets *offsets;
14359 offsets = arm_get_frame_offsets ();
14363 case ARG_POINTER_REGNUM:
14366 case STACK_POINTER_REGNUM:
14367 return offsets->outgoing_args - offsets->saved_args;
14369 case FRAME_POINTER_REGNUM:
14370 return offsets->soft_frame - offsets->saved_args;
14372 case ARM_HARD_FRAME_POINTER_REGNUM:
14373 return offsets->saved_regs - offsets->saved_args;
14375 case THUMB_HARD_FRAME_POINTER_REGNUM:
14376 return offsets->locals_base - offsets->saved_args;
14379 gcc_unreachable ();
14383 case FRAME_POINTER_REGNUM:
14386 case STACK_POINTER_REGNUM:
14387 return offsets->outgoing_args - offsets->soft_frame;
14389 case ARM_HARD_FRAME_POINTER_REGNUM:
14390 return offsets->saved_regs - offsets->soft_frame;
14392 case THUMB_HARD_FRAME_POINTER_REGNUM:
14393 return offsets->locals_base - offsets->soft_frame;
14396 gcc_unreachable ();
14401 gcc_unreachable ();
14405 /* Generate the rest of a function's prologue. */
14407 thumb1_expand_prologue (void)
14411 HOST_WIDE_INT amount;
14412 arm_stack_offsets *offsets;
14413 unsigned long func_type;
14415 unsigned long live_regs_mask;
14417 func_type = arm_current_func_type ();
14419 /* Naked functions don't have prologues. */
14420 if (IS_NAKED (func_type))
14423 if (IS_INTERRUPT (func_type))
14425 error ("interrupt Service Routines cannot be coded in Thumb mode");
14429 live_regs_mask = thumb1_compute_save_reg_mask ();
14430 /* Load the pic register before setting the frame pointer,
14431 so we can use r7 as a temporary work register. */
14432 if (flag_pic && arm_pic_register != INVALID_REGNUM)
14433 arm_load_pic_register (live_regs_mask);
14435 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
14436 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
14437 stack_pointer_rtx);
14439 offsets = arm_get_frame_offsets ();
14440 amount = offsets->outgoing_args - offsets->saved_regs;
14445 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14446 GEN_INT (- amount)));
14447 RTX_FRAME_RELATED_P (insn) = 1;
14453 /* The stack decrement is too big for an immediate value in a single
14454 insn. In theory we could issue multiple subtracts, but after
14455 three of them it becomes more space efficient to place the full
14456 value in the constant pool and load into a register. (Also the
14457 ARM debugger really likes to see only one stack decrement per
14458 function). So instead we look for a scratch register into which
14459 we can load the decrement, and then we subtract this from the
14460 stack pointer. Unfortunately on the thumb the only available
14461 scratch registers are the argument registers, and we cannot use
14462 these as they may hold arguments to the function. Instead we
14463 attempt to locate a call preserved register which is used by this
14464 function. If we can find one, then we know that it will have
14465 been pushed at the start of the prologue and so we can corrupt
14467 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
14468 if (live_regs_mask & (1 << regno)
14469 && !(frame_pointer_needed
14470 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
14473 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
14475 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
14477 /* Choose an arbitrary, non-argument low register. */
14478 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
14480 /* Save it by copying it into a high, scratch register. */
14481 emit_insn (gen_movsi (spare, reg));
14482 /* Add a USE to stop propagate_one_insn() from barfing. */
14483 emit_insn (gen_prologue_use (spare));
14485 /* Decrement the stack. */
14486 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14487 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14488 stack_pointer_rtx, reg));
14489 RTX_FRAME_RELATED_P (insn) = 1;
14490 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14491 plus_constant (stack_pointer_rtx,
14493 RTX_FRAME_RELATED_P (dwarf) = 1;
14495 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14498 /* Restore the low register's original value. */
14499 emit_insn (gen_movsi (reg, spare));
14501 /* Emit a USE of the restored scratch register, so that flow
14502 analysis will not consider the restore redundant. The
14503 register won't be used again in this function and isn't
14504 restored by the epilogue. */
14505 emit_insn (gen_prologue_use (reg));
14509 reg = gen_rtx_REG (SImode, regno);
14511 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14513 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14514 stack_pointer_rtx, reg));
14515 RTX_FRAME_RELATED_P (insn) = 1;
14516 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14517 plus_constant (stack_pointer_rtx,
14519 RTX_FRAME_RELATED_P (dwarf) = 1;
14521 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14527 if (frame_pointer_needed)
14528 thumb_set_frame_pointer (offsets);
14530 /* If we are profiling, make sure no instructions are scheduled before
14531 the call to mcount. Similarly if the user has requested no
14532 scheduling in the prolog. Similarly if we want non-call exceptions
14533 using the EABI unwinder, to prevent faulting instructions from being
14534 swapped with a stack adjustment. */
14535 if (current_function_profile || !TARGET_SCHED_PROLOG
14536 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
14537 emit_insn (gen_blockage ());
14539 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
14540 if (live_regs_mask & 0xff)
14541 cfun->machine->lr_save_eliminated = 0;
14543 /* If the link register is being kept alive, with the return address in it,
14544 then make sure that it does not get reused by the ce2 pass. */
14545 if (cfun->machine->lr_save_eliminated)
14546 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
14551 thumb1_expand_epilogue (void)
14553 HOST_WIDE_INT amount;
14554 arm_stack_offsets *offsets;
14557 /* Naked functions don't have prologues. */
14558 if (IS_NAKED (arm_current_func_type ()))
14561 offsets = arm_get_frame_offsets ();
14562 amount = offsets->outgoing_args - offsets->saved_regs;
14564 if (frame_pointer_needed)
14566 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
14567 amount = offsets->locals_base - offsets->saved_regs;
14573 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14574 GEN_INT (amount)));
14577 /* r3 is always free in the epilogue. */
14578 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
14580 emit_insn (gen_movsi (reg, GEN_INT (amount)));
14581 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
14585 /* Emit a USE (stack_pointer_rtx), so that
14586 the stack adjustment will not be deleted. */
14587 emit_insn (gen_prologue_use (stack_pointer_rtx));
14589 if (current_function_profile || !TARGET_SCHED_PROLOG)
14590 emit_insn (gen_blockage ());
14592 /* Emit a clobber for each insn that will be restored in the epilogue,
14593 so that flow2 will get register lifetimes correct. */
14594 for (regno = 0; regno < 13; regno++)
14595 if (regs_ever_live[regno] && !call_used_regs[regno])
14596 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
14598 if (! regs_ever_live[LR_REGNUM])
14599 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
14603 thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14605 unsigned long live_regs_mask = 0;
14606 unsigned long l_mask;
14607 unsigned high_regs_pushed = 0;
14608 int cfa_offset = 0;
14611 if (IS_NAKED (arm_current_func_type ()))
14614 if (is_called_in_ARM_mode (current_function_decl))
14618 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
14619 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
14621 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14623 /* Generate code sequence to switch us into Thumb mode. */
14624 /* The .code 32 directive has already been emitted by
14625 ASM_DECLARE_FUNCTION_NAME. */
14626 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
14627 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
14629 /* Generate a label, so that the debugger will notice the
14630 change in instruction sets. This label is also used by
14631 the assembler to bypass the ARM code when this function
14632 is called from a Thumb encoded function elsewhere in the
14633 same file. Hence the definition of STUB_NAME here must
14634 agree with the definition in gas/config/tc-arm.c. */
14636 #define STUB_NAME ".real_start_of"
14638 fprintf (f, "\t.code\t16\n");
14640 if (arm_dllexport_name_p (name))
14641 name = arm_strip_name_encoding (name);
14643 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
14644 fprintf (f, "\t.thumb_func\n");
14645 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
14648 if (current_function_pretend_args_size)
14650 /* Output unwind directive for the stack adjustment. */
14651 if (ARM_EABI_UNWIND_TABLES)
14652 fprintf (f, "\t.pad #%d\n",
14653 current_function_pretend_args_size);
14655 if (cfun->machine->uses_anonymous_args)
14659 fprintf (f, "\tpush\t{");
14661 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
14663 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
14664 regno <= LAST_ARG_REGNUM;
14666 asm_fprintf (f, "%r%s", regno,
14667 regno == LAST_ARG_REGNUM ? "" : ", ");
14669 fprintf (f, "}\n");
14672 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
14673 SP_REGNUM, SP_REGNUM,
14674 current_function_pretend_args_size);
14676 /* We don't need to record the stores for unwinding (would it
14677 help the debugger any if we did?), but record the change in
14678 the stack pointer. */
14679 if (dwarf2out_do_frame ())
14681 char *l = dwarf2out_cfi_label ();
14683 cfa_offset = cfa_offset + current_function_pretend_args_size;
14684 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14688 /* Get the registers we are going to push. */
14689 live_regs_mask = thumb1_compute_save_reg_mask ();
14690 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14691 l_mask = live_regs_mask & 0x40ff;
14692 /* Then count how many other high registers will need to be pushed. */
14693 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14695 if (TARGET_BACKTRACE)
14698 unsigned work_register;
14700 /* We have been asked to create a stack backtrace structure.
14701 The code looks like this:
14705 0 sub SP, #16 Reserve space for 4 registers.
14706 2 push {R7} Push low registers.
14707 4 add R7, SP, #20 Get the stack pointer before the push.
14708 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14709 8 mov R7, PC Get hold of the start of this code plus 12.
14710 10 str R7, [SP, #16] Store it.
14711 12 mov R7, FP Get hold of the current frame pointer.
14712 14 str R7, [SP, #4] Store it.
14713 16 mov R7, LR Get hold of the current return address.
14714 18 str R7, [SP, #12] Store it.
14715 20 add R7, SP, #16 Point at the start of the backtrace structure.
14716 22 mov FP, R7 Put this value into the frame pointer. */
14718 work_register = thumb_find_work_register (live_regs_mask);
14720 if (ARM_EABI_UNWIND_TABLES)
14721 asm_fprintf (f, "\t.pad #16\n");
14724 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14725 SP_REGNUM, SP_REGNUM);
14727 if (dwarf2out_do_frame ())
14729 char *l = dwarf2out_cfi_label ();
14731 cfa_offset = cfa_offset + 16;
14732 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14737 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14738 offset = bit_count (l_mask) * UNITS_PER_WORD;
14743 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14744 offset + 16 + current_function_pretend_args_size);
14746 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14749 /* Make sure that the instruction fetching the PC is in the right place
14750 to calculate "start of backtrace creation code + 12". */
14753 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14754 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14756 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14757 ARM_HARD_FRAME_POINTER_REGNUM);
14758 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14763 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14764 ARM_HARD_FRAME_POINTER_REGNUM);
14765 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14767 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14768 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14772 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
14773 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14775 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14777 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14778 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
14780 /* Optimization: If we are not pushing any low registers but we are going
14781 to push some high registers then delay our first push. This will just
14782 be a push of LR and we can combine it with the push of the first high
14784 else if ((l_mask & 0xff) != 0
14785 || (high_regs_pushed == 0 && l_mask))
14786 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14788 if (high_regs_pushed)
14790 unsigned pushable_regs;
14791 unsigned next_hi_reg;
14793 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
14794 if (live_regs_mask & (1 << next_hi_reg))
14797 pushable_regs = l_mask & 0xff;
14799 if (pushable_regs == 0)
14800 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
14802 while (high_regs_pushed > 0)
14804 unsigned long real_regs_mask = 0;
14806 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
14808 if (pushable_regs & (1 << regno))
14810 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
14812 high_regs_pushed --;
14813 real_regs_mask |= (1 << next_hi_reg);
14815 if (high_regs_pushed)
14817 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
14819 if (live_regs_mask & (1 << next_hi_reg))
14824 pushable_regs &= ~((1 << regno) - 1);
14830 /* If we had to find a work register and we have not yet
14831 saved the LR then add it to the list of regs to push. */
14832 if (l_mask == (1 << LR_REGNUM))
14834 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
14836 real_regs_mask | (1 << LR_REGNUM));
14840 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
14845 /* Handle the case of a double word load into a low register from
14846 a computed memory address. The computed address may involve a
14847 register which is overwritten by the load. */
14849 thumb_load_double_from_address (rtx *operands)
14857 gcc_assert (GET_CODE (operands[0]) == REG);
14858 gcc_assert (GET_CODE (operands[1]) == MEM);
14860 /* Get the memory address. */
14861 addr = XEXP (operands[1], 0);
14863 /* Work out how the memory address is computed. */
14864 switch (GET_CODE (addr))
14867 operands[2] = adjust_address (operands[1], SImode, 4);
14869 if (REGNO (operands[0]) == REGNO (addr))
14871 output_asm_insn ("ldr\t%H0, %2", operands);
14872 output_asm_insn ("ldr\t%0, %1", operands);
14876 output_asm_insn ("ldr\t%0, %1", operands);
14877 output_asm_insn ("ldr\t%H0, %2", operands);
14882 /* Compute <address> + 4 for the high order load. */
14883 operands[2] = adjust_address (operands[1], SImode, 4);
14885 output_asm_insn ("ldr\t%0, %1", operands);
14886 output_asm_insn ("ldr\t%H0, %2", operands);
14890 arg1 = XEXP (addr, 0);
14891 arg2 = XEXP (addr, 1);
14893 if (CONSTANT_P (arg1))
14894 base = arg2, offset = arg1;
14896 base = arg1, offset = arg2;
14898 gcc_assert (GET_CODE (base) == REG);
14900 /* Catch the case of <address> = <reg> + <reg> */
14901 if (GET_CODE (offset) == REG)
14903 int reg_offset = REGNO (offset);
14904 int reg_base = REGNO (base);
14905 int reg_dest = REGNO (operands[0]);
14907 /* Add the base and offset registers together into the
14908 higher destination register. */
14909 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
14910 reg_dest + 1, reg_base, reg_offset);
14912 /* Load the lower destination register from the address in
14913 the higher destination register. */
14914 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
14915 reg_dest, reg_dest + 1);
14917 /* Load the higher destination register from its own address
14919 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
14920 reg_dest + 1, reg_dest + 1);
14924 /* Compute <address> + 4 for the high order load. */
14925 operands[2] = adjust_address (operands[1], SImode, 4);
14927 /* If the computed address is held in the low order register
14928 then load the high order register first, otherwise always
14929 load the low order register first. */
14930 if (REGNO (operands[0]) == REGNO (base))
14932 output_asm_insn ("ldr\t%H0, %2", operands);
14933 output_asm_insn ("ldr\t%0, %1", operands);
14937 output_asm_insn ("ldr\t%0, %1", operands);
14938 output_asm_insn ("ldr\t%H0, %2", operands);
14944 /* With no registers to worry about we can just load the value
14946 operands[2] = adjust_address (operands[1], SImode, 4);
14948 output_asm_insn ("ldr\t%H0, %2", operands);
14949 output_asm_insn ("ldr\t%0, %1", operands);
14953 gcc_unreachable ();
14960 thumb_output_move_mem_multiple (int n, rtx *operands)
14967 if (REGNO (operands[4]) > REGNO (operands[5]))
14970 operands[4] = operands[5];
14973 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
14974 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
14978 if (REGNO (operands[4]) > REGNO (operands[5]))
14981 operands[4] = operands[5];
14984 if (REGNO (operands[5]) > REGNO (operands[6]))
14987 operands[5] = operands[6];
14990 if (REGNO (operands[4]) > REGNO (operands[5]))
14993 operands[4] = operands[5];
14997 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
14998 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
15002 gcc_unreachable ();
15008 /* Output a call-via instruction for thumb state. */
15010 thumb_call_via_reg (rtx reg)
15012 int regno = REGNO (reg);
15015 gcc_assert (regno < LR_REGNUM);
15017 /* If we are in the normal text section we can use a single instance
15018 per compilation unit. If we are doing function sections, then we need
15019 an entry per section, since we can't rely on reachability. */
15020 if (in_section == text_section)
15022 thumb_call_reg_needed = 1;
15024 if (thumb_call_via_label[regno] == NULL)
15025 thumb_call_via_label[regno] = gen_label_rtx ();
15026 labelp = thumb_call_via_label + regno;
15030 if (cfun->machine->call_via[regno] == NULL)
15031 cfun->machine->call_via[regno] = gen_label_rtx ();
15032 labelp = cfun->machine->call_via + regno;
15035 output_asm_insn ("bl\t%a0", labelp);
15039 /* Routines for generating rtl. */
15041 thumb_expand_movmemqi (rtx *operands)
15043 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
15044 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
15045 HOST_WIDE_INT len = INTVAL (operands[2]);
15046 HOST_WIDE_INT offset = 0;
15050 emit_insn (gen_movmem12b (out, in, out, in));
15056 emit_insn (gen_movmem8b (out, in, out, in));
15062 rtx reg = gen_reg_rtx (SImode);
15063 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
15064 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
15071 rtx reg = gen_reg_rtx (HImode);
15072 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
15073 plus_constant (in, offset))));
15074 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
15082 rtx reg = gen_reg_rtx (QImode);
15083 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
15084 plus_constant (in, offset))));
15085 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
15091 thumb_reload_out_hi (rtx *operands)
15093 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
15096 /* Handle reading a half-word from memory during reload. */
15098 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
15100 gcc_unreachable ();
15103 /* Return the length of a function name prefix
15104 that starts with the character 'c'. */
15106 arm_get_strip_length (int c)
15110 ARM_NAME_ENCODING_LENGTHS
15115 /* Return a pointer to a function's name with any
15116 and all prefix encodings stripped from it. */
15118 arm_strip_name_encoding (const char *name)
15122 while ((skip = arm_get_strip_length (* name)))
15128 /* If there is a '*' anywhere in the name's prefix, then
15129 emit the stripped name verbatim, otherwise prepend an
15130 underscore if leading underscores are being used. */
15132 arm_asm_output_labelref (FILE *stream, const char *name)
15137 while ((skip = arm_get_strip_length (* name)))
15139 verbatim |= (*name == '*');
15144 fputs (name, stream);
15146 asm_fprintf (stream, "%U%s", name);
15150 arm_file_start (void)
15154 if (TARGET_UNIFIED_ASM)
15155 asm_fprintf (asm_out_file, "\t.syntax unified\n");
15159 const char *fpu_name;
15160 if (arm_select[0].string)
15161 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
15162 else if (arm_select[1].string)
15163 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
15165 asm_fprintf (asm_out_file, "\t.cpu %s\n",
15166 all_cores[arm_default_cpu].name);
15168 if (TARGET_SOFT_FLOAT)
15171 fpu_name = "softvfp";
15173 fpu_name = "softfpa";
15177 switch (arm_fpu_arch)
15182 case FPUTYPE_FPA_EMU2:
15185 case FPUTYPE_FPA_EMU3:
15188 case FPUTYPE_MAVERICK:
15189 fpu_name = "maverick";
15192 if (TARGET_HARD_FLOAT)
15193 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
15194 if (TARGET_HARD_FLOAT_ABI)
15195 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
15202 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
15204 /* Some of these attributes only apply when the corresponding features
15205 are used. However we don't have any easy way of figuring this out.
15206 Conservatively record the setting that would have been used. */
15208 /* Tag_ABI_PCS_wchar_t. */
15209 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
15210 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
15212 /* Tag_ABI_FP_rounding. */
15213 if (flag_rounding_math)
15214 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
15215 if (!flag_unsafe_math_optimizations)
15217 /* Tag_ABI_FP_denomal. */
15218 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
15219 /* Tag_ABI_FP_exceptions. */
15220 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
15222 /* Tag_ABI_FP_user_exceptions. */
15223 if (flag_signaling_nans)
15224 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
15225 /* Tag_ABI_FP_number_model. */
15226 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
15227 flag_finite_math_only ? 1 : 3);
15229 /* Tag_ABI_align8_needed. */
15230 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
15231 /* Tag_ABI_align8_preserved. */
15232 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
15233 /* Tag_ABI_enum_size. */
15234 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
15235 flag_short_enums ? 1 : 2);
15237 /* Tag_ABI_optimization_goals. */
15240 else if (optimize >= 2)
15246 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
15248 default_file_start();
15252 arm_file_end (void)
15256 if (NEED_INDICATE_EXEC_STACK)
15257 /* Add .note.GNU-stack. */
15258 file_end_indicate_exec_stack ();
15260 if (! thumb_call_reg_needed)
15263 switch_to_section (text_section);
15264 asm_fprintf (asm_out_file, "\t.code 16\n");
15265 ASM_OUTPUT_ALIGN (asm_out_file, 1);
15267 for (regno = 0; regno < LR_REGNUM; regno++)
15269 rtx label = thumb_call_via_label[regno];
15273 targetm.asm_out.internal_label (asm_out_file, "L",
15274 CODE_LABEL_NUMBER (label));
15275 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
15282 #ifdef AOF_ASSEMBLER
15283 /* Special functions only needed when producing AOF syntax assembler. */
15287 struct pic_chain * next;
15288 const char * symname;
15291 static struct pic_chain * aof_pic_chain = NULL;
15294 aof_pic_entry (rtx x)
15296 struct pic_chain ** chainp;
15299 if (aof_pic_label == NULL_RTX)
15301 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
15304 for (offset = 0, chainp = &aof_pic_chain; *chainp;
15305 offset += 4, chainp = &(*chainp)->next)
15306 if ((*chainp)->symname == XSTR (x, 0))
15307 return plus_constant (aof_pic_label, offset);
15309 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
15310 (*chainp)->next = NULL;
15311 (*chainp)->symname = XSTR (x, 0);
15312 return plus_constant (aof_pic_label, offset);
15316 aof_dump_pic_table (FILE *f)
15318 struct pic_chain * chain;
15320 if (aof_pic_chain == NULL)
15323 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
15324 PIC_OFFSET_TABLE_REGNUM,
15325 PIC_OFFSET_TABLE_REGNUM);
15326 fputs ("|x$adcons|\n", f);
15328 for (chain = aof_pic_chain; chain; chain = chain->next)
15330 fputs ("\tDCD\t", f);
15331 assemble_name (f, chain->symname);
15336 int arm_text_section_count = 1;
15338 /* A get_unnamed_section callback for switching to the text section. */
15341 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15343 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
15344 arm_text_section_count++);
15346 fprintf (asm_out_file, ", PIC, REENTRANT");
15347 fprintf (asm_out_file, "\n");
15350 static int arm_data_section_count = 1;
15352 /* A get_unnamed_section callback for switching to the data section. */
15355 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15357 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
15358 arm_data_section_count++);
15361 /* Implement TARGET_ASM_INIT_SECTIONS.
15363 AOF Assembler syntax is a nightmare when it comes to areas, since once
15364 we change from one area to another, we can't go back again. Instead,
15365 we must create a new area with the same attributes and add the new output
15366 to that. Unfortunately, there is nothing we can do here to guarantee that
15367 two areas with the same attributes will be linked adjacently in the
15368 resulting executable, so we have to be careful not to do pc-relative
15369 addressing across such boundaries. */
15372 aof_asm_init_sections (void)
15374 text_section = get_unnamed_section (SECTION_CODE,
15375 aof_output_text_section_asm_op, NULL);
15376 data_section = get_unnamed_section (SECTION_WRITE,
15377 aof_output_data_section_asm_op, NULL);
15378 readonly_data_section = text_section;
15382 zero_init_section (void)
15384 static int zero_init_count = 1;
15386 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
15390 /* The AOF assembler is religiously strict about declarations of
15391 imported and exported symbols, so that it is impossible to declare
15392 a function as imported near the beginning of the file, and then to
15393 export it later on. It is, however, possible to delay the decision
15394 until all the functions in the file have been compiled. To get
15395 around this, we maintain a list of the imports and exports, and
15396 delete from it any that are subsequently defined. At the end of
15397 compilation we spit the remainder of the list out before the END
15402 struct import * next;
15406 static struct import * imports_list = NULL;
15409 aof_add_import (const char *name)
15411 struct import * new;
15413 for (new = imports_list; new; new = new->next)
15414 if (new->name == name)
15417 new = (struct import *) xmalloc (sizeof (struct import));
15418 new->next = imports_list;
15419 imports_list = new;
15424 aof_delete_import (const char *name)
15426 struct import ** old;
15428 for (old = &imports_list; *old; old = & (*old)->next)
15430 if ((*old)->name == name)
15432 *old = (*old)->next;
15438 int arm_main_function = 0;
15441 aof_dump_imports (FILE *f)
15443 /* The AOF assembler needs this to cause the startup code to be extracted
15444 from the library. Brining in __main causes the whole thing to work
15446 if (arm_main_function)
15448 switch_to_section (text_section);
15449 fputs ("\tIMPORT __main\n", f);
15450 fputs ("\tDCD __main\n", f);
15453 /* Now dump the remaining imports. */
15454 while (imports_list)
15456 fprintf (f, "\tIMPORT\t");
15457 assemble_name (f, imports_list->name);
15459 imports_list = imports_list->next;
15464 aof_globalize_label (FILE *stream, const char *name)
15466 default_globalize_label (stream, name);
15467 if (! strcmp (name, "main"))
15468 arm_main_function = 1;
15472 aof_file_start (void)
15474 fputs ("__r0\tRN\t0\n", asm_out_file);
15475 fputs ("__a1\tRN\t0\n", asm_out_file);
15476 fputs ("__a2\tRN\t1\n", asm_out_file);
15477 fputs ("__a3\tRN\t2\n", asm_out_file);
15478 fputs ("__a4\tRN\t3\n", asm_out_file);
15479 fputs ("__v1\tRN\t4\n", asm_out_file);
15480 fputs ("__v2\tRN\t5\n", asm_out_file);
15481 fputs ("__v3\tRN\t6\n", asm_out_file);
15482 fputs ("__v4\tRN\t7\n", asm_out_file);
15483 fputs ("__v5\tRN\t8\n", asm_out_file);
15484 fputs ("__v6\tRN\t9\n", asm_out_file);
15485 fputs ("__sl\tRN\t10\n", asm_out_file);
15486 fputs ("__fp\tRN\t11\n", asm_out_file);
15487 fputs ("__ip\tRN\t12\n", asm_out_file);
15488 fputs ("__sp\tRN\t13\n", asm_out_file);
15489 fputs ("__lr\tRN\t14\n", asm_out_file);
15490 fputs ("__pc\tRN\t15\n", asm_out_file);
15491 fputs ("__f0\tFN\t0\n", asm_out_file);
15492 fputs ("__f1\tFN\t1\n", asm_out_file);
15493 fputs ("__f2\tFN\t2\n", asm_out_file);
15494 fputs ("__f3\tFN\t3\n", asm_out_file);
15495 fputs ("__f4\tFN\t4\n", asm_out_file);
15496 fputs ("__f5\tFN\t5\n", asm_out_file);
15497 fputs ("__f6\tFN\t6\n", asm_out_file);
15498 fputs ("__f7\tFN\t7\n", asm_out_file);
15499 switch_to_section (text_section);
15503 aof_file_end (void)
15506 aof_dump_pic_table (asm_out_file);
15508 aof_dump_imports (asm_out_file);
15509 fputs ("\tEND\n", asm_out_file);
15511 #endif /* AOF_ASSEMBLER */
15514 /* Symbols in the text segment can be accessed without indirecting via the
15515 constant pool; it may take an extra binary operation, but this is still
15516 faster than indirecting via memory. Don't do this when not optimizing,
15517 since we won't be calculating al of the offsets necessary to do this
15521 arm_encode_section_info (tree decl, rtx rtl, int first)
15523 /* This doesn't work with AOF syntax, since the string table may be in
15524 a different AREA. */
15525 #ifndef AOF_ASSEMBLER
15526 if (optimize > 0 && TREE_CONSTANT (decl))
15527 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
15530 /* If we are referencing a function that is weak then encode a long call
15531 flag in the function name, otherwise if the function is static or
15532 or known to be defined in this file then encode a short call flag. */
15533 if (first && DECL_P (decl))
15535 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
15536 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
15537 else if (! TREE_PUBLIC (decl))
15538 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
15541 default_encode_section_info (decl, rtl, first);
15543 #endif /* !ARM_PE */
15546 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
15548 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
15549 && !strcmp (prefix, "L"))
15551 arm_ccfsm_state = 0;
15552 arm_target_insn = NULL;
15554 default_internal_label (stream, prefix, labelno);
15557 /* Output code to add DELTA to the first argument, and then jump
15558 to FUNCTION. Used for C++ multiple inheritance. */
15560 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
15561 HOST_WIDE_INT delta,
15562 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
15565 static int thunk_label = 0;
15568 int mi_delta = delta;
15569 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
15571 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
15574 mi_delta = - mi_delta;
15575 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15578 int labelno = thunk_label++;
15579 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
15580 fputs ("\tldr\tr12, ", file);
15581 assemble_name (file, label);
15582 fputc ('\n', file);
15585 /* If we are generating PIC, the ldr instruction below loads
15586 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15587 the address of the add + 8, so we have:
15589 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15592 Note that we have "+ 1" because some versions of GNU ld
15593 don't set the low bit of the result for R_ARM_REL32
15594 relocations against thumb function symbols. */
15595 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
15596 assemble_name (file, labelpc);
15597 fputs (":\n", file);
15598 fputs ("\tadd\tr12, pc, r12\n", file);
15601 /* TODO: Use movw/movt for large constants when available. */
15602 while (mi_delta != 0)
15604 if ((mi_delta & (3 << shift)) == 0)
15608 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
15609 mi_op, this_regno, this_regno,
15610 mi_delta & (0xff << shift));
15611 mi_delta &= ~(0xff << shift);
15617 fprintf (file, "\tbx\tr12\n");
15618 ASM_OUTPUT_ALIGN (file, 2);
15619 assemble_name (file, label);
15620 fputs (":\n", file);
15623 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15624 rtx tem = XEXP (DECL_RTL (function), 0);
15625 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
15626 tem = gen_rtx_MINUS (GET_MODE (tem),
15628 gen_rtx_SYMBOL_REF (Pmode,
15629 ggc_strdup (labelpc)));
15630 assemble_integer (tem, 4, BITS_PER_WORD, 1);
15633 /* Output ".word .LTHUNKn". */
15634 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
15638 fputs ("\tb\t", file);
15639 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
15640 if (NEED_PLT_RELOC)
15641 fputs ("(PLT)", file);
15642 fputc ('\n', file);
15647 arm_emit_vector_const (FILE *file, rtx x)
15650 const char * pattern;
15652 gcc_assert (GET_CODE (x) == CONST_VECTOR);
15654 switch (GET_MODE (x))
15656 case V2SImode: pattern = "%08x"; break;
15657 case V4HImode: pattern = "%04x"; break;
15658 case V8QImode: pattern = "%02x"; break;
15659 default: gcc_unreachable ();
15662 fprintf (file, "0x");
15663 for (i = CONST_VECTOR_NUNITS (x); i--;)
15667 element = CONST_VECTOR_ELT (x, i);
15668 fprintf (file, pattern, INTVAL (element));
15675 arm_output_load_gr (rtx *operands)
15682 if (GET_CODE (operands [1]) != MEM
15683 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
15684 || GET_CODE (reg = XEXP (sum, 0)) != REG
15685 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
15686 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
15687 return "wldrw%?\t%0, %1";
15689 /* Fix up an out-of-range load of a GR register. */
15690 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
15691 wcgr = operands[0];
15693 output_asm_insn ("ldr%?\t%0, %1", operands);
15695 operands[0] = wcgr;
15697 output_asm_insn ("tmcr%?\t%0, %1", operands);
15698 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
15703 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
15705 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
15706 named arg and all anonymous args onto the stack.
15707 XXX I know the prologue shouldn't be pushing registers, but it is faster
15711 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
15712 enum machine_mode mode ATTRIBUTE_UNUSED,
15713 tree type ATTRIBUTE_UNUSED,
15715 int second_time ATTRIBUTE_UNUSED)
15717 cfun->machine->uses_anonymous_args = 1;
15718 if (cum->nregs < NUM_ARG_REGS)
15719 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
15722 /* Return nonzero if the CONSUMER instruction (a store) does not need
15723 PRODUCER's value to calculate the address. */
15726 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
15728 rtx value = PATTERN (producer);
15729 rtx addr = PATTERN (consumer);
15731 if (GET_CODE (value) == COND_EXEC)
15732 value = COND_EXEC_CODE (value);
15733 if (GET_CODE (value) == PARALLEL)
15734 value = XVECEXP (value, 0, 0);
15735 value = XEXP (value, 0);
15736 if (GET_CODE (addr) == COND_EXEC)
15737 addr = COND_EXEC_CODE (addr);
15738 if (GET_CODE (addr) == PARALLEL)
15739 addr = XVECEXP (addr, 0, 0);
15740 addr = XEXP (addr, 0);
15742 return !reg_overlap_mentioned_p (value, addr);
15745 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15746 have an early register shift value or amount dependency on the
15747 result of PRODUCER. */
15750 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
15752 rtx value = PATTERN (producer);
15753 rtx op = PATTERN (consumer);
15756 if (GET_CODE (value) == COND_EXEC)
15757 value = COND_EXEC_CODE (value);
15758 if (GET_CODE (value) == PARALLEL)
15759 value = XVECEXP (value, 0, 0);
15760 value = XEXP (value, 0);
15761 if (GET_CODE (op) == COND_EXEC)
15762 op = COND_EXEC_CODE (op);
15763 if (GET_CODE (op) == PARALLEL)
15764 op = XVECEXP (op, 0, 0);
15767 early_op = XEXP (op, 0);
15768 /* This is either an actual independent shift, or a shift applied to
15769 the first operand of another operation. We want the whole shift
15771 if (GET_CODE (early_op) == REG)
15774 return !reg_overlap_mentioned_p (value, early_op);
15777 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15778 have an early register shift value dependency on the result of
15782 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
15784 rtx value = PATTERN (producer);
15785 rtx op = PATTERN (consumer);
15788 if (GET_CODE (value) == COND_EXEC)
15789 value = COND_EXEC_CODE (value);
15790 if (GET_CODE (value) == PARALLEL)
15791 value = XVECEXP (value, 0, 0);
15792 value = XEXP (value, 0);
15793 if (GET_CODE (op) == COND_EXEC)
15794 op = COND_EXEC_CODE (op);
15795 if (GET_CODE (op) == PARALLEL)
15796 op = XVECEXP (op, 0, 0);
15799 early_op = XEXP (op, 0);
15801 /* This is either an actual independent shift, or a shift applied to
15802 the first operand of another operation. We want the value being
15803 shifted, in either case. */
15804 if (GET_CODE (early_op) != REG)
15805 early_op = XEXP (early_op, 0);
15807 return !reg_overlap_mentioned_p (value, early_op);
15810 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15811 have an early register mult dependency on the result of
15815 arm_no_early_mul_dep (rtx producer, rtx consumer)
15817 rtx value = PATTERN (producer);
15818 rtx op = PATTERN (consumer);
15820 if (GET_CODE (value) == COND_EXEC)
15821 value = COND_EXEC_CODE (value);
15822 if (GET_CODE (value) == PARALLEL)
15823 value = XVECEXP (value, 0, 0);
15824 value = XEXP (value, 0);
15825 if (GET_CODE (op) == COND_EXEC)
15826 op = COND_EXEC_CODE (op);
15827 if (GET_CODE (op) == PARALLEL)
15828 op = XVECEXP (op, 0, 0);
15831 return (GET_CODE (op) == PLUS
15832 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
15836 /* We can't rely on the caller doing the proper promotion when
15837 using APCS or ATPCS. */
15840 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
15842 return !TARGET_AAPCS_BASED;
15846 /* AAPCS based ABIs use short enums by default. */
15849 arm_default_short_enums (void)
15851 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
15855 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15858 arm_align_anon_bitfield (void)
15860 return TARGET_AAPCS_BASED;
15864 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15867 arm_cxx_guard_type (void)
15869 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
15873 /* The EABI says test the least significant bit of a guard variable. */
15876 arm_cxx_guard_mask_bit (void)
15878 return TARGET_AAPCS_BASED;
15882 /* The EABI specifies that all array cookies are 8 bytes long. */
15885 arm_get_cookie_size (tree type)
15889 if (!TARGET_AAPCS_BASED)
15890 return default_cxx_get_cookie_size (type);
15892 size = build_int_cst (sizetype, 8);
15897 /* The EABI says that array cookies should also contain the element size. */
15900 arm_cookie_has_size (void)
15902 return TARGET_AAPCS_BASED;
15906 /* The EABI says constructors and destructors should return a pointer to
15907 the object constructed/destroyed. */
15910 arm_cxx_cdtor_returns_this (void)
15912 return TARGET_AAPCS_BASED;
15915 /* The EABI says that an inline function may never be the key
15919 arm_cxx_key_method_may_be_inline (void)
15921 return !TARGET_AAPCS_BASED;
15925 arm_cxx_determine_class_data_visibility (tree decl)
15927 if (!TARGET_AAPCS_BASED)
15930 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15931 is exported. However, on systems without dynamic vague linkage,
15932 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15933 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
15934 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
15936 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
15937 DECL_VISIBILITY_SPECIFIED (decl) = 1;
15941 arm_cxx_class_data_always_comdat (void)
15943 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15944 vague linkage if the class has no key function. */
15945 return !TARGET_AAPCS_BASED;
15949 /* The EABI says __aeabi_atexit should be used to register static
15953 arm_cxx_use_aeabi_atexit (void)
15955 return TARGET_AAPCS_BASED;
15960 arm_set_return_address (rtx source, rtx scratch)
15962 arm_stack_offsets *offsets;
15963 HOST_WIDE_INT delta;
15965 unsigned long saved_regs;
15967 saved_regs = arm_compute_save_reg_mask ();
15969 if ((saved_regs & (1 << LR_REGNUM)) == 0)
15970 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15973 if (frame_pointer_needed)
15974 addr = plus_constant(hard_frame_pointer_rtx, -4);
15977 /* LR will be the first saved register. */
15978 offsets = arm_get_frame_offsets ();
15979 delta = offsets->outgoing_args - (offsets->frame + 4);
15984 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
15985 GEN_INT (delta & ~4095)));
15990 addr = stack_pointer_rtx;
15992 addr = plus_constant (addr, delta);
15994 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16000 thumb_set_return_address (rtx source, rtx scratch)
16002 arm_stack_offsets *offsets;
16003 HOST_WIDE_INT delta;
16004 HOST_WIDE_INT limit;
16007 unsigned long mask;
16009 emit_insn (gen_rtx_USE (VOIDmode, source));
16011 mask = thumb1_compute_save_reg_mask ();
16012 if (mask & (1 << LR_REGNUM))
16014 offsets = arm_get_frame_offsets ();
16017 /* Find the saved regs. */
16018 if (frame_pointer_needed)
16020 delta = offsets->soft_frame - offsets->saved_args;
16021 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
16027 delta = offsets->outgoing_args - offsets->saved_args;
16030 /* Allow for the stack frame. */
16031 if (TARGET_THUMB1 && TARGET_BACKTRACE)
16033 /* The link register is always the first saved register. */
16036 /* Construct the address. */
16037 addr = gen_rtx_REG (SImode, reg);
16040 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
16041 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
16045 addr = plus_constant (addr, delta);
16047 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16050 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16053 /* Implements target hook vector_mode_supported_p. */
16055 arm_vector_mode_supported_p (enum machine_mode mode)
16057 if ((mode == V2SImode)
16058 || (mode == V4HImode)
16059 || (mode == V8QImode))
16065 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16066 ARM insns and therefore guarantee that the shift count is modulo 256.
16067 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16068 guarantee no particular behavior for out-of-range counts. */
16070 static unsigned HOST_WIDE_INT
16071 arm_shift_truncation_mask (enum machine_mode mode)
16073 return mode == SImode ? 255 : 0;
16077 /* Map internal gcc register numbers to DWARF2 register numbers. */
16080 arm_dbx_register_number (unsigned int regno)
16085 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16086 compatibility. The EABI defines them as registers 96-103. */
16087 if (IS_FPA_REGNUM (regno))
16088 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
16090 if (IS_VFP_REGNUM (regno))
16091 return 64 + regno - FIRST_VFP_REGNUM;
16093 if (IS_IWMMXT_GR_REGNUM (regno))
16094 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
16096 if (IS_IWMMXT_REGNUM (regno))
16097 return 112 + regno - FIRST_IWMMXT_REGNUM;
16099 gcc_unreachable ();
16103 #ifdef TARGET_UNWIND_INFO
16104 /* Emit unwind directives for a store-multiple instruction or stack pointer
16105 push during alignment.
16106 These should only ever be generated by the function prologue code, so
16107 expect them to have a particular form. */
16110 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
16113 HOST_WIDE_INT offset;
16114 HOST_WIDE_INT nregs;
16120 e = XVECEXP (p, 0, 0);
16121 if (GET_CODE (e) != SET)
16124 /* First insn will adjust the stack pointer. */
16125 if (GET_CODE (e) != SET
16126 || GET_CODE (XEXP (e, 0)) != REG
16127 || REGNO (XEXP (e, 0)) != SP_REGNUM
16128 || GET_CODE (XEXP (e, 1)) != PLUS)
16131 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
16132 nregs = XVECLEN (p, 0) - 1;
16134 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
16137 /* The function prologue may also push pc, but not annotate it as it is
16138 never restored. We turn this into a stack pointer adjustment. */
16139 if (nregs * 4 == offset - 4)
16141 fprintf (asm_out_file, "\t.pad #4\n");
16145 fprintf (asm_out_file, "\t.save {");
16147 else if (IS_VFP_REGNUM (reg))
16150 fprintf (asm_out_file, "\t.vsave {");
16152 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
16154 /* FPA registers are done differently. */
16155 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
16159 /* Unknown register type. */
16162 /* If the stack increment doesn't match the size of the saved registers,
16163 something has gone horribly wrong. */
16164 if (offset != nregs * reg_size)
16169 /* The remaining insns will describe the stores. */
16170 for (i = 1; i <= nregs; i++)
16172 /* Expect (set (mem <addr>) (reg)).
16173 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16174 e = XVECEXP (p, 0, i);
16175 if (GET_CODE (e) != SET
16176 || GET_CODE (XEXP (e, 0)) != MEM
16177 || GET_CODE (XEXP (e, 1)) != REG)
16180 reg = REGNO (XEXP (e, 1));
16185 fprintf (asm_out_file, ", ");
16186 /* We can't use %r for vfp because we need to use the
16187 double precision register names. */
16188 if (IS_VFP_REGNUM (reg))
16189 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
16191 asm_fprintf (asm_out_file, "%r", reg);
16193 #ifdef ENABLE_CHECKING
16194 /* Check that the addresses are consecutive. */
16195 e = XEXP (XEXP (e, 0), 0);
16196 if (GET_CODE (e) == PLUS)
16198 offset += reg_size;
16199 if (GET_CODE (XEXP (e, 0)) != REG
16200 || REGNO (XEXP (e, 0)) != SP_REGNUM
16201 || GET_CODE (XEXP (e, 1)) != CONST_INT
16202 || offset != INTVAL (XEXP (e, 1)))
16206 || GET_CODE (e) != REG
16207 || REGNO (e) != SP_REGNUM)
16211 fprintf (asm_out_file, "}\n");
16214 /* Emit unwind directives for a SET. */
16217 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
16225 switch (GET_CODE (e0))
16228 /* Pushing a single register. */
16229 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
16230 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
16231 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
16234 asm_fprintf (asm_out_file, "\t.save ");
16235 if (IS_VFP_REGNUM (REGNO (e1)))
16236 asm_fprintf(asm_out_file, "{d%d}\n",
16237 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
16239 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
16243 if (REGNO (e0) == SP_REGNUM)
16245 /* A stack increment. */
16246 if (GET_CODE (e1) != PLUS
16247 || GET_CODE (XEXP (e1, 0)) != REG
16248 || REGNO (XEXP (e1, 0)) != SP_REGNUM
16249 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16252 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
16253 -INTVAL (XEXP (e1, 1)));
16255 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
16257 HOST_WIDE_INT offset;
16259 if (GET_CODE (e1) == PLUS)
16261 if (GET_CODE (XEXP (e1, 0)) != REG
16262 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16264 reg = REGNO (XEXP (e1, 0));
16265 offset = INTVAL (XEXP (e1, 1));
16266 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
16267 HARD_FRAME_POINTER_REGNUM, reg,
16268 INTVAL (XEXP (e1, 1)));
16270 else if (GET_CODE (e1) == REG)
16273 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
16274 HARD_FRAME_POINTER_REGNUM, reg);
16279 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
16281 /* Move from sp to reg. */
16282 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
16284 else if (GET_CODE (e1) == PLUS
16285 && GET_CODE (XEXP (e1, 0)) == REG
16286 && REGNO (XEXP (e1, 0)) == SP_REGNUM
16287 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
16289 /* Set reg to offset from sp. */
16290 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
16291 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
16293 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
16295 /* Stack pointer save before alignment. */
16297 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16310 /* Emit unwind directives for the given insn. */
16313 arm_unwind_emit (FILE * asm_out_file, rtx insn)
16317 if (!ARM_EABI_UNWIND_TABLES)
16320 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
16323 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
16325 pat = XEXP (pat, 0);
16327 pat = PATTERN (insn);
16329 switch (GET_CODE (pat))
16332 arm_unwind_emit_set (asm_out_file, pat);
16336 /* Store multiple. */
16337 arm_unwind_emit_sequence (asm_out_file, pat);
16346 /* Output a reference from a function exception table to the type_info
16347 object X. The EABI specifies that the symbol should be relocated by
16348 an R_ARM_TARGET2 relocation. */
16351 arm_output_ttype (rtx x)
16353 fputs ("\t.word\t", asm_out_file);
16354 output_addr_const (asm_out_file, x);
16355 /* Use special relocations for symbol references. */
16356 if (GET_CODE (x) != CONST_INT)
16357 fputs ("(TARGET2)", asm_out_file);
16358 fputc ('\n', asm_out_file);
16362 #endif /* TARGET_UNWIND_INFO */
16365 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16366 stack alignment. */
16369 arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
16371 rtx unspec = SET_SRC (pattern);
16372 gcc_assert (GET_CODE (unspec) == UNSPEC);
16376 case UNSPEC_STACK_ALIGN:
16377 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16378 put anything on the stack, so hopefully it won't matter.
16379 CFA = SP will be correct after alignment. */
16380 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
16381 SET_DEST (pattern));
16384 gcc_unreachable ();
16389 /* Output unwind directives for the start/end of a function. */
16392 arm_output_fn_unwind (FILE * f, bool prologue)
16394 if (!ARM_EABI_UNWIND_TABLES)
16398 fputs ("\t.fnstart\n", f);
16400 fputs ("\t.fnend\n", f);
16404 arm_emit_tls_decoration (FILE *fp, rtx x)
16406 enum tls_reloc reloc;
16409 val = XVECEXP (x, 0, 0);
16410 reloc = INTVAL (XVECEXP (x, 0, 1));
16412 output_addr_const (fp, val);
16417 fputs ("(tlsgd)", fp);
16420 fputs ("(tlsldm)", fp);
16423 fputs ("(tlsldo)", fp);
16426 fputs ("(gottpoff)", fp);
16429 fputs ("(tpoff)", fp);
16432 gcc_unreachable ();
16440 fputs (" + (. - ", fp);
16441 output_addr_const (fp, XVECEXP (x, 0, 2));
16443 output_addr_const (fp, XVECEXP (x, 0, 3));
16454 arm_output_addr_const_extra (FILE *fp, rtx x)
16456 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
16457 return arm_emit_tls_decoration (fp, x);
16458 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
16461 int labelno = INTVAL (XVECEXP (x, 0, 0));
16463 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
16464 assemble_name_raw (fp, label);
16468 else if (GET_CODE (x) == CONST_VECTOR)
16469 return arm_emit_vector_const (fp, x);
16474 /* Output assembly for a shift instruction.
16475 SET_FLAGS determines how the instruction modifies the condition codes.
16476 0 - Do not set conditiona codes.
16477 1 - Set condition codes.
16478 2 - Use smallest instruction. */
16480 arm_output_shift(rtx * operands, int set_flags)
16483 static const char flag_chars[3] = {'?', '.', '!'};
16488 c = flag_chars[set_flags];
16489 if (TARGET_UNIFIED_ASM)
16491 shift = shift_op(operands[3], &val);
16495 operands[2] = GEN_INT(val);
16496 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
16499 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
16502 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
16503 output_asm_insn (pattern, operands);
16507 /* Output a Thumb-2 casesi instruction. */
16509 thumb2_output_casesi (rtx *operands)
16511 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
16513 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
16515 output_asm_insn ("cmp\t%0, %1", operands);
16516 output_asm_insn ("bhi\t%l3", operands);
16517 switch (GET_MODE(diff_vec))
16520 return "tbb\t[%|pc, %0]";
16522 return "tbh\t[%|pc, %0, lsl #1]";
16526 output_asm_insn ("adr\t%4, %l2", operands);
16527 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
16528 output_asm_insn ("add\t%4, %4, %5", operands);
16533 output_asm_insn ("adr\t%4, %l2", operands);
16534 return "ldr\t%|pc, [%4, %0, lsl #2]";
16537 gcc_unreachable ();
16541 #include "gt-arm.h"